254 lines
9.7 KiB
LLVM
254 lines
9.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=SSE
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=AVX
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;
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; NOTE: this is generated by utils/update_llc_test_checks.py but we can't check NAN types (PR30443),
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; so we need to edit it to remove the NAN constant comments
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;
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; copysign(x, c1) -> fabs(x) iff ispos(c1)
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define <4 x float> @combine_vec_fcopysign_pos_constant0(<4 x float> %x) {
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; SSE-LABEL: combine_vec_fcopysign_pos_constant0:
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; SSE: # %bb.0:
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; SSE-NEXT: andps {{.*}}(%rip), %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_vec_fcopysign_pos_constant0:
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; AVX: # %bb.0:
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; AVX-NEXT: vbroadcastss {{.*#+}} xmm1 = [NaN,NaN,NaN,NaN]
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; AVX-NEXT: vandps %xmm1, %xmm0, %xmm0
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; AVX-NEXT: retq
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%1 = call <4 x float> @llvm.copysign.v4f32(<4 x float> %x, <4 x float> <float 2.0, float 2.0, float 2.0, float 2.0>)
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ret <4 x float> %1
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}
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define <4 x float> @combine_vec_fcopysign_pos_constant1(<4 x float> %x) {
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; SSE-LABEL: combine_vec_fcopysign_pos_constant1:
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; SSE: # %bb.0:
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; SSE-NEXT: andps {{.*}}(%rip), %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_vec_fcopysign_pos_constant1:
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; AVX: # %bb.0:
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; AVX-NEXT: vbroadcastss {{.*#+}} xmm1 = [NaN,NaN,NaN,NaN]
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; AVX-NEXT: vandps %xmm1, %xmm0, %xmm0
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; AVX-NEXT: retq
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%1 = call <4 x float> @llvm.copysign.v4f32(<4 x float> %x, <4 x float> <float 0.0, float 2.0, float 4.0, float 8.0>)
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ret <4 x float> %1
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}
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define <4 x float> @combine_vec_fcopysign_fabs_sgn(<4 x float> %x, <4 x float> %y) {
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; SSE-LABEL: combine_vec_fcopysign_fabs_sgn:
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; SSE: # %bb.0:
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; SSE-NEXT: andps {{.*}}(%rip), %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_vec_fcopysign_fabs_sgn:
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; AVX: # %bb.0:
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; AVX-NEXT: vbroadcastss {{.*#+}} xmm1 = [NaN,NaN,NaN,NaN]
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; AVX-NEXT: vandps %xmm1, %xmm0, %xmm0
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; AVX-NEXT: retq
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%1 = call <4 x float> @llvm.fabs.v4f32(<4 x float> %y)
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%2 = call <4 x float> @llvm.copysign.v4f32(<4 x float> %x, <4 x float> %1)
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ret <4 x float> %2
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}
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; copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1)
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define <4 x float> @combine_vec_fcopysign_neg_constant0(<4 x float> %x) {
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; SSE-LABEL: combine_vec_fcopysign_neg_constant0:
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; SSE: # %bb.0:
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; SSE-NEXT: orps {{.*}}(%rip), %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_vec_fcopysign_neg_constant0:
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; AVX: # %bb.0:
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; AVX-NEXT: vbroadcastss {{.*#+}} xmm1 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0]
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; AVX-NEXT: vorps %xmm1, %xmm0, %xmm0
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; AVX-NEXT: retq
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%1 = call <4 x float> @llvm.copysign.v4f32(<4 x float> %x, <4 x float> <float -2.0, float -2.0, float -2.0, float -2.0>)
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ret <4 x float> %1
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}
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define <4 x float> @combine_vec_fcopysign_neg_constant1(<4 x float> %x) {
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; SSE-LABEL: combine_vec_fcopysign_neg_constant1:
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; SSE: # %bb.0:
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; SSE-NEXT: orps {{.*}}(%rip), %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_vec_fcopysign_neg_constant1:
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; AVX: # %bb.0:
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; AVX-NEXT: vbroadcastss {{.*#+}} xmm1 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0]
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; AVX-NEXT: vorps %xmm1, %xmm0, %xmm0
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; AVX-NEXT: retq
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%1 = call <4 x float> @llvm.copysign.v4f32(<4 x float> %x, <4 x float> <float -0.0, float -2.0, float -4.0, float -8.0>)
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ret <4 x float> %1
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}
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define <4 x float> @combine_vec_fcopysign_fneg_fabs_sgn(<4 x float> %x, <4 x float> %y) {
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; SSE-LABEL: combine_vec_fcopysign_fneg_fabs_sgn:
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; SSE: # %bb.0:
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; SSE-NEXT: orps {{.*}}(%rip), %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_vec_fcopysign_fneg_fabs_sgn:
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; AVX: # %bb.0:
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; AVX-NEXT: vbroadcastss {{.*#+}} xmm1 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0]
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; AVX-NEXT: vorps %xmm1, %xmm0, %xmm0
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; AVX-NEXT: retq
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%1 = call <4 x float> @llvm.fabs.v4f32(<4 x float> %y)
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%2 = fsub <4 x float> <float -0.0, float -0.0, float -0.0, float -0.0>, %1
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%3 = call <4 x float> @llvm.copysign.v4f32(<4 x float> %x, <4 x float> %2)
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ret <4 x float> %3
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}
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; copysign(fabs(x), y) -> copysign(x, y)
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define <4 x float> @combine_vec_fcopysign_fabs_mag(<4 x float> %x, <4 x float> %y) {
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; SSE-LABEL: combine_vec_fcopysign_fabs_mag:
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; SSE: # %bb.0:
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; SSE-NEXT: andps {{.*}}(%rip), %xmm1
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; SSE-NEXT: andps {{.*}}(%rip), %xmm0
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; SSE-NEXT: orps %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_vec_fcopysign_fabs_mag:
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; AVX: # %bb.0:
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; AVX-NEXT: vbroadcastss {{.*#+}} xmm2 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0]
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; AVX-NEXT: vandps %xmm2, %xmm1, %xmm1
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; AVX-NEXT: vbroadcastss {{.*#+}} xmm2 = [NaN,NaN,NaN,NaN]
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; AVX-NEXT: vandps %xmm2, %xmm0, %xmm0
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; AVX-NEXT: vorps %xmm1, %xmm0, %xmm0
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; AVX-NEXT: retq
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%1 = call <4 x float> @llvm.fabs.v4f32(<4 x float> %x)
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%2 = call <4 x float> @llvm.copysign.v4f32(<4 x float> %1, <4 x float> %y)
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ret <4 x float> %2
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}
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; copysign(fneg(x), y) -> copysign(x, y)
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define <4 x float> @combine_vec_fcopysign_fneg_mag(<4 x float> %x, <4 x float> %y) {
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; SSE-LABEL: combine_vec_fcopysign_fneg_mag:
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; SSE: # %bb.0:
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; SSE-NEXT: andps {{.*}}(%rip), %xmm1
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; SSE-NEXT: andps {{.*}}(%rip), %xmm0
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; SSE-NEXT: orps %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_vec_fcopysign_fneg_mag:
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; AVX: # %bb.0:
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; AVX-NEXT: vbroadcastss {{.*#+}} xmm2 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0]
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; AVX-NEXT: vandps %xmm2, %xmm1, %xmm1
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; AVX-NEXT: vbroadcastss {{.*#+}} xmm2 = [NaN,NaN,NaN,NaN]
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; AVX-NEXT: vandps %xmm2, %xmm0, %xmm0
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; AVX-NEXT: vorps %xmm1, %xmm0, %xmm0
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; AVX-NEXT: retq
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%1 = fsub <4 x float> <float -0.0, float -0.0, float -0.0, float -0.0>, %x
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%2 = call <4 x float> @llvm.copysign.v4f32(<4 x float> %1, <4 x float> %y)
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ret <4 x float> %2
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}
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; copysign(copysign(x,z), y) -> copysign(x, y)
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define <4 x float> @combine_vec_fcopysign_fcopysign_mag(<4 x float> %x, <4 x float> %y, <4 x float> %z) {
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; SSE-LABEL: combine_vec_fcopysign_fcopysign_mag:
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; SSE: # %bb.0:
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; SSE-NEXT: andps {{.*}}(%rip), %xmm1
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; SSE-NEXT: andps {{.*}}(%rip), %xmm0
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; SSE-NEXT: orps %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_vec_fcopysign_fcopysign_mag:
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; AVX: # %bb.0:
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; AVX-NEXT: vbroadcastss {{.*#+}} xmm2 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0]
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; AVX-NEXT: vandps %xmm2, %xmm1, %xmm1
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; AVX-NEXT: vbroadcastss {{.*#+}} xmm2 = [NaN,NaN,NaN,NaN]
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; AVX-NEXT: vandps %xmm2, %xmm0, %xmm0
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; AVX-NEXT: vorps %xmm1, %xmm0, %xmm0
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; AVX-NEXT: retq
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%1 = call <4 x float> @llvm.copysign.v4f32(<4 x float> %x, <4 x float> %z)
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%2 = call <4 x float> @llvm.copysign.v4f32(<4 x float> %1, <4 x float> %y)
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ret <4 x float> %2
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}
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; copysign(x, copysign(y,z)) -> copysign(x, z)
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define <4 x float> @combine_vec_fcopysign_fcopysign_sgn(<4 x float> %x, <4 x float> %y, <4 x float> %z) {
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; SSE-LABEL: combine_vec_fcopysign_fcopysign_sgn:
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; SSE: # %bb.0:
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; SSE-NEXT: andps {{.*}}(%rip), %xmm2
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; SSE-NEXT: andps {{.*}}(%rip), %xmm0
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; SSE-NEXT: orps %xmm2, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_vec_fcopysign_fcopysign_sgn:
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; AVX: # %bb.0:
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; AVX-NEXT: vbroadcastss {{.*#+}} xmm1 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0]
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; AVX-NEXT: vandps %xmm1, %xmm2, %xmm1
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; AVX-NEXT: vbroadcastss {{.*#+}} xmm2 = [NaN,NaN,NaN,NaN]
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; AVX-NEXT: vandps %xmm2, %xmm0, %xmm0
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; AVX-NEXT: vorps %xmm1, %xmm0, %xmm0
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; AVX-NEXT: retq
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%1 = call <4 x float> @llvm.copysign.v4f32(<4 x float> %y, <4 x float> %z)
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%2 = call <4 x float> @llvm.copysign.v4f32(<4 x float> %x, <4 x float> %1)
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ret <4 x float> %2
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}
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; copysign(x, fp_extend(y)) -> copysign(x, y)
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define <4 x double> @combine_vec_fcopysign_fpext_sgn(<4 x double> %x, <4 x float> %y) {
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; SSE-LABEL: combine_vec_fcopysign_fpext_sgn:
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; SSE: # %bb.0:
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; SSE-NEXT: cvtps2pd %xmm2, %xmm3
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; SSE-NEXT: movhlps {{.*#+}} xmm2 = xmm2[1,1]
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; SSE-NEXT: cvtps2pd %xmm2, %xmm2
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; SSE-NEXT: movaps {{.*#+}} xmm4 = [NaN,NaN]
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; SSE-NEXT: andps %xmm4, %xmm0
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; SSE-NEXT: movaps %xmm4, %xmm5
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; SSE-NEXT: andnps %xmm3, %xmm5
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; SSE-NEXT: orps %xmm5, %xmm0
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; SSE-NEXT: andps %xmm4, %xmm1
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; SSE-NEXT: andnps %xmm2, %xmm4
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; SSE-NEXT: orps %xmm4, %xmm1
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_vec_fcopysign_fpext_sgn:
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; AVX: # %bb.0:
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; AVX-NEXT: vcvtps2pd %xmm1, %ymm1
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; AVX-NEXT: vbroadcastsd {{.*#+}} ymm2 = [NaN,NaN,NaN,NaN]
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; AVX-NEXT: vandps %ymm2, %ymm0, %ymm0
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; AVX-NEXT: vbroadcastsd {{.*#+}} ymm2 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0]
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; AVX-NEXT: vandps %ymm2, %ymm1, %ymm1
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; AVX-NEXT: vorps %ymm1, %ymm0, %ymm0
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; AVX-NEXT: retq
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%1 = fpext <4 x float> %y to <4 x double>
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%2 = call <4 x double> @llvm.copysign.v4f64(<4 x double> %x, <4 x double> %1)
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ret <4 x double> %2
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}
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; copysign(x, fp_round(y)) -> copysign(x, y)
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define <4 x float> @combine_vec_fcopysign_fptrunc_sgn(<4 x float> %x, <4 x double> %y) {
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; SSE-LABEL: combine_vec_fcopysign_fptrunc_sgn:
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; SSE: # %bb.0:
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; SSE-NEXT: cvtpd2ps %xmm2, %xmm2
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; SSE-NEXT: cvtpd2ps %xmm1, %xmm1
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; SSE-NEXT: unpcklpd {{.*#+}} xmm1 = xmm1[0],xmm2[0]
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; SSE-NEXT: andpd {{.*}}(%rip), %xmm1
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; SSE-NEXT: andpd {{.*}}(%rip), %xmm0
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; SSE-NEXT: orpd %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_vec_fcopysign_fptrunc_sgn:
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; AVX: # %bb.0:
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; AVX-NEXT: vcvtpd2ps %ymm1, %xmm1
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; AVX-NEXT: vbroadcastss {{.*#+}} xmm2 = [NaN,NaN,NaN,NaN]
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; AVX-NEXT: vandpd %xmm2, %xmm0, %xmm0
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; AVX-NEXT: vbroadcastss {{.*#+}} xmm2 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0]
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; AVX-NEXT: vandpd %xmm2, %xmm1, %xmm1
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; AVX-NEXT: vorpd %xmm1, %xmm0, %xmm0
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; AVX-NEXT: vzeroupper
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; AVX-NEXT: retq
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%1 = fptrunc <4 x double> %y to <4 x float>
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%2 = call <4 x float> @llvm.copysign.v4f32(<4 x float> %x, <4 x float> %1)
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ret <4 x float> %2
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}
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declare <4 x float> @llvm.fabs.v4f32(<4 x float> %p)
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declare <4 x float> @llvm.copysign.v4f32(<4 x float> %Mag, <4 x float> %Sgn)
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declare <4 x double> @llvm.copysign.v4f64(<4 x double> %Mag, <4 x double> %Sgn)
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