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llvm-project/llvm/test/CodeGen/Thumb2/LowOverheadLoops
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David Green 9cb8f4d1ad [ARM] Add a tail-predication loop predicate register 
The semantics of tail predication loops means that the value of LR as an
instruction is executed determines the predicate. In other words:

mov r3, #3
DLSTP lr, r3        // Start tail predication, lr==3
VADD.s32 q0, q1, q2 // Lanes 0,1 and 2 are updated in q0.
mov lr, #1
VADD.s32 q0, q1, q2 // Only first lane is updated.

This means that the value of lr cannot be spilled and re-used in tail
predication regions without potentially altering the behaviour of the
program. More lanes than required could be stored, for example, and in
the case of a gather those lanes might not have been setup, leading to
alignment exceptions.

This patch adds a new lr predicate operand to MVE instructions in order
to keep a reference to the lr that they use as a tail predicate. It will
usually hold the zeroreg meaning not predicated, being set to the LR phi
value in the MVETPAndVPTOptimisationsPass. This will prevent it from
being spilled anywhere that it needs to be used.

A lot of tests needed updating.

Differential Revision: https://reviews.llvm.org/D107638
 		2021-09-02 13:42:58 +01:00
..
add_reduce.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
begin-vpt-without-inst.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
biquad-cascade-default.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
biquad-cascade-optsize-strd-lr.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
biquad-cascade-optsize.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
branch-targets.ll [ARM] Improve WLS lowering 2021-03-11 17:56:19 +00:00
clear-maskedinsts.ll
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cmplx_cong.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
cond-mov.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
cond-vector-reduce-mve-codegen.ll [ARM] Clean up some tests, removing dead instructions. NFC 2021-05-22 13:38:00 +01:00
constbound.ll [ARM] Remove DLS lr, lr 2021-02-02 11:09:31 +00:00
count_dominates_start.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
ctlz-non-zeros.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
disjoint-vcmp.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
dont-ignore-vctp.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
dont-remove-loop-update.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
emptyblock.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
end-positive-offset.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
exitcount.ll [ARM] Remove dead mov's in preheader of tail predicated loops 2021-02-11 10:48:20 +00:00
extending-loads.ll [ARM] Clean up some tests, removing dead instructions. NFC 2021-05-22 13:38:00 +01:00
extract-element.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
fast-fp-loops.ll [ARM] Enable subreg liveness 2021-08-17 14:10:33 +01:00
incorrect-sub-8.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
incorrect-sub-16.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
incorrect-sub-32.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
inlineasm.ll
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inloop-vpnot-1.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
inloop-vpnot-2.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
inloop-vpnot-3.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
inloop-vpsel-1.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
inloop-vpsel-2.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
invariant-qreg.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
it-block-chain-store.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
it-block-chain.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
it-block-itercount.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
it-block-mov.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
it-block-random.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
iv-two-vcmp-reordered.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
iv-two-vcmp.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
iv-vcmp.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
livereg-no-loop-def.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
loop-dec-copy-chain.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
loop-dec-copy-prev-iteration.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
loop-dec-liveout.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
loop-guards.ll [ARM] Move t2DoLoopStart reg alloc hint 2021-03-11 17:56:19 +00:00
lsr-profitable-chain.ll [ARM] Enable subreg liveness 2021-08-17 14:10:33 +01:00
lstp-insertion-position.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
massive.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
matrix-debug.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
matrix.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
memcall.ll [ARM] Introduce t2WhileLoopStartTP 2021-06-13 13:55:34 +01:00
minloop.ll [ARM] Remove DLS lr, lr 2021-02-02 11:09:31 +00:00
mov-after-dls.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
mov-after-dlstp.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
mov-lr-terminator.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
mov-operand.ll [ARM] Enable subreg liveness 2021-08-17 14:10:33 +01:00
move-def-before-start.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
move-start-after-def.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
multi-block-cond-iter-count.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
multi-cond-iter-count.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
multiblock-massive.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
multiple-do-loops.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
mve-float-loops.ll [ARM] Enable subreg liveness 2021-08-17 14:10:33 +01:00
mve-tail-data-types.ll [ARM] Clean up some tests, removing dead instructions. NFC 2021-05-22 13:38:00 +01:00
nested.ll [ARM] Clean up some tests, removing dead instructions. NFC 2021-05-22 13:38:00 +01:00
no-dec-cbnz.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
no-dec-le-simple.ll
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no-dec-reorder.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
no-dec.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
no-vpsel-liveout.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
non-masked-load.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
non-masked-store.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
out-of-range-cbz.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
predicated-invariant.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
predicated-liveout-unknown-lanes.ll [ARM] Generate VDUP(Const) from constant buildvectors 2021-06-08 20:51:33 +01:00
predicated-liveout.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
reductions-vpt-liveout.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
reductions.ll [ARM] Clean up some tests, removing dead instructions. NFC 2021-05-22 13:38:00 +01:00
remat-vctp.ll [ARM] Ensure instructions are simplified prior to GatherScatter lowering. 2021-06-10 20:18:12 +01:00
remove-elem-moves.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
revert-after-call.mir
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revert-after-read.mir
…
revert-after-write.mir
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revert-non-header.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
revert-non-loop.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
revert-while.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
revertcallearly.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
safe-def-no-mov.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
safe-retaining.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
sibling-loops.ll [ARM] Don't handle low overhead branches in AnalyzeBranch 2021-01-18 17:16:07 +00:00
size-limit.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
skip-debug.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
skip-vpt-debug.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
subreg-liveness.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
switch.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
tail-pred-basic.ll [ARM] Clean up some tests, removing dead instructions. NFC 2021-05-22 13:38:00 +01:00
tail-pred-const.ll [ARM] Clean up some tests, removing dead instructions. NFC 2021-05-22 13:38:00 +01:00
tail-pred-disabled-in-loloops.ll Allow rematerialization of virtual reg uses 2021-08-24 11:09:02 -07:00
tail-pred-intrinsic-add-sat.ll [ARM] Clean up some tests, removing dead instructions. NFC 2021-05-22 13:38:00 +01:00
tail-pred-intrinsic-fabs.ll [ARM] Clean up some tests, removing dead instructions. NFC 2021-05-22 13:38:00 +01:00
tail-pred-intrinsic-round.ll [ARM] Enable subreg liveness 2021-08-17 14:10:33 +01:00
tail-pred-intrinsic-sub-sat.ll [ARM] Clean up some tests, removing dead instructions. NFC 2021-05-22 13:38:00 +01:00
tail-pred-narrow.ll
…
tail-pred-pattern-fail.ll
…
tail-pred-reduce.ll [ARM] Clean up some tests, removing dead instructions. NFC 2021-05-22 13:38:00 +01:00
tail-pred-widen.ll [ARM] Clean up some tests, removing dead instructions. NFC 2021-05-22 13:38:00 +01:00
tp-multiple-vpst.ll
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unpredicated-max.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
unpredload.ll [ARM] Enable subreg liveness 2021-08-17 14:10:33 +01:00
unrolled-and-vector.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
unsafe-cpsr-loop-def.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
unsafe-cpsr-loop-use.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
unsafe-retaining.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
unsafe-use-after.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
vaddv.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
varying-outer-2d-reduction.ll Allow rematerialization of virtual reg uses 2021-08-24 11:09:02 -07:00
vcmp-vpst-combination-across-blocks.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
vcmp-vpst-combination.ll [ARM] Don't handle low overhead branches in AnalyzeBranch 2021-01-18 17:16:07 +00:00
vctp-add-operand-liveout.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
vctp-in-vpt-2.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
vctp-in-vpt.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
vctp-subi3.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
vctp-subri.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
vctp-subri12.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
vctp16-reduce.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
vector-arith-codegen.ll [ARM] Clean up some tests, removing dead instructions. NFC 2021-05-22 13:38:00 +01:00
vector-reduce-mve-tail.ll [ARM] Clean up some tests, removing dead instructions. NFC 2021-05-22 13:38:00 +01:00
vector-unroll.ll
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vector_spill_in_loop.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
vmaxmin_vpred_r.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
vmldava_in_vpt.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
vpt-blocks.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
while-loops.ll Allow rematerialization of virtual reg uses 2021-08-24 11:09:02 -07:00
while-negative-offset.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
while.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
wls-search-killed.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
wls-search-pred.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
wlstp.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
wrong-liveout-lsr-shift.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
wrong-vctp-opcode-liveout.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
wrong-vctp-operand-liveout.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00