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llvm-project/llvm/test/CodeGen/AMDGPU
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Brendon Cahoon d45a247998 [AMDGPU] Don't remove VGPR to AGPR dead spills from frame info 
Removing dead frame indices for VGPR to AGPR spills is incorrect
when the frame index is shared by multiple objects, which may
occur due to stack slot coloring. The problem is that subsequent
code that processes the other object will assert because the stack
frame index is marked dead.

Removing dead frame indices is needed prior to stack slot
coloring, which is what happens with SGPR to VGPR spills. These
spills are lowered prior to stack slot coloring, but the VGPR
to AGPR spills are processed afterwards during the Prolog/Epilog
Inserter pass. This patch marks the VGPR to AGPR spill slot as
dead if the slot is not used by another object.

Differential Revision: https://reviews.llvm.org/D115996
 		2021-12-23 11:09:19 -06:00
..
GlobalISel AMDGPU/GlobalISel: Fix attempt to select non-legal instr in mir test 2021-12-23 16:14:33 +01:00
32-bit-local-address-space.ll [AMDGPU] Lower kernel LDS into a sorted structure 2021-05-25 11:29:29 -07:00
InlineAsmCrash.ll
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README
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SRSRC-GIT-clobber-check.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
aa-points-to-constant-memory.ll
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abi-attribute-hints-undefined-behavior.ll Revert "[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range" 2021-12-22 11:39:28 -05:00
acc-ldst.ll [AMDGPU] gfx90a support 2021-02-17 16:01:32 -08:00
accvgpr-copy.mir AMDGPU: Use v_accvgpr_mov_b32 when copying AGPR tuples on gfx90a 2021-12-15 18:20:49 -05:00
add-debug.ll
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add.i16.ll
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add.ll [AMDGPU] Add some more GFX10 test coverage 2021-12-03 14:03:31 +00:00
add.v2i16.ll [AMDGPU] Add some more GFX10 test coverage 2021-12-03 14:03:31 +00:00
add3.ll [AMDGPU] Switch PostRA sched to MachineSched 2021-09-14 15:11:27 -04:00
add_i1.ll
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add_i64.ll
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add_i128.ll
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add_shl.ll [AMDGPU] Stop adding an implicit def of vcc_hi for wave32 2020-12-02 10:11:42 +00:00
addrspacecast-captured.ll
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addrspacecast-constantexpr.ll AMDGPU: Invert ABI attribute handling 2021-09-09 18:24:28 -04:00
addrspacecast-initializer-unsupported.ll [AMDGPU] Rename "LDS lowering" pass name. 2021-04-14 20:19:53 +05:30
addrspacecast-initializer.ll
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addrspacecast.ll AMDGPU: Enable fixed function ABI by default 2021-12-04 10:49:18 -05:00
adjust-writemask-invalid-copy.ll [AMDGPU] Added -mcpu to couple more tests. NFC. 2021-02-03 10:20:18 -08:00
adjust-writemask-vectorized.ll [AMDGPU] gfx90a support 2021-02-17 16:01:32 -08:00
agpr-copy-no-vgprs.mir AMDGPU: Use v_accvgpr_mov_b32 when copying AGPR tuples on gfx90a 2021-12-15 18:20:49 -05:00
agpr-copy-propagation.mir [MachineCopyPropagation] Check CrossCopyRegClass for cross-class copys 2021-08-24 21:22:36 -07:00
agpr-copy-sgpr-no-vgprs.mir AMDGPU: Use v_accvgpr_mov_b32 when copying AGPR tuples on gfx90a 2021-12-15 18:20:49 -05:00
agpr-csr.ll RegAlloc: Allow targets to split register allocation 2021-07-13 18:49:29 -04:00
agpr-register-count.ll [AMDGPU] Improve register computation for indirect calls 2021-07-20 13:48:50 +02:00
agpr-remat.ll [AMDGPU] Switch PostRA sched to MachineSched 2021-09-14 15:11:27 -04:00
agpr-to-agpr-copy.mir [AMDGPU] Fix SGPR checks in S_MOV_B64_IMM_PSEUDO generation. 2021-11-03 09:09:24 +05:30
alignbit-pat.ll
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alloc-aligned-tuples-gfx90a.mir RegAlloc: Allow targets to split register allocation 2021-07-13 18:49:29 -04:00
alloc-aligned-tuples-gfx908.mir RegAlloc: Allow targets to split register allocation 2021-07-13 18:49:29 -04:00
alloc-all-regs-reserved-in-class.mir RegAlloc: Fix assert if all registers in class reserved 2021-01-31 11:10:04 -05:00
alloca.ll
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always-uniform.ll
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amd.endpgm.ll [AMDGPU] Do not generate ELF symbols for the local branch target labels 2021-11-20 10:32:41 +05:30
amdgcn-ieee.ll [AMDGPU] Add volatile support to SIMemoryLegalizer 2021-01-09 00:52:33 +00:00
amdgcn-load-offset-from-reg.ll CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
amdgcn.bitcast.ll
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amdgcn.private-memory.ll [AMDGPU] Divergence-driven compare operations instruction selection 2021-08-25 18:30:49 +03:00
amdgpu-alias-analysis.ll [NewPM][AMDGPU] Make amdgpu-aa work with NewPM 2021-01-04 12:36:27 -08:00
amdgpu-codegenprepare-fdiv.ll
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amdgpu-codegenprepare-fold-binop-select.ll [AMDGPU] Use S_BITCMP1_* to replace AND in optimizeCompareInstr 2021-09-01 15:59:12 -07:00
amdgpu-codegenprepare-foldnegate.ll [AMDGPU] [CodeGen] Fold negate llvm.amdgcn.class into test mask 2021-06-18 13:04:12 -06:00
amdgpu-codegenprepare-i16-to-i32.ll [AMDGPU] Update generated checks. NFC. 2021-06-18 10:49:02 +01:00
amdgpu-codegenprepare-idiv.ll [AMDGPU] Set most sched model resource's BufferSize to one 2021-12-01 22:31:28 -08:00
amdgpu-codegenprepare-mul24.ll [AMDGPU] Fix rhs of the tests in amdgpu-codegenprepare-mul24.ll. 2021-10-28 16:57:48 +05:30
amdgpu-function-calls-option.ll
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amdgpu-inline.ll [AMDGPU] Do not check max-bb for a single block callee 2021-03-01 19:48:50 -08:00
amdgpu-late-codegenprepare.ll AMDGPU: Fix assert on constant load from addrspacecasted pointer 2021-05-11 20:12:20 -04:00
amdgpu-mul24-knownbits.ll [LiveIntervals] Repair live intervals that gain subranges 2021-09-24 11:58:08 +01:00
amdgpu-reloc-const.ll [test] Avoid llvm-readelf/llvm-readobj one-dash long options and deprecated aliases (e.g. --file-headers) 2021-07-15 10:26:21 -07:00
amdgpu-shader-calling-convention.ll
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amdgpu-unroll-threshold.ll
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amdgpu.private-memory.ll [AMDGPU] Use s_add_i32 for address additions 2021-06-07 16:09:48 +02:00
amdgpu.work-item-intrinsics.deprecated.ll [NFC] Removed unused prefixes in CodeGen/AMDGPU 2021-01-05 14:10:03 -08:00
amdhsa-trap-num-sgprs.ll
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amdpal-callable.ll Revert "[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range" 2021-12-22 11:39:28 -05:00
amdpal-cs.ll [NFC] Removed unused prefixes in CodeGen/AMDGPU 2021-01-05 14:10:03 -08:00
amdpal-elf.ll [test] Change -t to --syms and -s to -S for llvm-readobj RUN lines 2021-06-29 11:50:31 -07:00
amdpal-es.ll [NFC] Removed unused prefixes in CodeGen/AMDGPU 2021-01-05 14:10:03 -08:00
amdpal-gs.ll [NFC] Removed unused prefixes in CodeGen/AMDGPU 2021-01-05 14:10:03 -08:00
amdpal-hs.ll [NFC] Removed unused prefixes in CodeGen/AMDGPU 2021-01-05 14:10:03 -08:00
amdpal-ls.ll [NFC] Removed unused prefixes in CodeGen/AMDGPU 2021-01-05 14:10:03 -08:00
amdpal-msgpack-cs.ll [NFC] Removed unused prefixes in CodeGen/AMDGPU 2021-01-05 14:10:03 -08:00
amdpal-msgpack-default.ll [NFC] Removed unused prefixes in CodeGen/AMDGPU 2021-01-05 14:10:03 -08:00
amdpal-msgpack-denormal.ll [NFC] Removed unused prefixes in CodeGen/AMDGPU 2021-01-05 14:10:03 -08:00
amdpal-msgpack-dx10-clamp.ll [NFC] Removed unused prefixes in CodeGen/AMDGPU 2021-01-05 14:10:03 -08:00
amdpal-msgpack-es.ll [NFC] Removed unused prefixes in CodeGen/AMDGPU 2021-01-05 14:10:03 -08:00
amdpal-msgpack-gs.ll [NFC] Removed unused prefixes in CodeGen/AMDGPU 2021-01-05 14:10:03 -08:00
amdpal-msgpack-hs.ll [NFC] Removed unused prefixes in CodeGen/AMDGPU 2021-01-05 14:10:03 -08:00
amdpal-msgpack-ieee.ll [NFC] Removed unused prefixes in CodeGen/AMDGPU 2021-01-05 14:10:03 -08:00
amdpal-msgpack-ls.ll [NFC] Removed unused prefixes in CodeGen/AMDGPU 2021-01-05 14:10:03 -08:00
amdpal-msgpack-ps.ll [NFC] Removed unused prefixes in CodeGen/AMDGPU 2021-01-05 14:10:03 -08:00
amdpal-msgpack-psenable.ll [NFC] Removed unused prefixes in CodeGen/AMDGPU 2021-01-05 14:10:03 -08:00
amdpal-msgpack-vs.ll [NFC] Removed unused prefixes in CodeGen/AMDGPU 2021-01-05 14:10:03 -08:00
amdpal-ps.ll [NFC] Removed unused prefixes in CodeGen/AMDGPU 2021-01-05 14:10:03 -08:00
amdpal-psenable.ll [NFC] Removed unused prefixes in CodeGen/AMDGPU 2021-01-05 14:10:03 -08:00
amdpal-vs.ll [NFC] Removed unused prefixes in CodeGen/AMDGPU 2021-01-05 14:10:03 -08:00
amdpal.ll
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amdpal_scratch_mergedshader.ll
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and-gcn.ll
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and.ll [AMDGPU] Set most sched model resource's BufferSize to one 2021-12-01 22:31:28 -08:00
and_or.ll [AMDGPU] Stop adding an implicit def of vcc_hi for wave32 2020-12-02 10:11:42 +00:00
andorbitset.ll
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andorn2.ll [NFC] Removed unused prefixes in CodeGen/AMDGPU 2021-01-05 14:10:03 -08:00
andorxorinvimm.ll
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annotate-existing-abi-attributes.ll AMDGPU: Invert AMDGPUAttributor 2021-08-26 21:32:13 -04:00
annotate-kernel-features-hsa-call.ll AMDGPU: Sanitized functions require implicit arguments 2021-12-02 17:55:43 -05:00
annotate-kernel-features-hsa.ll AMDGPU: Invert ABI attribute handling 2021-09-09 18:24:28 -04:00
annotate-kernel-features.ll AMDGPU: Invert ABI attribute handling 2021-09-09 18:24:28 -04:00
annotate-noclobber.ll AMDGPU: Annotate amdgpu.noclobber for global loads only 2021-01-05 14:47:19 -08:00
anonymous-gv.ll
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any_extend_vector_inreg.ll
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anyext.ll [AMDGPU] Set most sched model resource's BufferSize to one 2021-12-01 22:31:28 -08:00
are-loads-from-same-base-ptr.ll
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array-ptr-calc-i32.ll
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array-ptr-calc-i64.ll
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artificial-terminators.mir [AMDGPU] Only remove branches in SIInstrInfo::removeBranch 2021-10-06 10:34:26 +09:00
ashr.v2i16.ll [AMDGPU] Only select VOP3 forms of VOP2 instructions 2021-11-24 11:15:30 +00:00
asm-printer-check-vcc.mir
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at-least-one-def-value-assert.mir
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atomic_cmp_swap_local.ll [NFC] Removed unused prefixes in CodeGen/AMDGPU 2021-01-05 14:10:03 -08:00
atomic_load_add.ll
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atomic_load_local.ll [AMDGPU] Add patterns for i8/i16 local atomic load/store 2021-10-18 11:23:10 +02:00
atomic_load_sub.ll
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atomic_optimizations_buffer.ll [AMDGPU] Remove weird target triples from tests. NFC. 2021-03-19 16:48:32 +00:00
atomic_optimizations_global_pointer.ll [AMDGPU] Set most sched model resource's BufferSize to one 2021-12-01 22:31:28 -08:00
atomic_optimizations_local_pointer.ll [AMDGPU] Implement widening multiplies with v_mad_i64_i32/v_mad_u64_u32 2021-11-24 11:25:02 +00:00
atomic_optimizations_pixelshader.ll [AMDGPU] Do not generate ELF symbols for the local branch target labels 2021-11-20 10:32:41 +05:30
atomic_optimizations_raw_buffer.ll [AMDGPU] Remove weird target triples from tests. NFC. 2021-03-19 16:48:32 +00:00
atomic_optimizations_struct_buffer.ll [AMDGPU] Remove weird target triples from tests. NFC. 2021-03-19 16:48:32 +00:00
atomic_store_local.ll [AMDGPU] Add patterns for i8/i16 local atomic load/store 2021-10-18 11:23:10 +02:00
atomicrmw-nand.ll [AMDGPU] Do not generate ELF symbols for the local branch target labels 2021-11-20 10:32:41 +05:30
atomics-cas-remarks-gfx90a.ll [Remarks] [AMDGPU] Emit optimization remarks for atomics generating hardware instructions 2021-08-19 20:51:19 -06:00
atomics-hw-remarks-gfx90a.ll [Remarks] [AMDGPU] Emit optimization remarks for atomics generating hardware instructions 2021-08-19 20:51:19 -06:00
attr-amdgpu-flat-work-group-size-v3.ll AMDGPU: Add target id and code object v4 support 2021-03-24 11:54:05 -04:00
attr-amdgpu-flat-work-group-size-vgpr-limit.ll [AMDGPU] Allow to use a whole register file on gfx90a for VGPRs 2021-10-21 18:24:34 -07:00
attr-amdgpu-flat-work-group-size.ll AMDGPU: Add target id and code object v4 support 2021-03-24 11:54:05 -04:00
attr-amdgpu-num-sgpr.ll [NFC] Removed unused prefixes in CodeGen/AMDGPU 2021-01-05 14:10:03 -08:00
attr-amdgpu-num-vgpr.ll
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attr-amdgpu-waves-per-eu.ll AMDGPU: Don't consider whether amdgpu-flat-work-group-size was set 2021-10-22 16:23:50 -04:00
attr-unparseable.ll
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av_spill_cross_bb_usage.mir [AMDGPU] Add AV class spill pseudo instructions 2021-12-10 03:10:34 -05:00
barrier-elimination.ll
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basic-branch.ll [AMDGPU] Do not generate ELF symbols for the local branch target labels 2021-11-20 10:32:41 +05:30
basic-call-return.ll
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basic-loop.ll
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bfe-combine.ll
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bfe-patterns.ll [AMDGPU] Only select VOP3 forms of VOP2 instructions 2021-11-24 11:15:30 +00:00
bfe_uint.ll
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bfi_int.ll
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bfm.ll [NFC] Removed unused prefixes in test/CodeGen/AMDGPU 2021-01-05 14:16:52 -08:00
big_alu.ll
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bitcast-constant-to-vector.ll
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bitcast-v4f16-v4i16.ll
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bitcast-vector-extract.ll
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bitreverse-inline-immediates.ll
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bitreverse.ll [AMDGPU] Set most sched model resource's BufferSize to one 2021-12-01 22:31:28 -08:00
br_cc.f16.ll
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branch-condition-and.ll [AMDGPU] Do not generate ELF symbols for the local branch target labels 2021-11-20 10:32:41 +05:30
branch-relax-bundle.ll [AMDGPU] Do not generate ELF symbols for the local branch target labels 2021-11-20 10:32:41 +05:30
branch-relax-spill.ll Revert "[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range" 2021-12-22 11:39:28 -05:00
branch-relaxation-debug-info.mir [AMDGPU] Do not generate ELF symbols for the local branch target labels 2021-11-20 10:32:41 +05:30
branch-relaxation-gfx10-branch-offset-bug.ll [AMDGPU] Do not generate ELF symbols for the local branch target labels 2021-11-20 10:32:41 +05:30
branch-relaxation-inst-size-gfx10.ll [AMDGPU] Set most sched model resource's BufferSize to one 2021-12-01 22:31:28 -08:00
branch-relaxation.ll [AMDGPU] Set most sched model resource's BufferSize to one 2021-12-01 22:31:28 -08:00
branch-uniformity.ll
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break-smem-soft-clauses.mir AMDGPU: Add target id and code object v4 support 2021-03-24 11:54:05 -04:00
break-vmem-soft-clauses.mir [AMDGPU] Use single cache policy operand 2021-03-15 13:00:59 -07:00
bswap.ll [AMDGPU] Set most sched model resource's BufferSize to one 2021-12-01 22:31:28 -08:00
buffer-intrinsics-mmo-offsets.ll [AMDGPU] Fix MMO for raw/struct buffer access with non-constant offset 2021-07-26 14:27:30 +01:00
buffer-schedule.ll [AMDGPU] Fix MMO for raw/struct buffer access with non-constant offset 2021-07-26 14:27:30 +01:00
bug-sdag-scheduler-cycle.ll
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bug-v4f64-subvector.ll [AMDGPU] Add SelectionDAG support for insert_subvector on v4f64 2021-07-27 10:11:34 +09:00
bug-vopc-commute.ll
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build-vector-insert-elt-infloop.ll
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build-vector-packed-partial-undef.ll
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build_vector.ll [AMDGPU] Set most sched model resource's BufferSize to one 2021-12-01 22:31:28 -08:00
bundle-latency.mir [AMDGPU] Use single cache policy operand 2021-03-15 13:00:59 -07:00
bypass-div.ll [AMDGPU] Implement widening multiplies with v_mad_i64_i32/v_mad_u64_u32 2021-11-24 11:25:02 +00:00
byval-frame-setup.ll [AMDGPU] Do not generate ELF symbols for the local branch target labels 2021-11-20 10:32:41 +05:30
call-argument-types.ll AMDGPU: Enable fixed function ABI by default 2021-12-04 10:49:18 -05:00
call-constant.ll AMDGPU: Remove fixed function ABI option 2021-12-10 19:41:19 -05:00
call-constexpr.ll Revert "AMDGPU: Remove AMDGPUFixFunctionBitcasts pass" 2021-12-16 21:21:32 +00:00
call-encoding.ll [NFC] Removed unused prefixes in test/CodeGen/AMDGPU 2021-01-05 14:16:52 -08:00
call-graph-register-usage.ll Revert "[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range" 2021-12-22 11:39:28 -05:00
call-preserved-registers.ll Revert "[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range" 2021-12-22 11:39:28 -05:00
call-return-types.ll
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call-skip.ll [AMDGPU] Do not generate ELF symbols for the local branch target labels 2021-11-20 10:32:41 +05:30
call-to-kernel-undefined.ll
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call-to-kernel.ll
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call-waitcnt.ll AMDGPU: Enable fixed function ABI by default 2021-12-04 10:49:18 -05:00
call-waw-waitcnt.mir [AMDGPU] Use single cache policy operand 2021-03-15 13:00:59 -07:00
call_fs.ll
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callee-frame-setup.ll Revert "[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range" 2021-12-22 11:39:28 -05:00
callee-special-input-sgprs-fixed-abi.ll Revert "[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range" 2021-12-22 11:39:28 -05:00
callee-special-input-vgprs-packed.ll AMDGPU: Enable fixed function ABI by default 2021-12-04 10:49:18 -05:00
callee-special-input-vgprs.ll AMDGPU: Remove fixed function ABI option 2021-12-10 19:41:19 -05:00
calling-conventions.ll
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captured-frame-index.ll [AMDGPU] Switch PostRA sched to MachineSched 2021-09-14 15:11:27 -04:00
carryout-selection.ll [AMDGPU] Simplify 64-bit division/remainder expansion 2021-11-12 15:48:41 +00:00
cayman-loop-bug.ll
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cc-sgpr-limit.ll
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cc-sgpr-over-limit.ll
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cc-update.ll AMDGPU: Enable fixed function ABI by default 2021-12-04 10:49:18 -05:00
cf-loop-on-constant.ll [AMDGPU] Do not generate ELF symbols for the local branch target labels 2021-11-20 10:32:41 +05:30
cf-stack-bug.ll
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cf_end.ll
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cgp-addressing-modes-flat.ll [AMDGPU] Do not generate ELF symbols for the local branch target labels 2021-11-20 10:32:41 +05:30
cgp-addressing-modes-gfx908.ll [AMDGPU] Do not generate ELF symbols for the local branch target labels 2021-11-20 10:32:41 +05:30
cgp-addressing-modes-gfx1030.ll [AMDGPU] Do not generate ELF symbols for the local branch target labels 2021-11-20 10:32:41 +05:30
cgp-addressing-modes.ll [AMDGPU] Do not generate ELF symbols for the local branch target labels 2021-11-20 10:32:41 +05:30
cgp-bitfield-extract.ll [AMDGPU] Do not generate ELF symbols for the local branch target labels 2021-11-20 10:32:41 +05:30
chain-hi-to-lo.ll [AMDGPU] Set most sched model resource's BufferSize to one 2021-12-01 22:31:28 -08:00
change-scc-to-vcc.mir [AMDGPU] Update SCC defs to VCC when uses are changed to VCC 2021-05-14 18:05:05 -04:00
clamp-modifier.ll [FPEnv][AMDGPU] Disable FSUB(-0,X)->FNEG(X) DAGCombine when subnormals are flushed 2021-01-04 14:44:10 -06:00
clamp-omod-special-case.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
clamp.ll Revert "[NFC] remove explicit default value for strboolattr attribute in tests" 2021-05-24 19:43:40 +02:00
cluster-flat-loads-postra.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
cluster-flat-loads.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
cluster_stores.ll [AMDGPU] Switch PostRA sched to MachineSched 2021-09-14 15:11:27 -04:00
cmp_shrink.mir
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cndmask-no-def-vcc.ll [AMDGPU] Divergence-driven compare operations instruction selection 2021-08-25 18:30:49 +03:00
coalesce-identity-copies-undef-subregs.mir RegisterCoalescer: Prune undef subranges from copy pairs in loops 2021-02-03 13:42:53 -05:00
coalesce-vgpr-alignment.ll AMDGPU: Remove special case in shouldCoalesce 2021-02-24 14:49:44 -05:00
coalescer-extend-pruned-subrange.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
coalescer-identical-values-undef.mir
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coalescer-remat-dead-use.mir Prevent dead uses in register coalescer after rematerialization 2021-07-21 15:19:55 -07:00
coalescer-removepartial-extend-undef-subrange.mir
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coalescer-subranges-another-copymi-not-live.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
coalescer-subranges-another-prune-error.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
coalescer-subranges-prune-kill-copy.mir
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coalescer-subreg-join.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
coalescer-subregjoin-fullcopy.mir [AMDGPU] Use single cache policy operand 2021-03-15 13:00:59 -07:00
coalescer-with-subregs-bad-identical.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
coalescer_distribute.ll
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coalescer_remat.ll [AMDGPU] Switch AnnotateUniformValues to MemorySSA 2021-05-05 18:34:41 -07:00
coalescing-subreg-was-undef-but-became-def.mir
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coalescing-with-subregs-in-loop-bug.mir
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coalescing_makes_lanes_undef.mir
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code-object-v3.ll [AMDGPU] Set most sched model resource's BufferSize to one 2021-12-01 22:31:28 -08:00
codegen-prepare-addrmode-sext.ll
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collapse-endcf-broken.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
collapse-endcf.ll [AMDGPU] Do not generate ELF symbols for the local branch target labels 2021-11-20 10:32:41 +05:30
collapse-endcf.mir
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collapse-endcf2.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
combine-add-zext-xor.ll [AMDGPU] Fix a miscompile with S_ADD/S_SUB 2021-02-17 12:24:58 +01:00
combine-and-sext-bool.ll
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combine-cond-add-sub.ll
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combine-ftrunc.ll
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combine-reg-or-const.ll [AMDGPU] Small correction in SITargetLowering::performOrCombine(). 2021-11-10 21:07:27 -05:00
combine-sreg64-inits.mir [AMDGPU] Fix SGPR checks in S_MOV_B64_IMM_PSEUDO generation. 2021-11-03 09:09:24 +05:30
combine_vloads.ll
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comdat.ll
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commute-compares.ll [NFC] Removed unused prefixes in test/CodeGen/AMDGPU 2021-01-05 14:16:52 -08:00
commute-shifts.ll [AMDGPU] Set most sched model resource's BufferSize to one 2021-12-01 22:31:28 -08:00
commute-vop3.mir [AMDGPU] Make some VOP3 insts commutable 2021-04-28 13:59:08 -04:00
commute_modifiers.ll [AMDGPU] Add volatile support to SIMemoryLegalizer 2021-01-09 00:52:33 +00:00
complex-folding.ll
…
computeKnownBits-scalar-to-vector-crash.ll
…
computeNumSignBits-mul.ll
…
concat_vectors.ll [NFC] Removed unused prefixes in test/CodeGen/AMDGPU 2021-01-05 14:16:52 -08:00
constant-address-space-32bit.ll [AMDGPU] Update subtarget features for new target ID support 2021-01-26 11:25:51 -08:00
constant-fold-imm-immreg.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
constant-fold-mi-operands.ll
…
constrained-shift.ll [AMDGPU] Check for unneeded shift mask in shift PatFrags. 2021-11-24 10:53:12 +05:30
control-flow-fastregalloc.ll [AMDGPU] Do not generate ELF symbols for the local branch target labels 2021-11-20 10:32:41 +05:30
control-flow-optnone.ll [AMDGPU] Divergence-driven compare operations instruction selection 2021-08-25 18:30:49 +03:00
convergent-inlineasm.ll
…
copy-illegal-type.ll [AMDGPU] Set most sched model resource's BufferSize to one 2021-12-01 22:31:28 -08:00
copy-overlap-vgpr-kill.mir
…
copy-to-reg.ll
…
copy_phys_vgpr64.mir [AMDGPU] Extend gfx10 test coverage. NFC. 2021-03-29 11:13:55 +02:00
copy_to_scc.ll [AMDGPU] Set most sched model resource's BufferSize to one 2021-12-01 22:31:28 -08:00
couldnt-join-subrange-3.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
cross-block-use-is-not-abi-copy.ll Revert "[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range" 2021-12-22 11:39:28 -05:00
cse-phi-incoming-val.ll
…
csr-gfx10.ll
…
csr-sgpr-spill-live-ins.mir AMDGPU: Add spilled CSR SGPRs to entry block live ins 2020-12-22 21:55:59 -05:00
ctlz.ll [AMDGPU] Set most sched model resource's BufferSize to one 2021-12-01 22:31:28 -08:00
ctlz_zero_undef.ll [AMDGPU] Set most sched model resource's BufferSize to one 2021-12-01 22:31:28 -08:00
ctpop.ll
…
ctpop16.ll [AMDGPU] Set most sched model resource's BufferSize to one 2021-12-01 22:31:28 -08:00
ctpop64.ll [AMDGPU] Set most sched model resource's BufferSize to one 2021-12-01 22:31:28 -08:00
cttz.ll [AMDGPU] Set most sched model resource's BufferSize to one 2021-12-01 22:31:28 -08:00
cttz_zero_undef.ll AMDGPU/GlobalISel: Stop using NarrowScalar/FewerElements for unaligned splitting 2021-12-20 18:07:11 -05:00
cube.ll [NFC] Removed unused prefixes in test/CodeGen/AMDGPU 2021-01-05 14:16:52 -08:00
cvt_f32_ubyte.ll [AMDGPU] Set most sched model resource's BufferSize to one 2021-12-01 22:31:28 -08:00
cvt_flr_i32_f32.ll
…
cvt_rpi_i32_f32.ll
…
dag-divergence-atomic.ll [AMDGPU] Set most sched model resource's BufferSize to one 2021-12-01 22:31:28 -08:00
dag-divergence.ll
…
dagcomb-shuffle-vecextend-non2.ll
…
dagcombine-fma-fmad.ll [AMDGPU] Prefer v_fmac over v_fma only when no source modifiers are used 2021-09-21 11:57:45 +01:00
dagcombine-reassociate-bug.ll
…
dagcombine-select.ll [amdgpu] Enable selection of `s_cselect_b64`. 2021-09-07 10:45:07 -04:00
dagcombine-setcc-select.ll
…
dagcombiner-bug-illegal-vec4-int-to-fp.ll
…
dbg-value-ends-sched-region.mir [AMDGPU] Set most sched model resource's BufferSize to one 2021-12-01 22:31:28 -08:00
dce-disjoint-intervals.mir [AMDGPU] Use single cache policy operand 2021-03-15 13:00:59 -07:00
dead-lane.mir [LiveIntervals] Remove unused subreg ranges in repairIntervalsInRange 2021-09-30 09:15:10 +01:00
dead-machine-elim-after-dead-lane.ll
…
dead_copy.mir [AMDGPU] Use single cache policy operand 2021-03-15 13:00:59 -07:00
debug-value-scheduler-crash.mir [AMDGPU] Use single cache policy operand 2021-03-15 13:00:59 -07:00
debug-value.ll VirtRegMap: Preserve LiveDebugVariables 2021-05-27 10:40:14 -04:00
debug-value2.ll
…
debug.ll [NFC] Removed unused prefixes in test/CodeGen/AMDGPU 2021-01-05 14:16:52 -08:00
debug_frame.ll [MCAsmInfo] Support UsesCFIForDebug for targets with no exception handling 2021-05-06 04:53:45 +05:30
default-flat-work-group-size-overrides-waves-per-eu.ll AMDGPU: Don't consider whether amdgpu-flat-work-group-size was set 2021-10-22 16:23:50 -04:00
default-fp-mode.ll
…
detect-dead-lanes.mir
…
direct-indirect-call.ll AMDGPU: Use attributor to propagate uniform-work-group-size 2021-09-09 18:24:28 -04:00
directive-amdgcn-target.ll [AMDGPU] Add gfx1035 target 2021-06-24 14:32:41 -04:00
disable_form_clauses.ll AMDGPU: Use kill instruction to hint soft clause live ranges 2021-02-26 18:26:40 -05:00
disconnected-predset-break-bug.ll
…
div_i128.ll
…
diverge-extra-formal-args.ll [NFC] Removed unused prefixes in test/CodeGen/AMDGPU 2021-01-05 14:16:52 -08:00
diverge-interp-mov-lower.ll [NFC] Removed unused prefixes in test/CodeGen/AMDGPU 2021-01-05 14:16:52 -08:00
diverge-switch-default.ll
…
divergence-at-use.ll
…
divergence-driven-bfe-isel.ll [AMDGPU] Enable divergence-driven BFE selection 2021-11-03 23:26:59 +03:00
divergence-driven-buildvector.ll [AMDGPU] Select build_vector DAG nodes according to the divergence 2021-12-23 02:27:12 +03:00
divergence-driven-ctlz-cttz.ll [AMDGPU] Enable divergence predicates for ctlz/cttz 2021-12-20 20:53:48 +03:00
divergence-driven-min-max.ll [AMDGPU] Re-enabling divergence predicates for min/max 2021-12-20 16:10:55 +03:00
divergence-driven-not-isel.ll [AMDGPU] Expand not pattern according to the XOR node divergence 2021-12-20 14:41:38 +03:00
divergent-branch-uniform-condition.ll [AMDGPU] Do not generate ELF symbols for the local branch target labels 2021-11-20 10:32:41 +05:30
divrem24-assume.ll
…
dpp64_combine.ll [AMDGPU][MC] Corrected bound_ctrl for compatibility with sp3 2021-02-22 14:59:40 +03:00
dpp64_combine.mir AMDGPU: Add even aligned VGPR/AGPR register classes 2021-02-24 14:49:37 -05:00
dpp_combine.ll [AMDGPU][MC] Corrected bound_ctrl for compatibility with sp3 2021-02-22 14:59:40 +03:00
dpp_combine.mir [AMDGPU] GCNDPPCombine: don't shrink V_ADD_CO_U32 if carry out is used 2021-04-20 09:17:52 +01:00
drop-mem-operand-move-smrd.ll [NFC] Removed unused prefixes in test/CodeGen/AMDGPU 2021-01-05 14:16:52 -08:00
ds-alignment.ll AMDGPU/GlobalISel: Stop using NarrowScalar/FewerElements for unaligned splitting 2021-12-20 18:07:11 -05:00
ds-combine-large-stride.ll [AMDGPU] Better selection of base offset when merging DS reads/writes 2021-02-11 17:46:09 +00:00
ds-combine-with-dependence.ll
…
ds-negative-offset-addressing-mode-loop.ll
…
ds-sub-offset.ll [AMDGPU] Fix latency for implicit vcc_lo operands on GFX10 wave32 2021-10-22 20:03:29 +01:00
ds_gws_align.ll [AMDGPU] All GWS instructions need aligned VGPR on gfx90a 2021-06-01 17:08:03 -07:00
ds_read2.ll AMDGPU: Enable fixed function ABI by default 2021-12-04 10:49:18 -05:00
ds_read2_offset_order.ll [AMDGPU] Increase alignment of LDS globals if necessary before LDS lowering. 2021-06-07 18:00:41 +05:30
ds_read2_superreg.ll [NFC] Removed unused prefixes in test/CodeGen/AMDGPU 2021-01-05 14:16:52 -08:00
ds_read2st64.ll
…
ds_write2.ll [AMDGPU] Set most sched model resource's BufferSize to one 2021-12-01 22:31:28 -08:00
ds_write2st64.ll [AMDGPU] Add volatile support to SIMemoryLegalizer 2021-01-09 00:52:33 +00:00
duplicate-attribute-indirect.ll AMDGPU: Invert ABI attribute handling 2021-09-09 18:24:28 -04:00
dynamic_stackalloc.ll
…
early-if-convert-cost.ll
…
early-if-convert.ll [AMDGPU] Do not generate ELF symbols for the local branch target labels 2021-11-20 10:32:41 +05:30
early-inline-alias.ll
…
early-inline.ll Revert "Revert "Temporarily do not drop volatile stores before unreachable"" 2021-07-09 11:44:34 -04:00
early-tailduplicator-nophis.mir
…
early-tailduplicator-terminator.mir [TailDuplicator] Fix merging block with terminator 2021-10-29 10:52:46 +02:00
early-term.mir [AMDGPU] Allow frontends to disable null export for pixel shaders 2021-07-22 10:20:46 +09:00
elf-header-flags-mach.ll [test] Avoid llvm-readelf/llvm-readobj one-dash long options and deprecated aliases (e.g. --file-headers) 2021-07-15 10:26:21 -07:00
elf-header-flags-sramecc.ll [test] Avoid llvm-readelf/llvm-readobj one-dash long options and deprecated aliases (e.g. --file-headers) 2021-07-15 10:26:21 -07:00
elf-header-flags-xnack.ll AMDGPU: Add target id and code object v4 support 2021-03-24 11:54:05 -04:00
elf-header-osabi.ll AMDGPU: Add target id and code object v4 support 2021-03-24 11:54:05 -04:00
elf-notes.ll AMDGPU: Add target id and code object v4 support 2021-03-24 11:54:05 -04:00
elf.ll
…
elf.metadata.ll
…
elf.r600.ll
…
else.ll
…
empty-function.ll
…
enable-no-signed-zeros-fp-math.ll
…
endcf-loop-header.ll [AMDGPU] Do not generate ELF symbols for the local branch target labels 2021-11-20 10:32:41 +05:30
endpgm-dce.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
enqueue-kernel.ll OpaquePtr: Bulk update tests to use typed byval 2020-11-20 14:00:46 -05:00
exceed-max-sgprs.ll Improve the diagnostic of DiagnosticInfoResourceLimit (and warn-stack-size in particular) 2021-06-22 09:55:20 -07:00
expand-atomicrmw-syncscope.ll [AMDGPU] Update gfx90a memory model support 2021-04-07 22:17:58 +00:00
expand-scalar-carry-out-select-user.ll [AMDGPU] Do not generate ELF symbols for the local branch target labels 2021-11-20 10:32:41 +05:30
expand-si-indirect.mir [AMDGPU] Use single cache policy operand 2021-03-15 13:00:59 -07:00
extend-bit-ops-i16.ll
…
extend-phi-subrange-not-in-parent.mir [AMDGPU] Enable copy between VGPR and AGPR classes during regalloc 2021-11-29 22:19:33 -05:00
extload-align.ll CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
extload-private.ll [AMDGPU] Add volatile support to SIMemoryLegalizer 2021-01-09 00:52:33 +00:00
extload.ll [NFC] Removed unused prefixes in test/CodeGen/AMDGPU 2021-01-05 19:18:30 -08:00
extra-sroa-after-unroll.ll [opt] Directly translate -O# to -passes='default<O#>' 2021-10-18 16:48:10 -07:00
extract-load-i1.ll Revert "[LiveIntervals] Fix repairOldRegInRange for simple def cases" 2021-09-23 17:55:05 +01:00
extract-lowbits.ll [AMDGPU] Only select VOP3 forms of VOP2 instructions 2021-11-24 11:15:30 +00:00
extract-subvector-equal-length.ll
…
extract-subvector.ll
…
extract-vector-elt-build-vector-combine.ll
…
extract_subvector_vec4_vec3.ll [AMDGPU] Fix MMO for raw/struct buffer access with non-constant offset 2021-07-26 14:27:30 +01:00
extract_vector_dynelt.ll [AMDGPU] More robust checks in extract_vector_dynelt.ll 2021-11-02 13:26:31 +00:00
extract_vector_elt-f16.ll
…
extract_vector_elt-f64.ll [amdgpu] Enable selection of `s_cselect_b64`. 2021-09-07 10:45:07 -04:00
extract_vector_elt-i8.ll [AMDGPU] Set most sched model resource's BufferSize to one 2021-12-01 22:31:28 -08:00
extract_vector_elt-i16.ll [AMDGPU] Set most sched model resource's BufferSize to one 2021-12-01 22:31:28 -08:00
extract_vector_elt-i64.ll [amdgpu] Enable selection of `s_cselect_b64`. 2021-09-07 10:45:07 -04:00
extractelt-to-trunc.ll [AMDGPU] Divergence-driven compare operations instruction selection 2021-08-25 18:30:49 +03:00
fabs.f16.ll AMDGPU: Select global saddr mode from SGPR pointer 2020-11-16 11:51:06 -05:00
fabs.f64.ll [AMDGPU] Enable fneg and fabs divergence-driven instruction selection. 2021-11-23 19:37:07 +03:00
fabs.ll [AMDGPU] Set most sched model resource's BufferSize to one 2021-12-01 22:31:28 -08:00
fadd-fma-fmul-combine.ll [AMDGPU] Add volatile support to SIMemoryLegalizer 2021-01-09 00:52:33 +00:00
fadd.f16.ll
…
fadd.ll Revert "[NFC] remove explicit default value for strboolattr attribute in tests" 2021-05-24 19:43:40 +02:00
fadd64.ll [AMDGPU] Fix dubious regexes with unescaped brackets. NFC. 2021-04-06 13:17:41 +01:00
fail-select-buffer-atomic-fadd.ll
…
fast-ra-kills-vcc.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
fast-regalloc-bundles.mir [NFC] Removed unused prefixes in test/CodeGen/AMDGPU 2021-01-05 19:18:30 -08:00
fast-unaligned-load-store.global.ll [AMDGPU] Set most sched model resource's BufferSize to one 2021-12-01 22:31:28 -08:00
fast-unaligned-load-store.private.ll [AMDGPU] Set most sched model resource's BufferSize to one 2021-12-01 22:31:28 -08:00
fastregalloc-illegal-subreg-physreg.mir
…
fastregalloc-self-loop-heuristic.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
fcanonicalize-elimination.ll [AMDGPU] Improve Codegen for build_vector 2021-05-12 14:17:44 +01:00
fcanonicalize.f16.ll [AMDGPU] Switch PostRA sched to MachineSched 2021-09-14 15:11:27 -04:00
fcanonicalize.ll AMDGPU: Select global saddr mode from SGPR pointer 2020-11-16 11:51:06 -05:00
fceil.ll
…
fceil64.ll
…
fcmp-cnd.ll
…
fcmp-cnde-int-args.ll
…
fcmp.f16.ll
…
fcmp.ll
…
fcmp64.ll [AMDGPU] Fix dubious regexes with unescaped brackets. NFC. 2021-04-06 13:17:41 +01:00
fconst64.ll
…
fcopysign.f16.ll [NFC] Removed unused prefixes in test/CodeGen/AMDGPU 2021-01-05 19:18:30 -08:00
fcopysign.f32.ll
…
fcopysign.f64.ll
…
fdiv-nofpexcept.ll Revert "[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range" 2021-12-22 11:39:28 -05:00
fdiv.f16.ll
…
fdiv.f64.ll Revert "[NFC] remove explicit default value for strboolattr attribute in tests" 2021-05-24 19:43:40 +02:00
fdiv.ll [AMDGPU] Prefer fmac over fma when selecting FMA_W_CHAIN 2021-09-21 11:57:45 +01:00
fdiv32-to-rcp-folding.ll [FPEnv][AMDGPU] Disable FSUB(-0,X)->FNEG(X) DAGCombine when subnormals are flushed 2021-01-04 14:44:10 -06:00
fdot2.ll
…
fence-barrier.ll
…
fence-lds-read2-write2.ll [AMDGPU] Better selection of base offset when merging DS reads/writes 2021-02-11 17:46:09 +00:00
fetch-limits.r600.ll
…
fetch-limits.r700+.ll
…
fexp.ll [AMDGPU] Switch PostRA sched to MachineSched 2021-09-14 15:11:27 -04:00
ffloor.f64.ll [AMDGPU] Fix dubious regexes with unescaped brackets. NFC. 2021-04-06 13:17:41 +01:00
ffloor.ll
…
fix-frame-ptr-reg-copy-livein.ll Revert "[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range" 2021-12-22 11:39:28 -05:00
fix-sgpr-copies.mir
…
fix-vgpr-copies.mir
…
fix-wwm-vgpr-copy.ll [AMDGPU] Rename amdgcn_wwm to amdgcn_strict_wwm 2021-03-03 09:33:57 +01:00
flat-address-space.ll [AMDGPU] Add volatile support to SIMemoryLegalizer 2021-01-09 00:52:33 +00:00
flat-error-unsupported-gpu-hsa.ll CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
flat-for-global-subtarget-feature.ll
…
flat-load-clustering.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
flat-offset-bug.ll
…
flat-scratch-fold-fi.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
flat-scratch-init.ll AMDGPU: Enable fixed function ABI by default 2021-12-04 10:49:18 -05:00
flat-scratch-reg.ll [AMDGPU] Always reserve flat scratch SGPR for architected flat scratch 2021-09-24 09:46:31 -07:00
flat-scratch.ll [AMDGPU] Only select VOP3 forms of VOP2 instructions 2021-11-24 11:15:30 +00:00
flat_atomics.ll
…
flat_atomics_i64.ll
…
floor.ll
…
fma-combine.ll Revert "[NFC] remove explicit default value for strboolattr attribute in tests" 2021-05-24 19:43:40 +02:00
fma.f64.ll [AMDGPU] Prefer v_fmac over v_fma only when no source modifiers are used 2021-09-21 11:57:45 +01:00
fma.ll [DAGCombine] Add node level checks for fp-contract and fp-ninf in visitFMULForFMADistributiveCombine(). 2021-09-02 11:33:14 +05:30
fmac.sdwa.ll
…
fmad-formation-fmul-distribute-denormal-mode.ll [AMDGPU] Prefer v_fmac over v_fma only when no source modifiers are used 2021-09-21 11:57:45 +01:00
fmad.ll
…
fmax.ll
…
fmax3.f64.ll [AMDGPU] Add volatile support to SIMemoryLegalizer 2021-01-09 00:52:33 +00:00
fmax3.ll AMDGPU: Try to eliminate clearing of high bits of 16-bit instructions 2021-06-22 13:42:49 -04:00
fmax_legacy.f16.ll [AMDGPU] Switch PostRA sched to MachineSched 2021-09-14 15:11:27 -04:00
fmax_legacy.f64.ll [AMDGPU] Set most sched model resource's BufferSize to one 2021-12-01 22:31:28 -08:00
fmax_legacy.ll [NFC] Removed unused prefixes in test/CodeGen/AMDGPU 2021-01-05 19:18:30 -08:00
fmaxnum.f64.ll
…
fmaxnum.ll
…
fmaxnum.r600.ll
…
fmed3.ll
…
fmin.ll
…
fmin3.ll AMDGPU: Try to eliminate clearing of high bits of 16-bit instructions 2021-06-22 13:42:49 -04:00
fmin_fmax_legacy.amdgcn.ll [NFC] Removed unused prefixes in test/CodeGen/AMDGPU 2021-01-05 19:18:30 -08:00
fmin_legacy.f16.ll [AMDGPU] Switch PostRA sched to MachineSched 2021-09-14 15:11:27 -04:00
fmin_legacy.f64.ll [AMDGPU] Set most sched model resource's BufferSize to one 2021-12-01 22:31:28 -08:00
fmin_legacy.ll [NFC] Removed unused prefixes in test/CodeGen/AMDGPU 2021-01-05 19:18:30 -08:00
fminnum.f64.ll [AMDGPU] Set most sched model resource's BufferSize to one 2021-12-01 22:31:28 -08:00
fminnum.ll
…
fminnum.r600.ll
…
fmul-2-combine-multi-use.ll
…
fmul.f16.ll
…
fmul.ll
…
fmul64.ll
…
fmuladd.f16.ll [AMDGPU] Prefer v_fmac over v_fma only when no source modifiers are used 2021-09-21 11:57:45 +01:00
fmuladd.f32.ll [DAGCombine] reassoc flag shouldn't enable contract 2021-06-21 21:15:43 +00:00
fmuladd.f64.ll [DAGCombine] reassoc flag shouldn't enable contract 2021-06-21 21:15:43 +00:00
fmuladd.v2f16.ll [DAGCombine] reassoc flag shouldn't enable contract 2021-06-21 21:15:43 +00:00
fnearbyint.ll
…
fneg-combines.ll DAG: Fix incorrect folding of fmul -1 to fneg 2021-09-14 21:25:02 -04:00
fneg-combines.si.ll [NFC] Removed unused prefixes in test/CodeGen/AMDGPU 2021-01-05 19:18:30 -08:00
fneg-fabs-divergence-driven-isel.ll [AMDGPU] Enable fneg and fabs divergence-driven instruction selection. 2021-11-23 19:37:07 +03:00
fneg-fabs.f16.ll [AMDGPU] Switch PostRA sched to MachineSched 2021-09-14 15:11:27 -04:00
fneg-fabs.f64.ll [AMDGPU] Enable fneg and fabs divergence-driven instruction selection. 2021-11-23 19:37:07 +03:00
fneg-fabs.ll [NFC] Removed unused prefixes in test/CodeGen/AMDGPU 2021-01-05 19:18:30 -08:00
fneg-fold-legalize-dag-increase-insts.ll [AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts 2021-04-26 17:21:49 -04:00
fneg.f16.ll AMDGPU: Select global saddr mode from SGPR pointer 2020-11-16 11:51:06 -05:00
fneg.f64.ll [AMDGPU] Enable fneg and fabs divergence-driven instruction selection. 2021-11-23 19:37:07 +03:00
fneg.ll
…
fold-cndmask-wave32.mir [AMDGPU] SIFoldOperands: eagerly delete dead copies 2021-04-09 13:52:54 +01:00
fold-cndmask.mir [AMDGPU] SIFoldOperands: eagerly delete dead copies 2021-04-09 13:52:54 +01:00
fold-fi-mubuf.mir [AMDGPU] Use single cache policy operand 2021-03-15 13:00:59 -07:00
fold-fi-operand-shrink.mir
…
fold-fmul-to-neg-abs.ll
…
fold-imm-copy.mir [AMDGPU] Fix typo in regular expression checks. NFC. 2021-04-06 12:29:48 +01:00
fold-imm-f16-f32.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
fold-immediate-operand-shrink-with-carry.mir
…
fold-immediate-operand-shrink.mir
…
fold-immediate-output-mods.mir [AMDGPU] Use single cache policy operand 2021-03-15 13:00:59 -07:00
fold-implicit-operand.mir
…
fold-multiple.mir [AMDGPU] Use single cache policy operand 2021-03-15 13:00:59 -07:00
fold-operands-order.mir [AMDGPU] SIFoldOperands: eagerly delete dead copies 2021-04-09 13:52:54 +01:00
fold-operands-remove-m0-redef.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
fold-over-exec.mir
…
fold-readlane.mir [GlobalISel] Allow DBG_VALUE to use undefined vregs before LiveDebugValues. 2021-12-05 15:55:59 -05:00
fold-reload-into-exec.mir [AMDGPU] Save all lanes for reserved VGPRs 2021-02-04 09:56:36 +01:00
fold-reload-into-m0.mir [AMDGPU] Save all lanes for reserved VGPRs 2021-02-04 09:56:36 +01:00
fold-sgpr-copy.mir [AMDGPU] Use single cache policy operand 2021-03-15 13:00:59 -07:00
fold-sgpr-multi-imm.mir
…
fold-vgpr-copy.mir [AMDGPU] Add _e64 suffix to VOP3 Insts 2021-01-12 18:33:18 -05:00
fold_16bit_imm.mir [AMDGPU] Add _e64 suffix to VOP3 Insts 2021-01-12 18:33:18 -05:00
fold_acc_copy_into_valu.mir
…
force-alwaysinline-lds-global-address-codegen.ll [AMDGPU] Disable forceful inline of non-kernel functions which use LDS. 2021-04-15 09:12:56 +05:30
force-alwaysinline-lds-global-address.ll [AMDGPU] Disable forceful inline of non-kernel functions which use LDS. 2021-04-15 09:12:56 +05:30
fp-atomic-to-s_denormmode.mir [AMDGPU][MC][GFX10] Corrected global_atomic_fcmpswap* 2021-11-15 12:51:12 +03:00
fp-classify.ll
…
fp-min-max-atomics.ll [GlobalISel] Rework more/fewer elements for vectors 2021-12-23 14:30:02 +01:00
fp-min-max-global-atomics-gfx10.ll [AMDGPU] Support global_atomic_fmin/max on gfx10 2021-08-25 09:35:10 -04:00
fp16_to_fp32.ll
…
fp16_to_fp64.ll
…
fp32_to_fp16.ll
…
fp64-atomics-gfx90a.ll [AMDGPU] Set most sched model resource's BufferSize to one 2021-12-01 22:31:28 -08:00
fp_to_sint.f64.ll
…
fp_to_sint.ll [AMDGPU] Set most sched model resource's BufferSize to one 2021-12-01 22:31:28 -08:00
fp_to_uint.f64.ll
…
fp_to_uint.ll [AMDGPU] Set most sched model resource's BufferSize to one 2021-12-01 22:31:28 -08:00
fpext-free.ll [DAGCombine] Allow FMA combine with both FMA and FMAD 2021-08-27 19:49:35 +09:00
fpext.f16.ll [AMDGPU] Switch PostRA sched to MachineSched 2021-09-14 15:11:27 -04:00
fpext.ll
…
fpow.ll Revert "[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range" 2021-12-22 11:39:28 -05:00
fptosi.f16.ll [AMDGPU] Set most sched model resource's BufferSize to one 2021-12-01 22:31:28 -08:00
fptoui.f16.ll [AMDGPU] Set most sched model resource's BufferSize to one 2021-12-01 22:31:28 -08:00
fptrunc.f16.ll [AMDGPU] Switch PostRA sched to MachineSched 2021-09-14 15:11:27 -04:00
fptrunc.ll
…
fract.f64.ll [NFC] Removed unused prefixes in test/CodeGen/AMDGPU 2021-01-05 19:18:30 -08:00
fract.ll [NFC] Removed unused prefixes in test/CodeGen/AMDGPU 2021-01-05 19:18:30 -08:00
frame-index-elimination.ll [AMDGPU] Set most sched model resource's BufferSize to one 2021-12-01 22:31:28 -08:00
frame-lowering-entry-all-sgpr-used.mir
…
frame-lowering-fp-adjusted.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
frame-setup-without-sgpr-to-vgpr-spills.ll Revert "[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range" 2021-12-22 11:39:28 -05:00
frem.ll [AMDGPU] Prefer fmac over fma when selecting FMA_W_CHAIN 2021-09-21 11:57:45 +01:00
fshl.ll [AMDGPU] Set most sched model resource's BufferSize to one 2021-12-01 22:31:28 -08:00
fshr.ll Revert "[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range" 2021-12-22 11:39:28 -05:00
fsqrt.f64.ll Revert "[NFC] remove explicit default value for strboolattr attribute in tests" 2021-05-24 19:43:40 +02:00
fsqrt.ll Revert "[NFC] remove explicit default value for strboolattr attribute in tests" 2021-05-24 19:43:40 +02:00
fsub.f16.ll [NFC] Removed unused prefixes in test/CodeGen/AMDGPU 2021-01-05 19:18:30 -08:00
fsub.ll
…
fsub64.ll
…
ftrunc.f64.ll
…
ftrunc.ll
…
function-args.ll AMDGPU: Enable fixed function ABI by default 2021-12-04 10:49:18 -05:00
function-call-relocs.ll
…
function-returns.ll [AMDGPU] Add 224-bit vector types and link 192-bit types to MVTs 2021-06-24 12:41:22 +09:00
fused-bitlogic.ll [AMDGPU] Expand not pattern according to the XOR node divergence 2021-12-20 14:41:38 +03:00
gds-atomic.ll
…
gep-address-space.ll
…
gfx-callable-argument-types.ll Revert "[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range" 2021-12-22 11:39:28 -05:00
gfx-callable-preserved-registers.ll Revert "[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range" 2021-12-22 11:39:28 -05:00
gfx-callable-return-types.ll Revert "[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range" 2021-12-22 11:39:28 -05:00
gfx10-vop-literal.ll [AMDGPU][MC][GFX10][GFX90A] Corrected _e32/_e64 suffices 2021-04-01 14:21:00 +03:00
gfx90a-enc.ll [AMDGPU] gfx90a support 2021-02-17 16:01:32 -08:00
gfx902-without-xnack.ll
…
global-atomics-fp-wrong-subtarget.ll AMDGPU: Restore atomic fp feature on FP atomic instruction definitions 2021-04-22 21:32:01 -04:00
global-atomics-fp.ll [AMDGPU] Do not generate ELF symbols for the local branch target labels 2021-11-20 10:32:41 +05:30
global-constant.ll [AMDGPU] Fix copying a machine operand 2021-10-11 20:22:47 +01:00
global-directive.ll
…
global-extload-i16.ll
…
global-load-saddr-to-vaddr.ll [AMDGPU] Do not generate ELF symbols for the local branch target labels 2021-11-20 10:32:41 +05:30
global-saddr-atomics.gfx908.ll [NFC] Removed unused prefixes in test/CodeGen/AMDGPU 2021-01-05 19:18:30 -08:00
global-saddr-atomics.gfx1030.ll [NFC] Removed unused prefixes in test/CodeGen/AMDGPU 2021-01-05 19:18:30 -08:00
global-saddr-atomics.ll [AMDGPU][MC][GFX10][GFX90A] Corrected _e32/_e64 suffices 2021-04-01 14:21:00 +03:00
global-saddr-load.ll [AMDGPU] Do not generate ELF symbols for the local branch target labels 2021-11-20 10:32:41 +05:30
global-saddr-store.ll [AMDGPU] Don't check for VMEM hazards on GFX10 2021-03-04 21:44:56 +00:00
global-smrd-unknown.ll [AMDGPU] Switch AnnotateUniformValues to MemorySSA 2021-05-05 18:34:41 -07:00
global-variable-relocs.ll
…
global_atomics.ll [AMDGPU] Improve global SADDR selection 2021-05-05 14:44:21 -07:00
global_atomics_i64.ll [AMDGPU] Improve global SADDR selection 2021-05-05 14:44:21 -07:00
global_smrd.ll
…
global_smrd_cfg.ll [AA] Split up LocationSize::unknown() 2020-11-26 18:39:55 +01:00
greedy-alloc-fail-sgpr1024-spill.mir AMDGPU: Add alloc priority to global ranges 2021-08-10 13:12:34 -04:00
greedy-broken-ssa-verifier-error.mir
…
greedy-global-heuristic.mir RegAllocGreedy: Account for reserved registers in num regs heuristic 2021-09-14 21:00:29 -04:00
gv-const-addrspace.ll [NFC] Removed unused prefixes in test/CodeGen/AMDGPU 2021-01-05 19:18:30 -08:00
gv-offset-folding.ll
…
gws-hazards.mir [AMDGPU] Extend gfx10 test coverage. NFC. 2021-03-29 11:13:55 +02:00
half.ll [AMDGPU] Set most sched model resource's BufferSize to one 2021-12-01 22:31:28 -08:00
hard-clauses.mir [AMDGPU] Ignore KILLs when forming clauses 2021-09-27 16:33:52 +02:00
hazard-buffer-store-v-interp.mir [AMDGPU] Use single cache policy operand 2021-03-15 13:00:59 -07:00
hazard-hidden-bundle.mir [AMDGPU] Use single cache policy operand 2021-03-15 13:00:59 -07:00
hazard-in-bundle.mir [AMDGPU] Use single cache policy operand 2021-03-15 13:00:59 -07:00
hazard-inlineasm.mir [AMDGPU] Use single cache policy operand 2021-03-15 13:00:59 -07:00
hazard-kill.mir [AMDGPU] Use single cache policy operand 2021-03-15 13:00:59 -07:00
hazard-pass-ordering.mir [AMDGPU] Use single cache policy operand 2021-03-15 13:00:59 -07:00
hazard-pseudo-machineinstrs.mir [AMDGPU] Skip pseudo MIs in hazard recognizer 2021-08-16 23:11:14 -04:00
hazard-recognizer-meta-insts.mir [AMDGPU] Use single cache policy operand 2021-03-15 13:00:59 -07:00
hazard.mir [AMDGPU] Skip pseudo MIs in hazard recognizer 2021-08-16 23:11:14 -04:00
high-bits-zeroed-16-bit-ops.mir [AMDGPU] Improve zeroesHigh16BitsOfDest for GFX9 legacy opcodes 2021-12-15 13:14:48 +00:00
hip.extern.shared.array.ll [AMDGPU] Inline non-kernel functions using extern lds 2021-09-16 10:58:51 -07:00
hoist-cond.ll [AMDGPU] Fix dubious regexes with unescaped brackets. NFC. 2021-04-06 13:17:41 +01:00
hsa-default-device.ll
…
hsa-fp-mode.ll
…
hsa-func-align.ll
…
hsa-func.ll
…
hsa-globals.ll
…
hsa-group-segment.ll
…
hsa-metadata-deduce-ro-arg-v3.ll
…
hsa-metadata-deduce-ro-arg.ll
…
hsa-metadata-enqueue-kernel-v3.ll AMDGPU: Optimize out implicit kernarg argument allocation if unused 2021-12-04 10:38:25 -05:00
hsa-metadata-enqueue-kernel.ll AMDGPU: Optimize out implicit kernarg argument allocation if unused 2021-12-04 10:38:25 -05:00
hsa-metadata-from-llvm-ctor-dtor-list.ll [AMDGPU] Handle functions in llvm's global ctors and dtors list 2021-08-06 15:53:33 +05:30
hsa-metadata-from-llvm-ir-full-v3.ll AMDGPU: Optimize out implicit kernarg argument allocation if unused 2021-12-04 10:38:25 -05:00
hsa-metadata-from-llvm-ir-full.ll AMDGPU: Optimize out implicit kernarg argument allocation if unused 2021-12-04 10:38:25 -05:00
hsa-metadata-hidden-args-v3.ll AMDGPU: Optimize out implicit kernarg argument allocation if unused 2021-12-04 10:38:25 -05:00
hsa-metadata-hidden-args.ll AMDGPU: Optimize out implicit kernarg argument allocation if unused 2021-12-04 10:38:25 -05:00
hsa-metadata-hostcall-absent-v3.ll AMDGPU: Optimize out implicit kernarg argument allocation if unused 2021-12-04 10:38:25 -05:00
hsa-metadata-hostcall-absent.ll AMDGPU: Optimize out implicit kernarg argument allocation if unused 2021-12-04 10:38:25 -05:00
hsa-metadata-hostcall-present-v3-asan.ll Emit hidden hostcall argument for sanitized kernels 2021-11-10 17:05:57 -05:00
hsa-metadata-hostcall-present-v3.ll AMDGPU: Optimize out implicit kernarg argument allocation if unused 2021-12-04 10:38:25 -05:00
hsa-metadata-hostcall-present.ll AMDGPU: Optimize out implicit kernarg argument allocation if unused 2021-12-04 10:38:25 -05:00
hsa-metadata-images-v3.ll AMDGPU: Add target id and code object v4 support 2021-03-24 11:54:05 -04:00
hsa-metadata-images.ll [NFC] Removed unused prefixes in CodeGen/AMDGPU 2021-01-05 20:22:40 -08:00
hsa-metadata-invalid-ocl-version-1-v3.ll AMDGPU: Add target id and code object v4 support 2021-03-24 11:54:05 -04:00
hsa-metadata-invalid-ocl-version-1.ll
…
hsa-metadata-invalid-ocl-version-2-v3.ll AMDGPU: Add target id and code object v4 support 2021-03-24 11:54:05 -04:00
hsa-metadata-invalid-ocl-version-2.ll
…
hsa-metadata-invalid-ocl-version-3-v3.ll AMDGPU: Add target id and code object v4 support 2021-03-24 11:54:05 -04:00
hsa-metadata-invalid-ocl-version-3.ll
…
hsa-metadata-kernel-code-props-v3.ll [test] Avoid llvm-readelf/llvm-readobj one-dash long options and deprecated aliases (e.g. --file-headers) 2021-07-15 10:26:21 -07:00
hsa-metadata-kernel-code-props.ll [AMDGPU] Add 224-bit vector types and link 192-bit types to MVTs 2021-06-24 12:41:22 +09:00
hsa-metadata-wavefrontsize.ll AMDGPU: Add target id and code object v4 support 2021-03-24 11:54:05 -04:00
hsa-note-no-func.ll AMDGPU: Add target id and code object v4 support 2021-03-24 11:54:05 -04:00
hsa.ll [test] Change -t to --syms and -s to -S for llvm-readobj RUN lines 2021-06-29 11:50:31 -07:00
huge-number-operand-folds.mir [AMDGPU] SIFoldOperands: eagerly delete dead copies 2021-04-09 13:52:54 +01:00
huge-private-buffer.ll
…
i1-copies-rpo.mir [AMDGPU] Fix inconsistent ---/... in MIR tests and regenerate checks 2021-04-30 14:10:50 +01:00
i1-copy-from-loop.ll [AMDGPU] Do not generate ELF symbols for the local branch target labels 2021-11-20 10:32:41 +05:30
i1-copy-implicit-def.ll
…
i1-copy-phi-uniform-branch.ll [AMDGPU] Do not generate ELF symbols for the local branch target labels 2021-11-20 10:32:41 +05:30
i1-copy-phi.ll
…
i1_copy_phi_with_phi_incoming_value.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
i8-to-double-to-float.ll
…
icmp-select-sete-reverse-args.ll
…
icmp.i16.ll
…
icmp64.ll [AMDGPU] Divergence-driven compare operations instruction selection 2021-08-25 18:30:49 +03:00
idiv-licm.ll [AMDGPU] Do not generate ELF symbols for the local branch target labels 2021-11-20 10:32:41 +05:30
idot2.ll [AMDGPU] Set most sched model resource's BufferSize to one 2021-12-01 22:31:28 -08:00
idot4s.ll [AMDGPU] Set most sched model resource's BufferSize to one 2021-12-01 22:31:28 -08:00
idot4u.ll [AMDGPU] Set most sched model resource's BufferSize to one 2021-12-01 22:31:28 -08:00
idot8s.ll [AMDGPU] Select build_vector DAG nodes according to the divergence 2021-12-23 02:27:12 +03:00
idot8u.ll [AMDGPU] Set most sched model resource's BufferSize to one 2021-12-01 22:31:28 -08:00
illegal-sgpr-to-vgpr-copy.ll
…
image-attributes.ll
…
image-load-d16-tfe.ll [AMDGPU] Add volatile support to SIMemoryLegalizer 2021-01-09 00:52:33 +00:00
image-resource-id.ll
…
image-sample-waterfall.ll [AMDGPU] Do not generate ELF symbols for the local branch target labels 2021-11-20 10:32:41 +05:30
image-schedule.ll
…
image_ls_mipmap_zero.ll
…
img-nouse-adjust.ll
…
imm.ll [AMDGPU] Set most sched model resource's BufferSize to one 2021-12-01 22:31:28 -08:00
imm16.ll [AMDGPU] Set most sched model resource's BufferSize to one 2021-12-01 22:31:28 -08:00
immv216.ll [AMDGPU] Set most sched model resource's BufferSize to one 2021-12-01 22:31:28 -08:00
implicit-def-muse.ll
…
indirect-addressing-si-gfx9.ll AMDGPU: Fix assert on m0_lo16/m0_hi16 2021-06-18 18:48:53 -04:00
indirect-addressing-si-noopt.ll [AMDGPU] Do not generate ELF symbols for the local branch target labels 2021-11-20 10:32:41 +05:30
indirect-addressing-si-pregfx9.ll [NFC] Removed unused prefixes in CodeGen/AMDGPU 2021-01-05 20:22:40 -08:00
indirect-addressing-si.ll [AMDGPU] Do not generate ELF symbols for the local branch target labels 2021-11-20 10:32:41 +05:30
indirect-addressing-term.ll CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
indirect-call-known-callees.ll AMDGPU: Enable fixed function ABI by default 2021-12-04 10:49:18 -05:00
indirect-call.ll Revert "[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range" 2021-12-22 11:39:28 -05:00
indirect-private-64.ll [NFC] Removed unused prefixes in CodeGen/AMDGPU 2021-01-05 20:22:40 -08:00
infer-addrpace-pipeline.ll [NewPM] Port infer-address-spaces 2020-12-28 19:58:12 -08:00
infer-uniform-load-shader.ll
…
infinite-loop-evergreen.ll
…
infinite-loop.ll [AMDGPU] Do not generate ELF symbols for the local branch target labels 2021-11-20 10:32:41 +05:30
inline-asm.i128.ll Revert "[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range" 2021-12-22 11:39:28 -05:00
inline-asm.ll [AMDGPU] Only select VOP3 forms of VOP2 instructions 2021-11-24 11:15:30 +00:00
inline-attr.ll Reapply [IR] Don't mark mustprogress as type attribute 2021-07-09 20:57:44 +02:00
inline-calls.ll [HIP] [AlwaysInliner] Disable AlwaysInliner to eliminate undefined symbols 2021-10-18 16:53:15 -06:00
inline-constraints.ll [AMDGPU] Add S_MOV_B64_IMM_PSEUDO for wide constants 2021-06-30 11:45:38 -07:00
inline-maxbb.ll [AMDGPU][Inliner] Remove amdgpu-inline and add a new TTI inline hook 2021-01-21 20:29:17 -08:00
inlineasm-16.ll
…
inlineasm-illegal-type.ll
…
inlineasm-packed.ll [NFC] Removed unused prefixes in CodeGen/AMDGPU 2021-01-05 20:22:40 -08:00
input-mods.ll
…
insert-branch-w32.mir [AMDGPU] Stop adding an implicit def of vcc_hi for wave32 2020-12-02 10:11:42 +00:00
insert-skip-from-vcc.mir
…
insert-skips-flat-vmem-ds.mir [AMDGPU] Merge SIRemoveShortExecBranches into SIPreEmitPeephole 2021-03-20 11:26:42 +09:00
insert-skips-gws.mir [AMDGPU] Merge SIRemoveShortExecBranches into SIPreEmitPeephole 2021-03-20 11:26:42 +09:00
insert-skips-ignored-insts.mir [AMDGPU] Merge SIRemoveShortExecBranches into SIPreEmitPeephole 2021-03-20 11:26:42 +09:00
insert-subvector-unused-scratch.ll [AMDGPU] Set most sched model resource's BufferSize to one 2021-12-01 22:31:28 -08:00
insert-waitcnts-callee.mir
…
insert-waitcnts-exp.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
insert_subreg.ll
…
insert_vector_dynelt.ll [AMDGPU] Set most sched model resource's BufferSize to one 2021-12-01 22:31:28 -08:00
insert_vector_elt.ll [AMDGPU] Set most sched model resource's BufferSize to one 2021-12-01 22:31:28 -08:00
insert_vector_elt.v2i16.ll [AMDGPU] Set most sched model resource's BufferSize to one 2021-12-01 22:31:28 -08:00
insert_vector_elt.v2i16.subtest-nosaddr.ll [NFC] Removed unused prefixes in CodeGen/AMDGPU 2021-01-05 20:22:40 -08:00
insert_vector_elt.v2i16.subtest-saddr.ll [NFC] Removed unused prefixes in CodeGen/AMDGPU 2021-01-05 20:22:40 -08:00
inserted-wait-states.mir [AMDGPU] Use single cache policy operand 2021-03-15 13:00:59 -07:00
internalize.ll [NewPM][AMDGPU] Run InternalizePass when -amdgpu-internalize-symbols 2021-01-04 11:34:40 -08:00
invalid-addrspacecast.ll
…
invariant-load-no-alias-store.ll
…
invert-br-undef-vcc.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
ipra-regmask.ll [AMDGPU] Add 224-bit vector types and link 192-bit types to MVTs 2021-06-24 12:41:22 +09:00
ipra.ll Revert "[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range" 2021-12-22 11:39:28 -05:00
jump-address.ll
…
kcache-fold.ll
…
kernarg-size.ll AMDGPU: Add target id and code object v4 support 2021-03-24 11:54:05 -04:00
kernarg-stack-alignment.ll
…
kernel-args.ll [AMDGPU] Set most sched model resource's BufferSize to one 2021-12-01 22:31:28 -08:00
kernel-argument-dag-lowering.ll [AMDGPU] Set most sched model resource's BufferSize to one 2021-12-01 22:31:28 -08:00
kill-infinite-loop.ll [AMDGPU] Do not generate ELF symbols for the local branch target labels 2021-11-20 10:32:41 +05:30
known-never-nan.ll
…
known-never-snan.ll [FPEnv][AMDGPU] Disable FSUB(-0,X)->FNEG(X) DAGCombine when subnormals are flushed 2021-01-04 14:44:10 -06:00
knownbits-recursion.ll
…
large-alloca-compute.ll [AMDGPU] Init scratch only if necessary 2021-07-14 10:45:22 +02:00
large-alloca-graphics.ll
…
large-constant-initializer.ll
…
large-work-group-promote-alloca.ll AMDGPU: Fix test relying on incompatible attributes 2021-09-21 22:44:35 -04:00
lcssa-optnone.ll
…
lds-alignment.ll [AMDGPU] Increase alignment of LDS globals if necessary before LDS lowering. 2021-06-07 18:00:41 +05:30
lds-atomic-fadd.ll [AMDGPU] Enable ds_min/ds_max on more subtargets 2021-08-31 13:22:31 -04:00
lds-atomic-fmin-fmax.ll [GlobalISel] Rework more/fewer elements for vectors 2021-12-23 14:30:02 +01:00
lds-bounds.ll
…
lds-branch-vmem-hazard.mir [AMDGPU] Use single cache policy operand 2021-03-15 13:00:59 -07:00
lds-global-non-entry-func.ll AMDGPU: Enable fixed function ABI by default 2021-12-04 10:49:18 -05:00
lds-initializer.ll [Diagnose] Unify MCContext and LLVMContext diagnosing 2021-03-01 15:58:37 -08:00
lds-m0-init-in-loop.ll [AMDGPU] Do not generate ELF symbols for the local branch target labels 2021-11-20 10:32:41 +05:30
lds-misaligned-bug.ll [AMDGPU] Only use ds_read/write_b128 for alignment >= 16 2021-04-08 08:12:05 +05:30
lds-oqap-crash.ll
…
lds-output-queue.ll
…
lds-relocs.ll [test] Change -t to --syms and -s to -S for llvm-readobj RUN lines 2021-06-29 11:50:31 -07:00
lds-size.ll
…
lds-zero-initializer.ll [AMDGPU] Legalize initialized LDS variables 2021-09-23 22:53:20 -04:00
legalize-fp-load-invariant.ll CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
legalizedag-bug-expand-setcc.ll
…
licm-regpressure.mir Prevent machine licm if remattable with a vreg use 2021-08-16 12:09:00 -07:00
limit-coalesce.mir [AMDGPU] Use single cache policy operand 2021-03-15 13:00:59 -07:00
limit-soft-clause-reg-pressure.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
lit.local.cfg [NFC] Disallow unused prefixes under llvm/test/CodeGen 2021-01-11 12:32:18 -08:00
literals.ll
…
liveness.mir
…
llc-pipeline.ll [NFC][regalloc] Introduce the RegAllocEvictionAdvisorAnalysis 2021-12-16 17:56:46 -08:00
llvm.amdgcn.alignb.ll
…
llvm.amdgcn.atomic.csub.ll AMDGPU: Select global saddr mode from SGPR pointer 2020-11-16 11:51:06 -05:00
llvm.amdgcn.atomic.dec.ll [AMDGPU] Fix flags of V_MOV_B64_PSEUDO 2021-07-09 12:49:28 -07:00
llvm.amdgcn.atomic.fadd.gfx90a.ll [AMDGPU] gfx90a support 2021-02-17 16:01:32 -08:00
llvm.amdgcn.atomic.fadd.ll [AMDGPU] gfx90a support 2021-02-17 16:01:32 -08:00
llvm.amdgcn.atomic.inc.ll [Tests] Fix incorrect noalias metadata 2021-09-18 20:51:00 +02:00
llvm.amdgcn.ballot.i32.ll [AMDGPU] Stop adding an implicit def of vcc_hi for wave32 2020-12-02 10:11:42 +00:00
llvm.amdgcn.ballot.i64.ll
…
llvm.amdgcn.buffer.atomic.ll
…
llvm.amdgcn.buffer.load.dwordx3.ll
…
llvm.amdgcn.buffer.load.format.d16.ll
…
llvm.amdgcn.buffer.load.format.ll
…
llvm.amdgcn.buffer.load.ll [AMDGPU] Use divergent addresses for vector loads 2021-02-23 13:33:15 +00:00
llvm.amdgcn.buffer.store.dwordx3.ll
…
llvm.amdgcn.buffer.store.format.d16.ll [NFC] Removed unused prefixes from CodeGen/AMDGPU 2021-01-06 09:34:11 -08:00
llvm.amdgcn.buffer.store.format.ll AMDGPU: Explicitly use SelectionDAG in legacy intrinsic tests 2021-01-06 11:37:00 -05:00
llvm.amdgcn.buffer.store.ll
…
llvm.amdgcn.buffer.wbinvl1.ll
…
llvm.amdgcn.buffer.wbinvl1.sc.ll
…
llvm.amdgcn.buffer.wbinvl1.vol.ll
…
llvm.amdgcn.class.f16.ll [AMDGPU] Set most sched model resource's BufferSize to one 2021-12-01 22:31:28 -08:00
llvm.amdgcn.class.ll
…
llvm.amdgcn.cos.f16.ll
…
llvm.amdgcn.cos.ll [NFC] Removed unused prefixes from CodeGen/AMDGPU 2021-01-06 09:34:11 -08:00
llvm.amdgcn.cubeid.ll [NFC] Removed unused prefixes from CodeGen/AMDGPU 2021-01-06 09:34:11 -08:00
llvm.amdgcn.cubema.ll [NFC] Removed unused prefixes from CodeGen/AMDGPU 2021-01-06 09:34:11 -08:00
llvm.amdgcn.cubesc.ll [NFC] Removed unused prefixes from CodeGen/AMDGPU 2021-01-06 09:34:11 -08:00
llvm.amdgcn.cubetc.ll [NFC] Removed unused prefixes from CodeGen/AMDGPU 2021-01-06 09:34:11 -08:00
llvm.amdgcn.cvt.pk.i16.ll
…
llvm.amdgcn.cvt.pk.u16.ll
…
llvm.amdgcn.cvt.pknorm.i16.ll
…
llvm.amdgcn.cvt.pknorm.u16.ll
…
llvm.amdgcn.cvt.pkrtz.ll [AMDGPU] Set most sched model resource's BufferSize to one 2021-12-01 22:31:28 -08:00
llvm.amdgcn.dispatch.id.ll
…
llvm.amdgcn.dispatch.ptr.ll
…
llvm.amdgcn.div.fixup.f16.ll
…
llvm.amdgcn.div.fixup.ll
…
llvm.amdgcn.div.fmas.ll [AMDGPU] Use S_BITCMP1_* to replace AND in optimizeCompareInstr 2021-09-01 15:59:12 -07:00
llvm.amdgcn.div.scale.ll
…
llvm.amdgcn.ds.append.ll
…
llvm.amdgcn.ds.bpermute.ll
…
llvm.amdgcn.ds.consume.ll
…
llvm.amdgcn.ds.gws.barrier-fastregalloc.ll CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
llvm.amdgcn.ds.gws.barrier.ll [AMDGPU] Do not generate ELF symbols for the local branch target labels 2021-11-20 10:32:41 +05:30
llvm.amdgcn.ds.gws.init.ll [AMDGPU] Do not generate ELF symbols for the local branch target labels 2021-11-20 10:32:41 +05:30
llvm.amdgcn.ds.gws.sema.br.ll [AMDGPU] Do not generate ELF symbols for the local branch target labels 2021-11-20 10:32:41 +05:30
llvm.amdgcn.ds.gws.sema.p.ll [AMDGPU] Do not generate ELF symbols for the local branch target labels 2021-11-20 10:32:41 +05:30
llvm.amdgcn.ds.gws.sema.release.all.ll [AMDGPU] Do not generate ELF symbols for the local branch target labels 2021-11-20 10:32:41 +05:30
llvm.amdgcn.ds.gws.sema.v.ll [AMDGPU] Do not generate ELF symbols for the local branch target labels 2021-11-20 10:32:41 +05:30
llvm.amdgcn.ds.ordered.add.gfx10.ll
…
llvm.amdgcn.ds.ordered.add.ll
…
llvm.amdgcn.ds.ordered.swap.ll [AMDGPU] Do not generate ELF symbols for the local branch target labels 2021-11-20 10:32:41 +05:30
llvm.amdgcn.ds.permute.ll
…
llvm.amdgcn.ds.swizzle.ll
…
llvm.amdgcn.exp.compr.ll
…
llvm.amdgcn.exp.ll [AMDGPU] Fix scheduling of exp pos4 2020-11-12 19:57:14 +00:00
llvm.amdgcn.exp.prim.ll
…
llvm.amdgcn.fcmp.ll
…
llvm.amdgcn.fdiv.fast.ll
…
llvm.amdgcn.fdot2.ll
…
llvm.amdgcn.fma.legacy.ll [AMDGPU] Add tests for legacy multiply-add with immediate 2021-11-01 14:24:13 +00:00
llvm.amdgcn.fmad.ftz.f16.ll
…
llvm.amdgcn.fmad.ftz.ll [AMDGPU] Set most sched model resource's BufferSize to one 2021-12-01 22:31:28 -08:00
llvm.amdgcn.fmed3.f16.ll
…
llvm.amdgcn.fmed3.ll
…
llvm.amdgcn.fmul.legacy.ll [AMDGPU] Add tests for legacy multiply-add with immediate 2021-11-01 14:24:13 +00:00
llvm.amdgcn.fract.f16.ll
…
llvm.amdgcn.fract.ll [NFC] Removed unused prefixes from CodeGen/AMDGPU 2021-01-06 09:34:11 -08:00
llvm.amdgcn.frexp.exp.f16.ll AMDGPU: Try to eliminate clearing of high bits of 16-bit instructions 2021-06-22 13:42:49 -04:00
llvm.amdgcn.frexp.exp.ll
…
llvm.amdgcn.frexp.mant.f16.ll
…
llvm.amdgcn.frexp.mant.ll
…
llvm.amdgcn.groupstaticsize.ll
…
llvm.amdgcn.icmp.ll [AMDGPU] Divergence-driven compare operations instruction selection 2021-08-25 18:30:49 +03:00
llvm.amdgcn.image.a16.dim.ll [AMDGPU] Stop adding an implicit def of vcc_hi for wave32 2020-12-02 10:11:42 +00:00
llvm.amdgcn.image.a16.encode.ll [AMDGPU] Stop adding an implicit def of vcc_hi for wave32 2020-12-02 10:11:42 +00:00
llvm.amdgcn.image.atomic.dim.ll [AMDGPU] gfx90a support 2021-02-17 16:01:32 -08:00
llvm.amdgcn.image.d16.dim.ll [NFC] Removed unused prefixes from CodeGen/AMDGPU 2021-01-06 09:34:11 -08:00
llvm.amdgcn.image.dim.gfx90a.ll AMDGPU: Remove special case in shouldCoalesce 2021-02-24 14:49:44 -05:00
llvm.amdgcn.image.dim.ll [AMDGPU] Set most sched model resource's BufferSize to one 2021-12-01 22:31:28 -08:00
llvm.amdgcn.image.gather4.a16.dim.ll [AMDGPU] Fixes in ISelDAG path and GlobalISel path for 'bias' operand with A16 bit on 2021-12-17 16:11:51 +05:30
llvm.amdgcn.image.gather4.d16.dim.ll [NFC] Removed unused prefixes from CodeGen/AMDGPU 2021-01-06 09:34:11 -08:00
llvm.amdgcn.image.gather4.dim.ll [AMDGPU] Add v5f32/VReg_160 support for MIMG instructions 2021-06-08 11:11:40 +09:00
llvm.amdgcn.image.gather4.o.dim.ll [AMDGPU] Add VReg_192/VReg_224 support for MIMG instructions 2021-07-22 10:42:15 +09:00
llvm.amdgcn.image.getlod.dim.ll
…
llvm.amdgcn.image.load.a16.d16.ll
…
llvm.amdgcn.image.load.a16.ll
…
llvm.amdgcn.image.msaa.load.x.ll [AMDGPU] Restrict image_msaa_load to MSAA dimension types 2021-03-12 09:47:24 +09:00
llvm.amdgcn.image.nsa.ll [AMDGPU] Add maximum NSA size limit ISA feature 2021-07-23 16:16:06 +09:00
llvm.amdgcn.image.sample.a16.dim.ll [AMDGPU] Fixes in ISelDAG path and GlobalISel path for 'bias' operand with A16 bit on 2021-12-17 16:11:51 +05:30
llvm.amdgcn.image.sample.d16.dim.ll [AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts 2021-04-26 17:21:49 -04:00
llvm.amdgcn.image.sample.dim.gfx90a.ll [AMDGPU] gfx90a support 2021-02-17 16:01:32 -08:00
llvm.amdgcn.image.sample.dim.ll [AMDGPU] Set most sched model resource's BufferSize to one 2021-12-01 22:31:28 -08:00
llvm.amdgcn.image.sample.g16.a16.dim.ll [AMDGPU] Switch PostRA sched to MachineSched 2021-09-14 15:11:27 -04:00
llvm.amdgcn.image.sample.g16.encode.ll [AMDGPU] Add maximum NSA size limit ISA feature 2021-07-23 16:16:06 +09:00
llvm.amdgcn.image.sample.g16.ll [AMDGPU] Add maximum NSA size limit ISA feature 2021-07-23 16:16:06 +09:00
llvm.amdgcn.image.sample.ltolz.ll
…
llvm.amdgcn.image.sample.o.dim.ll [AMDGPU] Add VReg_192/VReg_224 support for MIMG instructions 2021-07-22 10:42:15 +09:00
llvm.amdgcn.image.store.a16.d16.ll [AMDGPU] Stop adding an implicit def of vcc_hi for wave32 2020-12-02 10:11:42 +00:00
llvm.amdgcn.image.store.a16.ll [AMDGPU] Stop adding an implicit def of vcc_hi for wave32 2020-12-02 10:11:42 +00:00
llvm.amdgcn.implicit.buffer.ptr.hsa.ll
…
llvm.amdgcn.implicit.buffer.ptr.ll
…
llvm.amdgcn.implicitarg.ptr.ll Revert "[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range" 2021-12-22 11:39:28 -05:00
llvm.amdgcn.init.exec.ll [AMDGPU] Fix llvm.amdgcn.init.exec and frame materialization 2021-01-25 08:31:17 +09:00
llvm.amdgcn.init.exec.wave32.ll [AMDGPU] Add some more GFX10 test coverage 2021-12-03 14:03:31 +00:00
llvm.amdgcn.interp.f16.ll
…
llvm.amdgcn.interp.ll [NFC] Removed unused prefixes from CodeGen/AMDGPU 2021-01-06 09:34:11 -08:00
llvm.amdgcn.intersect_ray.ll [AMDGPU] Change llvm.amdgcn.image.bvh.intersect.ray to take vec3 args 2021-12-04 10:32:11 +00:00
llvm.amdgcn.is.private.ll [AMDGPU] Divergence-driven compare operations instruction selection 2021-08-25 18:30:49 +03:00
llvm.amdgcn.is.shared.ll [AMDGPU] Divergence-driven compare operations instruction selection 2021-08-25 18:30:49 +03:00
llvm.amdgcn.kernarg.segment.ptr.ll AMDGPU: Assume all amdhsa kernarg passed implicit arguments by default 2021-12-04 10:38:25 -05:00
llvm.amdgcn.kill.ll [AMDGPU] Divergence-driven compare operations instruction selection 2021-08-25 18:30:49 +03:00
llvm.amdgcn.ldexp.f16.ll
…
llvm.amdgcn.ldexp.ll
…
llvm.amdgcn.lerp.ll
…
llvm.amdgcn.log.clamp.ll [NFC] Removed unused prefixes from CodeGen/AMDGPU 2021-01-06 09:34:11 -08:00
llvm.amdgcn.mbcnt.ll
…
llvm.amdgcn.mfma.bf16.ll [AMDGPU] gfx90a support 2021-02-17 16:01:32 -08:00
llvm.amdgcn.mfma.gfx90a.ll [AMDGPU] Fix typo in regular expression checks. NFC. 2021-04-06 12:29:48 +01:00
llvm.amdgcn.mfma.i8.ll [AMDGPU] gfx90a support 2021-02-17 16:01:32 -08:00
llvm.amdgcn.mfma.ll [AMDGPU] Propagate defining src reg for AGPR to AGPR Copys 2021-09-23 15:17:53 -07:00
llvm.amdgcn.mov.dpp.ll [AMDGPU][MC] Corrected bound_ctrl for compatibility with sp3 2021-02-22 14:59:40 +03:00
llvm.amdgcn.mov.dpp8.ll
…
llvm.amdgcn.mqsad.pk.u16.u8.ll
…
llvm.amdgcn.mqsad.u32.u8.ll
…
llvm.amdgcn.msad.u8.ll
…
llvm.amdgcn.mul.i24.ll
…
llvm.amdgcn.mul.u24.ll
…
llvm.amdgcn.mulhi.i24.ll [AMDGPU] Implement llvm.amdgcn.mulhi.[i,u]24 intrinsics. 2021-10-26 18:53:07 +05:30
llvm.amdgcn.mulhi.u24.ll [AMDGPU] Implement llvm.amdgcn.mulhi.[i,u]24 intrinsics. 2021-10-26 18:53:07 +05:30
llvm.amdgcn.perm.ll [AMDGPU] Expose __builtin_amdgcn_perm for v_perm_b32 2021-05-06 16:17:33 -07:00
llvm.amdgcn.permlane.ll
…
llvm.amdgcn.ps.live.ll [AMDGPU] Added -mcpu=tahiti to 3 tests. NFC. 2021-01-25 15:50:59 -08:00
llvm.amdgcn.qsad.pk.u16.u8.ll
…
llvm.amdgcn.queue.ptr.ll
…
llvm.amdgcn.raw.buffer.atomic.fadd.ll
…
llvm.amdgcn.raw.buffer.atomic.ll [NFC] Removed unused prefixes from CodeGen/AMDGPU 2021-01-06 09:34:11 -08:00
llvm.amdgcn.raw.buffer.load.format.d16.ll
…
llvm.amdgcn.raw.buffer.load.format.ll [NFC] Removed unused prefixes from CodeGen/AMDGPU 2021-01-06 09:34:11 -08:00
llvm.amdgcn.raw.buffer.load.ll [NFC] Removed unused prefixes from CodeGen/AMDGPU 2021-01-06 09:34:11 -08:00
llvm.amdgcn.raw.buffer.store.format.d16.ll [NFC] Removed unused prefixes from CodeGen/AMDGPU 2021-01-06 09:34:11 -08:00
llvm.amdgcn.raw.buffer.store.format.ll
…
llvm.amdgcn.raw.buffer.store.ll
…
llvm.amdgcn.raw.tbuffer.load.d16.ll
…
llvm.amdgcn.raw.tbuffer.load.ll [AMDGPU] Set most sched model resource's BufferSize to one 2021-12-01 22:31:28 -08:00
llvm.amdgcn.raw.tbuffer.store.d16.ll
…
llvm.amdgcn.raw.tbuffer.store.ll [NFC] Removed unused prefixes from CodeGen/AMDGPU 2021-01-06 09:34:11 -08:00
llvm.amdgcn.rcp.f16.ll
…
llvm.amdgcn.rcp.legacy.ll
…
llvm.amdgcn.rcp.ll AMDGPU: Remove v_rsq_f64 patterns 2021-01-21 10:51:36 -05:00
llvm.amdgcn.readfirstlane.ll
…
llvm.amdgcn.readlane.ll
…
llvm.amdgcn.rsq.clamp.ll [AMDGPU] Fix typo in regular expression checks. NFC. 2021-04-06 12:29:48 +01:00
llvm.amdgcn.rsq.f16.ll
…
llvm.amdgcn.rsq.legacy.ll
…
llvm.amdgcn.rsq.ll
…
llvm.amdgcn.s.barrier.ll [AMDGPU] Update subtarget features for new target ID support 2021-01-26 11:25:51 -08:00
llvm.amdgcn.s.buffer.load.ll
…
llvm.amdgcn.s.dcache.inv.ll
…
llvm.amdgcn.s.dcache.inv.vol.ll
…
llvm.amdgcn.s.dcache.wb.ll
…
llvm.amdgcn.s.dcache.wb.vol.ll
…
llvm.amdgcn.s.decperflevel.ll
…
llvm.amdgcn.s.get.waveid.in.workgroup.ll AMDGPU: Select global saddr mode from SGPR pointer 2020-11-16 11:51:06 -05:00
llvm.amdgcn.s.getpc.ll
…
llvm.amdgcn.s.getreg.ll
…
llvm.amdgcn.s.incperflevel.ll
…
llvm.amdgcn.s.memrealtime.ll [NFC] Removed unused prefixes from CodeGen/AMDGPU 2021-01-06 09:34:11 -08:00
llvm.amdgcn.s.memtime.ll Revert "Revert "[AMDGPU] Restore the s_memtime instruction in gfx1030"" 2021-03-06 09:00:01 +00:00
llvm.amdgcn.s.sethalt.ll [AMDGPU] New intrinsic void llvm.amdgcn.s.sethalt(i32) 2021-03-01 14:30:23 +00:00
llvm.amdgcn.s.setreg.ll [AMDGPU] Stop adding an implicit def of vcc_hi for wave32 2020-12-02 10:11:42 +00:00
llvm.amdgcn.s.sleep.ll
…
llvm.amdgcn.s.waitcnt.ll
…
llvm.amdgcn.sad.hi.u8.ll
…
llvm.amdgcn.sad.u8.ll
…
llvm.amdgcn.sad.u16.ll
…
llvm.amdgcn.sbfe.ll [NFC] Removed unused prefixes from CodeGen/AMDGPU 2021-01-06 09:34:11 -08:00
llvm.amdgcn.sdot2.ll
…
llvm.amdgcn.sdot4.ll
…
llvm.amdgcn.sdot8.ll
…
llvm.amdgcn.sendmsg.ll [AMDGPU][SelectionDAG] Don't combine uniform multiplies to MUL_[UI]24 2021-02-23 15:39:19 +00:00
llvm.amdgcn.set.inactive.ll [AMDGPU] Set most sched model resource's BufferSize to one 2021-12-01 22:31:28 -08:00
llvm.amdgcn.sffbh.ll
…
llvm.amdgcn.sin.f16.ll
…
llvm.amdgcn.sin.ll [NFC] Removed unused prefixes from CodeGen/AMDGPU 2021-01-06 09:34:11 -08:00
llvm.amdgcn.softwqm.ll [AMDGPU] Rename amdgcn_wwm to amdgcn_strict_wwm 2021-03-03 09:33:57 +01:00
llvm.amdgcn.sqrt.f16.ll
…
llvm.amdgcn.sqrt.ll
…
llvm.amdgcn.struct.buffer.atomic.fadd.ll
…
llvm.amdgcn.struct.buffer.atomic.ll [NFC] Removed unused prefixes from CodeGen/AMDGPU 2021-01-06 09:34:11 -08:00
llvm.amdgcn.struct.buffer.load.format.d16.ll
…
llvm.amdgcn.struct.buffer.load.format.ll [NFC] Removed unused prefixes from CodeGen/AMDGPU 2021-01-06 09:34:11 -08:00
llvm.amdgcn.struct.buffer.load.format.v3f16.ll [AMDGPU] Do not generate ELF symbols for the local branch target labels 2021-11-20 10:32:41 +05:30
llvm.amdgcn.struct.buffer.load.ll [NFC] Removed unused prefixes from CodeGen/AMDGPU 2021-01-06 09:34:11 -08:00
llvm.amdgcn.struct.buffer.store.format.d16.ll [NFC] Removed unused prefixes from CodeGen/AMDGPU 2021-01-06 09:34:11 -08:00
llvm.amdgcn.struct.buffer.store.format.ll
…
llvm.amdgcn.struct.buffer.store.ll
…
llvm.amdgcn.struct.tbuffer.load.d16.ll [NFC] Removed unused prefixes from CodeGen/AMDGPU 2021-01-06 09:34:11 -08:00
llvm.amdgcn.struct.tbuffer.load.ll [AMDGPU] Set most sched model resource's BufferSize to one 2021-12-01 22:31:28 -08:00
llvm.amdgcn.struct.tbuffer.store.d16.ll [NFC] Removed unused prefixes from CodeGen/AMDGPU 2021-01-06 09:34:11 -08:00
llvm.amdgcn.struct.tbuffer.store.ll
…
llvm.amdgcn.tbuffer.load.d16.ll AMDGPU: Explicitly use SelectionDAG in legacy intrinsic tests 2021-01-06 11:37:00 -05:00
llvm.amdgcn.tbuffer.load.dwordx3.ll AMDGPU: Explicitly use SelectionDAG in legacy intrinsic tests 2021-01-06 11:37:00 -05:00
llvm.amdgcn.tbuffer.load.ll [AMDGPU] Set most sched model resource's BufferSize to one 2021-12-01 22:31:28 -08:00
llvm.amdgcn.tbuffer.store.d16.ll [NFC] Removed unused prefixes from CodeGen/AMDGPU 2021-01-06 09:34:11 -08:00
llvm.amdgcn.tbuffer.store.dwordx3.ll AMDGPU: Explicitly use SelectionDAG in legacy intrinsic tests 2021-01-06 11:37:00 -05:00
llvm.amdgcn.tbuffer.store.ll AMDGPU: Explicitly use SelectionDAG in legacy intrinsic tests 2021-01-06 11:37:00 -05:00
llvm.amdgcn.trig.preop.ll
…
llvm.amdgcn.ubfe.ll [AMDGPU] Set most sched model resource's BufferSize to one 2021-12-01 22:31:28 -08:00
llvm.amdgcn.udot2.ll [AMDGPU] Added udot2 op_sel test. NFC. 2021-04-09 12:19:42 -07:00
llvm.amdgcn.udot4.ll
…
llvm.amdgcn.udot8.ll
…
llvm.amdgcn.unreachable.ll
…
llvm.amdgcn.update.dpp.ll [AMDGPU] Refine -O0 and -O1 passes. 2021-07-15 09:51:54 -07:00
llvm.amdgcn.wave.barrier.ll
…
llvm.amdgcn.wavefrontsize.ll [NewPM][AMDGPU] Pass TargetMachine to AMDGPUSimplifyLibCallsPass 2021-01-04 13:48:09 -08:00
llvm.amdgcn.workgroup.id.ll [NFC] Removed unused prefixes from CodeGen/AMDGPU 2021-01-06 09:34:11 -08:00
llvm.amdgcn.workitem.id.ll AMDGPU: Fix checks in llvm.amdgcn.workitem.id.ll 2021-02-18 11:56:15 -05:00
llvm.amdgcn.wqm.demote.ll [AMDGPU] Only select VOP3 forms of VOP2 instructions 2021-11-24 11:15:30 +00:00
llvm.amdgcn.wqm.vote.ll [AMDGPU] Move kill lowering to WQM pass and add live mask tracking 2021-02-11 20:31:29 +09:00
llvm.amdgcn.writelane.ll [NFC] Removed unused prefixes from CodeGen/AMDGPU 2021-01-06 09:34:11 -08:00
llvm.ceil.f16.ll
…
llvm.cos.f16.ll [AMDGPU] Set most sched model resource's BufferSize to one 2021-12-01 22:31:28 -08:00
llvm.cos.ll
…
llvm.dbg.value.ll
…
llvm.exp2.f16.ll
…
llvm.exp2.ll
…
llvm.floor.f16.ll
…
llvm.fma.f16.ll [AMDGPU] Set most sched model resource's BufferSize to one 2021-12-01 22:31:28 -08:00
llvm.fmuladd.f16.ll [AMDGPU] Set most sched model resource's BufferSize to one 2021-12-01 22:31:28 -08:00
llvm.log.f16.ll [AMDGPU] Improve Codegen for build_vector 2021-05-12 14:17:44 +01:00
llvm.log.ll [NFC] Removed unused prefixes from CodeGen/AMDGPU 2021-01-06 09:34:11 -08:00
llvm.log2.f16.ll
…
llvm.log2.ll
…
llvm.log10.f16.ll [AMDGPU] Improve Codegen for build_vector 2021-05-12 14:17:44 +01:00
llvm.log10.ll [NFC] Removed unused prefixes from CodeGen/AMDGPU 2021-01-06 09:34:11 -08:00
llvm.maxnum.f16.ll [AMDGPU] Set most sched model resource's BufferSize to one 2021-12-01 22:31:28 -08:00
llvm.memcpy.ll
…
llvm.minnum.f16.ll [AMDGPU] Set most sched model resource's BufferSize to one 2021-12-01 22:31:28 -08:00
llvm.mulo.ll [AMDGPU] Implement widening multiplies with v_mad_i64_i32/v_mad_u64_u32 2021-11-24 11:25:02 +00:00
llvm.pow-gfx9.ll [AMDGPU][MC][GFX10][GFX90A] Corrected _e32/_e64 suffices 2021-04-01 14:21:00 +03:00
llvm.pow.ll
…
llvm.powi.ll Revert "[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range" 2021-12-22 11:39:28 -05:00
llvm.r600.cube.ll
…
llvm.r600.dot4.ll
…
llvm.r600.group.barrier.ll
…
llvm.r600.read.local.size.ll [AMDGPU][SelectionDAG] Don't combine uniform multiplies to MUL_[UI]24 2021-02-23 15:39:19 +00:00
llvm.r600.recipsqrt.clamped.ll
…
llvm.r600.recipsqrt.ieee.ll
…
llvm.r600.tex.ll
…
llvm.rint.f16.ll [AMDGPU] Improve Codegen for build_vector 2021-05-12 14:17:44 +01:00
llvm.rint.f64.ll
…
llvm.rint.ll
…
llvm.round.f64.ll [AMDGPU] Expand not pattern according to the XOR node divergence 2021-12-20 14:41:38 +03:00
llvm.round.ll [AMDGPU] Improve Codegen for build_vector 2021-05-12 14:17:44 +01:00
llvm.sin.f16.ll [AMDGPU] Set most sched model resource's BufferSize to one 2021-12-01 22:31:28 -08:00
llvm.sin.ll
…
llvm.sqrt.f16.ll
…
llvm.trunc.f16.ll
…
lo16-32bit-physreg-copy.mir
…
lo16-hi16-illegal-copy.mir
…
lo16-hi16-physreg-copy.mir
…
lo16-lo16-physreg-copy-agpr.mir
…
lo16-lo16-physreg-copy-sgpr.mir
…
load-constant-f32.ll Test commit 2021-11-30 15:00:16 +01:00
load-constant-f64.ll
…
load-constant-i1.ll
…
load-constant-i8.ll
…
load-constant-i16.ll [AMDGPU] Set most sched model resource's BufferSize to one 2021-12-01 22:31:28 -08:00
load-constant-i32.ll
…
load-constant-i64.ll [AMDGPU] Add 224-bit vector types and link 192-bit types to MVTs 2021-06-24 12:41:22 +09:00
load-global-f32.ll [NFC] Removed unused prefixes from CodeGen/AMDGPU 2021-01-06 09:34:11 -08:00
load-global-f64.ll [AMDGPU] Add 224-bit vector types and link 192-bit types to MVTs 2021-06-24 12:41:22 +09:00
load-global-i1.ll
…
load-global-i8.ll
…
load-global-i16.ll [AMDGPU] Set most sched model resource's BufferSize to one 2021-12-01 22:31:28 -08:00
load-global-i32.ll AMDGPU: Select global saddr mode from SGPR pointer 2020-11-16 11:51:06 -05:00
load-global-i64.ll [AMDGPU] Add 224-bit vector types and link 192-bit types to MVTs 2021-06-24 12:41:22 +09:00
load-hi16.ll [AMDGPU] Set most sched model resource's BufferSize to one 2021-12-01 22:31:28 -08:00
load-input-fold.ll
…
load-lo16.ll [AMDGPU] Set most sched model resource's BufferSize to one 2021-12-01 22:31:28 -08:00
load-local-f32-no-ds128.ll
…
load-local-f32.ll
…
load-local-f64.ll [NFC] Removed unused prefixes from CodeGen/AMDGPU 2021-01-06 09:34:11 -08:00
load-local-i1.ll
…
load-local-i8.ll
…
load-local-i16.ll
…
load-local-i32.ll [NFC] Removed unused prefixes from CodeGen/AMDGPU 2021-01-06 09:34:11 -08:00
load-local-i64.ll
…
load-local-redundant-copies.ll [AMDGPU] Add 224-bit vector types and link 192-bit types to MVTs 2021-06-24 12:41:22 +09:00
load-local.96.ll [AMDGPU] Set most sched model resource's BufferSize to one 2021-12-01 22:31:28 -08:00
load-local.128.ll [AMDGPU] Set most sched model resource's BufferSize to one 2021-12-01 22:31:28 -08:00
load-select-ptr.ll [amdgpu] Enable selection of `s_cselect_b64`. 2021-09-07 10:45:07 -04:00
load-store-opt-scc.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
load-weird-sizes.ll [NFC] Removed unused prefixes from CodeGen/AMDGPU 2021-01-06 09:34:11 -08:00
local-64.ll
…
local-atomics-fp.ll [AMDGPU] Limit memory scope for scratch, LDS and GDS 2021-02-14 17:34:12 +00:00
local-atomics.ll
…
local-atomics64.ll [NFC] Removed unused prefixes from CodeGen/AMDGPU 2021-01-06 09:34:11 -08:00
local-memory.amdgcn.ll [AMDGPU] Set most sched model resource's BufferSize to one 2021-12-01 22:31:28 -08:00
local-memory.ll [AMDGPU] Lower kernel LDS into a sorted structure 2021-05-25 11:29:29 -07:00
local-memory.r600.ll
…
local-stack-alloc-block-sp-reference.ll PrologEpilogInserter: Use explicit control for scavenge slot placement 2021-11-23 18:01:12 -05:00
local-stack-slot-offset.ll
…
loop-address.ll
…
loop-idiom.ll
…
loop-live-out-copy-undef-subrange.ll [AMDGPU] Do not generate ELF symbols for the local branch target labels 2021-11-20 10:32:41 +05:30
loop-prefetch.ll [AMDGPU] Do not generate ELF symbols for the local branch target labels 2021-11-20 10:32:41 +05:30
loop_break.ll [AMDGPU] Do not generate ELF symbols for the local branch target labels 2021-11-20 10:32:41 +05:30
loop_exit_with_xor.ll [AMDGPU] Move code sinking before structurizer 2021-05-11 14:07:23 +02:00
loop_header_nopred.mir [AMDGPU] Remove SI_MASK_BRANCH 2021-03-09 09:13:23 +08:00
lower-control-flow-other-terminators.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
lower-ctor-dtor.ll [AMDGPU] Change ASAN init/fini kernels linkage to external. 2021-09-27 11:50:37 -06:00
lower-empty-ctor-dtor.ll [amdgpu] Don't crash on empty global ctor/dtor 2021-11-16 14:36:08 +00:00
lower-i1-copies-implicit-def-unstructured-loop.mir AMDGPU: Treat IMPLICIT_DEF like a constant lanemask source 2021-07-27 11:44:38 -04:00
lower-kernargs.ll AMDGPU: Assume all amdhsa kernarg passed implicit arguments by default 2021-12-04 10:38:25 -05:00
lower-kernel-and-module-lds.ll [AMDGPU] Propagate LDS align into to instructions 2021-06-23 00:57:16 -07:00
lower-kernel-lds-constexpr.ll [IR] Replace *all* uses of a constant expression by corresponding instruction 2021-11-02 10:01:46 +05:30
lower-kernel-lds-super-align.ll [amdgpu] Increase alignment of all LDS variables 2021-12-12 19:30:32 +00:00
lower-kernel-lds.ll [AMDGPU] Disable LDS lowering for GFX shaders 2021-07-20 02:55:25 -07:00
lower-lds-struct-aa-memcpy.ll [AMDGPU] Correctly merge alias.scope and noalias metadata for memops 2021-09-21 13:02:01 -05:00
lower-lds-struct-aa-merge.ll [AMDGPU] Correctly merge alias.scope and noalias metadata for memops 2021-09-21 13:02:01 -05:00
lower-lds-struct-aa.ll [AMDGPU] Add alias.scope metadata to lowered LDS struct 2021-08-19 11:40:30 -07:00
lower-mem-intrinsics-threshold.ll
…
lower-mem-intrinsics.ll
…
lower-module-lds-check-metadata.ll [amdgpu] Add regression test for LDS in metadata 2021-12-13 13:35:38 +00:00
lower-module-lds-constantexpr.ll [AMDGPU] Use performOptimizedStructLayout for LDS sort 2021-06-22 09:58:10 -07:00
lower-module-lds-inactive.ll [AMDGPU] Lower kernel LDS into a sorted structure 2021-05-25 11:29:29 -07:00
lower-module-lds-offsets.ll [AMDGPU] Lower kernel LDS into a sorted structure 2021-05-25 11:29:29 -07:00
lower-module-lds-used-list.ll [AMDGPU] Propagate LDS align into to instructions 2021-06-23 00:57:16 -07:00
lower-module-lds.ll AMDGPU: Fix crashing on kernel declarations when lowering LDS 2021-08-26 19:01:10 -04:00
lower-multiple-ctor-dtor.ll [AMDGPU] Change ASAN init/fini kernels linkage to external. 2021-09-27 11:50:37 -06:00
lower-range-metadata-intrinsic-call.ll
…
lower-term-opcodes.mir [AMDGPU] Fix lowering of S_MOV_{B32,B64}_term 2020-11-10 12:16:31 +09:00
lshl64-to-32.ll [AMDGPU] Set most sched model resource's BufferSize to one 2021-12-01 22:31:28 -08:00
lshr.v2i16.ll [AMDGPU] Set most sched model resource's BufferSize to one 2021-12-01 22:31:28 -08:00
machine-cse-commute-target-flags.mir
…
machinelicm-convergent.mir Prevent LICM and machineLICM from hoisting convergent operations 2020-11-06 10:26:39 -08:00
macro-fusion-cluster-vcc-uses.mir
…
mad-combine.ll [DAGCombine] Allow FMA combine with both FMA and FMAD 2021-08-27 19:49:35 +09:00
mad-mix-hi.ll [AMDGPU] Add volatile support to SIMemoryLegalizer 2021-01-09 00:52:33 +00:00
mad-mix-lo.ll [AMDGPU] Convert mac/fmac to mad/fma when folding output modifiers 2021-09-22 09:36:34 +01:00
mad-mix.ll [AMDGPU] Convert mac/fmac to mad/fma when folding output modifiers 2021-09-22 09:36:34 +01:00
mad.u16.ll AMDGPU: Select global saddr mode from SGPR pointer 2020-11-16 11:51:06 -05:00
mad24-get-global-id.ll [AMDGPU][SelectionDAG] Don't combine uniform multiplies to MUL_[UI]24 2021-02-23 15:39:19 +00:00
mad_64_32.ll [AMDGPU] Implement widening multiplies with v_mad_i64_i32/v_mad_u64_u32 2021-11-24 11:25:02 +00:00
mad_int24.ll [AMDGPU][SelectionDAG] Don't combine uniform multiplies to MUL_[UI]24 2021-02-23 15:39:19 +00:00
mad_uint24.ll [AMDGPU][SelectionDAG] Don't combine uniform multiplies to MUL_[UI]24 2021-02-23 15:39:19 +00:00
madak-inline-constant.mir
…
madak.ll [AMDGPU] Add volatile support to SIMemoryLegalizer 2021-01-09 00:52:33 +00:00
madmk.ll [AMDGPU] Add volatile support to SIMemoryLegalizer 2021-01-09 00:52:33 +00:00
mai-hazards-gfx90a.mir [AMDGPU] Use single cache policy operand 2021-03-15 13:00:59 -07:00
mai-hazards.mir [AMDGPU] Use single cache policy operand 2021-03-15 13:00:59 -07:00
mai-inline.ll AMDGPU: Select global saddr mode from SGPR pointer 2020-11-16 11:51:06 -05:00
max-literals.ll
…
max-sgprs.ll
…
max.i16.ll [AMDGPU] Set most sched model resource's BufferSize to one 2021-12-01 22:31:28 -08:00
max.ll
…
max3.ll
…
mcp-overlap-after-propagation.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
mdt-preserving-crash.ll [amdgpu] Fix a crash case when preserving MDT in SILowerControlFlow 2021-10-15 13:21:53 -04:00
med3-no-simplify.ll [NFC] Removed unused prefixes in CodeGen/AMDGPU 2021-01-06 10:32:44 -08:00
mem-builtins.ll
…
memcpy-fixed-align.ll [AMDGPU] Enable multi-dword flat scratch load/stores 2020-11-12 13:38:56 -08:00
memcpy-inline-fails.ll
…
memcpy-scoped-aa.ll AMDGPU: Fix hardcoded registers in tests 2021-10-22 15:36:50 -04:00
memory-legalizer-atomic-insert-end.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
memory-legalizer-fence.ll [AMDGPU] Update gfx90a memory model support 2021-06-30 04:05:22 +00:00
memory-legalizer-flat-agent.ll [AMDGPU] Set most sched model resource's BufferSize to one 2021-12-01 22:31:28 -08:00
memory-legalizer-flat-nontemporal.ll [AMDGPU] Set most sched model resource's BufferSize to one 2021-12-01 22:31:28 -08:00
memory-legalizer-flat-singlethread.ll [AMDGPU] Set most sched model resource's BufferSize to one 2021-12-01 22:31:28 -08:00
memory-legalizer-flat-system.ll [AMDGPU] Set most sched model resource's BufferSize to one 2021-12-01 22:31:28 -08:00
memory-legalizer-flat-volatile.ll [AMDGPU] Set most sched model resource's BufferSize to one 2021-12-01 22:31:28 -08:00
memory-legalizer-flat-wavefront.ll [AMDGPU] Set most sched model resource's BufferSize to one 2021-12-01 22:31:28 -08:00
memory-legalizer-flat-workgroup.ll [AMDGPU] Set most sched model resource's BufferSize to one 2021-12-01 22:31:28 -08:00
memory-legalizer-global-agent.ll [AMDGPU] Set most sched model resource's BufferSize to one 2021-12-01 22:31:28 -08:00
memory-legalizer-global-nontemporal.ll [AMDGPU] Set most sched model resource's BufferSize to one 2021-12-01 22:31:28 -08:00
memory-legalizer-global-singlethread.ll [AMDGPU] Set most sched model resource's BufferSize to one 2021-12-01 22:31:28 -08:00
memory-legalizer-global-system.ll [AMDGPU] Set most sched model resource's BufferSize to one 2021-12-01 22:31:28 -08:00
memory-legalizer-global-volatile.ll [AMDGPU] Set most sched model resource's BufferSize to one 2021-12-01 22:31:28 -08:00
memory-legalizer-global-wavefront.ll [AMDGPU] Set most sched model resource's BufferSize to one 2021-12-01 22:31:28 -08:00
memory-legalizer-global-workgroup.ll [AMDGPU] Set most sched model resource's BufferSize to one 2021-12-01 22:31:28 -08:00
memory-legalizer-invalid-addrspace.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
memory-legalizer-invalid-syncscope.ll
…
memory-legalizer-local-agent.ll [AMDGPU] Set most sched model resource's BufferSize to one 2021-12-01 22:31:28 -08:00
memory-legalizer-local-nontemporal.ll [AMDGPU] Set most sched model resource's BufferSize to one 2021-12-01 22:31:28 -08:00
memory-legalizer-local-singlethread.ll [AMDGPU] Set most sched model resource's BufferSize to one 2021-12-01 22:31:28 -08:00
memory-legalizer-local-system.ll [AMDGPU] Set most sched model resource's BufferSize to one 2021-12-01 22:31:28 -08:00
memory-legalizer-local-volatile.ll [AMDGPU] Set most sched model resource's BufferSize to one 2021-12-01 22:31:28 -08:00
memory-legalizer-local-wavefront.ll [AMDGPU] Set most sched model resource's BufferSize to one 2021-12-01 22:31:28 -08:00
memory-legalizer-local-workgroup.ll [AMDGPU] Set most sched model resource's BufferSize to one 2021-12-01 22:31:28 -08:00
memory-legalizer-local.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
memory-legalizer-multiple-mem-operands-atomics.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
memory-legalizer-multiple-mem-operands-nontemporal-1.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
memory-legalizer-multiple-mem-operands-nontemporal-2.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
memory-legalizer-private-nontemporal.ll [AMDGPU] Set most sched model resource's BufferSize to one 2021-12-01 22:31:28 -08:00
memory-legalizer-private-volatile.ll [AMDGPU] Set most sched model resource's BufferSize to one 2021-12-01 22:31:28 -08:00
memory-legalizer-region.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
memory-legalizer-store-infinite-loop.ll
…
memory_clause.ll AMDGPU: Enable fixed function ABI by default 2021-12-04 10:49:18 -05:00
memory_clause.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
merge-image-load-gfx10.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
merge-image-load.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
merge-image-sample-gfx10.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
merge-image-sample.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
merge-load-store-agpr.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
merge-load-store-physreg.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
merge-load-store-vreg.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
merge-load-store.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
merge-m0.mir
…
merge-out-of-order-ldst.ll
…
merge-out-of-order-ldst.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
merge-sbuffer-load.mir [AMDGPU] Add merging into S_BUFFER_LOAD_DWORDX8_IMM 2021-09-02 16:26:25 +02:00
merge-store-crash.ll
…
merge-store-usedef.ll
…
merge-stores.ll
…
merge-tbuffer.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
mesa3d.ll
…
mesa_regression.ll
…
mfma-loop.ll [AMDGPU] Do not generate ELF symbols for the local branch target labels 2021-11-20 10:32:41 +05:30
min.ll [AMDGPU] Set most sched model resource's BufferSize to one 2021-12-01 22:31:28 -08:00
min3.ll
…
mir-print-dead-csr-fi.mir
…
misched-killflags.mir
…
missing-store.ll [AMDGPU] Set most sched model resource's BufferSize to one 2021-12-01 22:31:28 -08:00
mixed-wave32-wave64.ll [NFC] Removed unused prefixes in CodeGen/AMDGPU 2021-01-06 10:32:44 -08:00
mixed_wave32_wave64.ll
…
mode-register.mir
…
move-addr64-rsrc-dead-subreg-writes.ll [AMDGPU] Set most sched model resource's BufferSize to one 2021-12-01 22:31:28 -08:00
move-load-addr-to-valu.mir [AMDGPU] Divergence-driven compare operations instruction selection 2021-08-25 18:30:49 +03:00
move-to-valu-atomicrmw.ll [NFC] Removed unused prefixes in CodeGen/AMDGPU 2021-01-06 10:32:44 -08:00
move-to-valu-worklist.ll
…
movreld-bug.ll
…
movrels-bug.mir
…
mubuf-legalize-operands.ll [AMDGPU] Do not generate ELF symbols for the local branch target labels 2021-11-20 10:32:41 +05:30
mubuf-legalize-operands.mir [AMDGPU] Mark waterfall loops as SI_WATERFALL_LOOP 2021-07-13 12:15:08 +02:00
mubuf-offset-private.ll
…
mubuf-shader-vgpr.ll
…
mubuf.ll [AMDGPU] Fix typo in regular expression checks. NFC. 2021-04-06 12:29:48 +01:00
mul.i16.ll [AMDGPU] Switch PostRA sched to MachineSched 2021-09-14 15:11:27 -04:00
mul.ll [AMDGPU] Implement widening multiplies with v_mad_i64_i32/v_mad_u64_u32 2021-11-24 11:25:02 +00:00
mul24-pass-ordering.ll Revert "[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range" 2021-12-22 11:39:28 -05:00
mul_int24.ll [AMDGPU] Set most sched model resource's BufferSize to one 2021-12-01 22:31:28 -08:00
mul_uint24-amdgcn.ll [AMDGPU] Set most sched model resource's BufferSize to one 2021-12-01 22:31:28 -08:00
mul_uint24-r600.ll [AMDGPU] Regenerate mul24 test checks 2021-07-25 15:13:09 +01:00
multi-divergent-exit-region.ll [AMDGPU] Do not generate ELF symbols for the local branch target labels 2021-11-20 10:32:41 +05:30
multi-dword-vgpr-spill.ll [AMDGPU] Use multi-dword flat scratch for spilling 2020-12-14 14:19:29 -08:00
multilevel-break.ll [AMDGPU] Do not generate ELF symbols for the local branch target labels 2021-11-20 10:32:41 +05:30
nand.ll [NFC] Removed unused prefixes in CodeGen/AMDGPU 2021-01-06 10:32:44 -08:00
need-fp-from-vgpr-spills.ll Revert "[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range" 2021-12-22 11:39:28 -05:00
nested-calls.ll Revert "[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range" 2021-12-22 11:39:28 -05:00
nested-loop-conditions.ll [AMDGPU] Do not generate ELF symbols for the local branch target labels 2021-11-20 10:32:41 +05:30
no-bundle-asm.ll
…
no-hsa-graphics-shaders.ll
…
no-initializer-constant-addrspace.ll [llvm-readobj] - For SHT_REL relocations, don't display an addend. 2020-12-14 12:03:00 +03:00
no-remat-indirect-mov.mir Revert "[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range" 2021-12-22 11:39:28 -05:00
no-shrink-extloads.ll
…
no-source-locations-in-prologue.ll Revert "[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range" 2021-12-22 11:39:28 -05:00
non-entry-alloca.ll AMDGPU: Enable fixed function ABI by default 2021-12-04 10:49:18 -05:00
noop-shader-O0.ll
…
nop-data.ll
…
nor.ll [NFC] Removed unused prefixes in CodeGen/AMDGPU 2021-01-06 10:32:44 -08:00
not-scalarize-volatile-load.ll
…
nsa-reassign.ll [AMDGPU] Update subtarget features for new target ID support 2021-01-26 11:25:51 -08:00
nsa-reassign.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
nsa-vmem-hazard.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
nullptr.ll
…
occupancy-levels.ll AMDGPU: Don't consider whether amdgpu-flat-work-group-size was set 2021-10-22 16:23:50 -04:00
offset-split-flat.ll [AMDGPU][MC][GFX10][GFX90A] Corrected _e32/_e64 suffices 2021-04-01 14:21:00 +03:00
offset-split-global.ll [AMDGPU] Improve global SADDR selection 2021-05-05 14:44:21 -07:00
omod-nsz-flag.mir
…
omod.ll [AMDGPU] Enable output modifiers for double precision instructions 2021-04-01 10:08:17 -04:00
opencl-image-metadata.ll [NFC] Removed unused prefixes in CodeGen/AMDGPU 2021-01-06 10:32:44 -08:00
opencl-printf-no-hostcall.ll
…
opencl-printf.ll [NewPM][AMDGPU] Port amdgpu-printf-runtime-binding 2021-01-04 12:25:50 -08:00
operand-folding.ll [LiveIntervals] Update subranges in processTiedPairs 2021-11-11 12:24:59 +00:00
operand-spacing.ll [AMDGPU] Set most sched model resource's BufferSize to one 2021-12-01 22:31:28 -08:00
opt-pipeline.ll [AMDGPU] Promote generic pointer kernel arguments into global 2021-10-12 10:07:33 -07:00
opt-sgpr-to-vgpr-copy.mir [AMDGPU] Use single cache policy operand 2021-03-15 13:00:59 -07:00
opt_exec_copy_fold.mir [AMDGPU] SIOptimizeExecMaskingPreRA should check constant bus constraint when folds EXEC copy 2021-03-24 14:14:13 +03:00
optimize-compare.ll [AMDGPU] Process any power of 2 in optimizeCompareInstr 2021-09-02 17:39:17 -07:00
optimize-compare.mir [AMDGPU] Process any power of 2 in optimizeCompareInstr 2021-09-02 17:39:17 -07:00
optimize-exec-copies-extra-insts-after-copy.mir
…
optimize-exec-mask-pre-ra-loop-phi.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
optimize-exec-masking-pre-ra.mir [AMDGPU] Remove SI_MASK_BRANCH 2021-03-09 09:13:23 +08:00
optimize-exec-masking-strip-terminator-bits.mir
…
optimize-if-exec-masking.mir [AMDGPU] Use single cache policy operand 2021-03-15 13:00:59 -07:00
optimize-negated-cond-exec-masking-wave32.mir
…
optimize-negated-cond-exec-masking.mir
…
optimize-negated-cond.ll [AMDGPU] Do not generate ELF symbols for the local branch target labels 2021-11-20 10:32:41 +05:30
or.ll [AMDGPU] Divergence-driven compare operations instruction selection 2021-08-25 18:30:49 +03:00
or3.ll [AMDGPU] Stop adding an implicit def of vcc_hi for wave32 2020-12-02 10:11:42 +00:00
pack.v2f16.ll [NFC] Removed unused prefixes in CodeGen/AMDGPU 2021-01-06 10:32:44 -08:00
pack.v2i16.ll [NFC] Removed unused prefixes in CodeGen/AMDGPU 2021-01-06 10:32:44 -08:00
packed-fp32.ll [AMDGPU] Add S_MOV_B64_IMM_PSEUDO for wide constants 2021-06-30 11:45:38 -07:00
packed-op-sel.ll [AMDGPU] Set most sched model resource's BufferSize to one 2021-12-01 22:31:28 -08:00
packetizer.ll
…
pal-simple-indirect-call.ll [AMDGPU] Changes the AMDGPU_Gfx calling convention by making the SGPRs 4..29 callee-save. This is to avoid superfluous s_movs when executing amdgpu_gfx function calls as the callee is likely not going to change the argument values. 2021-11-04 21:50:18 +01:00
pal-userdata-regs.ll
…
parallelandifcollapse.ll
…
parallelorifcollapse.ll
…
partial-regcopy-and-spill-missed-at-regalloc.ll [AMDGPU] Add AV class spill pseudo instructions 2021-12-10 03:10:34 -05:00
partial-sgpr-to-vgpr-spills.ll [AMDGPU] Do not generate ELF symbols for the local branch target labels 2021-11-20 10:32:41 +05:30
partial-shift-shrink.ll [NFC] Removed unused prefixes in CodeGen/AMDGPU 2021-01-06 10:32:44 -08:00
partially-dead-super-register-immediate.ll
…
peephole-opt-regseq-removal.mir
…
pei-build-av-spill.mir [AMDGPU] Add AV class spill pseudo instructions 2021-12-10 03:10:34 -05:00
pei-build-spill-partial-agpr.mir [AMDGPU] Invert partial vgpr to agpr spill lane order 2021-08-26 09:39:03 -07:00
pei-build-spill.mir [AMDGPU] Invert partial vgpr to agpr spill lane order 2021-08-26 09:39:03 -07:00
pei-reg-scavenger-position.mir AMDGPU: Mark prolog/epilog SCC defs as dead 2021-11-15 21:35:06 -05:00
pei-scavenge-sgpr-carry-out.mir AMDGPU: Mark SCC def as dead when expanding frame indexes 2021-12-08 18:40:39 -05:00
pei-scavenge-sgpr-gfx9.mir AMDGPU: Mark SCC def as dead when expanding frame indexes 2021-12-08 18:40:39 -05:00
pei-scavenge-sgpr.mir AMDGPU: Mark SCC def as dead when expanding frame indexes 2021-12-08 18:40:39 -05:00
pei-scavenge-vgpr-spill.mir AMDGPU: Mark SCC def as dead when expanding frame indexes 2021-12-08 18:40:39 -05:00
perfhint.ll [AMDGPU] Tune perfhint analysis to account access width 2021-07-21 12:46:10 -07:00
permute.ll
…
phi-elimination-assertion.mir
…
phi-elimination-end-cf.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
phi-vgpr-input-moveimm.mir
…
pk_max_f16_literal.ll
…
post-ra-sched-kill-bundle-use-inst.mir [AMDGPU] Use single cache policy operand 2021-03-15 13:00:59 -07:00
post-ra-sched-reset.mir
…
post-ra-soft-clause-dbg-info.ll AMDGPU: Fix debug info handling in post-RA bundler 2021-02-16 10:42:06 -05:00
postra-bundle-memops.mir [AMDGPU] Fix SIPostRABundler crash on null register used by dbg value 2021-11-18 17:01:19 -08:00
postra-machine-sink.mir
…
postra-norename.mir
…
power-sched-no-instr-sunit.mir [AMDGPU] Use single cache policy operand 2021-03-15 13:00:59 -07:00
pr51516.mir [AMDGPU] Set most sched model resource's BufferSize to one 2021-12-01 22:31:28 -08:00
predicate-dp4.ll
…
predicates.ll
…
preserve-hi16.ll AMDGPU: Try to eliminate clearing of high bits of 16-bit instructions 2021-06-22 13:42:49 -04:00
print-mir-custom-pseudo.ll [AMDGPU] Implement mir parseCustomPseudoSourceValue 2021-01-22 11:24:08 +01:00
private-access-no-objects.ll [AMDGPU] Add volatile support to SIMemoryLegalizer 2021-01-09 00:52:33 +00:00
private-element-size.ll [NFC] Removed unused prefixes in CodeGen/AMDGPU 2021-01-06 10:32:44 -08:00
private-memory-atomics.ll
…
private-memory-r600.ll [AMDGPU, test] Fix use of undef FileCheck var 2021-04-08 09:42:59 +01:00
promote-alloca-addrspacecast.ll
…
promote-alloca-array-aggregate.ll
…
promote-alloca-array-allocation.ll
…
promote-alloca-bitcast-function.ll
…
promote-alloca-calling-conv.ll
…
promote-alloca-globals.ll [AMDGPU] Increase alignment of LDS globals if necessary before LDS lowering. 2021-06-07 18:00:41 +05:30
promote-alloca-invariant-markers.ll
…
promote-alloca-lifetime.ll
…
promote-alloca-mem-intrinsics.ll [AMDGPU] Fix promote alloca with double use in a same insn 2021-02-11 11:42:25 -08:00
promote-alloca-no-opts.ll
…
promote-alloca-padding-size-estimate.ll [AMDGPU] Lower kernel LDS into a sorted structure 2021-05-25 11:29:29 -07:00
promote-alloca-pointer-array.ll
…
promote-alloca-stored-pointer-value.ll
…
promote-alloca-strip-abi-opt-attributes.ll AMDGPU: Remove implicit argument attributes when introducing new calls 2021-08-26 22:08:04 -04:00
promote-alloca-to-lds-constantexpr-use.ll [AMDGPU] Rename "LDS lowering" pass name. 2021-04-14 20:19:53 +05:30
promote-alloca-to-lds-icmp.ll
…
promote-alloca-to-lds-phi.ll
…
promote-alloca-to-lds-select.ll
…
promote-alloca-unhandled-intrinsic.ll
…
promote-alloca-vector-to-vector.ll [AMDGPU] Add S_MOV_B64_IMM_PSEUDO for wide constants 2021-06-30 11:45:38 -07:00
promote-alloca-volatile.ll
…
promote-constOffset-to-imm-gfx10.mir [AMDGPU] Use single cache policy operand 2021-03-15 13:00:59 -07:00
promote-constOffset-to-imm-gfx90a.mir AMDGPU: Fix SILoadStoreOptimizer for gfx90a 2021-05-11 21:26:43 -04:00
promote-constOffset-to-imm.ll AMDGPU: Enable fixed function ABI by default 2021-12-04 10:49:18 -05:00
promote-constOffset-to-imm.mir [AMDGPU] Use single cache policy operand 2021-03-15 13:00:59 -07:00
promote-kernel-arguments.ll [AMDGPU] Promote generic pointer kernel arguments into global 2021-10-12 10:07:33 -07:00
promote-vect3-load.ll
…
propagate-attributes-bitcast-function.ll
…
propagate-attributes-clone.ll [NewPM][AMDGPU] Port amdgpu-propagate-attributes-early/late 2021-01-04 11:53:37 -08:00
propagate-attributes-function-pointer-argument.ll Revert "[AMDGPU] [IndirectCalls] Don't propagate attributes to address taken functions and their callees" 2021-06-24 02:33:50 +01:00
propagate-attributes-single-set.ll [NewPM][AMDGPU] Port amdgpu-propagate-attributes-early/late 2021-01-04 11:53:37 -08:00
propagate-flat-work-group-size.ll AMDGPU: Use attributor to propagate amdgpu-flat-work-group-size 2021-10-22 16:23:50 -04:00
ps-shader-arg-count.ll [AMDGPU] Set number vgprs used in PS shaders based on input registers actually used 2021-10-08 14:24:35 +01:00
ptr-arg-dbg-value.ll AMDGPU: Enable fixed function ABI by default 2021-12-04 10:49:18 -05:00
ptrmask.ll [AMDGPU] Extend gfx10 test coverage. NFC. 2021-03-29 11:13:55 +02:00
pv-packing.ll
…
pv.ll
…
r600-constant-array-fixup.ll [llvm-readobj] - For SHT_REL relocations, don't display an addend. 2020-12-14 12:03:00 +03:00
r600-encoding.ll
…
r600-export-fix.ll
…
r600-infinite-loop-bug-while-reorganizing-vector.ll
…
r600-legalize-umax-bug.ll [DAG] SimplifyDemandedBits - use KnownBits comparisons to remove ISD::UMIN/UMAX ops 2021-01-18 10:29:23 +00:00
r600.add.ll
…
r600.alu-limits.ll
…
r600.amdgpu-alias-analysis.ll [opt] Directly translate -O# to -passes='default<O#>' 2021-10-18 16:48:10 -07:00
r600.bitcast.ll [NFC] Removed unused prefixes in CodeGen/AMDGPU 2021-01-06 10:32:44 -08:00
r600.extract-lowbits.ll
…
r600.func-alignment.ll
…
r600.global_atomics.ll
…
r600.private-memory.ll
…
r600.sub.ll
…
r600.work-item-intrinsics.ll
…
r600cfg.ll
…
rcp-pattern.ll Revert "[NFC] remove explicit default value for strboolattr attribute in tests" 2021-05-24 19:43:40 +02:00
rcp_iflag.ll
…
read-register-invalid-subtarget.ll
…
read-register-invalid-type-i32.ll
…
read-register-invalid-type-i64.ll
…
read_register.ll
…
readcyclecounter.ll [AMDGPU] Add some GFX10.3 testing. NFC. 2021-05-11 11:21:19 +01:00
readlane_exec0.mir [AMDGPU] Rename SIInsertSkips Pass 2021-03-20 11:48:04 +09:00
reassoc-scalar.ll [AMDGPU] Update subtarget features for new target ID support 2021-01-26 11:25:51 -08:00
recursion.ll AMDGPU: Report large stack usage for recursive calls 2021-11-10 20:02:01 -05:00
reduce-build-vec-ext-to-ext-build-vec.ll
…
reduce-load-width-alignment.ll [NFC] Removed unused prefixes in CodeGen/AMDGPU 2021-01-06 10:32:44 -08:00
reduce-saveexec.mir
…
reduce-store-width-alignment.ll
…
reduction.ll
…
reg-coalescer-sched-crash.ll
…
regcoal-subrange-join-seg.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
regcoal-subrange-join.mir [AMDGPU] Use single cache policy operand 2021-03-15 13:00:59 -07:00
regcoalesce-cannot-join-failures.mir
…
regcoalesce-dbg.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
regcoalesce-keep-valid-lanes-implicit-def-bug39602.mir
…
regcoalesce-prune.mir
…
regcoalescer-resolve-lane-conflict-by-subranges.mir [RegisterCoalescer] Resolve conflict based on liveness of subregister 2021-07-14 14:43:22 +08:00
regcoalescing-remove-partial-redundancy-assert.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
register-count-comments.ll
…
rel32.ll [AMDGPU] Add some gfx1010 test coverage. NFC. 2021-03-18 14:00:07 +00:00
remat-dead-subreg.mir Check subrange liveness at rematerialization 2021-12-13 11:11:55 -08:00
remat-fp64-constants.ll [AMDGPU] Do not generate ELF symbols for the local branch target labels 2021-11-20 10:32:41 +05:30
remat-sop.mir [AMDGPU] Allow rematerialization of SOP with virtual registers 2021-10-20 11:46:50 -07:00
remat-vop.mir [AMDGPU] Mark relevant rematerializable VOP3 instructions 2021-07-21 14:44:13 -07:00
remove-short-exec-branches-gpr-idx-mode.mir [AMDGPU] Merge SIRemoveShortExecBranches into SIPreEmitPeephole 2021-03-20 11:26:42 +09:00
remove-short-exec-branches-special-instructions.mir [AMDGPU] Merge SIRemoveShortExecBranches into SIPreEmitPeephole 2021-03-20 11:26:42 +09:00
rename-disconnected-bug.ll
…
rename-independent-subregs-mac-operands.mir [AMDGPU] Use single cache policy operand 2021-03-15 13:00:59 -07:00
rename-independent-subregs.mir [AMDGPU] Add _e64 suffix to VOP3 Insts 2021-01-12 18:33:18 -05:00
reorder-stores.ll
…
replace-lds-by-ptr-call-diamond-shape.ll Revert "Revert "Disable ReplaceLDS pass, patch up tests to match"" 2021-09-01 21:52:50 +05:30
replace-lds-by-ptr-call-selected_functions.ll Revert "Revert "Disable ReplaceLDS pass, patch up tests to match"" 2021-09-01 21:52:50 +05:30
replace-lds-by-ptr-call-to-declare-only-func.ll Revert "Revert "Disable ReplaceLDS pass, patch up tests to match"" 2021-09-01 21:52:50 +05:30
replace-lds-by-ptr-ignore-global-scope-use.ll Revert "Revert "Disable ReplaceLDS pass, patch up tests to match"" 2021-09-01 21:52:50 +05:30
replace-lds-by-ptr-ignore-inline-asm-call.ll Revert "Revert "Disable ReplaceLDS pass, patch up tests to match"" 2021-09-01 21:52:50 +05:30
replace-lds-by-ptr-ignore-kernel-only-used-lds.ll Revert "Revert "Disable ReplaceLDS pass, patch up tests to match"" 2021-09-01 21:52:50 +05:30
replace-lds-by-ptr-ignore-not-reachable-lds.ll Revert "Revert "Disable ReplaceLDS pass, patch up tests to match"" 2021-09-01 21:52:50 +05:30
replace-lds-by-ptr-ignore-small-lds.ll Revert "Revert "Disable ReplaceLDS pass, patch up tests to match"" 2021-09-01 21:52:50 +05:30
replace-lds-by-ptr-indirect-call-diamond-shape.ll Revert "Revert "Disable ReplaceLDS pass, patch up tests to match"" 2021-09-01 21:52:50 +05:30
replace-lds-by-ptr-indirect-call-selected_functions.ll Revert "Revert "Disable ReplaceLDS pass, patch up tests to match"" 2021-09-01 21:52:50 +05:30
replace-lds-by-ptr-indirect-call-signature-match.ll Revert "Revert "Disable ReplaceLDS pass, patch up tests to match"" 2021-09-01 21:52:50 +05:30
replace-lds-by-ptr-use-multiple-lds.ll Revert "Revert "Disable ReplaceLDS pass, patch up tests to match"" 2021-09-01 21:52:50 +05:30
replace-lds-by-ptr-use-same-lds.ll Revert "Revert "Disable ReplaceLDS pass, patch up tests to match"" 2021-09-01 21:52:50 +05:30
replace-lds-by-ptr-use-within-const-expr1.ll Revert "Revert "Disable ReplaceLDS pass, patch up tests to match"" 2021-09-01 21:52:50 +05:30
replace-lds-by-ptr-use-within-const-expr2.ll Revert "Revert "Disable ReplaceLDS pass, patch up tests to match"" 2021-09-01 21:52:50 +05:30
replace-lds-by-ptr-use-within-phi-inst.ll Revert "Revert "Disable ReplaceLDS pass, patch up tests to match"" 2021-09-01 21:52:50 +05:30
reqd-work-group-size.ll [NewPM][AMDGPU] Port amdgpu-lower-kernel-attributes 2020-12-29 10:26:06 -08:00
reserve-vgpr-for-sgpr-spill.ll Revert "[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range" 2021-12-22 11:39:28 -05:00
reserved-reg-in-clause.mir [AMDGPU] Use single cache policy operand 2021-03-15 13:00:59 -07:00
ret.ll
…
ret_jump.ll [AMDGPU] Do not generate ELF symbols for the local branch target labels 2021-11-20 10:32:41 +05:30
return-with-successors.mir
…
returnaddress.ll AMDGPU: Remove fixed function ABI option 2021-12-10 19:41:19 -05:00
rewrite-out-arguments-address-space.ll Use unary CreateShuffleVector if possible 2020-12-30 22:36:08 +09:00
rewrite-out-arguments.ll Use unary CreateShuffleVector if possible 2020-12-30 22:36:08 +09:00
rotl.i64.ll
…
rotl.ll
…
rotr.i64.ll
…
rotr.ll
…
rsq.ll AMDGPU: Remove v_rsq_f64 patterns 2021-01-21 10:51:36 -05:00
rv7x0_count3.ll
…
s_add_co_pseudo_lowering.mir [AMDGPU] Add _e64 suffix to VOP3 Insts 2021-01-12 18:33:18 -05:00
s_addk_i32.ll AMDGPU: Add target id and code object v4 support 2021-03-24 11:54:05 -04:00
s_code_end.ll [AMDGPU] gfx90a support 2021-02-17 16:01:32 -08:00
s_movk_i32.ll
…
s_mulk_i32.ll AMDGPU: Add target id and code object v4 support 2021-03-24 11:54:05 -04:00
sad.ll [AMDGPU] Divergence-driven compare operations instruction selection 2021-08-25 18:30:49 +03:00
saddo.ll [AMDGPU] Set most sched model resource's BufferSize to one 2021-12-01 22:31:28 -08:00
saddsat.ll [AMDGPU] Switch PostRA sched to MachineSched 2021-09-14 15:11:27 -04:00
salu-to-valu.ll [AMDGPU] Set most sched model resource's BufferSize to one 2021-12-01 22:31:28 -08:00
same-slot-agpr-sgpr.mir [AMDGPU] Don't remove VGPR to AGPR dead spills from frame info 2021-12-23 11:09:19 -06:00
sampler-resource-id.ll
…
save-fp.ll Revert "[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range" 2021-12-22 11:39:28 -05:00
scalar-branch-missing-and-exec.ll
…
scalar-store-cache-flush.mir [AMDGPU] Use single cache policy operand 2021-03-15 13:00:59 -07:00
scalar_to_vector.ll [AMDGPU] Set most sched model resource's BufferSize to one 2021-12-01 22:31:28 -08:00
scalar_to_vector_v2x16.ll [AMDGPU] Refine -O0 and -O1 passes. 2021-07-15 09:51:54 -07:00
scc-clobbered-sgpr-to-vmem-spill.ll AMDGPU: Mark scc defs dead in SGPR to VMEM path for no free SGPRs 2021-12-08 18:40:49 -05:00
sched-assert-dead-def-subreg-use-other-subreg.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
sched-assert-onlydbg-value-empty-region.mir [AMDGPU] Set most sched model resource's BufferSize to one 2021-12-01 22:31:28 -08:00
sched-crash-dbg-value.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
sched-handleMoveUp-subreg-def-across-subreg-def.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
sched-prefer-non-mfma.mir [AMDGPU] Add _e64 suffix to VOP3 Insts 2021-01-12 18:33:18 -05:00
schedule-barrier-fpmode.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
schedule-barrier.mir [AMDGPU] Use single cache policy operand 2021-03-15 13:00:59 -07:00
schedule-fs-loop-nested-if.ll
…
schedule-fs-loop-nested.ll
…
schedule-fs-loop.ll
…
schedule-global-loads.ll
…
schedule-if-2.ll
…
schedule-if.ll
…
schedule-ilp.ll AMDGPU: Don't consider whether amdgpu-flat-work-group-size was set 2021-10-22 16:23:50 -04:00
schedule-ilp.mir [AMDGPU] Set most sched model resource's BufferSize to one 2021-12-01 22:31:28 -08:00
schedule-kernel-arg-loads.ll
…
schedule-regpressure-limit-clustering.ll
…
schedule-regpressure-limit.ll
…
schedule-regpressure-limit2.ll [NFC] Removed unused prefixes in CodeGen/AMDGPU 2021-01-07 08:00:11 -08:00
schedule-regpressure-limit3.ll [AMDGPU] Use max waves for scheduler's initial occupancy target 2021-10-26 15:30:26 -07:00
schedule-regpressure-misched-max-waves.ll [AMDGPU] Use max waves for scheduler's initial occupancy target 2021-10-26 15:30:26 -07:00
schedule-regpressure.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
schedule-vs-if-nested-loop-failure.ll
…
schedule-vs-if-nested-loop.ll
…
schedule-xdl-resource.ll
…
scheduler-handle-move-bundle.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
scheduler-subrange-crash.ll
…
scratch-buffer.ll
…
scratch-simple.ll [NFC] Removed unused prefixes in CodeGen/AMDGPU 2021-01-07 08:00:11 -08:00
sdiv.ll [AMDGPU] Set most sched model resource's BufferSize to one 2021-12-01 22:31:28 -08:00
sdiv64.ll [Support] improve known bits analysis for multiply by power-of-2 (1 set bit) 2021-12-08 11:50:05 -05:00
sdivrem24.ll
…
sdivrem64.r600.ll
…
sdwa-gfx9.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
sdwa-op64-test.ll
…
sdwa-ops.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
sdwa-peephole-instr-gfx10.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
sdwa-peephole-instr.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
sdwa-peephole.ll [AMDGPU] Set most sched model resource's BufferSize to one 2021-12-01 22:31:28 -08:00
sdwa-preserve.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
sdwa-scalar-ops.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
sdwa-stack.mir
…
sdwa-vop2-64bit.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
select-constant-cttz.ll [AMDGPU] Divergence-driven compare operations instruction selection 2021-08-25 18:30:49 +03:00
select-constant-xor.ll [AMDGPU] Only select VOP3 forms of VOP2 instructions 2021-11-24 11:15:30 +00:00
select-fabs-fneg-extract-legacy.ll [NFC] Removed unused prefixes in CodeGen/AMDGPU 2021-01-07 08:00:11 -08:00
select-fabs-fneg-extract.ll [AMDGPU] Divergence-driven compare operations instruction selection 2021-08-25 18:30:49 +03:00
select-i1.ll [AMDGPU] Use S_BITCMP1_* to replace AND in optimizeCompareInstr 2021-09-01 15:59:12 -07:00
select-opt.ll [AMDGPU] Divergence-driven compare operations instruction selection 2021-08-25 18:30:49 +03:00
select-undef.ll
…
select-vectors.ll [AMDGPU] Divergence-driven compare operations instruction selection 2021-08-25 18:30:49 +03:00
select.f16.ll [AMDGPU] Set most sched model resource's BufferSize to one 2021-12-01 22:31:28 -08:00
select.ll
…
select64.ll [AMDGPU] Set most sched model resource's BufferSize to one 2021-12-01 22:31:28 -08:00
selectcc-cnd.ll
…
selectcc-cnde-int.ll
…
selectcc-icmp-select-float.ll [DAG] Remove oneuse check in select_cc setgt X, -1, C, ~C fold 2021-09-05 16:18:31 +01:00
selectcc-opt.ll [AMDGPU] Divergence-driven compare operations instruction selection 2021-08-25 18:30:49 +03:00
selectcc.ll [amdgpu] Enable selection of `s_cselect_b64`. 2021-09-07 10:45:07 -04:00
sendmsg-m0-hazard.mir [NFC] Removed unused prefixes in CodeGen/AMDGPU 2021-01-07 08:00:11 -08:00
set-dx10.ll
…
set-gpr-idx-peephole.mir [AMDGPU] Add an implicit use of M0 to all V_MOV_B32_indirect_read/write 2021-11-19 19:00:17 +00:00
setcc-equivalent.ll
…
setcc-fneg-constant.ll [NFC] Removed unused prefixes in CodeGen/AMDGPU 2021-01-07 08:00:11 -08:00
setcc-limit-load-shrink.ll [AMDGPU] Update subtarget features for new target ID support 2021-01-26 11:25:51 -08:00
setcc-opt.ll [AMDGPU] Divergence-driven compare operations instruction selection 2021-08-25 18:30:49 +03:00
setcc-sext.ll
…
setcc.ll [AMDGPU] Fold immediates in the optimizeCompareInstr 2021-09-02 17:23:26 -07:00
setcc64.ll [AMDGPU] Fix setcc combine for i128 2021-10-26 13:39:50 +02:00
seto.ll
…
setuo.ll
…
sext-divergence-driven-isel.ll [AMDGPU] Set most sched model resource's BufferSize to one 2021-12-01 22:31:28 -08:00
sext-eliminate.ll
…
sext-in-reg-failure-r600.ll
…
sext-in-reg.ll [AMDGPU] Only select VOP3 forms of VOP2 instructions 2021-11-24 11:15:30 +00:00
sgpr-control-flow.ll [AMDGPU] Set most sched model resource's BufferSize to one 2021-12-01 22:31:28 -08:00
sgpr-copy-duplicate-operand.ll
…
sgpr-copy-local-cse.ll
…
sgpr-copy.ll [AMDGPU] Do not generate ELF symbols for the local branch target labels 2021-11-20 10:32:41 +05:30
sgpr-phys-copy.mir
…
sgpr-regalloc-flags.ll CodeGen: Make MachineOptimizationRemarkEmitterPass a CFG analysis 2021-07-19 21:08:26 -04:00
sgpr-spill-dead-frame-in-dbg-value.mir [AMDGPU] Fix the dead frame indices during custom spill lowering. 2021-03-09 23:22:49 +05:30
sgpr-spill-incorrect-fi-bookkeeping-bug.ll AMDGPU: Simplify test for SGPR spilling bug 2021-12-08 18:40:44 -05:00
sgpr-spill-no-vgprs.ll [AMDGPU] Do not generate ELF symbols for the local branch target labels 2021-11-20 10:32:41 +05:30
sgpr-spill-partially-undef.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
sgpr-spill-wrong-stack-id.mir RegAlloc: Allow targets to split register allocation 2021-07-13 18:49:29 -04:00
sgpr-spill.mir AMDGPU: Mark SCC def as dead when expanding frame indexes 2021-12-08 18:40:39 -05:00
sgprcopies.ll
…
shader-addr64-nonuniform.ll
…
shared-op-cycle.ll
…
shift-and-i64-ubfe.ll
…
shift-and-i128-ubfe.ll [AMDGPU] Set most sched model resource's BufferSize to one 2021-12-01 22:31:28 -08:00
shift-i64-opts.ll [AMDGPU] Add constrained shift pattern matches. 2021-10-26 19:07:19 +05:30
shift-i128.ll [AMDGPU] Set most sched model resource's BufferSize to one 2021-12-01 22:31:28 -08:00
shift-select.ll
…
shl-add-to-add-shl.ll
…
shl.ll [AMDGPU] Set most sched model resource's BufferSize to one 2021-12-01 22:31:28 -08:00
shl.v2i16.ll [AMDGPU] Set most sched model resource's BufferSize to one 2021-12-01 22:31:28 -08:00
shl_add.ll [AMDGPU] Stop adding an implicit def of vcc_hi for wave32 2020-12-02 10:11:42 +00:00
shl_add_constant.ll
…
shl_add_ptr.ll [AMDGPU] Switch PostRA sched to MachineSched 2021-09-14 15:11:27 -04:00
shl_add_ptr_csub.ll [AMDGPU][MC][GFX10][GFX90A] Corrected _e32/_e64 suffices 2021-04-01 14:21:00 +03:00
shl_add_ptr_global.ll [AMDGPU] Set most sched model resource's BufferSize to one 2021-12-01 22:31:28 -08:00
shl_or.ll [AMDGPU] Stop adding an implicit def of vcc_hi for wave32 2020-12-02 10:11:42 +00:00
shrink-add-sub-constant.ll [AMDGPU] Set most sched model resource's BufferSize to one 2021-12-01 22:31:28 -08:00
shrink-carry.mir [AMDGPU] Preserve deadness of vcc when shrinking instructions 2021-10-22 14:22:24 +01:00
shrink-instructions-flags.mir
…
shrink-instructions-illegal-fold.mir [AMDGPU] Avoid an illegal operand in si-shrink-instructions 2021-01-28 08:49:21 +01:00
shrink-instructions-implicit-vcclo.mir
…
shrink-insts-scalar-bit-ops.mir
…
shrink-vop3-carry-out.mir [AMDGPU] Use single cache policy operand 2021-03-15 13:00:59 -07:00
si-annotate-cf-kill.ll [AMDGPU] Do not generate ELF symbols for the local branch target labels 2021-11-20 10:32:41 +05:30
si-annotate-cf-noloop.ll [AMDGPU][SimplifyCFG] Teach AMDGPUUnifyDivergentExitNodes to preserve {,Post}DomTree 2021-01-02 01:01:20 +03:00
si-annotate-cf-unreachable.ll
…
si-annotate-cf.ll [AMDGPU] Set most sched model resource's BufferSize to one 2021-12-01 22:31:28 -08:00
si-annotate-cfg-loop-assert.ll [AMDGPU] Do not generate ELF symbols for the local branch target labels 2021-11-20 10:32:41 +05:30
si-annotatecfg-multiple-backedges.ll
…
si-fix-sgpr-copies.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
si-i1-copies.mir
…
si-instr-info-correct-implicit-operands.ll
…
si-lower-control-flow-kill.ll
…
si-lower-control-flow-unreachable-block.ll [AMDGPU] Do not generate ELF symbols for the local branch target labels 2021-11-20 10:32:41 +05:30
si-lower-control-flow.mir [AMDGPU] Use single cache policy operand 2021-03-15 13:00:59 -07:00
si-lower-i1-copies.mir
…
si-lower-sgpr-spills.mir
…
si-scheduler.ll [AMDGPU] Added -mcpu=tahiti to 3 tests. NFC. 2021-01-25 15:50:59 -08:00
si-sgpr-spill.ll [AMDGPU] Added -mcpu=tahiti to 3 tests. NFC. 2021-01-25 15:50:59 -08:00
si-spill-cf.ll
…
si-spill-sgpr-stack.ll [AMDGPU] Save VGPR of whole wave when spilling 2021-04-12 11:01:38 +02:00
si-triv-disjoint-mem-access.ll [AMDGPU] Set most sched model resource's BufferSize to one 2021-12-01 22:31:28 -08:00
si-vector-hang.ll
…
sibling-call.ll Revert "[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range" 2021-12-22 11:39:28 -05:00
sign_extend.ll [AMDGPU] Set most sched model resource's BufferSize to one 2021-12-01 22:31:28 -08:00
simple-indirect-call.ll AMDGPU: Invert ABI attribute handling 2021-09-09 18:24:28 -04:00
simplify-libcalls.ll [amdgpu] Add `-enable-ocl-mangling-mismatch-workaround`. 2021-06-08 15:42:27 -04:00
simplify-libcalls2.ll [NewPM][AMDGPU] Port amdgpu-simplifylib/amdgpu-usenative 2020-12-28 10:38:51 -08:00
simplifydemandedbits-recursion.ll
…
sink-image-sample.ll [AMDGPU] Move code sinking before structurizer 2021-05-11 14:07:23 +02:00
sint_to_fp.f64.ll [amdgpu] Enable selection of `s_cselect_b64`. 2021-09-07 10:45:07 -04:00
sint_to_fp.i64.ll [AMDGPU] Set most sched model resource's BufferSize to one 2021-12-01 22:31:28 -08:00
sint_to_fp.ll [AMDGPU] Divergence-driven compare operations instruction selection 2021-08-25 18:30:49 +03:00
sitofp.f16.ll
…
skip-branch-taildup-ret.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
skip-branch-trap.ll [AMDGPU] Do not generate ELF symbols for the local branch target labels 2021-11-20 10:32:41 +05:30
skip-if-dead.ll [AMDGPU] Do not generate ELF symbols for the local branch target labels 2021-11-20 10:32:41 +05:30
skip-promote-alloca-vector-users.ll [AMDGPU] Skip promote-alloca for insertelement/insertvalue users 2021-04-30 08:37:26 +05:30
smed3.ll [amdgpu] Update med3 combine to skip i64 2021-03-18 15:56:41 +00:00
smem-no-clause-coalesced.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
smem-war-hazard.mir [AMDGPU] Use single cache policy operand 2021-03-15 13:00:59 -07:00
sminmax.ll
…
sminmax.v2i16.ll
…
smrd-fold-offset.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
smrd-gfx10.ll
…
smrd-vccz-bug.ll [AMDGPU] Do not generate ELF symbols for the local branch target labels 2021-11-20 10:32:41 +05:30
smrd.ll [AMDGPU] Update subtarget features for new target ID support 2021-01-26 11:25:51 -08:00
smrd_vmem_war.ll AMDGPU: Select global saddr mode from SGPR pointer 2020-11-16 11:51:06 -05:00
soft-clause-dbg-value.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
soft-clause-exceeds-register-budget.ll RegAllocGreedy: Account for reserved registers in num regs heuristic 2021-09-14 21:00:29 -04:00
sopk-compares.ll [AMDGPU] Add S_MOV_B64_IMM_PSEUDO for wide constants 2021-06-30 11:45:38 -07:00
speculative-execution-freecasts.ll
…
spill-agpr-partially-undef.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
spill-agpr.ll [AMDGPU] Add AV class spill pseudo instructions 2021-12-10 03:10:34 -05:00
spill-agpr.mir [AMDGPU] Invert partial vgpr to agpr spill lane order 2021-08-26 09:39:03 -07:00
spill-alloc-sgpr-init-bug.ll
…
spill-before-exec.mir [AMDGPU] Remove weird target triples from tests. NFC. 2021-03-19 16:48:32 +00:00
spill-cfg-position.ll [AMDGPU] Do not generate ELF symbols for the local branch target labels 2021-11-20 10:32:41 +05:30
spill-csr-frame-ptr-reg-copy.ll AMDGPU: Enable fixed function ABI by default 2021-12-04 10:49:18 -05:00
spill-empty-live-interval.mir [AMDGPU] Use max waves for scheduler's initial occupancy target 2021-10-26 15:30:26 -07:00
spill-m0.ll [AMDGPU] Do not generate ELF symbols for the local branch target labels 2021-11-20 10:32:41 +05:30
spill-offset-calculation.ll PrologEpilogInserter: Use explicit control for scavenge slot placement 2021-11-23 18:01:12 -05:00
spill-reg-tuple-super-reg-use.mir AMDGPU: Mark prolog/epilog SCC defs as dead 2021-11-15 21:35:06 -05:00
spill-scavenge-offset.ll [AMDGPU] Switch PostRA sched to MachineSched 2021-09-14 15:11:27 -04:00
spill-sgpr-csr-live-ins.mir AMDGPU: Fix verifier error with argument passed in CSR SGPR 2021-02-09 13:49:44 -05:00
spill-sgpr-stack-no-sgpr.ll [AMDGPU] Save VGPR of whole wave when spilling 2021-04-12 11:01:38 +02:00
spill-special-sgpr.mir AMDGPU: Mark prolog/epilog SCC defs as dead 2021-11-15 21:35:06 -05:00
spill-to-agpr-partial.mir [AMDGPU] Invert partial vgpr to agpr spill lane order 2021-08-26 09:39:03 -07:00
spill-vector-superclass.ll [AMDGPU] Add AV class spill pseudo instructions 2021-12-10 03:10:34 -05:00
spill-vgpr-to-agpr.ll [AMDGPU] Enable copy between VGPR and AGPR classes during regalloc 2021-11-29 22:19:33 -05:00
spill-wide-sgpr.ll [NFC][AMDGPU] Clean up some lit test prefixes 2020-11-11 17:12:37 +00:00
spill192.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
spill224.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
spill_more_than_wavesize_csr_sgprs.ll RegAlloc: Allow targets to split register allocation 2021-07-13 18:49:29 -04:00
split-arg-dbg-value.ll [MCAsmInfo] Support UsesCFIForDebug for targets with no exception handling 2021-05-06 04:53:45 +05:30
split-scalar-i64-add.ll
…
split-smrd.ll
…
split-vector-memoperand-offsets.ll
…
splitkit-copy-bundle.mir Revert "[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range" 2021-12-22 11:39:28 -05:00
splitkit-copy-live-lanes.mir RegAllocGreedy: Account for reserved registers in num regs heuristic 2021-09-14 21:00:29 -04:00
splitkit-getsubrangeformask.ll [AMDGPU] Regenerate test checks in splitkit-getsubrangeformask.ll 2021-11-18 16:03:28 +00:00
splitkit-nolivesubranges.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
splitkit.mir [VirtRegRewriter] Insert missing killed flags when tracking subregister liveness 2021-03-03 12:02:04 -05:00
sra.ll [AMDGPU] Set most sched model resource's BufferSize to one 2021-12-01 22:31:28 -08:00
sram-ecc-default.ll AMDGPU: Add target id and code object v4 support 2021-03-24 11:54:05 -04:00
sramecc-subtarget-feature-any.ll [AMDGPU] Update subtarget features for new target ID support 2021-01-26 11:25:51 -08:00
sramecc-subtarget-feature-disabled.ll [AMDGPU] Update subtarget features for new target ID support 2021-01-26 11:25:51 -08:00
sramecc-subtarget-feature-enabled.ll [AMDGPU] Update subtarget features for new target ID support 2021-01-26 11:25:51 -08:00
srem-seteq-illegal-types.ll [AMDGPU] Enable divergence-driven BFE selection 2021-11-03 23:26:59 +03:00
srem.ll [AMDGPU][SelectionDAG] Don't combine uniform multiplies to MUL_[UI]24 2021-02-23 15:39:19 +00:00
srem64.ll [Support] improve known bits analysis for multiply by power-of-2 (1 set bit) 2021-12-08 11:50:05 -05:00
srl.ll [AMDGPU] Set most sched model resource's BufferSize to one 2021-12-01 22:31:28 -08:00
sroa-before-unroll.ll [AMDGPU][NewPM] Port amdgpu-promote-alloca(-to-vector) 2020-12-28 17:52:31 -08:00
ssubo.ll
…
ssubsat.ll AMDGPU: Enable fixed function ABI by default 2021-12-04 10:49:18 -05:00
stack-pointer-offset-relative-frameindex.ll AMDGPU: Enable fixed function ABI by default 2021-12-04 10:49:18 -05:00
stack-realign-kernel.ll [AMDGPU] Init scratch only if necessary 2021-07-14 10:45:22 +02:00
stack-realign.ll Revert "[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range" 2021-12-22 11:39:28 -05:00
stack-size-overflow.ll Make DiagnosticInfoResourceLimit's limit param required 2021-09-21 15:27:58 -07:00
stack-slot-color-sgpr-vgpr-spills.mir RegAlloc: Allow targets to split register allocation 2021-07-13 18:49:29 -04:00
stale-livevar-in-twoaddr-pass.mir [AMDGPU] Add _e64 suffix to VOP3 Insts 2021-01-12 18:33:18 -05:00
store-barrier.ll
…
store-clobbers-load.ll AMDGPU: Annotate amdgpu.noclobber for global loads only 2021-01-05 14:47:19 -08:00
store-global.ll AMDGPU: Select global saddr mode from SGPR pointer 2020-11-16 11:51:06 -05:00
store-hi16.ll PrologEpilogInserter: Use explicit control for scavenge slot placement 2021-11-23 18:01:12 -05:00
store-local.96.ll [AMDGPU] Set most sched model resource's BufferSize to one 2021-12-01 22:31:28 -08:00
store-local.128.ll [AMDGPU] Set most sched model resource's BufferSize to one 2021-12-01 22:31:28 -08:00
store-local.ll
…
store-private.ll
…
store-v3i64.ll
…
store-vector-ptrs.ll
…
store-weird-sizes.ll [AMDGPU] Set most sched model resource's BufferSize to one 2021-12-01 22:31:28 -08:00
store_typed.ll
…
stress-calls.ll
…
strict_fadd.f16.ll Revert "[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range" 2021-12-22 11:39:28 -05:00
strict_fadd.f32.ll [AMDGPU] Extend gfx10 test coverage. NFC. 2021-03-29 11:13:55 +02:00
strict_fadd.f64.ll [AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts 2021-04-26 17:21:49 -04:00
strict_fma.f16.ll [AMDGPU] Use v_fma_f16 on GFX10 2021-12-15 13:14:48 +00:00
strict_fma.f32.ll [AMDGPU] Prefer v_fmac over v_fma only when no source modifiers are used 2021-09-21 11:57:45 +01:00
strict_fma.f64.ll [AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts 2021-04-26 17:21:49 -04:00
strict_fmul.f16.ll Revert "[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range" 2021-12-22 11:39:28 -05:00
strict_fmul.f32.ll [AMDGPU] Extend gfx10 test coverage. NFC. 2021-03-29 11:13:55 +02:00
strict_fmul.f64.ll [AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts 2021-04-26 17:21:49 -04:00
strict_fsub.f16.ll Revert "[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range" 2021-12-22 11:39:28 -05:00
strict_fsub.f32.ll [AMDGPU] Extend gfx10 test coverage. NFC. 2021-03-29 11:13:55 +02:00
strict_fsub.f64.ll [AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts 2021-04-26 17:21:49 -04:00
structurize.ll
…
structurize1.ll
…
sub-zext-cc-zext-cc.ll
…
sub.i16.ll
…
sub.ll [AMDGPU] Set most sched model resource's BufferSize to one 2021-12-01 22:31:28 -08:00
sub.v2i16.ll [AMDGPU] Set most sched model resource's BufferSize to one 2021-12-01 22:31:28 -08:00
sub_i1.ll
…
subreg-coalescer-crash.ll
…
subreg-coalescer-undef-use.ll
…
subreg-eliminate-dead.ll
…
subreg-intervals.mir
…
subreg-split-live-in-error.mir [AMDGPU] Mark relevant rematerializable VOP3 instructions 2021-07-21 14:44:13 -07:00
subreg-undef-def-with-other-subreg-defs.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
subreg_interference.mir [VirtRegRewriter] Insert missing killed flags when tracking subregister liveness 2021-03-03 12:02:04 -05:00
subvector-test.mir [AMDGPU] Do not generate ELF symbols for the local branch target labels 2021-11-20 10:32:41 +05:30
swdev282079.ll AMDGPU: Fix assert on inline asm on gfx90a 2021-04-23 09:00:25 -04:00
swdev282079.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
switch-default-block-unreachable.ll
…
switch-unreachable.ll
…
swizzle-export.ll
…
syncscopes.ll CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
tail-call-amdgpu-gfx.ll Revert "[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range" 2021-12-22 11:39:28 -05:00
tail-call-cgp.ll
…
tail-dup-bundle.mir
…
tail-duplication-convergent.ll
…
target-cpu.ll AMDGPU: Don't consider whether amdgpu-flat-work-group-size was set 2021-10-22 16:23:50 -04:00
tex-clause-antidep.ll
…
texture-input-merge.ll
…
tgsplit.ll [AMDGPU] gfx90a support 2021-02-17 16:01:32 -08:00
tid-code-object-v2-backwards-compatibility.ll AMDGPU: Add gfx90c support to code object v2 for backwards compatibility 2021-04-08 16:42:43 -04:00
tid-mul-func-xnack-all-any.ll AMDGPU: Add target id and code object v4 support 2021-03-24 11:54:05 -04:00
tid-mul-func-xnack-all-not-supported.ll AMDGPU: Add target id and code object v4 support 2021-03-24 11:54:05 -04:00
tid-mul-func-xnack-all-off.ll AMDGPU: Add target id and code object v4 support 2021-03-24 11:54:05 -04:00
tid-mul-func-xnack-all-on.ll AMDGPU: Add target id and code object v4 support 2021-03-24 11:54:05 -04:00
tid-mul-func-xnack-any-off-1.ll AMDGPU: Add target id and code object v4 support 2021-03-24 11:54:05 -04:00
tid-mul-func-xnack-any-off-2.ll AMDGPU: Add target id and code object v4 support 2021-03-24 11:54:05 -04:00
tid-mul-func-xnack-any-on-1.ll AMDGPU: Add target id and code object v4 support 2021-03-24 11:54:05 -04:00
tid-mul-func-xnack-any-on-2.ll AMDGPU: Add target id and code object v4 support 2021-03-24 11:54:05 -04:00
tid-mul-func-xnack-invalid-any-off-on.ll AMDGPU: Add target id and code object v4 support 2021-03-24 11:54:05 -04:00
tid-one-func-xnack-any.ll AMDGPU: Add target id and code object v4 support 2021-03-24 11:54:05 -04:00
tid-one-func-xnack-not-supported.ll AMDGPU: Add target id and code object v4 support 2021-03-24 11:54:05 -04:00
tid-one-func-xnack-off.ll AMDGPU: Add target id and code object v4 support 2021-03-24 11:54:05 -04:00
tid-one-func-xnack-on.ll AMDGPU: Add target id and code object v4 support 2021-03-24 11:54:05 -04:00
token-factor-inline-limit-test.ll AMDGPU: Enable fixed function ABI by default 2021-12-04 10:49:18 -05:00
transform-block-with-return-to-epilog.ll CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
trap-abis.ll [AMDGPU] Do not generate ELF symbols for the local branch target labels 2021-11-20 10:32:41 +05:30
trap.ll
…
trunc-bitcast-vector.ll
…
trunc-cmp-constant.ll
…
trunc-combine.ll [AMDGPU][SelectionDAG] Don't combine uniform multiplies to MUL_[UI]24 2021-02-23 15:39:19 +00:00
trunc-store-f64-to-f16.ll
…
trunc-store-i1.ll [NFC] Removed unused prefixes from CodeGen/AMDGPU 2021-01-07 09:48:14 -08:00
trunc-store-i64.ll AMDGPU: Select global saddr mode from SGPR pointer 2020-11-16 11:51:06 -05:00
trunc-store-vec-i16-to-i8.ll
…
trunc-store.ll
…
trunc-vector-store-assertion-failure.ll
…
trunc.ll [AMDGPU] Switch PostRA sched to MachineSched 2021-09-14 15:11:27 -04:00
tti-unroll-prefs.ll
…
twoaddr-constrain.ll [GlobalISel] Rework more/fewer elements for vectors 2021-12-23 14:30:02 +01:00
twoaddr-fma-f64.mir AMDGPU: Add even aligned VGPR/AGPR register classes 2021-02-24 14:49:37 -05:00
twoaddr-fma.mir [AMDGPU] Fixed incomplete definitions in twoaddr-fma.mir. NFC. 2021-12-03 10:18:03 -08:00
twoaddr-mad.mir [AMDGPU] Add _e64 suffix to VOP3 Insts 2021-01-12 18:33:18 -05:00
twoaddr-regsequence.mir [LiveIntervals] Fix repairOldRegInRange for simple def cases 2021-09-24 11:44:49 +01:00
uaddo.ll [AMDGPU] Legalize operands of V_ADDC_U32_e32 and friends 2021-08-03 09:04:52 +01:00
uaddsat.ll AMDGPU: Enable fixed function ABI by default 2021-12-04 10:49:18 -05:00
udiv.ll Revert "[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range" 2021-12-22 11:39:28 -05:00
udiv64.ll Revert "[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range" 2021-12-22 11:39:28 -05:00
udivrem.ll [AMDGPU] Set most sched model resource's BufferSize to one 2021-12-01 22:31:28 -08:00
udivrem24.ll
…
udivrem64.r600.ll
…
uint_to_fp.f64.ll [amdgpu] Enable selection of `s_cselect_b64`. 2021-09-07 10:45:07 -04:00
uint_to_fp.i64.ll [AMDGPU] Set most sched model resource's BufferSize to one 2021-12-01 22:31:28 -08:00
uint_to_fp.ll [AMDGPU] Divergence-driven compare operations instruction selection 2021-08-25 18:30:49 +03:00
uitofp.f16.ll
…
umed3.ll
…
unaligned-load-store.ll [AMDGPU] Support unaligned flat scratch in TLI 2020-12-22 16:12:31 -08:00
unallocatable-bundle-regression.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
undef-copy-propagation.mir [MachineCopyPropagation] Handle propagation of undef copies 2021-10-07 20:34:27 +09:00
undef-subreg-use-after-coalesce.mir RegisterCoalescer: Fix not setting undef on coalesced subregister uses 2021-02-03 13:54:43 -05:00
undefined-physreg-sgpr-spill.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
undefined-subreg-liverange.ll [AMDGPU] Do not generate ELF symbols for the local branch target labels 2021-11-20 10:32:41 +05:30
unexpected-reg-unit-state.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
unhandled-loop-condition-assertion.ll
…
uniform-branch-intrinsic-cond.ll
…
uniform-cfg.ll [AMDGPU] Set most sched model resource's BufferSize to one 2021-12-01 22:31:28 -08:00
uniform-crash.ll [AMDGPU] Do not generate ELF symbols for the local branch target labels 2021-11-20 10:32:41 +05:30
uniform-loop-inside-nonuniform.ll [AMDGPU] Do not generate ELF symbols for the local branch target labels 2021-11-20 10:32:41 +05:30
uniform-work-group-attribute-missing.ll AMDGPU: Use attributor to propagate uniform-work-group-size 2021-09-09 18:24:28 -04:00
uniform-work-group-multistep.ll AMDGPU: Use attributor to propagate uniform-work-group-size 2021-09-09 18:24:28 -04:00
uniform-work-group-nested-function-calls.ll AMDGPU: Use attributor to propagate uniform-work-group-size 2021-09-09 18:24:28 -04:00
uniform-work-group-prevent-attribute-propagation.ll AMDGPU: Use attributor to propagate uniform-work-group-size 2021-09-09 18:24:28 -04:00
uniform-work-group-propagate-attribute.ll AMDGPU: Use attributor to propagate uniform-work-group-size 2021-09-09 18:24:28 -04:00
uniform-work-group-recursion-test.ll AMDGPU: Use attributor to propagate uniform-work-group-size 2021-09-09 18:24:28 -04:00
uniform-work-group-test.ll AMDGPU: Use attributor to propagate uniform-work-group-size 2021-09-09 18:24:28 -04:00
unify-metadata.ll [NewPM][AMDGPU] Port amdgpu-unify-metadata 2021-01-04 11:57:46 -08:00
unigine-liveness-crash.ll [AMDGPU][SimplifyCFG] Teach AMDGPUUnifyDivergentExitNodes to preserve {,Post}DomTree 2021-01-02 01:01:20 +03:00
unknown-processor.ll
…
unpack-half.ll
…
unroll.ll [AMDGPU][CostModel] Refine cost model for control-flow instructions. 2021-04-10 09:20:24 +03:00
unstructured-cfg-def-use-issue.ll Revert "[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range" 2021-12-22 11:39:28 -05:00
unsupported-calls.ll Revert "AMDGPU: Remove AMDGPUFixFunctionBitcasts pass" 2021-12-16 21:21:32 +00:00
unsupported-cc.ll
…
unsupported-image-a16.ll CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
unsupported-image-g16.ll CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
update-lds-alignment.ll [AMDGPU] Use performOptimizedStructLayout for LDS sort 2021-06-22 09:58:10 -07:00
update-phi.ll [AMDGPU] Don't handle export done when unify exit nodes 2021-07-14 14:54:37 +08:00
urem-seteq-illegal-types.ll Revert "[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range" 2021-12-22 11:39:28 -05:00
urem.ll
…
urem64.ll Revert "[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range" 2021-12-22 11:39:28 -05:00
use-sgpr-multiple-times.ll [AMDGPU] Set most sched model resource's BufferSize to one 2021-12-01 22:31:28 -08:00
usubo.ll
…
usubsat.ll AMDGPU: Enable fixed function ABI by default 2021-12-04 10:49:18 -05:00
v1i64-kernel-arg.ll
…
v1024.ll
…
v_cndmask.ll [AMDGPU] Divergence-driven compare operations instruction selection 2021-08-25 18:30:49 +03:00
v_cvt_pk_u8_f32.ll
…
v_mac.ll [AMDGPU] Add volatile support to SIMemoryLegalizer 2021-01-09 00:52:33 +00:00
v_mac_f16.ll [FPEnv][AMDGPU] Disable FSUB(-0,X)->FNEG(X) DAGCombine when subnormals are flushed 2021-01-04 14:44:10 -06:00
v_madak_f16.ll [AMDGPU] Set most sched model resource's BufferSize to one 2021-12-01 22:31:28 -08:00
v_mov_b64_expand_and_shrink.mir [AMDGPU] Fix immediate sign during V_MOV_B64_PSEUDO expansion 2021-07-01 09:00:29 -07:00
v_mov_b64_expansion.mir [AMDGPU] Fix immediate sign during V_MOV_B64_PSEUDO expansion 2021-07-01 09:00:29 -07:00
v_pack.ll [AMDGPU] Improve Codegen for build_vector 2021-05-12 14:17:44 +01:00
v_swap_b32.mir [AMDGPU] Fix v_swap_b32 formation on physical registers 2021-04-29 20:53:40 +01:00
valu-i1.ll [AMDGPU] Do not generate ELF symbols for the local branch target labels 2021-11-20 10:32:41 +05:30
vccz-corrupt-bug-workaround.mir [AMDGPU] Use single cache policy operand 2021-03-15 13:00:59 -07:00
vcmpx-exec-war-hazard.mir [AMDGPU] Move kill lowering to WQM pass and add live mask tracking 2021-02-11 20:31:29 +09:00
vcmpx-permlane-hazard.mir [AMDGPU] Move kill lowering to WQM pass and add live mask tracking 2021-02-11 20:31:29 +09:00
vector-alloca-addrspacecast.ll
…
vector-alloca-atomic.ll
…
vector-alloca-bitcast.ll [AMDGPU] Switch PostRA sched to MachineSched 2021-09-14 15:11:27 -04:00
vector-alloca-limits.ll [AMDGPU] Limit promote alloca max size in functions 2021-09-24 13:38:39 -07:00
vector-alloca.ll [NFC] Removed unused prefixes from CodeGen/AMDGPU 2021-01-07 09:48:14 -08:00
vector-extract-insert.ll [AMDGPU] Set most sched model resource's BufferSize to one 2021-12-01 22:31:28 -08:00
vector-legalizer-divergence.ll
…
vector-spill-restore-to-other-vector-type.mir [AMDGPU] Enable copy between VGPR and AGPR classes during regalloc 2021-11-29 22:19:33 -05:00
vector_shuffle.packed.ll [AMDGPU] Select build_vector DAG nodes according to the divergence 2021-12-23 02:27:12 +03:00
vectorize-buffer-fat-pointer.ll
…
vectorize-global-local.ll
…
vectorize-loads.ll
…
verify-constant-bus-violations.mir
…
verify-ds-gws-align.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
verify-duplicate-literal.mir [AMDGPU] Allow multiple uses of the same literal 2021-04-20 16:44:01 +01:00
verify-gfx90a-aligned-vgprs.mir [AMDGPU] Use single cache policy operand 2021-03-15 13:00:59 -07:00
verify-sop.mir
…
vertex-fetch-encoding.ll
…
vgpr-agpr-limit-gfx90a.ll [AMDGPU] Allow to use a whole register file on gfx90a for VGPRs 2021-10-21 18:24:34 -07:00
vgpr-descriptor-waterfall-loop-idom-update.ll [AMDGPU] Do not generate ELF symbols for the local branch target labels 2021-11-20 10:32:41 +05:30
vgpr-liverange-ir.ll [AMDGPU] Changes the AMDGPU_Gfx calling convention by making the SGPRs 4..29 callee-save. This is to avoid superfluous s_movs when executing amdgpu_gfx function calls as the callee is likely not going to change the argument values. 2021-11-04 21:50:18 +01:00
vgpr-liverange.ll [AMDGPU] Do not generate ELF symbols for the local branch target labels 2021-11-20 10:32:41 +05:30
vgpr-remat.mir [AMDGPU] Fix isReallyTriviallyReMaterializable for V_MOV_* 2021-03-10 16:18:12 +00:00
vgpr-spill-dead-frame-in-dbg-value.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
vgpr-spill-emergency-stack-slot-compute.ll
…
vgpr-spill-emergency-stack-slot.ll
…
vgpr-spill.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
vgpr-tuple-allocation.ll Revert "[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range" 2021-12-22 11:39:28 -05:00
vi-removed-intrinsics.ll
…
virtregrewrite-undef-identity-copy.mir RegAlloc: Allow targets to split register allocation 2021-07-13 18:49:29 -04:00
visit-physreg-vgpr-imm-folding-bug.ll
…
vmem-to-salu-hazard.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
vmem-vcc-hazard.mir [AMDGPU] Use single cache policy operand 2021-03-15 13:00:59 -07:00
vop-shrink-frame-index.mir
…
vop-shrink-non-ssa.mir
…
vop-shrink.ll
…
vselect.ll [AMDGPU] Divergence-driven compare operations instruction selection 2021-08-25 18:30:49 +03:00
vselect64.ll
…
vtx-fetch-branch.ll
…
vtx-schedule.ll
…
wait.ll
…
waitcnt-agpr.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
waitcnt-back-edge-loop.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
waitcnt-bvh.mir [AMDGPU] Add support for in-order bvh in waitcnt pass 2021-12-02 14:26:11 +00:00
waitcnt-debug.mir [AMDGPU] Revise handling of preexisting waitcnt 2021-05-05 17:21:33 -07:00
waitcnt-flat.ll
…
waitcnt-loop-irreducible.mir [AMDGPU] Use single cache policy operand 2021-03-15 13:00:59 -07:00
waitcnt-loop-single-basic-block.mir [AMDGPU] Use single cache policy operand 2021-03-15 13:00:59 -07:00
waitcnt-looptest.ll
…
waitcnt-meta-instructions.mir [AMDGPU] Use single cache policy operand 2021-03-15 13:00:59 -07:00
waitcnt-no-redundant.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
waitcnt-overflow.mir [AMDGPU] Use single cache policy operand 2021-03-15 13:00:59 -07:00
waitcnt-permute.mir
…
waitcnt-preexisting-vscnt.mir [AMDGPU] Revise handling of preexisting waitcnt 2021-05-05 17:21:33 -07:00
waitcnt-preexisting.mir [AMDGPU] Fix extra waitcnt being added with BUFFER_INVL2 2021-05-11 13:17:33 -07:00
waitcnt-skip-meta.mir
…
waitcnt-vmem-waw.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
waitcnt-vscnt.ll
…
waitcnt-vscnt.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
waitcnt.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
wave32.ll Revert "[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range" 2021-12-22 11:39:28 -05:00
wave_dispatch_regs.ll
…
widen-smrd-loads.ll [AMDGPU] Set most sched model resource's BufferSize to one 2021-12-01 22:31:28 -08:00
widen-vselect-and-mask.ll
…
widen_extending_scalar_loads.ll
…
wqm.ll [AMDGPU] Do not generate ELF symbols for the local branch target labels 2021-11-20 10:32:41 +05:30
wqm.mir [AMDGPU] Only allow implicit WQM in pixel shaders 2021-11-24 20:04:42 +09:00
write-register-vgpr-into-sgpr.ll
…
write_register.ll
…
wrong-transalu-pos-fix.ll
…
wwm-reserved-spill.ll Revert "[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range" 2021-12-22 11:39:28 -05:00
wwm-reserved.ll [AMDGPU] Implement widening multiplies with v_mad_i64_i32/v_mad_u64_u32 2021-11-24 11:25:02 +00:00
xfail.r600.bitcast.ll
…
xnack-subtarget-feature-any.ll [AMDGPU] Update subtarget features for new target ID support 2021-01-26 11:25:51 -08:00
xnack-subtarget-feature-disabled.ll [AMDGPU] Update subtarget features for new target ID support 2021-01-26 11:25:51 -08:00
xnack-subtarget-feature-enabled.ll [AMDGPU] Update subtarget features for new target ID support 2021-01-26 11:25:51 -08:00
xnor.ll [NFC] Removed unused prefixes from CodeGen/AMDGPU 2021-01-07 09:48:14 -08:00
xor.ll
…
xor3-i1-const.ll
…
xor3.ll [AMDGPU] Switch PostRA sched to MachineSched 2021-09-14 15:11:27 -04:00
xor_add.ll [AMDGPU] Stop adding an implicit def of vcc_hi for wave32 2020-12-02 10:11:42 +00:00
zero_extend.ll [AMDGPU] Divergence-driven compare operations instruction selection 2021-08-25 18:30:49 +03:00
zext-i64-bit-operand.ll
…
zext-lid.ll
…

README 

+==============================================================================+
| How to organize the lit tests                                                |
+==============================================================================+

- If you write a test for matching a single DAG opcode or intrinsic, it should
  go in a file called {opcode_name,intrinsic_name}.ll (e.g. fadd.ll)

- If you write a test that matches several DAG opcodes and checks for a single
  ISA instruction, then that test should go in a file called {ISA_name}.ll (e.g.
  bfi_int.ll

- For all other tests, use your best judgement for organizing tests and naming
  the files.

+==============================================================================+
| Naming conventions                                                           |
+==============================================================================+

- Use dash '-' and not underscore '_' to separate words in file names, unless
  the file is named after a DAG opcode or ISA instruction that has an
  underscore '_' in its name.