llvm-project/llvm/test/CodeGen
Brendon Cahoon d45a247998 [AMDGPU] Don't remove VGPR to AGPR dead spills from frame info
Removing dead frame indices for VGPR to AGPR spills is incorrect
when the frame index is shared by multiple objects, which may
occur due to stack slot coloring. The problem is that subsequent
code that processes the other object will assert because the stack
frame index is marked dead.

Removing dead frame indices is needed prior to stack slot
coloring, which is what happens with SGPR to VGPR spills. These
spills are lowered prior to stack slot coloring, but the VGPR
to AGPR spills are processed afterwards during the Prolog/Epilog
Inserter pass. This patch marks the VGPR to AGPR spill slot as
dead if the slot is not used by another object.

Differential Revision: https://reviews.llvm.org/D115996
2021-12-23 11:09:19 -06:00
..
AArch64 [AArch64] Add a tablegen pattern for SQXTN2. 2021-12-23 15:19:13 +00:00
AMDGPU [AMDGPU] Don't remove VGPR to AGPR dead spills from frame info 2021-12-23 11:09:19 -06:00
ARC
ARM [ARM] Add AddrModeT2_i8neg addressing mode support for frame lowering. 2021-12-14 12:49:27 +00:00
AVR [asm] Remove explicit branch for modifier 'l' 2021-11-19 09:19:53 -05:00
BPF BPF: Workaround InstCombine trunc+icmp => mask+icmp Optimization 2021-11-18 20:25:28 -08:00
CSKY [CSKY] Complete codegen of basic arithmetic and load/store operations 2021-12-09 11:40:20 +08:00
Generic [NFC][regalloc] Introduce the RegAllocEvictionAdvisorAnalysis 2021-12-16 17:56:46 -08:00
Hexagon Reapply [xray] add support for hexagon 2021-12-10 05:32:28 -08:00
Inputs
Lanai
M68k
MIR Revert "[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range" 2021-12-22 11:39:28 -05:00
MLRegalloc [NFC][regalloc] Introduce the RegAllocEvictionAdvisorAnalysis 2021-12-16 17:56:46 -08:00
MSP430
Mips [MIPS] Allow i1 values for 'r' constraint in inline-asm 2021-12-14 01:19:34 +03:00
NVPTX [NVPTX] Auto-generate tests for sufrace and texture instructions 2021-12-07 15:27:51 +03:00
PowerPC [PowerPC] Add missed test case updates 2021-12-21 14:55:19 -06:00
RISCV [RISCV] Use positive 0.0 for the neutral element in fadd reductions if nsz is present. 2021-12-23 10:38:00 -06:00
SPARC [SPARC] Zero-extend the operands when doing UMULO on 64-bit integers 2021-11-14 19:59:52 +01:00
SystemZ [z/OS] Implement prologue and epilogue generation for z/OS target. 2021-12-16 09:04:05 -05:00
Thumb [clang][ARM] PACBTI-M assembly support 2021-11-30 09:28:18 +00:00
Thumb2 [ARM] Fold away CMP/CSINC from CMOV 2021-12-19 21:53:50 +00:00
VE [VE] FADD,FSUB,FMUL,FDIV v256f32|f64 isel and tests 2021-12-21 09:15:31 +01:00
WebAssembly [WebAssembly] Add simd-vector-trunc.ll test missing from 2a4a229 2021-12-15 09:22:40 -08:00
WinCFGuard
WinEH
X86 [X86][SSE] Add ISD::ROTR support 2021-12-23 15:07:30 +00:00
XCore