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llvm-project/llvm/test/CodeGen/MIR
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Ron Lieberman 09b53296cf Revert "[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range" 
This reverts commit 9075009d1f.

 Failed amdgpu runtime buildbot # 3514
 		2021-12-22 11:39:28 -05:00
..
AArch64 CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
AMDGPU Revert "[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range" 2021-12-22 11:39:28 -05:00
ARM CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
Generic [MIRParser] Add machine metadata. 2021-06-28 22:29:36 -04:00
Hexagon CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
Mips CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
NVPTX
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PowerPC CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
WebAssembly
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X86 [DebugInfo][InstrRef][NFC] "Final" x86 test cleanup 2021-11-29 22:56:09 +00:00
README
…

README 

This directory contains tests for the MIR file format parser and printer. It
was necessary to split the tests across different targets as no single target
covers all features available in machine IR.

Tests for codegen passes should NOT be here but in test/CodeGen/sometarget. As
a rule of thumb this directory should only contain tests using
'llc -run-pass none'.