llvm-project/llvm/test/CodeGen/VE/Vector
Simon Moll b2cea573c9 [VE] FADD,FSUB,FMUL,FDIV v256f32|f64 isel and tests
Depends on D115940 for the `Binary_rv_vr_vv` pattern class op isel
fragment used for divisions.

Reviewed By: kaz7

Differential Revision: https://reviews.llvm.org/D116035
2021-12-21 09:15:31 +01:00
..
expand_single_elem_build_vec.ll
extract_elt.ll
fastcc_callee.ll
fastcc_caller.ll
feature_vpu.ll
insert_elt.ll
vec_add.ll
vec_and.ll
vec_broadcast.ll
vp_add.ll
vp_and.ll
vp_ashr.ll [VE] SHL,SRA,SRL v256i32|64 isel and tests 2021-12-15 11:32:18 +01:00
vp_fadd.ll [VE] FADD,FSUB,FMUL,FDIV v256f32|f64 isel and tests 2021-12-21 09:15:31 +01:00
vp_fdiv.ll [VE] FADD,FSUB,FMUL,FDIV v256f32|f64 isel and tests 2021-12-21 09:15:31 +01:00
vp_fmul.ll [VE] FADD,FSUB,FMUL,FDIV v256f32|f64 isel and tests 2021-12-21 09:15:31 +01:00
vp_fsub.ll [VE] FADD,FSUB,FMUL,FDIV v256f32|f64 isel and tests 2021-12-21 09:15:31 +01:00
vp_lshr.ll [VE] SHL,SRA,SRL v256i32|64 isel and tests 2021-12-15 11:32:18 +01:00
vp_mul.ll [VE] MUL,SUB,OR,XOR v256i32|64 isel 2021-12-14 13:23:48 +01:00
vp_or.ll [VE] MUL,SUB,OR,XOR v256i32|64 isel 2021-12-14 13:23:48 +01:00
vp_sdiv.ll [VE] U|SDIV v256i32|64 isel and tests 2021-12-21 08:51:01 +01:00
vp_shl.ll [VE] SHL,SRA,SRL v256i32|64 isel and tests 2021-12-15 11:32:18 +01:00
vp_sra.ll [VE] SHL,SRA,SRL v256i32|64 isel and tests 2021-12-15 11:32:18 +01:00
vp_srem.ll [VE][NFC] Use POSIX-compatible stream redirection 2021-12-01 17:28:57 +01:00
vp_srl.ll [VE] SHL,SRA,SRL v256i32|64 isel and tests 2021-12-15 11:32:18 +01:00
vp_sub.ll [VE] MUL,SUB,OR,XOR v256i32|64 isel 2021-12-14 13:23:48 +01:00
vp_udiv.ll [VE] U|SDIV v256i32|64 isel and tests 2021-12-21 08:51:01 +01:00
vp_urem.ll [VE][NFC] Use POSIX-compatible stream redirection 2021-12-01 17:28:57 +01:00
vp_xor.ll [VE] MUL,SUB,OR,XOR v256i32|64 isel 2021-12-14 13:23:48 +01:00