241 lines
8.6 KiB
LLVM
241 lines
8.6 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx | FileCheck %s --check-prefix=AVX --check-prefix=AVX1
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; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx2 | FileCheck %s --check-prefix=AVX --check-prefix=AVX2
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; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx512f | FileCheck %s --check-prefix=AVX --check-prefix=AVX512F
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; 'signum' test cases (PR13248)
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;
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; generic implementation for 128-bit vectors
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;
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define void @signum32a(<4 x float>*) {
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; AVX-LABEL: signum32a:
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; AVX: # %bb.0: # %entry
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; AVX-NEXT: vmovaps (%rdi), %xmm0
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; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1
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; AVX-NEXT: vcmpltps %xmm1, %xmm0, %xmm2
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; AVX-NEXT: vcvtdq2ps %xmm2, %xmm2
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; AVX-NEXT: vcmpltps %xmm0, %xmm1, %xmm0
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; AVX-NEXT: vcvtdq2ps %xmm0, %xmm0
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; AVX-NEXT: vsubps %xmm0, %xmm2, %xmm0
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; AVX-NEXT: vmovaps %xmm0, (%rdi)
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; AVX-NEXT: retq
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entry:
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%1 = load <4 x float>, <4 x float>* %0
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%2 = fcmp olt <4 x float> %1, zeroinitializer
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%3 = sitofp <4 x i1> %2 to <4 x float>
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%4 = fcmp ogt <4 x float> %1, zeroinitializer
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%5 = sitofp <4 x i1> %4 to <4 x float>
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%6 = fsub <4 x float> %3, %5
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store <4 x float> %6, <4 x float>* %0
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ret void
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}
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define void @signum64a(<2 x double>*) {
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; AVX-LABEL: signum64a:
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; AVX: # %bb.0: # %entry
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; AVX-NEXT: vmovapd (%rdi), %xmm0
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; AVX-NEXT: vxorpd %xmm1, %xmm1, %xmm1
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; AVX-NEXT: vcmpltpd %xmm1, %xmm0, %xmm2
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; AVX-NEXT: vpermilps {{.*#+}} xmm2 = xmm2[0,2,2,3]
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; AVX-NEXT: vcvtdq2pd %xmm2, %xmm2
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; AVX-NEXT: vcmpltpd %xmm0, %xmm1, %xmm0
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; AVX-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[0,2,2,3]
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; AVX-NEXT: vcvtdq2pd %xmm0, %xmm0
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; AVX-NEXT: vsubpd %xmm0, %xmm2, %xmm0
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; AVX-NEXT: vmovapd %xmm0, (%rdi)
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; AVX-NEXT: retq
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entry:
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%1 = load <2 x double>, <2 x double>* %0
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%2 = fcmp olt <2 x double> %1, zeroinitializer
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%3 = sitofp <2 x i1> %2 to <2 x double>
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%4 = fcmp ogt <2 x double> %1, zeroinitializer
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%5 = sitofp <2 x i1> %4 to <2 x double>
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%6 = fsub <2 x double> %3, %5
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store <2 x double> %6, <2 x double>* %0
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ret void
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}
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;
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; generic implementation for 256-bit vectors
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;
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define void @signum32b(<8 x float>*) {
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; AVX-LABEL: signum32b:
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; AVX: # %bb.0: # %entry
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; AVX-NEXT: vmovaps (%rdi), %ymm0
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; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1
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; AVX-NEXT: vcmpltps %ymm1, %ymm0, %ymm2
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; AVX-NEXT: vcvtdq2ps %ymm2, %ymm2
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; AVX-NEXT: vcmpltps %ymm0, %ymm1, %ymm0
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; AVX-NEXT: vcvtdq2ps %ymm0, %ymm0
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; AVX-NEXT: vsubps %ymm0, %ymm2, %ymm0
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; AVX-NEXT: vmovaps %ymm0, (%rdi)
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; AVX-NEXT: vzeroupper
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; AVX-NEXT: retq
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entry:
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%1 = load <8 x float>, <8 x float>* %0
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%2 = fcmp olt <8 x float> %1, zeroinitializer
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%3 = sitofp <8 x i1> %2 to <8 x float>
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%4 = fcmp ogt <8 x float> %1, zeroinitializer
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%5 = sitofp <8 x i1> %4 to <8 x float>
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%6 = fsub <8 x float> %3, %5
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store <8 x float> %6, <8 x float>* %0
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ret void
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}
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define void @signum64b(<4 x double>*) {
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; AVX1-LABEL: signum64b:
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; AVX1: # %bb.0: # %entry
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; AVX1-NEXT: vmovapd (%rdi), %ymm0
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; AVX1-NEXT: vxorpd %xmm1, %xmm1, %xmm1
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; AVX1-NEXT: vcmpltpd %ymm1, %ymm0, %ymm2
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; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm3
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; AVX1-NEXT: vpackssdw %xmm3, %xmm2, %xmm2
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; AVX1-NEXT: vcvtdq2pd %xmm2, %ymm2
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; AVX1-NEXT: vcmpltpd %ymm0, %ymm1, %ymm0
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; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
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; AVX1-NEXT: vpackssdw %xmm1, %xmm0, %xmm0
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; AVX1-NEXT: vcvtdq2pd %xmm0, %ymm0
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; AVX1-NEXT: vsubpd %ymm0, %ymm2, %ymm0
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; AVX1-NEXT: vmovapd %ymm0, (%rdi)
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; AVX1-NEXT: vzeroupper
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: signum64b:
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; AVX2: # %bb.0: # %entry
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; AVX2-NEXT: vmovapd (%rdi), %ymm0
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; AVX2-NEXT: vxorpd %xmm1, %xmm1, %xmm1
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; AVX2-NEXT: vcmpltpd %ymm1, %ymm0, %ymm2
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; AVX2-NEXT: vextractf128 $1, %ymm2, %xmm3
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; AVX2-NEXT: vpackssdw %xmm3, %xmm2, %xmm2
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; AVX2-NEXT: vcvtdq2pd %xmm2, %ymm2
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; AVX2-NEXT: vcmpltpd %ymm0, %ymm1, %ymm0
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; AVX2-NEXT: vextractf128 $1, %ymm0, %xmm1
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; AVX2-NEXT: vpackssdw %xmm1, %xmm0, %xmm0
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; AVX2-NEXT: vcvtdq2pd %xmm0, %ymm0
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; AVX2-NEXT: vsubpd %ymm0, %ymm2, %ymm0
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; AVX2-NEXT: vmovapd %ymm0, (%rdi)
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; AVX2-NEXT: vzeroupper
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; AVX2-NEXT: retq
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;
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; AVX512F-LABEL: signum64b:
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; AVX512F: # %bb.0: # %entry
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; AVX512F-NEXT: vmovapd (%rdi), %ymm0
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; AVX512F-NEXT: vxorpd %xmm1, %xmm1, %xmm1
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; AVX512F-NEXT: vcmpltpd %ymm1, %ymm0, %ymm2
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; AVX512F-NEXT: vpmovqd %zmm2, %ymm2
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; AVX512F-NEXT: vcvtdq2pd %xmm2, %ymm2
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; AVX512F-NEXT: vcmpltpd %ymm0, %ymm1, %ymm0
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; AVX512F-NEXT: vpmovqd %zmm0, %ymm0
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; AVX512F-NEXT: vcvtdq2pd %xmm0, %ymm0
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; AVX512F-NEXT: vsubpd %ymm0, %ymm2, %ymm0
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; AVX512F-NEXT: vmovapd %ymm0, (%rdi)
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; AVX512F-NEXT: vzeroupper
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; AVX512F-NEXT: retq
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entry:
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%1 = load <4 x double>, <4 x double>* %0
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%2 = fcmp olt <4 x double> %1, zeroinitializer
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%3 = sitofp <4 x i1> %2 to <4 x double>
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%4 = fcmp ogt <4 x double> %1, zeroinitializer
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%5 = sitofp <4 x i1> %4 to <4 x double>
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%6 = fsub <4 x double> %3, %5
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store <4 x double> %6, <4 x double>* %0
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ret void
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}
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;
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; implementation using AVX intrinsics for 256-bit vectors
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;
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define void @signum32c(<8 x float>*) {
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; AVX-LABEL: signum32c:
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; AVX: # %bb.0: # %entry
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; AVX-NEXT: vmovaps (%rdi), %ymm0
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; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1
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; AVX-NEXT: vcmpltps %ymm1, %ymm0, %ymm2
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; AVX-NEXT: vcvtdq2ps %ymm2, %ymm2
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; AVX-NEXT: vcmpltps %ymm0, %ymm1, %ymm0
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; AVX-NEXT: vcvtdq2ps %ymm0, %ymm0
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; AVX-NEXT: vsubps %ymm0, %ymm2, %ymm0
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; AVX-NEXT: vmovaps %ymm0, (%rdi)
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; AVX-NEXT: vzeroupper
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; AVX-NEXT: retq
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entry:
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%1 = load <8 x float>, <8 x float>* %0
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%2 = tail call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %1, <8 x float> zeroinitializer, i8 1)
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%3 = bitcast <8 x float> %2 to <8 x i32>
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%4 = sitofp <8 x i32> %3 to <8 x float>
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%5 = tail call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> zeroinitializer, <8 x float> %1, i8 1)
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%6 = bitcast <8 x float> %5 to <8 x i32>
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%7 = sitofp <8 x i32> %6 to <8 x float>
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%8 = fsub <8 x float> %4, %7
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store <8 x float> %8, <8 x float>* %0
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ret void
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}
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define void @signum64c(<4 x double>*) {
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; AVX1-LABEL: signum64c:
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; AVX1: # %bb.0: # %entry
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; AVX1-NEXT: vmovapd (%rdi), %ymm0
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; AVX1-NEXT: vxorpd %xmm1, %xmm1, %xmm1
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; AVX1-NEXT: vcmpltpd %ymm1, %ymm0, %ymm2
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; AVX1-NEXT: vcmpltpd %ymm0, %ymm1, %ymm0
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; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
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; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm3
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; AVX1-NEXT: vpsubd %xmm1, %xmm3, %xmm1
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; AVX1-NEXT: vpsubd %xmm0, %xmm2, %xmm0
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; AVX1-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2]
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; AVX1-NEXT: vcvtdq2pd %xmm0, %ymm0
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; AVX1-NEXT: vmovaps %ymm0, (%rdi)
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; AVX1-NEXT: vzeroupper
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: signum64c:
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; AVX2: # %bb.0: # %entry
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; AVX2-NEXT: vmovapd (%rdi), %ymm0
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; AVX2-NEXT: vxorpd %xmm1, %xmm1, %xmm1
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; AVX2-NEXT: vcmpltpd %ymm1, %ymm0, %ymm2
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; AVX2-NEXT: vcmpltpd %ymm0, %ymm1, %ymm0
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; AVX2-NEXT: vpsubd %ymm0, %ymm2, %ymm0
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; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
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; AVX2-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2]
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; AVX2-NEXT: vcvtdq2pd %xmm0, %ymm0
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; AVX2-NEXT: vmovaps %ymm0, (%rdi)
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; AVX2-NEXT: vzeroupper
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; AVX2-NEXT: retq
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;
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; AVX512F-LABEL: signum64c:
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; AVX512F: # %bb.0: # %entry
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; AVX512F-NEXT: vmovapd (%rdi), %ymm0
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; AVX512F-NEXT: vxorpd %xmm1, %xmm1, %xmm1
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; AVX512F-NEXT: vcmpltpd %ymm1, %ymm0, %ymm2
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; AVX512F-NEXT: vcmpltpd %ymm0, %ymm1, %ymm0
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; AVX512F-NEXT: vpsubd %ymm0, %ymm2, %ymm0
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; AVX512F-NEXT: vextracti128 $1, %ymm0, %xmm1
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; AVX512F-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2]
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; AVX512F-NEXT: vcvtdq2pd %xmm0, %ymm0
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; AVX512F-NEXT: vmovaps %ymm0, (%rdi)
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; AVX512F-NEXT: vzeroupper
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; AVX512F-NEXT: retq
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entry:
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%x = load <4 x double>, <4 x double>* %0
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%xgt = tail call <4 x double> @llvm.x86.avx.cmp.pd.256(<4 x double> %x, <4 x double> zeroinitializer, i8 1)
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%igt = bitcast <4 x double> %xgt to <8 x i32>
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%xlt = tail call <4 x double> @llvm.x86.avx.cmp.pd.256(<4 x double> zeroinitializer, <4 x double> %x, i8 1)
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%ilt = bitcast <4 x double> %xlt to <8 x i32>
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; it is important to use %igt twice as source in order to make LLVM use a shuffle operation
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%isign = sub <8 x i32> %igt, %ilt
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%ssign = shufflevector <8 x i32> %isign, <8 x i32> %isign, <4 x i32> <i32 0, i32 2, i32 12, i32 14>
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%sign = tail call <4 x double> @llvm.x86.avx.cvtdq2.pd.256(<4 x i32> %ssign)
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store <4 x double> %sign, <4 x double>* %0
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ret void
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}
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declare <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float>, <8 x float>, i8) nounwind readnone
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declare <4 x double> @llvm.x86.avx.cmp.pd.256(<4 x double>, <4 x double>, i8) nounwind readnone
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declare <4 x double> @llvm.x86.avx.cvtdq2.pd.256(<4 x i32>) nounwind readnone
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