e9adcbde31
Cortex-A55 has 2 64bit NEON vector units, meaning a 128bit instruction requires taking both units (and can only be issued as the first instruction in a dual issue pair). This patch models that by splitting the WriteV SchedWrite into two - the WriteVd that reads/writes only 64bit operands, and the WriteVq that read/writes 128bit registers. The A55 schedule then uses this distinction to model the WriteVq as taking both resource units, and starting a Schedule Group and WriteVd as taking one as before. I believe this is more correct, even if it does not lead to much better performance. Differential Revision: https://reviews.llvm.org/D108766 |
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| .. | ||
| IPC | ||
| A53-carry-over.s | ||
| A55-add-sequence.s | ||
| A55-all-stats.s | ||
| A55-all-views.s | ||
| A55-basic-instructions.s | ||
| A55-in-order-retire.s | ||
| A55-load-readadv.s | ||
| A55-load-store-alias.s | ||
| A55-load-store-noalias.s | ||
| A55-neon-instructions.s | ||
| A55-out-of-order-retire.s | ||
| A55-store-readadv.s | ||
| direct-branch.s | ||
| forwarding-A57.s | ||
| in-order-bottleneck-analysis.s | ||
| shifted-register.s | ||