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llvm-project/llvm/test/CodeGen/MIR
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Jay Foad ddd3807e69 [AMDGPU] Use new target MMO flag MONoClobber 
This allows us to set the noclobber flag on (the MMO of) a load
instruction instead of on the pointer. This fixes a bug where noclobber
was being applied to all loads from the same pointer, even if some of
them were clobbered.

Differential Revision: https://reviews.llvm.org/D118775
 		2022-02-02 17:12:36 +00:00
..
AArch64 CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
AMDGPU [AMDGPU] Use new target MMO flag MONoClobber 2022-02-02 17:12:36 +00:00
ARM CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
Generic [MIRParser] Add machine metadata. 2021-06-28 22:29:36 -04:00
Hexagon CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
Mips CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
NVPTX
…
PowerPC CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
WebAssembly
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X86 [DebugInfo][InstrRef][NFC] "Final" x86 test cleanup 2021-11-29 22:56:09 +00:00
README
…

README 

This directory contains tests for the MIR file format parser and printer. It
was necessary to split the tests across different targets as no single target
covers all features available in machine IR.

Tests for codegen passes should NOT be here but in test/CodeGen/sometarget. As
a rule of thumb this directory should only contain tests using
'llc -run-pass none'.