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llvm-project/llvm/test/CodeGen/AArch64/aarch64-fpclass.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mattr=+bf16 | FileCheck %s -check-prefix=CHECK
define i1 @isnan_half(half %x) nounwind {
; CHECK-LABEL: isnan_half:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: // kill: def $h0 killed $h0 def $s0
; CHECK-NEXT: fmov w8, s0
; CHECK-NEXT: and w8, w8, #0x7fff
; CHECK-NEXT: mov w9, #31744
; CHECK-NEXT: cmp w8, w9
; CHECK-NEXT: cset w0, gt
; CHECK-NEXT: ret
entry:
%0 = tail call i1 @llvm.isnan.f16(half %x)
ret i1 %0
}
define i1 @isnan_float(float %x) nounwind {
; CHECK-LABEL: isnan_float:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: fcmp s0, s0
; CHECK-NEXT: cset w0, vs
; CHECK-NEXT: ret
entry:
%0 = tail call i1 @llvm.isnan.f32(float %x)
ret i1 %0
}
define i1 @isnan_double(double %x) nounwind {
; CHECK-LABEL: isnan_double:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: fcmp d0, d0
; CHECK-NEXT: cset w0, vs
; CHECK-NEXT: ret
entry:
%0 = tail call i1 @llvm.isnan.f64(double %x)
ret i1 %0
}
define i1 @isnan_ldouble(fp128 %x) nounwind {
; CHECK-LABEL: isnan_ldouble:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT: mov v1.16b, v0.16b
; CHECK-NEXT: bl __unordtf2
; CHECK-NEXT: cmp w0, #0
; CHECK-NEXT: cset w0, ne
; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: ret
entry:
%0 = tail call i1 @llvm.isnan.f128(fp128 %x)
ret i1 %0
}
define i1 @isnan_half_strictfp(half %x) strictfp nounwind {
; CHECK-LABEL: isnan_half_strictfp:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: // kill: def $h0 killed $h0 def $s0
; CHECK-NEXT: fmov w8, s0
; CHECK-NEXT: and w8, w8, #0x7fff
; CHECK-NEXT: mov w9, #31744
; CHECK-NEXT: cmp w8, w9
; CHECK-NEXT: cset w0, gt
; CHECK-NEXT: ret
entry:
%0 = tail call i1 @llvm.isnan.f16(half %x)
ret i1 %0
}
define i1 @isnan_bfloat_strictfp(bfloat %x) strictfp nounwind {
; CHECK-LABEL: isnan_bfloat_strictfp:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: // kill: def $h0 killed $h0 def $s0
; CHECK-NEXT: fmov w8, s0
; CHECK-NEXT: and w8, w8, #0x7fff
; CHECK-NEXT: mov w9, #32640
; CHECK-NEXT: cmp w8, w9
; CHECK-NEXT: cset w0, gt
; CHECK-NEXT: ret
entry:
%0 = tail call i1 @llvm.isnan.bf16(bfloat %x)
ret i1 %0
}
define i1 @isnan_float_strictfp(float %x) strictfp nounwind {
; CHECK-LABEL: isnan_float_strictfp:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: fmov w8, s0
; CHECK-NEXT: and w8, w8, #0x7fffffff
; CHECK-NEXT: mov w9, #2139095040
; CHECK-NEXT: cmp w8, w9
; CHECK-NEXT: cset w0, gt
; CHECK-NEXT: ret
entry:
%0 = tail call i1 @llvm.isnan.f32(float %x)
ret i1 %0
}
define i1 @isnan_double_strictfp(double %x) strictfp nounwind {
; CHECK-LABEL: isnan_double_strictfp:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: fmov x8, d0
; CHECK-NEXT: and x8, x8, #0x7fffffffffffffff
; CHECK-NEXT: mov x9, #9218868437227405312
; CHECK-NEXT: cmp x8, x9
; CHECK-NEXT: cset w0, gt
; CHECK-NEXT: ret
entry:
%0 = tail call i1 @llvm.isnan.f64(double %x)
ret i1 %0
}
define i1 @isnan_ldouble_strictfp(fp128 %x) strictfp nounwind {
; CHECK-LABEL: isnan_ldouble_strictfp:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: str q0, [sp, #-16]!
; CHECK-NEXT: ldp x8, x9, [sp], #16
; CHECK-NEXT: mov x10, #9223090561878065152
; CHECK-NEXT: cmp x8, #0
; CHECK-NEXT: and x8, x9, #0x7fffffffffffffff
; CHECK-NEXT: cset w9, ne
; CHECK-NEXT: cmp x8, x10
; CHECK-NEXT: cset w8, gt
; CHECK-NEXT: csel w0, w9, w8, eq
; CHECK-NEXT: ret
entry:
%0 = tail call i1 @llvm.isnan.f128(fp128 %x)
ret i1 %0
}
define <1 x i1> @isnan_half_vec1(<1 x half> %x) nounwind {
; CHECK-LABEL: isnan_half_vec1:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: // kill: def $h0 killed $h0 def $q0
; CHECK-NEXT: umov w8, v0.h[0]
; CHECK-NEXT: and w8, w8, #0x7fff
; CHECK-NEXT: mov w9, #31744
; CHECK-NEXT: cmp w8, w9
; CHECK-NEXT: cset w0, gt
; CHECK-NEXT: ret
entry:
%0 = tail call <1 x i1> @llvm.isnan.v1f16(<1 x half> %x)
ret <1 x i1> %0
}
define <1 x i1> @isnan_float_vec1(<1 x float> %x) nounwind {
; CHECK-LABEL: isnan_float_vec1:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-NEXT: fcmp s0, s0
; CHECK-NEXT: cset w0, vs
; CHECK-NEXT: ret
entry:
%0 = tail call <1 x i1> @llvm.isnan.v1f32(<1 x float> %x)
ret <1 x i1> %0
}
define <1 x i1> @isnan_double_vec1(<1 x double> %x) nounwind {
; CHECK-LABEL: isnan_double_vec1:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: fcmp d0, d0
; CHECK-NEXT: cset w0, vs
; CHECK-NEXT: ret
entry:
%0 = tail call <1 x i1> @llvm.isnan.v1f64(<1 x double> %x)
ret <1 x i1> %0
}
define <1 x i1> @isnan_ldouble_vec1(<1 x fp128> %x) nounwind {
; CHECK-LABEL: isnan_ldouble_vec1:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT: mov v1.16b, v0.16b
; CHECK-NEXT: bl __unordtf2
; CHECK-NEXT: cmp w0, #0
; CHECK-NEXT: cset w0, ne
; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: ret
entry:
%0 = tail call <1 x i1> @llvm.isnan.v1f128(<1 x fp128> %x)
ret <1 x i1> %0
}
define <2 x i1> @isnan_half_vec2(<2 x half> %x) nounwind {
; CHECK-LABEL: isnan_half_vec2:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-NEXT: umov w8, v0.h[0]
; CHECK-NEXT: umov w9, v0.h[1]
; CHECK-NEXT: fmov s1, w8
; CHECK-NEXT: movi v0.2s, #127, msl #8
; CHECK-NEXT: mov v1.s[1], w9
; CHECK-NEXT: and v0.8b, v1.8b, v0.8b
; CHECK-NEXT: movi v1.2s, #124, lsl #8
; CHECK-NEXT: cmgt v0.2s, v0.2s, v1.2s
; CHECK-NEXT: ret
entry:
%0 = tail call <2 x i1> @llvm.isnan.v2f16(<2 x half> %x)
ret <2 x i1> %0
}
define <2 x i1> @isnan_float_vec2(<2 x float> %x) nounwind {
; CHECK-LABEL: isnan_float_vec2:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: fcmge v1.2s, v0.2s, #0.0
; CHECK-NEXT: fcmlt v0.2s, v0.2s, #0.0
; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b
; CHECK-NEXT: mvn v0.8b, v0.8b
; CHECK-NEXT: ret
entry:
%0 = tail call <2 x i1> @llvm.isnan.v2f32(<2 x float> %x)
ret <2 x i1> %0
}
define <2 x i1> @isnan_double_vec2(<2 x double> %x) nounwind {
; CHECK-LABEL: isnan_double_vec2:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: fcmge v1.2d, v0.2d, #0.0
; CHECK-NEXT: fcmlt v0.2d, v0.2d, #0.0
; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b
; CHECK-NEXT: mvn v0.16b, v0.16b
; CHECK-NEXT: xtn v0.2s, v0.2d
; CHECK-NEXT: ret
entry:
%0 = tail call <2 x i1> @llvm.isnan.v2f64(<2 x double> %x)
ret <2 x i1> %0
}
define <2 x i1> @isnan_ldouble_vec2(<2 x fp128> %x) nounwind {
; CHECK-LABEL: isnan_ldouble_vec2:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: sub sp, sp, #48
; CHECK-NEXT: str q0, [sp, #16] // 16-byte Folded Spill
; CHECK-NEXT: mov v0.16b, v1.16b
; CHECK-NEXT: str x30, [sp, #32] // 8-byte Folded Spill
; CHECK-NEXT: bl __unordtf2
; CHECK-NEXT: cmp w0, #0
; CHECK-NEXT: cset w8, ne
; CHECK-NEXT: sbfx x8, x8, #0, #1
; CHECK-NEXT: dup v0.2d, x8
; CHECK-NEXT: str q0, [sp] // 16-byte Folded Spill
; CHECK-NEXT: ldr q0, [sp, #16] // 16-byte Folded Reload
; CHECK-NEXT: mov v1.16b, v0.16b
; CHECK-NEXT: bl __unordtf2
; CHECK-NEXT: cmp w0, #0
; CHECK-NEXT: ldr q1, [sp] // 16-byte Folded Reload
; CHECK-NEXT: cset w8, ne
; CHECK-NEXT: sbfx x8, x8, #0, #1
; CHECK-NEXT: ldr x30, [sp, #32] // 8-byte Folded Reload
; CHECK-NEXT: dup v0.2d, x8
; CHECK-NEXT: zip1 v0.4s, v0.4s, v1.4s
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-NEXT: add sp, sp, #48
; CHECK-NEXT: ret
entry:
%0 = tail call <2 x i1> @llvm.isnan.v2f128(<2 x fp128> %x)
ret <2 x i1> %0
}
define <2 x i1> @isnan_half_vec2_strictfp(<2 x half> %x) strictfp nounwind {
; CHECK-LABEL: isnan_half_vec2_strictfp:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-NEXT: umov w8, v0.h[0]
; CHECK-NEXT: umov w9, v0.h[1]
; CHECK-NEXT: fmov s1, w8
; CHECK-NEXT: movi v0.2s, #127, msl #8
; CHECK-NEXT: mov v1.s[1], w9
; CHECK-NEXT: and v0.8b, v1.8b, v0.8b
; CHECK-NEXT: movi v1.2s, #124, lsl #8
; CHECK-NEXT: cmgt v0.2s, v0.2s, v1.2s
; CHECK-NEXT: ret
entry:
%0 = tail call <2 x i1> @llvm.isnan.v2f16(<2 x half> %x)
ret <2 x i1> %0
}
define <2 x i1> @isnan_bfloat_vec2_strictfp(<2 x bfloat> %x) strictfp nounwind {
; CHECK-LABEL: isnan_bfloat_vec2_strictfp:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-NEXT: umov w8, v0.h[0]
; CHECK-NEXT: umov w9, v0.h[1]
; CHECK-NEXT: fmov s1, w8
; CHECK-NEXT: movi v0.2s, #127, msl #8
; CHECK-NEXT: mov w10, #32640
; CHECK-NEXT: mov v1.s[1], w9
; CHECK-NEXT: and v0.8b, v1.8b, v0.8b
; CHECK-NEXT: dup v1.2s, w10
; CHECK-NEXT: cmgt v0.2s, v0.2s, v1.2s
; CHECK-NEXT: ret
entry:
%0 = tail call <2 x i1> @llvm.isnan.v2bf16(<2 x bfloat> %x)
ret <2 x i1> %0
}
define <2 x i1> @isnan_float_vec2_strictfp(<2 x float> %x) strictfp nounwind {
; CHECK-LABEL: isnan_float_vec2_strictfp:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov w8, #2139095040
; CHECK-NEXT: dup v1.2s, w8
; CHECK-NEXT: bic v0.2s, #128, lsl #24
; CHECK-NEXT: cmgt v0.2s, v0.2s, v1.2s
; CHECK-NEXT: ret
entry:
%0 = tail call <2 x i1> @llvm.isnan.v2f32(<2 x float> %x)
ret <2 x i1> %0
}
define <2 x i1> @isnan_double_vec2_strictfp(<2 x double> %x) strictfp nounwind {
; CHECK-LABEL: isnan_double_vec2_strictfp:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov x8, #9223372036854775807
; CHECK-NEXT: mov x9, #9218868437227405312
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
; CHECK-NEXT: dup v1.2d, x9
; CHECK-NEXT: cmgt v0.2d, v0.2d, v1.2d
; CHECK-NEXT: xtn v0.2s, v0.2d
; CHECK-NEXT: ret
entry:
%0 = tail call <2 x i1> @llvm.isnan.v2f64(<2 x double> %x)
ret <2 x i1> %0
}
define <2 x i1> @isnan_ldouble_vec2_strictfp(<2 x fp128> %x) strictfp nounwind {
; CHECK-LABEL: isnan_ldouble_vec2_strictfp:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: stp q0, q1, [sp, #-32]!
; CHECK-NEXT: ldp x11, x10, [sp, #16]
; CHECK-NEXT: ldp x8, x9, [sp]
; CHECK-NEXT: mov x12, #9223090561878065152
; CHECK-NEXT: and x10, x10, #0x7fffffffffffffff
; CHECK-NEXT: cmp x11, #0
; CHECK-NEXT: cset w11, ne
; CHECK-NEXT: cmp x10, x12
; CHECK-NEXT: cset w10, gt
; CHECK-NEXT: and x9, x9, #0x7fffffffffffffff
; CHECK-NEXT: csel w10, w11, w10, eq
; CHECK-NEXT: cmp x8, #0
; CHECK-NEXT: sbfx x8, x10, #0, #1
; CHECK-NEXT: cset w10, ne
; CHECK-NEXT: cmp x9, x12
; CHECK-NEXT: dup v0.2d, x8
; CHECK-NEXT: cset w8, gt
; CHECK-NEXT: csel w8, w10, w8, eq
; CHECK-NEXT: sbfx x8, x8, #0, #1
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: zip1 v0.4s, v1.4s, v0.4s
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-NEXT: add sp, sp, #32
; CHECK-NEXT: ret
entry:
%0 = tail call <2 x i1> @llvm.isnan.v2f128(<2 x fp128> %x)
ret <2 x i1> %0
}
define <4 x i1> @isnan_half_vec4(<4 x half> %x) nounwind {
; CHECK-LABEL: isnan_half_vec4:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: movi v1.4h, #124, lsl #8
; CHECK-NEXT: bic v0.4h, #128, lsl #8
; CHECK-NEXT: cmgt v0.4h, v0.4h, v1.4h
; CHECK-NEXT: ret
entry:
%0 = tail call <4 x i1> @llvm.isnan.v4f16(<4 x half> %x)
ret <4 x i1> %0
}
define <4 x i1> @isnan_float_vec4(<4 x float> %x) nounwind {
; CHECK-LABEL: isnan_float_vec4:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: fcmge v1.4s, v0.4s, #0.0
; CHECK-NEXT: fcmlt v0.4s, v0.4s, #0.0
; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b
; CHECK-NEXT: mvn v0.16b, v0.16b
; CHECK-NEXT: xtn v0.4h, v0.4s
; CHECK-NEXT: ret
entry:
%0 = tail call <4 x i1> @llvm.isnan.v4f32(<4 x float> %x)
ret <4 x i1> %0
}
define <4 x i1> @isnan_double_vec4(<4 x double> %x) nounwind {
; CHECK-LABEL: isnan_double_vec4:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: fcmge v2.2d, v0.2d, #0.0
; CHECK-NEXT: fcmlt v0.2d, v0.2d, #0.0
; CHECK-NEXT: fcmge v3.2d, v1.2d, #0.0
; CHECK-NEXT: fcmlt v1.2d, v1.2d, #0.0
; CHECK-NEXT: orr v0.16b, v0.16b, v2.16b
; CHECK-NEXT: orr v1.16b, v1.16b, v3.16b
; CHECK-NEXT: mvn v0.16b, v0.16b
; CHECK-NEXT: xtn v0.2s, v0.2d
; CHECK-NEXT: mvn v1.16b, v1.16b
; CHECK-NEXT: xtn2 v0.4s, v1.2d
; CHECK-NEXT: xtn v0.4h, v0.4s
; CHECK-NEXT: ret
entry:
%0 = tail call <4 x i1> @llvm.isnan.v4f64(<4 x double> %x)
ret <4 x i1> %0
}
define <4 x i1> @isnan_half_vec4_strictfp(<4 x half> %x) strictfp nounwind {
; CHECK-LABEL: isnan_half_vec4_strictfp:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: movi v1.4h, #124, lsl #8
; CHECK-NEXT: bic v0.4h, #128, lsl #8
; CHECK-NEXT: cmgt v0.4h, v0.4h, v1.4h
; CHECK-NEXT: ret
entry:
%0 = tail call <4 x i1> @llvm.isnan.v4f16(<4 x half> %x)
ret <4 x i1> %0
}
define <4 x i1> @isnan_bfloat_vec4_strictfp(<4 x bfloat> %x) strictfp nounwind {
; CHECK-LABEL: isnan_bfloat_vec4_strictfp:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov w8, #32640
; CHECK-NEXT: dup v1.4h, w8
; CHECK-NEXT: bic v0.4h, #128, lsl #8
; CHECK-NEXT: cmgt v0.4h, v0.4h, v1.4h
; CHECK-NEXT: ret
entry:
%0 = tail call <4 x i1> @llvm.isnan.v4bf16(<4 x bfloat> %x)
ret <4 x i1> %0
}
define <4 x i1> @isnan_float_vec4_strictfp(<4 x float> %x) strictfp nounwind {
; CHECK-LABEL: isnan_float_vec4_strictfp:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov w8, #2139095040
; CHECK-NEXT: dup v1.4s, w8
; CHECK-NEXT: bic v0.4s, #128, lsl #24
; CHECK-NEXT: cmgt v0.4s, v0.4s, v1.4s
; CHECK-NEXT: xtn v0.4h, v0.4s
; CHECK-NEXT: ret
entry:
%0 = tail call <4 x i1> @llvm.isnan.v4f32(<4 x float> %x)
ret <4 x i1> %0
}
define <4 x i1> @isnan_double_vec4_strictfp(<4 x double> %x) strictfp nounwind {
; CHECK-LABEL: isnan_double_vec4_strictfp:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov x8, #9223372036854775807
; CHECK-NEXT: mov x9, #9218868437227405312
; CHECK-NEXT: dup v2.2d, x8
; CHECK-NEXT: dup v3.2d, x9
; CHECK-NEXT: and v0.16b, v0.16b, v2.16b
; CHECK-NEXT: and v1.16b, v1.16b, v2.16b
; CHECK-NEXT: cmgt v0.2d, v0.2d, v3.2d
; CHECK-NEXT: cmgt v1.2d, v1.2d, v3.2d
; CHECK-NEXT: xtn v0.2s, v0.2d
; CHECK-NEXT: xtn2 v0.4s, v1.2d
; CHECK-NEXT: xtn v0.4h, v0.4s
; CHECK-NEXT: ret
entry:
%0 = tail call <4 x i1> @llvm.isnan.v4f64(<4 x double> %x)
ret <4 x i1> %0
}
declare i1 @llvm.isnan.f16(half)
declare i1 @llvm.isnan.bf16(bfloat)
declare i1 @llvm.isnan.f32(float)
declare i1 @llvm.isnan.f64(double)
declare i1 @llvm.isnan.f128(fp128)
declare <1 x i1> @llvm.isnan.v1f16(<1 x half>)
declare <1 x i1> @llvm.isnan.v1bf16(<1 x bfloat>)
declare <1 x i1> @llvm.isnan.v1f32(<1 x float>)
declare <1 x i1> @llvm.isnan.v1f64(<1 x double>)
declare <1 x i1> @llvm.isnan.v1f128(<1 x fp128>)
declare <2 x i1> @llvm.isnan.v2f16(<2 x half>)
declare <2 x i1> @llvm.isnan.v2bf16(<2 x bfloat>)
declare <2 x i1> @llvm.isnan.v2f32(<2 x float>)
declare <2 x i1> @llvm.isnan.v2f64(<2 x double>)
declare <2 x i1> @llvm.isnan.v2f128(<2 x fp128>)
declare <4 x i1> @llvm.isnan.v4f16(<4 x half>)
declare <4 x i1> @llvm.isnan.v4bf16(<4 x bfloat>)
declare <4 x i1> @llvm.isnan.v4f32(<4 x float>)
declare <4 x i1> @llvm.isnan.v4f64(<4 x double>)
declare <4 x i1> @llvm.isnan.v4f128(<4 x fp128>)
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