llvm-project/llvm/test/CodeGen/MIR/AMDGPU
Matt Arsenault fae05692a3 CodeGen: Print/parse LLTs in MachineMemOperands
This will currently accept the old number of bytes syntax, and convert
it to a scalar. This should be removed in the near future (I think I
converted all of the tests already, but likely missed a few).

Not sure what the exact syntax and policy should be. We can continue
printing the number of bytes for non-generic instructions to avoid
test churn and only allow non-scalar types for generic instructions.

This will currently print the LLT in parentheses, but accept parsing
the existing integers and implicitly converting to scalar. The
parentheses are a bit ugly, but the parser logic seems unable to deal
without either parentheses or some keyword to indicate the start of a
type.
2021-06-30 16:54:13 -04:00
..
custom-pseudo-source-values.ll CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
expected-target-index-name.mir
intrinsics.mir
invalid-frame-index-invalid-fixed-stack.mir [AMDGPU] Serialize MFInfo::ScavengeFI 2021-05-07 11:15:25 +02:00
invalid-frame-index-invalid-stack.mir [AMDGPU] Serialize MFInfo::ScavengeFI 2021-05-07 11:15:25 +02:00
invalid-frame-index-no-stack.mir [AMDGPU] Serialize MFInfo::ScavengeFI 2021-05-07 11:15:25 +02:00
invalid-frame-index.mir [AMDGPU] Serialize MFInfo::ScavengeFI 2021-05-07 11:15:25 +02:00
invalid-frame-index2.mir [AMDGPU] Serialize MFInfo::ScavengeFI 2021-05-07 11:15:25 +02:00
invalid-target-index-operand.mir
lit.local.cfg
llc-target-cpu-attr-from-cmdline-ir.mir
llc-target-cpu-attr-from-cmdline.mir
load-store-opt-dlc.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
machine-function-info-after-pei.ll [AMDGPU] Serialize MFInfo::ScavengeFI 2021-05-07 11:15:25 +02:00
machine-function-info-dynlds-align-invalid-case.mir
machine-function-info-no-ir.mir [AMDGPU] Serialize MFInfo::ScavengeFI 2021-05-07 11:15:25 +02:00
machine-function-info-register-parse-error1.mir
machine-function-info-register-parse-error2.mir
machine-function-info.ll [AMDGPU] Lower kernel LDS into a sorted structure 2021-05-25 11:29:29 -07:00
machine-metadata-error.mir [MIRParser] Add machine metadata. 2021-06-28 22:29:36 -04:00
machine-metadata.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
mfi-frame-offset-reg-class.mir
mfi-parse-error-frame-offset-reg.mir
mfi-parse-error-scratch-rsrc-reg.mir
mfi-parse-error-stack-ptr-offset-reg.mir
mfi-scratch-rsrc-reg-reg-class.mir
mfi-stack-ptr-offset-reg-class.mir
mir-canon-multi.mir [AMDGPU] Use single cache policy operand 2021-03-15 13:00:59 -07:00
mircanon-memoperands.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
parse-order-reserved-regs.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
stack-id-assert.mir [AMDGPU] Use single cache policy operand 2021-03-15 13:00:59 -07:00
stack-id.mir
subreg-def-is-not-ssa.mir
syncscopes.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
target-flags.mir
target-index-operands.mir [AMDGPU] Use single cache policy operand 2021-03-15 13:00:59 -07:00