32 lines
1.0 KiB
LLVM
32 lines
1.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs -stop-after=finalize-isel < %s | FileCheck %s
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; This test makes sure we match FrameIndex into the base address.
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; Done as a MIR test because eliminateFrameIndex will likely turn it
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; back into an addi.
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declare void @llvm.riscv.vse.nxv1i64(
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<vscale x 1 x i64>,
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<vscale x 1 x i64>*,
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i64);
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define i64 @test(<vscale x 1 x i64> %0) nounwind {
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; CHECK-LABEL: name: test
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; CHECK: bb.0.entry:
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; CHECK: liveins: $v8
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; CHECK: [[COPY:%[0-9]+]]:vr = COPY $v8
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; CHECK: PseudoVSE64_V_M1 [[COPY]], %stack.0.a, 1, 6
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; CHECK: [[LD:%[0-9]+]]:gpr = LD %stack.0.a, 0 :: (dereferenceable load (s64) from %ir.a)
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; CHECK: $x10 = COPY [[LD]]
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; CHECK: PseudoRET implicit $x10
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entry:
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%a = alloca i64
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%b = bitcast i64* %a to <vscale x 1 x i64>*
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call void @llvm.riscv.vse.nxv1i64(
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<vscale x 1 x i64> %0,
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<vscale x 1 x i64>* %b,
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i64 1)
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%c = load i64, i64* %a
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ret i64 %c
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}
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