David Green e9adcbde31 [AArch64] Model Cortex-A55 Q register NEON instructions ... Cortex-A55 has 2 64bit NEON vector units, meaning a 128bit instruction requires taking both units (and can only be issued as the first instruction in a dual issue pair). This patch models that by splitting the WriteV SchedWrite into two - the WriteVd that reads/writes only 64bit operands, and the WriteVq that read/writes 128bit registers. The A55 schedule then uses this distinction to model the WriteVq as taking both resource units, and starting a Schedule Group and WriteVd as taking one as before. I believe this is more correct, even if it does not lead to much better performance. Differential Revision: https://reviews.llvm.org/D108766		2021-09-29 16:55:31 +01:00
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AArch64	[AArch64] Model Cortex-A55 Q register NEON instructions	2021-09-29 16:55:31 +01:00
AMDGPU	[MCA] Adding an AMDGPUCustomBehaviour implementation.	2021-08-24 13:33:58 -07:00
ARM	[MCA][InstrBuilder] Check for the presence of flag VariadicOpsAreDefs.	2021-06-15 09:52:38 +01:00
JSON/X86	[llvm-mca][JSON] Store extra information about driver flags used for the simulation	2021-07-16 09:18:40 +02:00
SystemZ	…
X86	[X86][SLM] Fix ADDQ/SUBQ/CMPEQQ throughput to account for running on either port.	2021-09-24 10:06:14 +01:00
invalid_input_file_name.test	[test] Use host platform specific error message substitution in lit tests	2021-01-29 07:16:30 -05:00
lit.local.cfg	…