142 lines
3.9 KiB
LLVM
142 lines
3.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=aarch64-- | FileCheck %s
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; PR48683 'Quadratic Reciprocity' - and(mul(x,x),2) -> 0
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define i1 @PR48683(i32 %x) {
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; CHECK-LABEL: PR48683:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w0, wzr
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; CHECK-NEXT: ret
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%a = mul i32 %x, %x
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%b = and i32 %a, 2
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%c = icmp ne i32 %b, 0
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ret i1 %c
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}
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define <4 x i1> @PR48683_vec(<4 x i32> %x) {
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; CHECK-LABEL: PR48683_vec:
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; CHECK: // %bb.0:
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; CHECK-NEXT: movi v0.2d, #0000000000000000
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; CHECK-NEXT: ret
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%a = mul <4 x i32> %x, %x
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%b = and <4 x i32> %a, <i32 2, i32 2, i32 2, i32 2>
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%c = icmp ne <4 x i32> %b, zeroinitializer
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ret <4 x i1> %c
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}
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define <4 x i1> @PR48683_vec_undef(<4 x i32> %x) {
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; CHECK-LABEL: PR48683_vec_undef:
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; CHECK: // %bb.0:
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; CHECK-NEXT: movi v1.4s, #2
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; CHECK-NEXT: mul v0.4s, v0.4s, v0.4s
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; CHECK-NEXT: cmtst v0.4s, v0.4s, v1.4s
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; CHECK-NEXT: xtn v0.4h, v0.4s
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; CHECK-NEXT: ret
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%a = mul <4 x i32> %x, %x
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%b = and <4 x i32> %a, <i32 2, i32 2, i32 2, i32 undef>
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%c = icmp ne <4 x i32> %b, zeroinitializer
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ret <4 x i1> %c
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}
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; mul(x,x) - bit[1] is 0, but if demanding the other bits the source must not be undef
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define i64 @combine_mul_self_demandedbits(i64 %x) {
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; CHECK-LABEL: combine_mul_self_demandedbits:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mul x8, x0, x0
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; CHECK-NEXT: and x0, x8, #0xfffffffffffffffd
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; CHECK-NEXT: ret
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%1 = mul i64 %x, %x
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%2 = and i64 %1, -3
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ret i64 %2
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}
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define <4 x i32> @combine_mul_self_demandedbits_vector(<4 x i32> %x) {
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; CHECK-LABEL: combine_mul_self_demandedbits_vector:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mul v0.4s, v0.4s, v0.4s
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; CHECK-NEXT: ret
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%1 = freeze <4 x i32> %x
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%2 = mul <4 x i32> %1, %1
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%3 = and <4 x i32> %2, <i32 -3, i32 -3, i32 -3, i32 -3>
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ret <4 x i32> %3
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}
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define i8 @one_demanded_bit(i8 %x) {
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; CHECK-LABEL: one_demanded_bit:
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; CHECK: // %bb.0:
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; CHECK-NEXT: lsl w8, w0, #6
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; CHECK-NEXT: orr w0, w8, #0xffffffbf
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; CHECK-NEXT: ret
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%m = mul i8 %x, 192 ; 0b1100_0000
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%r = or i8 %m, 191 ; 0b1011_1111
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ret i8 %r
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}
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define <2 x i64> @one_demanded_bit_splat(<2 x i64> %x) {
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; CHECK-LABEL: one_demanded_bit_splat:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w8, #32
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; CHECK-NEXT: shl v0.2d, v0.2d, #5
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; CHECK-NEXT: dup v1.2d, x8
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; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
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; CHECK-NEXT: ret
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%m = mul <2 x i64> %x, <i64 160, i64 160> ; 0b1010_0000
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%r = and <2 x i64> %m, <i64 32, i64 32> ; 0b0010_0000
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ret <2 x i64> %r
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}
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define i32 @one_demanded_low_bit(i32 %x) {
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; CHECK-LABEL: one_demanded_low_bit:
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; CHECK: // %bb.0:
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; CHECK-NEXT: and w0, w0, #0x1
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; CHECK-NEXT: ret
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%m = mul i32 %x, -63 ; any odd number will do
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%r = and i32 %m, 1
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ret i32 %r
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}
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define i16 @squared_one_demanded_low_bit(i16 %x) {
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; CHECK-LABEL: squared_one_demanded_low_bit:
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; CHECK: // %bb.0:
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; CHECK-NEXT: and w0, w0, #0x1
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; CHECK-NEXT: ret
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%mul = mul i16 %x, %x
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%and = and i16 %mul, 1
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ret i16 %and
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}
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define <4 x i32> @squared_one_demanded_low_bit_splat(<4 x i32> %x) {
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; CHECK-LABEL: squared_one_demanded_low_bit_splat:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mvni v1.4s, #1
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; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b
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; CHECK-NEXT: ret
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%mul = mul <4 x i32> %x, %x
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%and = or <4 x i32> %mul, <i32 -2, i32 -2, i32 -2, i32 -2>
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ret <4 x i32> %and
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}
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define i32 @squared_demanded_2_low_bits(i32 %x) {
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; CHECK-LABEL: squared_demanded_2_low_bits:
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; CHECK: // %bb.0:
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; CHECK-NEXT: and w0, w0, #0x1
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; CHECK-NEXT: ret
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%mul = mul i32 %x, %x
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%and = and i32 %mul, 3
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ret i32 %and
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}
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define <2 x i64> @squared_demanded_2_low_bits_splat(<2 x i64> %x) {
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; CHECK-LABEL: squared_demanded_2_low_bits_splat:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov x8, #-2
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; CHECK-NEXT: dup v1.2d, x8
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; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b
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; CHECK-NEXT: ret
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%mul = mul <2 x i64> %x, %x
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%and = or <2 x i64> %mul, <i64 -2, i64 -2>
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ret <2 x i64> %and
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}
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