..
GlobalISel
[SchedModels][CortexA55] Add ASIMD integer instructions
2022-02-17 13:41:57 +03:00
2s-complement-asm.ll
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128bit_load_store.ll
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DAGCombine_vscale.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
O0-pipeline.ll
GlobalISel: Always enable GISelKnownBits for InstructionSelect
2022-01-12 18:57:24 -05:00
O3-pipeline.ll
[MLGO] ML Regalloc Eviction Advisor
2022-01-19 11:00:32 -08:00
PBQP-chain.ll
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PBQP-coalesce-benefit.ll
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PBQP-csr.ll
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PBQP.ll
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PHIElimination-crash.mir
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PHIElimination-debugloc.mir
Make sure PHIElimination doesn't copy debug locations across basic blocks.
2021-04-20 17:03:29 -07:00
README
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Redundantstore.ll
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a55-fuse-address.mir
[AArch64] Improve schedule modelling on the Cortex-A55
2021-09-21 13:03:34 +01:00
a57-csel.ll
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aarch-multipart.ll
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aarch64-2014-08-11-MachineCombinerCrash.ll
Revert "[NFC] remove explicit default value for strboolattr attribute in tests"
2021-05-24 19:43:40 +02:00
aarch64-2014-12-02-combine-soften.ll
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aarch64-DAGCombine-findBetterNeighborChains-crash.ll
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aarch64-a57-fp-load-balancing.ll
Revert "[NFC] remove explicit default value for strboolattr attribute in tests"
2021-05-24 19:43:40 +02:00
aarch64-address-type-promotion-assertion.ll
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aarch64-address-type-promotion.ll
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aarch64-addv.ll
[AArch64] Reassociate integer extending reductions to pairwise addition.
2022-02-03 11:05:48 +00:00
aarch64-avoid-illegal-extract-subvector.ll
[DAGCombine] Check the legality of the index of EXTRACT_SUBVECTOR
2021-08-25 19:33:39 +08:00
aarch64-be-bv.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
aarch64-bf16-dotprod-intrinsics.ll
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aarch64-bf16-ldst-intrinsics.ll
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aarch64-bif-gen.ll
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aarch64-bit-gen.ll
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aarch64-bswap-ext.ll
[AArch64] Combine vector shift instructions in SelectionDAG
2021-05-20 10:50:13 +03:00
aarch64-checkMergeStoreCandidatesForDependencies.ll
[DAGCombiner] Fix dependency analysis in checkMergeStoreCandidatesForDependencies
2022-02-04 08:53:01 +01:00
aarch64-codegen-prepare-atp.ll
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aarch64-combine-fmul-fsub.mir
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aarch64-dup-ext-crash.ll
[AArch64] Regenerate some test checks. NFC
2021-09-08 11:08:32 +01:00
aarch64-dup-ext-scalable.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
aarch64-dup-ext-vectortype-crash.ll
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aarch64-dup-ext.ll
[SchedModels][CortexA55] Add ASIMD integer instructions
2022-02-17 13:41:57 +03:00
aarch64-dup-extract-scalable.ll
[AArch64][SVE] Codegen dup_lane for dup(vector_extract)
2021-03-30 10:35:08 +08:00
aarch64-dynamic-stack-layout.ll
[AArch64InstPrinter] Change printAddSubImm to comment imm value when shifted
2021-08-03 02:28:46 -07:00
aarch64-fix-cortex-a53-835769.ll
[AArch64] Use Feature for A53 Erratum 835769 Fix
2021-12-10 15:09:59 +00:00
aarch64-fold-lslfast.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
aarch64-gep-opt.ll
[AArch64] Enable UseAA globally in the AArch64 backend
2021-04-24 17:51:50 +01:00
aarch64-insert-subvector-undef.ll
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aarch64-interleaved-ld-combine.ll
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aarch64-isel-csinc-type.ll
[DAGCombiner][AArch64] Enhance to fold CSNEG into CSINC instruction
2022-02-16 09:39:38 +08:00
aarch64-isel-csinc.ll
[DAGCombiner][AArch64] Enhance to fold CSNEG into CSINC instruction
2022-02-16 09:39:38 +08:00
aarch64-ldst-modified-baseReg.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
aarch64-ldst-no-premature-sp-pop.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
aarch64-ldst-subsuperReg-no-ldp.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
aarch64-load-ext.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
aarch64-loop-gep-opt.ll
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aarch64-matmul.ll
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aarch64-matrix-umull-smull.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
aarch64-minmaxv.ll
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aarch64-mops-consecutive.ll
[AArch64][SelectionDAG] CodeGen for Armv8.8/9.3 MOPS
2022-01-31 20:56:27 +00:00
aarch64-mops-mte.ll
[AArch64] Do not use ABI alignment for mops.memset.tag
2022-02-01 14:37:53 +01:00
aarch64-mops.ll
[AArch64][SelectionDAG] CodeGen for Armv8.8/9.3 MOPS
2022-01-31 20:56:27 +00:00
aarch64-mov-debug-locs.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
aarch64-mull-masks.ll
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aarch64-named-reg-w18.ll
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aarch64-named-reg-x18.ll
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aarch64-neon-v1i1-setcc.ll
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aarch64-p2align-max-bytes-neoverse.ll
[AArch64][CodeGen] Emit alignment "Max Skip" operand for AArch64 loops
2022-01-05 12:54:31 +00:00
aarch64-p2align-max-bytes.ll
[CodeGen] Emit alignment "Max Skip" operand
2022-01-05 12:54:30 +00:00
aarch64-signedreturnaddress.ll
[AArch64][v8.3A] Avoid inserting implicit landing pads (PACI*SP)
2021-06-24 18:24:32 +01:00
aarch64-smax-constantfold.ll
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aarch64-smov-gen.ll
[AArch64] Generate SMOV in place of sext(fmov(...))
2021-08-25 15:23:22 +01:00
aarch64-smull.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
aarch64-split-and-bitmask-immediate.ll
Third Recommit "[AArch64] Split bitmask immediate of bitwise AND operation"
2021-10-08 11:28:49 +01:00
aarch64-stp-cluster.ll
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aarch64-sve-and-combine-crash.ll
[AArch64ISelLowering] Fix null pointer access in performSVEAndCombine.
2021-09-10 10:36:43 -07:00
aarch64-sve-asm-negative.ll
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aarch64-sve-asm.ll
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aarch64-tail-dup-size.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
aarch64-tbz.ll
[test, AArch64] Fix use of var defined in CHECK-NOT
2021-04-06 10:45:08 +01:00
aarch64-tryBitfieldInsertOpFromOr-crash.ll
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aarch64-unroll-and-jam.ll
[AArch64] Further enable UnrollAndJam
2021-06-04 14:18:49 +01:00
aarch64-vcvtfp2fxs-combine.ll
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aarch64-vector-pcs.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
aarch64-vuzp.ll
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aarch64-wide-shuffle.ll
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aarch64_f16_be.ll
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aarch64_tree_tests.ll
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aarch64_win64cc_vararg.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
aarch64st1.mir
[AArch64] Handle ST1iN instructions in isAArch64FrameOffsetLegal
2021-10-25 17:05:12 +03:00
active_lane_mask.ll
[SchedModels][CortexA55] Add ASIMD integer instructions
2022-02-17 13:41:57 +03:00
adc.ll
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addcarry-crash.ll
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addg_subg.mir
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addimm-mulimm.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
addr-of-ret-addr.ll
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addsub-24bit-imm.mir
[AArch64] Optimize add/sub with immediate through MIPeepholeOpt
2022-01-22 12:39:22 +00:00
addsub-constant-folding.ll
[SchedModels][CortexA55] Add ASIMD integer instructions
2022-02-17 13:41:57 +03:00
addsub-shifted.ll
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addsub.ll
Revert "[AArch64] Adds SUBS and ADDS instructions to the MIPeepholeOpt."
2022-02-13 10:40:23 -07:00
addsub_ext.ll
[AArch64] Rewrite addsub_ext.ll test. NFC
2021-09-10 10:08:57 +01:00
align-down.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
alloca.ll
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analyze-branch.ll
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analyzecmp.ll
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and-mask-removal.ll
[TypePromotion] Extend TypePromotion::isSafeWrap
2021-11-14 11:18:31 +00:00
and-sink.ll
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andandshift.ll
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andcompare.ll
[AArch64] Genereate CCMP from And CSel
2022-02-02 13:48:16 +00:00
andorbrcompare.ll
[AArch64] Attempt to emitConjunction from brcond
2022-02-08 11:27:10 +00:00
apple-latest-cpu.ll
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argument-blocks-array-of-struct.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
argument-blocks.ll
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arm64-2011-03-09-CPSRSpill.ll
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arm64-2011-03-17-AsmPrinterCrash.ll
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arm64-2011-03-21-Unaligned-Frame-Index.ll
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arm64-2011-04-21-CPSRBug.ll
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arm64-2011-10-18-LdStOptBug.ll
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arm64-2012-01-11-ComparisonDAGCrash.ll
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arm64-2012-05-07-DAGCombineVectorExtract.ll
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arm64-2012-05-07-MemcpyAlignBug.ll
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arm64-2012-05-09-LOADgot-bug.ll
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arm64-2012-05-22-LdStOptBug.ll
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arm64-2012-06-06-FPToUI.ll
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arm64-2012-07-11-InstrEmitterBug.ll
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arm64-2013-01-13-ffast-fcmp.ll
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arm64-2013-01-23-frem-crash.ll
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arm64-2013-01-23-sext-crash.ll
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arm64-2013-02-12-shufv8i8.ll
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arm64-AdvSIMD-Scalar.ll
[SchedModels][CortexA55] Add ASIMD integer instructions
2022-02-17 13:41:57 +03:00
arm64-AnInfiniteLoopInDAGCombine.ll
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arm64-EXT-undef-mask.ll
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arm64-aapcs-be.ll
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arm64-aapcs.ll
[AArch64] Emit AssertZExt for i1 arguments
2021-10-11 11:55:11 +03:00
arm64-abi-hfa-args.ll
[clang][AArch64] Correctly align HFA arguments when passed on the stack
2021-04-15 22:58:14 +01:00
arm64-abi-varargs.ll
[AArch64InstPrinter] Change printAddSubImm to comment imm value when shifted
2021-08-03 02:28:46 -07:00
arm64-abi.ll
[AArch64][GlobalISel] Emit extloads for ZExt/SExt values in assignValueToAddress
2021-08-02 14:48:44 -07:00
arm64-abi_align.ll
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arm64-addp.ll
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arm64-addr-mode-folding.ll
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arm64-addr-type-promotion.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
arm64-addrmode.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
arm64-alloc-no-stack-realign.ll
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arm64-alloca-frame-pointer-offset.ll
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arm64-andCmpBrToTBZ.ll
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arm64-ands-bad-peephole.ll
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arm64-anyregcc-crash.ll
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arm64-anyregcc.ll
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arm64-arith-saturating.ll
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arm64-arith.ll
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arm64-arm64-dead-def-elimination-flag.ll
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arm64-assert-zext-sext.ll
[AArch64] Remove redundant ORRWrs which is generated by zero-extend
2021-10-25 09:47:07 +01:00
arm64-atomic-128.ll
AArch64: do not use xzr for ldxp -> stxp dataflow.
2022-02-09 12:29:16 +00:00
arm64-atomic.ll
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arm64-bcc.ll
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arm64-big-endian-bitconverts.ll
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arm64-big-endian-eh.ll
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arm64-big-endian-varargs.ll
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arm64-big-endian-vector-callee.ll
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arm64-big-endian-vector-caller.ll
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arm64-big-imm-offsets.ll
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arm64-big-stack.ll
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arm64-bitfield-extract.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
arm64-blockaddress.ll
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arm64-build-vector.ll
[AArch64] Avoid SCALAR_TO_VECTOR for single FP constant vector.
2021-03-31 10:17:36 +01:00
arm64-builtins-linux.ll
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arm64-call-tailcalls.ll
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arm64-cast-opt.ll
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arm64-ccmp-heuristics.ll
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arm64-ccmp.ll
[AArch64] Genereate CCMP from And CSel
2022-02-02 13:48:16 +00:00
arm64-clrsb.ll
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arm64-coalesce-ext.ll
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arm64-coalescing-MOVi32imm.ll
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arm64-code-model-large-darwin.ll
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arm64-codegen-prepare-extload.ll
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arm64-collect-loh-garbage-crash.ll
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arm64-collect-loh-str.ll
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arm64-collect-loh.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
arm64-complex-ret.ll
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arm64-const-addr.ll
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arm64-constrained-fcmp-no-nans-opt.ll
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arm64-convert-v4f64.ll
[AArch64] Add a tablegen pattern for UZP1.
2021-12-14 11:51:05 +00:00
arm64-copy-tuple.ll
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arm64-crc32.ll
[AArch64] Add support for the 'R' architecture profile.
2021-10-27 12:32:30 +01:00
arm64-crypto.ll
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arm64-cse.ll
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arm64-csel.ll
[DAGCombiner][AArch64] Enhance to support for scalar CSINC
2022-02-07 10:27:48 +08:00
arm64-csldst-mmo.ll
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arm64-custom-call-saved-reg.ll
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arm64-cvt.ll
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arm64-dagcombiner-convergence.ll
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arm64-dagcombiner-dead-indexed-load.ll
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arm64-dagcombiner-load-slicing.ll
…
arm64-darwin-cc.ll
…
arm64-dead-def-frame-index.ll
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arm64-dead-register-def-bug.ll
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arm64-detect-vec-redux.ll
Revert "[NFC] remove explicit default value for strboolattr attribute in tests"
2021-05-24 19:43:40 +02:00
arm64-dup.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
arm64-early-ifcvt.ll
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arm64-elf-calls.ll
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arm64-elf-constpool.ll
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arm64-ext.ll
…
arm64-extend-int-to-fp.ll
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arm64-extend.ll
…
arm64-extload-knownzero.ll
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arm64-extract.ll
…
arm64-extract_subvector.ll
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arm64-fast-isel-addr-offset.ll
…
arm64-fast-isel-alloca.ll
…
arm64-fast-isel-br.ll
…
arm64-fast-isel-call.ll
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arm64-fast-isel-conversion-fallback.ll
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arm64-fast-isel-conversion.ll
…
arm64-fast-isel-fcmp.ll
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arm64-fast-isel-gv.ll
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arm64-fast-isel-icmp.ll
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arm64-fast-isel-indirectbr.ll
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arm64-fast-isel-intrinsic.ll
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arm64-fast-isel-materialize.ll
[AArch64] Default to zero-cycle-zeroing FP registers
2021-04-06 09:47:50 +01:00
arm64-fast-isel-noconvert.ll
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arm64-fast-isel-rem.ll
[FastISel] Remove kill tracking
2021-04-03 15:50:13 +02:00
arm64-fast-isel-ret.ll
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arm64-fast-isel-store.ll
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arm64-fast-isel.ll
…
arm64-fastcc-tailcall.ll
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arm64-fastisel-gep-promote-before-add.ll
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arm64-fcmp-opt.ll
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arm64-fcopysign.ll
[SchedModels][CortexA55] Add ASIMD integer instructions
2022-02-17 13:41:57 +03:00
arm64-fixed-point-scalar-cvt-dagcombine.ll
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arm64-fma-combine-with-fpfusion.ll
Revert "[NFC] remove explicit default value for strboolattr attribute in tests"
2021-05-24 19:43:40 +02:00
arm64-fma-combines.ll
[AArch64] Add Machine InstCombiner patterns for FMUL indexed variant
2021-11-09 15:30:19 +03:00
arm64-fmadd.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
arm64-fmax-safe.ll
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arm64-fmax.ll
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arm64-fminv.ll
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arm64-fml-combines.ll
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arm64-fmuladd.ll
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arm64-fold-address.ll
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arm64-fold-lsl.ll
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arm64-fp-contract-zero.ll
[AArch64] Default to zero-cycle-zeroing FP registers
2021-04-06 09:47:50 +01:00
arm64-fp-imm-size.ll
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arm64-fp-imm.ll
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arm64-fp.ll
Revert "[NFC] remove explicit default value for strboolattr attribute in tests"
2021-05-24 19:43:40 +02:00
arm64-fp128-folding.ll
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arm64-fp128.ll
[AArch64InstPrinter] Change printAddSubImm to comment imm value when shifted
2021-08-03 02:28:46 -07:00
arm64-fpcr.ll
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arm64-frame-index.ll
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arm64-global-address.ll
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arm64-hello.ll
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arm64-homogeneous-prolog-epilog-bad-outline.mir
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arm64-homogeneous-prolog-epilog-frame-tail.ll
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arm64-homogeneous-prolog-epilog-no-helper.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
arm64-homogeneous-prolog-epilog.ll
[AArch64] Fix Local Deallocation for Homogeneous Prolog/Epilog
2021-07-25 10:51:11 -07:00
arm64-i16-subreg-extract.ll
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arm64-icmp-opt.ll
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arm64-indexed-memory.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
arm64-indexed-vector-ldst-2.ll
Revert "[NFC] remove explicit default value for strboolattr attribute in tests"
2021-05-24 19:43:40 +02:00
arm64-indexed-vector-ldst.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
arm64-inline-asm-error-I.ll
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arm64-inline-asm-error-J.ll
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arm64-inline-asm-error-K.ll
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arm64-inline-asm-error-L.ll
…
arm64-inline-asm-error-M.ll
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arm64-inline-asm-error-N.ll
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arm64-inline-asm-zero-reg-error.ll
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arm64-inline-asm.ll
[Tests] Add elementtype attribute to indirect inline asm operands (NFC)
2022-01-06 14:23:51 +01:00
arm64-instruction-mix-remarks.ll
Revert "[AArch64] Adds SUBS and ADDS instructions to the MIPeepholeOpt."
2022-02-13 10:40:23 -07:00
arm64-isel-or.ll
[AArch64ISelDAGToDAG] Fix ORRWrs/ORRXrs usefulbits calculation bug
2021-07-06 00:38:42 +08:00
arm64-join-reserved.ll
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arm64-jumptable.ll
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arm64-large-frame.ll
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arm64-ld-from-st.ll
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arm64-ld1.ll
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arm64-ldp-aa.ll
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arm64-ldp-cluster.ll
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arm64-ldp.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
arm64-ldst-unscaled-pre-post.mir
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arm64-ldur.ll
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arm64-ldxr-stxr.ll
Add test update for a11d9a1f48 which disables fallbacks.
2021-07-27 12:16:06 -07:00
arm64-leaf.ll
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arm64-long-shift.ll
[DAG] Add a generic expansion for SHIFT_PARTS opcodes using funnel shifts
2021-05-07 13:12:30 +01:00
arm64-memcpy-inline.ll
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arm64-memset-inline.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
arm64-memset-to-bzero-pgso.ll
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arm64-memset-to-bzero.ll
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arm64-misaligned-memcpy-inline.ll
[AArch64] Regenerate some test checks. NFC
2021-09-12 12:13:29 +01:00
arm64-misched-basic-A53.ll
Revert "[NFC] remove explicit default value for strboolattr attribute in tests"
2021-05-24 19:43:40 +02:00
arm64-misched-basic-A57.ll
Revert "[NFC] remove explicit default value for strboolattr attribute in tests"
2021-05-24 19:43:40 +02:00
arm64-misched-forwarding-A53.ll
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arm64-misched-memdep-bug.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
arm64-misched-multimmo.ll
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arm64-movi.ll
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arm64-mte.ll
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arm64-mul.ll
…
arm64-named-reg-alloc.ll
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arm64-named-reg-notareg.ll
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arm64-narrow-st-merge.ll
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arm64-neg.ll
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arm64-neon-2velem-high.ll
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arm64-neon-2velem.ll
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arm64-neon-3vdiff.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
arm64-neon-aba-abd.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
arm64-neon-across.ll
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arm64-neon-add-pairwise.ll
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arm64-neon-add-sub.ll
…
arm64-neon-copy.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
arm64-neon-copyPhysReg-tuple.ll
…
arm64-neon-mul-div-cte.ll
…
arm64-neon-mul-div.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
arm64-neon-scalar-by-elem-mul.ll
…
arm64-neon-select_cc.ll
…
arm64-neon-simd-ldst-one.ll
…
arm64-neon-simd-shift.ll
…
arm64-neon-simd-vget.ll
…
arm64-neon-v1i1-setcc.ll
…
arm64-neon-v8.1a.ll
[ARM][AArch64] Introduce qrdmlah and qrdmlsh intrinsics
2022-01-27 19:19:46 +00:00
arm64-neon-vector-list-spill.ll
…
arm64-neon-vector-shuffle-extract.ll
…
arm64-nvcast.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
arm64-opt-remarks-lazy-bfi.ll
…
arm64-patchpoint-scratch-regs.ll
…
arm64-patchpoint-webkit_jscc.ll
…
arm64-patchpoint.ll
…
arm64-pic-local-symbol.ll
…
arm64-platform-reg.ll
…
arm64-popcnt.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
arm64-prefetch.ll
…
arm64-preserve-most.ll
…
arm64-promote-const-complex-initializers.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
arm64-promote-const.ll
…
arm64-raddhn-combine.ll
[AArch64] Add a tablegen pattern for RADDHN/RADDHN2.
2021-12-24 11:13:25 +00:00
arm64-redzone.ll
…
arm64-reg-copy-noneon.ll
…
arm64-register-offset-addressing.ll
…
arm64-register-pairing.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
arm64-regress-f128csel-flags.ll
…
arm64-regress-interphase-shift.ll
…
arm64-regress-opt-cmp.mir
…
arm64-reserve-call-saved-reg.ll
…
arm64-reserved-arg-reg-call-error.ll
…
arm64-return-vector.ll
…
arm64-returnaddr.ll
…
arm64-rev.ll
[GlobalISel] Fold or of shifts with constant amount to funnel shift.
2022-01-24 10:43:32 +05:30
arm64-rounding.ll
Revert "[NFC] remove explicit default value for strboolattr attribute in tests"
2021-05-24 19:43:40 +02:00
arm64-scaled_iv.ll
…
arm64-scvt.ll
…
arm64-setcc-int-to-fp-combine.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
arm64-shifted-sext.ll
…
arm64-shrink-v1i64.ll
…
arm64-shrink-wrapping.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
arm64-simd-scalar-to-vector.ll
…
arm64-simplest-elf.ll
…
arm64-sincos.ll
…
arm64-sitofp-combine-chains.ll
…
arm64-sli-sri-opt.ll
[SchedModels][CortexA55] Add ASIMD integer instructions
2022-02-17 13:41:57 +03:00
arm64-smaxv.ll
…
arm64-sminv.ll
…
arm64-spill-lr.ll
…
arm64-spill-remarks-treshold-hotness.ll
Re-land [GreedyRA ORE] Add Cost of spill locations into remark
2021-04-20 16:21:07 +07:00
arm64-spill-remarks.ll
Re-land [GreedyRA ORE] Add Cost of spill locations into remark
2021-04-20 16:21:07 +07:00
arm64-spill.ll
…
arm64-sqshl-uqshl-i64Contant.ll
…
arm64-sqxtn2-combine.ll
[AArch64] Add a tablegen pattern for SQXTN2.
2021-12-23 15:19:13 +00:00
arm64-srl-and.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
arm64-st1.ll
…
arm64-stack-no-frame.ll
…
arm64-stackmap-nops.ll
…
arm64-stackmap.ll
…
arm64-stackpointer.ll
…
arm64-stacksave.ll
…
arm64-storebytesmerge.ll
Revert "[NFC] remove explicit default value for strboolattr attribute in tests"
2021-05-24 19:43:40 +02:00
arm64-stp-aa.ll
…
arm64-stp.ll
…
arm64-strict-align.ll
…
arm64-stur.ll
…
arm64-subsections.ll
…
arm64-subvector-extend.ll
[SchedModels][CortexA55] Add ASIMD integer instructions
2022-02-17 13:41:57 +03:00
arm64-summary-remarks.ll
…
arm64-swizzle-tbl-i16-layout.ll
…
arm64-tbl.ll
…
arm64-this-return.ll
[TargetLowering] Only inspect attributes in the arguments for ArgListEntry
2021-05-18 14:30:22 -07:00
arm64-tls-darwin.ll
…
arm64-tls-dynamic-together.ll
…
arm64-tls-dynamics.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
arm64-tls-initial-exec.ll
…
arm64-tls-local-exec.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
arm64-trap.ll
[GlobalISel] Implement support for the "trap-func-name" attribute.
2021-09-20 14:32:01 -07:00
arm64-triv-disjoint-mem-access.ll
Revert "[NFC] remove explicit default value for strboolattr attribute in tests"
2021-05-24 19:43:40 +02:00
arm64-trn.ll
…
arm64-trunc-store.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
arm64-umaxv.ll
…
arm64-uminv.ll
…
arm64-umov.ll
…
arm64-unaligned_ldst.ll
…
arm64-uzp.ll
…
arm64-vaargs.ll
…
arm64-vabs.ll
[AArch64] Reassociate integer extending reductions to pairwise addition.
2022-02-03 11:05:48 +00:00
arm64-vadd.ll
…
arm64-vaddlv.ll
…
arm64-vaddv.ll
…
arm64-variadic-aapcs.ll
[AArch64] Enable UseAA globally in the AArch64 backend
2021-04-24 17:51:50 +01:00
arm64-vbitwise.ll
[AArch64] Lower bitreverse in ISel
2021-05-17 13:35:27 +01:00
arm64-vclz.ll
…
arm64-vcmp.ll
…
arm64-vcnt.ll
…
arm64-vcombine.ll
…
arm64-vcvt.ll
…
arm64-vcvt_f.ll
[AArch64] Prefer fmov over orr v.16b when copying f32/f64
2021-08-03 17:25:40 +01:00
arm64-vcvt_f32_su32.ll
…
arm64-vcvt_n.ll
…
arm64-vcvt_su32_f32.ll
…
arm64-vcvtxd_f32_f64.ll
…
arm64-vecCmpBr.ll
…
arm64-vecFold.ll
…
arm64-vector-ext.ll
…
arm64-vector-imm.ll
…
arm64-vector-insertion.ll
[AArch64] Prefer fmov over orr v.16b when copying f32/f64
2021-08-03 17:25:40 +01:00
arm64-vector-ldst.ll
…
arm64-vext.ll
…
arm64-vext_reverse.ll
…
arm64-vfloatintrinsics.ll
Update @llvm.powi to handle different int sizes for the exponent
2021-06-17 09:38:28 +02:00
arm64-vhadd.ll
[SchedModels][CortexA55] Add ASIMD integer instructions
2022-02-17 13:41:57 +03:00
arm64-vhsub.ll
…
arm64-virtual_base.ll
[AArch64] Enable UseAA globally in the AArch64 backend
2021-04-24 17:51:50 +01:00
arm64-vmax.ll
…
arm64-vminmaxnm.ll
…
arm64-vmovn.ll
…
arm64-vmul.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
arm64-volatile.ll
…
arm64-vpopcnt.ll
…
arm64-vqadd.ll
…
arm64-vqsub.ll
…
arm64-vselect.ll
…
arm64-vsetcc_fp.ll
…
arm64-vshift.ll
Recommit "[AArch64] Custom lower <4 x i8> loads"
2021-06-30 09:18:06 +01:00
arm64-vshr.ll
[AArch64] Convert sra(X, elt_size(X)-1) to cmlt(X, 0)
2021-12-14 16:03:02 +00:00
arm64-vshuffle.ll
Revert "[CodeGen][AArch64] Ensure isSExtCheaperThanZExt returns true for negative constants"
2022-01-13 15:59:43 +00:00
arm64-vsqrt.ll
…
arm64-vsra.ll
…
arm64-vsub.ll
…
arm64-weak-reference.ll
…
arm64-windows-calls.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
arm64-windows-tailcall.ll
…
arm64-xaluo.ll
[AArch64] Regenerate arith overflow test, and add a few more select tests. NFC
2022-01-06 11:02:14 +00:00
arm64-zero-cycle-regmov.ll
…
arm64-zero-cycle-zeroing.ll
[CodeGen][AArch64] Fix typo in arm64-zero-cycle-zeroing.ll
2022-02-01 12:08:06 +00:00
arm64-zeroreg.ll
…
arm64-zext.ll
…
arm64-zextload-unscaled.ll
…
arm64-zip.ll
…
arm64_32-addrs.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
arm64_32-atomics.ll
Revert "[CodeGen][AArch64] Ensure isSExtCheaperThanZExt returns true for negative constants"
2022-01-13 15:59:43 +00:00
arm64_32-fastisel.ll
…
arm64_32-frame-pointers.ll
…
arm64_32-gep-sink.ll
…
arm64_32-memcpy.ll
…
arm64_32-neon.ll
…
arm64_32-null.ll
…
arm64_32-pointer-extend.ll
…
arm64_32-stack-pointers.ll
…
arm64_32-tls.ll
…
arm64_32-va.ll
…
arm64_32.ll
[Tests] Add elementtype attribute to indirect inline asm operands (NFC)
2022-01-06 14:23:51 +01:00
asm-large-immediate.ll
…
asm-print-comments.ll
…
asm-srcloc.ll
…
assertion-rc-mismatch.ll
…
atomic-ops-lse.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
atomic-ops-not-barriers.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
atomic-ops.ll
[AArch64] Enable type promotion for AArch64
2021-09-29 15:13:12 +01:00
atomicrmw-O0.ll
[AArch64InstPrinter] Change printAddSubImm to comment imm value when shifted
2021-08-03 02:28:46 -07:00
atomicrmw-xchg-fp.ll
[AArch64InstPrinter] Change printAddSubImm to comment imm value when shifted
2021-08-03 02:28:46 -07:00
autoupgrade-aarch64-neon-addp-float.ll
…
basic-pic.ll
[AArch64][ELF] Prefer to lower MC_GlobalAddress operands to .Lfoo$local
2021-05-07 09:44:26 -07:00
bcmp-inline-small.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
bf16-convert-intrinsics.ll
…
bf16-vector-bitcast.ll
[AArch64] Prefer fmov over orr v.16b when copying f32/f64
2021-08-03 17:25:40 +01:00
bf16-vector-shuffle.ll
[AArch64] Prefer fmov over orr v.16b when copying f32/f64
2021-08-03 17:25:40 +01:00
bf16.ll
[AArch64] Add isel for bitcasting between bfloat and half types.
2022-01-29 11:26:13 +00:00
bics.ll
…
big-callframe.ll
…
bisect-post-ra-machine-sink.mir
…
bitcast-promote-widen.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
bitcast-v2i8.ll
…
bitcast.ll
…
bitfield-extract.ll
[TargetLowering] Only inspect attributes in the arguments for ArgListEntry
2021-05-18 14:30:22 -07:00
bitfield-insert-0.ll
…
bitfield-insert.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
bitfield.ll
…
bitreverse.ll
[AArch64] Optimise bitreverse lowering in ISel
2021-06-02 12:51:12 +01:00
blockaddress.ll
…
bool-ext-inc.ll
…
bool-loads.ll
…
br-cond-not-merge.ll
…
br-to-eh-lpad.ll
…
br-undef-cond.ll
…
branch-folder-merge-mmos.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
branch-folder-oneinst.mir
…
branch-relax-alignment.ll
Revert "Revert "Temporarily do not drop volatile stores before unreachable""
2021-07-09 11:44:34 -04:00
branch-relax-asm.ll
[SimplifyCFG] Tail-merging all blocks with `ret` terminator
2021-06-24 13:15:39 +03:00
branch-relax-bcc.ll
[AArch64InstPrinter] Change printAddSubImm to comment imm value when shifted
2021-08-03 02:28:46 -07:00
branch-relax-block-size.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
branch-relax-cbz.ll
[AArch64InstPrinter] Change printAddSubImm to comment imm value when shifted
2021-08-03 02:28:46 -07:00
branch-target-enforcement-indirect-calls.ll
…
branch-target-enforcement.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
breg.ll
…
bswap-known-bits.ll
[SDAG] add demanded bits transform for bswap
2022-01-17 18:25:42 -05:00
bti-branch-relaxation.ll
Revert "[NFC] remove explicit default value for strboolattr attribute in tests"
2021-05-24 19:43:40 +02:00
build-one-lane.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
build-pair-isel.ll
…
build-vector-extract.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
byval-type.ll
…
call-rv-marker.ll
[AArch64][GlobalISel] Implement support for clang.arc.attachedcall call operand bundles.
2022-02-16 17:35:22 -08:00
callbr-asm-label.ll
[llvm][test] rewrite callbr to use i rather than X constraint NFC
2022-01-11 11:31:08 -08:00
callbr-asm-obj-file.ll
[llvm][test] rewrite callbr to use i rather than X constraint NFC
2022-01-11 11:31:08 -08:00
callee-save.ll
…
ccmp-successor-probs.mir
…
cfguard-checks.ll
[SimplifyCFG] Tail-merging all blocks with `ret` terminator
2021-06-24 13:15:39 +03:00
cfguard-module-flag.ll
…
cfi_restore.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
cfinv-def-nzcv.mir
…
cfinv-use-nzcv.mir
…
cgp-trivial-phi-node.ll
…
cgp-usubo.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
check-sign-bit-before-extension.ll
Revert "[SimplifyCFG] Start redesigning `FoldTwoEntryPHINode()`."
2022-02-03 12:32:50 +03:00
chkstk.ll
…
clang-section-macho.ll
…
cls.ll
…
cluster-frame-index.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
cmp-bool.ll
…
cmp-const-max.ll
…
cmp-frameindex.ll
[Test] Regenerate some of llc test checks using auto updater
2021-10-28 16:18:30 +07:00
cmp-select-sign.ll
[SchedModels][CortexA55] Add ASIMD integer instructions
2022-02-17 13:41:57 +03:00
cmp-to-cmn.ll
Fix typo of colon to semicolon in lit tests
2021-10-09 10:03:50 +08:00
cmpwithshort.ll
…
cmpxchg-O0.ll
…
cmpxchg-idioms.ll
Revert "[CodeGen][AArch64] Ensure isSExtCheaperThanZExt returns true for negative constants"
2022-01-13 15:59:43 +00:00
cmpxchg-lse-even-regs.ll
…
code-model-large-abs.ll
…
code-model-tiny-abs.ll
…
combine-and-like.ll
…
combine-andintoload.ll
Revert "[DAG] Extend SearchForAndLoads with any_extend handling"
2022-02-01 20:18:40 +00:00
combine-comparisons-by-cse.ll
Revert "[SimplifyCFG] Start redesigning `FoldTwoEntryPHINode()`."
2022-02-03 12:32:50 +03:00
combine-mul.ll
[SDAG] try to fold one-demanded-bit-of-multiply
2022-02-07 17:24:35 -05:00
compare-branch.ll
…
compiler-ident.ll
…
complex-copy-noneon.ll
…
complex-fp-to-int.ll
…
complex-int-to-fp.ll
…
concat-vector.ll
[AArch64] NFC: Clarify and auto-generate some CodeGen tests.
2022-01-24 17:42:37 +00:00
concat_vector-scalar-combine.ll
…
concat_vector-truncate-combine.ll
[DAG] foldConstantFPMath - fold vector splats as well as scalar constants
2021-12-17 15:19:26 +00:00
concat_vector-truncated-scalar-combine.ll
…
cond-br-tuning.ll
[SimplifyCFG] Tail-merging all blocks with `ret` terminator
2021-06-24 13:15:39 +03:00
cond-sel-value-prop.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
cond-sel.ll
…
const-shift-of-constmasked.ll
…
consthoist-gep.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
convertphitype.ll
…
copyprop.mir
…
cpus.ll
[Driver][AArch64]Add driver support for neoverse-512tvb target
2021-10-28 09:08:40 +01:00
csel-zero-float.ll
…
csinc-cmp-removal.mir
[AArch64] Fix comparison peephole opt with non-0/1 immediate (PR51476)
2021-08-15 12:35:52 +02:00
csr-split.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
ctpop-nonean.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
cvt-fp-int-fp.ll
…
cxx-tlscc.ll
AArch64: don't claim to preserve registers used by prologue code
2022-01-10 12:27:04 +00:00
dag-combine-insert-subvector.ll
[SVE] Remove checks for warnings in scalable-vector tests.
2021-04-07 15:59:32 +01:00
dag-combine-invaraints.ll
Revert "[NFC] remove explicit default value for strboolattr attribute in tests"
2021-05-24 19:43:40 +02:00
dag-combine-lifetime-end-store-typesize.ll
[SVE] Remove checks for warnings in scalable-vector tests.
2021-04-07 15:59:32 +01:00
dag-combine-mul-shl.ll
…
dag-combine-select.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
dag-combine-trunc-build-vec.ll
[AArch64] Add a tablegen pattern for UZP1.
2021-12-14 11:51:05 +00:00
dag-numsignbits.ll
[SchedModels][CortexA55] Add ASIMD integer instructions
2022-02-17 13:41:57 +03:00
dbg-declare-tag-offset.ll
…
dbg-value-tag-offset.ll
…
debug-info-sve-dbg-declare.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
debug-info-sve-dbg-value.mir
…
debugtrap.ll
[GlobalISel] Implement support for the "trap-func-name" attribute.
2021-09-20 14:32:01 -07:00
directcond.ll
…
div-rem-pair-recomposition-signed.ll
[SchedModels][CortexA55] Add ASIMD integer instructions
2022-02-17 13:41:57 +03:00
div-rem-pair-recomposition-unsigned.ll
[SchedModels][CortexA55] Add ASIMD integer instructions
2022-02-17 13:41:57 +03:00
div_minsize.ll
[AArch64] Convert sra(X, elt_size(X)-1) to cmlt(X, 0)
2021-12-14 16:03:02 +00:00
divrem.ll
…
dllexport.ll
…
dllimport.ll
…
dont-shrink-wrap-stack-mayloadorstore.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
dont-take-over-the-world.ll
…
dp-3source.ll
…
dp1.ll
…
dp2.ll
…
dwarf-cfi.ll
…
early-ifcvt-regclass-mismatch.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
early-ifcvt-same-value.mir
[EarlyIfConversion] Avoid producing selects with identical operands
2021-04-30 15:51:14 -07:00
eh_recoverfp.ll
…
ehcontguard.ll
…
elf-globals-pic.ll
…
elf-globals-static.ll
[AArch64][ELF] Prefer to lower MC_GlobalAddress operands to .Lfoo$local
2021-05-07 09:44:26 -07:00
elf-preemption.ll
[AArch64][ELF] Prefer to lower MC_GlobalAddress operands to .Lfoo$local
2021-05-07 09:44:26 -07:00
elim-dead-mi.mir
[Aarch64] Correct register class for pseudo instructions
2021-09-09 14:31:49 -04:00
eliminate-trunc.ll
…
emutls.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
emutls_generic.ll
…
eon.ll
…
eor3.ll
Teach the AArch64 backend patterns to generate the EOR3 instruction.
2021-08-30 20:01:08 +00:00
expand-blr-rvmarker-pseudo.mir
[ObjCARC] Require the function argument in the clang.arc.attachedcall bundle.
2022-01-28 12:41:45 -08:00
expand-movi-renamable.mir
…
expand-select.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
expand-subs-pseudo.mir
[AArch64] Avoid adding duplicate implicit operands when expanding pseudo insts.
2021-09-07 17:11:58 +08:00
expand-vector-rot.ll
[SchedModels][CortexA55] Add ASIMD integer instructions
2022-02-17 13:41:57 +03:00
ext-narrow-index.ll
[AArch64] NFC: Clarify and auto-generate some CodeGen tests.
2022-01-24 17:42:37 +00:00
extern-weak.ll
…
extra-callee-save.mir
…
extract-bits.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
extract-insert.ll
…
extract-lowbits.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
extract-sext-zext.ll
[AArch64][Global ISel] Add sext/zext of vector extract improvements
2021-09-07 21:17:51 +01:00
extract.ll
…
f16-convert.ll
…
f16-imm.ll
[AArch64] Regenerate some test checks. NFC
2021-09-08 11:08:32 +01:00
f16-instructions.ll
[SchedModels][CortexA55] Add ASIMD integer instructions
2022-02-17 13:41:57 +03:00
fabs.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
fadd-combines.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
faddp-half.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
faddp.ll
…
falkor-hwpf-fix.ll
…
falkor-hwpf-fix.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
falkor-hwpf.ll
…
fast-isel-address-extends.ll
…
fast-isel-addressing-modes.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
fast-isel-assume.ll
…
fast-isel-atomic.ll
…
fast-isel-branch-cond-mask.ll
…
fast-isel-branch-cond-split.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
fast-isel-branch-uncond-debug.ll
…
fast-isel-branch_weights.ll
…
fast-isel-call-return.ll
…
fast-isel-cbz.ll
…
fast-isel-cmp-branch.ll
…
fast-isel-cmp-vec.ll
Revert "[CodeGen][AArch64] Ensure isSExtCheaperThanZExt returns true for negative constants"
2022-01-13 15:59:43 +00:00
fast-isel-cmpxchg.ll
…
fast-isel-dbg.ll
…
fast-isel-erase.ll
…
fast-isel-folded-shift.ll
…
fast-isel-folding.ll
…
fast-isel-fpimm.ll
[AArch64] Materialize FP constant in code for large code model
2021-04-07 21:02:05 +02:00
fast-isel-gep.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
fast-isel-int-ext.ll
…
fast-isel-int-ext2.ll
…
fast-isel-int-ext3.ll
…
fast-isel-int-ext4.ll
…
fast-isel-int-ext5.ll
…
fast-isel-intrinsic.ll
…
fast-isel-logic-op.ll
…
fast-isel-memcpy.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
fast-isel-mul.ll
…
fast-isel-runtime-libcall.ll
…
fast-isel-sdiv.ll
[AArch64InstPrinter] Change printAddSubImm to comment imm value when shifted
2021-08-03 02:28:46 -07:00
fast-isel-select.ll
[AArch64] Prefer fmov over orr v.16b when copying f32/f64
2021-08-03 17:25:40 +01:00
fast-isel-shift.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
fast-isel-sp-adjust.ll
…
fast-isel-sqrt.ll
…
fast-isel-switch-phi.ll
…
fast-isel-tail-call.ll
…
fast-isel-tbz.ll
…
fast-isel-trunc.ll
…
fast-isel-vector-arithmetic.ll
…
fast-isel-vret.ll
…
fast-regalloc-empty-bb-with-liveins.mir
…
fastcc-reserved.ll
…
fastcc.ll
…
fastisel-debugvalue-undef.ll
…
fcmp.ll
…
fcopysign.ll
[SchedModels][CortexA55] Add ASIMD integer instructions
2022-02-17 13:41:57 +03:00
fcsel-zero.ll
Revert "[NFC] remove explicit default value for strboolattr attribute in tests"
2021-05-24 19:43:40 +02:00
fcvt-fixed.ll
[AArch64] Combine fptoi.sat(fmul) to fixed point cvtf
2021-11-08 10:07:34 +00:00
fcvt-int.ll
…
fcvt_combine.ll
[SelectionDAG] Add FP_TO_UINT_SAT/FP_TO_SINT_SAT to computeKnownBits/computeNumSignBits.
2022-01-09 17:48:05 -08:00
fdiv-combine.ll
[DAGCombiner] Fix invalid size request in combineRepeatedFPDivisors
2022-01-28 17:01:08 +00:00
fdiv_combine.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
fence-singlethread.ll
…
fjcvtzs.ll
…
fjcvtzs.mir
…
flags-multiuse.ll
…
floatdp_1source.ll
[AArch64] Rewrite floatdp_1source.ll test. NFC
2021-09-08 23:00:34 +01:00
floatdp_2source.ll
…
fmov-imm-licm.ll
…
fold-constants.ll
…
fold-global-offsets.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
fp-cond-sel.ll
…
fp-const-fold.ll
…
fp-dp3.ll
…
fp-intrinsics.ll
…
fp16-fmla.ll
…
fp16-v4-instructions.ll
[AArch64] Prefer fmov over orr v.16b when copying f32/f64
2021-08-03 17:25:40 +01:00
fp16-v8-instructions.ll
[AArch64] Add a tablegen pattern for UZP1.
2021-12-14 11:51:05 +00:00
fp16-v16-instructions.ll
[AArch64] Regenerate fp16 tests.
2021-08-02 13:05:16 -07:00
fp16-vector-bitcast.ll
[AArch64] Prefer fmov over orr v.16b when copying f32/f64
2021-08-03 17:25:40 +01:00
fp16-vector-load-store.ll
…
fp16-vector-nvcast.ll
…
fp16-vector-shuffle.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
fp16_intrinsic_lane.ll
[AArch64] Regenerate some test checks. NFC
2021-09-08 11:08:32 +01:00
fp16_intrinsic_scalar_1op.ll
…
fp16_intrinsic_scalar_2op.ll
…
fp16_intrinsic_scalar_3op.ll
DAG: Fix incorrect folding of fmul -1 to fneg
2021-09-14 21:25:02 -04:00
fp16_intrinsic_vector_1op.ll
…
fp16_intrinsic_vector_2op.ll
…
fp16_intrinsic_vector_3op.ll
…
fp128-folding.ll
…
fpclamptosat.ll
[DAG] Create fptoui.sat from clamped fptoui
2022-01-26 08:37:44 +00:00
fpclamptosat_vec.ll
[DAG] Create fptoui.sat from clamped fptoui
2022-01-26 08:37:44 +00:00
fpconv-vector-op-scalarize.ll
…
fpenv.ll
…
fpimm.ll
[AArch64] Materialize FP constant in code for large code model
2021-04-07 21:02:05 +02:00
fptosi-sat-scalar.ll
[AArch64] Improve fptosi.sat lowering
2021-10-15 11:12:23 +01:00
fptosi-sat-vector.ll
[SchedModels][CortexA55] Add ASIMD integer instructions
2022-02-17 13:41:57 +03:00
fptosi-strictfp.ll
[AArch64] provide strictfp attributes in test file
2021-08-26 16:56:43 +01:00
fptoui-sat-scalar.ll
[SelectionDAG] Add FP_TO_UINT_SAT/FP_TO_SINT_SAT to computeKnownBits/computeNumSignBits.
2022-01-09 17:48:05 -08:00
fptoui-sat-vector.ll
[SchedModels][CortexA55] Add ASIMD integer instructions
2022-02-17 13:41:57 +03:00
fptouint-i8-zext.ll
…
frameaddr.ll
…
framelayout-fp-csr.ll
…
framelayout-frame-record.mir
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
framelayout-offset-immediate-change.mir
…
framelayout-scavengingslot.mir
…
framelayout-sve-basepointer.mir
…
framelayout-sve-calleesaves-fix.mir
…
framelayout-sve-scavengingslot.mir
…
framelayout-sve.mir
…
framelayout-unaligned-fp.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
free-zext.ll
…
frintn.ll
…
ftrunc.ll
Revert "[NFC] remove explicit default value for strboolattr attribute in tests"
2021-05-24 19:43:40 +02:00
func-argpassing.ll
…
func-calls.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
funclet-local-stack-size.ll
…
funclet-match-add-sub-stack.ll
…
funcptr_cast.ll
…
function-info-noredzone-present.ll
…
function-subtarget-features.ll
…
funnel-shift-rot.ll
[SchedModels][CortexA55] Add ASIMD integer instructions
2022-02-17 13:41:57 +03:00
funnel-shift.ll
Revert "[CodeGen][AArch64] Ensure isSExtCheaperThanZExt returns true for negative constants"
2022-01-18 08:40:20 +00:00
gep-nullptr.ll
…
ghc-cc.ll
…
global-alignment.ll
…
global-merge-1.ll
…
global-merge-2.ll
…
global-merge-3.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
global-merge-4.ll
…
global-merge-group-by-use.ll
…
global-merge-hidden-minsize.ll
…
global-merge-ignore-single-use-minsize.ll
…
global-merge-ignore-single-use.ll
…
global-merge-minsize.ll
…
global-merge.ll
…
got-abuse.ll
…
hadd-combine.ll
[DAGCombine] Move AVG combine to SimplifyDemandBits
2022-02-15 10:17:02 +00:00
half.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
hints.ll
…
hoist-and-by-const-from-lshr-in-eqcmp-zero.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
hoist-and-by-const-from-shl-in-eqcmp-zero.ll
[AArch64InstPrinter] Change printAddSubImm to comment imm value when shifted
2021-08-03 02:28:46 -07:00
hwasan-check-memaccess.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
hwasan-prefer-fp.ll
…
i1-contents.ll
[AArch64] Emit AssertZExt for i1 arguments
2021-10-11 11:55:11 +03:00
i128-align.ll
…
i128-fast-isel-fallback.ll
…
i128_volatile_load_store.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
iabs.ll
…
icmp-shift-opt.ll
[AArch64] Precommit i256 test from D111530
2021-11-08 10:47:57 +00:00
ifcvt-select.ll
…
illegal-float-ops.ll
Update @llvm.powi to handle different int sizes for the exponent
2021-06-17 09:38:28 +02:00
ilp32-tlsdesc.ll
…
ilp32-va.ll
[AArch64] Enable UseAA globally in the AArch64 backend
2021-04-24 17:51:50 +01:00
immcost.ll
…
implicit-null-check.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
implicit-sret.ll
…
inc-of-add.ll
[AArch64InstPrinter] Change printAddSubImm to comment imm value when shifted
2021-08-03 02:28:46 -07:00
init-array.ll
…
inline-asm-blockaddress.ll
…
inline-asm-clobber.ll
…
inline-asm-constraints-bad-sve.ll
…
inline-asm-constraints-badI.ll
…
inline-asm-constraints-badK.ll
…
inline-asm-constraints-badK2.ll
…
inline-asm-constraints-badL.ll
…
inline-asm-globaladdress.ll
…
inline-asm-i-constraint-i1.ll
…
inline-asm-multilevel-gep.ll
…
inlineasm-S-constraint.ll
[SimplifyCFG] FoldTwoEntryPHINode(): don't fold if either block has it's address taken
2021-06-20 12:37:14 +03:00
inlineasm-X-allocation.ll
…
inlineasm-X-constraint.ll
[SelectionDAG] treat X constrained labels as i for asm
2022-01-11 10:29:40 -08:00
inlineasm-illegal-type.ll
…
inlineasm-ldr-pseudo.ll
…
inlineasm-output-template.ll
…
insert-subvector-res-legalization.ll
[SchedModels][CortexA55] Add ASIMD integer instructions
2022-02-17 13:41:57 +03:00
intrinsics-memory-barrier.ll
…
irg-nomem.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
irg.ll
…
irg_sp_tagp.ll
…
isinf.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
jti-correct-datatype.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
jump-table-32.ll
…
jump-table-compress.mir
…
jump-table-duplicate.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
jump-table-exynos.ll
…
jump-table.ll
…
known-never-nan.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
lack-of-signed-truncation-check.ll
[AArch64] Enable type promotion for AArch64
2021-09-29 15:13:12 +01:00
landingpad-ifcvt.ll
…
large-consts.ll
…
large-stack-cmp.ll
[Test] Regenerate some of llc test checks using auto updater
2021-10-28 16:18:30 +07:00
large-stack.ll
…
large_shift.ll
…
ldp-stp-scaled-unscaled-pairs.ll
…
ldradr.ll
…
ldrpre-ldr-merge.mir
AArch64: don't form indexed paired ops if base reg overlaps operands.
2021-08-20 11:39:38 +01:00
ldst-miflags.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
ldst-nopreidx-sp-redzone.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
ldst-opt-aa.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
ldst-opt-after-block-placement.ll
[SimplifyCFG] Tail-merging all blocks with `ret` terminator
2021-06-24 13:15:39 +03:00
ldst-opt-mte-with-dbg.mir
…
ldst-opt-mte.mir
…
ldst-opt-non-imm-offset.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
ldst-opt-zr-clobber.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
ldst-opt.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
ldst-opt.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
ldst-paired-aliasing.ll
[AArch64InstPrinter] Change printAddSubImm to comment imm value when shifted
2021-08-03 02:28:46 -07:00
ldst-regoffset.ll
…
ldst-unscaledimm.ll
…
ldst-unsignedimm.ll
[AArch64] Rewrite ldst-unsignedimm.ll codegen test.
2021-09-24 09:08:59 +01:00
ldst-zero.ll
…
legalize-bug-bogus-cpu.ll
…
lit.local.cfg
…
literal_pools_float.ll
[AArch64] Materialize FP constant in code for large code model
2021-04-07 21:02:05 +02:00
live-debugvalues-sve.mir
[X86] Return src/dest register from stack spill/restore recogniser
2021-07-09 18:12:30 +01:00
live-interval-analysis.mir
…
llrint-conv-fp16.ll
…
llrint-conv.ll
…
llround-conv-fp16.ll
…
llround-conv.ll
…
llvm-ir-to-intrinsic.ll
[SVE] Extend isel pattern coverage for BIC.
2022-01-28 13:14:46 +00:00
llvm-masked-gather-legal-for-sve.ll
[SVE] Remove checks for warnings in scalable-vector tests.
2021-04-07 15:59:32 +01:00
llvm-masked-scatter-legal-for-sve.ll
[SVE] Remove checks for warnings in scalable-vector tests.
2021-04-07 15:59:32 +01:00
load-combine-big-endian.ll
[AArch64] Regenerate some test checks. NFC
2021-09-08 11:08:32 +01:00
load-combine.ll
…
load-store-forwarding.ll
…
local_vars.ll
…
logical-imm.ll
…
logical_shifted_reg.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
loh-adrp-add-ldr-clobber.mir
…
loh-use-between-adrp-add.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
loh.mir
…
loop-micro-op-buffer-size-t99.ll
[LoopUnroll] Simplify optimization remarks
2021-06-18 23:47:03 +02:00
loop-sink-limit.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
loop-sink.mir
[Aarch64] Correct register class for pseudo instructions
2021-09-09 14:31:49 -04:00
lower-ptrmask.ll
…
lower-range-metadata-func-call.ll
…
lowerMUL-newload.ll
[SchedModels][CortexA55] Add ASIMD integer instructions
2022-02-17 13:41:57 +03:00
lrint-conv-fp16-win.ll
…
lrint-conv-fp16.ll
…
lrint-conv-win.ll
…
lrint-conv.ll
…
lround-conv-fp16-win.ll
…
lround-conv-fp16.ll
…
lround-conv-win.ll
…
lround-conv.ll
…
ls64-inline-asm.ll
[AArch64InstPrinter] Change printAddSubImm to comment imm value when shifted
2021-08-03 02:28:46 -07:00
ls64-intrinsics.ll
…
machine-combiner-fmul-dup.mir
[AArch64] Add Machine InstCombiner patterns for FMUL indexed variant
2021-11-09 15:30:19 +03:00
machine-combiner-instr-fmf.mir
[AArch64] Make machine combiner patterns preserve MIFlags
2022-02-03 11:58:59 +00:00
machine-combiner-madd.ll
…
machine-combiner-reassociate.mir
[AArch64] Adjust machine-combiner-reassociate.mir test
2022-02-03 12:40:14 +00:00
machine-combiner.ll
[AArch64] Prefer fmov over orr v.16b when copying f32/f64
2021-08-03 17:25:40 +01:00
machine-combiner.mir
…
machine-copy-prop.ll
…
machine-copy-remove.ll
…
machine-copy-remove.mir
…
machine-cp-clobbers.mir
…
machine-dead-copy.mir
…
machine-licm-sink-instr.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
machine-outliner-2fixup-blr-terminator.mir
…
machine-outliner-all-stack.mir
…
machine-outliner-bad-adrp.mir
…
machine-outliner-bad-register.mir
…
machine-outliner-bti.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
machine-outliner-calls.mir
…
machine-outliner-cfi-tail-some.mir
…
machine-outliner-cfi-tail.mir
…
machine-outliner-cfi.mir
…
machine-outliner-compatible-candidates.mir
…
machine-outliner-create-lr-livein.mir
[MachineOutliner][AArch64] Ensure LR is live-in when inserting reg-save calls
2021-09-08 17:44:27 -07:00
machine-outliner-default.mir
…
machine-outliner-drop-stack.mir
…
machine-outliner-flags.ll
…
machine-outliner-function-annotate.mir
…
machine-outliner-inline-asm-adrp.mir
…
machine-outliner-iterative-2.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
machine-outliner-iterative.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
machine-outliner-no-noreturn-no-stack.mir
…
machine-outliner-noredzone.ll
…
machine-outliner-noreturn-no-stack.mir
…
machine-outliner-noreturn-save-lr.mir
…
machine-outliner-ordering.mir
…
machine-outliner-outline-bti.ll
…
machine-outliner-patchable.ll
[MachineOutliner] Don't outline functions starting with PATCHABLE_FUNCTION_ENTER/FENTRL_CALL
2021-12-13 13:24:29 -08:00
machine-outliner-regsave.mir
…
machine-outliner-remarks.ll
…
machine-outliner-retaddr-sign-cfi.ll
Revert "[AArch64] Emit .cfi_negate_ra_state for PAC-auth instructions."
2022-01-06 19:17:45 +01:00
machine-outliner-retaddr-sign-diff-scope-same-key.ll
…
machine-outliner-retaddr-sign-non-leaf.ll
…
machine-outliner-retaddr-sign-regsave.mir
Revert "[AArch64] Emit .cfi_negate_ra_state for PAC-auth instructions."
2022-01-06 19:17:45 +01:00
machine-outliner-retaddr-sign-same-scope-diff-key.ll
…
machine-outliner-retaddr-sign-same-scope-same-key-a.ll
…
machine-outliner-retaddr-sign-same-scope-same-key-b.ll
…
machine-outliner-retaddr-sign-sp-mod.ll
[AArch64][v8.3A] Avoid inserting implicit landing pads (PACI*SP)
2021-06-24 18:24:32 +01:00
machine-outliner-retaddr-sign-sp-mod.mir
Revert "[AArch64] Emit .cfi_negate_ra_state for PAC-auth instructions."
2022-01-06 19:17:45 +01:00
machine-outliner-retaddr-sign-subtarget.ll
[AArch64][v8.3A] Avoid inserting implicit landing pads (PACI*SP)
2021-06-24 18:24:32 +01:00
machine-outliner-retaddr-sign-thunk.ll
Revert "[AArch64] Emit .cfi_negate_ra_state for PAC-auth instructions."
2022-01-06 19:17:45 +01:00
machine-outliner-retaddr-sign-v8-3.ll
[AArch64][v8.3A] Avoid inserting implicit landing pads (PACI*SP)
2021-06-24 18:24:32 +01:00
machine-outliner-side-effect-2.mir
Fix the side effect of outlined function when the register is implicit use and implicit-def in the same instruction.
2021-11-17 09:44:10 -08:00
machine-outliner-side-effect.mir
Fix the side effect of outlined function when the register is implicit use and implicit-def in the same instruction.
2021-11-17 09:44:10 -08:00
machine-outliner-size-info.mir
…
machine-outliner-tail.ll
…
machine-outliner-throw.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
machine-outliner-throw2.ll
…
machine-outliner-thunk.ll
[AArch64] Regenerate some test checks. NFC
2021-09-08 11:08:32 +01:00
machine-outliner-unsafe-stack-call.mir
…
machine-outliner.ll
…
machine-outliner.mir
…
machine-scheduler.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
machine-sink-getmemoperandwithoffset.mir
…
machine-sink-kill-flags.ll
[Test] Regenerate some of llc test checks using auto updater
2021-10-28 16:18:30 +07:00
machine-sink-zr.mir
…
machine-zero-copy-remove.mir
…
machine_cse.ll
…
machine_cse_illegal_hoist.ll
…
machine_cse_impdef_killflags.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
macho-global-symbols.ll
…
macho-trap.ll
…
macro-fusion-last.mir
…
macro-fusion.ll
…
madd-combiner.ll
[AArch64] Canonicalize X*(Y+1) or X*(1-Y) to madd/msub
2021-11-08 16:49:31 +08:00
madd-lohi.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
mature-mc-support.ll
…
max-jump-table.ll
…
memcpy-f128.ll
…
memcpy-scoped-aa.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
memset.ll
Use v16i8 rather than v2i64 as the VT for memset expansion on AArch64.
2021-08-19 16:54:07 +00:00
memsize-remarks.ll
[Remarks] Make memsize remarks report as an analysis, not a missed opportunity.
2021-06-22 18:22:47 -07:00
merge-scoped-aa-store.ll
[SelectionDAG] Re-calculate scoped AA metadata when merging stores.
2021-09-21 11:41:17 -04:00
merge-store-dependency.ll
…
merge-store.ll
…
merge-trunc-store.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
mergestores_noimplicitfloat.ll
…
midpoint-int.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
min-jump-table.ll
…
min-max.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
mingw-refptr.ll
…
minmax-of-minmax.ll
[SchedModels][CortexA55] Add ASIMD integer instructions
2022-02-17 13:41:57 +03:00
minmax.ll
[SchedModels][CortexA55] Add ASIMD integer instructions
2022-02-17 13:41:57 +03:00
misched-fusion-addr-tune.ll
[AArch64] Split out processor/tuning features
2021-10-19 15:18:55 +01:00
misched-fusion-addr.ll
…
misched-fusion-aes.ll
[Driver][AArch64]Add driver support for neoverse-512tvb target
2021-10-28 09:08:40 +01:00
misched-fusion-arith-logic.mir
…
misched-fusion-crypto-eor.mir
…
misched-fusion-csel.ll
…
misched-fusion-lit.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
misched-fusion.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
misched-predicate-virtreg.mir
[AArch64][SchedModels] Handle virtual registers in FP/NEON predicates
2022-02-17 13:41:05 +03:00
misched-stp.ll
[AArch64] Enable UseAA globally in the AArch64 backend
2021-04-24 17:51:50 +01:00
mla_mls_merge.ll
[AArch64] Prefer fmov over orr v.16b when copying f32/f64
2021-08-03 17:25:40 +01:00
mlicm-stack-write-check.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
movimm-wzr.mir
…
movw-consts.ll
[AArch64] Regenerate some more tests
2021-10-06 10:38:22 +01:00
movw-shift-encoding.ll
…
mul-lohi.ll
…
mul_by_elt.ll
…
mul_pow2.ll
…
multi-vector-store-size.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
named-vector-shuffle-reverse-neon.ll
[AArch64InstPrinter] Change printAddSubImm to comment imm value when shifted
2021-08-03 02:28:46 -07:00
named-vector-shuffle-reverse-sve.ll
[CodeGen][SVE] Add missing isel patterns for vector_reverse
2021-11-18 09:59:26 +00:00
named-vector-shuffles-neon.ll
[IR] Change vector.splice intrinsic to reject out-of-bounds indices
2022-01-11 09:37:39 +00:00
named-vector-shuffles-sve.ll
[AArch64] NFC: Clarify and auto-generate some CodeGen tests.
2022-01-24 17:42:37 +00:00
neg-abs.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
neg-imm.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
neon-abd.ll
[AArch64] Add NEON test cases for ISD::ABDS/U.
2022-01-26 13:05:57 +00:00
neon-addlv.ll
[AArch64] Expand UADDLV patterns to SADDLV
2022-02-04 14:07:02 +00:00
neon-bitcast.ll
…
neon-bitselect.ll
[AArch64][NEON] Match (or (and -a b) (and (a+1) b)) => bit select
2021-04-15 13:52:47 +01:00
neon-bitwise-instructions.ll
[DAG] SelectionDAG::getNode(N1,N2) - detect N2 constant vector splats as well as scalars
2022-01-27 10:59:08 +00:00
neon-compare-instructions.ll
[AArch64][GlobalISel] Add post-legalizer lowering for NEON vector fcmps
2021-05-10 15:40:06 -07:00
neon-diagnostics.ll
…
neon-dot-product.ll
…
neon-dotpattern.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
neon-dotreduce.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
neon-extract.ll
…
neon-fma-FMF.ll
…
neon-fma.ll
…
neon-fp16fml.ll
…
neon-fpextend_f16.ll
…
neon-fpround_f128.ll
…
neon-idiv.ll
…
neon-inline-asm-16-bit-fp.ll
…
neon-mla-mls.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
neon-mov.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
neon-or-combine.ll
…
neon-perm.ll
…
neon-reverseshuffle.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
neon-sad.ll
[AArch64] Add TableGen patterns to generate uaddlv
2021-06-18 17:23:26 +01:00
neon-scalar-by-elem-fma.ll
…
neon-scalar-copy.ll
…
neon-sha3.ll
…
neon-shift-left-long.ll
…
neon-shift-neg.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
neon-sm4-sm3.ll
…
neon-stepvector.ll
[AArch64] NFC: Clarify and auto-generate some CodeGen tests.
2022-01-24 17:42:37 +00:00
neon-truncstore.ll
[AArch64] Add a tablegen pattern for UZP1.
2021-12-14 11:51:05 +00:00
neon-vcadd.ll
…
neon-vcmla.ll
…
neon-vmull-high-p8.ll
[AARCH64][NEON] Allow to sink operands for aarch64_neon_pmull
2022-02-03 16:46:49 +00:00
neon-vmull-high-p64.ll
…
neon-wide-splat.ll
…
neon-widen-shuffle.ll
[AArch64] Improve shuffle vector by using wider types
2021-10-18 21:24:45 +08:00
neon_rbit.ll
[AArch64] Optimise bitreverse lowering in ISel
2021-06-02 12:51:12 +01:00
nest-register.ll
…
no-fp-asm-clobbers-crash.ll
…
no-quad-ldp-stp.ll
…
no-stack-arg-probe.ll
…
no_cfi.ll
…
nomerge.ll
…
nonlazybind.ll
…
nontemporal.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
note-gnu-property-pac-bti-0.ll
…
note-gnu-property-pac-bti-1.ll
…
note-gnu-property-pac-bti-2.ll
…
note-gnu-property-pac-bti-3.ll
…
note-gnu-property-pac-bti-4.ll
…
nzcv-save.ll
…
optimize-cond-branch.ll
[SimplifyCFG] Tail-merging all blocks with `ret` terminator
2021-06-24 13:15:39 +03:00
optimize-imm.ll
…
or-combine.ll
…
overeager_mla_fusing.ll
[SchedModels][CortexA55] Add ASIMD integer instructions
2022-02-17 13:41:57 +03:00
overlapping-copy-bundle-cycle.mir
…
overlapping-copy-bundle.mir
…
pacbti-llvm-generated-funcs-1.ll
…
pacbti-llvm-generated-funcs-2.ll
[AArch64][v8.3A] Avoid inserting implicit landing pads (PACI*SP)
2021-06-24 18:24:32 +01:00
pacbti-module-attrs.ll
[AArch64][v8.3A] Avoid inserting implicit landing pads (PACI*SP)
2021-06-24 18:24:32 +01:00
paired-load.ll
…
parity.ll
…
partial-pipeline-execution.ll
Revert "[NFC] remove explicit default value for strboolattr attribute in tests"
2021-05-24 19:43:40 +02:00
patchable-function-entry-bti.ll
[AArch64][v8.5A] Add BTI to all function starts
2021-04-14 15:24:01 +01:00
patchable-function-entry-empty.mir
…
patchable-function-entry.ll
…
peephole-and-tst.ll
…
peephole-opt-check-cflags.mir
…
phi-dbg.ll
…
pic-eh-stubs.ll
…
pie.ll
…
popcount.ll
[AArch64][GlobalISel] Legalize ctpop s128
2021-08-05 11:54:53 -07:00
post-ra-machine-sink.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
postra-mi-sched.ll
…
pow.75.ll
[AArch64] Regenerate some test checks. NFC
2021-09-08 11:08:32 +01:00
pow.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
powi-windows.ll
Update @llvm.powi to handle different int sizes for the exponent
2021-06-17 09:38:28 +02:00
pr27816.ll
…
pr33172.ll
[NFC][Codegen] Tune a few tests to not end with a naked `unreachable` terminator
2021-07-02 23:33:30 +03:00
pr40091.ll
…
pr48188.ll
[AArch64][GlobalISel] Widen G_PHI before clamping it during legalization
2021-08-04 10:25:14 -07:00
pr49781.ll
[SelectionDAG] Teach SelectionDAG::FoldConstantArithmetic to handle SPLAT_VECTOR
2021-04-07 10:03:33 -07:00
pr51476.ll
[AArch64] Fix comparison peephole opt with non-0/1 immediate (PR51476)
2021-08-15 12:35:52 +02:00
pr51516.mir
Fix late rematerialization operands check
2021-08-23 12:23:58 -07:00
pr53315-returned-i128.ll
[AArch64][GlobalISel] Support returned argument with multiple registers
2022-01-24 10:55:28 +01:00
preferred-alignment.ll
…
preferred-function-alignment.ll
[AArch64] Sets the preferred function alignment for Cortex-A53/A55.
2021-05-03 00:00:10 +01:00
prefixdata.ll
…
preserve_mostcc.ll
…
print-mrs-system-register.ll
…
prologue-epilogue-remarks.mir
…
ptrauth-intrinsic-sign-generic.ll
[AArch64][PAC] Select llvm.ptrauth.sign/sign.generic to PAC*.
2021-11-18 15:21:30 -08:00
ptrauth-intrinsic-sign.ll
[AArch64][PAC] Select llvm.ptrauth.sign/sign.generic to PAC*.
2021-11-18 15:21:30 -08:00
pull-binop-through-shift.ll
…
pull-conditional-binop-through-shift.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
qmovn.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
ragreedy-csr.ll
…
ragreedy-local-interval-cost.ll
[SchedModels][CortexA55] Add ASIMD integer instructions
2022-02-17 13:41:57 +03:00
rand.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
rbit.ll
…
read-pc.ll
…
readcyclecounter.ll
[AArch64] FeaturePerfMon Added to CPUs
2022-02-08 11:19:26 +00:00
recp-fastmath.ll
Revert "[NFC] remove explicit default value for strboolattr attribute in tests"
2021-05-24 19:43:40 +02:00
reduce-and.ll
Revert "[CodeGen][AArch64] Ensure isSExtCheaperThanZExt returns true for negative constants"
2022-01-18 08:40:20 +00:00
reduce-or.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
reduce-xor.ll
[AArch64][GlobalISel] Legalize G_VECREDUCE_XOR. Treated same as other bitwise reductions.
2021-10-10 17:01:21 -07:00
redundant-copy-elim-empty-mbb.ll
Revert "[CodeGen][AArch64] Ensure isSExtCheaperThanZExt returns true for negative constants"
2022-01-13 15:59:43 +00:00
redundant-mov-from-zero-extend.ll
[AArch64] Remove redundant ORRWrs which is generated by zero-extend
2021-10-25 09:47:07 +01:00
redundant-orrwrs-from-zero-extend.mir
[AArch64] Remove redundant ORRWrs which is generated by zero-extend
2021-10-25 09:47:07 +01:00
reg-scavenge-frame.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
regcoal-physreg.mir
…
regress-bitcast-formals.ll
…
regress-combine-extract-vectors.ll
…
regress-f128csel-flags.ll
…
regress-fp128-livein.ll
…
regress-tail-livereg.ll
…
regress-tblgen-chains.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
regress-w29-reserved-with-fp.ll
…
relaxed-fp-atomics.ll
[AArch64] Add patterns for relaxed atomic ld/st into fp registers
2022-01-25 15:33:37 +03:00
reloc-specifiers.mir
…
rem_crash.ll
…
remat-float0.ll
[AArch64] Default to zero-cycle-zeroing FP registers
2021-04-06 09:47:50 +01:00
remat.ll
…
returnaddr.ll
…
reverse-csr-restore-seq.mir
…
rm_redundant_cmp.ll
…
rmif-def-nzcv.mir
…
rmif-use-nzcv.mir
…
rotate-extract.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
rotate.ll
…
round-conv.ll
…
round-fptosi-sat-scalar.ll
[AArch64] Lower fpto*i.sat intrinsics.
2021-05-17 10:19:19 +01:00
round-fptoui-sat-scalar.ll
[AArch64] Lower fpto*i.sat intrinsics.
2021-05-17 10:19:19 +01:00
rvmarker-pseudo-expansion-and-outlining.mir
[ObjCARC] Require the function argument in the clang.arc.attachedcall bundle.
2022-01-28 12:41:45 -08:00
sadd_sat.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
sadd_sat_plus.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
sadd_sat_vec.ll
[SchedModels][CortexA55] Add ASIMD integer instructions
2022-02-17 13:41:57 +03:00
sat-add.ll
[SchedModels][CortexA55] Add ASIMD integer instructions
2022-02-17 13:41:57 +03:00
scalable-vector-promotion.ll
…
sched-past-vector-ldst.ll
Revert "[NFC] remove explicit default value for strboolattr attribute in tests"
2021-05-24 19:43:40 +02:00
scheduledag-constreg.mir
…
sdag-no-typesize-warnings-regandsizes.ll
[SVE] Remove checks for warnings in scalable-vector tests.
2021-04-07 15:59:32 +01:00
sdag-store-merging-bug.ll
…
sdivpow2.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
seh-finally.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
seh_funclet_x1.ll
…
select-constant-xor.ll
[DAG] Fix GT -> GE condition when creating SetCC
2021-09-08 12:41:51 +01:00
select-with-and-or.ll
[AArch64] Genereate CCMP from And CSel
2022-02-02 13:48:16 +00:00
select_cc.ll
[AArch64] Bail out for float operands in SetCC optimization.
2022-01-31 18:20:47 +00:00
select_const.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
select_fmf.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
selectcc-to-shiftand.ll
[SchedModels][CortexA55] Add ASIMD integer instructions
2022-02-17 13:41:57 +03:00
selectiondag-order.ll
…
semantic-interposition-asm.ll
[test] Improve CodeGen/*/semantic-interposition-asm.ll
2021-05-16 11:17:09 -07:00
seqpaircopy.mir
…
seqpairspill.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
setcc-takes-i32.ll
…
setcc-type-mismatch.ll
…
setf8-def-nzcv.mir
…
setf8-use-nzcv.mir
…
setf16-def-nzcv.mir
…
setf16-use-nzcv.mir
…
settag-merge-order.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
settag-merge.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
settag-merge.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
settag.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
shadow-call-stack.ll
[AArch64] Emit CFI instruction for updating x18 when using ShadowCallStack with exception unwinding
2021-10-08 14:20:26 -07:00
shift-accumulate.ll
Optimize shift and accumulate pattern in AArch64.
2022-01-20 01:57:40 +00:00
shift-amount-mod.ll
[AArch64] Add a special case for shifting by (BitWidth - 1) - X
2022-02-11 08:23:33 +00:00
shift-by-signext.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
shift-logic.ll
…
shift-mod.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
shift_minsize.ll
[AArch64] NFC: Clarify and auto-generate some CodeGen tests.
2022-01-24 17:42:37 +00:00
shrink-constant-multiple-users.ll
…
shrink-wrap.ll
…
shrink-wrapping-vla.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
shuffle-mask-legal.ll
…
sibling-call.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
sign-return-address-cfi-negate-ra-state.ll
[AArch64][v8.3A] Avoid inserting implicit landing pads (PACI*SP)
2021-06-24 18:24:32 +01:00
sign-return-address.ll
Revert "[AArch64] Emit .cfi_negate_ra_state for PAC-auth instructions."
2022-01-06 19:17:45 +01:00
signbit-shift.ll
[SchedModels][CortexA55] Add ASIMD integer instructions
2022-02-17 13:41:57 +03:00
signed-truncation-check.ll
[AArch64] Enable type promotion for AArch64
2021-09-29 15:13:12 +01:00
simple-macho.ll
…
sincos-expansion.ll
…
sincospow-vector-expansion.ll
…
sink-addsub-of-const.ll
[SchedModels][CortexA55] Add ASIMD integer instructions
2022-02-17 13:41:57 +03:00
sink-copy-for-shrink-wrap.ll
…
sinksplat.ll
[SchedModels][CortexA55] Add ASIMD integer instructions
2022-02-17 13:41:57 +03:00
sitofp-fixed-legal.ll
[SchedModels][CortexA55] Add ASIMD integer instructions
2022-02-17 13:41:57 +03:00
space.ll
…
special-reg.ll
…
speculation-hardening-dagisel.ll
…
speculation-hardening-loads.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
speculation-hardening-sls-blr.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
speculation-hardening-sls.ll
[llvm][test] rewrite callbr to use i rather than X constraint NFC
2022-01-11 11:31:08 -08:00
speculation-hardening-sls.mir
…
speculation-hardening.ll
[test, AArch64] Fix use of var defined in CHECK-NOT
2021-04-06 21:15:15 +01:00
speculation-hardening.mir
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
spill-fold.ll
…
spill-fold.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
spill-stack-realignment.mir
…
spill-undef.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
spillfill-sve.ll
Fix the default alignment of i1 vectors.
2021-07-31 14:09:59 -07:00
spillfill-sve.mir
…
split-vector-insert.ll
[AArch64][SVE] Lower vector.insert to predicated merged MOV
2021-12-13 11:17:55 +00:00
sponentry.ll
…
sqrt-fastmath.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
srem-lkk.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
srem-seteq-illegal-types.ll
[SchedModels][CortexA55] Add ASIMD integer instructions
2022-02-17 13:41:57 +03:00
srem-seteq-optsize.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
srem-seteq-vec-nonsplat.ll
[SchedModels][CortexA55] Add ASIMD integer instructions
2022-02-17 13:41:57 +03:00
srem-seteq-vec-splat.ll
[SchedModels][CortexA55] Add ASIMD integer instructions
2022-02-17 13:41:57 +03:00
srem-seteq.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
srem-vector-lkk.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
sshl_sat.ll
[DAGCombiner] Fold SSHLSAT/USHLSAT to SHL when no saturation will occur
2022-02-06 18:59:06 +01:00
ssub_sat.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
ssub_sat_plus.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
ssub_sat_vec.ll
[SchedModels][CortexA55] Add ASIMD integer instructions
2022-02-17 13:41:57 +03:00
stack-guard-reassign-sve.mir
[AArch64][SVE] Fix handling of stack protection with SVE
2021-12-14 11:30:48 +00:00
stack-guard-reassign.ll
…
stack-guard-reassign.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
stack-guard-remat-bitcast.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
stack-guard-sve.ll
[AArch64][SVE] Fix handling of stack protection with SVE
2021-12-14 11:30:48 +00:00
stack-guard-sysreg.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
stack-guard-vaarg.ll
…
stack-id-pei-alloc.mir
…
stack-id-stackslot-scavenging.mir
…
stack-protector-musttail.ll
StackProtector: ensure protection does not interfere with tail call frame.
2021-04-13 15:14:57 +01:00
stack-protector-target.ll
…
stack-tagging-dbg.ll
[DebugInfo] Correctly update dbg.values with duplicated location ops
2021-07-14 11:17:24 +01:00
stack-tagging-ex-1.ll
Revert "[NFC] remove explicit default value for strboolattr attribute in tests"
2021-05-24 19:43:40 +02:00
stack-tagging-ex-2.ll
Revert "[NFC] remove explicit default value for strboolattr attribute in tests"
2021-05-24 19:43:40 +02:00
stack-tagging-initializer-merge.ll
…
stack-tagging-musttail.ll
[mte] fix compiler crash with musttail.
2022-02-02 16:13:46 -08:00
stack-tagging-setjmp.ll
[mte] work around lifetime issue with setjmp.
2022-02-02 13:55:09 -08:00
stack-tagging-split-lifetime.ll
[mte] support more complicated lifetimes (e.g. for exceptions).
2022-02-02 14:39:22 -08:00
stack-tagging-unchecked-ld-st.ll
…
stack-tagging-untag-placement.ll
Revert "[NFC] remove explicit default value for strboolattr attribute in tests"
2021-05-24 19:43:40 +02:00
stack-tagging.ll
…
stack_guard_remat.ll
Revert "[NFC] remove explicit default value for strboolattr attribute in tests"
2021-05-24 19:43:40 +02:00
stackguard-internal.ll
…
stackmap-frame-setup.ll
…
stackmap-liveness.ll
…
stackmap.ll
…
statepoint-call-lowering-sp.ll
[Statepoint] Update gc.statepoint calls in tests with elementtype (NFC)
2022-02-04 14:15:41 +01:00
statepoint-call-lowering.ll
[Statepoint] Update gc.statepoint calls in tests with elementtype (NFC)
2022-02-04 14:15:41 +01:00
stgp.ll
…
store_merge_pair_offset.ll
…
storepairsuppress_minsize.ll
[AArch64] Disable AArch64StorePairSuppress under optsize
2021-10-04 18:28:15 +01:00
stp-opt-with-renaming-debug.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
stp-opt-with-renaming-ld3.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
stp-opt-with-renaming-reserved-regs.mir
[AArch64][SME] Add load and store instructions
2021-07-16 10:11:10 +00:00
stp-opt-with-renaming-undef-assert.mir
[NFC] Simplify pairwise store test mir to drop stack accesses.
2022-02-10 12:40:32 -08:00
stp-opt-with-renaming.mir
[AArch64][SME] Add load and store instructions
2021-07-16 10:11:10 +00:00
strict-fp-int-promote.ll
…
strpre-str-merge.mir
AArch64: don't form indexed paired ops if base reg overlaps operands.
2021-08-20 11:39:38 +01:00
strqro.ll
…
strqu.ll
[AArch64] Regenerate some test checks. NFC
2021-09-08 11:08:32 +01:00
sub-of-bias.ll
…
sub-of-not.ll
[AArch64InstPrinter] Change printAddSubImm to comment imm value when shifted
2021-08-03 02:28:46 -07:00
sub-splat-sub.ll
[DAG] Fold neg(splat(neg(x)) -> splat(x)
2021-06-25 19:53:29 +01:00
sub1.ll
[AArch64InstPrinter] Change printAddSubImm to comment imm value when shifted
2021-08-03 02:28:46 -07:00
subs-to-sub-opt.ll
…
sve-abd.ll
[SVE] Enable ISD::ABDS/U ISel for scalable vectors.
2022-01-25 12:14:53 +00:00
sve-adr.ll
[AArch64][SVE] Add patterns to generate ADR instruction
2021-09-21 15:50:49 -07:00
sve-alloca-stackid.ll
[SVE] Remove checks for warnings in scalable-vector tests.
2021-04-07 15:59:32 +01:00
sve-alloca.ll
[SVE] Fix TypeSize->uint64_t implicit conversion in visitAlloca()
2022-01-31 14:37:23 +00:00
sve-bad-intrinsics.ll
…
sve-bad-select.ll
…
sve-bit-counting-pred.ll
[SVE] Remove checks for warnings in scalable-vector tests.
2021-04-07 15:59:32 +01:00
sve-bit-counting.ll
[SVE] Remove checks for warnings in scalable-vector tests.
2021-04-07 15:59:32 +01:00
sve-bitcast.ll
[AArch64][SVE] Optimize bitcasts between unpacked half/i16 vectors.
2021-07-19 08:29:28 +01:00
sve-breakdown-scalable-vectortype.ll
[AArch64][SelectionDAG] Support passing/returning scalable vectors with unusual types.
2021-08-02 15:53:16 -07:00
sve-callbyref-notailcall.ll
[SVE] Remove checks for warnings in scalable-vector tests.
2021-04-07 15:59:32 +01:00
sve-calling-convention-byref.ll
Fix the default alignment of i1 vectors.
2021-07-31 14:09:59 -07:00
sve-calling-convention-mixed.ll
[AArch64][SVE] Use TargetFrameIndex in more SVE load/store addressing modes
2021-10-29 14:44:16 +00:00
sve-calling-convention-tuple-types.ll
[SVE] Remove checks for warnings in scalable-vector tests.
2021-04-07 15:59:32 +01:00
sve-calling-convention.ll
[SVE] Remove checks for warnings in scalable-vector tests.
2021-04-07 15:59:32 +01:00
sve-cmp-folds.ll
[CodeGen] Support folds of not(cmp(cc, ...)) -> cmp(!cc, ...) for scalable vectors
2022-02-01 09:50:00 +00:00
sve-cmp-select.ll
[AArch64] NFC: Clarify and auto-generate some CodeGen tests.
2022-01-24 17:42:37 +00:00
sve-cntp-combine.ll
[SVE] Extend isel pattern coverage for INCP & DECP.
2022-01-31 19:05:05 +00:00
sve-coalesce-ptrue-intrinsics.ll
[AArch64][SVE] Move convert.{from,to}.svbool optimization into InstCombine
2021-04-29 12:17:42 +01:00
sve-copy-zprpair.mir
…
sve-expand-div.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
sve-extract-element.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
sve-extract-fixed-from-scalable-vector.ll
[SVE] Fix incorrect DAG combines when extracting fixed-width from scalable vectors
2021-10-06 09:27:44 +01:00
sve-extract-fixed-vector.ll
[SVE][CodeGen] Bail out for scalable vectors in AArch64TargetLowering::ReconstructShuffle
2022-02-10 14:18:49 +00:00
sve-extract-scalable-vector.ll
[DAGCombiner] Fold `ty1 extract_vector(ty2 splat(V)) -> ty1 splat(V)`
2022-02-09 14:30:01 +00:00
sve-extract-subvector.ll
[SVE] Remove checks for warnings in scalable-vector tests.
2021-04-07 15:59:32 +01:00
sve-extract-vector-to-predicate-store.ll
[AArch64][SVE] Combine bitcasts of predicate types with vector inserts/extracts of loads/stores
2021-08-04 15:51:14 +00:00
sve-fcmp.ll
[AArch64][SVE] Add ISel patterns for floating point compare with zero instructions
2021-07-08 10:46:12 +00:00
sve-fcopysign.ll
[AArch64][NEON][SVE] Lower FCOPYSIGN using AArch64ISD::BSP
2022-02-07 14:35:26 +00:00
sve-fcvt.ll
[AArch64][SVE] Remove false register dependency for unary FP convert operations
2022-02-04 09:55:39 +00:00
sve-fix-length-and-combine-512.ll
…
sve-fixed-length-bit-counting.ll
[SVE] Use reg+reg addressing mode for immediate offsets.
2021-07-26 16:24:16 +01:00
sve-fixed-length-bitcast.ll
[AArch64][SVE] Improve SVE codegen for fixed length BITCAST
2021-05-10 14:43:53 +01:00
sve-fixed-length-bitselect.ll
[AArch64] Block tryCombineToBSL combines for vectors wider than NEON
2021-04-22 15:09:13 +00:00
sve-fixed-length-concat.ll
[AArch64] Improve shuffle vector by using wider types
2021-10-18 21:24:45 +08:00
sve-fixed-length-ext-loads.ll
[AArch64][SVE] Add fixed type lowering for EXTRACT_SUBVECTOR
2021-10-12 14:56:15 +00:00
sve-fixed-length-extract-subvector.ll
[AArch64][SVE] Add fixed type lowering for EXTRACT_SUBVECTOR
2021-10-12 14:56:15 +00:00
sve-fixed-length-extract-vector-elt.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
sve-fixed-length-float-compares.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
sve-fixed-length-fp-arith.ll
[SVE] Use reg+reg addressing mode for immediate offsets.
2021-07-26 16:24:16 +01:00
sve-fixed-length-fp-convert.ll
[AArch64][SVE] Fix selection failure caused by fp/int convert using non-Neon types
2022-02-11 11:46:59 +00:00
sve-fixed-length-fp-extend-trunc.ll
[SVE] Prefer zero-extending loads when lowering ISD::EXTLOAD.
2022-02-10 14:30:28 +00:00
sve-fixed-length-fp-fma.ll
[SVE] Fix VLS FMA matching for CodeGenOpt::Aggressive.
2021-11-01 10:43:52 -07:00
sve-fixed-length-fp-minmax.ll
[SVE] Use reg+reg addressing mode for immediate offsets.
2021-07-26 16:24:16 +01:00
sve-fixed-length-fp-reduce.ll
[SVE] Use reg+reg addressing mode for immediate offsets.
2021-07-26 16:24:16 +01:00
sve-fixed-length-fp-rounding.ll
[SVE] Use reg+reg addressing mode for immediate offsets.
2021-07-26 16:24:16 +01:00
sve-fixed-length-fp-select.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
sve-fixed-length-fp-to-int.ll
[AArch64][SVE] Add fixed type lowering for EXTRACT_SUBVECTOR
2021-10-12 14:56:15 +00:00
sve-fixed-length-fp-vselect.ll
[AArch64] Convert sra(X, elt_size(X)-1) to cmlt(X, 0)
2021-12-14 16:03:02 +00:00
sve-fixed-length-insert-vector-elt.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
sve-fixed-length-int-arith.ll
[SVE] Remove AArch64ISD::ADD_PRED and AArch64ISD::SUB_PRED.
2022-02-10 17:22:01 +00:00
sve-fixed-length-int-compares.ll
[SVE] Use reg+reg addressing mode for immediate offsets.
2021-07-26 16:24:16 +01:00
sve-fixed-length-int-div.ll
[SchedModels][CortexA55] Add ASIMD integer instructions
2022-02-17 13:41:57 +03:00
sve-fixed-length-int-extends.ll
[SVE] Remove AArch64ISD::ADD_PRED and AArch64ISD::SUB_PRED.
2022-02-10 17:22:01 +00:00
sve-fixed-length-int-immediates.ll
[SVE] Remove AArch64ISD::ADD_PRED and AArch64ISD::SUB_PRED.
2022-02-10 17:22:01 +00:00
sve-fixed-length-int-log.ll
…
sve-fixed-length-int-minmax.ll
[SVE] Use reg+reg addressing mode for immediate offsets.
2021-07-26 16:24:16 +01:00
sve-fixed-length-int-mulh.ll
[SchedModels][CortexA55] Add ASIMD integer instructions
2022-02-17 13:41:57 +03:00
sve-fixed-length-int-reduce.ll
[SVE] Remove AArch64ISD::ADD_PRED and AArch64ISD::SUB_PRED.
2022-02-10 17:22:01 +00:00
sve-fixed-length-int-rem.ll
[SchedModels][CortexA55] Add ASIMD integer instructions
2022-02-17 13:41:57 +03:00
sve-fixed-length-int-select.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
sve-fixed-length-int-shifts.ll
[SVE] Use reg+reg addressing mode for immediate offsets.
2021-07-26 16:24:16 +01:00
sve-fixed-length-int-to-fp.ll
[AArch64][SVE] Add fixed type lowering for EXTRACT_SUBVECTOR
2021-10-12 14:56:15 +00:00
sve-fixed-length-int-vselect.ll
[AArch64] Convert sra(X, elt_size(X)-1) to cmlt(X, 0)
2021-12-14 16:03:02 +00:00
sve-fixed-length-limit-duplane.ll
[SVE] Remove AArch64ISD::ADD_PRED and AArch64ISD::SUB_PRED.
2022-02-10 17:22:01 +00:00
sve-fixed-length-loads.ll
[SVE] Use reg+reg addressing mode for immediate offsets.
2021-07-26 16:24:16 +01:00
sve-fixed-length-log-reduce.ll
[SVE] Use reg+reg addressing mode for immediate offsets.
2021-07-26 16:24:16 +01:00
sve-fixed-length-mask-opt.ll
[SVE] Prefer zero-extending loads when lowering ISD::EXTLOAD.
2022-02-10 14:30:28 +00:00
sve-fixed-length-masked-gather.ll
[SVE] Remove AArch64ISD::ADD_PRED and AArch64ISD::SUB_PRED.
2022-02-10 17:22:01 +00:00
sve-fixed-length-masked-loads.ll
[AArch64][SVE][VLS] Move extends into arguments of comparisons
2022-01-28 14:16:08 +00:00
sve-fixed-length-masked-scatter.ll
[SchedModels][CortexA55] Add ASIMD integer instructions
2022-02-17 13:41:57 +03:00
sve-fixed-length-masked-stores.ll
[DAG][sve] Lowering for VLS masked truncating stores
2021-12-17 15:04:45 +00:00
sve-fixed-length-optimize-ptrue.ll
[SVE] Remove AArch64ISD::ADD_PRED and AArch64ISD::SUB_PRED.
2022-02-10 17:22:01 +00:00
sve-fixed-length-permute-rev.ll
[AArch64][SVE] Lower shuffles to permute instructions: rev/revb/revh/revw
2021-12-15 21:53:00 +08:00
sve-fixed-length-permute-zip-uzp-trn.ll
[SVE] Remove AArch64ISD::ADD_PRED and AArch64ISD::SUB_PRED.
2022-02-10 17:22:01 +00:00
sve-fixed-length-ptest.ll
[AArch64][SVE] NFC: Add test file for predicate vector reductions.
2022-02-09 15:00:08 +00:00
sve-fixed-length-reshuffle.ll
[SVE][CodeGen] Bail out for scalable vectors in AArch64TargetLowering::ReconstructShuffle
2022-02-10 14:18:49 +00:00
sve-fixed-length-rev.ll
[SVE] Use reg+reg addressing mode for immediate offsets.
2021-07-26 16:24:16 +01:00
sve-fixed-length-sdiv-pow2.ll
[AArch64] NFC: Clarify and auto-generate some CodeGen tests.
2022-01-24 17:42:37 +00:00
sve-fixed-length-shuffles.ll
[AArch64][SVE] Fix selection failure during lowering of shuffle_vector
2022-02-10 12:07:51 +00:00
sve-fixed-length-splat-vector.ll
[SVE] Use reg+reg addressing mode for immediate offsets.
2021-07-26 16:24:16 +01:00
sve-fixed-length-stores.ll
[SVE] Use reg+reg addressing mode for immediate offsets.
2021-07-26 16:24:16 +01:00
sve-fixed-length-subvector.ll
[SVE] Remove checks for warnings in scalable-vector tests.
2021-04-07 15:59:32 +01:00
sve-fixed-length-trunc-stores.ll
[SVE] Use reg+reg addressing mode for immediate offsets.
2021-07-26 16:24:16 +01:00
sve-fixed-length-trunc.ll
[SVE] Remove AArch64ISD::ADD_PRED and AArch64ISD::SUB_PRED.
2022-02-10 17:22:01 +00:00
sve-fixed-length-vector-shuffle.ll
[AArch64][SVE] Use TargetFrameIndex in more SVE load/store addressing modes
2021-10-29 14:44:16 +00:00
sve-fold-vscale.ll
[SVE][LSR] Teach LSR to enable simple scaled-index addressing mode generation for SVE.
2021-06-14 16:42:34 -07:00
sve-forward-st-to-ld.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
sve-fp-combine.ll
[SVE] Only combine (fneg (fma)) => FNMLA with nsz
2021-12-13 11:33:07 +00:00
sve-fp-immediates-merging.ll
[llvm][AArch64][SVE] Fold literals into math instructions
2021-10-17 10:57:04 +00:00
sve-fp-reciprocal.ll
[SVE][CodeGen] Enable reciprocal estimates for scalable fdiv/fsqrt
2021-10-25 11:30:44 +01:00
sve-fp-reduce.ll
[SVE] Remove checks for warnings in scalable-vector tests.
2021-04-07 15:59:32 +01:00
sve-fp-rounding.ll
…
sve-fp-vselect.ll
[AArch64][SVE] Fold vselect into predicated fmul, fsub and fadd
2022-02-03 13:43:15 +00:00
sve-fp.ll
[SVE] Add ISel for fabs(fsub(a,b)) ==> FABD.
2022-01-05 11:59:25 +00:00
sve-fpext-load.ll
[AArch64][SVE] Remove false register dependency for unary FP convert operations
2022-02-04 09:55:39 +00:00
sve-fptrunc-store.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
sve-gather-scatter-addr-opts.ll
[SVE] Prefer zero-extending loads when lowering ISD::EXTLOAD.
2022-02-10 14:30:28 +00:00
sve-gather-scatter-dag-combine.ll
[AArch64][SVE] Break false dependencies for inactive lanes of unary operations
2021-07-26 15:01:21 +00:00
sve-gep.ll
[SVE][CodeGen] Add patterns for ADD/SUB + element count
2021-10-13 11:36:15 +01:00
sve-implicit-zero-filling.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
sve-insert-element.ll
[AArch64][SVE] Use TargetFrameIndex in more SVE load/store addressing modes
2021-10-29 14:44:16 +00:00
sve-insert-vector-to-predicate-load.ll
[AArch64][SVE] Combine bitcasts of predicate types with vector inserts/extracts of loads/stores
2021-08-04 15:51:14 +00:00
sve-insert-vector.ll
[DAGCombiner] Fold `ty1 extract_vector(ty2 splat(V)) -> ty1 splat(V)`
2022-02-09 14:30:01 +00:00
sve-insr.ll
[AArch64][SVE] Use SIMD variant of INSR when scalar is the result of a vector extract
2021-04-29 12:17:42 +01:00
sve-int-arith-imm.ll
[SVE] Use DUPM to handling more splat immediate cases.
2022-01-26 12:04:44 +00:00
sve-int-arith-pred.ll
[SVE] Remove checks for warnings in scalable-vector tests.
2021-04-07 15:59:32 +01:00
sve-int-arith.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
sve-int-div-pred.ll
[SVE] Remove checks for warnings in scalable-vector tests.
2021-04-07 15:59:32 +01:00
sve-int-imm.ll
[AArch64][SVE] Fix missed immediate selection due to mishandling of signedness
2021-05-13 16:02:49 +01:00
sve-int-log-imm.ll
[SVE] Remove checks for warnings in scalable-vector tests.
2021-04-07 15:59:32 +01:00
sve-int-log-pred.ll
[SVE] Remove checks for warnings in scalable-vector tests.
2021-04-07 15:59:32 +01:00
sve-int-log.ll
[SVE] By using SEL when orring predicates we forgo the need for a PTRUE.
2022-01-31 19:39:23 +00:00
sve-int-mad-pred.ll
[SVE] Remove checks for warnings in scalable-vector tests.
2021-04-07 15:59:32 +01:00
sve-int-mul-pred.ll
[SVE] Remove checks for warnings in scalable-vector tests.
2021-04-07 15:59:32 +01:00
sve-int-mulh-pred.ll
[AArch64][SVE] Lower MULHU/MULHS nodes to umulh/smulh instructions
2021-04-20 15:18:06 +01:00
sve-int-pred-reduce.ll
[AArch64][SVE] Avoid using ptrue for ptest in VECREDUCE_OR.
2022-01-27 11:44:49 +00:00
sve-int-reduce-pred.ll
[SVE] Remove checks for warnings in scalable-vector tests.
2021-04-07 15:59:32 +01:00
sve-int-reduce.ll
[SVE] Remove checks for warnings in scalable-vector tests.
2021-04-07 15:59:32 +01:00
sve-intrinsics-adr.ll
[SVE] Remove checks for warnings in scalable-vector tests.
2021-04-07 15:59:32 +01:00
sve-intrinsics-bfloat.ll
[SVE] Remove checks for warnings in scalable-vector tests.
2021-04-07 15:59:32 +01:00
sve-intrinsics-contiguous-prefetches.ll
[SVE] Remove checks for warnings in scalable-vector tests.
2021-04-07 15:59:32 +01:00
sve-intrinsics-conversion.ll
[SVE] Remove checks for warnings in scalable-vector tests.
2021-04-07 15:59:32 +01:00
sve-intrinsics-counting-bits.ll
[SVE] Remove checks for warnings in scalable-vector tests.
2021-04-07 15:59:32 +01:00
sve-intrinsics-counting-elems-i32.ll
[NFC][SVE] Add missing tests for i32 INC/DEC patterns.
2021-12-17 13:13:36 +00:00
sve-intrinsics-counting-elems.ll
[SVE][CodeGen] Add patterns for ADD/SUB + element count
2021-10-13 11:36:15 +01:00
sve-intrinsics-create-tuple.ll
[SVE] Remove checks for warnings in scalable-vector tests.
2021-04-07 15:59:32 +01:00
sve-intrinsics-dup-x.ll
[SVE] Remove checks for warnings in scalable-vector tests.
2021-04-07 15:59:32 +01:00
sve-intrinsics-ff-gather-loads-32bit-scaled-offsets.ll
[SVE] Remove checks for warnings in scalable-vector tests.
2021-04-07 15:59:32 +01:00
sve-intrinsics-ff-gather-loads-32bit-unscaled-offsets.ll
[SVE] Remove checks for warnings in scalable-vector tests.
2021-04-07 15:59:32 +01:00
sve-intrinsics-ff-gather-loads-64bit-scaled-offset.ll
[SVE] Remove checks for warnings in scalable-vector tests.
2021-04-07 15:59:32 +01:00
sve-intrinsics-ff-gather-loads-64bit-unscaled-offset.ll
[SVE] Remove checks for warnings in scalable-vector tests.
2021-04-07 15:59:32 +01:00
sve-intrinsics-ff-gather-loads-vector-base-imm-offset.ll
[SVE] Remove checks for warnings in scalable-vector tests.
2021-04-07 15:59:32 +01:00
sve-intrinsics-ff-gather-loads-vector-base-scalar-offset.ll
[SVE] Remove checks for warnings in scalable-vector tests.
2021-04-07 15:59:32 +01:00
sve-intrinsics-ffr-manipulation.ll
[CodeGen][AArch64][SVE] Canonicalize intrinsic rdffr{ => _z}
2021-05-20 16:22:50 +00:00
sve-intrinsics-fp-arith-imm.ll
[llvm][AArch64][SVE] Fold literals into math instructions
2021-10-17 10:57:04 +00:00
sve-intrinsics-fp-arith-merging.ll
[SVE] Remove checks for warnings in scalable-vector tests.
2021-04-07 15:59:32 +01:00
sve-intrinsics-fp-arith.ll
[SVE] Remove checks for warnings in scalable-vector tests.
2021-04-07 15:59:32 +01:00
sve-intrinsics-fp-compares.ll
[AArch64][SVE] Add ISel patterns for floating point compare with zero instructions
2021-07-08 10:46:12 +00:00
sve-intrinsics-fp-converts.ll
[SVE] Remove checks for warnings in scalable-vector tests.
2021-04-07 15:59:32 +01:00
sve-intrinsics-fp-reduce.ll
[SVE] Remove checks for warnings in scalable-vector tests.
2021-04-07 15:59:32 +01:00
sve-intrinsics-gather-loads-32bit-scaled-offsets.ll
[SVE] Remove checks for warnings in scalable-vector tests.
2021-04-07 15:59:32 +01:00
sve-intrinsics-gather-loads-32bit-unscaled-offsets.ll
[SVE] Remove checks for warnings in scalable-vector tests.
2021-04-07 15:59:32 +01:00
sve-intrinsics-gather-loads-64bit-scaled-offset.ll
[SVE] Remove checks for warnings in scalable-vector tests.
2021-04-07 15:59:32 +01:00
sve-intrinsics-gather-loads-64bit-unscaled-offset.ll
[SVE] Remove checks for warnings in scalable-vector tests.
2021-04-07 15:59:32 +01:00
sve-intrinsics-gather-loads-vector-base-imm-offset.ll
[SVE] Remove checks for warnings in scalable-vector tests.
2021-04-07 15:59:32 +01:00
sve-intrinsics-gather-loads-vector-base-scalar-offset.ll
[SVE] Remove checks for warnings in scalable-vector tests.
2021-04-07 15:59:32 +01:00
sve-intrinsics-gather-prefetches-scalar-base-vector-indexes.ll
[SVE] Remove checks for warnings in scalable-vector tests.
2021-04-07 15:59:32 +01:00
sve-intrinsics-gather-prefetches-vect-base-imm-offset.ll
[SVE] Remove checks for warnings in scalable-vector tests.
2021-04-07 15:59:32 +01:00
sve-intrinsics-gather-prefetches-vect-base-invalid-imm-offset.ll
[SVE] Remove checks for warnings in scalable-vector tests.
2021-04-07 15:59:32 +01:00
sve-intrinsics-index.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
sve-intrinsics-insert-extract-tuple.ll
[SVE] Remove checks for warnings in scalable-vector tests.
2021-04-07 15:59:32 +01:00
sve-intrinsics-int-arith-imm.ll
[SVE] Use DUPM to handling more splat immediate cases.
2022-01-26 12:04:44 +00:00
sve-intrinsics-int-arith-merging.ll
[SVE] Remove checks for warnings in scalable-vector tests.
2021-04-07 15:59:32 +01:00
sve-intrinsics-int-arith.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
sve-intrinsics-int-compares-with-imm.ll
[AArch64][SVE] Implement all-inactive predicate with PFALSE.
2021-09-07 14:29:02 +01:00
sve-intrinsics-int-compares.ll
[AArch64][SVE] Fold predicate into compare
2022-01-10 10:52:06 +00:00
sve-intrinsics-ld1-addressing-mode-reg-imm.ll
[SVE] Remove checks for warnings in scalable-vector tests.
2021-04-07 15:59:32 +01:00
sve-intrinsics-ld1-addressing-mode-reg-reg.ll
[SVE] Remove checks for warnings in scalable-vector tests.
2021-04-07 15:59:32 +01:00
sve-intrinsics-ld1.ll
[SVE] Remove checks for warnings in scalable-vector tests.
2021-04-07 15:59:32 +01:00
sve-intrinsics-ld1ro-addressing-mode-reg-imm.ll
[SVE] Use reg+reg addressing mode for immediate offsets.
2021-07-26 16:24:16 +01:00
sve-intrinsics-ld1ro-addressing-mode-reg-reg.ll
[SVE] Remove checks for warnings in scalable-vector tests.
2021-04-07 15:59:32 +01:00
sve-intrinsics-ld1ro.ll
[SVE] Remove checks for warnings in scalable-vector tests.
2021-04-07 15:59:32 +01:00
sve-intrinsics-ldN-reg+imm-addr-mode.ll
[SVE] Remove checks for warnings in scalable-vector tests.
2021-04-07 15:59:32 +01:00
sve-intrinsics-ldN-reg+reg-addr-mode.ll
[SVE] Remove checks for warnings in scalable-vector tests.
2021-04-07 15:59:32 +01:00
sve-intrinsics-ldN-sret-reg+imm-addr-mode.ll
[AArch64][SVE] Add new ld<n> intrinsics that return a struct of vscale types
2021-10-22 14:13:17 +00:00
sve-intrinsics-ldN-sret-reg+reg-addr-mode.ll
[AArch64][SVE] Add new ld<n> intrinsics that return a struct of vscale types
2021-10-22 14:13:17 +00:00
sve-intrinsics-loads-ff.ll
[SVE] Remove checks for warnings in scalable-vector tests.
2021-04-07 15:59:32 +01:00
sve-intrinsics-loads-nf.ll
[SVE] Remove checks for warnings in scalable-vector tests.
2021-04-07 15:59:32 +01:00
sve-intrinsics-loads.ll
[SVE] Remove checks for warnings in scalable-vector tests.
2021-04-07 15:59:32 +01:00
sve-intrinsics-logical-imm.ll
[AArch64][SVE] Add unpredicated vector BIC ISD node
2021-05-14 16:12:13 +01:00
sve-intrinsics-logical.ll
[SVE] Remove checks for warnings in scalable-vector tests.
2021-04-07 15:59:32 +01:00
sve-intrinsics-matmul-fp32.ll
[SVE] Remove checks for warnings in scalable-vector tests.
2021-04-07 15:59:32 +01:00
sve-intrinsics-matmul-fp64.ll
[SVE] Remove checks for warnings in scalable-vector tests.
2021-04-07 15:59:32 +01:00
sve-intrinsics-matmul-int8.ll
[SVE] Remove checks for warnings in scalable-vector tests.
2021-04-07 15:59:32 +01:00
sve-intrinsics-perm-select-matmul-fp64.ll
[SVE] Remove checks for warnings in scalable-vector tests.
2021-04-07 15:59:32 +01:00
sve-intrinsics-perm-select.ll
[SVE] Remove checks for warnings in scalable-vector tests.
2021-04-07 15:59:32 +01:00
sve-intrinsics-pred-creation.ll
[SVE] Remove checks for warnings in scalable-vector tests.
2021-04-07 15:59:32 +01:00
sve-intrinsics-pred-operations.ll
[SVE] Remove checks for warnings in scalable-vector tests.
2021-04-07 15:59:32 +01:00
sve-intrinsics-pred-testing.ll
[SVE] Remove checks for warnings in scalable-vector tests.
2021-04-07 15:59:32 +01:00
sve-intrinsics-reinterpret.ll
[AArch64][SVE] Avoid using ptrue for unpredicated predicate AND.
2022-01-27 13:00:23 +00:00
sve-intrinsics-reversal.ll
[SVE] Remove checks for warnings in scalable-vector tests.
2021-04-07 15:59:32 +01:00
sve-intrinsics-scalar-to-vec.ll
[SVE] Remove checks for warnings in scalable-vector tests.
2021-04-07 15:59:32 +01:00
sve-intrinsics-scatter-stores-32bit-scaled-offsets.ll
[SVE] Remove checks for warnings in scalable-vector tests.
2021-04-07 15:59:32 +01:00
sve-intrinsics-scatter-stores-32bit-unscaled-offsets.ll
[SVE] Remove checks for warnings in scalable-vector tests.
2021-04-07 15:59:32 +01:00
sve-intrinsics-scatter-stores-64bit-scaled-offset.ll
[SVE] Remove checks for warnings in scalable-vector tests.
2021-04-07 15:59:32 +01:00
sve-intrinsics-scatter-stores-64bit-unscaled-offset.ll
[SVE] Remove checks for warnings in scalable-vector tests.
2021-04-07 15:59:32 +01:00
sve-intrinsics-scatter-stores-vector-base-imm-offset.ll
[SVE] Remove checks for warnings in scalable-vector tests.
2021-04-07 15:59:32 +01:00
sve-intrinsics-scatter-stores-vector-base-scalar-offset.ll
[SVE] Remove checks for warnings in scalable-vector tests.
2021-04-07 15:59:32 +01:00
sve-intrinsics-sel.ll
[SVE] Remove checks for warnings in scalable-vector tests.
2021-04-07 15:59:32 +01:00
sve-intrinsics-shifts-merging.ll
[SVE] Remove checks for warnings in scalable-vector tests.
2021-04-07 15:59:32 +01:00
sve-intrinsics-shifts.ll
[SVE] Remove checks for warnings in scalable-vector tests.
2021-04-07 15:59:32 +01:00
sve-intrinsics-sqdec.ll
[SVE] Remove checks for warnings in scalable-vector tests.
2021-04-07 15:59:32 +01:00
sve-intrinsics-sqinc.ll
[SVE] Remove checks for warnings in scalable-vector tests.
2021-04-07 15:59:32 +01:00
sve-intrinsics-st1-addressing-mode-reg-imm.ll
[SVE] Remove checks for warnings in scalable-vector tests.
2021-04-07 15:59:32 +01:00
sve-intrinsics-st1-addressing-mode-reg-reg.ll
[SVE] Remove checks for warnings in scalable-vector tests.
2021-04-07 15:59:32 +01:00
sve-intrinsics-st1.ll
[SVE] Remove checks for warnings in scalable-vector tests.
2021-04-07 15:59:32 +01:00
sve-intrinsics-stN-reg-imm-addr-mode.ll
[SVE] Remove checks for warnings in scalable-vector tests.
2021-04-07 15:59:32 +01:00
sve-intrinsics-stN-reg-reg-addr-mode.ll
[SVE] Remove checks for warnings in scalable-vector tests.
2021-04-07 15:59:32 +01:00
sve-intrinsics-stores.ll
[SVE] Remove checks for warnings in scalable-vector tests.
2021-04-07 15:59:32 +01:00
sve-intrinsics-unpred-form.ll
[AArch64][SVE] Add unpredicated vector BIC ISD node
2021-05-14 16:12:13 +01:00
sve-intrinsics-uqdec.ll
[SVE] Remove checks for warnings in scalable-vector tests.
2021-04-07 15:59:32 +01:00
sve-intrinsics-uqinc.ll
[SVE] Remove checks for warnings in scalable-vector tests.
2021-04-07 15:59:32 +01:00
sve-intrinsics-while.ll
[SVE] Remove checks for warnings in scalable-vector tests.
2021-04-07 15:59:32 +01:00
sve-ld-post-inc.ll
[SVE] Remove AArch64ISD::ADD_PRED and AArch64ISD::SUB_PRED.
2022-02-10 17:22:01 +00:00
sve-ld1-addressing-mode-reg-imm.ll
[SVE] Remove checks for warnings in scalable-vector tests.
2021-04-07 15:59:32 +01:00
sve-ld1-addressing-mode-reg-reg.ll
[AArch64][SVE] Add missing load/store patterns for unpacked bfloat vectors.
2021-09-22 09:45:33 +01:00
sve-ld1r.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
sve-ld1r.mir
[CodeGen][AArch64][SVE] Use ld1r[bhsd] for vector splat from memory
2021-07-06 12:03:54 +00:00
sve-ldnf1.mir
[AArch64][SVE] Use TargetFrameIndex in more SVE load/store addressing modes
2021-10-29 14:44:16 +00:00
sve-ldstnt1.mir
[AArch64][SVE] Use TargetFrameIndex in more SVE load/store addressing modes
2021-10-29 14:44:16 +00:00
sve-localstackalloc.mir
…
sve-lsr-scaled-index-addressing-mode.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
sve-masked-gather-32b-signed-scaled.ll
…
sve-masked-gather-32b-signed-unscaled.ll
…
sve-masked-gather-32b-unsigned-scaled.ll
…
sve-masked-gather-32b-unsigned-unscaled.ll
…
sve-masked-gather-64b-scaled.ll
…
sve-masked-gather-64b-unscaled.ll
…
sve-masked-gather-legalize.ll
[SVE] Prefer zero-extending loads when lowering ISD::EXTLOAD.
2022-02-10 14:30:28 +00:00
sve-masked-gather-vec-plus-imm.ll
…
sve-masked-gather-vec-plus-reg.ll
…
sve-masked-gather.ll
[AArch64][SVE] Add support for fixed length MSCATTER/MGATHER
2021-07-01 12:13:59 +01:00
sve-masked-ldst-nonext.ll
[SVE] Prefer zero-extending loads when lowering ISD::EXTLOAD.
2022-02-10 14:30:28 +00:00
sve-masked-ldst-sext.ll
[SVE][CodeGen] Fix incorrect legalisation of zero-extended masked loads
2021-10-27 14:15:41 +01:00
sve-masked-ldst-trunc.ll
[SVE] Remove checks for warnings in scalable-vector tests.
2021-04-07 15:59:32 +01:00
sve-masked-ldst-zext.ll
[SVE][CodeGen] Fix incorrect legalisation of zero-extended masked loads
2021-10-27 14:15:41 +01:00
sve-masked-scatter-32b-scaled.ll
…
sve-masked-scatter-32b-unscaled.ll
…
sve-masked-scatter-64b-scaled.ll
…
sve-masked-scatter-64b-unscaled.ll
…
sve-masked-scatter-legalize.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
sve-masked-scatter-vec-plus-imm.ll
…
sve-masked-scatter-vec-plus-reg.ll
…
sve-masked-scatter.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
sve-merging-stores.ll
[SVE] Remove checks for warnings in scalable-vector tests.
2021-04-07 15:59:32 +01:00
sve-no-typesize-warnings.ll
[AArch64][sve] Prevent incorrect function call on fixed width vector
2021-09-06 14:25:03 +01:00
sve-pfalse-machine-cse.mir
[AArch64][SVE] Implement PFALSE with explicit AArch64ISD node.
2022-01-27 10:30:13 +00:00
sve-pred-arith.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
sve-pred-contiguous-ldst-addressing-mode-reg-imm.ll
[SVE] Prefer zero-extending loads when lowering ISD::EXTLOAD.
2022-02-10 14:30:28 +00:00
sve-pred-contiguous-ldst-addressing-mode-reg-reg.ll
[SVE] Prefer zero-extending loads when lowering ISD::EXTLOAD.
2022-02-10 14:30:28 +00:00
sve-pred-log.ll
[SelectionDAG] Make WidenVecRes_SELECT work for scalable vectors
2021-11-17 08:55:11 +00:00
sve-pred-non-temporal-ldst-addressing-mode-reg-imm.ll
[SVE] Remove checks for warnings in scalable-vector tests.
2021-04-07 15:59:32 +01:00
sve-pred-non-temporal-ldst-addressing-mode-reg-reg.ll
[SVE] Remove checks for warnings in scalable-vector tests.
2021-04-07 15:59:32 +01:00
sve-pseudos-expand-undef.mir
…
sve-ptest-removal-brk.ll
…
sve-ptest-removal-cmpeq.ll
…
sve-ptest-removal-cmpeq.mir
…
sve-ptest-removal-cmpge.ll
…
sve-ptest-removal-cmpgt.ll
…
sve-ptest-removal-cmphi.ll
…
sve-ptest-removal-cmphs.ll
…
sve-ptest-removal-cmple.ll
…
sve-ptest-removal-cmplo.ll
…
sve-ptest-removal-cmpls.ll
…
sve-ptest-removal-cmplt.ll
…
sve-ptest-removal-cmpne.ll
…
sve-ptest-removal-match.ll
[AArch64][SVE] Remove redundant PTEST of MATCH/NMATCH results
2021-04-12 12:55:00 +01:00
sve-ptest-removal-pfirst-pnext.ll
[AArch64][SVE] Remove redundant PTEST following PNEXT/PFIRST
2021-10-05 15:10:48 +00:00
sve-ptest-removal-rdffr.mir
[CodeGen][AArch64][SVE] Fold [rdffr, ptest] => rdffrs; bugfix for optimizePTestInstr
2021-05-12 15:06:22 +01:00
sve-ptest-removal-whilege.mir
…
sve-ptest-removal-whilegt.mir
…
sve-ptest-removal-whilehi.mir
…
sve-ptest-removal-whilehs.mir
…
sve-ptest-removal-whilele.mir
…
sve-ptest-removal-whilelo.mir
…
sve-ptest-removal-whilels.mir
…
sve-ptest-removal-whilelt.mir
…
sve-ptest-removal-whilerw.mir
…
sve-ptest-removal-whilewr.mir
…
sve-punpklo-combine.ll
[AArch64] NFC: Clarify and auto-generate some CodeGen tests.
2022-01-24 17:42:37 +00:00
sve-redundant-store.ll
[SVE] Remove checks for warnings in scalable-vector tests.
2021-04-07 15:59:32 +01:00
sve-rev.ll
[SVE] Remove checks for warnings in scalable-vector tests.
2021-04-07 15:59:32 +01:00
sve-sdiv-pow2.ll
[AArch64][SVE] Generate ASRD instructions for power of 2 signed divides
2021-11-26 11:08:27 +00:00
sve-select.ll
[SelectionDAG] Make WidenVecRes_SELECT work for scalable vectors
2021-11-17 08:55:11 +00:00
sve-setcc.ll
[AArch64] NFC: Autogen check lines for sve-setcc.ll
2022-02-09 14:32:50 +00:00
sve-sext-zext.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
sve-smulo-sdnode.ll
[SVE] By using SEL when orring predicates we forgo the need for a PTRUE.
2022-01-31 19:39:23 +00:00
sve-split-extract-elt.ll
[AArch64][SVE] Use TargetFrameIndex in more SVE load/store addressing modes
2021-10-29 14:44:16 +00:00
sve-split-fcvt.ll
[AArch64][SVE] Remove false register dependency for unary FP convert operations
2022-02-04 09:55:39 +00:00
sve-split-fp-reduce.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
sve-split-insert-elt.ll
[AArch64][SVE] Use TargetFrameIndex in more SVE load/store addressing modes
2021-10-29 14:44:16 +00:00
sve-split-int-pred-reduce.ll
[SVE] By using SEL when orring predicates we forgo the need for a PTRUE.
2022-01-31 19:39:23 +00:00
sve-split-int-reduce.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
sve-split-load.ll
[SVE] Prefer zero-extending loads when lowering ISD::EXTLOAD.
2022-02-10 14:30:28 +00:00
sve-split-store.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
sve-split-trunc.ll
…
sve-srem-combine-loop.ll
[DAGCombiner] When combining REM ensure optimized div nodes are unique
2021-12-01 11:24:26 +00:00
sve-st1-addressing-mode-reg-imm.ll
[DAGCombiner] Fold `ty1 extract_vector(ty2 splat(V)) -> ty1 splat(V)`
2022-02-09 14:30:01 +00:00
sve-st1-addressing-mode-reg-reg.ll
[AArch64][SVE] Add missing load/store patterns for unpacked bfloat vectors.
2021-09-22 09:45:33 +01:00
sve-stepvector.ll
[ISEL] Canonicalize STEP_VECTOR to LHS if RHS is a splat.
2022-02-03 09:31:46 +00:00
sve-tailcall.ll
[SVE] Remove checks for warnings in scalable-vector tests.
2021-04-07 15:59:32 +01:00
sve-trunc.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
sve-umulo-sdnode.ll
[SVE] By using SEL when orring predicates we forgo the need for a PTRUE.
2022-01-31 19:39:23 +00:00
sve-unary-movprfx.ll
[AArch64][SVE] Break false dependencies for inactive lanes of FP unary operations
2021-11-15 09:15:21 +00:00
sve-varargs-callee-broken.ll
…
sve-varargs-caller-broken.ll
…
sve-varargs.ll
[SVE] Remove checks for warnings in scalable-vector tests.
2021-04-07 15:59:32 +01:00
sve-vecreduce-fold.ll
[DAGCombiner] Fold vecreduce_or/and if operand is insert_subvector.
2022-02-05 14:35:53 +00:00
sve-vector-splat.ll
[SVE] Use DUPM to handling more splat immediate cases.
2022-01-26 12:04:44 +00:00
sve-vl-arith.ll
[SVE][CodeGen] Add patterns for ADD/SUB + element count
2021-10-13 11:36:15 +01:00
sve-vscale-attr.ll
[SchedModels][CortexA55] Add ASIMD integer instructions
2022-02-17 13:41:57 +03:00
sve-vscale-combine.ll
[SVE] Remove checks for warnings in scalable-vector tests.
2021-04-07 15:59:32 +01:00
sve-vscale.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
sve-vselect-fold.ll
[AArch64][SVE] Folds VSELECT if the predicate is all active.
2022-01-27 15:58:56 +00:00
sve-vselect-imm.ll
[SVE] Use DUPM to handling more splat immediate cases.
2022-01-26 12:04:44 +00:00
sve-widen-scalable-vectortype.ll
[TargetLowering] Improve legalization of scalable vector types
2021-05-12 16:33:07 +01:00
sve-zeroinit.ll
[AArch64][SVE] Implement all-inactive predicate with PFALSE.
2021-09-07 14:29:02 +01:00
sve2-bitwise-ternary.ll
[SVE] Remove checks for warnings in scalable-vector tests.
2021-04-07 15:59:32 +01:00
sve2-fcopysign.ll
[AArch64][NEON][SVE] Lower FCOPYSIGN using AArch64ISD::BSP
2022-02-07 14:35:26 +00:00
sve2-int-addsub-long.ll
[SVE] Remove checks for warnings in scalable-vector tests.
2021-04-07 15:59:32 +01:00
sve2-int-mul.ll
[SVE] Use DUPM to handling more splat immediate cases.
2022-01-26 12:04:44 +00:00
sve2-int-mulh.ll
[AArch64][SVE] Lower MULHU/MULHS nodes to umulh/smulh instructions
2021-04-20 15:18:06 +01:00
sve2-intrinsics-binary-narrowing-add-sub.ll
[SVE] Remove checks for warnings in scalable-vector tests.
2021-04-07 15:59:32 +01:00
sve2-intrinsics-binary-narrowing-shr.ll
[AArch64][SVE][CodeGen] Add tests for RSHRN{T,B} instructions
2021-10-18 11:00:01 +00:00
sve2-intrinsics-bit-permutation.ll
[SVE] Remove checks for warnings in scalable-vector tests.
2021-04-07 15:59:32 +01:00
sve2-intrinsics-character-match.ll
[SVE] Remove checks for warnings in scalable-vector tests.
2021-04-07 15:59:32 +01:00
sve2-intrinsics-complex-dot.ll
[SVE] Remove checks for warnings in scalable-vector tests.
2021-04-07 15:59:32 +01:00
sve2-intrinsics-contiguous-conflict-detection.ll
[SVE] Remove checks for warnings in scalable-vector tests.
2021-04-07 15:59:32 +01:00
sve2-intrinsics-crypto.ll
[SVE] Remove checks for warnings in scalable-vector tests.
2021-04-07 15:59:32 +01:00
sve2-intrinsics-fp-converts.ll
[SVE] Remove checks for warnings in scalable-vector tests.
2021-04-07 15:59:32 +01:00
sve2-intrinsics-fp-int-binary-logarithm.ll
[SVE] Remove checks for warnings in scalable-vector tests.
2021-04-07 15:59:32 +01:00
sve2-intrinsics-fp-widening-mul-acc.ll
[SVE] Remove checks for warnings in scalable-vector tests.
2021-04-07 15:59:32 +01:00
sve2-intrinsics-int-arith-imm.ll
[AArch64] Regenerate some test checks. NFC
2021-09-08 11:08:32 +01:00
sve2-intrinsics-int-mul-lane.ll
[SVE] Remove checks for warnings in scalable-vector tests.
2021-04-07 15:59:32 +01:00
sve2-intrinsics-non-widening-pairwise-arith.ll
[SVE] Remove checks for warnings in scalable-vector tests.
2021-04-07 15:59:32 +01:00
sve2-intrinsics-nt-gather-loads-32bit-unscaled-offset.ll
[SVE] Remove checks for warnings in scalable-vector tests.
2021-04-07 15:59:32 +01:00
sve2-intrinsics-nt-gather-loads-64bit-scaled-offset.ll
[SVE] Remove checks for warnings in scalable-vector tests.
2021-04-07 15:59:32 +01:00
sve2-intrinsics-nt-gather-loads-64bit-unscaled-offset.ll
[SVE] Remove checks for warnings in scalable-vector tests.
2021-04-07 15:59:32 +01:00
sve2-intrinsics-nt-gather-loads-vector-base-scalar-offset.ll
[SVE] Remove checks for warnings in scalable-vector tests.
2021-04-07 15:59:32 +01:00
sve2-intrinsics-nt-scatter-stores-32bit-unscaled-offset.ll
[SVE] Remove checks for warnings in scalable-vector tests.
2021-04-07 15:59:32 +01:00
sve2-intrinsics-nt-scatter-stores-64bit-scaled-offset.ll
[SVE] Remove checks for warnings in scalable-vector tests.
2021-04-07 15:59:32 +01:00
sve2-intrinsics-nt-scatter-stores-64bit-unscaled-offset.ll
[SVE] Remove checks for warnings in scalable-vector tests.
2021-04-07 15:59:32 +01:00
sve2-intrinsics-nt-scatter-stores-vector-base-scalar-offset.ll
[SVE] Remove checks for warnings in scalable-vector tests.
2021-04-07 15:59:32 +01:00
sve2-intrinsics-perm-tb.ll
[SVE] Remove checks for warnings in scalable-vector tests.
2021-04-07 15:59:32 +01:00
sve2-intrinsics-polynomial-arithmetic-128.ll
[SVE] Remove checks for warnings in scalable-vector tests.
2021-04-07 15:59:32 +01:00
sve2-intrinsics-polynomial-arithmetic.ll
[SVE] Remove checks for warnings in scalable-vector tests.
2021-04-07 15:59:32 +01:00
sve2-intrinsics-unary-narrowing.ll
[SVE] Remove checks for warnings in scalable-vector tests.
2021-04-07 15:59:32 +01:00
sve2-intrinsics-uniform-complex-arith.ll
[SVE] Remove checks for warnings in scalable-vector tests.
2021-04-07 15:59:32 +01:00
sve2-intrinsics-uniform-dsp-zeroing.ll
[SVE] Remove checks for warnings in scalable-vector tests.
2021-04-07 15:59:32 +01:00
sve2-intrinsics-uniform-dsp.ll
[AArch64][SVE] Add support for using reverse forms of SVE2 shifts
2021-06-04 12:56:53 +01:00
sve2-intrinsics-vec-hist-count.ll
[SVE] Remove checks for warnings in scalable-vector tests.
2021-04-07 15:59:32 +01:00
sve2-intrinsics-while.ll
[SVE] Remove checks for warnings in scalable-vector tests.
2021-04-07 15:59:32 +01:00
sve2-intrinsics-widening-complex-int-arith.ll
[SVE] Remove checks for warnings in scalable-vector tests.
2021-04-07 15:59:32 +01:00
sve2-intrinsics-widening-dsp.ll
[SVE] Remove checks for warnings in scalable-vector tests.
2021-04-07 15:59:32 +01:00
sve2-intrinsics-widening-pairwise-arith.ll
[SVE] Remove checks for warnings in scalable-vector tests.
2021-04-07 15:59:32 +01:00
sve2-mla-indexed.ll
[SVE] Remove checks for warnings in scalable-vector tests.
2021-04-07 15:59:32 +01:00
sve2-mla-unpredicated.ll
[SVE] Remove checks for warnings in scalable-vector tests.
2021-04-07 15:59:32 +01:00
sve2-unary-movprfx.ll
[AArch64] Regenerate some test checks. NFC
2021-09-08 11:08:32 +01:00
swap-compare-operands.ll
…
swift-async-reg.ll
IR+AArch64: add a "swiftasync" argument attribute.
2021-05-14 11:43:58 +01:00
swift-async-unwind.ll
IR+AArch64: add a "swiftasync" argument attribute.
2021-05-14 11:43:58 +01:00
swift-async.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
swift-dynamic-async-frame.ll
Teach the backend to make references to swift_async_extendedFramePointerFlags weak if it emits it
2021-12-15 10:02:06 -08:00
swift-error.ll
…
swift-return.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
swiftcc.ll
…
swifterror.ll
[FastISel] Reuse register for bitcast that does not change MVT
2022-02-14 09:13:17 +01:00
swiftself-scavenger.ll
…
swiftself.ll
…
swifttail-arm64_32.ll
AArch64: use 4-byte slots for arm64_32 pointers in a tail call
2021-07-13 11:08:59 +01:00
swifttail-async.ll
IR/AArch64/X86: add "swifttailcc" calling convention.
2021-05-17 10:48:34 +01:00
swifttail-call.ll
SwiftTailCC: teach verifier musttail rules applicable to this CC.
2021-05-28 11:12:00 +01:00
switch-unreachable-default.ll
…
tagged-globals-pic.ll
…
tagged-globals-static.ll
…
tagp.ll
…
tail-call-unused-zext.ll
…
tail-call.ll
IR/AArch64/X86: add "swifttailcc" calling convention.
2021-05-17 10:48:34 +01:00
tailcall-bitcast-memcpy.ll
…
tailcall-ccmismatch.ll
…
tailcall-explicit-sret.ll
[TargetLowering] Only inspect attributes in the arguments for ArgListEntry
2021-05-18 14:30:22 -07:00
tailcall-fastisel.ll
…
tailcall-implicit-sret.ll
…
tailcall-mem-intrinsics.ll
…
tailcall-ssp-split-debug.ll
Reapply: StackProtector: ignore debug insts when splitting blocks.
2022-02-14 10:58:22 +00:00
tailcall-string-rvo.ll
…
tailcall_misched_graph.ll
…
tailcc-notail.ll
SwiftTailCC: teach verifier musttail rules applicable to this CC.
2021-05-28 11:12:00 +01:00
tailcc-tail-call.ll
IR/AArch64/X86: add "swifttailcc" calling convention.
2021-05-17 10:48:34 +01:00
taildup-cfi.ll
…
taildup-inst-dup-loc.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
tailmerging_in_mbp.ll
…
tbi.ll
…
tbz-tbnz.ll
…
tiny-model-pic.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
tiny-model-static.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
tiny_supported.ll
…
tme.ll
…
trunc-v1i64.ll
…
tst-br.ll
[AArch64] Regenerate some test checks. NFC
2021-09-08 09:14:01 +01:00
typepromotion-overflow.ll
[TypePromotion] Extend TypePromotion::isSafeWrap
2021-11-14 11:18:31 +00:00
typepromotion-phisret.ll
Revert "[SimplifyCFG] Start redesigning `FoldTwoEntryPHINode()`."
2022-02-03 12:32:50 +03:00
typepromotion-signed.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
uadd_sat.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
uadd_sat_plus.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
uadd_sat_vec.ll
[SchedModels][CortexA55] Add ASIMD integer instructions
2022-02-17 13:41:57 +03:00
uaddo.ll
[AArch64InstPrinter] Change printAddSubImm to comment imm value when shifted
2021-08-03 02:28:46 -07:00
ubsantrap.ll
[GlobalISel] Implement support for the "trap-func-name" attribute.
2021-09-20 14:32:01 -07:00
umulo-128-legalisation-lowering.ll
[AArch64] Genereate CCMP from And CSel
2022-02-02 13:48:16 +00:00
unfold-masked-merge-scalar-constmask-innerouter.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
unfold-masked-merge-scalar-constmask-interleavedbits.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
unfold-masked-merge-scalar-constmask-interleavedbytehalves.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
unfold-masked-merge-scalar-constmask-lowhigh.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
unfold-masked-merge-scalar-variablemask.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
unfold-masked-merge-vector-variablemask-const.ll
[ISEL] Canonicalise constant splats to RHS.
2022-01-24 09:38:36 +00:00
unfold-masked-merge-vector-variablemask.ll
Revert "[CodeGen][AArch64] Ensure isSExtCheaperThanZExt returns true for negative constants"
2022-01-18 08:40:20 +00:00
unreachable-emergency-spill-slot.mir
…
unwind-preserved-from-mir.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
unwind-preserved.ll
[AArch64] Regenerate some test checks. NFC
2021-09-08 11:08:32 +01:00
urem-lkk.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
urem-seteq-illegal-types.ll
[SchedModels][CortexA55] Add ASIMD integer instructions
2022-02-17 13:41:57 +03:00
urem-seteq-nonzero.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
urem-seteq-optsize.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
urem-seteq-vec-nonsplat.ll
[SchedModels][CortexA55] Add ASIMD integer instructions
2022-02-17 13:41:57 +03:00
urem-seteq-vec-nonzero.ll
[SchedModels][CortexA55] Add ASIMD integer instructions
2022-02-17 13:41:57 +03:00
urem-seteq-vec-splat.ll
[SchedModels][CortexA55] Add ASIMD integer instructions
2022-02-17 13:41:57 +03:00
urem-seteq-vec-tautological.ll
[SchedModels][CortexA55] Add ASIMD integer instructions
2022-02-17 13:41:57 +03:00
urem-seteq.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
urem-vector-lkk.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
use-cr-result-of-dom-icmp-st.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
ushl_sat.ll
[DAGCombiner] Fold SSHLSAT/USHLSAT to SHL when no saturation will occur
2022-02-06 18:59:06 +01:00
usub_sat.ll
…
usub_sat_plus.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
usub_sat_vec.ll
[SchedModels][CortexA55] Add ASIMD integer instructions
2022-02-17 13:41:57 +03:00
v3f-to-int.ll
…
v8.4-atomic-128.ll
AArch64: use ldp/stp for 128-bit atomic load/store in v.84 onwards
2021-09-20 09:50:11 +01:00
v8.5a-neon-frint3264-intrinsic.ll
…
v8.5a-scalar-frint3264-intrinsic.ll
…
vararg-tallcall.ll
…
variant-pcs.ll
[AArch64] Use \t in AsmStreamer to match the prevailing style
2021-05-23 11:35:42 -07:00
vcvt-oversize.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
vec-extract-branch.ll
[SimplifyCFG] Tail-merging all blocks with `ret` terminator
2021-06-24 13:15:39 +03:00
vec-libcalls.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
vec_cttz.ll
[SchedModels][CortexA55] Add ASIMD integer instructions
2022-02-17 13:41:57 +03:00
vec_uaddo.ll
[SchedModels][CortexA55] Add ASIMD integer instructions
2022-02-17 13:41:57 +03:00
vec_umulo.ll
[SchedModels][CortexA55] Add ASIMD integer instructions
2022-02-17 13:41:57 +03:00
vecreduce-add-legalization.ll
…
vecreduce-add.ll
[SchedModels][CortexA55] Add ASIMD integer instructions
2022-02-17 13:41:57 +03:00
vecreduce-and-legalization.ll
[SchedModels][CortexA55] Add ASIMD integer instructions
2022-02-17 13:41:57 +03:00
vecreduce-bool.ll
[AArch64InstPrinter] Change printAddSubImm to comment imm value when shifted
2021-08-03 02:28:46 -07:00
vecreduce-fadd-legalization-strict.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
vecreduce-fadd-legalization.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
vecreduce-fadd.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
vecreduce-fmax-legalization-nan.ll
…
vecreduce-fmax-legalization.ll
[SchedModels][CortexA55] Add ASIMD integer instructions
2022-02-17 13:41:57 +03:00
vecreduce-fmin-legalization.ll
[SchedModels][CortexA55] Add ASIMD integer instructions
2022-02-17 13:41:57 +03:00
vecreduce-fmul-legalization-strict.ll
…
vecreduce-propagate-sd-flags.ll
[DAG] Improve FMINNUM/FMAXNUM/FMINIMUM/FMAXIMUM constant folding
2021-12-19 11:45:51 +00:00
vecreduce-umax-legalization.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
vector-fcopysign.ll
[SchedModels][CortexA55] Add ASIMD integer instructions
2022-02-17 13:41:57 +03:00
vector-gep.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
vector-insert-shuffle-cycle.ll
…
vector-op-scalarize-strict.ll
[AArch64] Fix legalization of v1f64 strict_fsetcc and strict_fsetccs
2022-02-04 12:55:38 +00:00
vector-popcnt-128-ult-ugt.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
vector_merge_dep_check.ll
[Tests] Fix incorrect noalias metadata
2021-09-18 20:51:00 +02:00
vector_splat-const-shift-of-constmasked.ll
…
vldn_shuffle.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
volatile-combine.ll
AArch64: copy all parts of the mem operand across when combining a store
2021-08-19 18:26:39 +01:00
vselect-constants.ll
[SchedModels][CortexA55] Add ASIMD integer instructions
2022-02-17 13:41:57 +03:00
win-alloca-no-stack-probe.ll
…
win-alloca.ll
…
win-catchpad-nested-cxx.ll
…
win-tls.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
win64-jumptable.ll
[AArch64] [COFF] Move jump tables back to the readonly section
2021-11-23 10:13:48 +02:00
win64-no-uwtable.ll
…
win64-nocfi.ll
…
win64_vararg.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
win64_vararg_float.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
win64_vararg_float_cc.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
win64cc-backup-x18.ll
…
win_cst_pool.ll
…
windows-SEH-support.ll
…
windows-extern-weak.ll
…
windows-trap.ll
…
wineh-frame-predecrement.mir
…
wineh-frame-scavenge.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
wineh-frame0.mir
…
wineh-frame1.mir
…
wineh-frame2.mir
…
wineh-frame3.mir
…
wineh-frame4.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
wineh-frame5.mir
Revert "[NFC] remove explicit default value for strboolattr attribute in tests"
2021-05-24 19:43:40 +02:00
wineh-frame6.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
wineh-frame7.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
wineh-frame8.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
wineh-mingw.ll
…
wineh-save-lrpair1.mir
…
wineh-save-lrpair2.mir
…
wineh-save-lrpair3.mir
…
wineh-try-catch-cbz.ll
…
wineh-try-catch-nobase.ll
[AArch64InstPrinter] Change printAddSubImm to comment imm value when shifted
2021-08-03 02:28:46 -07:00
wineh-try-catch-realign.ll
…
wineh-try-catch-vla.ll
…
wineh-try-catch.ll
…
wineh-unwindhelp-via-fp.ll
…
wineh1.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
wineh2.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
wineh3.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
wineh4.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
wineh5.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
wineh6.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
wineh7.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
wineh8.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
wineh_shrinkwrap.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
wrong-callee-save-size-after-livedebugvariables.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
wrong_debug_loc_after_regalloc.ll
…
xbfiz.ll
…
xor.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
xray-attribute-instrumentation.ll
[XRay][test] Clean up llc RUN lines
2022-01-21 17:00:03 -08:00
xray-omit-function-index.ll
[XRay][test] Clean up llc RUN lines
2022-01-21 17:00:03 -08:00
xray-partial-instrumentation-skip-entry.ll
[XRay][test] Clean up llc RUN lines
2022-01-21 17:00:03 -08:00
xray-partial-instrumentation-skip-exit.ll
[XRay][test] Clean up llc RUN lines
2022-01-21 17:00:03 -08:00
xray-tail-call-sled.ll
[XRay][test] Clean up llc RUN lines
2022-01-21 17:00:03 -08:00
zero-reg.ll
…
zext-logic-shift-load.ll
…
zext-reg-coalesce.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
