llvm-project/llvm/test/MC/Disassembler/RISCV
Ana Pazos 0a5fcefa31 [RISCV] Fix disassembling of fence instruction with invalid field
Summary:
Instruction with 0 in fence field being disassembled as fence , iorw.
Printing "unknown" to match GAS behavior.

This bug was uncovered by a LLVM MC Disassembler Protocol Buffer Fuzzer
for the RISC-V assembly language.

Reviewers: asb

Subscribers: rbar, johnrusso, simoncook, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, mgrang, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, jfb, PkmX, jocewei, asb

Differential Revision: https://reviews.llvm.org/D51828

llvm-svn: 344309
2018-10-11 22:49:13 +00:00
..
fuzzer-invalid.txt
invalid-fp-rounding-mode.txt
invalid-instruction.txt [RISCV] Fix decoding of invalid instruction with C extension enabled. 2018-09-13 18:21:19 +00:00
lit.local.cfg
unknown-fence-field.txt [RISCV] Fix disassembling of fence instruction with invalid field 2018-10-11 22:49:13 +00:00