llvm-project

History

Matt Arsenault 94ebd7d9ff MachineVerifier: Verify REG_SEQUENCE Somehow there was no verification of this, other than an ad-hoc assertion in TwoAddressInstructions.		2022-09-22 09:51:15 -04:00
..
AArch64	llvm-reduce: Don't assert on functions which don't track liveness	2022-06-07 10:00:25 -04:00
AMDGPU	AMDGPU: Move test to correct location	2022-09-21 11:30:32 -04:00
ARM	CodeGen: Print/parse LLTs in MachineMemOperands	2021-06-30 16:54:13 -04:00
Generic	Untangle the mess which is MachineBasicBlock::hasAddressTaken().	2022-08-16 16:15:44 -07:00
Hexagon	CodeGen: Print/parse LLTs in MachineMemOperands	2021-06-30 16:54:13 -04:00
Mips	CodeGen: Print/parse LLTs in MachineMemOperands	2021-06-30 16:54:13 -04:00
NVPTX	…
PowerPC	CodeGen: Print/parse LLTs in MachineMemOperands	2021-06-30 16:54:13 -04:00
RISCV	[RISCV][NFC] Add missing lit.local.cfg in test/CodeGen/MIR/RISCV/	2022-04-08 12:10:20 +08:00
WebAssembly	…
X86	MachineVerifier: Verify REG_SEQUENCE	2022-09-22 09:51:15 -04:00
README	…

README

This directory contains tests for the MIR file format parser and printer. It
was necessary to split the tests across different targets as no single target
covers all features available in machine IR.

Tests for codegen passes should NOT be here but in test/CodeGen/sometarget. As
a rule of thumb this directory should only contain tests using
'llc -run-pass none'.