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llvm-project/llvm/test/tools/llvm-mca
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Simon Pilgrim 9202c9fb47 [X86] ROR*mCL instruction models should match ROL*mCL etc. 
Confirmed with Craig Topper - fix a typo that was missing a Port4 uop for ROR*mCL instructions on some Intel models.

Yet another step on the scheduler model cleanup marathon......

llvm-svn: 342846
 		2018-09-23 19:16:01 +00:00
..
AArch64 [llvm-mca] Add fields "Total uOps" and "uOps Per Cycle" to the report generated by the SummaryView. 2018-08-29 17:56:39 +00:00
ARM [llvm-mca] Add fields "Total uOps" and "uOps Per Cycle" to the report generated by the SummaryView. 2018-08-29 17:56:39 +00:00
X86 [X86] ROR*mCL instruction models should match ROL*mCL etc. 2018-09-23 19:16:01 +00:00
invalid_input_file_name.test Replace unused output filenames with /dev/null in tests 2018-07-02 18:16:44 +00:00
lit.local.cfg
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