llvm-project/llvm/test/CodeGen
Adhemerval Zanella dad55c2218 [ARM] [ELF] Fix ARMMaterializeGV for Indirect calls
Recent shouldAssumeDSOLocal changes (introduced by 961f31d8ad)
do not take in consideration the relocation model anymore.  The ARM
fast-isel pass uses the function return to set whether a global symbol
is loaded indirectly or not, and without the expected information
llvm now generates an extra load for following code:

```
$ cat test.ll
@__asan_option_detect_stack_use_after_return = external global i32
define dso_local i32 @main(i32 %argc, i8** %argv) #0 {
entry:
  %0 = load i32, i32* @__asan_option_detect_stack_use_after_return,
align 4
  %1 = icmp ne i32 %0, 0
  br i1 %1, label %2, label %3

2:
  ret i32 0

3:
  ret i32 1
}

attributes #0 = { noinline optnone }

$ lcc test.ll -o -
[...]
main:
        .fnstart
[...]
        movw    r0, :lower16:__asan_option_detect_stack_use_after_return
        movt    r0, :upper16:__asan_option_detect_stack_use_after_return
        ldr     r0, [r0]
        ldr     r0, [r0]
        cmp     r0, #0
[...]
```

And without 'optnone' it produces:
```
[...]
main:
        .fnstart
[...]
        movw    r0, :lower16:__asan_option_detect_stack_use_after_return
        movt    r0, :upper16:__asan_option_detect_stack_use_after_return
        ldr     r0, [r0]
        clz     r0, r0
        lsr     r0, r0, #5
        bx      lr

[...]
```

This triggered a lot of invalid memory access in sanitizers for
arm-linux-gnueabihf.  I checked this patch both a stage1 built with
gcc and a stage2 bootstrap and it fixes all the Linux sanitizers
issues.

Reviewed By: MaskRay

Differential Revision: https://reviews.llvm.org/D95379
2021-01-26 15:57:55 -03:00
..
AArch64 [SVE] Fix some logical arithmetic tests 2021-01-26 11:06:09 +00:00
AMDGPU AMDGPU: Fix redundant FP spilling/assert in some functions 2021-01-26 13:01:45 -05:00
ARC
ARM [ARM] [ELF] Fix ARMMaterializeGV for Indirect calls 2021-01-26 15:57:55 -03:00
AVR [update_llc_test_checks] Support AVR 2021-01-26 17:50:56 +08:00
BPF
Generic Use unary CreateShuffleVector if possible 2020-12-30 22:36:08 +09:00
Hexagon [NewPM][opt] Run the "default" AA pipeline by default 2021-01-21 21:08:54 -08:00
Inputs
Lanai
MIR [AMDGPU] Implement mir parseCustomPseudoSourceValue 2021-01-22 11:24:08 +01:00
MSP430
Mips [CodeGen] Try to make the print of memory operand alignment a little more user friendly. 2021-01-11 19:58:47 -08:00
NVPTX [NFC] Disallow unused prefixes under llvm/test/CodeGen 2021-01-11 12:32:18 -08:00
PowerPC [PowerPC] Do not emit HW loop with half precision operations 2021-01-25 20:55:56 -06:00
RISCV [RISCV] Have customLegalizeToWOp truncate to the original type instead of i32 now that we use it for i8/i16 as well. 2021-01-26 10:50:03 -08:00
SPARC [SPARC] Fix fp128 load/stores 2021-01-13 14:59:50 -08:00
SystemZ [SystemZ] misched-cutoff tests can only be tested on non-NDEBUG (assertion) builds 2021-01-14 15:46:27 +00:00
Thumb [RISCV][PrologEpilogInserter] "Float" emergency spill slots to avoid making them immediately unreachable from the stack pointer 2021-01-23 09:10:03 +00:00
Thumb2 [LSR] Drop potentially invalid nowrap flags when switching to post-inc IV (PR46943) 2021-01-25 23:13:48 +01:00
VE [VE] Update VELIntrinsic tests 2021-01-13 00:12:50 +09:00
WebAssembly [WebAssembly] Prototype new f64x2 conversions 2021-01-20 11:28:06 -08:00
WinCFGuard
WinEH
X86 [Win64] Ensure all stack frames are 8 byte aligned 2021-01-25 10:39:27 -08:00
XCore [test] Add explicit dso_local to definitions in ELF static relocation model tests 2020-12-30 15:47:16 -08:00