| .. |
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GlobalISel
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intrinsics
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rvv
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[RISCV] Adjust RISCVInstrInfoVSDPatterns.td for different pseudo instructions for different FPR.
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2021-01-26 01:00:50 -08:00 |
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add-before-shl.ll
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…
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add-imm.ll
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[RISCV] optimize addition with a pair of (addi imm)
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2020-07-07 18:57:28 -07:00 |
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addc-adde-sube-subc.ll
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…
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addcarry.ll
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…
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addimm-mulimm.ll
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[RISCV][test] Add a test for (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2) transformation
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2020-07-10 18:33:12 -07:00 |
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addrspacecast.ll
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[RISCV] Assume no-op addrspacecasts by default
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2020-12-18 21:03:37 +00:00 |
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align.ll
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…
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alloca.ll
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[RISCV][NFC] Regenerate RISCV CodeGen tests
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2020-12-09 19:42:49 +00:00 |
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alu8.ll
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[RISCV] Don't print zext.b alias.
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2021-01-05 10:41:08 -08:00 |
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alu16.ll
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…
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alu32.ll
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…
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alu64.ll
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[RISCV] Add isel pattern to match (i64 (sra (shl X, 32), C)) to SRAIW if C > 32.
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2020-11-25 21:57:48 -08:00 |
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analyze-branch.ll
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[RISCV][NFC] Regenerate RISCV CodeGen tests
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2020-12-09 19:42:49 +00:00 |
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arith-with-overflow.ll
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…
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atomic-cmpxchg-flag.ll
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…
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atomic-cmpxchg.ll
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[RISCV] Add isel patterns to remove (and X, 31) from sllw/srlw/sraw shift amounts.
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2021-01-23 15:08:18 -08:00 |
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atomic-fence.ll
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…
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atomic-load-store.ll
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[RISCV][NFC] Regenerate RISCV CodeGen tests
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2020-12-09 19:42:49 +00:00 |
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atomic-rmw.ll
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[RISCV] Add isel patterns to remove (and X, 31) from sllw/srlw/sraw shift amounts.
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2021-01-23 15:08:18 -08:00 |
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attributes.ll
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[RISCV] Update V extension to v1.0-draft 08a0b464.
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2021-01-26 12:02:43 +08:00 |
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blockaddress.ll
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[RISCV] Fix inaccurate annotations on PseudoBRIND
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2020-08-21 11:38:42 +01:00 |
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branch-relaxation.ll
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[RISCV] Indirect branch generation in position independent code
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2020-08-17 13:09:26 +01:00 |
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branch.ll
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Revert "[BPI] Improve static heuristics for integer comparisons"
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2020-08-17 20:44:33 +02:00 |
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bswap-ctlz-cttz-ctpop.ll
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[RISCV] Don't print zext.b alias.
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2021-01-05 10:41:08 -08:00 |
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byval.ll
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[RISCV][NFC] Regenerate RISCV CodeGen tests
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2020-12-09 19:42:49 +00:00 |
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callee-saved-fpr32s.ll
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[RISCV][NFC] Regenerate Calling Convention Tests
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2021-01-14 22:35:17 +00:00 |
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callee-saved-fpr64s.ll
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[RISCV][NFC] Regenerate Calling Convention Tests
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2021-01-14 22:35:17 +00:00 |
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callee-saved-gprs.ll
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[RISCV][NFC] Regenerate Calling Convention Tests
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2021-01-14 22:35:17 +00:00 |
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calling-conv-ilp32-ilp32f-common.ll
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[RISCV][NFC] Regenerate Calling Convention Tests
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2021-01-14 22:35:17 +00:00 |
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calling-conv-ilp32-ilp32f-ilp32d-common.ll
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[RISCV][NFC] Regenerate Calling Convention Tests
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2021-01-14 22:35:17 +00:00 |
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calling-conv-ilp32.ll
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[RISCV][NFC] Regenerate Calling Convention Tests
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2021-01-14 22:35:17 +00:00 |
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calling-conv-ilp32d.ll
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[RISCV][NFC] Regenerate Calling Convention Tests
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2021-01-14 22:35:17 +00:00 |
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calling-conv-ilp32f-ilp32d-common.ll
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[RISCV][NFC] Regenerate Calling Convention Tests
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2021-01-14 22:35:17 +00:00 |
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calling-conv-lp64-lp64f-common.ll
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[RISCV][NFC] Regenerate Calling Convention Tests
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2021-01-14 22:35:17 +00:00 |
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calling-conv-lp64-lp64f-lp64d-common.ll
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[RISCV][NFC] Regenerate Calling Convention Tests
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2021-01-14 22:35:17 +00:00 |
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calling-conv-lp64.ll
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[RISCV][NFC] Regenerate Calling Convention Tests
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2021-01-14 22:35:17 +00:00 |
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calling-conv-rv32f-ilp32.ll
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[RISCV][NFC] Regenerate Calling Convention Tests
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2021-01-14 22:35:17 +00:00 |
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calling-conv-sext-zext.ll
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[RISCV] Don't print zext.b alias.
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2021-01-05 10:41:08 -08:00 |
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calls.ll
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[RISCV][NFC] Regenerate RISCV CodeGen tests
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2020-12-09 19:42:49 +00:00 |
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cmp-bool.ll
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[DAGCombiner] Rebuild (setcc x, y, ==) from (xor (xor x, y), 1)
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2020-07-15 07:34:22 +00:00 |
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codemodel-lowering.ll
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[RISCV] Fix inaccurate annotations on PseudoBRIND
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2020-08-21 11:38:42 +01:00 |
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compress-float.ll
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[test] llvm/test/: change llvm-objdump single-dash long options to double-dash options
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2020-03-15 17:46:23 -07:00 |
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compress-inline-asm.ll
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[test] llvm/test/: change llvm-objdump single-dash long options to double-dash options
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2020-03-15 17:46:23 -07:00 |
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compress.ll
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[RISCV] Add support for printing pcrel immediates as absolute addresses in llvm-objdump
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2020-12-04 10:34:12 -08:00 |
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copy-frameindex.mir
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[RISCV] Only return DestSourcePair from isCopyInstrImpl for registers
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2020-11-03 03:55:47 +00:00 |
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copysign-casts.ll
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[RISCV] Add implementation of targetShrinkDemandedConstant to optimize AND immediates.
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2021-01-15 11:14:14 -08:00 |
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disable-tail-calls.ll
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…
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disjoint.ll
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…
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div.ll
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[RISCV][NFC] Regenerate RISCV CodeGen tests
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2020-12-09 19:42:49 +00:00 |
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double-arith.ll
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[RISCV] Add an implementation of isFMAFasterThanFMulAndFAdd
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2020-11-25 15:07:34 -08:00 |
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double-bitmanip-dagcombines.ll
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…
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double-br-fcmp.ll
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[RISCV] Add DAG combine to turn (setcc X, 1, setne) -> (setcc X, 0, seteq) if we can prove X is 0/1.
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2021-01-19 11:21:48 -08:00 |
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double-calling-conv.ll
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[RISCV][NFC] Regenerate RISCV CodeGen tests
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2020-12-09 19:42:49 +00:00 |
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double-convert.ll
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[RISCV] Use bitsLE instead of strict == MVT::i32 in assertsexti32 and assertzexti32.
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2021-01-24 13:58:14 -08:00 |
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double-fcmp.ll
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[LegalizeDAG][RISCV][PowerPC][AMDGPU][WebAssembly] Improve expansion of SETONE/SETUEQ on targets without SETO/SETUO.
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2021-01-12 10:45:03 -08:00 |
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double-frem.ll
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[RISCV][NFC] Regenerate RISCV CodeGen tests
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2020-12-09 19:42:49 +00:00 |
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double-imm.ll
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[RISCV] Support Constant Pools in Load/Store Peephole
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2020-05-11 19:20:38 +01:00 |
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double-intrinsics.ll
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[RISCV][NFC] Regenerate RISCV CodeGen tests
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2020-12-09 19:42:49 +00:00 |
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double-isnan.ll
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[RISCV][LegalizeDAG] Expand SETO and SETUO comparisons. Teach LegalizeDAG to expand SETUO expansion when UNE isn't legal.
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2020-12-10 09:15:52 -08:00 |
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double-mem.ll
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[RISCV][test] Add explicit dso_local to definitions in ELF static relocation model tests
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2020-12-30 15:28:11 -08:00 |
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double-previous-failure.ll
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[RISCV][NFC] Regenerate RISCV CodeGen tests
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2020-12-09 19:42:49 +00:00 |
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double-select-fcmp.ll
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[RISCV] Optimize select_cc after fp compare expansion
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2021-01-14 13:41:40 -08:00 |
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double-stack-spill-restore.ll
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[TargetLowering][RISCV] Don't transform (seteq/ne (sext_inreg X, VT), C1) -> (seteq/ne (zext_inreg X, VT), C1) if the sext_inreg is cheaper
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2021-01-25 16:37:21 -08:00 |
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dwarf-eh.ll
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…
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exception-pointer-register.ll
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[RISCV][NFC] Regenerate RISCV CodeGen tests
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2020-12-09 19:42:49 +00:00 |
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fastcc-float.ll
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[RISCV][NFC] Regenerate RISCV CodeGen tests
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2020-12-09 19:42:49 +00:00 |
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fastcc-int.ll
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[RISCV][NFC] Regenerate RISCV CodeGen tests
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2020-12-09 19:42:49 +00:00 |
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fixups-diff.ll
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[llvm-readobj] Update tests because of changes in llvm-readobj behavior
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2020-07-20 10:39:04 +01:00 |
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fixups-relax-diff.ll
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[llvm-readobj] Update tests because of changes in llvm-readobj behavior
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2020-07-20 10:39:04 +01:00 |
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float-arith.ll
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[RISCV] Add an implementation of isFMAFasterThanFMulAndFAdd
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2020-11-25 15:07:34 -08:00 |
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float-bit-preserving-dagcombines.ll
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[RISCV][NFC] Regenerate RISCV CodeGen tests
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2020-12-09 19:42:49 +00:00 |
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float-bitmanip-dagcombines.ll
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…
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float-br-fcmp.ll
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[RISCV] Add DAG combine to turn (setcc X, 1, setne) -> (setcc X, 0, seteq) if we can prove X is 0/1.
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2021-01-19 11:21:48 -08:00 |
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float-convert.ll
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[RISCV] Use bitsLE instead of strict == MVT::i32 in assertsexti32 and assertzexti32.
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2021-01-24 13:58:14 -08:00 |
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float-fcmp.ll
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[LegalizeDAG][RISCV][PowerPC][AMDGPU][WebAssembly] Improve expansion of SETONE/SETUEQ on targets without SETO/SETUO.
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2021-01-12 10:45:03 -08:00 |
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float-frem.ll
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[RISCV][NFC] Regenerate RISCV CodeGen tests
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2020-12-09 19:42:49 +00:00 |
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float-imm.ll
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[RISCV] Support Constant Pools in Load/Store Peephole
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2020-05-11 19:20:38 +01:00 |
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float-intrinsics.ll
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[RISCV][NFC] Regenerate RISCV CodeGen tests
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2020-12-09 19:42:49 +00:00 |
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float-isnan.ll
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[RISCV][LegalizeDAG] Expand SETO and SETUO comparisons. Teach LegalizeDAG to expand SETUO expansion when UNE isn't legal.
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2020-12-10 09:15:52 -08:00 |
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float-mem.ll
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[RISCV][test] Add explicit dso_local to definitions in ELF static relocation model tests
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2020-12-30 15:28:11 -08:00 |
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float-select-fcmp.ll
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[RISCV] Optimize select_cc after fp compare expansion
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2021-01-14 13:41:40 -08:00 |
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flt-rounds.ll
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…
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fold-addi-loadstore.ll
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[RISCV][test] Add explicit dso_local to definitions in ELF static relocation model tests
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2020-12-30 15:28:11 -08:00 |
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fp-imm.ll
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[RISCV] Support Constant Pools in Load/Store Peephole
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2020-05-11 19:20:38 +01:00 |
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fp16-promote.ll
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[RISCV][NFC] Regenerate RISCV CodeGen tests
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2020-12-09 19:42:49 +00:00 |
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fp128.ll
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[RISCV][NFC] Regenerate RISCV CodeGen tests
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2020-12-09 19:42:49 +00:00 |
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frame-info.ll
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[RISCV] Add implementation of targetShrinkDemandedConstant to optimize AND immediates.
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2021-01-15 11:14:14 -08:00 |
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frame.ll
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[RISCV][NFC] Regenerate RISCV CodeGen tests
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2020-12-09 19:42:49 +00:00 |
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frameaddr-returnaddr.ll
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[RISCV][NFC] Regenerate RISCV CodeGen tests
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2020-12-09 19:42:49 +00:00 |
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get-register-invalid.ll
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Revert "Revert "Reland "[Support] make report_fatal_error `abort` instead of `exit`"""
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2020-02-13 10:16:06 -08:00 |
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get-register-noreserve.ll
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…
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get-register-reserve.ll
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Revert "Revert "Reland "[Support] make report_fatal_error `abort` instead of `exit`"""
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2020-02-13 10:16:06 -08:00 |
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get-setcc-result-type.ll
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…
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ghccc-rv32.ll
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[RISCV][NFC] Regenerate RISCV CodeGen tests
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2020-12-09 19:42:49 +00:00 |
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ghccc-rv64.ll
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[RISCV][NFC] Regenerate RISCV CodeGen tests
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2020-12-09 19:42:49 +00:00 |
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half-arith.ll
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[RISCV] Add additional half precision fnmadd/fnmsub tests with an fneg on the second operand instead of the first.
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2020-12-02 21:13:42 -08:00 |
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half-bitmanip-dagcombines.ll
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[RISCV] Add implementation of targetShrinkDemandedConstant to optimize AND immediates.
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2021-01-15 11:14:14 -08:00 |
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half-br-fcmp.ll
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[RISCV] Add DAG combine to turn (setcc X, 1, setne) -> (setcc X, 0, seteq) if we can prove X is 0/1.
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2021-01-19 11:21:48 -08:00 |
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half-convert.ll
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[RISCV] Use bitsLE instead of strict == MVT::i32 in assertsexti32 and assertzexti32.
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2021-01-24 13:58:14 -08:00 |
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half-fcmp.ll
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[LegalizeDAG][RISCV][PowerPC][AMDGPU][WebAssembly] Improve expansion of SETONE/SETUEQ on targets without SETO/SETUO.
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2021-01-12 10:45:03 -08:00 |
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half-imm.ll
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[RISCV] Support Zfh half-precision floating-point extension.
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2020-12-03 09:16:33 +08:00 |
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half-intrinsics.ll
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[RISCV] Add f16 to isFMAFasterThanFMulAndFAdd now that the Zfh extension is supported
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2020-12-02 20:31:43 -08:00 |
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half-isnan.ll
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[RISCV][LegalizeDAG] Expand SETO and SETUO comparisons. Teach LegalizeDAG to expand SETUO expansion when UNE isn't legal.
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2020-12-10 09:15:52 -08:00 |
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half-mem.ll
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[RISCV][test] Add explicit dso_local to definitions in ELF static relocation model tests
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2020-12-30 15:28:11 -08:00 |
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half-select-fcmp.ll
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[RISCV] Optimize select_cc after fp compare expansion
|
2021-01-14 13:41:40 -08:00 |
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hoist-global-addr-base.ll
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[RISCV][NFC] Regenerate RISCV CodeGen tests
|
2020-12-09 19:42:49 +00:00 |
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i32-icmp.ll
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[RISCV] Optimize seteq/setne pattern expansions for better code size
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2020-02-11 22:45:15 +08:00 |
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imm-cse.ll
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…
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imm.ll
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[RISCV][NFC] Add more tests for 32-bit constant materialization
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2020-10-22 11:36:34 +01:00 |
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indirectbr.ll
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[RISCV] Fix inaccurate annotations on PseudoBRIND
|
2020-08-21 11:38:42 +01:00 |
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init-array.ll
|
…
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inline-asm-abi-names.ll
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[RISCV][NFC] Regenerate RISCV CodeGen tests
|
2020-12-09 19:42:49 +00:00 |
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inline-asm-clobbers.ll
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…
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inline-asm-d-abi-names.ll
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[RISCV][NFC] Regenerate RISCV CodeGen tests
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2020-12-09 19:42:49 +00:00 |
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inline-asm-d-constraint-f.ll
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…
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inline-asm-f-abi-names.ll
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[RISCV][NFC] Regenerate RISCV CodeGen tests
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2020-12-09 19:42:49 +00:00 |
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inline-asm-f-constraint-f.ll
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…
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inline-asm-i-constraint-i1.ll
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…
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inline-asm-invalid.ll
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…
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inline-asm.ll
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[MC][RISCV] Set UseIntegratedAssembler to true
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2020-07-12 21:04:48 -07:00 |
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interrupt-attr-args-error.ll
|
Revert "Revert "Reland "[Support] make report_fatal_error `abort` instead of `exit`"""
|
2020-02-13 10:16:06 -08:00 |
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interrupt-attr-callee.ll
|
[RISCV][NFC] Regenerate RISCV CodeGen tests
|
2020-12-09 19:42:49 +00:00 |
|
interrupt-attr-invalid.ll
|
Revert "Revert "Reland "[Support] make report_fatal_error `abort` instead of `exit`"""
|
2020-02-13 10:16:06 -08:00 |
|
interrupt-attr-nocall.ll
|
[RISCV][NFC] Regenerate RISCV CodeGen tests
|
2020-12-09 19:42:49 +00:00 |
|
interrupt-attr-ret-error.ll
|
Revert "Revert "Reland "[Support] make report_fatal_error `abort` instead of `exit`"""
|
2020-02-13 10:16:06 -08:00 |
|
interrupt-attr.ll
|
[RISCV][NFC] Regenerate RISCV CodeGen tests
|
2020-12-09 19:42:49 +00:00 |
|
jumptable.ll
|
[RISCV] Basic jump table lowering
|
2020-12-22 15:05:54 +00:00 |
|
large-stack.ll
|
[RISCV][NFC] Regenerate RISCV CodeGen tests
|
2020-12-09 19:42:49 +00:00 |
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legalize-fneg.ll
|
…
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lit.local.cfg
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…
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lsr-legaladdimm.ll
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…
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machineoutliner.mir
|
…
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mattr-invalid-combination.ll
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Revert "Revert "Reland "[Support] make report_fatal_error `abort` instead of `exit`"""
|
2020-02-13 10:16:06 -08:00 |
|
mem.ll
|
[RISCV][test] Add explicit dso_local to definitions in ELF static relocation model tests
|
2020-12-30 15:28:11 -08:00 |
|
mem64.ll
|
[RISCV][test] Add explicit dso_local to definitions in ELF static relocation model tests
|
2020-12-30 15:28:11 -08:00 |
|
mir-target-flags.ll
|
[TargetMachine] Don't imply dso_local on function declarations in Reloc::Static model for ELF/wasm
|
2020-12-05 14:54:37 -08:00 |
|
module-target-abi.ll
|
Revert "Revert "Reland "[Support] make report_fatal_error `abort` instead of `exit`"""
|
2020-02-13 10:16:06 -08:00 |
|
module-target-abi2.ll
|
Revert "Revert "Reland "[Support] make report_fatal_error `abort` instead of `exit`"""
|
2020-02-13 10:16:06 -08:00 |
|
mul.ll
|
[RISCV] Optimize multiplication with constant
|
2021-01-09 10:37:21 +08:00 |
|
musttail-call.ll
|
OpaquePtr: Bulk update tests to use typed sret
|
2020-11-20 17:58:26 -05:00 |
|
neg-abs.ll
|
[RISCV][NFC] Increase test coverage of Zbt extension
|
2021-01-18 17:30:35 +00:00 |
|
nomerge.ll
|
Add NoMerge MIFlag to avoid MIR branch folding
|
2020-05-29 12:31:06 -07:00 |
|
option-nopic.ll
|
[RISCV][AsmParser] Implement .option (no)pic
|
2020-04-17 12:08:30 +00:00 |
|
option-norelax.ll
|
[llvm-objdump] -d: print `00000000 <foo>:` instead of `00000000 foo:`
|
2020-03-05 18:05:28 -08:00 |
|
option-norvc.ll
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[test] llvm/test/: change llvm-objdump single-dash long options to double-dash options
|
2020-03-15 17:46:23 -07:00 |
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option-pic.ll
|
[RISCV][AsmParser] Implement .option (no)pic
|
2020-04-17 12:08:30 +00:00 |
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option-relax.ll
|
[llvm-objdump] -d: print `00000000 <foo>:` instead of `00000000 foo:`
|
2020-03-05 18:05:28 -08:00 |
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option-rvc.ll
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[test] llvm/test/: change llvm-objdump single-dash long options to double-dash options
|
2020-03-15 17:46:23 -07:00 |
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out-of-reach-emergency-slot.mir
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[RISCV][PrologEpilogInserter] "Float" emergency spill slots to avoid making them immediately unreachable from the stack pointer
|
2021-01-23 09:10:03 +00:00 |
|
pic-models.ll
|
Revert "[RISCV] Avoid Splitting MBB in RISCVExpandPseudo"
|
2020-07-14 11:15:01 +01:00 |
|
pr40333.ll
|
…
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prefetch.ll
|
…
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readcyclecounter.ll
|
…
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rem.ll
|
[RISCV][NFC] Regenerate RISCV CodeGen tests
|
2020-12-09 19:42:49 +00:00 |
|
remat.ll
|
[RISCV][NFC] Regenerate RISCV CodeGen tests
|
2020-12-09 19:42:49 +00:00 |
|
reserved-reg-errors.ll
|
…
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reserved-regs.ll
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…
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rotl-rotr.ll
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…
|
|
|
rv32Zba.ll
|
[RISCV] Add isel patterns for SH*ADD(.UW)
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2021-01-22 13:28:41 -08:00 |
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rv32Zbb.ll
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[RISCV] Add support for rev8 and orc.b to Zbb.
|
2021-01-22 12:49:10 -08:00 |
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rv32Zbbp.ll
|
[RISCV] Move pack instructions to Zbp extension only.
|
2021-01-22 12:49:10 -08:00 |
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rv32Zbp.ll
|
[RISCV] Add isel patterns to remove masks on SLO/SRO shift amounts.
|
2021-01-23 15:57:41 -08:00 |
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rv32Zbs.ll
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[RISCV] Rename Zbs instructions to start with just 'b' instead of 'sb' to match 0.93 bitmanip spec.
|
2021-01-22 12:49:10 -08:00 |
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rv32Zbt.ll
|
[RISCV] Rename Zbs instructions to start with just 'b' instead of 'sb' to match 0.93 bitmanip spec.
|
2021-01-22 12:49:10 -08:00 |
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rv32e.ll
|
Revert "Revert "Reland "[Support] make report_fatal_error `abort` instead of `exit`"""
|
2020-02-13 10:16:06 -08:00 |
|
rv32i-rv64i-float-double.ll
|
[RISCV][NFC] Regenerate RISCV CodeGen tests
|
2020-12-09 19:42:49 +00:00 |
|
rv32i-rv64i-half.ll
|
[RISCV][NFC] Regenerate RISCV CodeGen tests
|
2020-12-09 19:42:49 +00:00 |
|
rv64-large-stack.ll
|
[RISCV][NFC] Regenerate RISCV CodeGen tests
|
2020-12-09 19:42:49 +00:00 |
|
rv64Zba.ll
|
[RISCV] Add isel patterns to optimize slli.uw patterns without Zba extension.
|
2021-01-25 16:12:08 -08:00 |
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rv64Zbb.ll
|
[RISCV] Add support for rev8 and orc.b to Zbb.
|
2021-01-22 12:49:10 -08:00 |
|
rv64Zbbp.ll
|
[RISCV] Move pack instructions to Zbp extension only.
|
2021-01-22 12:49:10 -08:00 |
|
rv64Zbp.ll
|
[RISCV] Add isel patterns to remove masks on SLO/SRO shift amounts.
|
2021-01-23 15:57:41 -08:00 |
|
rv64Zbs.ll
|
[RISCV] Rename Zbs instructions to start with just 'b' instead of 'sb' to match 0.93 bitmanip spec.
|
2021-01-22 12:49:10 -08:00 |
|
rv64Zbt.ll
|
Recommit "[RISCV] Legalize select when Zbt extension available"
|
2021-01-21 12:07:44 -08:00 |
|
rv64d-double-convert.ll
|
[RISCV] Use fcvt.h/d/f.w if the input is an assertsexti32 not just when the input is sext_inreg.
|
2020-12-04 18:40:02 -08:00 |
|
rv64f-float-convert.ll
|
[RISCV] Use fcvt.h/d/f.w if the input is an assertsexti32 not just when the input is sext_inreg.
|
2020-12-04 18:40:02 -08:00 |
|
rv64f-half-convert.ll
|
[RISCV] Use fcvt.h/d/f.w if the input is an assertsexti32 not just when the input is sext_inreg.
|
2020-12-04 18:40:02 -08:00 |
|
rv64i-complex-float.ll
|
[RISCV][NFC] Regenerate RISCV CodeGen tests
|
2020-12-09 19:42:49 +00:00 |
|
rv64i-demanded-bits.ll
|
[RISCV] Improve worklist management in the DAG combine for SLLW/SRLW/SRAW
|
2020-10-29 14:52:53 -07:00 |
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rv64i-double-softfloat.ll
|
[RISCV][NFC] Regenerate RISCV CodeGen tests
|
2020-12-09 19:42:49 +00:00 |
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rv64i-exhaustive-w-insts.ll
|
…
|
|
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rv64i-single-softfloat.ll
|
[RISCV] Use sign extend for i32 arguments and returns in makeLibCall on RV64.
|
2021-01-25 09:33:48 -08:00 |
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rv64i-tricky-shifts.ll
|
…
|
|
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rv64i-w-insts-legalization.ll
|
…
|
|
|
rv64m-exhaustive-w-insts.ll
|
[RISCV] Have customLegalizeToWOp truncate to the original type instead of i32 now that we use it for i8/i16 as well.
|
2021-01-26 10:50:03 -08:00 |
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rv64m-w-insts-legalization.ll
|
Revert "[BPI] Improve static heuristics for integer comparisons"
|
2020-08-17 20:44:33 +02:00 |
|
saverestore.ll
|
[RISCV] Add support for save/restore of callee-saved registers via libcalls
|
2020-02-11 21:23:03 +00:00 |
|
scalable-vector-struct.ll
|
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
|
2021-01-22 07:55:24 +08:00 |
|
sdata-limit-0.ll
|
…
|
|
|
sdata-limit-4.ll
|
…
|
|
|
sdata-limit-8.ll
|
…
|
|
|
sdata-local-sym.ll
|
…
|
|
|
select-and.ll
|
Recommit "[RISCV] Legalize select when Zbt extension available"
|
2021-01-21 12:07:44 -08:00 |
|
select-bare.ll
|
Recommit "[RISCV] Legalize select when Zbt extension available"
|
2021-01-21 12:07:44 -08:00 |
|
select-cc.ll
|
Recommit "[RISCV] Legalize select when Zbt extension available"
|
2021-01-21 12:07:44 -08:00 |
|
select-const.ll
|
Recommit "[RISCV] Legalize select when Zbt extension available"
|
2021-01-21 12:07:44 -08:00 |
|
select-optimize-multiple.ll
|
[RISCV] Add more cmov isel patterns to handle seteq/ne with a small non-zero immediate.
|
2021-01-22 14:51:22 -08:00 |
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select-optimize-multiple.mir
|
[RISCV][NFC] Increase test coverage of Zbt extension
|
2021-01-18 17:30:35 +00:00 |
|
select-or.ll
|
Recommit "[RISCV] Legalize select when Zbt extension available"
|
2021-01-21 12:07:44 -08:00 |
|
setcc-logic.ll
|
[TargetLowering][RISCV] Don't transform (seteq/ne (sext_inreg X, VT), C1) -> (seteq/ne (zext_inreg X, VT), C1) if the sext_inreg is cheaper
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2021-01-25 16:37:21 -08:00 |
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sext-zext-trunc.ll
|
[TargetLowering][RISCV] Don't transform (seteq/ne (sext_inreg X, VT), C1) -> (seteq/ne (zext_inreg X, VT), C1) if the sext_inreg is cheaper
|
2021-01-25 16:37:21 -08:00 |
|
shadowcallstack.ll
|
[RISCV][NFC] Regenerate RISCV CodeGen tests
|
2020-12-09 19:42:49 +00:00 |
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shift-masked-shamt.ll
|
…
|
|
|
shifts.ll
|
[RISCV][NFC] Regenerate RISCV CodeGen tests
|
2020-12-09 19:42:49 +00:00 |
|
shrinkwrap.ll
|
[RISCV][NFC] Regenerate RISCV CodeGen tests
|
2020-12-09 19:42:49 +00:00 |
|
split-offsets.ll
|
…
|
|
|
split-sp-adjust.ll
|
[RISCV][NFC] Regenerate RISCV CodeGen tests
|
2020-12-09 19:42:49 +00:00 |
|
srem-lkk.ll
|
[RISCV] Add implementation of targetShrinkDemandedConstant to optimize AND immediates.
|
2021-01-15 11:14:14 -08:00 |
|
srem-vector-lkk.ll
|
[RISCV] Add implementation of targetShrinkDemandedConstant to optimize AND immediates.
|
2021-01-15 11:14:14 -08:00 |
|
stack-realignment-with-variable-sized-objects.ll
|
[RISCV] Add implementation of targetShrinkDemandedConstant to optimize AND immediates.
|
2021-01-15 11:14:14 -08:00 |
|
stack-realignment.ll
|
[RISCV][NFC] Regenerate Calling Convention Tests
|
2021-01-14 22:35:17 +00:00 |
|
stack-store-check.ll
|
[RISCV][NFC] Regenerate RISCV CodeGen tests
|
2020-12-09 19:42:49 +00:00 |
|
subtarget-features-std-ext.ll
|
…
|
|
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tail-calls.ll
|
OpaquePtr: Bulk update tests to use typed sret
|
2020-11-20 17:58:26 -05:00 |
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target-abi-invalid.ll
|
…
|
|
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target-abi-valid.ll
|
Revert "Revert "Reland "[Support] make report_fatal_error `abort` instead of `exit`"""
|
2020-02-13 10:16:06 -08:00 |
|
thread-pointer.ll
|
[RISCV] Support llvm.thread.pointer
|
2020-03-27 17:30:12 -07:00 |
|
tls-models.ll
|
[RISCV][NFC] Regenerate RISCV CodeGen tests
|
2020-12-09 19:42:49 +00:00 |
|
umulo-128-legalisation-lowering.ll
|
[RISCV][NFC] Regenerate RISCV CodeGen tests
|
2020-12-09 19:42:49 +00:00 |
|
urem-lkk.ll
|
[RISCV][NFC] Regenerate RISCV CodeGen tests
|
2020-12-09 19:42:49 +00:00 |
|
urem-vector-lkk.ll
|
[RISCV][NFC] Regenerate RISCV CodeGen tests
|
2020-12-09 19:42:49 +00:00 |
|
vararg.ll
|
[RISCV] Add implementation of targetShrinkDemandedConstant to optimize AND immediates.
|
2021-01-15 11:14:14 -08:00 |
|
verify-instr.mir
|
Revert "Revert "Reland "[Support] make report_fatal_error `abort` instead of `exit`"""
|
2020-02-13 10:16:06 -08:00 |
|
vfrece7-rv32.ll
|
[RISCV] Add intrinsics for RVV1.0 VFRSQRTE7 & VFRECE7
|
2021-01-21 18:38:49 -08:00 |
|
vfrece7-rv64.ll
|
[RISCV] Add intrinsics for RVV1.0 VFRSQRTE7 & VFRECE7
|
2021-01-21 18:38:49 -08:00 |
|
vfrsqrte7-rv32.ll
|
[RISCV] Add intrinsics for RVV1.0 VFRSQRTE7 & VFRECE7
|
2021-01-21 18:38:49 -08:00 |
|
vfrsqrte7-rv64.ll
|
[RISCV] Add intrinsics for RVV1.0 VFRSQRTE7 & VFRECE7
|
2021-01-21 18:38:49 -08:00 |
|
wide-mem.ll
|
[RISCV] Fold ADDIs into load/stores with nonzero offsets
|
2020-07-06 17:32:57 +01:00 |
|
zext-with-load-is-free.ll
|
[RISCV][test] Add explicit dso_local to definitions in ELF static relocation model tests
|
2020-12-30 15:28:11 -08:00 |
|
zfh-imm.ll
|
[RISCV] Support Zfh half-precision floating-point extension.
|
2020-12-03 09:16:33 +08:00 |
f9d7f77267