79 lines
3.1 KiB
LLVM
79 lines
3.1 KiB
LLVM
; RUN: opt --amdgpu-annotate-uniform -S %s | FileCheck %s -check-prefix=UNIFORM
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; RUN: opt --amdgpu-annotate-uniform --si-annotate-control-flow -S %s | FileCheck %s -check-prefix=CONTROLFLOW
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; This module creates a divergent branch in block Flow2. The branch is
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; marked as divergent by the divergence analysis but the condition is
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; not. This test ensures that the divergence of the branch is tested,
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; not its condition, so that branch is correctly emitted as divergent.
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target triple = "amdgcn-mesa-mesa3d"
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define amdgpu_ps void @main(i32 %0, float %1) {
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start:
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%v0 = call float @llvm.amdgcn.interp.p1(float %1, i32 0, i32 0, i32 %0)
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br label %loop
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loop: ; preds = %Flow, %start
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%v1 = phi i32 [ 0, %start ], [ %6, %Flow ]
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%v2 = icmp ugt i32 %v1, 31
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%2 = xor i1 %v2, true
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br i1 %2, label %endif1, label %Flow
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Flow1: ; preds = %endif2, %endif1
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%3 = phi i32 [ %v5, %endif2 ], [ undef, %endif1 ]
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%4 = phi i1 [ false, %endif2 ], [ true, %endif1 ]
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br label %Flow
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; UNIFORM-LABEL: Flow2:
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; UNIFORM-NEXT: br i1 %8, label %if1, label %endloop
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; UNIFORM-NOT: !amdgpu.uniform
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; UNIFORM: if1:
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; CONTROLFLOW-LABEL: Flow2:
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; CONTROLFLOW-NEXT: call void @llvm.amdgcn.end.cf.i64(i64 %{{.*}})
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; CONTROLFLOW-NEXT: [[IF:%.*]] = call { i1, i64 } @llvm.amdgcn.if.i64(i1 %{{.*}})
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; CONTROLFLOW-NEXT: [[COND:%.*]] = extractvalue { i1, i64 } [[IF]], 0
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; CONTROLFLOW-NEXT: %{{.*}} = extractvalue { i1, i64 } [[IF]], 1
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; CONTROLFLOW-NEXT: br i1 [[COND]], label %if1, label %endloop
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Flow2: ; preds = %Flow
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br i1 %8, label %if1, label %endloop
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if1: ; preds = %Flow2
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%v3 = call float @llvm.sqrt.f32(float %v0)
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br label %endloop
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endif1: ; preds = %loop
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%v4 = fcmp ogt float %v0, 0.000000e+00
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%5 = xor i1 %v4, true
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br i1 %5, label %endif2, label %Flow1
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Flow: ; preds = %Flow1, %loop
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%6 = phi i32 [ %3, %Flow1 ], [ undef, %loop ]
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%7 = phi i1 [ %4, %Flow1 ], [ true, %loop ]
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%8 = phi i1 [ false, %Flow1 ], [ true, %loop ]
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br i1 %7, label %Flow2, label %loop
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endif2: ; preds = %endif1
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%v5 = add i32 %v1, 1
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br label %Flow1
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endloop: ; preds = %if1, %Flow2
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%v6 = phi float [ 0.000000e+00, %Flow2 ], [ %v3, %if1 ]
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call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %v6, float %v6, float %v6, float %v6, i1 true, i1 true)
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ret void
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}
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; Function Attrs: nounwind readnone speculatable willreturn
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declare float @llvm.sqrt.f32(float) #0
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; Function Attrs: nounwind readnone speculatable
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declare float @llvm.amdgcn.interp.p1(float, i32 immarg, i32 immarg, i32) #1
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; Function Attrs: inaccessiblememonly nounwind writeonly
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declare void @llvm.amdgcn.exp.f32(i32 immarg, i32 immarg, float, float, float, float, i1 immarg, i1 immarg) #2
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attributes #0 = { nounwind readnone speculatable willreturn }
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attributes #1 = { nounwind readnone speculatable }
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attributes #2 = { inaccessiblememonly nounwind writeonly }
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