Guozhi Wei 6599961c17 [TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation ... This patch contains following enhancements to SrcRegMap and DstRegMap: 1 In findOnlyInterestingUse not only check if the Reg is two address usage, but also check after commutation can it be two address usage. 2 If a physical register is clobbered, remove SrcRegMap entries that are mapped to it. 3 In processTiedPairs, when create a new COPY instruction, add a SrcRegMap entry only when the COPY instruction is coalescable. (The COPY src is killed) With these enhancements isProfitableToCommute can do better commute decision, and finally more register copies are removed. Differential Revision: https://reviews.llvm.org/D108731		2021-10-11 15:28:31 -07:00
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atomics	…
calling-conv/c	…
features	…
inline-asm	[AVR] Improve inline assembly	2021-05-30 23:44:43 +08:00
integration	…
intrinsics	[AVR] Only support sp, r0 and r1 in llvm.read_register	2021-07-24 14:03:27 +02:00
pseudo	[AVR] Fix lifeness issues in the AVR backend	2021-03-04 14:04:39 +01:00
relax-mem	[AVR] Fix def state of operands	2021-03-03 15:36:05 +01:00
PR31344.ll	…
PR31345.ll	…
PR37143.ll	…
add.ll	…
alloca.ll	…
and.ll	…
avr-rust-issue-123.ll	…
block-address-is-in-progmem-space.ll	Place the BlockAddress type in the address space of the containing function	2021-07-02 12:17:55 +01:00
branch-relaxation-long.ll	…
branch-relaxation.ll	…
brind.ll	Place the BlockAddress type in the address space of the containing function	2021-07-02 12:17:55 +01:00
call.ll	[AVR] Do not chain stores in call frame setup	2021-07-24 14:03:26 +02:00
clear-bss.ll	…
cmp.ll	[AVR] Optimize 16-bit comparison with constant	2021-01-24 00:38:57 +08:00
com.ll	[update_llc_test_checks] Support AVR	2021-01-26 17:50:56 +08:00
copy-data-to-ram.ll	…
ctlz.ll	[AVR] Optimize 8-bit logic left/right shifts	2021-01-23 23:54:16 +08:00
ctors.ll	[AVR] emit 'MCSA_Global' references to '__do_global_ctors' and '__do_global_dtors'	2021-08-05 10:37:36 +08:00
ctpop.ll	[TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation	2021-10-11 15:28:31 -07:00
cttz.ll	[AVR] Optimize 8-bit logic left/right shifts	2021-01-23 23:54:16 +08:00
directmem.ll	…
div.ll	…
dynalloca.ll	[AVR] Do not chain stores in call frame setup	2021-07-24 14:03:26 +02:00
eor.ll	…
expand-integer-failure.ll	…
frame.ll	…
frmidx-iterator-bug.ll	…
hardware-mul.ll	[TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation	2021-10-11 15:28:31 -07:00
high-pressure-on-ptrregs.ll	…
icall-func-pointer-correct-addr-space.ll	…
impossible-reg-to-reg-copy.ll	…
interrupts.ll	[AVR] Fix a bug in prologue of ISR	2021-06-29 21:44:50 +08:00
io.ll	…
issue-cannot-select-bswap.ll	…
issue-regalloc-stackframe-folding-earlyclobber.ll	…
jmp-long.ll	…
large-return-size.ll	…
lit.local.cfg	…
load.ll	…
lower-formal-args-struct-return.ll	…
lower-formal-arguments-assertion.ll	…
neg.ll	[AVR] Fix expansion of NEGW	2021-03-03 15:36:05 +01:00
no-print-operand-twice.ll	…
or.ll	…
pre-schedule.ll	…
progmem-extended.ll	…
progmem.ll	…
rem.ll	…
return.ll	…
rot.ll	[AVR] Fix rotate instructions	2021-07-24 14:03:26 +02:00
runtime-trig.ll	…
rust-avr-bug-37.ll	…
rust-avr-bug-95.ll	…
rust-avr-bug-99.ll	…
rust-avr-bug-112.ll	…
rust-trait-object.ll	[AVR] Fix global references to function symbols	2021-02-10 00:40:49 +13:00
sections.ll	…
select-must-add-unconditional-jump.ll	…
sext.ll	…
shift-expand.ll	[AVR] Expand large shifts early in IR	2021-07-24 14:03:26 +02:00
shift.ll	[AVR] Fix a bug in 16-bit shifts	2021-02-14 11:54:55 +08:00
sign-extension.ll	…
smul-with-overflow.ll	[AVR] Optimize 8-bit int shift	2021-01-24 11:04:37 +08:00
software-mul.ll	…
std-ldd-immediate-overflow.ll	…
store-undef.ll	…
store.ll	…
struct.ll	[AVR][test] Add a new test: functions with struct return type	2021-06-28 21:19:26 +08:00
sub.ll	…
trunc.ll	…
umul-with-overflow.ll	…
umul.with.overflow.i16-bug.ll	…
unaligned-atomic-loads.ll	…
varargs.ll	[AVR] Do not chain stores in call frame setup	2021-07-24 14:03:26 +02:00
xor.ll	…
zext.ll	…