Sanjay Patel bf5748a1af [x86] fold vector (X > -1) & Y to shift+andn ... and (pcmpgt X, -1), Y --> pandn (vsrai X, BitWidth-1), Y This avoids the -1 constant vector in favor of an arithmetic shift instruction if it exists (the ISA is still not complete after all these years...). We catch this pattern late in combining by matching PCMPGT, so it should not interfere with more general folds. Differential Revision: https://reviews.llvm.org/D113603		2021-11-12 08:17:46 -05:00
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AArch64	[DAGCombiner] add fold for vselect based on mask of signbit, part 3	2021-11-11 10:27:37 -05:00
AMDGPU	[AMDGPU] Regenerate some div/rem test checks	2021-11-11 15:26:22 +00:00
ARC	…
ARM	[ARM] implement support for TLS register based stack protector	2021-11-09 18:19:47 +01:00
AVR	[TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation	2021-10-11 15:28:31 -07:00
BPF	BPF: change btf_type_tag BTF output format	2021-11-09 11:34:25 -08:00
CSKY	[CSKY] First patch to construct codegen infra and generate first add instruction	2021-11-01 10:06:56 +08:00
Generic	[AIX] XFAIL 2009-03-29-SoftFloatVectorExtract.ll because of no soft float support	2021-11-10 20:58:26 -05:00
Hexagon	[LiveIntervals] Update subranges in processTiedPairs	2021-11-11 12:24:59 +00:00
Inputs	…
Lanai	…
M68k	…
MIR	[X86] Update RET/LRET instruction to use the same naming convention as IRET (PR36876). NFC	2021-11-07 15:06:54 +00:00
MSP430	[llvm-readobj] Support dumping of MSP430 ELF attributes	2021-09-28 00:56:11 +03:00
Mips	[SelectionDAG] Optimize expansion for rotates/funnel shifts	2021-11-02 11:38:25 +00:00
NVPTX	[NVPTX] Add imm variants for surface and texture instructions	2021-11-10 19:05:03 +03:00
PowerPC	[PowerPC] PPC backend optimization to lower int_ppc_tdw/int_ppc_tw intrinsics to TDI/TWI machine instructions	2021-11-11 09:52:00 -06:00
RISCV	Fix minor deficiency in machine-sink.	2021-11-12 08:01:13 +01:00
SPARC	[SparcISelLowering] avoid emitting libcalls to __muloti4 and __mulodi4	2021-10-29 13:14:09 -07:00
SystemZ	[SystemZ] Improvement of emitMemMemWrapper()	2021-10-26 17:03:01 +02:00
Thumb	[TwoAddressInstructionPass] Update existing physreg live intervals	2021-11-05 21:20:30 +00:00
Thumb2	[DAG] reassociateOpsCommutative - peek through bitcasts to find constants	2021-11-11 12:00:22 +00:00
VE	[VE][NFC] correct bitmasking in popcnt expansion test	2021-10-25 13:55:58 +02:00
WebAssembly	[WebAssembly] Add prototype relaxed float to int trunc instructions	2021-10-28 14:01:53 -07:00
WinCFGuard	…
WinEH	…
X86	[x86] fold vector (X > -1) & Y to shift+andn	2021-11-12 08:17:46 -05:00
XCore	…