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Sanjay Patel bf5748a1af [x86] fold vector (X > -1) & Y to shift+andn 
and (pcmpgt X, -1), Y --> pandn (vsrai X, BitWidth-1), Y

This avoids the -1 constant vector in favor of an arithmetic shift
instruction if it exists (the ISA is still not complete after all
these years...).

We catch this pattern late in combining by matching PCMPGT, so it
should not interfere with more general folds.

Differential Revision: https://reviews.llvm.org/D113603
 		2021-11-12 08:17:46 -05:00
..
AMX [X86] [AMX] Replace bitcast with specific AMX intrinsics with X86 specific cast. 2021-08-17 17:04:26 +08:00
GC
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GlobalISel Delay outgoing register assignments to last. 2021-10-04 12:33:20 -07:00
Inputs [SampleFDO] Flow Sensitive Sample FDO (FSAFDO) profile loader 2021-08-18 18:37:35 -07:00
avx512-shuffles Revert "[X86] combineX86ShuffleChain(): canonicalize mask elts picking from splats" 2021-08-05 18:58:08 +02:00
3addr-16bit.ll
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3addr-or.ll
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3dnow-intrinsics.ll
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4char-promote.ll
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8bit_cmov_of_trunc_promotion.ll
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64-bit-shift-by-32-minus-y.ll RegAllocGreedy: Account for reserved registers in num regs heuristic 2021-09-14 21:00:29 -04:00
2003-08-03-CallArgLiveRanges.ll
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2003-08-23-DeadBlockTest.ll
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2003-11-03-GlobalBool.ll
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2004-02-13-FrameReturnAddress.ll
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2004-02-14-InefficientStackPointer.ll
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2004-02-22-Casts.ll
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2004-03-30-Select-Max.ll
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2004-04-13-FPCMOV-Crash.ll
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2004-06-10-StackifierCrash.ll
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2004-10-08-SelectSetCCFold.ll
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2005-01-17-CycleInDAG.ll
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2005-02-14-IllegalAssembler.ll
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2005-05-08-FPStackifierPHI.ll
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2006-01-19-ISelFoldingBug.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
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2006-03-02-InstrSchedBug.ll
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2006-04-04-CrossBlockCrash.ll
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2006-04-27-ISelFoldingBug.ll
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2006-05-01-SchedCausingSpills.ll
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2006-05-02-InstrSched1.ll
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2006-05-02-InstrSched2.ll
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2006-05-08-CoalesceSubRegClass.ll
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2006-05-11-InstrSched.ll
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2006-05-17-VectorArg.ll
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2006-05-22-FPSetEQ.ll
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2006-05-25-CycleInDAG.ll
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2006-07-10-InlineAsmAConstraint.ll
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2006-07-12-InlineAsmQConstraint.ll
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2006-07-20-InlineAsm.ll
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2006-07-28-AsmPrint-Long-As-Pointer.ll
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2006-07-31-SingleRegClass.ll
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2006-08-07-CycleInDAG.ll
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2006-08-16-CycleInDAG.ll
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2006-08-21-ExtraMovInst.ll
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2006-09-01-CycleInDAG.ll
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2006-10-02-BoolRetCrash.ll
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2006-10-09-CycleInDAG.ll
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2006-10-10-FindModifiedNodeSlotBug.ll
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2006-10-12-CycleInDAG.ll
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2006-10-13-CycleInDAG.ll
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2006-10-19-SwitchUnnecessaryBranching.ll
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2006-11-12-CSRetCC.ll
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2006-11-17-IllegalMove.ll
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2006-11-27-SelectLegalize.ll
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2006-12-16-InlineAsmCrash.ll
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2006-12-19-IntelSyntax.ll
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2007-01-08-InstrSched.ll
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2007-01-08-X86-64-Pointer.ll
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2007-01-13-StackPtrIndex.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
2007-01-29-InlineAsm-ir.ll
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2007-02-04-OrAddrMode.ll
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2007-02-16-BranchFold.ll X86InstrInfo: Optimize more combinations of SUB+CMP 2021-10-28 10:33:56 -07:00
2007-02-19-LiveIntervalAssert.ll
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2007-02-23-DAGCombine-Miscompile.ll
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2007-02-25-FastCCStack.ll
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2007-03-01-SpillerCrash.ll
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2007-03-15-GEP-Idx-Sink.ll
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2007-03-16-InlineAsm.ll
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2007-03-18-LiveIntervalAssert.ll
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2007-03-24-InlineAsmMultiRegConstraint.ll
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2007-03-24-InlineAsmPModifier.ll
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2007-03-24-InlineAsmVectorOp.ll
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2007-03-24-InlineAsmXConstraint.ll
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2007-03-26-CoalescerBug.ll
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2007-04-08-InlineAsmCrash.ll
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2007-04-11-InlineAsmVectorResult.ll
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2007-04-17-LiveIntervalAssert.ll
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2007-04-24-Huge-Stack.ll
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2007-04-24-VectorCrash.ll
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2007-04-27-InlineAsm-IntMemInput.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
2007-05-05-Personality.ll
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2007-05-05-VecCastExpand.ll
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2007-05-14-LiveIntervalAssert.ll
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2007-05-15-maskmovq.ll
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2007-05-17-ShuffleISelBug.ll
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2007-06-04-X86-64-CtorAsmBugs.ll
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2007-06-28-X86-64-isel.ll
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2007-06-29-DAGCombinerBug.ll
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2007-06-29-VecFPConstantCSEBug.ll
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2007-07-03-GR64ToVR64.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
2007-07-10-StackerAssert.ll
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2007-07-18-Vector-Extract.ll
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2007-08-01-LiveVariablesBug.ll
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2007-08-09-IllegalX86-64Asm.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
2007-08-10-SignExtSubreg.ll
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2007-09-05-InvalidAsm.ll
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2007-09-06-ExtWeakAliasee.ll
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2007-09-27-LDIntrinsics.ll Update @llvm.powi to handle different int sizes for the exponent 2021-06-17 09:38:28 +02:00
2007-10-04-AvoidEFLAGSCopy.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
2007-10-12-CoalesceExtSubReg.ll
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2007-10-12-SpillerUnfold1.ll RegAllocGreedy: Account for reserved registers in num regs heuristic 2021-09-14 21:00:29 -04:00
2007-10-12-SpillerUnfold2.ll
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2007-10-15-CoalescerCrash.ll
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2007-10-19-SpillerUnfold.ll
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2007-10-28-inlineasm-q-modifier.ll
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2007-10-29-ExtendSetCC.ll
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2007-10-30-LSRCrash.ll
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2007-10-31-extractelement-i64.ll
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2007-11-01-ISelCrash.ll
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2007-11-03-x86-64-q-constraint.ll
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2007-11-04-LiveIntervalCrash.ll
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2007-11-04-LiveVariablesBug.ll
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2007-11-04-rip-immediate-constant.ll
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2007-11-06-InstrSched.ll
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2007-11-07-MulBy4.ll
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2007-11-30-LoadFolding-Bug.ll
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2007-12-16-BURRSchedCrash.ll
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2007-12-18-LoadCSEBug.ll
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2008-01-08-IllegalCMP.ll
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2008-01-08-SchedulerCrash.ll
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2008-01-09-LongDoubleSin.ll
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2008-01-16-FPStackifierAssert.ll
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2008-02-06-LoadFoldingBug.ll
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2008-02-14-BitMiscompile.ll
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2008-02-18-TailMergingBug.ll
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2008-02-20-InlineAsmClobber.ll
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2008-02-22-LocalRegAllocBug.ll
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2008-02-25-InlineAsmBug.ll
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2008-02-25-X86-64-CoalescerBug.ll
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2008-02-26-AsmDirectMemOp.ll
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2008-02-27-DeadSlotElimBug.ll
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2008-02-27-PEICrash.ll
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2008-03-06-frem-fpstack.ll
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2008-03-07-APIntBug.ll
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2008-03-10-RegAllocInfLoop.ll
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2008-03-12-ThreadLocalAlias.ll
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2008-03-13-TwoAddrPassCrash.ll
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2008-03-14-SpillerCrash.ll
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2008-03-19-DAGCombinerBug.ll
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2008-03-23-DarwinAsmComments.ll
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2008-03-25-TwoAddrPassBug.ll
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2008-03-31-SpillerFoldingBug.ll
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2008-04-02-unnamedEH.ll
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2008-04-08-CoalescerCrash.ll
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2008-04-09-BranchFolding.ll
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2008-04-15-LiveVariableBug.ll
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2008-04-16-CoalescerBug.ll
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2008-04-16-ReMatBug.ll RegAllocGreedy: Account for reserved registers in num regs heuristic 2021-09-14 21:00:29 -04:00
2008-04-17-CoalescerBug.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
2008-04-24-MemCpyBug.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
2008-04-24-pblendw-fold-crash.ll
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2008-04-26-Asm-Optimize-Imm.ll
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2008-04-28-CoalescerBug.ll
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2008-04-28-CyclicSchedUnit.ll
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2008-05-01-InvalidOrdCompare.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
2008-05-09-PHIElimBug.ll
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2008-05-09-ShuffleLoweringBug.ll
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2008-05-12-tailmerge-5.ll
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2008-05-21-CoalescerBug.ll
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2008-05-22-FoldUnalignedLoad.ll
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2008-05-28-CoalescerBug.ll
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2008-05-28-LocalRegAllocBug.ll
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2008-06-13-NotVolatileLoadStore.ll
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2008-06-13-VolatileLoadStore.ll
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2008-06-16-SubregsBug.ll
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2008-06-25-VecISelBug.ll
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2008-07-07-DanglingDeadInsts.ll
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2008-07-09-ELFSectionAttributes.ll
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2008-07-11-SHLBy1.ll
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2008-07-16-CoalescerCrash.ll
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2008-07-19-movups-spills.ll
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2008-07-22-CombinerCrash.ll
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2008-07-23-VSetCC.ll
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2008-08-06-CmpStride.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
2008-08-06-RewriterBug.ll
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2008-08-17-UComiCodeGenBug.ll
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2008-08-23-64Bit-maskmovq.ll
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2008-08-31-EH_RETURN32.ll
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2008-08-31-EH_RETURN64.ll
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2008-09-05-sinttofp-2xi32.ll
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2008-09-09-LinearScanBug.ll
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2008-09-11-CoalescerBug.ll
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2008-09-11-CoalescerBug2.ll [X86] Canonicalize SGT/UGT compares with constants to use SGE/UGE to reduce the number of EFLAGs reads. (PR48760) 2021-06-30 18:46:50 +01:00
2008-09-17-inline-asm-1.ll
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2008-09-18-inline-asm-2.ll
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2008-09-19-RegAllocBug.ll
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2008-09-25-sseregparm-1.ll
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2008-09-26-FrameAddrBug.ll
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2008-09-29-ReMatBug.ll
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2008-09-29-VolatileBug.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
2008-10-06-x87ld-nan-1.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
2008-10-06-x87ld-nan-2.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
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2008-10-11-CallCrash.ll
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2008-10-13-CoalescerBug.ll
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2008-10-16-VecUnaryOp.ll
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2008-10-17-Asm64bitRConstraint.ll
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2008-10-20-AsmDoubleInI32.ll
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2008-10-24-FlippedCompare.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
2008-10-27-CoalescerBug.ll
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2008-10-29-ExpandVAARG.ll
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2008-11-03-F80VAARG.ll
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2008-11-06-testb.ll
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2008-11-29-ULT-Sign.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
2008-12-01-SpillerAssert.ll
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2008-12-01-loop-iv-used-outside-loop.ll
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2008-12-02-IllegalResultType.ll
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2008-12-02-dagcombine-1.ll
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2008-12-02-dagcombine-2.ll
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2008-12-02-dagcombine-3.ll
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2008-12-16-dagcombine-4.ll
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2008-12-19-EarlyClobberBug.ll
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2008-12-23-crazy-address.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
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2009-01-13-DoubleUpdate.ll
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2009-01-16-SchedulerBug.ll
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2009-01-18-ConstantExprCrash.ll
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2009-01-25-NoSSE.ll
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2009-01-26-WrongCheck.ll
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2009-01-27-NullStrings.ll
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2009-01-31-BigShift.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
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2009-01-31-BigShift3.ll
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2009-02-01-LargeMask.ll
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2009-02-03-AnalyzedTwice.ll
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2009-02-04-sext-i64-gep.ll
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2009-02-08-CoalescerBug.ll
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2009-02-09-ivs-different-sizes.ll
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2009-02-11-codegenprepare-reuse.ll
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2009-02-12-DebugInfoVLA.ll
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2009-02-12-InlineAsm-nieZ-constraints.ll
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2009-02-21-ExtWeakInitializer.ll
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2009-02-25-CommuteBug.ll
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2009-02-26-MachineLICMBug.ll
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2009-03-03-BTHang.ll
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2009-03-03-BitcastLongDouble.ll
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2009-03-05-burr-list-crash.ll
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2009-03-09-APIntCrash.ll
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2009-03-16-PHIElimInLPad.ll
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2009-03-23-LinearScanBug.ll
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2009-03-23-MultiUseSched.ll [X86FixupLEAs] Try again to transform the sequence LEA/SUB to SUB/SUB 2021-07-16 10:16:03 -07:00
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2009-03-26-NoImplicitFPBug.ll
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2009-04-12-FastIselOverflowCrash.ll
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2009-04-12-picrel.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
2009-04-13-2AddrAssert-2.ll
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2009-04-13-2AddrAssert.ll
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2009-04-14-IllegalRegs.ll
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2009-04-16-SpillerUnfold.ll
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2009-04-24.ll
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2009-04-25-CoalescerBug.ll
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2009-04-27-CoalescerAssert.ll
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2009-04-27-LiveIntervalsAssert.ll
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2009-04-27-LiveIntervalsAssert2.ll
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2009-04-29-IndirectDestOperands.ll
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2009-04-29-LinearScanBug.ll
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2009-04-29-RegAllocAssert.ll
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2009-04-scale.ll
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2009-05-08-InlineAsmIOffset.ll
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2009-05-11-tailmerge-crash.ll
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2009-05-19-SingleElementExtractElement.ll
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2009-05-23-available_externally.ll
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2009-05-23-dagcombine-shifts.ll
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2009-05-28-DAGCombineCrash.ll
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2009-05-30-ISelBug.ll
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2009-06-02-RewriterBug.ll
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2009-06-03-Win64DisableRedZone.ll
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2009-06-03-Win64SpillXMM.ll
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2009-06-04-VirtualLiveIn.ll
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2009-06-06-ConcatVectors.ll
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2009-06-12-x86_64-tail-call-conv-out-of-sync-bug.ll
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2009-06-15-not-a-tail-call.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
2009-06-18-movlp-shuffle-register.ll
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2009-07-06-TwoAddrAssert.ll
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2009-07-07-SplitICmp.ll
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2009-07-09-ExtractBoolFromVector.ll
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2009-07-15-CoalescerBug.ll
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2009-07-16-CoalescerBug.ll
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2009-07-19-AsmExtraOperands.ll
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2009-07-20-CoalescerBug.ll
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2009-07-20-DAGCombineBug.ll
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2009-08-06-branchfolder-crash.ll
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2009-08-06-inlineasm.ll
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2009-08-08-CastError.ll
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2009-08-12-badswitch.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
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2009-08-23-SubRegReuseUndo.ll
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2009-09-10-LoadFoldingBug.ll
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2009-09-10-SpillComments.ll
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2009-09-19-earlyclobber.ll
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2009-09-21-NoSpillLoopCount.ll
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2009-09-22-CoalescerBug.ll
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2009-09-23-LiveVariablesBug.ll
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2009-10-14-LiveVariablesBug.ll
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2009-10-16-Scope.ll
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2009-10-19-EmergencySpill.ll
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2009-10-19-atomic-cmp-eflags.ll
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2009-10-25-RewriterBug.ll
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2009-11-04-SubregCoalescingBug.ll
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2009-11-13-VirtRegRewriterBug.ll
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2009-11-16-MachineLICM.ll
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2009-11-16-UnfoldMemOpBug.ll
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2009-11-17-UpdateTerminator.ll
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2009-11-18-TwoAddrKill.ll
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2009-11-25-ImpDefBug.ll
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2009-12-01-EarlyClobberBug.ll
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2009-12-11-TLSNoRedZone.ll
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2010-03-17-ISelBug.ll
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2010-04-21-CoalescerBug.ll
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2010-04-29-CoalescerCrash.ll
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2010-04-30-LocalAlloc-LandingPad.ll
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2010-05-03-CoalescerSubRegClobber.ll
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2010-05-05-LocalAllocEarlyClobber.ll
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2010-05-06-LocalInlineAsmClobber.ll
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2010-05-07-ldconvert.ll Update @llvm.powi to handle different int sizes for the exponent 2021-06-17 09:38:28 +02:00
2010-05-10-DAGCombinerBug.ll
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2010-05-12-FastAllocKills.ll
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2010-05-16-nosseconversion.ll
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2010-05-25-DotDebugLoc.ll
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2010-05-26-DotDebugLoc.ll
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2010-05-28-Crash.ll
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2010-06-01-DeadArg-DbgInfo.ll
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2010-06-09-FastAllocRegisters.ll
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2010-06-14-fast-isel-fs-load.ll
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2010-06-15-FastAllocEarlyCLobber.ll
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2010-06-24-g-constraint-crash.ll
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2010-06-25-CoalescerSubRegDefDead.ll
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2010-06-25-asm-RA-crash.ll
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2010-06-28-FastAllocTiedOperand.ll
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2010-06-28-matched-g-constraint.ll
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2010-07-02-UnfoldBug.ll
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2010-07-02-asm-alignstack.ll
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2010-07-06-asm-RIP.ll
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2010-07-11-FPStackLoneUse.ll
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2010-07-13-indirectXconstraint.ll
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2010-07-15-Crash.ll
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2010-07-29-SetccSimplify.ll
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2010-08-04-MaskedSignedCompare.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
2010-08-04-MingWCrash.ll
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2010-09-01-RemoveCopyByCommutingDef.ll
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2010-09-17-SideEffectsInChain.ll
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2010-09-30-CMOV-JumpTable-PHI.ll
…
2010-10-08-cmpxchg8b.ll
…
2010-11-02-DbgParameter.ll
…
2010-11-09-MOVLPS.ll
…
2010-11-18-SelectOfExtload.ll
…
2011-01-07-LegalizeTypesCrash.ll
…
2011-01-10-DagCombineHang.ll
…
2011-01-24-DbgValue-Before-Use.ll
…
2011-02-04-FastRegallocNoFP.ll
…
2011-02-12-shuffle.ll
…
2011-02-21-VirtRegRewriter-KillSubReg.ll
…
2011-02-23-UnfoldBug.ll
…
2011-02-27-Fpextend.ll
…
2011-03-02-DAGCombiner.ll
…
2011-03-08-Sched-crash.ll
…
2011-03-09-Physreg-Coalescing.ll
…
2011-03-30-CreateFixedObjCrash.ll
…
2011-04-13-SchedCmpJmp.ll
…
2011-04-19-sclr-bb.ll
…
2011-05-09-loaduse.ll
…
2011-05-26-UnreachableBlockElim.ll
…
2011-05-27-CrossClassCoalescing.ll
…
2011-06-01-fildll.ll
…
2011-06-03-x87chain.ll
…
2011-06-06-fgetsign80bit.ll
…
2011-06-12-FastAllocSpill.ll
…
2011-06-14-PreschedRegalias.ll
…
2011-06-14-mmx-inlineasm.ll
…
2011-06-19-QuicksortCoalescerBug.ll
…
2011-07-13-BadFrameIndexDisplacement.ll
…
2011-08-23-PerformSubCombine128.ll
…
2011-08-23-Trampoline.ll
…
2011-08-29-BlockConstant.ll
…
2011-08-29-InitOrder.ll [static initializers] Emit global_ctors and global_dtors in reverse order when .ctors/.dtors are used. 2021-06-10 16:44:47 -07:00
2011-09-14-valcoalesce.ll
…
2011-09-18-sse2cmp.ll
…
2011-09-21-setcc-bug.ll
…
2011-10-11-SpillDead.ll
…
2011-10-11-srl.ll
…
2011-10-12-MachineCSE.ll
…
2011-10-18-FastISel-VectorParams.ll
…
2011-10-19-LegelizeLoad.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
2011-10-19-widen_vselect.ll
…
2011-10-21-widen-cmp.ll
…
2011-10-27-tstore.ll
…
2011-10-30-padd.ll
…
2011-11-07-LegalizeBuildVector.ll
…
2011-11-22-AVX2-Domains.ll
…
2011-11-30-or.ll
…
2011-12-06-AVXVectorExtractCombine.ll
…
2011-12-06-BitcastVectorGlobal.ll
…
2011-12-08-AVXISelBugs.ll
…
2011-12-8-bitcastintprom.ll
…
2011-12-15-vec_shift.ll
…
2011-12-26-extractelement-duplicate-load.ll
…
2011-12-28-vselecti8.ll
…
2011-20-21-zext-ui2fp.ll
…
2012-01-10-UndefExceptionEdge.ll
…
2012-1-10-buildvector.ll
…
2012-01-11-split-cv.ll
…
2012-01-12-extract-sv.ll
…
2012-01-16-mfence-nosse-flags.ll
…
2012-01-18-vbitcast.ll
…
2012-02-12-dagco.ll
…
2012-02-14-scalar.ll
…
2012-02-23-mmx-inlineasm.ll
…
2012-02-29-CoalescerBug.ll
…
2012-03-15-build_vector_wl.ll
…
2012-03-20-LargeConstantExpr.ll
…
2012-03-26-PostRALICMBug.ll
…
2012-04-09-TwoAddrPassBug.ll
…
2012-04-26-sdglue.ll [DAG] DAGCombiner::visitVECTOR_SHUFFLE - recognise INSERT_SUBVECTOR patterns 2021-08-05 15:40:48 +01:00
2012-05-17-TwoAddressBug.ll
…
2012-05-19-CoalescerCrash.ll
…
2012-07-10-extload64.ll
…
2012-07-10-shufnorm.ll
…
2012-07-15-BuildVectorPromote.ll
…
2012-07-15-broadcastfold.ll
…
2012-07-15-tconst_shl.ll
…
2012-07-15-vshl.ll
…
2012-07-16-LeaUndef.ll
…
2012-07-16-fp2ui-i1.ll
…
2012-07-17-vtrunc.ll
…
2012-07-23-select_cc.ll
…
2012-08-07-CmpISelBug.ll
…
2012-08-16-setcc.ll [X86] Fold cmpeq/ne(trunc(logic(x)),0) --> cmpeq/ne(logic(x),0) 2021-04-12 16:05:34 +01:00
2012-08-17-legalizer-crash.ll
…
2012-08-28-UnsafeMathCrash.ll
…
2012-09-13-dagco-fneg.ll
…
2012-09-28-CGPBug.ll
…
2012-10-02-DAGCycle.ll
…
2012-10-03-DAGCycle.ll
…
2012-10-18-crash-dagco.ll
…
2012-11-28-merge-store-alias.ll
…
2012-12-1-merge-multiple.ll
…
2012-12-12-DAGCombineCrash.ll
…
2012-12-14-v8fp80-crash.ll
…
2012-12-19-NoImplicitFloat.ll
…
2013-01-09-DAGCombineBug.ll
…
2013-03-13-VEX-DestReg.ll Revert "[NFC] remove explicit default value for strboolattr attribute in tests" 2021-05-24 19:43:40 +02:00
2013-05-06-ConactVectorCrash.ll
…
2013-10-14-FastISel-incorrect-vreg.ll
…
2014-05-29-factorial.ll
…
2014-08-29-CompactUnwind.ll
…
2020_12_02_decrementing_loop.ll
…
9601.ll
…
20090313-signext.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
20210831-inlineasm.ll [SelectionDAGBuilder] Bugfix in visitInlineAsm() 2021-09-06 17:46:31 +02:00
AppendingLinkage.ll
…
Atomics-64.ll
…
DbgValueOtherTargets.test
…
DynamicCalleeSavedRegisters.ll [TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation 2021-10-11 15:28:31 -07:00
MachineBranchProb.ll
…
MachineSink-CritEdge.ll
…
MachineSink-DbgValue.ll
…
MachineSink-PHIUse.ll
…
MachineSink-SubReg.ll
…
MachineSink-eflags.ll
…
MergeConsecutiveStores.ll
…
O0-pipeline.ll [CSSPGO] Set PseudoProbeInserter as a default pass. 2021-09-22 09:09:48 -07:00
PR34565.ll
…
PR37310.mir
…
PR40322.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
StackColoring-dbg-invariance.mir [StackColoring] Fix a debug invariance problem 2021-09-14 19:21:56 +02:00
StackColoring-dbg.ll
…
StackColoring-use-between-allocas.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
StackColoring.ll
…
SwitchLowering.ll [ISEL][BitTestBlock] omit additional bit test when default destination is unreachable 2021-09-08 11:03:47 -07:00
SwizzleShuff.ll
…
TruncAssertSext.ll
…
TruncAssertZext.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
WidenArith.ll [UpdateTestChecks] Default --x86_scrub_rip to False 2021-05-21 19:26:15 -07:00
abi-isel.ll [UpdateTestChecks] Default --x86_scrub_rip to False 2021-05-21 19:26:15 -07:00
abs.ll [X86] Use CMOVNS for abs instead of CMOVGE. 2021-10-14 12:28:28 -07:00
absolute-bit-mask-fastisel.ll
…
absolute-bit-mask.ll
…
absolute-bt.ll
…
absolute-cmp.ll
…
absolute-constant.ll
…
absolute-rotate.ll
…
add-cmov.ll [TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation 2021-10-11 15:28:31 -07:00
add-ext.ll
…
add-i64.ll
…
add-of-carry.ll
…
add-sub-nsw-nuw.ll
…
add.ll
…
add32ri8.ll
…
add_shl_constant.ll
…
addcarry.ll [TwoAddressInstructionPass] Put all new instructions into DistanceMap 2021-10-28 11:11:59 -07:00
addcarry2.ll
…
addr-label-difference.ll
…
addr-mode-matcher-2.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
addr-mode-matcher.ll
…
addr-of-ret-addr.ll
…
address-type-promotion-constantexpr.ll
…
addrsig.ll [Verifier] Add verification logic for GlobalIFuncs 2021-10-31 20:00:57 -07:00
addsub-constant-folding.ll [TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation 2021-10-11 15:28:31 -07:00
adx-commute.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
adx-intrinsics-upgrade.ll
…
adx-intrinsics.ll
…
aes_intrinsics.ll
…
alias-gep.ll
…
alias-static-alloca.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
aliases.ll
…
align-branch-boundary-default.ll
…
align-branch-boundary-noautopadding.ll
…
align-branch-boundary-suppressions-tls.ll
…
align-branch-boundary-suppressions.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
align-down-const.ll
…
align-down.ll [TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation 2021-10-11 15:28:31 -07:00
aligned-comm.ll
…
aligned-variadic.ll
…
alignment-2.ll
…
alignment.ll
…
all-ones-vector.ll
…
alldiv-divdi3.ll
…
alloca-align-rounding-32.ll
…
alloca-align-rounding.ll
…
alloca-overaligned.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
allrem-moddi3.ll
…
and-encoding.ll
…
and-load-fold.ll
…
and-or-fold.ll
…
and-sink.ll
…
and-su.ll
…
and-with-overflow.ll [X86] combineCMP - fold cmpEQ/NE(TRUNC(X),0) -> cmpEQ/NE(X,0) 2021-04-15 13:55:51 +01:00
andimm8.ll
…
anyext.ll
…
anyregcc-crash.ll
…
anyregcc.ll
…
apm.ll
…
arg-cast.ll
…
arg-copy-elide-win64.ll
…
arg-copy-elide.ll [SelectionDAG] Fix argument copy elision with irregular types 2021-05-22 09:43:37 +02:00
arg_returned_bitcast.ll
…
arithmetic_fence.ll [ISel] Legalized arithmetic.fence.f128 for 32-bits target 2021-09-28 10:27:25 +08:00
arithmetic_fence2.ll [TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation 2021-10-11 15:28:31 -07:00
asan-check-memaccess-add.ll [asan] Fixed a bug causing a crash when redzone optimization kicked in on X86 with -asan-optimize-callbacks flag on. 2021-09-21 22:26:03 +00:00
asan-check-memaccess-or.ll [asan] Fixed a bug causing a crash when redzone optimization kicked in on X86 with -asan-optimize-callbacks flag on. 2021-09-21 22:26:03 +00:00
asm-block-labels.ll
…
asm-global-imm.ll
…
asm-indirect-mem.ll
…
asm-invalid-register-class-crasher.ll
…
asm-label.ll
…
asm-label2.ll
…
asm-mismatched-types.ll
…
asm-modifier-P.ll
…
asm-modifier.ll
…
asm-modifier2.ll
…
asm-reg-type-mismatch-avx512.ll
…
asm-reg-type-mismatch.ll
…
asm-reject-reg-type-mismatch.ll
…
asm-reject-rex.ll
…
asm-reject-vk32-vk64.ll
…
asm-reject-x87-int.ll
…
asm-reject-xmm16.ll
…
atom-call-reg-indirect-foldedreload32.ll
…
atom-call-reg-indirect-foldedreload64.ll
…
atom-call-reg-indirect.ll
…
atom-cmpb.ll
…
atom-fixup-lea1.ll
…
atom-fixup-lea2.ll
…
atom-fixup-lea3.ll
…
atom-fixup-lea4.ll Revert "[NFC] remove explicit default value for strboolattr attribute in tests" 2021-05-24 19:43:40 +02:00
atom-lea-addw-bug.ll
…
atom-lea-sp.ll
…
atom-pad-short-functions.ll
…
atom-sched.ll
…
atom-shuf.ll
…
atomic-add.ll
…
atomic-dagsched.ll
…
atomic-eflags-reuse.ll [X86] Canonicalize SGT/UGT compares with constants to use SGE/UGE to reduce the number of EFLAGs reads. (PR48760) 2021-06-30 18:46:50 +01:00
atomic-flags.ll [X86] Update PR20841 test description to make it clear we SHOULDN'T be folding EFLAGS with XADD 2021-05-04 13:29:19 +01:00
atomic-fp.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
atomic-idempotent.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
atomic-load-store-wide.ll
…
atomic-load-store.ll
…
atomic-mi.ll
…
atomic-minmax-i6432.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
atomic-monotonic.ll
…
atomic-non-integer-fp128.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
atomic-non-integer.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
atomic-op.ll
…
atomic-ops-ancient-64.ll
…
atomic-or.ll
…
atomic-pointer.ll
…
atomic-unordered.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
atomic8.ll
…
atomic16.ll
…
atomic32.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
atomic64.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
atomic128.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
atomic6432.ll
…
atomicf128.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
attr-dontcall.ll Reland [clang] Rework dontcall attributes 2021-09-28 15:31:30 -07:00
attribute-sections.ll
…
avg-mask.ll
…
avg.ll [X86][SSE] Add X86ISD::AVG to isCommutativeBinOp to support folding shuffles through the binop 2021-10-13 10:54:37 +01:00
avoid-lea-scale2.ll
…
avoid-loop-align-2.ll
…
avoid-loop-align.ll
…
avoid-sfb-g-no-change.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
avoid-sfb-g-no-change2.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
avoid-sfb-g-no-change3.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
avoid-sfb-kill-flags.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
avoid-sfb-offset.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
avoid-sfb-overlaps.ll Revert "[NFC] remove explicit default value for strboolattr attribute in tests" 2021-05-24 19:43:40 +02:00
avoid-sfb.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
avoid_complex_am.ll
…
avx-arith.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
avx-basic.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
avx-bitcast.ll
…
avx-brcond.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
avx-cast.ll
…
avx-cmp.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
avx-cvt-2.ll
…
avx-cvt-3.ll
…
avx-cvt.ll
…
avx-cvttp2si.ll Revert "[NFC] remove explicit default value for strboolattr attribute in tests" 2021-05-24 19:43:40 +02:00
avx-fp2int.ll
…
avx-gfni-intrinsics.ll
…
avx-insertelt.ll [X86] Lower insertions into upper half of an 256-bit vector as broadcast+blend (PR50971) 2021-08-17 18:45:10 +03:00
avx-intel-ocl.ll
…
avx-intrinsics-fast-isel.ll
…
avx-intrinsics-x86-upgrade.ll [DAG] DAGCombiner::visitVECTOR_SHUFFLE - recognise INSERT_SUBVECTOR patterns 2021-08-05 15:40:48 +01:00
avx-intrinsics-x86.ll
…
avx-intrinsics-x86_64.ll [CodeGen][regalloc] Don't align stack slots if the stack can't be realigned 2021-06-11 16:49:12 +01:00
avx-isa-check.ll
…
avx-load-store.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
avx-logic.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
avx-minmax.ll
…
avx-select.ll
…
avx-shift.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
avx-shuffle-x86_32.ll
…
avx-splat.ll
…
avx-trunc.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
avx-unpack.ll
…
avx-varargs-x86_64.ll
…
avx-vbroadcast.ll [X86] Exclude invalid element types for bitcast/broadcast folding. 2021-06-24 12:39:01 +01:00
avx-vbroadcastf128.ll
…
avx-vextractf128.ll
…
avx-vinsertf128.ll
…
avx-vpclmulqdq.ll
…
avx-vperm2x128.ll [DAG] DAGCombiner::visitVECTOR_SHUFFLE - recognise INSERT_SUBVECTOR patterns 2021-08-05 15:40:48 +01:00
avx-vzeroupper.ll [CodeGen][regalloc] Don't align stack slots if the stack can't be realigned 2021-06-11 16:49:12 +01:00
avx-win64-args.ll
…
avx-win64.ll
…
avx.ll [X86][AVX] matchShuffleAsBlend - use isElementEquivalent to help match broadcast/repeated elements 2021-08-22 15:26:17 +01:00
avx1-logical-load-folding.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
avx2-arith.ll [X86][SSE] Regenerate some tests to expose the rip relative vector/broadcast loads 2021-05-26 14:50:47 +01:00
avx2-cmp.ll
…
avx2-conversions.ll [X86] Split FeatureFastVariableShuffle tuning into Lane-Crossing and Per-Lane variants 2021-06-01 10:39:36 +03:00
avx2-fma-fneg-combine.ll [X86] Don't fold (fneg (fma (fneg X), Y, (fneg Z))) to (fma X, Y, Z) 2021-05-21 23:02:19 +08:00
avx2-gather.ll
…
avx2-intrinsics-canonical.ll
…
avx2-intrinsics-fast-isel.ll
…
avx2-intrinsics-x86-upgrade.ll
…
avx2-intrinsics-x86.ll [X86] Remove Commutable flag from mpsadbw intrinsics. 2021-09-19 13:22:22 -07:00
avx2-logic.ll
…
avx2-masked-gather.ll [X86] Lower insertions into upper half of an 256-bit vector as broadcast+blend (PR50971) 2021-08-17 18:45:10 +03:00
avx2-nontemporal.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
avx2-phaddsub.ll
…
avx2-pmovxrm.ll
…
avx2-shift.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
avx2-vbroadcast.ll [X86] Exclude invalid element types for bitcast/broadcast folding. 2021-06-24 12:39:01 +01:00
avx2-vbroadcasti128.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
avx2-vector-shifts.ll [X86] Split FeatureFastVariableShuffle tuning into Lane-Crossing and Per-Lane variants 2021-06-01 10:39:36 +03:00
avx2-vperm.ll
…
avx512-adc-sbb.ll
…
avx512-any_extend_load.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
avx512-arith.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
avx512-broadcast-unfold.ll [X86][SSE] Regenerate some tests to expose the rip relative vector/broadcast loads 2021-05-26 14:50:47 +01:00
avx512-bugfix-23634.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
avx512-bugfix-25270.ll [CodeGen][regalloc] Don't align stack slots if the stack can't be realigned 2021-06-11 16:49:12 +01:00
avx512-bugfix-26264.ll
…
avx512-build-vector.ll
…
avx512-calling-conv.ll RegAllocGreedy: Account for reserved registers in num regs heuristic 2021-09-14 21:00:29 -04:00
avx512-cmp-kor-sequence.ll Revert "[NFC] remove explicit default value for strboolattr attribute in tests" 2021-05-24 19:43:40 +02:00
avx512-cmp-mask.ll
…
avx512-cmp.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
avx512-cvt.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
avx512-cvttp2i.ll
…
avx512-ext.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
avx512-extract-subvector-load-store.ll Fix the default alignment of i1 vectors. 2021-07-31 14:09:59 -07:00
avx512-extract-subvector.ll
…
avx512-fma-commute.ll
…
avx512-fma-intrinsics-upgrade.ll
…
avx512-fma-intrinsics.ll
…
avx512-fma.ll
…
avx512-fsel.ll
…
avx512-gather-scatter-intrin-deprecated.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
avx512-gather-scatter-intrin.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
avx512-gfni-intrinsics.ll
…
avx512-hadd-hsub.ll
…
avx512-i1test.ll
…
avx512-inc-dec.ll [TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation 2021-10-11 15:28:31 -07:00
avx512-insert-extract.ll [X86] Lower insertions into upper half of an 256-bit vector as broadcast+blend (PR50971) 2021-08-17 18:45:10 +03:00
avx512-insert-extract_i1.ll
…
avx512-intel-ocl.ll
…
avx512-intrinsics-canonical.ll
…
avx512-intrinsics-fast-isel.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
avx512-intrinsics-upgrade.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
avx512-intrinsics-x86_64.ll
…
avx512-intrinsics.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
avx512-load-store.ll
…
avx512-load-trunc-store-i1.ll
…
avx512-logic.ll [DAGCombiner] add fold for vselect based on mask of signbit 2021-11-05 10:06:16 -04:00
avx512-mask-op.ll [TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation 2021-10-11 15:28:31 -07:00
avx512-mask-spills.ll
…
avx512-mask-zext-bugfix.ll
…
avx512-masked-memop-64-32.ll [X86] Lower insertions into upper half of an 256-bit vector as broadcast+blend (PR50971) 2021-08-17 18:45:10 +03:00
avx512-masked_memop-16-8.ll
…
avx512-memfold.ll
…
avx512-mov.ll
…
avx512-movmsk.ll
…
avx512-nontemporal.ll
…
avx512-pmovxrm.ll
…
avx512-regcall-Mask.ll
…
avx512-regcall-NoMask.ll [TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation 2021-10-11 15:28:31 -07:00
avx512-rndscale.ll
…
avx512-rotate.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
avx512-scalar.ll
…
avx512-scalarIntrinsics.ll
…
avx512-scalar_mask.ll
…
avx512-select.ll RegAllocGreedy: Account for reserved registers in num regs heuristic 2021-09-14 21:00:29 -04:00
avx512-shift.ll
…
avx512-skx-insert-subvec.ll
…
avx512-trunc.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
avx512-unsafe-fp-math.ll
…
avx512-vbroadcast.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
avx512-vbroadcasti128.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
avx512-vbroadcasti256.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
avx512-vec-cmp.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
avx512-vec3-crash.ll
…
avx512-vpclmulqdq.ll
…
avx512-vpermv3-commute.ll
…
avx512-vpternlog-commute.ll
…
avx512-vselect-crash.ll
…
avx512-vselect.ll
…
avx512bf16-intrinsics.ll
…
avx512bf16-vl-intrinsics.ll
…
avx512bw-arith.ll
…
avx512bw-intrinsics-canonical.ll
…
avx512bw-intrinsics-fast-isel.ll
…
avx512bw-intrinsics-upgrade.ll [DAG] reassociateOpsCommutative - peek through bitcasts to find constants 2021-11-11 12:00:22 +00:00
avx512bw-intrinsics.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
avx512bw-mask-op.ll [TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation 2021-10-11 15:28:31 -07:00
avx512bw-mov.ll
…
avx512bw-vec-cmp.ll
…
avx512bw-vec-test-testn.ll
…
avx512bwvl-arith.ll
…
avx512bwvl-intrinsics-canonical.ll
…
avx512bwvl-intrinsics-fast-isel.ll
…
avx512bwvl-intrinsics-upgrade.ll RegAllocGreedy: Account for reserved registers in num regs heuristic 2021-09-14 21:00:29 -04:00
avx512bwvl-intrinsics.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
avx512bwvl-mov.ll
…
avx512bwvl-vec-cmp.ll
…
avx512bwvl-vec-test-testn.ll
…
avx512cd-intrinsics-fast-isel.ll
…
avx512cd-intrinsics-upgrade.ll
…
avx512cd-intrinsics.ll
…
avx512cdvl-intrinsics-upgrade.ll
…
avx512cdvl-intrinsics.ll
…
avx512cfma-intrinsics.ll [X86][FP16] Change the order of the operands in complex FMA intrinsics to allow swap between the mul operands. 2021-09-23 11:02:48 +08:00
avx512cfmul-intrinsics.ll [X86][FP16] Change the order of the operands in complex FMA intrinsics to allow swap between the mul operands. 2021-09-23 11:02:48 +08:00
avx512cfmulsh-instrinsics.ll [X86][FP16] Change the order of the operands in complex FMA intrinsics to allow swap between the mul operands. 2021-09-23 11:02:48 +08:00
avx512dq-intrinsics-fast-isel.ll
…
avx512dq-intrinsics-upgrade.ll
…
avx512dq-intrinsics.ll
…
avx512dq-mask-op.ll [TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation 2021-10-11 15:28:31 -07:00
avx512dqvl-intrinsics-fast-isel.ll
…
avx512dqvl-intrinsics-upgrade.ll
…
avx512dqvl-intrinsics.ll
…
avx512er-intrinsics.ll
…
avx512f-256-set0.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
avx512f-vec-test-testn.ll
…
avx512fp16-arith-intrinsics.ll [X86] AVX512FP16 instructions enabling 3/6 2021-08-18 09:03:41 +08:00
avx512fp16-arith-vl-intrinsics.ll [X86] Optimize fdiv with reciprocal instructions for half type 2021-10-08 09:41:13 +08:00
avx512fp16-arith.ll [X86] Optimize fdiv with reciprocal instructions for half type 2021-10-08 09:41:13 +08:00
avx512fp16-combine-vfmac-fadd.ll [X86][FP16] Fix a bug when Combine the FADD(A, FMA(B, C, 0)) to FMA(B, C, A). 2021-09-28 11:38:53 +08:00
avx512fp16-combine-vfmulc-fadd.ll [X86][FP16] Fix a bug when Combine the FADD(A, FMA(B, C, 0)) to FMA(B, C, A). 2021-09-28 11:38:53 +08:00
avx512fp16-combine-xor-vfmulc-fadd.ll [X86][FP16] Fix a bug when Combine the FADD(A, FMA(B, C, 0)) to FMA(B, C, A). 2021-09-28 11:38:53 +08:00
avx512fp16-combine-xor-vfmulc.ll [X86] AVX512FP16 instructions enabling 6/6 2021-08-30 13:08:45 +08:00
avx512fp16-cvt-ph-w-intrinsics.ll [X86] AVX512FP16 instructions enabling 3/6 2021-08-18 09:03:41 +08:00
avx512fp16-cvt-ph-w-vl-intrinsics.ll [X86] AVX512FP16 instructions enabling 3/6 2021-08-18 09:03:41 +08:00
avx512fp16-cvt.ll [X86] AVX512FP16 instructions enabling 3/6 2021-08-18 09:03:41 +08:00
avx512fp16-fma-commute.ll [X86] AVX512FP16 instructions enabling 5/6 2021-08-24 09:07:19 +08:00
avx512fp16-fma-intrinsics.ll [X86] AVX512FP16 instructions enabling 5/6 2021-08-24 09:07:19 +08:00
avx512fp16-fmaxnum.ll [X86] AVX512FP16 instructions enabling 2/6 2021-08-15 08:56:33 +08:00
avx512fp16-fminnum.ll [X86] AVX512FP16 instructions enabling 2/6 2021-08-15 08:56:33 +08:00
avx512fp16-fold-load-binops.ll [X86] AVX512FP16 instructions enabling 2/6 2021-08-15 08:56:33 +08:00
avx512fp16-fold-xmm-zero.ll [X86] AVX512FP16 instructions enabling 2/6 2021-08-15 08:56:33 +08:00
avx512fp16-fp-logic.ll [X86] AVX512FP16 instructions enabling 2/6 2021-08-15 08:56:33 +08:00
avx512fp16-insert-extract.ll [X86] AVX512FP16 instructions enabling 1/6 2021-08-10 12:46:01 +08:00
avx512fp16-intrinsics.ll [X86] Optimize fdiv with reciprocal instructions for half type 2021-10-08 09:41:13 +08:00
avx512fp16-machine-combiner.ll [X86] AVX512FP16 instructions enabling 2/6 2021-08-15 08:56:33 +08:00
avx512fp16-mov.ll [X86][FP16] Avoid to generate VZEXT_MOVL with i16 2021-11-12 09:32:29 +08:00
avx512fp16-mscatter.ll [X86] AVX512FP16 instructions enabling 1/6 2021-08-10 12:46:01 +08:00
avx512fp16-rndscale.ll [X86] AVX512FP16 instructions enabling 4/6 2021-08-22 08:59:35 +08:00
avx512fp16-scalar.ll [X86] AVX512FP16 instructions enabling 4/6 2021-08-22 08:59:35 +08:00
avx512fp16-subv-broadcast-fp16.ll [X86] AVX512FP16 instructions enabling 1/6 2021-08-10 12:46:01 +08:00
avx512fp16-unsafe-fp-math.ll [X86] AVX512FP16 instructions enabling 2/6 2021-08-15 08:56:33 +08:00
avx512fp16vl-fma-intrinsics.ll [X86] AVX512FP16 instructions enabling 5/6 2021-08-24 09:07:19 +08:00
avx512fp16vl-intrinsics.ll [X86] Optimize fdiv with reciprocal instructions for half type 2021-10-08 09:41:13 +08:00
avx512ifma-intrinsics-fast-isel.ll
…
avx512ifma-intrinsics-upgrade.ll
…
avx512ifma-intrinsics.ll
…
avx512ifmavl-intrinsics-fast-isel.ll
…
avx512ifmavl-intrinsics-upgrade.ll
…
avx512ifmavl-intrinsics.ll
…
avx512vbmi-intrinsics-fast-isel.ll
…
avx512vbmi-intrinsics-upgrade.ll
…
avx512vbmi-intrinsics.ll
…
avx512vbmi2-funnel-shifts.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
avx512vbmi2-intrinsics-fast-isel.ll
…
avx512vbmi2-intrinsics-upgrade.ll [DAG] CombineConsecutiveLoads - replace getABITypeAlign with allowsMemoryAccess (PR45116) 2021-08-24 12:31:22 +01:00
avx512vbmi2-intrinsics.ll [DAG] CombineConsecutiveLoads - replace getABITypeAlign with allowsMemoryAccess (PR45116) 2021-08-24 12:31:22 +01:00
avx512vbmi2vl-funnel-shifts.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
avx512vbmi2vl-intrinsics-fast-isel.ll
…
avx512vbmi2vl-intrinsics-upgrade.ll
…
avx512vbmi2vl-intrinsics.ll
…
avx512vbmivl-intrinsics-fast-isel.ll
…
avx512vbmivl-intrinsics-upgrade.ll
…
avx512vbmivl-intrinsics.ll
…
avx512vl-arith.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
avx512vl-intrinsics-canonical.ll
…
avx512vl-intrinsics-fast-isel.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
avx512vl-intrinsics-upgrade.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
avx512vl-intrinsics.ll
…
avx512vl-logic.ll [DAGCombiner] add fold for vselect based on mask of signbit 2021-11-05 10:06:16 -04:00
avx512vl-mov.ll
…
avx512vl-nontemporal.ll
…
avx512vl-vbroadcast.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
avx512vl-vec-cmp.ll
…
avx512vl-vec-masked-cmp.ll
…
avx512vl-vec-test-testn.ll
…
avx512vl-vpclmulqdq.ll
…
avx512vl_vnni-intrinsics-upgrade.ll
…
avx512vl_vnni-intrinsics.ll
…
avx512vlcd-intrinsics-fast-isel.ll
…
avx512vlvp2intersect-intrinsics.ll
…
avx512vnni-intrinsics-upgrade.ll
…
avx512vnni-intrinsics.ll
…
avx512vnni.ll
…
avx512vp2intersect-intrinsics.ll
…
avx512vpopcntdq-intrinsics.ll
…
avx_vnni-intrinsics.ll
…
avxvnni.ll
…
backpropmask.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
bad-tls-fold.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
barrier-sse.ll
…
barrier.ll
…
base-pointer-and-cmpxchg.ll reland [IR] make -stack-alignment= into a module attr 2021-06-08 10:59:46 -07:00
base-pointer-and-mwaitx.ll reland [IR] make -stack-alignment= into a module attr 2021-06-08 10:59:46 -07:00
basic-block-sections-blockaddress-taken.ll
…
basic-block-sections-clusters-branches.ll
…
basic-block-sections-clusters-eh.ll
…
basic-block-sections-clusters-error.ll
…
basic-block-sections-clusters.ll
…
basic-block-sections-cold.ll
…
basic-block-sections-directjumps.ll
…
basic-block-sections-eh.ll
…
basic-block-sections-labels-empty-function.ll
…
basic-block-sections-labels-functions-sections.ll
…
basic-block-sections-labels.ll
…
basic-block-sections-list.ll
…
basic-block-sections-listbb.ll
…
basic-block-sections-mir-parse.mir [X86] Update RET/LRET instruction to use the same naming convention as IRET (PR36876). NFC 2021-11-07 15:06:54 +00:00
basic-block-sections-mir-print.ll
…
basic-block-sections-named-section.ll Basic block sections for functions with implicit-section-name attribute 2021-04-29 12:29:34 -07:00
basic-block-sections-pragma-sections.ll Basic block sections for functions with implicit-section-name attribute 2021-04-29 12:29:34 -07:00
basic-block-sections-source-drift.ll
…
basic-block-sections-unreachable.ll
…
basic-block-sections.ll
…
basic-block-sections_2.ll
…
basic-promote-integers.ll
…
bb_rotate.ll
…
bc-extract.ll
…
bigstructret.ll
…
bigstructret2.ll
…
bit-piece-comment.ll Revert "[NFC] remove explicit default value for strboolattr attribute in tests" 2021-05-24 19:43:40 +02:00
bit-test-shift.ll
…
bitcast-and-setcc-128.ll
…
bitcast-and-setcc-256.ll
…
bitcast-and-setcc-512.ll
…
bitcast-i256.ll
…
bitcast-int-to-vector-bool-sext.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
bitcast-int-to-vector-bool-zext.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
bitcast-int-to-vector-bool.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
bitcast-int-to-vector.ll
…
bitcast-mmx.ll
…
bitcast-setcc-128.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
bitcast-setcc-256.ll
…
bitcast-setcc-512.ll
…
bitcast-vector-bool.ll Fix the default alignment of i1 vectors. 2021-07-31 14:09:59 -07:00
bitcast.ll
…
bitcast2.ll
…
bitcnt-false-dep.ll
…
bitreverse.ll [LegalizeVectorOps][X86] Don't defer BITREVERSE expansion to LegalizeDAG. 2021-10-21 15:23:23 -07:00
bittest-intrin.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
block-placement.ll Revert rest of `IRBuilderBase`'s short-circuiting folds 2021-10-28 02:15:14 +03:00
block-placement.mir [X86] Update RET/LRET instruction to use the same naming convention as IRET (PR36876). NFC 2021-11-07 15:06:54 +00:00
block_set.ll
…
bmi-intrinsics-fast-isel-x86_64.ll
…
bmi-intrinsics-fast-isel.ll
…
bmi-x86_64.ll
…
bmi.ll [X86] Fold cmpeq/ne(and(X,Y),Y) --> cmpeq/ne(and(~X,Y),0) 2021-04-11 18:42:01 +01:00
bmi2-x86_64.ll
…
bmi2.ll
…
bool-ext-inc.ll
…
bool-math.ll
…
bool-simplify.ll
…
bool-vector.ll RegAllocGreedy: Account for reserved registers in num regs heuristic 2021-09-14 21:00:29 -04:00
bool-zext.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
br-fold.ll
…
branchfolding-catchpads.ll
…
branchfolding-debug-invariant.mir
…
branchfolding-debugloc.ll
…
branchfolding-ehpad.mir
…
branchfolding-landingpads.ll
…
branchfolding-undef.mir
…
brcond.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
break-anti-dependencies.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
break-false-dep.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
broadcast-elm-cross-splat-vec.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
broadcastm-lowering.ll [X86] Split FeatureFastVariableShuffle tuning into Lane-Crossing and Per-Lane variants 2021-06-01 10:39:36 +03:00
bss_pagealigned.ll
…
bswap-inline-asm.ll
…
bswap-rotate.ll
…
bswap-vector.ll
…
bswap-wide-int.ll
…
bswap.ll RegAllocGreedy: Account for reserved registers in num regs heuristic 2021-09-14 21:00:29 -04:00
bswap_tree.ll
…
bswap_tree2.ll [TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation 2021-10-11 15:28:31 -07:00
bt.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
btc_bts_btr.ll
…
btq.ll
…
bug26810.ll Revert "[NFC] remove explicit default value for strboolattr attribute in tests" 2021-05-24 19:43:40 +02:00
bug37521.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
bug47278-eflags-error.mir
…
bug47278.mir [X86] Update RET/LRET instruction to use the same naming convention as IRET (PR36876). NFC 2021-11-07 15:06:54 +00:00
bug80500.ll
…
build-vector-128.ll RegAllocGreedy: Account for reserved registers in num regs heuristic 2021-09-14 21:00:29 -04:00
build-vector-256.ll
…
build-vector-512.ll
…
build_fp16_constant_vector.ll [X86] Building constant vector which element type is half will cause assertion fail. 2021-08-24 14:34:30 +08:00
buildvec-extract.ll [NFC][X86][Codegen] Re-autogenerate a few tests to reduce noise in future changes 2021-05-28 00:58:01 +03:00
buildvec-insertvec.ll
…
bypass-slow-division-32.ll
…
bypass-slow-division-64.ll
…
bypass-slow-division-tune.ll
…
byref.ll
…
byval-align.ll
…
byval-callee-cleanup.ll
…
byval.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
byval2.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
byval3.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
byval4.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
byval5.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
byval6.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
byval7.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
cache-intrinsic.ll
…
call-imm.ll
…
call-push.ll
…
call-rv-marker.ll [ObjC][ARC] Use the addresses of the ARC runtime functions instead of 2021-09-08 11:58:03 -07:00
call-site-info-output.ll
…
call-structfp.ll [X86] Fix X32 indirect call generation 2021-11-03 16:43:44 +00:00
callbr-asm-bb-exports.ll
…
callbr-asm-blockplacement.ll Revert "Allow rematerialization of virtual reg uses" 2021-09-24 10:26:11 -07:00
callbr-asm-branch-folding.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
callbr-asm-destinations.ll
…
callbr-asm-errors.ll
…
callbr-asm-instr-scheduling.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
callbr-asm-kill.mir [PHIElimination] Account for INLINEASM_BR when inserting kills 2021-10-07 20:04:39 +01:00
callbr-asm-label-addr.ll
…
callbr-asm-obj-file.ll
…
callbr-asm-outputs-pred-succ.ll [MIRParser] Add support for IsInlineAsmBrIndirectTarget 2021-10-07 19:08:01 +01:00
callbr-asm-outputs.ll
…
callbr-asm-phi-placement.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
callbr-asm-sink.ll
…
callbr-asm.ll
…
callbr-codegenprepare.ll
…
cas.ll
…
cast-vsel.ll
…
catch.ll
…
catchpad-dynamic-alloca.ll
…
catchpad-lifetime.ll
…
catchpad-realign-savexmm.ll
…
catchpad-regmask.ll Revert "[NFC] remove explicit default value for strboolattr attribute in tests" 2021-05-24 19:43:40 +02:00
catchpad-reuse.ll
…
catchpad-weight.ll Revert "[NFC] remove explicit default value for strboolattr attribute in tests" 2021-05-24 19:43:40 +02:00
catchret-empty-fallthrough.ll Fix SEH table addresses for Windows 2021-08-20 22:32:12 +03:00
catchret-fallthrough.ll
…
catchret-regmask.ll
…
cet_endbr_imm_enhance.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
cf-opt-memops.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
cfguard-checks.ll
…
cfguard-module-flag.ll
…
cfguard-x86-64-vectorcall.ll
…
cfguard-x86-vectorcall.ll
…
cfi-basic-block-sections-1.ll
…
cfi-epilogue-with-return.mir
…
cfi-epilogue-without-return.mir
…
cfi-inserter-basic-block-sections-callee-save-registers.ll
…
cfi-inserter-callee-save-register-2.mir
…
cfi-inserter-callee-save-register.mir
…
cfi-inserter-cfg-with-merge.mir
…
cfi-inserter-check-order.ll
…
cfi-inserter-noreturnblock.mir
…
cfi-inserter-verify-inconsistent-csr.mir
…
cfi-inserter-verify-inconsistent-loc.mir
…
cfi-inserter-verify-inconsistent-offset.mir
…
cfi-inserter-verify-inconsistent-register.mir
…
cfi-xmm.ll
…
cfi.ll
…
cfstring.ll
…
cgp-usubo.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
chain_order.ll
…
change-compare-stride-1.ll
…
change-compare-stride-trickiness-0.ll
…
change-compare-stride-trickiness-1.ll
…
change-compare-stride-trickiness-2.ll
…
change-unsafe-fp-math.ll
…
cldemote-intrinsic.ll
…
cleanuppad-inalloca.ll Revert "[NFC] remove explicit default value for strboolattr attribute in tests" 2021-05-24 19:43:40 +02:00
cleanuppad-large-codemodel.ll
…
cleanuppad-realign.ll
…
clear-bitfield.ll
…
clear-highbits.ll RegAllocGreedy: Account for reserved registers in num regs heuristic 2021-09-14 21:00:29 -04:00
clear-lowbits.ll [X86] Move newly-added tests into the right file 2021-09-07 23:20:36 +03:00
clear_upper_vector_element_bits.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
clflushopt.ll
…
clwb.ll [X86] Remove FeatureCLWB from FeaturesICLClient 2021-04-12 12:08:59 +08:00
clz.ll [CGP] despeculateCountZeros - Don't create is-zero branch if cttz/ctlz source is known non-zero 2021-07-24 13:11:49 +01:00
clzero.ll
…
cmov-double.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
cmov-fp.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
cmov-into-branch.ll
…
cmov-promotion.ll
…
cmov.ll [X86] Canonicalize SGT/UGT compares with constants to use SGE/UGE to reduce the number of EFLAGs reads. (PR48760) 2021-06-30 18:46:50 +01:00
cmovcmov.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
cmp-bool.ll
…
cmp-concat.ll [TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation 2021-10-11 15:28:31 -07:00
cmp-fast-isel.ll
…
cmp.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
cmpxchg-clobber-flags.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
cmpxchg-i1.ll
…
cmpxchg-i128-i1.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
cmpxchg8b.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
cmpxchg8b_alloca_regalloc_handling.ll
…
coal-sections.ll
…
coalesce-dbg-value-subreg-rewrite.mir
…
coalesce-dead-lanes.mir
…
coalesce-esp.ll
…
coalesce-implicitdef.ll
…
coalesce_commute_movsd.ll
…
coalesce_commute_subreg.ll
…
coalescer-commute1.ll
…
coalescer-commute2.ll
…
coalescer-commute3.ll
…
coalescer-commute4.ll
…
coalescer-commute5.ll
…
coalescer-cross.ll
…
coalescer-dce.ll
…
coalescer-dce2.ll
…
coalescer-identity.ll
…
coalescer-remat.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
coalescer-subreg.ll
…
coalescer-win64.ll
…
code-model-elf-memset.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
code-model-elf.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
code-model-kernel.ll
…
code_placement.ll
…
code_placement_align_all.ll
…
code_placement_cold_loop_blocks.ll
…
code_placement_eh.ll
…
code_placement_ignore_succ_in_inner_loop.ll
…
code_placement_loop_rotation.ll
…
code_placement_loop_rotation2.ll
…
code_placement_loop_rotation3.ll
…
code_placement_no_header_change.ll
…
codegen-prepare-addrmode-sext.ll
…
codegen-prepare-cast.ll
…
codegen-prepare-collapse.ll
…
codegen-prepare-crash.ll
…
codegen-prepare-extload.ll
…
codegen-prepare-replacephi.mir
…
codegen-prepare-replacephi2.mir
…
codegen-prepare-uaddo.ll
…
codegen-prepare.ll
…
codemodel.ll
…
coff-comdat.ll [IR] Rename `comdat noduplicates` to `comdat nodeduplicate` 2021-07-20 12:47:10 -07:00
coff-comdat2.ll
…
coff-comdat3.ll
…
coff-feat00.ll
…
coff-fp-section-name.ll
…
coff-linkonce.ll
…
coff-no-dead-strip.ll
…
coff-weak.ll
…
coldcc64.ll
…
combine-64bit-vec-binop.ll
…
combine-abs.ll [X86] Use CMOVNS for abs instead of CMOVGE. 2021-10-14 12:28:28 -07:00
combine-adc.ll
…
combine-add-ssat.ll [ISel] Expand saddsat and ssubsat via asr and xor 2021-08-19 16:08:07 +01:00
combine-add-usat.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
combine-add.ll [DAGCombiner] don't try to partially reduce add-with-overflow ops 2021-07-29 08:51:54 -04:00
combine-addo.ll
…
combine-adx.ll
…
combine-and.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
combine-avx-intrinsics.ll
…
combine-avx2-intrinsics.ll
…
combine-bextr.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
combine-bitreverse.ll [LegalizeVectorOps][X86] Don't defer BITREVERSE expansion to LegalizeDAG. 2021-10-21 15:23:23 -07:00
combine-bitselect.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
combine-bswap.ll
…
combine-concatvectors.ll [X86][AVX] Add missing X86ISD::VBROADCAST(v4f32 -> v8f32) isel pattern for AVX1 targets 2021-11-07 12:59:35 +00:00
combine-fabs.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
combine-fcopysign.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
combine-lds.ll
…
combine-movmsk-avx.ll
…
combine-movmsk.ll
…
combine-mul.ll [TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation 2021-10-11 15:28:31 -07:00
combine-mulo.ll [TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation 2021-10-11 15:28:31 -07:00
combine-multiplies.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
combine-or.ll [TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation 2021-10-11 15:28:31 -07:00
combine-pmadd.ll [X86] Fold PMADD(x,0) or PMADD(0,x) -> 0 2021-09-02 10:48:50 +01:00
combine-pmuldq.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
combine-ptest.ll
…
combine-rotates.ll [X86][SSE] Regenerate some tests to expose the rip relative vector/broadcast loads 2021-05-26 14:50:47 +01:00
combine-sbb.ll RegAllocGreedy: Account for reserved registers in num regs heuristic 2021-09-14 21:00:29 -04:00
combine-sdiv.ll [TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation 2021-10-11 15:28:31 -07:00
combine-select.ll
…
combine-sext-in-reg.ll
…
combine-shl.ll [DAG] DAGCombiner::foldSelectOfBinops - propagate the common flags to the merged binop 2021-07-18 18:38:59 +01:00
combine-smax.ll [TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation 2021-10-11 15:28:31 -07:00
combine-smin.ll [TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation 2021-10-11 15:28:31 -07:00
combine-sra.ll [TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation 2021-10-11 15:28:31 -07:00
combine-srem.ll [TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation 2021-10-11 15:28:31 -07:00
combine-srl.ll [TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation 2021-10-11 15:28:31 -07:00
combine-sse41-intrinsics.ll
…
combine-sub-ssat.ll
…
combine-sub-usat.ll
…
combine-sub.ll [x86] limit vector increment fold to allow load folding 2021-10-29 15:48:35 -04:00
combine-subo.ll
…
combine-testm-and.ll
…
combine-testpd.ll
…
combine-testps.ll
…
combine-udiv.ll [TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation 2021-10-11 15:28:31 -07:00
combine-umax.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
combine-umin.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
combine-undef-index-mscatter.ll
…
combine-urem.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
combineIncDecVector-crash.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
commandline-metadata.ll
…
commute-3dnow.ll
…
commute-blend-avx2.ll
…
commute-blend-sse41.ll
…
commute-clmul.ll
…
commute-fcmp.ll
…
commute-intrinsic.ll
…
commute-two-addr.ll
…
commute-vpclmulqdq-avx.ll
…
commute-vpclmulqdq-avx512.ll
…
commute-xop.ll
…
commuted-blend-mask.ll
…
compact-unwind.ll
…
compare-add.ll
…
compare-global.ll
…
compare-inf.ll
…
compare_folding.ll
…
compiler_used.ll
…
complex-asm.ll
…
complex-fastmath.ll Revert "[NFC] remove explicit default value for strboolattr attribute in tests" 2021-05-24 19:43:40 +02:00
complex-fca.ll
…
computeKnownBits_urem.ll
…
concat-cast.ll [X86] Implement smarter instruction lowering for FP_TO_UINT from f32/f64 to i32/i64 and vXf32/vXf64 to vXi32 for SSE2 and AVX2 by using the exact semantic of the CVTTPS2SI instruction. 2021-07-14 12:03:49 +01:00
conditional-indecrement.ll
…
conditional-tailcall-pgso.ll
…
conditional-tailcall-samedest.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
conditional-tailcall.ll
…
consecutive-load-shuffle.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
const-base-addr.ll
…
const-shift-of-constmasked.ll
…
constant-combines.ll
…
constant-hoisting-and.ll
…
constant-hoisting-bfi.ll
…
constant-hoisting-cmp.ll
…
constant-hoisting-optnone.ll
…
constant-hoisting-shift-immediate.ll
…
constant-pool-remat-0.ll
…
constant-pool-sharing.ll
…
constpool.ll
…
constrained-fp80-trunc-ext.ll
…
constructor.ll [static initializers] Emit global_ctors and global_dtors in reverse order when .ctors/.dtors are used. 2021-06-10 16:44:47 -07:00
convert-2-addr-3-addr-inc64.ll
…
convertphitype.ll
…
copy-eflags-liveinlists.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
copy-eflags.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
copy-low-subvec-elt-to-high-subvec-elt.ll [X86][TLI] SimplifyDemandedVectorEltsForTargetNode(): don't break apart broadcasts from which not just the 0'th elt is demanded 2021-09-19 17:38:32 +03:00
copy-propagation.ll
…
copysign-constant-magnitude.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
cpus-amd-no-x86_64.ll
…
cpus-amd.ll
…
cpus-intel-no-x86_64.ll
…
cpus-intel.ll [X86] Support -march=rocketlake 2021-04-13 09:48:13 +08:00
cpus-no-x86_64.ll
…
cpus-other.ll
…
crash-O0.ll
…
crash-lre-eliminate-dead-def.ll Revert "[NFC] remove explicit default value for strboolattr attribute in tests" 2021-05-24 19:43:40 +02:00
crash-nosse.ll
…
crash.ll
…
crc32-intrinsics-fast-isel-x86_64.ll [X86] Add CRC32 feature. 2021-09-06 17:24:30 +08:00
crc32-intrinsics-x86.ll [X86] Add CRC32 feature. 2021-09-06 17:24:30 +08:00
crc32-intrinsics-x86_64.ll [X86] Add CRC32 feature. 2021-09-06 17:24:30 +08:00
crc32-target-feature.ll [X86] Add CRC32 feature. 2021-09-06 17:24:30 +08:00
critical-anti-dep-breaker.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
critical-edge-split-2.ll
…
cse-add-with-overflow.ll
…
csr-split.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
cstring.ll
…
ctor-priority-coff.ll
…
ctpop-combine.ll [TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation 2021-10-11 15:28:31 -07:00
cvt16-2.ll [X86] AVX512FP16 instructions enabling 3/6 2021-08-18 09:03:41 +08:00
cvt16.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
cvtv2f32.ll
…
cxx_tlscc64.ll
…
dag-fmf-cse.ll
…
dag-merge-fast-accesses.ll
…
dag-optnone.ll Revert "[NFC] remove explicit default value for strboolattr attribute in tests" 2021-05-24 19:43:40 +02:00
dag-rauw-cse.ll
…
dag-update-nodetomatch.ll Revert "Allow rematerialization of virtual reg uses" 2021-09-24 10:26:11 -07:00
dagcombine-and-setcc.ll
…
dagcombine-buildvector.ll
…
dagcombine-cse.ll
…
dagcombine-dead-store.ll [DAGCombiner] Fix DAG combine store elimination, different address space. 2021-05-12 07:14:22 -07:00
dagcombine-select.ll
…
dagcombine-shifts.ll
…
dagcombine-tokenfactor-limit-crash.ll
…
dagcombine-unsafe-math.ll
…
darwin-bzero.ll
…
darwin-no-dead-strip.ll
…
darwin-preemption.ll
…
darwin-quote.ll
…
darwin-tls.ll
…
dbg-baseptr.ll
…
dbg-changes-codegen-branch-folding.ll Revert "[NFC] remove explicit default value for strboolattr attribute in tests" 2021-05-24 19:43:40 +02:00
dbg-changes-codegen-branch-folding2.mir [X86] Update RET/LRET instruction to use the same naming convention as IRET (PR36876). NFC 2021-11-07 15:06:54 +00:00
dbg-changes-codegen.ll Revert "[NFC] remove explicit default value for strboolattr attribute in tests" 2021-05-24 19:43:40 +02:00
dbg-combine.ll Revert "[NFC] remove explicit default value for strboolattr attribute in tests" 2021-05-24 19:43:40 +02:00
dbg-distringtype-uint.ll [llvm] Inclusive language: replace master with main in file paths in LIT tests 2021-11-08 12:39:50 -06:00
dbg-line-0-no-discriminator.ll
…
dbg-list-dependencies.ll Reapply "[DebugInfo] Correctly track SDNode dependencies for list debug values" 2021-04-12 12:51:29 +01:00
dbg-value-func-arg.ll
…
dbg-value-superreg-copy.mir [X86] Update RET/LRET instruction to use the same naming convention as IRET (PR36876). NFC 2021-11-07 15:06:54 +00:00
debug-loclists-lto.ll Revert "[NFC] remove explicit default value for strboolattr attribute in tests" 2021-05-24 19:43:40 +02:00
debug-loclists.ll
…
debug-nodebug-crash.ll
…
debuginfo-locations-dce.ll
…
debugloc-argsize.ll Revert "[NFC] remove explicit default value for strboolattr attribute in tests" 2021-05-24 19:43:40 +02:00
debugloc-no-line-0.ll
…
delete-dead-instrs-with-live-uses.mir Revert "Allow rematerialization of virtual reg uses" 2021-09-24 10:26:11 -07:00
deopt-bundles.ll
…
deopt-intrinsic-cconv.ll
…
deopt-intrinsic.ll
…
disable-shrink-store.ll
…
disable-tail-calls.ll
…
discontiguous-loops.ll
…
discriminate-mem-ops-missing-info.ll
…
discriminate-mem-ops-skip-pfetch.ll
…
discriminate-mem-ops.ll
…
distancemap.mir [TwoAddressInstructionPass] Put all new instructions into DistanceMap 2021-10-28 11:11:59 -07:00
div-rem-pair-recomposition-signed.ll RegAllocGreedy: Account for reserved registers in num regs heuristic 2021-09-14 21:00:29 -04:00
div-rem-pair-recomposition-unsigned.ll RegAllocGreedy: Account for reserved registers in num regs heuristic 2021-09-14 21:00:29 -04:00
div-rem-simplify.ll
…
div8.ll
…
divide-by-constant.ll
…
divide-windows-itanium.ll
…
divmod128.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
divrem.ll
…
divrem8_ext.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
dllexport-x86_64.ll
…
dllexport.ll [COFF] Force Symbols containing '.' to be quoted 2021-08-30 17:26:57 -04:00
dllimport-x86_64.ll
…
dllimport.ll
…
dollar-name.ll
…
domain-reassignment-implicit-def.ll
…
domain-reassignment-test.ll
…
domain-reassignment.mir [MachineVerifier] Diagnose invalid INSERT_SUBREGs 2021-07-20 17:32:29 -07:00
dont-remove-empty-preheader.ll
…
dont-trunc-store-double-to-float.ll
…
dropped_constructor.ll
…
dso_local_equivalent.ll [Verifier] Add verification logic for GlobalIFuncs 2021-10-31 20:00:57 -07:00
dtor-priority-coff.ll
…
dup-cost.ll
…
dwarf-comp-dir.ll
…
dwarf-eh-prepare.ll Re-apply the fix on DwarfEHPrepare and add a test 2021-10-02 21:50:35 -04:00
dwarf-headers.ll
…
dwarf-split-line-1.ll
…
dwarf-split-line-2.ll
…
dwarf_eh_resume.ll
…
dyn-stackalloc.ll
…
dyn_alloca_aligned.ll
…
dynamic-alloca-in-entry.ll
…
dynamic-alloca-lifetime.ll
…
dynamic-allocas-VLAs-stack-align.ll reland [IR] make -stack-alignment= into a module attr 2021-06-08 10:59:46 -07:00
dynamic-allocas-VLAs.ll reland [IR] make -stack-alignment= into a module attr 2021-06-08 10:59:46 -07:00
dynamic-regmask.ll
…
early-cfi-sections.ll Revert "[NFC] remove explicit default value for strboolattr attribute in tests" 2021-05-24 19:43:40 +02:00
early-ifcvt-crash.ll
…
early-ifcvt-remarks.ll
…
early-ifcvt.ll
…
eh-frame-unreachable.ll
…
eh-label.ll
…
eh-nolandingpads.ll
…
eh-null-personality.ll
…
eh-unknown.ll
…
eh_frame.ll
…
ehcontguard.ll
…
eip-addressing-i386.ll
…
element-wise-atomic-memory-intrinsics.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
elf-associated-discarded.ll Fix typo of colon to semicolon in lit tests 2021-10-09 10:03:50 +08:00
elf-associated.ll
…
elf-comdat.ll
…
elf-comdat2.ll
…
elf-group.ll [IR] Rename `comdat noduplicates` to `comdat nodeduplicate` 2021-07-20 12:47:10 -07:00
elf-retain.ll
…
elf-unique-sections-by-flags.ll [MC] Move elf-unique-sections-by-flags.ll to X86/ 2021-05-26 12:28:17 +01:00
embed-bitcode.ll
…
emit-big-cst.ll
…
empty-function.ll
…
empty-functions.ll
…
empty-struct-return-type.ll
…
emutls-pic.ll
…
emutls-pie.ll
…
emutls.ll
…
emutls_generic.ll
…
enqcmd-intrinsics.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
epilogue-cfi-fp.ll
…
epilogue-cfi-no-fp.ll
…
epilogue.ll
…
equiv_with_fndef.ll
…
equiv_with_vardef.ll
…
evex-to-vex-compress.mir [X86] Update RET/LRET instruction to use the same naming convention as IRET (PR36876). NFC 2021-11-07 15:06:54 +00:00
exception-label.ll
…
exedeps-movq.ll
…
exedepsfix-broadcast.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
expand-call-rvmarker.mir [X86] Update RET/LRET instruction to use the same naming convention as IRET (PR36876). NFC 2021-11-07 15:06:54 +00:00
expand-integer-x86_64-intrinsic-error.ll
…
expand-opaque-const.ll
…
expand-post-ra-pseudo.mir
…
expand-vr64-gr64-copy.mir [X86] Update RET/LRET instruction to use the same naming convention as IRET (PR36876). NFC 2021-11-07 15:06:54 +00:00
explicit-section-mergeable.ll [MC][ELF] Emit unique sections for different flags 2021-05-26 11:51:29 +01:00
extend-set-cc-uses-dbg.ll [llvm] Inclusive language: replace master with main in file paths in LIT tests 2021-11-08 12:39:50 -06:00
extend.ll
…
extended-fma-contraction.ll
…
extern_weak.ll
…
extmul64.ll
…
extmul128.ll
…
extract-bits.ll
…
extract-combine.ll
…
extract-concat.ll
…
extract-extract.ll
…
extract-fp.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
extract-insert.ll
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extract-lowbits.ll [NFC][X86] Adjust multi-use tests in extract-lowbits.ll 2021-09-07 23:20:36 +03:00
extract-store.ll
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extractelement-fp.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
extractelement-from-arg.ll
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extractelement-index.ll
…
extractelement-legalization-cycle.ll
…
extractelement-legalization-store-ordering.ll
…
extractelement-load.ll
…
extractelement-shuffle.ll
…
extractps.ll
…
f16c-intrinsics-fast-isel.ll
…
f16c-intrinsics-upgrade.ll
…
f16c-intrinsics.ll
…
fabs.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
fadd-combines.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
fast-cc-callee-pops.ll
…
fast-cc-merge-stack-adj.ll [TargetLowering] Only inspect attributes in the arguments for ArgListEntry 2021-05-18 14:30:22 -07:00
fast-cc-pass-in-regs.ll [TargetLowering] Only inspect attributes in the arguments for ArgListEntry 2021-05-18 14:30:22 -07:00
fast-isel-abort-warm.ll
…
fast-isel-agg-constant.ll
…
fast-isel-args-fail.ll
…
fast-isel-args-fail2.ll
…
fast-isel-args.ll
…
fast-isel-atomic.ll
…
fast-isel-avoid-unnecessary-pic-base.ll
…
fast-isel-bail.ll
…
fast-isel-bc.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
fast-isel-bitcast-crash.ll
…
fast-isel-bitcasts-avx.ll
…
fast-isel-bitcasts-avx512.ll
…
fast-isel-bitcasts.ll
…
fast-isel-branch_weights.ll
…
fast-isel-call-bool.ll
…
fast-isel-call-cleanup.ll
…
fast-isel-call.ll
…
fast-isel-cmp-branch.ll MachineBasicBlock: add liveout iterator aware of which liveins are defined by the runtime. 2021-05-19 11:00:24 +01:00
fast-isel-cmp-branch2.ll
…
fast-isel-cmp-branch3.ll
…
fast-isel-cmp.ll
…
fast-isel-constpool.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
fast-isel-constrain-store-indexreg.ll
…
fast-isel-deadcode.ll
…
fast-isel-divrem-x86-64.ll
…
fast-isel-divrem.ll
…
fast-isel-double-half-convertion.ll
…
fast-isel-emutls.ll
…
fast-isel-expect.ll
…
fast-isel-extract.ll
…
fast-isel-float-half-convertion.ll
…
fast-isel-fneg.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
fast-isel-fold-mem.ll
…
fast-isel-fptrunc-fpext.ll
…
fast-isel-freeze.ll
…
fast-isel-gc-intrinsics.ll
…
fast-isel-gep.ll
…
fast-isel-gv.ll
…
fast-isel-i1.ll
…
fast-isel-int-float-conversion-x86-64.ll
…
fast-isel-int-float-conversion.ll
…
fast-isel-load-i1.ll
…
fast-isel-mem.ll
…
fast-isel-movsbl-indexreg.ll
…
fast-isel-nontemporal.ll
…
fast-isel-noplt-pic.ll
…
fast-isel-prolog-dbgloc.ll
…
fast-isel-ret-ext.ll
…
fast-isel-select-cmov.ll
…
fast-isel-select-cmov2.ll
…
fast-isel-select-cmp.ll
…
fast-isel-select-pseudo-cmov.ll
…
fast-isel-select-sse.ll
…
fast-isel-select.ll
…
fast-isel-sext-zext.ll
…
fast-isel-sext.ll
…
fast-isel-shift.ll
…
fast-isel-sse12-fptoint.ll
…
fast-isel-stackcheck.ll
…
fast-isel-store.ll
…
fast-isel-tailcall.ll
…
fast-isel-tls.ll
…
fast-isel-trunc-kill-subreg.ll
…
fast-isel-uint-float-conversion-x86-64.ll
…
fast-isel-uint-float-conversion.ll
…
fast-isel-undef-fp.ll [X86] Selecting fld0 for undefined value in fast ISEL. 2021-06-26 08:43:09 +08:00
fast-isel-vecload.ll
…
fast-isel-x32.ll
…
fast-isel-x86-64.ll
…
fast-isel-x86.ll
…
fast-isel.ll
…
fast-regalloc-live-out-debug-values.mir [X86] Update RET/LRET instruction to use the same naming convention as IRET (PR36876). NFC 2021-11-07 15:06:54 +00:00
fastcall-correct-mangling.ll
…
fastcc-2.ll
…
fastcc-byval.ll
…
fastcc-sret.ll
…
fastcc.ll
…
fastcc3struct.ll
…
fastisel-gep-promote-before-add.ll
…
fastisel-memset-flush.ll
…
fastisel-softfloat.ll
…
fastmath-float-half-conversion.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
fcmove.ll
…
fcmp-constant.ll
…
fcmp-logic.ll [x86] add test for 3 fcmps and logic; NFC 2021-09-30 11:02:59 -04:00
fdiv-combine-vec.ll
…
fdiv-combine.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
fdiv.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
fentry-insertion.ll
…
field-extract-use-trunc.ll
…
fildll.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
file-directive.ll
…
file-source-filename.ll
…
finite-libcalls.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
fixed-stack-di-mir.ll
…
fixup-bw-copy.ll
…
fixup-bw-copy.mir [X86] Update RET/LRET instruction to use the same naming convention as IRET (PR36876). NFC 2021-11-07 15:06:54 +00:00
fixup-bw-inst.ll
…
fixup-bw-inst.mir [X86] Update RET/LRET instruction to use the same naming convention as IRET (PR36876). NFC 2021-11-07 15:06:54 +00:00
fixup-lea.ll
…
flags-copy-lowering.mir Recommit "[X86] Clear kill flags when rewriting SETCC uses in flag copy lowering." 2021-09-21 14:59:25 -07:00
float-asmprint.ll
…
float-conv-elim.ll Revert "[NFC] remove explicit default value for strboolattr attribute in tests" 2021-05-24 19:43:40 +02:00
floor-soft-float.ll
…
flt-rounds.ll
…
fltused.ll
…
fltused_function_pointer.ll
…
fltused_math.ll
…
fma-commute-loop.ll
…
fma-commute-x86.ll
…
fma-do-not-commute.ll
…
fma-fneg-combine-2.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
fma-fneg-combine.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
fma-intrinsics-canonical.ll
…
fma-intrinsics-fast-isel.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
fma-intrinsics-phi-213-to-231.ll
…
fma-intrinsics-x86-upgrade.ll
…
fma-intrinsics-x86.ll
…
fma-phi-213-to-231.ll
…
fma-scalar-combine.ll [DAGCombine] Add node level checks for fp-contract and fp-ninf in visitFMULForFMADistributiveCombine(). 2021-09-02 11:33:14 +05:30
fma-scalar-memfold.ll
…
fma-signed-zero.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
fma.ll [CodeGen][regalloc] Don't align stack slots if the stack can't be realigned 2021-06-11 16:49:12 +01:00
fma4-commute-x86.ll
…
fma4-fneg-combine.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
fma4-intrinsics-x86-upgrade.ll
…
fma4-intrinsics-x86.ll
…
fma4-intrinsics-x86_64-folded-load.ll
…
fma4-scalar-memfold.ll
…
fma_patterns.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
fma_patterns_wide.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
fmaddsub-combine.ll
…
fmaxnum.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
fmf-flags.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
fmf-propagation.ll [x86] propagate FMF from x86-specific intrinsic nodes to others during lowering 2021-05-19 13:11:15 -04:00
fmf-reduction.ll
…
fminnum.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
fmsubadd-combine.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
fmul-combines.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
fnabs.ll
…
fold-add.ll
…
fold-and-shift-x86_64.ll
…
fold-and-shift.ll
…
fold-call-2.ll
…
fold-call-3.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
fold-call-oper.ll
…
fold-call.ll
…
fold-imm.ll
…
fold-load-binops.ll
…
fold-load-unops.ll
…
fold-load-vec.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
fold-load.ll
…
fold-mul-lohi.ll
…
fold-pcmpeqd-1.ll
…
fold-pcmpeqd-2.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
fold-push.ll
…
fold-rmw-ops.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
fold-sext-trunc.ll [llvm] Inclusive language: replace master with main in file paths in LIT tests 2021-11-08 12:39:50 -06:00
fold-tied-op.ll Revert "[NFC] remove explicit default value for strboolattr attribute in tests" 2021-05-24 19:43:40 +02:00
fold-vector-bv-crash.ll
…
fold-vector-sext-crash.ll
…
fold-vector-sext-crash2.ll
…
fold-vector-sext-zext.ll
…
fold-vector-shl-crash.ll
…
fold-vector-shuffle-crash.ll
…
fold-vector-trunc-sitofp.ll
…
fold-vex.ll
…
fold-xmm-zero.ll
…
fold-zext-trunc.ll [llvm] Inclusive language: replace master with main in file paths in LIT tests 2021-11-08 12:39:50 -06:00
fops-windows-itanium.ll
…
force-align-stack-alloca.ll reland [IR] make -stack-alignment= into a module attr 2021-06-08 10:59:46 -07:00
force-align-stack.ll
…
fp-arith.ll
…
fp-cvt.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
fp-double-rounding.ll
…
fp-elim-and-no-fp-elim.ll
…
fp-elim.ll
…
fp-fast.ll
…
fp-fold.ll
…
fp-immediate-shorten.ll
…
fp-in-intregs.ll
…
fp-intrinsics-flags-x86_64.ll
…
fp-intrinsics-flags.ll CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
fp-intrinsics-fma.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
fp-intrinsics.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
fp-load-trunc.ll
…
fp-logic-replace.ll
…
fp-logic.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
fp-round.ll [X86][ISel] Lowering FROUND(f16) and FROUNDEVEN(f16) 2021-09-27 13:35:03 +08:00
fp-roundeven.ll [X86][ISel] Lowering FROUND(f16) and FROUNDEVEN(f16) 2021-09-27 13:35:03 +08:00
fp-select-cmp-and.ll
…
fp-stack-2results.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
fp-stack-O0-crash.ll
…
fp-stack-O0.ll
…
fp-stack-compare-cmov.ll
…
fp-stack-compare.ll
…
fp-stack-direct-ret.ll
…
fp-stack-ret-conv.ll
…
fp-stack-ret-store.ll
…
fp-stack-ret.ll
…
fp-stack-retcopy.ll
…
fp-stack-set-st1.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
fp-stack.ll
…
fp-strict-libcalls-msvc32.ll
…
fp-strict-scalar-cmp-fp16.ll [X86] AVX512FP16 instructions enabling 2/6 2021-08-15 08:56:33 +08:00
fp-strict-scalar-cmp.ll
…
fp-strict-scalar-fp16.ll [X86] AVX512FP16 instructions enabling 5/6 2021-08-24 09:07:19 +08:00
fp-strict-scalar-fptoint-fp16.ll [X86] AVX512FP16 instructions enabling 3/6 2021-08-18 09:03:41 +08:00
fp-strict-scalar-fptoint.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
fp-strict-scalar-inttofp-fp16.ll [X86] AVX512FP16 instructions enabling 3/6 2021-08-18 09:03:41 +08:00
fp-strict-scalar-inttofp.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
fp-strict-scalar-round-fp16.ll [X86][ISel] Lowering FROUND(f16) and FROUNDEVEN(f16) 2021-09-27 13:35:03 +08:00
fp-strict-scalar-round.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
fp-strict-scalar.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
fp-trunc.ll
…
fp-undef.ll
…
fp-une-cmp.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
fp2sint.ll
…
fp80-strict-libcalls.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
fp80-strict-scalar-cmp.ll
…
fp80-strict-scalar.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
fp128-calling-conv.ll
…
fp128-cast-strict.ll [X86] AVX512FP16 instructions enabling 1/6 2021-08-10 12:46:01 +08:00
fp128-cast.ll RegAllocGreedy: Account for reserved registers in num regs heuristic 2021-09-14 21:00:29 -04:00
fp128-compare.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
fp128-extract.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
fp128-g.ll Revert "[NFC] remove explicit default value for strboolattr attribute in tests" 2021-05-24 19:43:40 +02:00
fp128-i128.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
fp128-libcalls-strict.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
fp128-libcalls.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
fp128-load.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
fp128-select.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
fp128-store.ll
…
fp_constant_op.ll
…
fp_load_cast_fold.ll
…
fp_load_fold.ll
…
fpcmp-soft-fp.ll
…
fpenv.ll [FPEnv][X86] Implement lowering of llvm.set.rounding 2021-05-13 14:30:38 +07:00
fpstack-debuginstr-kill.ll
…
fptosi-constant.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
fptosi-sat-scalar.ll RegAllocGreedy: Account for reserved registers in num regs heuristic 2021-09-14 21:00:29 -04:00
fptoui-may-overflow.ll [X86] Remove incorrect use of known bits in shuffle simplification. 2021-07-18 18:13:11 -07:00
fptoui-sat-scalar.ll [X86] Implement smarter instruction lowering for FP_TO_UINT from f32/f64 to i32/i64 and vXf32/vXf64 to vXi32 for SSE2 and AVX2 by using the exact semantic of the CVTTPS2SI instruction. 2021-07-14 12:03:49 +01:00
frame-base.ll
…
frame-lowering-debug-intrinsic-2.ll
…
frame-lowering-debug-intrinsic.ll
…
frame-order.ll Revert "[NFC] remove explicit default value for strboolattr attribute in tests" 2021-05-24 19:43:40 +02:00
frameaddr.ll
…
frameregister.ll
…
freeze-combine.ll
…
freeze-constant-fold.ll [DAG] isGuaranteedNotToBeUndefOrPoison - handle ISD::BUILD_VECTOR nodes 2021-07-31 15:08:25 +01:00
freeze-legalize.ll [DAG] isGuaranteedNotToBeUndefOrPoison - handle ISD::BUILD_VECTOR nodes 2021-07-31 15:08:25 +01:00
freeze.ll [X86] Add ISD::FREEZE and ISD::AssertAlign to the list of opcodes that don't guarantee upper 32 bits are zero. 2021-06-12 09:52:29 -07:00
frem-msvc32.ll
…
fsafdo_test1.ll [SampleFDO] Add two passes of MIRAddFSDiscriminatorsPass 2021-08-11 11:11:04 -07:00
fsafdo_test2.ll Fix CodeGen/X86/fsafdo_test2.ll fail in release 2021-08-19 16:54:04 +01:00
fsgsbase.ll
…
fshl.ll [SelectionDAG] Optimize expansion for rotates/funnel shifts 2021-11-02 11:38:25 +00:00
fshr.ll [SelectionDAG] Optimize expansion for rotates/funnel shifts 2021-11-02 11:38:25 +00:00
fsxor-alignment.ll
…
ftrunc.ll [X86] Implement smarter instruction lowering for FP_TO_UINT from f32/f64 to i32/i64 and vXf32/vXf64 to vXi32 for SSE2 and AVX2 by using the exact semantic of the CVTTPS2SI instruction. 2021-07-14 12:03:49 +01:00
full-lsr.ll
…
funclet-layout.ll
…
function-alias.ll
…
function-subtarget-features-2.ll
…
function-subtarget-features.ll [X86] Add CRC32 feature. 2021-09-06 17:24:30 +08:00
funnel-shift-rot.ll [SelectionDAG] Optimize expansion for rotates/funnel shifts 2021-11-02 11:38:25 +00:00
funnel-shift.ll [SelectionDAG] Optimize expansion for rotates/funnel shifts 2021-11-02 11:38:25 +00:00
ga-offset.ll
…
ga-offset2.ll
…
gather-addresses.ll RegAllocGreedy: Account for reserved registers in num regs heuristic 2021-09-14 21:00:29 -04:00
gcc_except_table-multi.ll [IR] Rename `comdat noduplicates` to `comdat nodeduplicate` 2021-07-20 12:47:10 -07:00
gcc_except_table.ll
…
gcc_except_table_bb_sections.ll [X86] Fix position-independent TType encoding 2021-05-10 17:04:33 +01:00
gcc_except_table_bb_sections_ehpad_groups_with_cold.ll
…
gcc_except_table_functions.ll
…
gep-expanded-vector.ll
…
getelementptr.ll
…
gfni-intrinsics.ll
…
ghc-cc.ll
…
ghc-cc64.ll
…
global-access-pie.ll
…
global-fill.ll
…
global-sections-comdat.ll
…
global-sections-tls.ll
…
global-sections.ll
…
gnu-eh-alternative.ll
…
gnu-seh-nolpads.ll
…
gpr-to-mask.ll
…
greedy_regalloc_bad_eviction_sequence.ll Revert "[NFC] remove explicit default value for strboolattr attribute in tests" 2021-05-24 19:43:40 +02:00
gs-fold.ll
…
h-register-addressing-32.ll
…
h-register-addressing-64.ll
…
h-register-store.ll
…
h-registers-0.ll
…
h-registers-1.ll
…
h-registers-2.ll
…
h-registers-3.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
haddsub-2.ll
…
haddsub-3.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
haddsub-4.ll
…
haddsub-broadcast.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
haddsub-shuf-undef-operand.ll
…
haddsub-shuf.ll [TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation 2021-10-11 15:28:31 -07:00
haddsub-undef.ll [TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation 2021-10-11 15:28:31 -07:00
haddsub.ll [TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation 2021-10-11 15:28:31 -07:00
half-constrained.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
half.ll [LegalizeTypes][X86] Improve ExpandIntRes_FP_TO_SINT/ExpandIntRes_FP_TO_UINT when input is SoftPromoteHalf. 2021-08-30 13:12:59 -07:00
handle-move.ll
…
heap-alloc-markers.mir
…
hhvm-cc.ll
…
hidden-vis-2.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
hidden-vis-3.ll
…
hidden-vis-4.ll
…
hidden-vis-pic.ll
…
hidden-vis.ll
…
hipe-cc.ll reland [IR] make -stack-alignment= into a module attr 2021-06-08 10:59:46 -07:00
hipe-cc64.ll reland [IR] make -stack-alignment= into a module attr 2021-06-08 10:59:46 -07:00
hipe-prologue.ll
…
hoist-and-by-const-from-lshr-in-eqcmp-zero.ll RegAllocGreedy: Account for reserved registers in num regs heuristic 2021-09-14 21:00:29 -04:00
hoist-and-by-const-from-shl-in-eqcmp-zero.ll RegAllocGreedy: Account for reserved registers in num regs heuristic 2021-09-14 21:00:29 -04:00
hoist-common.ll
…
hoist-invariant-load.ll [tests] Stablize tests for possible change in deref semantics 2021-07-14 13:05:43 -07:00
hoist-spill-lpad.ll
…
hoist-spill.ll
…
horizontal-reduce-add.ll
…
horizontal-reduce-fadd.ll [TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation 2021-10-11 15:28:31 -07:00
horizontal-reduce-smax.ll RegAllocGreedy: Account for reserved registers in num regs heuristic 2021-09-14 21:00:29 -04:00
horizontal-reduce-smin.ll RegAllocGreedy: Account for reserved registers in num regs heuristic 2021-09-14 21:00:29 -04:00
horizontal-reduce-umax.ll RegAllocGreedy: Account for reserved registers in num regs heuristic 2021-09-14 21:00:29 -04:00
horizontal-reduce-umin.ll RegAllocGreedy: Account for reserved registers in num regs heuristic 2021-09-14 21:00:29 -04:00
horizontal-shuffle-2.ll [X86][SSE] Fix typo + infinite-loop in HOP(HOP'(X,X),HOP'(Y,Y)) fold (PR52040) 2021-10-02 15:31:12 +01:00
horizontal-shuffle-3.ll [X86][AVX] Add PR49971 test case 2021-04-22 11:32:29 +01:00
horizontal-shuffle-4.ll [X86][SSE] Add tests for permute(phaddw(phaddw(x,y),phaddw(z,w))) -> phaddw(phaddw(),phaddw()) folds. 2021-05-11 17:47:10 +01:00
horizontal-shuffle-demanded.ll
…
horizontal-shuffle.ll [X86][AVX] canonicalizeShuffleMaskWithHorizOp - improve support for 256/512-bit vectors 2021-05-12 12:13:24 +01:00
horizontal-sum.ll [TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation 2021-10-11 15:28:31 -07:00
hot-unlikely-section-prefix.ll
…
huge-stack-offset.ll
…
huge-stack-offset2.ll
…
i1narrowfail.ll [DAG] ReduceLoadOpStoreWidth - replace getABITypeAlign with allowsMemoryAccess (PR45116) 2021-09-25 18:35:57 +01:00
i2k.ll
…
i16lshr8pat.ll
…
i64-mem-copy.ll
…
i64-to-float.ll RegAllocGreedy: Account for reserved registers in num regs heuristic 2021-09-14 21:00:29 -04:00
i128-add.ll
…
i128-and-beyond.ll
…
i128-fpconv-win64-strict.ll [X86] Fix handling of i128<->fp on Windows 2021-09-29 13:05:59 +03:00
i128-fpconv-win64.ll [X86] Fix handling of i128<->fp on Windows 2021-09-29 13:05:59 +03:00
i128-immediate.ll
…
i128-mul.ll [TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation 2021-10-11 15:28:31 -07:00
i128-ret.ll
…
i128-sdiv.ll RegAllocGreedy: Account for reserved registers in num regs heuristic 2021-09-14 21:00:29 -04:00
i128-udiv.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
i256-add.ll RegAllocGreedy: Account for reserved registers in num regs heuristic 2021-09-14 21:00:29 -04:00
i386-setjmp-pic.ll
…
i386-shrink-wrapping.ll Revert "[NFC] remove explicit default value for strboolattr attribute in tests" 2021-05-24 19:43:40 +02:00
i386-tlscall-fastregalloc.ll
…
i486-fence-loop.ll
…
i686-win-shrink-wrapping.ll
…
iabs.ll [X86] Use CMOVNS for abs instead of CMOVGE. 2021-10-14 12:28:28 -07:00
icall-branch-funnel.ll
…
icmp-opt.ll
…
icmp-shift-opt.ll [CodeGen] Add PR50197 AArch64/ARM/X86 test coverage 2021-10-22 14:22:46 +01:00
ident-metadata.ll
…
ifunc-asm.ll [Verifier] Add verification logic for GlobalIFuncs 2021-10-31 20:00:57 -07:00
illegal-bitfield-loadstore.ll RegAllocGreedy: Account for reserved registers in num regs heuristic 2021-09-14 21:00:29 -04:00
illegal-insert.ll
…
illegal-vector-args-return.ll
…
immediate_merging.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
immediate_merging64.ll
…
implicit-faultmap.ll
…
implicit-null-check-negative.ll
…
implicit-null-check.ll
…
implicit-null-checks.mir [X86] Update RET/LRET instruction to use the same naming convention as IRET (PR36876). NFC 2021-11-07 15:06:54 +00:00
implicit-null-chk-reg-rewrite.mir [X86] Update RET/LRET instruction to use the same naming convention as IRET (PR36876). NFC 2021-11-07 15:06:54 +00:00
implicit-use-spill.mir
…
imul-lea-2.ll
…
imul-lea.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
imul.ll [TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation 2021-10-11 15:28:31 -07:00
inalloca-ctor.ll
…
inalloca-invoke.ll Revert "Allow rematerialization of virtual reg uses" 2021-09-24 10:26:11 -07:00
inalloca-regparm.ll
…
inalloca-stdcall.ll
…
inalloca.ll
…
inc-of-add.ll
…
inconsistent_landingpad.ll
…
indirect-branch-tracking-cm-lager.ll
…
indirect-branch-tracking-eh.ll
…
indirect-branch-tracking-eh2.ll Revert "Revert "Temporarily do not drop volatile stores before unreachable"" 2021-07-09 11:44:34 -04:00
indirect-branch-tracking-r2.ll
…
indirect-branch-tracking.ll [X32][CET] Fix handling of indirect branches 2021-04-29 08:33:22 +01:00
indirect-hidden.ll
…
init-priority.ll
…
inline-0bh.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
inline-asm-2addr.ll
…
inline-asm-A-constraint.ll [TwoAddressInstructionPass] Update existing physreg live intervals 2021-11-05 21:20:30 +00:00
inline-asm-R-constraint.ll
…
inline-asm-avx-v-constraint-32bit.ll
…
inline-asm-avx-v-constraint.ll
…
inline-asm-avx512f-v-constraint.ll
…
inline-asm-avx512f-x-constraint.ll [X86] Enable half type support in inline assembly constraints 2021-09-01 09:29:31 +08:00
inline-asm-avx512vl-v-constraint-32bit.ll
…
inline-asm-avx512vl-v-constraint.ll
…
inline-asm-bad-constraint-n.ll
…
inline-asm-bad-modifier.ll
…
inline-asm-default-clobbers.ll
…
inline-asm-duplicated-constraint.ll
…
inline-asm-e-constraint.ll
…
inline-asm-error.ll
…
inline-asm-flag-clobber.ll
…
inline-asm-flag-output.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
inline-asm-fpstack.ll Add nounwind for tests. NFC 2021-11-12 21:09:05 +08:00
inline-asm-h.ll
…
inline-asm-i-constraint-i1.ll
…
inline-asm-imm-out-of-range.ll
…
inline-asm-modifier-V.ll
…
inline-asm-modifier-c.ll
…
inline-asm-modifier-n.ll
…
inline-asm-modifier-q.ll
…
inline-asm-mrv.ll
…
inline-asm-multilevel-gep.ll
…
inline-asm-n-constraint.ll
…
inline-asm-out-regs.ll
…
inline-asm-pic.ll
…
inline-asm-ptr-cast.ll
…
inline-asm-q-regs.ll
…
inline-asm-sp-clobber-memcpy.ll
…
inline-asm-stack-realign.ll
…
inline-asm-stack-realign2.ll
…
inline-asm-stack-realign3.ll
…
inline-asm-tied.ll
…
inline-asm-x-i128.ll
…
inline-asm-x-scalar.ll
…
inline-asm.ll
…
inline-sse.ll
…
inlineasm-sched-bug.ll
…
innermost-loop-alignment.ll [CodeGen] Add -align-loops 2021-08-04 12:45:18 -07:00
inreg.ll
…
ins_split_regalloc.ll
…
ins_subreg_coalesce-1.ll
…
ins_subreg_coalesce-2.ll
…
ins_subreg_coalesce-3.ll
…
insert-into-constant-vector.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
insert-loaded-scalar.ll
…
insert-positions.ll
…
insert-prefetch-inline.afdo
…
insert-prefetch-inline.ll
…
insert-prefetch-invalid-instr.afdo
…
insert-prefetch-invalid-instr.ll
…
insert-prefetch-other.afdo
…
insert-prefetch.afdo
…
insert-prefetch.ll
…
insertelement-copytoregs.ll
…
insertelement-duplicates.ll
…
insertelement-legalize.ll
…
insertelement-ones.ll [X86] Improve i8 all-ones element insertion in pre-SSE4.1 2021-09-18 22:24:06 +03:00
insertelement-shuffle.ll [X86] Lower insertions into upper half of an 256-bit vector as broadcast+blend (PR50971) 2021-08-17 18:45:10 +03:00
insertelement-var-index.ll [X86] Fix lowering to illegal type in LowerINSERT_VECTOR_ELT 2021-07-28 08:16:59 +08:00
insertelement-zero.ll [X86] Split FeatureFastVariableShuffle tuning into Lane-Crossing and Per-Lane variants 2021-06-01 10:39:36 +03:00
insertps-O0-bug.ll
…
insertps-combine.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
insertps-from-constantpool.ll
…
insertps-unfold-load-bug.ll
…
instr-symbols.mir [X86] Update RET/LRET instruction to use the same naming convention as IRET (PR36876). NFC 2021-11-07 15:06:54 +00:00
int-intrinsic.ll
…
intersect-fma-fmf.ll
…
interval-update-remat.ll
…
invalid-liveness.mir [X86] Update RET/LRET instruction to use the same naming convention as IRET (PR36876). NFC 2021-11-07 15:06:54 +00:00
invalid-shift-immediate.ll
…
invpcid-intrinsic.ll
…
ipra-inline-asm.ll
…
ipra-local-linkage.ll
…
ipra-reg-alias.ll
…
ipra-reg-usage.ll [X86] Remove little support we had for MPX 2021-10-12 16:18:51 -07:00
ipra-transform.ll
…
isel-blendi-gettargetconstant.ll
…
isel-optnone.ll
…
isel-postprocessing-test-fold-memop.ll CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
isel-sink.ll
…
isel-sink2.ll
…
isel-sink3.ll
…
isint.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
isnan.ll
…
isnan2.ll
…
ispositive.ll
…
jump_sign.ll X86InstrInfo: Look across basic blocks in optimizeCompareInstr 2021-10-24 16:22:45 -07:00
keylocker-intrinsics-fast-isel.ll
…
keylocker-intrinsics.ll [X86] Adjust Keylocker handle mem size 2021-09-13 18:03:27 +08:00
known-bits-vector.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
known-bits.ll
…
known-signbits-vector.ll RegAllocGreedy: Account for reserved registers in num regs heuristic 2021-09-14 21:00:29 -04:00
kshift.ll
…
label-annotation.ll Revert "[NFC] remove explicit default value for strboolattr attribute in tests" 2021-05-24 19:43:40 +02:00
label-heapallocsite.ll Revert "[NFC] remove explicit default value for strboolattr attribute in tests" 2021-05-24 19:43:40 +02:00
label-redefinition.ll
…
lack-of-signed-truncation-check.ll [X86] Canonicalize SGT/UGT compares with constants to use SGE/UGE to reduce the number of EFLAGs reads. (PR48760) 2021-06-30 18:46:50 +01:00
lakemont.ll
…
large-code-model-isel.ll
…
large-constants.ll
…
large-gep-chain.ll
…
large-gep-scale.ll
…
large-global.ll
…
large-pic-string.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
late-address-taken.ll
…
late-remat-update-2.mir
…
late-remat-update.mir Revert "[NFC] remove explicit default value for strboolattr attribute in tests" 2021-05-24 19:43:40 +02:00
ldzero.ll
…
lea-2.ll
…
lea-3.ll
…
lea-4.ll
…
lea-5.ll
…
lea-dagdag.ll
…
lea-opt-cse1.ll
…
lea-opt-cse2.ll
…
lea-opt-cse3.ll
…
lea-opt-cse4.ll
…
lea-opt-memop-check-1.ll Revert "[NFC] remove explicit default value for strboolattr attribute in tests" 2021-05-24 19:43:40 +02:00
lea-opt-memop-check-2.ll
…
lea-opt-with-debug.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
lea-opt.ll
…
lea-opt2.ll [X86FixupLEAs] Try again to transform the sequence LEA/SUB to SUB/SUB 2021-07-16 10:16:03 -07:00
lea-recursion.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
lea.ll
…
leaFixup32.mir [X86] Update RET/LRET instruction to use the same naming convention as IRET (PR36876). NFC 2021-11-07 15:06:54 +00:00
leaFixup64.mir [X86] Update RET/LRET instruction to use the same naming convention as IRET (PR36876). NFC 2021-11-07 15:06:54 +00:00
leaf-fp-elim.ll
…
legalize-fmp-oeq-vector-select.ll
…
legalize-libcalls.ll
…
legalize-shift-64.ll
…
legalize-shift.ll
…
legalize-shl-vec.ll RegAllocGreedy: Account for reserved registers in num regs heuristic 2021-09-14 21:00:29 -04:00
legalize-sub-zero-2.ll
…
legalize-sub-zero.ll
…
legalize-types-remapid.ll
…
legalize-vaarg.ll
…
legalizedag_vec.ll
…
libcall-sret.ll
…
licm-dominance.ll [tests] Stablize tests for possible change in deref semantics 2021-07-14 13:05:43 -07:00
licm-nested.ll
…
licm-regpressure.ll Revert "Allow rematerialization of virtual reg uses" 2021-09-24 10:26:11 -07:00
licm-symbol.ll
…
lifetime-alias.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
limit-split-cost.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
limited-prec.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
line-zero-prologue-end.ll Do not emit prologue_end for line 0 locs if there is a non-zero loc present 2021-10-07 13:54:28 -07:00
linux-preemption.ll
…
lit.local.cfg
…
live-out-reg-info.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
live-range-nosubreg.ll
…
liveness-local-regalloc.ll
…
llc-override-mcpu-mattr.ll
…
llc-start-stop-instance.ll
…
llrint-conv.ll
…
llround-conv.ll
…
load-chain.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
load-combine-dbg.ll
…
load-combine.ll RegAllocGreedy: Account for reserved registers in num regs heuristic 2021-09-14 21:00:29 -04:00
load-local-v3i1.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
load-local-v3i129.ll Fix the default alignment of i1 vectors. 2021-07-31 14:09:59 -07:00
load-local-v4i5.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
load-partial-dot-product.ll [X86][SSE] Fix copy+paste typo in dot3_float4_as_float3 partial load test 2021-07-19 11:50:30 +01:00
load-partial.ll [DAG] LoadedSlice::canMergeExpensiveCrossRegisterBankCopy - replace getABITypeAlign with allowsMemoryAccess (PR45116) 2021-08-24 15:28:30 +01:00
load-scalar-as-vector.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
load-slice.ll
…
loadStore_vectorizer.ll
…
loc-remat.ll
…
local_stack_symbol_ordering.ll
…
localescape.ll
…
log2_not_readnone.ll
…
logical-load-fold.ll
…
long-setcc.ll
…
longlong-deadload.ll
…
loop-blocks.ll
…
loop-hoist.ll
…
loop-rotate.ll
…
loop-search.ll
…
loop-strength-reduce-2.ll
…
loop-strength-reduce-3.ll
…
loop-strength-reduce-crash.ll
…
loop-strength-reduce.ll
…
loop-strength-reduce2.ll
…
loop-strength-reduce4.ll
…
loop-strength-reduce5.ll
…
loop-strength-reduce6.ll
…
loop-strength-reduce7.ll
…
loop-strength-reduce8.ll
…
lower-bitcast.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
lower-ptrmask.ll
…
lower-vec-shift-2.ll
…
lower-vec-shift.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
lower-vec-shuffle-bug.ll
…
lrint-conv-i32.ll
…
lrint-conv-i64.ll
…
lround-conv-i32.ll
…
lround-conv-i64.ll
…
lrshrink.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
lsr-crash-empty-uses.ll
…
lsr-delayed-fold.ll
…
lsr-i386.ll
…
lsr-interesting-step.ll
…
lsr-loop-exit-cond.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
lsr-negative-stride.ll
…
lsr-nonaffine.ll
…
lsr-normalization.ll
…
lsr-overflow.ll
…
lsr-quadratic-expand.ll
…
lsr-redundant-addressing.ll
…
lsr-reuse-trunc.ll
…
lsr-reuse.ll
…
lsr-sort.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
lsr-static-addr.ll
…
lsr-wrap.ll
…
lvi-hardening-gadget-graph.ll CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
lvi-hardening-indirectbr.ll
…
lvi-hardening-inline-asm.ll
…
lvi-hardening-loads.ll
…
lvi-hardening-ret.ll
…
lwp-intrinsics-x86_64.ll
…
lwp-intrinsics.ll
…
lzcnt-cmp.ll
…
lzcnt-tzcnt.ll
…
lzcnt-zext-cmp.ll [x86] convert logic-of-FP-compares to FP logic-of-vector-compares 2021-09-24 11:38:19 -04:00
lzcnt.ll
…
macCatalyst.ll
…
machine-combiner-int-vec.ll
…
machine-combiner-int.ll
…
machine-combiner.ll [DAGCombine] reassoc flag shouldn't enable contract 2021-06-21 21:15:43 +00:00
machine-copy-dbgvalue.mir [X86] Update RET/LRET instruction to use the same naming convention as IRET (PR36876). NFC 2021-11-07 15:06:54 +00:00
machine-copy-prop.mir
…
machine-cp-debug.mir
…
machine-cp-mask-reg.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
machine-cp.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
machine-cse.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
machine-function-splitter.ll [CodeGen] Do not split functions with attr "implicit-section-name". 2021-04-21 21:51:33 -07:00
machine-outliner-cfi-tail-some.mir [X86] Update RET/LRET instruction to use the same naming convention as IRET (PR36876). NFC 2021-11-07 15:06:54 +00:00
machine-outliner-cfi-tail.mir [X86] Update RET/LRET instruction to use the same naming convention as IRET (PR36876). NFC 2021-11-07 15:06:54 +00:00
machine-outliner-debuginfo.ll
…
machine-outliner-disubprogram.ll
…
machine-outliner-noredzone.ll
…
machine-outliner-tailcalls.ll
…
machine-outliner.ll
…
machine-region-info.mir
…
machine-sink-and-implicit-null-checks.ll
…
machine-sink.ll
…
machine-trace-metrics-crash.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
machinesink-merge-debuginfo.ll
…
machinesink-null-debuginfo.ll
…
macho-comdat.ll
…
macho-trap.ll
…
madd.ll [X86][SSE] Improve PMADDWD SimplifyDemandedVectorElts handling 2021-11-04 12:56:31 +00:00
mangle-question-mark.ll
…
mask-negated-bool.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
masked-iv-safe.ll
…
masked-iv-unsafe.ll
…
masked_compressstore.ll
…
masked_expandload.ll [X86] Lower insertions into upper half of an 256-bit vector as broadcast+blend (PR50971) 2021-08-17 18:45:10 +03:00
masked_gather.ll [X86] Add a dependency breaking xor before any gathers with an undef passthru value. 2021-10-28 11:44:52 +08:00
masked_gather_scatter.ll [X86] combineX86GatherScatter - only fold scale if the index isn't extended 2021-10-29 11:48:05 +01:00
masked_gather_scatter_widen.ll [X86] Add a dependency breaking xor before any gathers with an undef passthru value. 2021-10-28 11:44:52 +08:00
masked_load.ll [X86] Lower insertions into upper half of an 256-bit vector as broadcast+blend (PR50971) 2021-08-17 18:45:10 +03:00
masked_store.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
masked_store_trunc.ll [X86][AVX2] Recognise 256-bit truncation shuffles and mask 256-bit source 2021-11-07 21:24:55 +00:00
masked_store_trunc_ssat.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
masked_store_trunc_usat.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
maskmovdqu.ll [X86] Fix handling of maskmovdqu in X32 2021-07-15 22:56:08 +01:00
materialize.ll
…
mature-mc-support.ll
…
mbp-false-cfg-break.ll
…
mcinst-avx-lowering.ll
…
mcinst-lowering.ll
…
mcu-abi.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
mem-intrin-base-reg.ll
…
mem-promote-integers.ll
…
membarrier.ll
…
memcmp-constant.ll
…
memcmp-mergeexpand.ll [tests] Stablize tests for possible change in deref semantics 2021-07-14 13:05:43 -07:00
memcmp-minsize-x32.ll [x86] split memcmp tests for 32/64-bit targets; NFC 2021-08-15 13:51:18 -04:00
memcmp-minsize.ll [x86] split memcmp tests for 32/64-bit targets; NFC 2021-08-15 13:51:18 -04:00
memcmp-more-load-pairs-x32.ll RegAllocGreedy: Account for reserved registers in num regs heuristic 2021-09-14 21:00:29 -04:00
memcmp-more-load-pairs.ll [x86] split memcmp tests for 32/64-bit targets; NFC 2021-08-15 13:51:18 -04:00
memcmp-optsize-x32.ll [x86] split memcmp tests for 32/64-bit targets; NFC 2021-08-15 13:51:18 -04:00
memcmp-optsize.ll [x86] split memcmp tests for 32/64-bit targets; NFC 2021-08-15 13:51:18 -04:00
memcmp-pgso-x32.ll [x86] split memcmp tests for 32/64-bit targets; NFC 2021-08-15 13:51:18 -04:00
memcmp-pgso.ll [x86] split memcmp tests for 32/64-bit targets; NFC 2021-08-15 13:51:18 -04:00
memcmp-x32.ll [x86] split memcmp tests for 32/64-bit targets; NFC 2021-08-15 13:51:18 -04:00
memcmp.ll [x86] split memcmp tests for 32/64-bit targets; NFC 2021-08-15 13:51:18 -04:00
memcpy-2.ll
…
memcpy-from-string.ll
…
memcpy-inline-fsrm.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
memcpy-inline.ll
…
memcpy-scoped-aa.ll CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
memcpy-struct-by-value.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
memcpy.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
mempcpy-32.ll
…
mempcpy.ll
…
memset-2.ll
…
memset-3.ll
…
memset-nonzero.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
memset-sse-stack-realignment.ll
…
memset-zero.ll
…
memset.ll
…
memset64-on-x86-32.ll
…
merge-consecutive-loads-128.ll
…
merge-consecutive-loads-256.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
merge-consecutive-loads-512.ll [DAG] Fold concat_vectors(concat_vectors(x,y),concat_vectors(a,b)) -> concat_vectors(x,y,a,b) 2021-08-16 16:06:54 +01:00
merge-consecutive-stores-i1.ll
…
merge-consecutive-stores-nt.ll [DAG] scalarizeExtractedVectorLoad - replace getABITypeAlign with allowsMemoryAccess (PR45116) 2021-10-01 21:07:34 +01:00
merge-consecutive-stores.ll
…
merge-sp-update-lea.ll
…
merge-sp-updates-cfi.ll
…
merge-store-constants.ll
…
merge-store-partially-alias-loads.ll CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
merge-vector-stores-scale-idx-crash.ll Revert "[NFC] remove explicit default value for strboolattr attribute in tests" 2021-05-24 19:43:40 +02:00
merge_store.ll [CGP] Support opaque pointers in address mode fold 2021-09-12 17:43:37 +02:00
merge_store_duplicated_loads.ll
…
mfence.ll
…
midpoint-int-vec-128.ll [TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation 2021-10-11 15:28:31 -07:00
midpoint-int-vec-256.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
midpoint-int-vec-512.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
midpoint-int.ll
…
min-legal-vector-width.ll [X86][SSE] LowerRotate - perform modulo on the amount splat source directly. 2021-07-25 17:30:32 +01:00
mingw-alloca.ll
…
mingw-comdats-xdata.ll
…
mingw-comdats.ll
…
mingw-refptr.ll
…
misaligned-memset.ll
…
misched-aa-colored.ll
…
misched-aa-mmos.ll
…
misched-balance.ll
…
misched-code-difference-with-debug.ll
…
misched-copy.ll Revert "[NFC] remove explicit default value for strboolattr attribute in tests" 2021-05-24 19:43:40 +02:00
misched-crash.ll
…
misched-fusion.ll
…
misched-ilp.ll
…
misched-matmul.ll Revert "[NFC] remove explicit default value for strboolattr attribute in tests" 2021-05-24 19:43:40 +02:00
misched-matrix.ll
…
misched-new.ll
…
misched_phys_reg_assign_order.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
mixed-ptr-sizes-i686.ll
…
mixed-ptr-sizes.ll
…
mmx-arg-passing-x86-64.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
mmx-arg-passing.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
mmx-arith.ll RegAllocGreedy: Account for reserved registers in num regs heuristic 2021-09-14 21:00:29 -04:00
mmx-bitcast-fold.ll
…
mmx-bitcast.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
mmx-build-vector.ll
…
mmx-coalescing.ll
…
mmx-copy-gprs.ll
…
mmx-cvt.ll
…
mmx-fold-load.ll
…
mmx-fold-zero.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
mmx-intrinsics.ll
…
mmx-only.ll
…
mov-zero-to-xor.ll
…
movbe.ll
…
movddup-load-fold.ll
…
movdir-intrinsic-x86.ll
…
movdir-intrinsic-x86_64.ll
…
move_latch_to_loop_top.ll
…
movfs.ll
…
movgs.ll
…
movmsk-cmp.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
movmsk.ll
…
movntdq-no-avx.ll
…
movpc32-check.ll Revert "[NFC] remove explicit default value for strboolattr attribute in tests" 2021-05-24 19:43:40 +02:00
movtopush-stack-align.ll reland [IR] make -stack-alignment= into a module attr 2021-06-08 10:59:46 -07:00
movtopush.ll reland [IR] make -stack-alignment= into a module attr 2021-06-08 10:59:46 -07:00
movtopush.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
movtopush64.ll
…
ms-inline-asm-PR44272.ll
…
ms-inline-asm-array.ll [X86][MS-InlineAsm][test] Add triple in ms-inline-asm-array.ll 2021-11-05 11:05:37 +08:00
ms-inline-asm-avx512.ll Revert "[NFC] remove explicit default value for strboolattr attribute in tests" 2021-05-24 19:43:40 +02:00
ms-inline-asm-redundant-clobber.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
ms-inline-asm.ll
…
mul-constant-i8.ll [TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation 2021-10-11 15:28:31 -07:00
mul-constant-i16.ll [TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation 2021-10-11 15:28:31 -07:00
mul-constant-i32.ll [TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation 2021-10-11 15:28:31 -07:00
mul-constant-i64.ll [TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation 2021-10-11 15:28:31 -07:00
mul-constant-result.ll RegAllocGreedy: Account for reserved registers in num regs heuristic 2021-09-14 21:00:29 -04:00
mul-i256.ll RegAllocGreedy: Account for reserved registers in num regs heuristic 2021-09-14 21:00:29 -04:00
mul-i512.ll RegAllocGreedy: Account for reserved registers in num regs heuristic 2021-09-14 21:00:29 -04:00
mul-i1024.ll RegAllocGreedy: Account for reserved registers in num regs heuristic 2021-09-14 21:00:29 -04:00
mul-legalize.ll
…
mul-remat.ll
…
mul-shift-reassoc.ll [LiveIntervals] Fix repairOldRegInRange for simple def cases 2021-09-24 11:44:49 +01:00
mul64.ll
…
mul128.ll [TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation 2021-10-11 15:28:31 -07:00
mul128_sext_loop.ll
…
mulfix_combine.ll
…
mulo-pow2.ll
…
muloti.ll [X86] Disable muloti4 libcalls for x86-64. 2021-09-09 10:03:15 -07:00
mult-alt-generic-i686.ll
…
mult-alt-generic-x86_64.ll
…
mult-alt-x86.ll
…
multiple-loop-post-inc.ll
…
multiple-return-values-cross-block.ll
…
mulvi32.ll
…
mulx32.ll
…
mulx64.ll
…
musttail-fastcall.ll
…
musttail-inalloca.ll
…
musttail-indirect.ll
…
musttail-tailcc.ll
…
musttail-thiscall.ll
…
musttail-varargs.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
musttail.ll
…
mwaitx.ll
…
mxcsr-reg-usage.ll
…
named-reg-alloc.ll
…
named-reg-notareg.ll
…
named-vector-shuffle-reverse.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
narrow-shl-cst.ll
…
narrow-shl-load.ll
…
narrow_op-1.ll [DAG] ReduceLoadOpStoreWidth - replace getABITypeAlign with allowsMemoryAccess (PR45116) 2021-09-25 18:35:57 +01:00
neg-abs.ll [X86] Add DAG combine for negation of CMOV absolute value pattern. 2021-10-16 13:31:43 -07:00
neg-of-3ops-lea.ll
…
neg-shl-add.ll
…
neg_cmp.ll
…
neg_fp.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
negate-add-zero.ll
…
negate-i1.ll
…
negate-shift.ll
…
negate.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
negative-offset.ll
…
negative-sin.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
negative-stride-fptosi-user.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
negative-subscript.ll
…
negative_zero.ll
…
new-remat.ll
…
newline-and-quote.ll
…
no-and8ri8.ll
…
no-cmov.ll
…
no-non-zero-debug-loc-prologue.ll Do not emit prologue_end for line 0 locs if there is a non-zero loc present 2021-10-07 13:54:28 -07:00
no-plt-libcalls.ll Revert "[BuildLibCalls/SimplifyLibCalls] Fix attributes on created CallInst instructions." 2021-06-24 19:24:34 -07:00
no-plt.ll
…
no-prolog-kill.ll
…
no-seh-unwind-inline-asm-codegen.ll Support unwinding from inline assembly 2021-05-13 19:13:03 +01:00
no-sse-win64.ll
…
no-sse-x86.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
no-sse2-avg.ll
…
no-stack-arg-probe.ll
…
no-unwind-inline-asm-codegen.ll Support unwinding from inline assembly 2021-05-13 19:13:03 +01:00
no-wide-load.ll
…
nobt.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
nocf_check.ll Revert "[NFC] remove explicit default value for strboolattr attribute in tests" 2021-05-24 19:43:40 +02:00
nocx16.ll
…
nomerge.ll
…
nomovtopush.ll
…
non-lazy-bind.ll
…
non-unique-sections.ll
…
non-value-mem-operand.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
nonconst-static-ev.ll
…
nonconst-static-iv.ll
…
nontemporal-2.ll
…
nontemporal-3.ll
…
nontemporal-loads-2.ll
…
nontemporal-loads.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
nontemporal.ll RegAllocGreedy: Account for reserved registers in num regs heuristic 2021-09-14 21:00:29 -04:00
noreturn-call-linux.ll
…
noreturn-call-win64.ll
…
noreturn-call.ll
…
norex-subreg.ll
…
nosse-error1.ll
…
nosse-varargs.ll
…
nosse-vector.ll RegAllocGreedy: Account for reserved registers in num regs heuristic 2021-09-14 21:00:29 -04:00
not-and-simplify.ll
…
not-of-dec.ll
…
note-cet-property.ll [X32][CET] Fix size and alignment of .note.gnu.property section 2021-05-01 22:17:04 +01:00
note-sections.ll
…
null-streamer.ll
…
objc-gc-module-flags.ll
…
oddshuffles.ll [x86] enhance mayFoldLoad to check alignment 2021-10-27 07:54:25 -04:00
oddsubvector.ll [X86] Split FeatureFastVariableShuffle tuning into Lane-Crossing and Per-Lane variants 2021-06-01 10:39:36 +03:00
offset-operator.ll
…
omit-urem-of-power-of-two-or-zero-when-comparing-with-zero.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
opaque-constant-asm.ll
…
opt-ext-uses.ll
…
opt-pipeline.ll [CSSPGO] Set PseudoProbeInserter as a default pass. 2021-09-22 09:09:48 -07:00
opt-shuff-tstore.ll
…
opt_phis.mir
…
opt_phis2.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
optimize-compare.mir [X86] Update RET/LRET instruction to use the same naming convention as IRET (PR36876). NFC 2021-11-07 15:06:54 +00:00
optimize-max-0.ll
…
optimize-max-1.ll
…
optimize-max-2.ll
…
optimize-max-3.ll
…
or-address.ll
…
or-branch.ll [X86] Canonicalize SGT/UGT compares with constants to use SGE/UGE to reduce the number of EFLAGs reads. (PR48760) 2021-06-30 18:46:50 +01:00
or-lea.ll
…
or-with-overflow.ll [X86] Fold cmpeq/ne(trunc(logic(x)),0) --> cmpeq/ne(logic(x),0) 2021-04-12 16:05:34 +01:00
oss-fuzz-25184.ll
…
osx-private-labels.ll MachO: don't emit L... private symbols in do_not_dead_strip sections. 2021-07-15 14:40:43 +01:00
overflow-intrinsic-optimizations.ll [X86ISelLowering] avoid emitting libcalls to __mulodi4() 2021-09-07 10:44:54 -07:00
overflow-intrinsic-setcc-fold.ll
…
overflow.ll [TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation 2021-10-11 15:28:31 -07:00
overflowing-iv-codegen.ll
…
overflowing-iv.ll
…
overlap-shift.ll
…
packed_struct.ll
…
packss.ll [DAG] FoldConstantArithmetic - fold intop(bitcast(buildvector(c1)),bitcast(buildvector(c1))) -> bitcast(intop(buildvector(c1'),buildvector(c2'))) 2021-11-11 11:35:18 +00:00
paddus.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
palignr.ll [TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation 2021-10-11 15:28:31 -07:00
parity-vec.ll [X86] Enable promotion of i16 popcnt (PR52056) 2021-10-15 15:41:37 +02:00
parity.ll [X86] Enable promotion of i16 popcnt (PR52056) 2021-10-15 15:41:37 +02:00
partial-fold32.ll
…
partial-fold64.ll
…
partial-tail-dup.ll
…
partition.ll [Verifier] Add verification logic for GlobalIFuncs 2021-10-31 20:00:57 -07:00
pass-three.ll
…
patchable-function-entry-ibt.ll
…
patchable-function-entry.ll
…
patchable-prologue.ll
…
patchpoint-invoke.ll
…
patchpoint-verifiable.mir [X86] Update RET/LRET instruction to use the same naming convention as IRET (PR36876). NFC 2021-11-07 15:06:54 +00:00
patchpoint-webkit_jscc.ll
…
patchpoint.ll
…
pause.ll
…
peep-setb.ll
…
peep-test-0.ll
…
peep-test-1.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
peep-test-2.ll
…
peep-test-3.ll
…
peep-test-4.ll
…
peep-test-5.ll X86InstrInfo: Support immediates that are +1/-1 different in optimizeCompareInstr 2021-11-03 14:12:23 -07:00
peephole-cvt-sse.ll
…
peephole-fold-movsd.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
peephole-fold-testrr.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
peephole-multiple-folds.ll
…
peephole-na-phys-copy-folding.ll RegAllocGreedy: Account for reserved registers in num regs heuristic 2021-09-14 21:00:29 -04:00
peephole-recurrence.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
peephole.mir
…
personality.ll
…
personality_size.ll
…
phaddsub-extract.ll
…
phaddsub-undef.ll
…
phaddsub.ll [TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation 2021-10-11 15:28:31 -07:00
phi-bit-propagation.ll
…
phi-immediate-factoring.ll
…
phielim-split.ll
…
phielim-undef.mir [X86] Update RET/LRET instruction to use the same naming convention as IRET (PR36876). NFC 2021-11-07 15:06:54 +00:00
phys-reg-local-regalloc.ll
…
phys_subreg_coalesce-2.ll
…
phys_subreg_coalesce-3.ll
…
phys_subreg_coalesce.ll
…
physreg-pairs-error.ll
…
physreg-pairs.ll
…
pic-load-remat.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
pic.ll
…
pic_jumptable.ll
…
pie.ll
…
pku.ll
…
pmaddubsw.ll [X86] combineMulToPMADDWD - handle any pow2 vector type and split to legal types 2021-11-09 15:20:43 +00:00
pmovext.ll
…
pmovsx-inreg.ll
…
pmul.ll [TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation 2021-10-11 15:28:31 -07:00
pmulh.ll [X86] combineMulToPMADDWD - handle any pow2 vector type and split to legal types 2021-11-09 15:20:43 +00:00
pmulld.ll
…
pointer-vector.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
poison-ops.ll
…
pop-stack-cleanup-msvc.ll
…
pop-stack-cleanup.ll [TargetLowering] Only inspect attributes in the arguments for ArgListEntry 2021-05-18 14:30:22 -07:00
popcnt.ll [X86] Enable promotion of i16 popcnt (PR52056) 2021-10-15 15:41:37 +02:00
post-ra-sched-with-debug.mir [X86] Update RET/LRET instruction to use the same naming convention as IRET (PR36876). NFC 2021-11-07 15:06:54 +00:00
post-ra-sched.ll
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postalloc-coalescing.ll X86InstrInfo: Optimize more combinations of SUB+CMP 2021-10-28 10:33:56 -07:00
postra-ignore-dbg-instrs.mir
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postra-licm.ll
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pow.75.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
pow.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
powi-windows.ll Update @llvm.powi to handle different int sizes for the exponent 2021-06-17 09:38:28 +02:00
powi.ll [TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation 2021-10-11 15:28:31 -07:00
pr1462.ll
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pr1489.ll
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pr1505.ll
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pr1505b.ll
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pr2177.ll
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pr2182.ll
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pr2326.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
pr2585.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
pr2656.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
pr2659.ll
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pr2849.ll
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pr2924.ll
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pr2982.ll
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pr3154.ll
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pr3216.ll
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pr3241.ll
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pr3243.ll
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pr3244.ll
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pr3250.ll
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pr3317.ll
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pr3366.ll
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pr3457.ll
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pr3522.ll
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pr5145.ll [X86] Canonicalize SGT/UGT compares with constants to use SGE/UGE to reduce the number of EFLAGs reads. (PR48760) 2021-06-30 18:46:50 +01:00
pr7882.ll
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pr9127.ll
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pr9517.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
pr9743.ll
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pr10068.ll
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pr10475.ll
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pr10499.ll
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pr10523.ll
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pr10524.ll
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pr10525.ll
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pr10526.ll
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pr11202.ll
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pr11334.ll
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pr11415.ll
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pr11468.ll reland [IR] make -stack-alignment= into a module attr 2021-06-08 10:59:46 -07:00
pr11985.ll
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pr11998.ll
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pr12360.ll
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pr12889.ll
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pr13209.ll
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pr13220.ll
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pr13458.ll
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pr13577.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
pr13859.ll
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pr13899.ll
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pr14088.ll
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pr14098.ll
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pr14161.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
pr14204.ll
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pr14314.ll
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pr14333.ll
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pr14562.ll
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pr15267.ll
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pr15296.ll Revert "[X86] combineX86ShuffleChain(): canonicalize mask elts picking from splats" 2021-08-05 18:58:08 +02:00
pr15309.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
pr15705.ll Revert "[NFC] remove explicit default value for strboolattr attribute in tests" 2021-05-24 19:43:40 +02:00
pr15981.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
pr16031.ll [DAG] Fold select_cc setgt X, -1, C, ~C -> xor (ashr X, BW-1), C 2021-09-05 16:04:01 +01:00
pr16360.ll
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pr16807.ll
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pr17546.ll
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pr17631.ll
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pr17764.ll
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pr18014.ll
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pr18054.ll
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pr18162.ll
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pr18344.ll
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pr18846.ll Revert "[NFC] remove explicit default value for strboolattr attribute in tests" 2021-05-24 19:43:40 +02:00
pr19049.ll
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pr20011.ll
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pr20012.ll
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pr20020.ll
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pr20088.ll
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pr21099.ll
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pr21792.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
pr22019.ll
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pr22103.ll
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pr22338.ll
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pr22473.ll
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pr22774.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
pr22970.ll
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pr23103.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
pr23246.ll
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pr23273.ll
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pr23603.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
pr23664.ll
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pr24139.ll
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pr24374.ll
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pr24602.ll
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pr25725.ll [NFC] Added testcase for PR25725 2021-09-17 15:48:55 +02:00
pr25828.ll
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pr26350.ll
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pr26625.ll
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pr26652.ll
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pr26757.ll
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pr26835.ll
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pr26870.ll
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pr27071.ll
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pr27202.ll [X86] Fold cmpeq/ne(and(X,Y),Y) --> cmpeq/ne(and(~X,Y),0) 2021-04-11 18:42:01 +01:00
pr27501.ll
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pr27591.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
pr27681.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
pr28129.ll
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pr28173.ll
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pr28444.ll
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pr28472.ll
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pr28489.ll
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pr28515.ll
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pr28560.ll
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pr28824.ll
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pr29010.ll
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pr29022.ll
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pr29061.ll
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pr29112.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
pr29170.ll
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pr29222.ll
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pr30284.ll
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pr30290.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
pr30430.ll
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pr30511.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
pr30562.ll
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pr30813.ll
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pr30821.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
pr31045.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
pr31088.ll RegAllocGreedy: Account for reserved registers in num regs heuristic 2021-09-14 21:00:29 -04:00
pr31143.ll
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pr31242.ll
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pr31271.ll
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pr31323.ll
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pr31593.ll
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pr31773.ll
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pr31956.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
pr32108.ll
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pr32241.ll
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pr32256.ll
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pr32278.ll
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pr32282.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
pr32284.ll RegAllocGreedy: Account for reserved registers in num regs heuristic 2021-09-14 21:00:29 -04:00
pr32329.ll RegAllocGreedy: Account for reserved registers in num regs heuristic 2021-09-14 21:00:29 -04:00
pr32340.ll
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pr32345.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
pr32368.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
pr32420.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
pr32451.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
pr32484.ll
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pr32515.ll
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pr32588.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
pr32610.ll RegAllocGreedy: Account for reserved registers in num regs heuristic 2021-09-14 21:00:29 -04:00
pr32659.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
pr32907.ll
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pr33010.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
pr33290.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
pr33349.ll
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pr33396.ll
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pr33715.ll
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pr33747.ll
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pr33828.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
pr33954.ll
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pr33960.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
pr34080-2.ll RegAllocGreedy: Account for reserved registers in num regs heuristic 2021-09-14 21:00:29 -04:00
pr34080.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
pr34088.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
pr34137.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
pr34139.ll
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pr34149.ll
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pr34177.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
pr34271-1.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
pr34271.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
pr34292.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
pr34381.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
pr34397.ll
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pr34421.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
pr34592.ll [DAG] DAGCombiner::visitVECTOR_SHUFFLE - recognise INSERT_SUBVECTOR patterns 2021-08-05 15:40:48 +01:00
pr34605.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
pr34629.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
pr34634.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
pr34653.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
pr34657.ll
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pr34855.ll
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pr35272.ll
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pr35316.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
pr35399.ll
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pr35443.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
pr35636.ll
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pr35761.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
pr35763.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
pr35765.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
pr35918.ll
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pr35972.ll
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pr35982.ll [DAG] CombineConsecutiveLoads - replace getABITypeAlign with allowsMemoryAccess (PR45116) 2021-08-24 12:31:22 +01:00
pr36199.ll
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pr36274.ll
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pr36312.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
pr36553.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
pr36602.ll
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pr36865.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
pr37025.ll [X86] Add PR37025 test coverage 2021-07-27 12:09:25 +01:00
pr37063.ll
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pr37264.ll
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pr37359.ll
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pr37499.ll
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pr37820.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
pr37826.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
pr37879.ll
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pr37916.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
pr38038.ll
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pr38185.ll
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pr38217.ll
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pr38533.ll
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pr38539.ll
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pr38639.ll
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pr38738.ll
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pr38743.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
pr38762.ll
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pr38763.ll
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pr38795.ll
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pr38803.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
pr38819.ll
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pr38865-2.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
pr38865-3.ll
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pr38865.ll
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pr38952.mir
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pr39098.ll
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pr39243.ll
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pr39666.ll
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pr39733.ll
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pr39896.ll
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pr39926.ll
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pr40090.ll
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pr40289-64bit.ll
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pr40289.ll
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pr40529.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
pr40539.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
pr40631_deadstore_elision.ll
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pr40730.ll
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pr40737.ll
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pr40811.ll
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pr40891.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
pr40994.ll
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pr41619.ll Fix the default alignment of i1 vectors. 2021-07-31 14:09:59 -07:00
pr41678.ll
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pr41748.ll
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pr42064.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
pr42452.ll
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pr42565.ll
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pr42616.ll
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pr42727.ll Revert "[NFC] remove explicit default value for strboolattr attribute in tests" 2021-05-24 19:43:40 +02:00
pr42870.ll
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pr42905.ll
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pr42909.ll
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pr42992.ll
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pr42998.ll [TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation 2021-10-11 15:28:31 -07:00
pr43157.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
pr43507.ll
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pr43509.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
pr43529.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
pr43575.ll
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pr43820.ll [SelectionDAG] Optimize bitreverse expansion to minimize the number of mask constants. 2021-08-26 09:33:24 -07:00
pr43866.ll
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pr43952.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
pr44140.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
pr44396.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
pr44412.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
pr44749.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
pr44812.ll
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pr44976.ll
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pr45067.ll [X86] Add a dependency breaking xor before any gathers with an undef passthru value. 2021-10-28 11:44:52 +08:00
pr45378.ll
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pr45443.ll
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pr45563-2.ll
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pr45563.ll
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pr45833.ll
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pr45995-2.ll [X86] Canonicalize SGT/UGT compares with constants to use SGE/UGE to reduce the number of EFLAGs reads. (PR48760) 2021-06-30 18:46:50 +01:00
pr45995.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
pr46004.ll
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pr46189.ll
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pr46315.ll [X86] Add PR46315 test case 2021-08-16 13:13:56 +01:00
pr46455.ll
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pr46527.ll RegAllocGreedy: Account for reserved registers in num regs heuristic 2021-09-14 21:00:29 -04:00
pr46532.ll
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pr46585.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
pr46820.ll
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pr46827.ll CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
pr46877.ll
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pr47000.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
pr47024.ll
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pr47299.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
pr47482.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
pr47517.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
pr47874.ll
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pr48064.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
pr48215.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
pr48458.ll
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pr48727.ll
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pr48888.ll
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pr49028.ll [X86] combineCMP - fold cmpEQ/NE(TRUNC(X),0) -> cmpEQ/NE(X,0) 2021-04-15 13:55:51 +01:00
pr49076.ll
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pr49087.ll
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pr49162.ll
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pr49393.ll
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pr49451.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
pr49466.ll
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pr49467.ll
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pr49587.ll
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pr50254.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
pr50374.ll [X86][SSE] combineScalarToVector - only reuse broadcasts for scalar_to_vector if the source operands scalar types match 2021-06-02 22:05:40 +01:00
pr50431.ll [X86] Call insertDAGNode on trunc/zext created in tryShiftAmountMod. 2021-05-24 10:23:22 -07:00
pr50609.ll [DAG] foldShuffleOfConcatUndefs - ensure shuffles of upper (undef) subvector elements is undef (PR50609) 2021-06-08 15:49:41 +01:00
pr50709.ll [X86] Use EVT::getVectorVT instead of changeVectorElementType in reduceVMULWidth. 2021-06-14 22:07:04 -07:00
pr50782.ll [X86] Teach X86FloatingPoint's handleCall to only erase the FP stack if there is a regmask operand that clobbers the FP stack. 2021-07-12 10:15:38 -07:00
pr50823.ll [X86] Twist shuffle mask when fold HOP(SHUFFLE(X,Y),SHUFFLE(X,Y)) -> SHUFFLE(HOP(X,Y)) 2021-07-05 21:29:42 +08:00
pr50907.ll [X86] Tighten up some inline assembly constraint handling. 2021-06-26 22:57:22 -07:00
pr51175.ll [X86] Fix a bug in TEST with immediate creation 2021-07-23 09:03:53 -07:00
pr51281.ll [X86][AVX] Extract SUBV_BROADCAST constant bits from just the lower subvector range (PR51281) 2021-08-06 11:21:31 +01:00
pr51371.ll [X86] Teach shouldSinkOperands to recognize pmuldq/pmuludq patterns. 2021-08-07 08:45:56 -07:00
pr51615.ll [Codegen][X86] EltsFromConsecutiveLoads(): if only have AVX1, ensure that the "load" is actually foldable (PR51615) 2021-08-27 20:26:53 +03:00
pr51878_computeAliasing.ll [SelectionDAG] Assume that a GlobalAlias may alias other global values 2021-10-05 12:15:55 +02:00
pr51903.mir Recommit "[X86] Clear kill flags when rewriting SETCC uses in flag copy lowering." 2021-09-21 14:59:25 -07:00
pre-coalesce-2.ll
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pre-coalesce.ll
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pre-coalesce.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
pre-ra-sched.ll
…
preallocated-nocall.ll
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preallocated-x64.ll
…
preallocated.ll [TargetLowering] Only inspect attributes in the arguments for ArgListEntry 2021-05-18 14:30:22 -07:00
prefer-avx256-lzcnt.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
prefer-avx256-mask-extend.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
prefer-avx256-mask-shuffle.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
prefer-avx256-mulo.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
prefer-avx256-popcnt.ll
…
prefer-avx256-shift.ll [X86][SSE] Regenerate vector shift codegen tests. NFCI. 2021-05-25 15:58:22 +01:00
prefer-avx256-trunc.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
prefer-avx256-wide-mul.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
prefetch.ll
…
prefixdata.ll
…
preserve_allcc64.ll
…
preserve_mostcc64.ll
…
private-2.ll
…
private.ll
…
probe-stack-x32.ll
…
prolog-push-seq.ll
…
prologepilog_deref_size.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
prologue-epilogue-remarks.mir [X86] Update RET/LRET instruction to use the same naming convention as IRET (PR36876). NFC 2021-11-07 15:06:54 +00:00
prologuedata.ll
…
promote-assert-zext.ll
…
promote-cmp.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
promote-i16.ll
…
promote-trunc.ll
…
promote-vec3.ll
…
promote.ll
…
ps4-noreturn.ll
…
ps4-ssp-nop.ll
…
psadbw.ll [X86] SimplifyDemandedVectorEltsForTargetNode - add PSADBW handling 2021-09-16 11:28:31 +01:00
pseudo_cmov_lower-fp16.ll [X86] AVX512FP16 instructions enabling 2/6 2021-08-15 08:56:33 +08:00
pseudo_cmov_lower.ll
…
pseudo_cmov_lower1.ll
…
pseudo_cmov_lower2.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
pshufb-mask-comments.ll
…
pshufd-combine-crash.ll
…
psubus.ll [DAGCombiner] make matching bit-hack form of usubsat more flexible 2021-10-25 09:01:52 -04:00
ptest.ll
…
ptr-rotate.ll
…
ptrtoint-constexpr.ll
…
ptrtoint-narrow.ll
…
ptwrite32-intrinsic.ll
…
ptwrite64-intrinsic.ll
…
pull-binop-through-shift.ll
…
pull-conditional-binop-through-shift.ll
…
push-cfi-debug.ll
…
push-cfi-obj.ll
…
push-cfi.ll
…
ragreedy-bug.ll
…
ragreedy-hoist-spill.ll Revert "Allow rematerialization of virtual reg uses" 2021-09-24 10:26:11 -07:00
ragreedy-last-chance-recoloring.ll Revert "[NFC] remove explicit default value for strboolattr attribute in tests" 2021-05-24 19:43:40 +02:00
rd-mod-wr-eflags.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
rdpid.ll
…
rdpmc.ll
…
rdrand-x86_64.ll
…
rdrand.ll
…
rdseed-x86_64.ll
…
rdseed.ll
…
rdtsc-upgrade.ll
…
rdtsc.ll
…
read-fp-no-frame-pointer.ll
…
recip-fastmath.ll [TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation 2021-10-11 15:28:31 -07:00
recip-fastmath2.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
recip-pic.ll
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red-zone.ll
…
red-zone2.ll
…
reduce-trunc-shl.ll
…
regalloc-advanced-split-cost.ll Revert "[NFC] remove explicit default value for strboolattr attribute in tests" 2021-05-24 19:43:40 +02:00
regalloc-copy-hints.mir
…
regalloc-fast-missing-live-out-spill.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
regalloc-reconcile-broken-hints.ll
…
regalloc-spill-at-ehpad.ll
…
regalloc-tight-invoke.ll MachineBasicBlock: add liveout iterator aware of which liveins are defined by the runtime. 2021-05-19 11:00:24 +01:00
regcall-no-plt.ll
…
reghinting.ll
…
regparm.ll Revert "[NFC] remove explicit default value for strboolattr attribute in tests" 2021-05-24 19:43:40 +02:00
regpressure.ll
…
relocimm-small-model.ll
…
relptr-rodata.ll
…
rem.ll
…
rem_crash.ll
…
remarks-section.ll
…
remat-constant.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
remat-fold-load.ll
…
remat-mov-0.ll
…
remat-phys-dead.ll
…
remat-scalar-zero.ll
…
replace-load-and-with-bzhi.ll
…
replace_unsupported_masked_mem_intrin.ll
…
ret-addr.ll
…
ret-i64-0.ll
…
ret-mmx.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
retpoline-external.ll
…
retpoline-regparm.ll
…
retpoline.ll
…
return-ext.ll
…
return_zeroext_i2.ll
…
returned-trunc-tail-calls.ll
…
rev16.ll [TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation 2021-10-11 15:28:31 -07:00
reverse_branches.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
rip-rel-address.ll
…
rip-rel-lea.ll
…
rodata-relocs.ll
…
rot16.ll [TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation 2021-10-11 15:28:31 -07:00
rot32.ll
…
rot64.ll
…
rotate-extract-vector.ll [CodeGen][regalloc] Don't align stack slots if the stack can't be realigned 2021-06-11 16:49:12 +01:00
rotate-extract.ll [TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation 2021-10-11 15:28:31 -07:00
rotate-multi.ll [TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation 2021-10-11 15:28:31 -07:00
rotate.ll
…
rotate2.ll
…
rotate4.ll
…
rotate_vec.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
rounding-ops.ll
…
rrlist-livereg-corrutpion.ll
…
rtm.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
sad.ll [X86] SimplifyDemandedVectorEltsForTargetNode - add PSADBW handling 2021-09-16 11:28:31 +01:00
sad_variations.ll [X86] SimplifyDemandedVectorEltsForTargetNode - add PSADBW handling 2021-09-16 11:28:31 +01:00
sadd_sat.ll RegAllocGreedy: Account for reserved registers in num regs heuristic 2021-09-14 21:00:29 -04:00
sadd_sat_plus.ll [TwoAddressInstructionPass] Put all new instructions into DistanceMap 2021-10-28 11:11:59 -07:00
sadd_sat_vec.ll [TwoAddressInstructionPass] Put all new instructions into DistanceMap 2021-10-28 11:11:59 -07:00
saddo-redundant-add.ll
…
safestack.ll
…
safestack_inline.ll
…
safestack_ssp.ll
…
sandybridge-loads.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
sar_fold.ll
…
sar_fold64.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
sat-add.ll [TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation 2021-10-11 15:28:31 -07:00
sbb.ll
…
scalar-extract.ll
…
scalar-fp-to-i32.ll [X86] Implement smarter instruction lowering for FP_TO_UINT from f32/f64 to i32/i64 and vXf32/vXf64 to vXi32 for SSE2 and AVX2 by using the exact semantic of the CVTTPS2SI instruction. 2021-07-14 12:03:49 +01:00
scalar-fp-to-i64.ll [X86] Implement smarter instruction lowering for FP_TO_UINT from f32/f64 to i32/i64 and vXf32/vXf64 to vXi32 for SSE2 and AVX2 by using the exact semantic of the CVTTPS2SI instruction. 2021-07-14 12:03:49 +01:00
scalar-int-to-fp.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
scalar-min-max-fill-operand.ll
…
scalar_sse_minmax.ll
…
scalar_widen_div.ll
…
scalarize-bitcast.ll
…
scalarize-fp.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
scatter-schedule.ll
…
scavenger.mir [X86] Update RET/LRET instruction to use the same naming convention as IRET (PR36876). NFC 2021-11-07 15:06:54 +00:00
scev-interchange.ll
…
scheduler-backtracking.ll RegAllocGreedy: Account for reserved registers in num regs heuristic 2021-09-14 21:00:29 -04:00
sdiv-exact.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
sdiv-pow2.ll
…
sdiv_fix.ll [TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation 2021-10-11 15:28:31 -07:00
sdiv_fix_sat.ll RegAllocGreedy: Account for reserved registers in num regs heuristic 2021-09-14 21:00:29 -04:00
section_mergeable_size.ll
…
segmented-stacks-dynamic.ll
…
segmented-stacks-standalone.ll
…
segmented-stacks.ll
…
seh-catch-all-win32.ll
…
seh-catch-all.ll
…
seh-catchpad.ll Fix SEH table addresses for Windows 2021-08-20 22:32:12 +03:00
seh-except-finally.ll Fix SEH table addresses for Windows 2021-08-20 22:32:12 +03:00
seh-except-restore.ll
…
seh-exception-code.ll
…
seh-filter-no-personality.ll
…
seh-finally.ll Fix SEH table addresses for Windows 2021-08-20 22:32:12 +03:00
seh-localaddress.ll
…
seh-no-invokes.ll Revert "[NFC] remove explicit default value for strboolattr attribute in tests" 2021-05-24 19:43:40 +02:00
seh-safe-div-win32.ll
…
seh-safe-div.ll Fix SEH table addresses for Windows 2021-08-20 22:32:12 +03:00
seh-stack-realign.ll
…
seh-unwind-inline-asm-codegen.ll Support unwinding from inline assembly 2021-05-13 19:13:03 +01:00
select-1-or-neg1.ll
…
select-constant-xor.ll [TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation 2021-10-11 15:28:31 -07:00
select-ext.ll
…
select-mmx.ll
…
select-of-fp-constants.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
select-of-half-constants.ll [X86] Modify the commuted load isel pattern for VCMPSHZrm to match VCMPSSZrm/VCMPSDZrm. 2021-08-15 11:43:56 -07:00
select-prof-codegen.ll
…
select-sra.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
select-testb-volatile-load.ll
…
select-with-and-or.ll
…
select.ll [TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation 2021-10-11 15:28:31 -07:00
select_const.ll [X86] Canonicalize SGT/UGT compares with constants to use SGE/UGE to reduce the number of EFLAGs reads. (PR48760) 2021-06-30 18:46:50 +01:00
select_meta.ll Remove "Rewrite Symbols" from codegen pipeline 2021-05-31 08:32:36 -07:00
selectcc-to-shiftand.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
selectiondag-crash.ll
…
selectiondag-cse.ll
…
selectiondag-debug-loc.ll [llvm] Inclusive language: replace master with main in file paths in LIT tests 2021-11-08 12:39:50 -06:00
selectiondag-dominator.ll
…
selectiondag-order.ll
…
semantic-interposition-asm.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
serialize-intrinsic.ll
…
setcc-combine.ll
…
setcc-freeze.ll [DAGCombiner] Fold SETCC(FREEZE(x),const) to FREEZE(SETCC(x,const)) if SETCC is used by BRCOND 2021-07-28 09:22:15 +09:00
setcc-logic.ll [X86] Canonicalize SGT/UGT compares with constants to use SGE/UGE to reduce the number of EFLAGs reads. (PR48760) 2021-06-30 18:46:50 +01:00
setcc-lowering.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
setcc-narrowing.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
setcc-wide-types.ll RegAllocGreedy: Account for reserved registers in num regs heuristic 2021-09-14 21:00:29 -04:00
setcc.ll [X86] Canonicalize SGT/UGT compares with constants to use SGE/UGE to reduce the number of EFLAGs reads. (PR48760) 2021-06-30 18:46:50 +01:00
setjmp-spills.ll
…
setoeq.ll
…
setuge.ll
…
sext-i1.ll
…
sext-load.ll
…
sext-ret-val.ll
…
sext-setcc-self.ll
…
sext-subreg.ll
…
sext-trunc.ll
…
sext-vsetcc.ll [CodeGen][regalloc] Don't align stack slots if the stack can't be realigned 2021-06-11 16:49:12 +01:00
sha.ll
…
shadow-stack.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
shift-amount-mod.ll
…
shift-and-x86_64.ll
…
shift-and.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
shift-avx2-crash.ll
…
shift-bmi2.ll
…
shift-by-signext.ll
…
shift-coalesce.ll
…
shift-codegen.ll
…
shift-combine-crash.ll
…
shift-combine.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
shift-double-x86_64.ll
…
shift-double.ll
…
shift-folding.ll
…
shift-i128.ll
…
shift-i256.ll
…
shift-logic.ll [TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation 2021-10-11 15:28:31 -07:00
shift-mask.ll
…
shift-one.ll
…
shift-pair.ll
…
shift-parts.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
shift-pcmp.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
shift_minsize.ll [SelectionDAG] Fix shift libcall ABI mismatch in shift-amount argument 2021-10-08 09:57:57 +08:00
shl-anyext.ll
…
shl-crash-on-legalize.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
shl-i64.ll
…
shl_elim.ll
…
shl_undef.ll
…
shrink-compare-pgso.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
shrink-compare.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
shrink-const.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
shrink-fp-const1.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
shrink-fp-const2.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
shrink-wrap-chkstk-x86_64.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
shrink-wrap-chkstk.ll
…
shrink-wrapping-vla.ll
…
shrink_vmul.ll [X86] combineMulToPMADDWD - handle any pow2 vector type and split to legal types 2021-11-09 15:20:43 +00:00
shrink_vmul_sse.ll
…
shrink_wrap_dbg_value.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
shrinkwrap-callbr.ll
…
shrinkwrap-hang.ll Revert "[NFC] remove explicit default value for strboolattr attribute in tests" 2021-05-24 19:43:40 +02:00
shuffle-combine-crash-2.ll
…
shuffle-combine-crash-3.ll
…
shuffle-combine-crash.ll
…
shuffle-extract-subvector.ll
…
shuffle-of-insert.ll
…
shuffle-of-splat-multiuses.ll [X86] Split FeatureFastVariableShuffle tuning into Lane-Crossing and Per-Lane variants 2021-06-01 10:39:36 +03:00
shuffle-strided-with-offset-128.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
shuffle-strided-with-offset-256.ll [X86] Split FeatureFastVariableShuffle tuning into Lane-Crossing and Per-Lane variants 2021-06-01 10:39:36 +03:00
shuffle-strided-with-offset-512.ll [X86] Split FeatureFastVariableShuffle tuning into Lane-Crossing and Per-Lane variants 2021-06-01 10:39:36 +03:00
shuffle-vs-trunc-128.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
shuffle-vs-trunc-256.ll [X86][AVX2] Recognise 256-bit truncation shuffles and mask 256-bit source 2021-11-07 21:24:55 +00:00
shuffle-vs-trunc-512.ll [X86] Split FeatureFastVariableShuffle tuning into Lane-Crossing and Per-Lane variants 2021-06-01 10:39:36 +03:00
sibcall-2.ll
…
sibcall-3.ll
…
sibcall-4.ll
…
sibcall-5.ll
…
sibcall-6.ll
…
sibcall-byval.ll
…
sibcall-win64.ll
…
sibcall.ll [X86] pr51000 in-register struct return tailcalling 2021-08-25 10:15:50 -07:00
signbit-shift.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
signed-truncation-check.ll
…
simple-register-allocation-read-undef.mir
…
simple-zext.ll
…
sincos-opt.ll
…
sincos.ll
…
sink-addsub-of-const.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
sink-blockfreq.ll
…
sink-gep-before-mem-inst.ll
…
sink-hoist.ll
…
sink-local-value.ll
…
sink-out-of-loop.ll
…
sitofp.ll
…
sjlj-baseptr.ll
…
sjlj-eh-musttail.ll [SjLj] Insert UnregisterFn before musttail call 2021-06-23 15:33:55 -07:00
sjlj-eh.ll
…
sjlj-shadow-stack-liveness.mir
…
sjlj-unwind-inline-asm-codegen.ll Don't run MachineVerifier on sjlj-unwind-inline-asm test because of known issue (PR39439) 2021-05-13 23:14:05 +01:00
sjlj.ll
…
slow-incdec.ll
…
slow-pmulld.ll [X86] combineMulToPMADDWD - handle any pow2 vector type and split to legal types 2021-11-09 15:20:43 +00:00
slow-unaligned-mem.ll [X86] AMD Zen 3 Scheduler Model 2021-05-01 22:08:13 +03:00
small-byval-memcpy.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
smax.ll [TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation 2021-10-11 15:28:31 -07:00
smin.ll [TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation 2021-10-11 15:28:31 -07:00
smul-with-overflow.ll
…
smul_fix.ll RegAllocGreedy: Account for reserved registers in num regs heuristic 2021-09-14 21:00:29 -04:00
smul_fix_sat.ll [TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation 2021-10-11 15:28:31 -07:00
smul_fix_sat_constants.ll [SelectionDAG] Fix miscompile bugs related to smul.fix.sat with scale zero 2021-08-30 22:08:26 +02:00
smulo-128-legalisation-lowering.ll RegAllocGreedy: Account for reserved registers in num regs heuristic 2021-09-14 21:00:29 -04:00
soft-fp-legal-in-HW-reg.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
soft-fp.ll
…
soft-sitofp.ll
…
speculative-execution-side-effect-suppression.ll
…
speculative-load-hardening-call-and-ret.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
speculative-load-hardening-gather.ll
…
speculative-load-hardening-indirect.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
speculative-load-hardening-no-spill.ll
…
speculative-load-hardening.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
splat-const.ll
…
splat-for-size.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
split-eh-lpad-edges.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
split-extend-vector-inreg.ll
…
split-store.ll
…
split-vector-bitcast.ll
…
split-vector-rem.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
sqrt-fastmath-mir.ll CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
sqrt-fastmath-tune.ll [TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation 2021-10-11 15:28:31 -07:00
sqrt-fastmath.ll [TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation 2021-10-11 15:28:31 -07:00
sqrt-partial.ll
…
sqrt.ll
…
srem-lkk.ll
…
srem-seteq-illegal-types.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
srem-seteq-optsize.ll
…
srem-seteq-vec-nonsplat.ll [TLI] prepareSREMEqFold(): use correct VT for the final VSELECT (PR51133) 2021-07-19 16:44:00 +03:00
srem-seteq-vec-splat.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
srem-seteq.ll [X86] Canonicalize SGT/UGT compares with constants to use SGE/UGE to reduce the number of EFLAGs reads. (PR48760) 2021-06-30 18:46:50 +01:00
srem-vector-lkk.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
sret-implicit.ll
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sse-align-0.ll
…
sse-align-1.ll
…
sse-align-2.ll
…
sse-align-3.ll
…
sse-align-4.ll
…
sse-align-5.ll
…
sse-align-6.ll
…
sse-align-7.ll
…
sse-align-8.ll
…
sse-align-9.ll
…
sse-align-10.ll
…
sse-align-11.ll
…
sse-align-12.ll
…
sse-commute.ll
…
sse-cvttp2si.ll Revert "[NFC] remove explicit default value for strboolattr attribute in tests" 2021-05-24 19:43:40 +02:00
sse-domains.ll [X86][SSE] Regenerate some tests to expose the rip relative vector/broadcast loads 2021-05-26 14:50:47 +01:00
sse-fcopysign.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
sse-fsignum.ll
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sse-insertelt-from-mem.ll [NFC][Codegen][X86] Improve test coverage for insertions into XMM vector 2021-07-25 21:08:03 +03:00
sse-insertelt.ll [NFC][Codegen][X86] Improve test coverage for insertions into XMM vector 2021-07-25 21:08:03 +03:00
sse-intel-ocl.ll
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sse-intrinsics-fast-isel-x86_64.ll
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sse-intrinsics-fast-isel.ll RegAllocGreedy: Account for reserved registers in num regs heuristic 2021-09-14 21:00:29 -04:00
sse-intrinsics-x86-upgrade.ll
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sse-intrinsics-x86.ll
…
sse-intrinsics-x86_64-upgrade.ll
…
sse-intrinsics-x86_64.ll
…
sse-load-ret.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
sse-minmax.ll [TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation 2021-10-11 15:28:31 -07:00
sse-only.ll
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sse-regcall.ll
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sse-scalar-fp-arith-unary.ll
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sse-scalar-fp-arith.ll
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sse-unaligned-mem-feature.ll
…
sse-varargs.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
sse1-fcopysign.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
sse1.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
sse2-intrinsics-canonical.ll
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sse2-intrinsics-fast-isel-x86_64.ll
…
sse2-intrinsics-fast-isel.ll RegAllocGreedy: Account for reserved registers in num regs heuristic 2021-09-14 21:00:29 -04:00
sse2-intrinsics-x86-upgrade.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
sse2-intrinsics-x86.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
sse2-intrinsics-x86_64-upgrade.ll
…
sse2-intrinsics-x86_64.ll
…
sse2-vector-shifts.ll [X86][SSE] Regenerate some tests to expose the rip relative vector/broadcast loads 2021-05-26 14:50:47 +01:00
sse2.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
sse3-avx-addsub-2.ll
…
sse3-avx-addsub.ll
…
sse3-intrinsics-fast-isel.ll
…
sse3-intrinsics-x86.ll
…
sse3.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
sse4a-intrinsics-fast-isel.ll
…
sse4a-upgrade.ll
…
sse4a.ll
…
sse41-intrinsics-fast-isel.ll
…
sse41-intrinsics-x86-upgrade.ll
…
sse41-intrinsics-x86.ll [X86] Remove Commutable flag from mpsadbw intrinsics. 2021-09-19 13:22:22 -07:00
sse41-pmovxrm.ll
…
sse41.ll [X86][TLI] SimplifyDemandedVectorEltsForTargetNode(): don't break apart broadcasts from which not just the 0'th elt is demanded 2021-09-19 17:38:32 +03:00
sse42-intrinsics-fast-isel.ll [X86] Add CRC32 feature. 2021-09-06 17:24:30 +08:00
sse42-intrinsics-x86.ll [X86] Add CRC32 feature. 2021-09-06 17:24:30 +08:00
sse_partial_update.ll
…
sse_reload_fold.ll
…
sshl_sat.ll [TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation 2021-10-11 15:28:31 -07:00
sshl_sat_vec.ll RegAllocGreedy: Account for reserved registers in num regs heuristic 2021-09-14 21:00:29 -04:00
ssp-data-layout.ll
…
ssp-guard-spill.ll
…
ssse3-intrinsics-fast-isel.ll
…
ssse3-intrinsics-x86-upgrade.ll
…
ssse3-intrinsics-x86.ll
…
ssub_sat.ll [TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation 2021-10-11 15:28:31 -07:00
ssub_sat_plus.ll [ISel] Expand saddsat and ssubsat via asr and xor 2021-08-19 16:08:07 +01:00
ssub_sat_vec.ll [TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation 2021-10-11 15:28:31 -07:00
stack-align-memcpy.ll RegAllocGreedy: Account for reserved registers in num regs heuristic 2021-09-14 21:00:29 -04:00
stack-align.ll
…
stack-align2.ll Default stack alignment of x86 NaCl to 16 bytes 2021-05-18 15:16:59 -07:00
stack-clash-dynamic-alloca.ll
…
stack-clash-large-large-align.ll
…
stack-clash-large.ll [X86] Don't clobber EBX in stackprobes 2021-09-07 15:00:44 -04:00
stack-clash-medium-natural-probes-mutliple-objects.ll
…
stack-clash-medium-natural-probes.ll
…
stack-clash-medium.ll
…
stack-clash-small-alloc-medium-align.ll
…
stack-clash-small-large-align.ll
…
stack-clash-small.ll
…
stack-clash-unknown-call.ll
…
stack-folding-3dnow.ll
…
stack-folding-adx-x86_64.ll
…
stack-folding-adx.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
stack-folding-avx512bf16.ll
…
stack-folding-avx512vp2intersect.ll
…
stack-folding-bmi.ll
…
stack-folding-bmi2.ll
…
stack-folding-bmi2.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
stack-folding-fp-avx1.ll Revert "[NFC] remove explicit default value for strboolattr attribute in tests" 2021-05-24 19:43:40 +02:00
stack-folding-fp-avx512.ll [TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation 2021-10-11 15:28:31 -07:00
stack-folding-fp-avx512fp16-fma.ll [X86] AVX512FP16 instructions enabling 5/6 2021-08-24 09:07:19 +08:00
stack-folding-fp-avx512fp16.ll [X86][FP16] Change the order of the operands in complex FMA intrinsics to allow swap between the mul operands. 2021-09-23 11:02:48 +08:00
stack-folding-fp-avx512fp16vl-fma.ll [X86] AVX512FP16 instructions enabling 5/6 2021-08-24 09:07:19 +08:00
stack-folding-fp-avx512fp16vl.ll [X86][FP16] Change the order of the operands in complex FMA intrinsics to allow swap between the mul operands. 2021-09-23 11:02:48 +08:00
stack-folding-fp-avx512vl.ll Revert "[NFC] remove explicit default value for strboolattr attribute in tests" 2021-05-24 19:43:40 +02:00
stack-folding-fp-nofpexcept.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
stack-folding-fp-sse42.ll Revert "[NFC] remove explicit default value for strboolattr attribute in tests" 2021-05-24 19:43:40 +02:00
stack-folding-int-avx1.ll
…
stack-folding-int-avx2.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
stack-folding-int-avx512.ll [TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation 2021-10-11 15:28:31 -07:00
stack-folding-int-avx512vl.ll
…
stack-folding-int-avx512vnni.ll
…
stack-folding-int-avxvnni.ll
…
stack-folding-int-sse42.ll [X86] Add CRC32 feature. 2021-09-06 17:24:30 +08:00
stack-folding-lwp.ll
…
stack-folding-mmx.ll
…
stack-folding-sha.ll
…
stack-folding-tbm.ll
…
stack-folding-x86_64.ll
…
stack-folding-xop.ll
…
stack-guard-memloc-vararg.ll
…
stack-guard-oob.ll
…
stack-probe-red-zone.ll
…
stack-probe-size.ll
…
stack-probes.ll
…
stack-protector-2.ll
…
stack-protector-3.ll fix up test from D102742 2021-05-24 12:09:02 -07:00
stack-protector-dbginfo.ll
…
stack-protector-msvc.ll
…
stack-protector-remarks.ll
…
stack-protector-strong-macho-win32-xor.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
stack-protector-target.ll
…
stack-protector-vreg-to-vreg-copy.ll Revert "[NFC] remove explicit default value for strboolattr attribute in tests" 2021-05-24 19:43:40 +02:00
stack-protector-weight.ll CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
stack-protector.ll
…
stack-size-section-function-sections.ll
…
stack-size-section.ll
…
stack-update-frame-opcode.ll
…
stack_guard_remat.ll Revert "[NFC] remove explicit default value for strboolattr attribute in tests" 2021-05-24 19:43:40 +02:00
stackguard-internal.ll
…
stackmap-fast-isel.ll
…
stackmap-frame-setup.ll
…
stackmap-large-constants.ll
…
stackmap-large-location-size.ll
…
stackmap-liveness.ll
…
stackmap-nops.ll
…
stackmap-shadow-optimization.ll
…
stackmap.ll
…
stackpointer.ll
…
statepoint-allocas.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
statepoint-call-lowering.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
statepoint-deopt-lowering.ll
…
statepoint-duplicates-export.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
statepoint-far-call.ll
…
statepoint-fastregalloc.mir [RegAllocFast] properly handle STATEPOINT instruction. 2021-05-11 17:27:00 +07:00
statepoint-fixup-call.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
statepoint-fixup-copy-prop-neg.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
statepoint-fixup-invoke.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
statepoint-fixup-shared-ehpad.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
statepoint-fixup-undef-def.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
statepoint-fixup-undef.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
statepoint-forward.ll
…
statepoint-gc-live.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
statepoint-gctransition-call-lowering.ll
…
statepoint-invoke-ra-enter-at-end.mir [X86] AVX512FP16 instructions enabling 1/6 2021-08-10 12:46:01 +08:00
statepoint-invoke-ra-hoist-copies.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
statepoint-invoke-ra-inline-spiller.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
statepoint-invoke-ra-remove-back-copies.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
statepoint-invoke-ra.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
statepoint-invoke.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
statepoint-live-in-remat.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
statepoint-live-in.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
statepoint-no-extra-const.ll
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statepoint-no-realign-stack.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
statepoint-ra-no-ls.ll
…
statepoint-ra.ll CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
statepoint-regs.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
statepoint-spill-lowering.ll
…
statepoint-spill-slot-size-promotion.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
statepoint-stack-usage.ll
…
statepoint-stackmap-format.ll
…
statepoint-stackmap-size.ll
…
statepoint-two-results.ll
…
statepoint-uniqueing.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
statepoint-vector-bad-spill.ll
…
statepoint-vector.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
statepoint-vreg-details.ll CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
statepoint-vreg-folding.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
statepoint-vreg-invoke.ll CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
statepoint-vreg-unlimited-tied-opnds.ll RegAllocGreedy: Account for reserved registers in num regs heuristic 2021-09-14 21:00:29 -04:00
statepoint-vreg.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
statepoint-vreg.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
stdarg.ll
…
stdcall-notailcall.ll
…
stdcall.ll [Mangler] Calculate the argument list byte count suffix correctly when returning large values 2021-09-29 11:42:28 -07:00
store-empty-member.ll
…
store-fp-constant.ll
…
store-global-address.ll
…
store-narrow.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
store-zero-and-minus-one.ll
…
store_op_load_fold.ll [X86] Regenerate store_op_load_fold.ll test checks 2021-08-19 12:42:09 +01:00
store_op_load_fold2.ll
…
stores-merging.ll [SDAG] fix miscompile from merging stores of different sizes 2021-06-09 09:51:39 -04:00
storetrunc-fp.ll
…
strict-fadd-combines.ll [X86] Add tests from D93707 for fsub_strict(x,fneg(y)) -> fadd_strict(x,y) folds. 2021-07-10 15:08:58 +01:00
strict-fsub-combines.ll [X86] Add tests from D93707 for fsub_strict(x,fneg(y)) -> fadd_strict(x,y) folds. 2021-07-10 15:08:58 +01:00
stride-nine-with-base-reg.ll
…
stride-reuse.ll
…
sttni.ll
…
sub-of-bias.ll
…
sub-of-not.ll
…
sub-with-overflow.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
sub.ll
…
subcarry.ll
…
subreg-to-reg-0.ll
…
subreg-to-reg-1.ll
…
subreg-to-reg-2.ll
…
subreg-to-reg-3.ll
…
subreg-to-reg-4.ll
…
subreg-to-reg-6.ll
…
subvector-broadcast.ll [X86][AVX] Add PR51226 test case 2021-11-02 18:56:39 +00:00
sunkaddr-ext.ll
…
swap.ll
…
swift-async-reg-win64.ll X86: pass swift_async context in R14 on Win64 2021-06-14 11:02:21 -07:00
swift-async-reg.ll Recommit X86: support Swift Async context 2021-05-18 15:19:05 +01:00
swift-async-win64.ll X86: balance the frame prologue and epilogue on Win64 2021-06-15 20:13:52 -07:00
swift-async.ll SwiftAsync: use runtime-provided flag for extended frame if back-deploying 2021-09-13 13:54:46 +01:00
swift-dynamic-async-frame.ll Add a command-line flag to control the Swift extended async frame info. 2021-09-16 06:57:45 -07:00
swift-error.ll
…
swift-return.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
swiftcc.ll
…
swifterror.ll
…
swiftself-win64.ll
…
swiftself.ll
…
swifttail-async-i386.ll IR/AArch64/X86: add "swifttailcc" calling convention. 2021-05-17 10:48:34 +01:00
swifttail-async-win64.ll X86: balance the frame prologue and epilogue on Win64 2021-06-15 20:13:52 -07:00
swifttail-async.ll IR/AArch64/X86: add "swifttailcc" calling convention. 2021-05-17 10:48:34 +01:00
swifttail-realign.ll X86: add test for realignment fix committed earlier. 2021-08-04 12:10:20 +01:00
swifttail-return.ll IR/AArch64/X86: add "swifttailcc" calling convention. 2021-05-17 10:48:34 +01:00
switch-bit-test-unreachable-default.ll [ISEL][BitTestBlock] omit additional bit test when default destination is unreachable 2021-09-08 11:03:47 -07:00
switch-bt.ll
…
switch-crit-edge-constant.ll
…
switch-default-only.ll
…
switch-density.ll
…
switch-edge-weight.ll
…
switch-jump-table.ll
…
switch-lower-peel-top-case.ll
…
switch-or.ll
…
switch-order-weight.ll
…
switch-zextload.ll
…
switch.ll
…
swizzle-2.ll
…
swizzle-avx2.ll
…
symbol-redefinition.ll
…
system-intrinsics-64-xsave.ll
…
system-intrinsics-64-xsavec.ll
…
system-intrinsics-64-xsaveopt.ll
…
system-intrinsics-64-xsaves.ll
…
system-intrinsics-64.ll
…
system-intrinsics-xgetbv.ll
…
system-intrinsics-xsave.ll
…
system-intrinsics-xsavec.ll
…
system-intrinsics-xsaveopt.ll
…
system-intrinsics-xsaves.ll
…
system-intrinsics-xsetbv.ll [X86] Remove isel predicates for xgetbv/xsetbv instructions so they can work on Windows. 2021-09-02 10:25:02 -07:00
system-intrinsics.ll
…
tagged-globals-pic.ll [X86] Don't affect jump tables under +tagged-globals. 2021-10-29 10:37:43 -07:00
tagged-globals-static.ll [X86] Don't affect jump tables under +tagged-globals. 2021-10-29 10:37:43 -07:00
tail-call-attrs.ll
…
tail-call-casts.ll
…
tail-call-conditional.mir
…
tail-call-got.ll
…
tail-call-legality.ll
…
tail-call-mutable-memarg.ll
…
tail-call-parameter-attrs-mismatch.ll
…
tail-call-win64.ll
…
tail-calls-compatible-attrs.ll [Analysis] Attribute alignment should not prevent tail call optimization 2021-04-24 19:57:42 +02:00
tail-dup-addr.ll
…
tail-dup-asm-goto.ll [MIRParser] Add support for IsInlineAsmBrIndirectTarget 2021-10-07 19:08:01 +01:00
tail-dup-catchret.ll
…
tail-dup-debugloc.ll
…
tail-dup-debugvalue.mir [DebugInfo] Correctly update debug users of SSA values in tail duplication 2021-07-26 17:27:57 +01:00
tail-dup-merge-loop-headers.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
tail-dup-multiple-latch-loop.ll [Taildup] Don't tail-duplicate loop header with multiple successors as its latches 2021-11-01 15:32:00 +08:00
tail-dup-no-other-successor.ll
…
tail-dup-partial.ll
…
tail-dup-repeat.ll
…
tail-merge-after-mbp.mir [X86] Update RET/LRET instruction to use the same naming convention as IRET (PR36876). NFC 2021-11-07 15:06:54 +00:00
tail-merge-debugloc.ll
…
tail-merge-identical.ll
…
tail-merge-unreachable.ll
…
tail-merge-wineh.ll Revert "[NFC] remove explicit default value for strboolattr attribute in tests" 2021-05-24 19:43:40 +02:00
tail-opts.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
tail-threshold.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
tailcall-64.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
tailcall-assume.ll
…
tailcall-calleesave.ll
…
tailcall-cgp-dup.ll
…
tailcall-disable.ll
…
tailcall-extract.ll
…
tailcall-fastisel.ll
…
tailcall-largecode.ll
…
tailcall-lifetime-end.ll
…
tailcall-mem-intrinsics.ll
…
tailcall-msvc-conventions.ll [TargetLowering] Only inspect attributes in the arguments for ArgListEntry 2021-05-18 14:30:22 -07:00
tailcall-multiret.ll Update @llvm.powi to handle different int sizes for the exponent 2021-06-17 09:38:28 +02:00
tailcall-pseudo-64.mir
…
tailcall-pseudo.mir
…
tailcall-readnone.ll
…
tailcall-returndup-void.ll
…
tailcall-ri64.ll
…
tailcall-stackalign.ll
…
tailcall-structret.ll
…
tailcall-swifttailcc.ll SwiftTailCC: teach verifier musttail rules applicable to this CC. 2021-05-28 11:12:00 +01:00
tailcall-tailcc.ll
…
tailcall.ll
…
tailcallbyval.ll
…
tailcallbyval64.ll
…
tailcallfp.ll
…
tailcallfp2.ll
…
tailcallpic1.ll
…
tailcallpic2.ll
…
tailcallpic3.ll
…
tailcallstack64.ll
…
tailcc-calleesave.ll
…
tailcc-disable-tail-calls.ll
…
tailcc-fastcc.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
tailcc-fastisel.ll
…
tailcc-largecode.ll
…
tailcc-notail.ll SwiftTailCC: teach verifier musttail rules applicable to this CC. 2021-05-28 11:12:00 +01:00
tailcc-ssp.ll StackProtector: ensure protection does not interfere with tail call frame. 2021-04-13 15:14:57 +01:00
tailcc-stackalign.ll
…
tailcc-structret.ll
…
tailccbyval.ll
…
tailccbyval64.ll
…
tailccfp.ll
…
tailccfp2.ll
…
tailccpic1.ll
…
tailccpic2.ll
…
tailccstack64.ll
…
taildup-callsiteinfo.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
taildup-crash.ll
…
taildup-heapallocsite.ll
…
tailjmp_gotpcrel_relax_relocation.ll
…
tailregccpic.ll
…
targetLoweringGeneric.ll
…
tbm-intrinsics-fast-isel-x86_64.ll [TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation 2021-10-11 15:28:31 -07:00
tbm-intrinsics-fast-isel.ll [TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation 2021-10-11 15:28:31 -07:00
tbm-intrinsics-x86_64.ll
…
tbm-intrinsics.ll
…
tbm_patterns.ll
…
test-nofold.ll
…
test-shrink-bug.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
test-shrink.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
test-vs-bittest.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
testb-je-fusion.ll [X86] Regenerate testb-je-fusion.ll with common NOFUSION/FUSION prefixes 2021-10-18 21:52:10 +01:00
testl-commute.ll
…
text-section-prefix.ll
…
this-return-64.ll
…
thread_pointer-error.ll [X86][ISel] Lowering llvm.thread.pointer 2021-10-12 11:01:18 +08:00
thread_pointer.ll [X86][ISel] Lowering llvm.thread.pointer 2021-10-12 11:01:18 +08:00
throws-cfi-fp.ll
…
throws-cfi-no-fp.ll
…
tied-depbreak.mir [X86] Update RET/LRET instruction to use the same naming convention as IRET (PR36876). NFC 2021-11-07 15:06:54 +00:00
tls-addr-non-leaf-function.ll
…
tls-android-negative.ll
…
tls-android.ll
…
tls-local-dynamic.ll
…
tls-models.ll
…
tls-no-plt.ll
…
tls-pic.ll
…
tls-pie.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
tls-shrink-wrapping.ll Revert "[NFC] remove explicit default value for strboolattr attribute in tests" 2021-05-24 19:43:40 +02:00
tls-windows-itanium.ll
…
tls.ll
…
tlv-1.ll
…
tlv-2.ll
…
tlv-3.ll
…
token_landingpad.ll
…
topdepthreduce-postra.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
trap.ll
…
tree_way_unsigned_cmp.ll
…
trunc-and.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
trunc-ext-ld-st.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
trunc-store.ll
…
trunc-subvector.ll
…
trunc-to-bool.ll
…
trunc-vector-width.ll
…
tsxldtrk-intrinsic.ll
…
twoaddr-coalesce-2.ll
…
twoaddr-coalesce-3.ll
…
twoaddr-coalesce.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
twoaddr-dbg-value.mir [X86] Update RET/LRET instruction to use the same naming convention as IRET (PR36876). NFC 2021-11-07 15:06:54 +00:00
twoaddr-lea.ll [X86] Regenerate twoaddr-lea.ll test checks. 2021-07-16 17:43:36 +01:00
twoaddr-mul2.mir [X86] Special-case ADD of two identical registers in convertToThreeAddress 2021-10-07 19:50:27 +01:00
twoaddr-sink-terminator.ll
…
typeid-alias.ll
…
uadd_inc_iv.ll
…
uadd_sat.ll RegAllocGreedy: Account for reserved registers in num regs heuristic 2021-09-14 21:00:29 -04:00
uadd_sat_plus.ll
…
uadd_sat_vec.ll [X86] Split FeatureFastVariableShuffle tuning into Lane-Crossing and Per-Lane variants 2021-06-01 10:39:36 +03:00
ubsantrap.ll [UBSAN][PS4] For the PS4 target, emit the ud2 ocpode for ubsan traps. 2021-10-06 11:49:36 -07:00
udiv_fix.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
udiv_fix_sat.ll [TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation 2021-10-11 15:28:31 -07:00
uint64-to-float.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
uint_to_fp-2.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
uint_to_fp-3.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
uint_to_fp.ll
…
uintr-intrinsics.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
umax.ll [TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation 2021-10-11 15:28:31 -07:00
umin.ll [TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation 2021-10-11 15:28:31 -07:00
umul-with-carry.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
umul-with-overflow.ll RegAllocGreedy: Account for reserved registers in num regs heuristic 2021-09-14 21:00:29 -04:00
umul_fix.ll [TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation 2021-10-11 15:28:31 -07:00
umul_fix_sat.ll [TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation 2021-10-11 15:28:31 -07:00
umulo-64-legalisation-lowering.ll [TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation 2021-10-11 15:28:31 -07:00
umulo-128-legalisation-lowering.ll [TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation 2021-10-11 15:28:31 -07:00
unaligned-32-byte-memops.ll
…
unaligned-load.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
unaligned-spill-folding.ll reland [IR] make -stack-alignment= into a module attr 2021-06-08 10:59:46 -07:00
undef-eflags.mir
…
undef-globals-bss.ll
…
undef-label.ll
…
undef-ops.ll
…
unfold-masked-merge-scalar-constmask-innerouter.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
unfold-masked-merge-scalar-constmask-interleavedbits.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
unfold-masked-merge-scalar-constmask-interleavedbytehalves.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
unfold-masked-merge-scalar-constmask-lowhigh.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
unfold-masked-merge-scalar-variablemask.ll [TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation 2021-10-11 15:28:31 -07:00
unfold-masked-merge-vector-variablemask-const.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
unfold-masked-merge-vector-variablemask.ll RegAllocGreedy: Account for reserved registers in num regs heuristic 2021-09-14 21:00:29 -04:00
unfoldMemoryOperand.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
unknown-location.ll
…
unreachable-loop-sinking.ll
…
unreachable-mbb-undef-phi.mir
…
unreachable-trap.ll
…
unreachableblockelim.ll
…
unused_stackslots.ll Revert "[NFC] remove explicit default value for strboolattr attribute in tests" 2021-05-24 19:43:40 +02:00
unwind-init.ll
…
unwind-inline-asm-codegen.ll Support unwinding from inline assembly 2021-05-13 19:13:03 +01:00
unwindraise.ll
…
update-terminator-debugloc.ll Recommit [ScalarEvolution] Make getMinusSCEV() fail for unrelated pointers. 2021-07-06 12:16:05 -07:00
update-terminator.mir [X86] Update RET/LRET instruction to use the same naming convention as IRET (PR36876). NFC 2021-11-07 15:06:54 +00:00
urem-i8-constant.ll
…
urem-lkk.ll [TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation 2021-10-11 15:28:31 -07:00
urem-power-of-two.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
urem-seteq-illegal-types.ll [X86] Canonicalize SGT/UGT compares with constants to use SGE/UGE to reduce the number of EFLAGs reads. (PR48760) 2021-06-30 18:46:50 +01:00
urem-seteq-nonzero.ll
…
urem-seteq-optsize.ll
…
urem-seteq-vec-nonsplat.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
urem-seteq-vec-nonzero.ll [TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation 2021-10-11 15:28:31 -07:00
urem-seteq-vec-splat.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
urem-seteq-vec-tautological.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
urem-seteq.ll [X86] Canonicalize SGT/UGT compares with constants to use SGE/UGE to reduce the number of EFLAGs reads. (PR48760) 2021-06-30 18:46:50 +01:00
urem-vector-lkk.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
use-add-flags.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
use-cr-result-of-dom-icmp-st.ll X86InstrInfo: Support immediates that are +1/-1 different in optimizeCompareInstr 2021-11-03 14:12:23 -07:00
ushl_sat.ll RegAllocGreedy: Account for reserved registers in num regs heuristic 2021-09-14 21:00:29 -04:00
ushl_sat_vec.ll RegAllocGreedy: Account for reserved registers in num regs heuristic 2021-09-14 21:00:29 -04:00
usub_inc_iv.ll
…
usub_sat.ll RegAllocGreedy: Account for reserved registers in num regs heuristic 2021-09-14 21:00:29 -04:00
usub_sat_plus.ll
…
usub_sat_vec.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
utf8.ll
…
utf16-cfstrings.ll
…
uwtables.ll Revert "[NFC] remove explicit default value for strboolattr attribute in tests" 2021-05-24 19:43:40 +02:00
v2f32.ll
…
v4f32-immediate.ll
…
v4i32load-crash.ll
…
v8i1-masks.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
vaargs-prolog-insert.ll [X86][VARARG] Assign MMO earlier to avoid prolog insert point been sunk across VASTART_SAVE_XMM_REGS 2021-11-03 10:13:32 +08:00
vaargs-win32.ll [X86][MS] Fix the aligement mismatch of vector variable arguments on Win32 2021-09-08 09:26:44 +08:00
vaargs.ll
…
vaes-intrinsics-avx-x86.ll
…
vaes-intrinsics-avx512-x86.ll
…
vaes-intrinsics-avx512vl-x86.ll
…
var-permute-128.ll [X86][AVX] Prefer vinsertf128 to vperm2f128 on AVX1 targets 2021-07-26 11:11:56 +01:00
var-permute-256.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
var-permute-512.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
vararg-callee-cleanup.ll
…
vararg_no_start.ll
…
vararg_tailcall.ll
…
varargs-softfloat.ll [X86] avoid assert with varargs, soft float, and no-implicit-float 2021-06-15 11:27:35 -07:00
variable-sized-darwin-bzero.ll
…
variadic-node-pic.ll
…
vastart-defs-eflags.ll
…
vbinop-simplify-bug.ll
…
vec-copysign-avx512.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
vec-copysign.ll
…
vec-libcalls.ll [CodeGen][regalloc] Don't align stack slots if the stack can't be realigned 2021-06-11 16:49:12 +01:00
vec-loadsingles-alignment.ll
…
vec-strict-128-fp16.ll [X86] AVX512FP16 instructions enabling 5/6 2021-08-24 09:07:19 +08:00
vec-strict-128.ll [CodeGen][regalloc] Don't align stack slots if the stack can't be realigned 2021-06-11 16:49:12 +01:00
vec-strict-256-fp16.ll [X86] AVX512FP16 instructions enabling 5/6 2021-08-24 09:07:19 +08:00
vec-strict-256.ll
…
vec-strict-512-fp16.ll [X86] AVX512FP16 instructions enabling 5/6 2021-08-24 09:07:19 +08:00
vec-strict-512.ll
…
vec-strict-cmp-128-fp16.ll [X86] AVX512FP16 instructions enabling 2/6 2021-08-15 08:56:33 +08:00
vec-strict-cmp-128.ll RegAllocGreedy: Account for reserved registers in num regs heuristic 2021-09-14 21:00:29 -04:00
vec-strict-cmp-256-fp16.ll [X86] AVX512FP16 instructions enabling 2/6 2021-08-15 08:56:33 +08:00
vec-strict-cmp-256.ll
…
vec-strict-cmp-512-fp16.ll [X86] AVX512FP16 instructions enabling 2/6 2021-08-15 08:56:33 +08:00
vec-strict-cmp-512.ll
…
vec-strict-cmp-sub128.ll RegAllocGreedy: Account for reserved registers in num regs heuristic 2021-09-14 21:00:29 -04:00
vec-strict-fptoint-128-fp16.ll [X86] AVX512FP16 instructions enabling 3/6 2021-08-18 09:03:41 +08:00
vec-strict-fptoint-128.ll [TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation 2021-10-11 15:28:31 -07:00
vec-strict-fptoint-256-fp16.ll [X86] AVX512FP16 instructions enabling 3/6 2021-08-18 09:03:41 +08:00
vec-strict-fptoint-256.ll RegAllocGreedy: Account for reserved registers in num regs heuristic 2021-09-14 21:00:29 -04:00
vec-strict-fptoint-512-fp16.ll [X86] AVX512FP16 instructions enabling 3/6 2021-08-18 09:03:41 +08:00
vec-strict-fptoint-512.ll
…
vec-strict-inttofp-128-fp16.ll [X86] AVX512FP16 instructions enabling 3/6 2021-08-18 09:03:41 +08:00
vec-strict-inttofp-128.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
vec-strict-inttofp-256-fp16.ll [X86] AVX512FP16 instructions enabling 3/6 2021-08-18 09:03:41 +08:00
vec-strict-inttofp-256.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
vec-strict-inttofp-512-fp16.ll [X86] AVX512FP16 instructions enabling 3/6 2021-08-18 09:03:41 +08:00
vec-strict-inttofp-512.ll RegAllocGreedy: Account for reserved registers in num regs heuristic 2021-09-14 21:00:29 -04:00
vec-strict-round-128.ll
…
vec-trunc-store.ll
…
vec3-setcc-crash.ll
…
vec3.ll
…
vec_align.ll
…
vec_align_i256.ll
…
vec_anyext.ll
…
vec_call.ll
…
vec_cast.ll
…
vec_cast2.ll
…
vec_cast3.ll [X86] Implement smarter instruction lowering for FP_TO_UINT from f32/f64 to i32/i64 and vXf32/vXf64 to vXi32 for SSE2 and AVX2 by using the exact semantic of the CVTTPS2SI instruction. 2021-07-14 12:03:49 +01:00
vec_cmp_sint-128.ll
…
vec_cmp_uint-128.ll
…
vec_compare-sse4.ll
…
vec_compare.ll
…
vec_ctbits.ll [TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation 2021-10-11 15:28:31 -07:00
vec_ext_inreg.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
vec_extract-avx.ll
…
vec_extract-mmx.ll
…
vec_extract-sse4.ll
…
vec_extract.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
vec_fabs.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
vec_floor.ll
…
vec_fneg.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
vec_fp_to_int.ll [X86] Implement smarter instruction lowering for FP_TO_UINT from f32/f64 to i32/i64 and vXf32/vXf64 to vXi32 for SSE2 and AVX2 by using the exact semantic of the CVTTPS2SI instruction. 2021-07-14 12:03:49 +01:00
vec_fpext.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
vec_fptrunc.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
vec_i64.ll
…
vec_ins_extract-1.ll
…
vec_ins_extract.ll
…
vec_insert-2.ll
…
vec_insert-3.ll
…
vec_insert-4.ll
…
vec_insert-5.ll [x86] enhance mayFoldLoad to check alignment 2021-10-27 07:54:25 -04:00
vec_insert-7.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
vec_insert-8.ll
…
vec_insert-9.ll
…
vec_insert-mmx.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
vec_int_to_fp.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
vec_loadsingles.ll
…
vec_logical.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
vec_minmax_match.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
vec_minmax_sint.ll [TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation 2021-10-11 15:28:31 -07:00
vec_minmax_uint.ll [TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation 2021-10-11 15:28:31 -07:00
vec_partial.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
vec_reassociate.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
vec_return.ll
…
vec_saddo.ll [TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation 2021-10-11 15:28:31 -07:00
vec_sdiv_to_shift.ll [TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation 2021-10-11 15:28:31 -07:00
vec_set-2.ll
…
vec_set-3.ll
…
vec_set-4.ll
…
vec_set-6.ll
…
vec_set-7.ll
…
vec_set-8.ll
…
vec_set-A.ll
…
vec_set-B.ll
…
vec_set-C.ll
…
vec_set-D.ll
…
vec_set-F.ll
…
vec_set-H.ll
…
vec_set.ll
…
vec_setcc-2.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
vec_setcc.ll
…
vec_shift.ll
…
vec_shift2.ll
…
vec_shift3.ll
…
vec_shift4.ll RegAllocGreedy: Account for reserved registers in num regs heuristic 2021-09-14 21:00:29 -04:00
vec_shift5.ll [X86] Fold (shift undef, X)->0 for vector shifts by immediate. 2021-05-27 09:31:47 -07:00
vec_shift6.ll [TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation 2021-10-11 15:28:31 -07:00
vec_shift7.ll
…
vec_shuf-insert.ll
…
vec_smulo.ll [TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation 2021-10-11 15:28:31 -07:00
vec_split.ll
…
vec_ss_load_fold.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
vec_ssubo.ll [TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation 2021-10-11 15:28:31 -07:00
vec_trunc_sext.ll
…
vec_uaddo.ll [X86] Split FeatureFastVariableShuffle tuning into Lane-Crossing and Per-Lane variants 2021-06-01 10:39:36 +03:00
vec_uint_to_fp-fastmath.ll
…
vec_uint_to_fp.ll
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vec_umulo.ll [TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation 2021-10-11 15:28:31 -07:00
vec_unsafe-fp-math.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
vec_usubo.ll [X86] Split FeatureFastVariableShuffle tuning into Lane-Crossing and Per-Lane variants 2021-06-01 10:39:36 +03:00
vec_zero-2.ll
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vec_zero.ll
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vec_zero_cse.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
vecloadextract.ll CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
vector-bitreverse.ll [LegalizeVectorOps][X86] Don't defer BITREVERSE expansion to LegalizeDAG. 2021-10-21 15:23:23 -07:00
vector-blend.ll
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vector-compare-all_of.ll [X86][SSE] combineSetCCMOVMSK - allow comparison with upper (known zero) bits in CMP(MOVMSK(PACKSS())) -> CMP(MOVMSK()) fold 2021-04-13 17:37:24 +01:00
vector-compare-any_of.ll [X86] combineCMP - fold cmpEQ/NE(TRUNC(X),0) -> cmpEQ/NE(X,0) 2021-04-15 13:55:51 +01:00
vector-compare-combines.ll
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vector-compare-results.ll
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vector-compare-simplify.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
vector-constrained-fp-intrinsics-flags.ll CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
vector-constrained-fp-intrinsics-fma.ll
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vector-constrained-fp-intrinsics.ll [CodeGen][regalloc] Don't align stack slots if the stack can't be realigned 2021-06-11 16:49:12 +01:00
vector-ext-logic.ll [TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation 2021-10-11 15:28:31 -07:00
vector-extend-inreg.ll
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vector-fshl-128.ll [DAG] FoldConstantArithmetic - fold bitlogic(bitcast(x),bitcast(y)) -> bitcast(bitlogic(x,y)) 2021-11-05 12:00:59 +00:00
vector-fshl-256.ll [X86][SSE] LowerRotate - perform modulo on the amount splat source directly. 2021-07-25 17:30:32 +01:00
vector-fshl-512.ll [TLI] SimplifyDemandedVectorElts(): handle SCALAR_TO_VECTOR(EXTRACT_VECTOR_ELT(?, 0)) 2021-06-14 23:52:53 +03:00
vector-fshl-rot-128.ll [DAG] FoldConstantArithmetic - fold intop(bitcast(buildvector(c1)),bitcast(buildvector(c1))) -> bitcast(intop(buildvector(c1'),buildvector(c2'))) 2021-11-11 11:35:18 +00:00
vector-fshl-rot-256.ll [X86] Freeze vXi8 shl(x,1) -> add(x,x) vector fold (PR50468) 2021-08-24 16:08:24 +01:00
vector-fshl-rot-512.ll [X86] Enable v32i16 rotate lowering on non-BWI targets 2021-11-05 11:00:31 +00:00
vector-fshl-rot-sub128.ll [X86][SSE] Regenerate vector funnel shift tests 2021-11-04 19:17:02 +00:00
vector-fshr-128.ll [DAG] FoldConstantArithmetic - fold bitlogic(bitcast(x),bitcast(y)) -> bitcast(bitlogic(x,y)) 2021-11-05 12:00:59 +00:00
vector-fshr-256.ll [X86] Freeze vXi8 shl(x,1) -> add(x,x) vector fold (PR50468) 2021-08-24 16:08:24 +01:00
vector-fshr-512.ll [X86] Enable v32i16 rotate lowering on non-BWI targets 2021-11-05 11:00:31 +00:00
vector-fshr-rot-128.ll [DAG] FoldConstantArithmetic - fold intop(bitcast(buildvector(c1)),bitcast(buildvector(c1))) -> bitcast(intop(buildvector(c1'),buildvector(c2'))) 2021-11-11 11:35:18 +00:00
vector-fshr-rot-256.ll [X86] Freeze vXi8 shl(x,1) -> add(x,x) vector fold (PR50468) 2021-08-24 16:08:24 +01:00
vector-fshr-rot-512.ll [X86] Enable v32i16 rotate lowering on non-BWI targets 2021-11-05 11:00:31 +00:00
vector-fshr-rot-sub128.ll [X86][SSE] Regenerate vector funnel shift tests 2021-11-04 19:17:02 +00:00
vector-gep.ll RegAllocGreedy: Account for reserved registers in num regs heuristic 2021-09-14 21:00:29 -04:00
vector-half-conversions.ll [CodeGen][regalloc] Don't align stack slots if the stack can't be realigned 2021-06-11 16:49:12 +01:00
vector-idiv-sdiv-128.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
vector-idiv-sdiv-256.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
vector-idiv-sdiv-512.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
vector-idiv-udiv-128.ll [TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation 2021-10-11 15:28:31 -07:00
vector-idiv-udiv-256.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
vector-idiv-udiv-512.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
vector-idiv-v2i32.ll RegAllocGreedy: Account for reserved registers in num regs heuristic 2021-09-14 21:00:29 -04:00
vector-idiv.ll
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vector-interleave.ll [X86][AVX] Prefer vinsertf128 to vperm2f128 on AVX1 targets 2021-07-26 11:11:56 +01:00
vector-interleaved-load-i8-stride-2.ll [X86] Add SSE2/AVX1/AVX512BW test coverage to interleaved load/store tests 2021-10-03 12:31:30 +01:00
vector-interleaved-load-i8-stride-3.ll [X86] Add SSE2/AVX1/AVX512BW test coverage to interleaved load/store tests 2021-10-03 12:31:30 +01:00
vector-interleaved-load-i8-stride-4.ll [X86] Add SSE2/AVX1/AVX512BW test coverage to interleaved load/store tests 2021-10-03 12:31:30 +01:00
vector-interleaved-load-i8-stride-6.ll [NFC][X86][Codegen] Add test coverage for interleaved i8 load/store stride=6 2021-10-03 14:35:17 +03:00
vector-interleaved-load-i16-stride-2.ll [X86] Add SSE2/AVX1/AVX512BW test coverage to interleaved load/store tests 2021-10-03 12:31:30 +01:00
vector-interleaved-load-i16-stride-3.ll [X86] Add SSE2/AVX1/AVX512BW test coverage to interleaved load/store tests 2021-10-03 12:31:30 +01:00
vector-interleaved-load-i16-stride-4.ll [X86][AVX2] Recognise 256-bit truncation shuffles and mask 256-bit source 2021-11-07 21:24:55 +00:00
vector-interleaved-load-i16-stride-5.ll [NFC][X86][Codegen] Add missing interleaving tests after D111546 2021-10-16 18:20:16 +03:00
vector-interleaved-load-i16-stride-6.ll [NFC][X86][Codegen] Add missing interleaving tests after D111546 2021-10-16 18:20:16 +03:00
vector-interleaved-load-i32-stride-2.ll [X86][AVX] Prefer VINSERTF128 over VPERM2F128 for 128->256 subvector concatenations 2021-11-01 10:45:50 +00:00
vector-interleaved-load-i32-stride-3.ll [NFC][X86][Codegen] Add missing interleaving tests after D111546 2021-10-16 18:20:16 +03:00
vector-interleaved-load-i32-stride-4.ll [NFC][X86][Codegen] Add missing interleaving tests after D111546 2021-10-16 18:20:16 +03:00
vector-interleaved-load-i32-stride-6.ll [X86][AVX] Prefer VINSERTF128 over VPERM2F128 for 128->256 subvector concatenations 2021-11-01 10:45:50 +00:00
vector-interleaved-load-i64-stride-2.ll [X86][AVX] Prefer VINSERTF128 over VPERM2F128 for 128->256 subvector concatenations 2021-11-01 10:45:50 +00:00
vector-interleaved-load-i64-stride-3.ll [NFC][X86][Codegen] Add test coverage for interleaved i64 load/store stride=3 2021-10-03 17:52:12 +03:00
vector-interleaved-load-i64-stride-4.ll [X86][AVX] Prefer VINSERTF128 over VPERM2F128 for 128->256 subvector concatenations 2021-11-01 10:45:50 +00:00
vector-interleaved-load-i64-stride-6.ll [NFC][X86][Codegen] Add test coverage for interleaved i64 load/store stride=6 2021-10-04 20:57:36 +03:00
vector-interleaved-store-i8-stride-2.ll [X86] Add SSE2/AVX1/AVX512BW test coverage to interleaved load/store tests 2021-10-03 12:31:30 +01:00
vector-interleaved-store-i8-stride-3.ll [X86] Add SSE2/AVX1/AVX512BW test coverage to interleaved load/store tests 2021-10-03 12:31:30 +01:00
vector-interleaved-store-i8-stride-4.ll [X86] Add SSE2/AVX1/AVX512BW test coverage to interleaved load/store tests 2021-10-03 12:31:30 +01:00
vector-interleaved-store-i8-stride-6.ll [NFC][X86][Codegen] Add test coverage for interleaved i8 load/store stride=6 2021-10-03 14:35:17 +03:00
vector-interleaved-store-i16-stride-2.ll [X86] Add SSE2/AVX1/AVX512BW test coverage to interleaved load/store tests 2021-10-03 12:31:30 +01:00
vector-interleaved-store-i16-stride-3.ll [X86] Add SSE2/AVX1/AVX512BW test coverage to interleaved load/store tests 2021-10-03 12:31:30 +01:00
vector-interleaved-store-i16-stride-4.ll [X86] Add SSE2/AVX1/AVX512BW test coverage to interleaved load/store tests 2021-10-03 12:31:30 +01:00
vector-interleaved-store-i16-stride-5.ll [NFC][X86][Codegen] Add missing interleaving tests after D111546 2021-10-16 18:20:16 +03:00
vector-interleaved-store-i16-stride-6.ll [NFC][X86][Codegen] Add missing interleaving tests after D111546 2021-10-16 18:20:16 +03:00
vector-interleaved-store-i32-stride-2.ll [X86] Add SSE2/AVX1/AVX512BW test coverage to interleaved load/store tests 2021-10-03 12:31:30 +01:00
vector-interleaved-store-i32-stride-3.ll [NFC][X86][Codegen] Add missing interleaving tests after D111546 2021-10-16 18:20:16 +03:00
vector-interleaved-store-i32-stride-4.ll [NFC][X86][Codegen] Add missing interleaving tests after D111546 2021-10-16 18:20:16 +03:00
vector-interleaved-store-i32-stride-6.ll [NFC][X86][Codegen] Add test coverage for interleaved i32 load/store stride=6 2021-10-04 20:57:35 +03:00
vector-interleaved-store-i64-stride-2.ll [NFC][X86][Codegen] Add missing interleaving tests after D111546 2021-10-16 18:20:16 +03:00
vector-interleaved-store-i64-stride-3.ll [NFC][X86][Codegen] Add test coverage for interleaved i64 load/store stride=3 2021-10-03 17:52:12 +03:00
vector-interleaved-store-i64-stride-4.ll [X86][AVX] Prefer VINSERTF128 over VPERM2F128 for 128->256 subvector concatenations 2021-11-01 10:45:50 +00:00
vector-interleaved-store-i64-stride-6.ll [NFC][X86][Codegen] Add test coverage for interleaved i64 load/store stride=6 2021-10-04 20:57:36 +03:00
vector-intrinsics.ll Update @llvm.powi to handle different int sizes for the exponent 2021-06-17 09:38:28 +02:00
vector-lzcnt-128.ll [TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation 2021-10-11 15:28:31 -07:00
vector-lzcnt-256.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
vector-lzcnt-512.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
vector-lzcnt-sub128.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
vector-merge-store-fp-constants.ll
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vector-mul.ll [TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation 2021-10-11 15:28:31 -07:00
vector-mulfix-legalize.ll [X86] Canonicalize SGT/UGT compares with constants to use SGE/UGE to reduce the number of EFLAGs reads. (PR48760) 2021-06-30 18:46:50 +01:00
vector-narrow-binop.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
vector-pack-128.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
vector-pack-256.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
vector-pack-512.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
vector-partial-undef.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
vector-pcmp.ll [x86] fold vector (X > -1) & Y to shift+andn 2021-11-12 08:17:46 -05:00
vector-popcnt-128-ult-ugt.ll [TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation 2021-10-11 15:28:31 -07:00
vector-popcnt-128.ll [TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation 2021-10-11 15:28:31 -07:00
vector-popcnt-256-ult-ugt.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
vector-popcnt-256.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
vector-popcnt-512-ult-ugt.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
vector-popcnt-512.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
vector-reduce-add.ll
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vector-reduce-and-bool.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
vector-reduce-and-cmp.ll [X86] combineCMP - fold cmpEQ/NE(TRUNC(X),0) -> cmpEQ/NE(X,0) 2021-04-15 13:55:51 +01:00
vector-reduce-and.ll
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vector-reduce-fadd-fast.ll [TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation 2021-10-11 15:28:31 -07:00
vector-reduce-fadd.ll [TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation 2021-10-11 15:28:31 -07:00
vector-reduce-fmax-fmin-fast.ll
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vector-reduce-fmax-nnan.ll [X86] AVX512FP16 instructions enabling 2/6 2021-08-15 08:56:33 +08:00
vector-reduce-fmax.ll [TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation 2021-10-11 15:28:31 -07:00
vector-reduce-fmin-nnan.ll [X86] AVX512FP16 instructions enabling 2/6 2021-08-15 08:56:33 +08:00
vector-reduce-fmin.ll
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vector-reduce-fmul-fast.ll [TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation 2021-10-11 15:28:31 -07:00
vector-reduce-fmul.ll [TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation 2021-10-11 15:28:31 -07:00
vector-reduce-mul.ll [X86] combineX86ShuffleChain - ensure we only peek through bitcasts to vectors (PR51858) 2021-09-15 10:21:05 +01:00
vector-reduce-or-bool.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
vector-reduce-or-cmp.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
vector-reduce-or.ll
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vector-reduce-smax.ll [TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation 2021-10-11 15:28:31 -07:00
vector-reduce-smin.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
vector-reduce-umax.ll [TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation 2021-10-11 15:28:31 -07:00
vector-reduce-umin.ll
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vector-reduce-xor-bool.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
vector-reduce-xor.ll
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vector-rem.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
vector-rotate-128.ll [TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation 2021-10-11 15:28:31 -07:00
vector-rotate-256.ll [X86] Freeze vXi8 shl(x,1) -> add(x,x) vector fold (PR50468) 2021-08-24 16:08:24 +01:00
vector-rotate-512.ll [X86] Enable v32i16 rotate lowering on non-BWI targets 2021-11-05 11:00:31 +00:00
vector-sext.ll RegAllocGreedy: Account for reserved registers in num regs heuristic 2021-09-14 21:00:29 -04:00
vector-shift-ashr-128.ll [DAG] FoldConstantArithmetic - fold intop(bitcast(buildvector(c1)),bitcast(buildvector(c1))) -> bitcast(intop(buildvector(c1'),buildvector(c2'))) 2021-11-11 11:35:18 +00:00
vector-shift-ashr-256.ll [DAG] FoldConstantArithmetic - fold intop(bitcast(buildvector(c1)),bitcast(buildvector(c1))) -> bitcast(intop(buildvector(c1'),buildvector(c2'))) 2021-11-11 11:35:18 +00:00
vector-shift-ashr-512.ll [X86][SSE] Regenerate vector shift codegen tests. NFCI. 2021-05-25 15:58:22 +01:00
vector-shift-ashr-sub128.ll [TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation 2021-10-11 15:28:31 -07:00
vector-shift-by-select-loop.ll
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vector-shift-lshr-128.ll [X86][SSE] Regenerate vector shift codegen tests. NFCI. 2021-05-25 15:58:22 +01:00
vector-shift-lshr-256.ll RegAllocGreedy: Account for reserved registers in num regs heuristic 2021-09-14 21:00:29 -04:00
vector-shift-lshr-512.ll [X86][SSE] Regenerate vector shift codegen tests. NFCI. 2021-05-25 15:58:22 +01:00
vector-shift-lshr-sub128.ll [X86][SSE] Regenerate vector shift codegen tests. NFCI. 2021-05-25 15:58:22 +01:00
vector-shift-shl-128.ll [X86][SSE] Regenerate vector shift codegen tests. NFCI. 2021-05-25 15:58:22 +01:00
vector-shift-shl-256.ll RegAllocGreedy: Account for reserved registers in num regs heuristic 2021-09-14 21:00:29 -04:00
vector-shift-shl-512.ll [X86][SSE] Regenerate vector shift codegen tests. NFCI. 2021-05-25 15:58:22 +01:00
vector-shift-shl-sub128.ll [X86][SSE] Regenerate vector shift codegen tests. NFCI. 2021-05-25 15:58:22 +01:00
vector-shuffle-128-unpck.ll [X86] Split FeatureFastVariableShuffle tuning into Lane-Crossing and Per-Lane variants 2021-06-01 10:39:36 +03:00
vector-shuffle-128-v2.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
vector-shuffle-128-v4.ll [X86] Split FeatureFastVariableShuffle tuning into Lane-Crossing and Per-Lane variants 2021-06-01 10:39:36 +03:00
vector-shuffle-128-v8.ll [X86][AVX] Adjust AllowBWIVPERMV3 tolerance to account for VariableCrossLaneShuffleDepth 2021-07-25 14:05:11 +01:00
vector-shuffle-128-v16.ll [X86][AVX] Adjust AllowBWIVPERMV3 tolerance to account for VariableCrossLaneShuffleDepth 2021-07-25 14:05:11 +01:00
vector-shuffle-256-v4.ll [X86] Split FeatureFastVariableShuffle tuning into Lane-Crossing and Per-Lane variants 2021-06-01 10:39:36 +03:00
vector-shuffle-256-v8.ll [X86][AVX] Prefer vinsertf128 to vperm2f128 on AVX1 targets 2021-07-26 11:11:56 +01:00
vector-shuffle-256-v16.ll [X86][AVX] Adjust AllowBWIVPERMV3 tolerance to account for VariableCrossLaneShuffleDepth 2021-07-25 14:05:11 +01:00
vector-shuffle-256-v32.ll Revert "[X86] combineX86ShuffleChain(): canonicalize mask elts picking from splats" 2021-08-05 18:58:08 +02:00
vector-shuffle-512-v8.ll
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vector-shuffle-512-v16.ll [DAG] Fold concat_vectors(concat_vectors(x,y),concat_vectors(a,b)) -> concat_vectors(x,y,a,b) 2021-08-16 16:06:54 +01:00
vector-shuffle-512-v32.ll
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vector-shuffle-512-v64.ll [X86][AVX] Adjust AllowBWIVPERMV3 tolerance to account for VariableCrossLaneShuffleDepth 2021-07-25 14:05:11 +01:00
vector-shuffle-avx512.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
vector-shuffle-combining-avx.ll [X86][AVX] Prefer VINSERTF128 over VPERM2F128 for 128->256 subvector concatenations 2021-11-01 10:45:50 +00:00
vector-shuffle-combining-avx2.ll [X86][AVX] Ensure we retain zero elements in select(pshufb,pshufb) -> or(pshufb,pshufb) fold (PR52122) 2021-10-11 14:50:24 +01:00
vector-shuffle-combining-avx512bw.ll [DAG] CombineConsecutiveLoads - replace getABITypeAlign with allowsMemoryAccess (PR45116) 2021-08-24 12:31:22 +01:00
vector-shuffle-combining-avx512bwvl.ll
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vector-shuffle-combining-avx512f.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
vector-shuffle-combining-avx512vbmi.ll [DAG] CombineConsecutiveLoads - replace getABITypeAlign with allowsMemoryAccess (PR45116) 2021-08-24 12:31:22 +01:00
vector-shuffle-combining-sse4a.ll
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vector-shuffle-combining-sse41.ll [X86][SSE] getFauxShuffleMask - don't decode OR(SHUFFLE,SHUFFLE) containing UNDEFs. (PR50049) 2021-04-21 18:47:00 +01:00
vector-shuffle-combining-ssse3.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
vector-shuffle-combining-xop.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
vector-shuffle-combining.ll [TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation 2021-10-11 15:28:31 -07:00
vector-shuffle-masked.ll
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vector-shuffle-mmx.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
vector-shuffle-sse1.ll
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vector-shuffle-sse4a.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
vector-shuffle-sse41.ll
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vector-shuffle-v1.ll [X86] Split FeatureFastVariableShuffle tuning into Lane-Crossing and Per-Lane variants 2021-06-01 10:39:36 +03:00
vector-shuffle-v48.ll [X86][AVX] Adjust AllowBWIVPERMV3 tolerance to account for VariableCrossLaneShuffleDepth 2021-07-25 14:05:11 +01:00
vector-shuffle-variable-128.ll
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vector-shuffle-variable-256.ll
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vector-sqrt.ll Revert "[NFC] remove explicit default value for strboolattr attribute in tests" 2021-05-24 19:43:40 +02:00
vector-trunc-math.ll [TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation 2021-10-11 15:28:31 -07:00
vector-trunc-packus.ll [X86] Split FeatureFastVariableShuffle tuning into Lane-Crossing and Per-Lane variants 2021-06-01 10:39:36 +03:00
vector-trunc-ssat.ll RegAllocGreedy: Account for reserved registers in num regs heuristic 2021-09-14 21:00:29 -04:00
vector-trunc-usat.ll [X86] Split FeatureFastVariableShuffle tuning into Lane-Crossing and Per-Lane variants 2021-06-01 10:39:36 +03:00
vector-trunc.ll [X86][AVX2] Recognise 256-bit truncation shuffles and mask 256-bit source 2021-11-07 21:24:55 +00:00
vector-truncate-combine.ll
…
vector-tzcnt-128.ll [TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation 2021-10-11 15:28:31 -07:00
vector-tzcnt-256.ll
…
vector-tzcnt-512.ll
…
vector-unsigned-cmp.ll [TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation 2021-10-11 15:28:31 -07:00
vector-variable-idx.ll
…
vector-variable-idx2.ll
…
vector-width-store-merge.ll Revert "[NFC] remove explicit default value for strboolattr attribute in tests" 2021-05-24 19:43:40 +02:00
vector-zext.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
vector-zmov.ll
…
vector.ll
…
vector_splat-const-shift-of-constmasked.ll [X86] Remove incorrect use of known bits in shuffle simplification. 2021-07-18 18:13:11 -07:00
vectorcall.ll [Mangler] Calculate the argument list byte count suffix correctly when returning large values 2021-09-29 11:42:28 -07:00
version_directive.ll
…
vfcmp.ll
…
viabs.ll
…
virtreg-physreg-def-regallocfast.mir
…
virtual-registers-cleared-in-machine-functions-liveins.ll
…
visibility.ll
…
visibility2.ll
…
vmaskmov-offset.ll CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
vmovq.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
volatile-memstores-nooverlapping-load-stores.ll
…
volatile.ll
…
vortex-bug.ll
…
vp2intersect_multiple_pairs.ll [X86FixupLEAs] Try again to transform the sequence LEA/SUB to SUB/SUB 2021-07-16 10:16:03 -07:00
vpshufbitqbm-intrinsics-upgrade.ll
…
vpshufbitqbm-intrinsics.ll
…
vsel-cmp-load.ll [x86] try harder to lower to PCMPGT instead of not-of-PCMPEQ 2021-05-12 08:25:29 -04:00
vselect-2.ll
…
vselect-avx.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
vselect-constants.ll [SelectionDAG] Merge FoldConstantVectorArithmetic into FoldConstantArithmetic (PR36544) 2021-11-09 11:31:01 +00:00
vselect-minmax.ll [TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation 2021-10-11 15:28:31 -07:00
vselect-packss.ll
…
vselect-pcmp.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
vselect-zero.ll [x86] fold vector (X > -1) & Y to shift+andn 2021-11-12 08:17:46 -05:00
vselect.ll [X86] Fold SHUFPS(shuffle(x),shuffle(y),mask) -> SHUFPS(x,y,mask') 2021-09-19 20:39:19 +01:00
vshift-1.ll
…
vshift-2.ll
…
vshift-3.ll
…
vshift-4.ll
…
vshift-5.ll
…
vshift-6.ll RegAllocGreedy: Account for reserved registers in num regs heuristic 2021-09-14 21:00:29 -04:00
vshift_scalar.ll
…
vshift_split.ll
…
vshift_split2.ll
…
vshli-simplify-demanded-bits.ll [X86] combineMulToPMADDWD - handle any pow2 vector type and split to legal types 2021-11-09 15:20:43 +00:00
vsplit-and.ll
…
vzero-excess.ll [CodeGen][regalloc] Don't align stack slots if the stack can't be realigned 2021-06-11 16:49:12 +01:00
waitpkg-intrinsics.ll
…
warn-stack.ll Improve the diagnostic of DiagnosticInfoResourceLimit (and warn-stack-size in particular) 2021-06-22 09:55:20 -07:00
wbinvd-intrinsic.ll
…
wbnoinvd-intrinsic.ll
…
weak-undef.ll
…
weak.ll
…
weak_def_can_be_hidden.ll
…
webkit-jscc.ll
…
wide-fma-contraction.ll
…
wide-integer-cmp.ll
…
wide-integer-fold.ll
…
widen_arith-1.ll
…
widen_arith-2.ll
…
widen_arith-3.ll
…
widen_arith-4.ll
…
widen_arith-5.ll
…
widen_arith-6.ll
…
widen_bitops-0.ll
…
widen_bitops-1.ll
…
widen_cast-1.ll
…
widen_cast-2.ll
…
widen_cast-3.ll
…
widen_cast-4.ll RegAllocGreedy: Account for reserved registers in num regs heuristic 2021-09-14 21:00:29 -04:00
widen_cast-5.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
widen_cast-6.ll
…
widen_compare-1.ll
…
widen_conv-1.ll
…
widen_conv-2.ll
…
widen_conv-3.ll
…
widen_conv-4.ll
…
widen_conversions.ll
…
widen_extract-1.ll
…
widen_load-0.ll
…
widen_load-1.ll
…
widen_load-2.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
widen_load-3.ll
…
widen_mul.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
widen_shuffle-1.ll
…
widened-broadcast.ll
…
win-alloca-expander.ll
…
win-catchpad-csrs.ll
…
win-catchpad-nested-cxx.ll
…
win-catchpad-nested.ll
…
win-catchpad-varargs.ll
…
win-catchpad.ll
…
win-cleanuppad.ll Revert "[NFC] remove explicit default value for strboolattr attribute in tests" 2021-05-24 19:43:40 +02:00
win-funclet-cfi.ll
…
win-mixed-ehpersonality.ll
…
win-smallparams.ll
…
win32-bool.ll
…
win32-eh-available-externally.ll
…
win32-eh-states.ll
…
win32-eh.ll
…
win32-pic-jumptable.ll
…
win32-preemption.ll
…
win32-seh-catchpad-realign.ll
…
win32-seh-catchpad.ll Revert "[NFC] remove explicit default value for strboolattr attribute in tests" 2021-05-24 19:43:40 +02:00
win32-seh-nested-finally.ll Revert "[NFC] remove explicit default value for strboolattr attribute in tests" 2021-05-24 19:43:40 +02:00
win32-spill-xmm.ll [X86][MS] Fix the aligement mismatch of vector variable arguments on Win32 2021-09-08 09:26:44 +08:00
win32-ssp.ll
…
win32_sret.ll
…
win64-bool.ll
…
win64-byval.ll
…
win64-eh-empty-block-2.mir [X86] Update RET/LRET instruction to use the same naming convention as IRET (PR36876). NFC 2021-11-07 15:06:54 +00:00
win64-eh-empty-block.ll
…
win64-funclet-savexmm.ll
…
win64-jumptable.ll
…
win64-long-double.ll
…
win64-nosse-csrs.ll
…
win64-stackprobe-overflow.ll
…
win64_alloca_dynalloca.ll
…
win64_call_epi.ll
…
win64_eh.ll
…
win64_eh_leaf.ll
…
win64_eh_leaf2.ll
…
win64_frame.ll
…
win64_nonvol.ll
…
win64_params.ll
…
win64_regcall.ll
…
win64_sibcall.ll
…
win64_vararg.ll
…
win_chkstk.ll
…
win_coreclr_chkstk.ll
…
win_coreclr_chkstk_liveins.mir
…
win_cst_pool.ll
…
windows-itanium-alloca.ll
…
wineh-coreclr.ll
…
wineh-exceptionpointer.ll
…
wineh-no-ehpads.ll
…
x32-cet-intrinsics.ll
…
x32-function_pointer-1.ll
…
x32-function_pointer-2.ll
…
x32-function_pointer-3.ll
…
x32-indirectbr.ll
…
x32-landingpad.ll
…
x32-lea-1.ll [X32] Add Triple::isX32(), use it. 2021-06-07 20:48:39 +01:00
x32-movtopush64.ll
…
x32-va_start.ll
…
x64-cet-intrinsics.ll
…
x86-16.ll
…
x86-32-intrcc.ll
…
x86-32-vector-calling-conv.ll
…
x86-64-and-mask.ll
…
x86-64-arg.ll
…
x86-64-asm.ll
…
x86-64-baseptr.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
x86-64-bittest-logic.ll
…
x86-64-call.ll
…
x86-64-disp.ll
…
x86-64-double-precision-shift-left.ll
…
x86-64-double-precision-shift-right.ll
…
x86-64-double-shifts-Oz-Os-O2.ll Revert "[NFC] remove explicit default value for strboolattr attribute in tests" 2021-05-24 19:43:40 +02:00
x86-64-double-shifts-var.ll [X86] AMD Zen 3 Scheduler Model 2021-05-01 22:08:13 +03:00
x86-64-extend-shift.ll
…
x86-64-flags-intrinsics.ll
…
x86-64-gv-offset.ll
…
x86-64-intrcc-nosse.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
x86-64-intrcc-uintr.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
x86-64-intrcc.ll
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x86-64-jumps.ll
…
x86-64-mem.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
x86-64-ms_abi-vararg.ll
…
x86-64-pic-1.ll
…
x86-64-pic-2.ll
…
x86-64-pic-3.ll
…
x86-64-pic-4.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
x86-64-pic-5.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
x86-64-pic-6.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
x86-64-pic-7.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
x86-64-pic-8.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
x86-64-pic-9.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
x86-64-pic-10.ll
…
x86-64-pic-11.ll
…
x86-64-pic-12.ll
…
x86-64-pic.ll
…
x86-64-plt-relative-reloc.ll
…
x86-64-psub.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
x86-64-ptr-arg-simple.ll
…
x86-64-ret0.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
x86-64-shortint.ll
…
x86-64-sret-return-2.ll
…
x86-64-sret-return.ll
…
x86-64-stack-and-frame-ptr.ll
…
x86-64-static-relo-movl.ll
…
x86-64-tls-1.ll
…
x86-64-varargs.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
x86-64-veccallcc.ll
…
x86-64-xmm-spill-unaligned.ll reland [IR] make -stack-alignment= into a module attr 2021-06-08 10:59:46 -07:00
x86-big-ret.ll
…
x86-cmov-converter.ll [X86] Update MachineLoopInfo in CMOV conversion. 2021-07-21 10:53:46 +08:00
x86-flags-intrinsics.ll
…
x86-fold-pshufb.ll
…
x86-framelowering-trap.ll
…
x86-inline-asm-validation.ll
…
x86-interleaved-access.ll [X86][AVX] Prefer VINSERTF128 over VPERM2F128 for 128->256 subvector concatenations 2021-11-01 10:45:50 +00:00
x86-interleaved-check.ll
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x86-interrupt_cc.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
x86-interrupt_cld.ll
…
x86-interrupt_vzeroupper.ll
…
x86-mixed-alignment-dagcombine.ll
…
x86-no_callee_saved_registers.ll
…
x86-no_caller_saved_registers-preserve.ll [TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation 2021-10-11 15:28:31 -07:00
x86-no_caller_saved_registers.ll
…
x86-plt-relative-reloc.ll
…
x86-regcall-got.ll
…
x86-repmov-copy-eflags.ll
…
x86-sanitizer-shrink-wrapping.ll
…
x86-setcc-int-to-fp-combine.ll
…
x86-shifts.ll [TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation 2021-10-11 15:28:31 -07:00
x86-shrink-wrap-unwind.ll
…
x86-shrink-wrapping.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
x86-store-gv-addr.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
x86-upgrade-avx-vbroadcast.ll
…
x86-upgrade-avx2-vbroadcast.ll
…
x86-win64-shrink-wrapping.ll
…
x86_64-mul-by-const.ll
…
x87-reg-usage.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
x87-stack-pop.mir [X86] Preserve FPSW when popping x87 stack 2021-11-12 12:00:09 +07:00
x87.ll
…
xaluo.ll
…
xaluo128.ll
…
xchg-nofold.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
xmm-r64.ll
…
xmm-vararg-noopt.ll
…
xmulo.ll RegAllocGreedy: Account for reserved registers in num regs heuristic 2021-09-14 21:00:29 -04:00
xop-ifma.ll
…
xop-intrinsics-fast-isel.ll
…
xop-intrinsics-x86_64-upgrade.ll
…
xop-intrinsics-x86_64.ll
…
xop-mask-comments.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
xop-pcmov.ll
…
xor-combine-debugloc.ll
…
xor-icmp.ll
…
xor-select-i1-combine.ll
…
xor-with-overflow.ll [X86] Fold cmpeq/ne(trunc(logic(x)),0) --> cmpeq/ne(logic(x),0) 2021-04-12 16:05:34 +01:00
xor.ll [UpdateTestChecks] Default --x86_scrub_rip to False 2021-05-21 19:26:15 -07:00
xray-attribute-instrumentation.ll
…
xray-custom-log.ll
…
xray-empty-firstmbb.mir
…
xray-ignore-loop-detection.ll
…
xray-log-args.ll
…
xray-loop-detection.ll
…
xray-multiplerets-in-blocks.mir [X86] Update RET/LRET instruction to use the same naming convention as IRET (PR36876). NFC 2021-11-07 15:06:54 +00:00
xray-partial-instrumentation-skip-entry.ll
…
xray-partial-instrumentation-skip-exit.ll
…
xray-section-group.ll
…
xray-selective-instrumentation-miss.ll
…
xray-selective-instrumentation.ll
…
xray-tail-call-sled.ll
…
xtest.ll
…
ymm-ordering.ll [Test] We can benefit from pipelining of ymm load/stores 2021-07-15 17:15:14 +07:00
zero-initialized-in-bss.ll
…
zero-remat.ll
…
zext-demanded.ll
…
zext-extract_subreg.ll
…
zext-fold.ll [NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated 2021-06-11 23:57:02 +03:00
zext-inreg-0.ll
…
zext-inreg-1.ll
…
zext-logicop-shift-load.ll
…
zext-sext.ll [X86] Canonicalize SGT/UGT compares with constants to use SGE/UGE to reduce the number of EFLAGs reads. (PR48760) 2021-06-30 18:46:50 +01:00
zext-shl.ll
…
zext-trunc.ll [LiveIntervals] Improve repair after convertToThreeAddress 2021-09-28 08:10:08 +01:00
zlib-longest-match.ll
…
znver3-gather.ll [NFC][X86] Add 'gather' optsize/minsize test coverage 2021-09-27 23:49:10 +03:00