mirror of https://github.com/RT-Thread/rt-thread
[GD32]add gd32470z-lckfb (#7022)
* --复制gd32450z-eval 作为立创梁山派 gd32470z-lckfb的模板进行移植 * -修改模板keil工程的配置，IROM需要注意总共为1024k，分为Code area 和Data area ，IRAM1为 ： 512K-64K=448K=458752=0x70000。 -重新用ENV生成编译固件 片上SRAM可分为4块，分别为SRAM0（112KB）、SRAM1（16KB）、SRAM2（64KB）和TCMSRAM（64KB）。SRAM0、SRAM1和SRAM2可以被所有的AHB主机访问，然而，TCMSRAM（紧耦合存储器SRAM）只可被Cortex ® -M4内核的数据总线访问。BKPSRAM（备份SRAM）应用于备份域，即使当VDD供电电源掉电时，该SRAM仍可保持其内容。附加SRAM（ADDSRAM）只在一些特殊的GD32F4xx器件中可用。由于采用AHB互联矩阵，上述SRAM块可以同时被不同的AHB主机访问，例如，即使CPU正在访问SRAM0，USBHS也可以访问SRAM1。 * -修改IAR编译的链接脚本 * --修改Flash和RAM大小 -RAM大小为448k是因为512K-64K=448K，其中后面的64K为TCMSRAM（紧耦合存储器SRAM）只可被Cortex ® -M4内核的数据总线访问，先不要乱分配 * -修改MDK链接脚本 * -修改board.h * -修改MCU型号 * -Finsh控制台和LED1闪灯程序工作正常，串口控制台名称错误，从uart改为uart0 -Scons正常生成工程 * -发现GD32固件库当前没有240Mhz的时钟配置，将固件库升级为GD32F4xx_Firmware_Library_V3.0.3-发布时间为2023-01-04 * -修改bsp/gd32/arm/gd32407v-start/board/SConscript文件 * -修改led1和change logs * -按照提交规范使能 One ELF Section per Function（MDK） 并用scons重新生成工程 * -发现整个GD32的IAR模板工程template.eww 是没有的，所以当前是不支持IAR开发的，需要后面学习一下IAR使用再实现了。 * -使用formatting源码格式化工具跑一边gd32470z-lckfb目录 * -使用formatting源码格式化工具跑一遍[components/net/netdev/src/netdev.c] -三个月前的提交多了几个空格
This commit is contained in:
yuanzihao
GitHub
parent
abfaa4bc4e
commit
23786ee481
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@ -82,6 +82,7 @@ jobs:
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- {RTT_BSP: "gd32/arm/gd32307e-start", RTT_TOOL_CHAIN: "sourcery-arm"}
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- {RTT_BSP: "gd32/arm/gd32307e-start", RTT_TOOL_CHAIN: "sourcery-arm"}
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- {RTT_BSP: "gd32/arm/gd32407v-start", RTT_TOOL_CHAIN: "sourcery-arm"}
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- {RTT_BSP: "gd32/arm/gd32407v-start", RTT_TOOL_CHAIN: "sourcery-arm"}
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- {RTT_BSP: "gd32/arm/gd32450z-eval", RTT_TOOL_CHAIN: "sourcery-arm"}
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- {RTT_BSP: "gd32/arm/gd32450z-eval", RTT_TOOL_CHAIN: "sourcery-arm"}
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- {RTT_BSP: "gd32/arm/gd32470z-lckfb", RTT_TOOL_CHAIN: "sourcery-arm"}
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- {RTT_BSP: "gd32e230k-start", RTT_TOOL_CHAIN: "sourcery-arm"}
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- {RTT_BSP: "gd32e230k-start", RTT_TOOL_CHAIN: "sourcery-arm"}
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- {RTT_BSP: "gd32vf103v-eval", RTT_TOOL_CHAIN: "sourcery-riscv-none-embed"}
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- {RTT_BSP: "gd32vf103v-eval", RTT_TOOL_CHAIN: "sourcery-riscv-none-embed"}
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- {RTT_BSP: "gd32303e-eval", RTT_TOOL_CHAIN: "sourcery-arm"}
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- {RTT_BSP: "gd32303e-eval", RTT_TOOL_CHAIN: "sourcery-arm"}
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@ -21,7 +21,7 @@ GD32 系列 BSP 目前支持情况如下表所示：
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| **F4 系列** | |
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| **F4 系列** | |
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| [gd32407v-start](arm/gd32407v-start) | 兆易创新 官方 GD32407V-START 开发板 |
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| [gd32407v-start](arm/gd32407v-start) | 兆易创新 官方 GD32407V-START 开发板 |
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| [gd32450z-eval](arm/gd32450z-eval) | 兆易创新 官方 GD32450Z-EVAL 开发板 |
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| [gd32450z-eval](arm/gd32450z-eval) | 兆易创新 官方 GD32450Z-EVAL 开发板 |
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| | |
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| [gd32470z-lckfb](arm/gd32470z-lckfb) | 立创梁山派 GD32F470ZGT6 开发板 |
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| **RISC-V 系列** | |
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| **RISC-V 系列** | |
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| **VF1 系列** | |
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| **VF1 系列** | |
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| [gd32vf103v-eval](risc-v/gd32vf103v-eval) | 兆易创新 官方 GGD32VF103V-EVAL 开发板 |
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| [gd32vf103v-eval](risc-v/gd32vf103v-eval) | 兆易创新 官方 GGD32VF103V-EVAL 开发板 |
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@ -20,6 +20,7 @@ GD32 ARM 系列 BSP 目前支持情况如下表所示：
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| **F4 系列** | |
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| **F4 系列** | |
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| [gd32407v-start](gd32407v-start) | 兆易创新 官方 GD32407V-START 开发板 |
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| [gd32407v-start](gd32407v-start) | 兆易创新 官方 GD32407V-START 开发板 |
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| [gd32450z-eval](gd32450z-eval) | 兆易创新 官方 GD32450Z-EVAL 开发板 |
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| [gd32450z-eval](gd32450z-eval) | 兆易创新 官方 GD32450Z-EVAL 开发板 |
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| [gd32470z-lckfb](gd32470z-lckfb) | 立创梁山派 GD32F470ZGT6 开发板 |
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可以通过阅读相应 BSP 下的 README 来快速上手，如果想要使用 BSP 更多功能可参考 docs 文件夹下提供的说明文档，如下表所示：
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可以通过阅读相应 BSP 下的 README 来快速上手，如果想要使用 BSP 更多功能可参考 docs 文件夹下提供的说明文档，如下表所示：
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@ -0,0 +1,714 @@
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#
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# Automatically generated file; DO NOT EDIT.
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# RT-Thread Configuration
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#
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#
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# RT-Thread Kernel
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#
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CONFIG_RT_NAME_MAX=8
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# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
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# CONFIG_RT_USING_SMP is not set
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CONFIG_RT_ALIGN_SIZE=8
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# CONFIG_RT_THREAD_PRIORITY_8 is not set
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CONFIG_RT_THREAD_PRIORITY_32=y
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# CONFIG_RT_THREAD_PRIORITY_256 is not set
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CONFIG_RT_THREAD_PRIORITY_MAX=32
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CONFIG_RT_TICK_PER_SECOND=1000
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CONFIG_RT_USING_OVERFLOW_CHECK=y
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CONFIG_RT_USING_HOOK=y
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CONFIG_RT_HOOK_USING_FUNC_PTR=y
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CONFIG_RT_USING_IDLE_HOOK=y
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CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
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CONFIG_IDLE_THREAD_STACK_SIZE=256
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CONFIG_RT_USING_TIMER_SOFT=y
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CONFIG_RT_TIMER_THREAD_PRIO=4
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CONFIG_RT_TIMER_THREAD_STACK_SIZE=512
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#
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# kservice optimization
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#
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CONFIG_RT_KSERVICE_USING_STDLIB=y
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# CONFIG_RT_KSERVICE_USING_STDLIB_MEMORY is not set
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# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set
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# CONFIG_RT_USING_TINY_FFS is not set
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# CONFIG_RT_KPRINTF_USING_LONGLONG is not set
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CONFIG_RT_DEBUG=y
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# CONFIG_RT_DEBUG_COLOR is not set
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# CONFIG_RT_DEBUG_INIT_CONFIG is not set
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# CONFIG_RT_DEBUG_THREAD_CONFIG is not set
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# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set
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# CONFIG_RT_DEBUG_IPC_CONFIG is not set
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# CONFIG_RT_DEBUG_TIMER_CONFIG is not set
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# CONFIG_RT_DEBUG_IRQ_CONFIG is not set
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# CONFIG_RT_DEBUG_MEM_CONFIG is not set
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# CONFIG_RT_DEBUG_SLAB_CONFIG is not set
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# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set
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# CONFIG_RT_DEBUG_MODULE_CONFIG is not set
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#
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# Inter-Thread communication
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#
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CONFIG_RT_USING_SEMAPHORE=y
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CONFIG_RT_USING_MUTEX=y
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CONFIG_RT_USING_EVENT=y
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CONFIG_RT_USING_MAILBOX=y
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CONFIG_RT_USING_MESSAGEQUEUE=y
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# CONFIG_RT_USING_SIGNALS is not set
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#
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# Memory Management
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#
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CONFIG_RT_PAGE_MAX_ORDER=11
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CONFIG_RT_USING_MEMPOOL=y
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CONFIG_RT_USING_SMALL_MEM=y
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# CONFIG_RT_USING_SLAB is not set
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# CONFIG_RT_USING_MEMHEAP is not set
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CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y
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# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set
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# CONFIG_RT_USING_SLAB_AS_HEAP is not set
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# CONFIG_RT_USING_USERHEAP is not set
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# CONFIG_RT_USING_NOHEAP is not set
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# CONFIG_RT_USING_MEMTRACE is not set
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# CONFIG_RT_USING_HEAP_ISR is not set
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CONFIG_RT_USING_HEAP=y
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#
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# Kernel Device Object
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#
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CONFIG_RT_USING_DEVICE=y
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# CONFIG_RT_USING_DEVICE_OPS is not set
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# CONFIG_RT_USING_DM is not set
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# CONFIG_RT_USING_INTERRUPT_INFO is not set
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CONFIG_RT_USING_CONSOLE=y
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CONFIG_RT_CONSOLEBUF_SIZE=128
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CONFIG_RT_CONSOLE_DEVICE_NAME="uart0"
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CONFIG_RT_VER_NUM=0x50000
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# CONFIG_RT_USING_CACHE is not set
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# CONFIG_ARCH_ARM_BOOTWITH_FLUSH_CACHE is not set
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# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
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# CONFIG_RT_USING_CPU_FFS is not set
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#
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# RT-Thread Components
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#
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CONFIG_RT_USING_COMPONENTS_INIT=y
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CONFIG_RT_USING_USER_MAIN=y
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CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048
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CONFIG_RT_MAIN_THREAD_PRIORITY=10
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# CONFIG_RT_USING_LEGACY is not set
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CONFIG_RT_USING_MSH=y
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CONFIG_RT_USING_FINSH=y
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CONFIG_FINSH_USING_MSH=y
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CONFIG_FINSH_THREAD_NAME="tshell"
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CONFIG_FINSH_THREAD_PRIORITY=20
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CONFIG_FINSH_THREAD_STACK_SIZE=4096
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CONFIG_FINSH_USING_HISTORY=y
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CONFIG_FINSH_HISTORY_LINES=5
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CONFIG_FINSH_USING_SYMTAB=y
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CONFIG_FINSH_CMD_SIZE=80
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CONFIG_MSH_USING_BUILT_IN_COMMANDS=y
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CONFIG_FINSH_USING_DESCRIPTION=y
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# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
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# CONFIG_FINSH_USING_AUTH is not set
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CONFIG_FINSH_ARG_MAX=10
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CONFIG_RT_USING_DFS=y
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CONFIG_DFS_USING_POSIX=y
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CONFIG_DFS_USING_WORKDIR=y
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CONFIG_DFS_FILESYSTEMS_MAX=4
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CONFIG_DFS_FILESYSTEM_TYPES_MAX=4
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CONFIG_DFS_FD_MAX=16
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# CONFIG_RT_USING_DFS_MNTTABLE is not set
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# CONFIG_RT_USING_DFS_ELMFAT is not set
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# CONFIG_RT_USING_DFS_DEVFS is not set
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# CONFIG_RT_USING_DFS_ROMFS is not set
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# CONFIG_RT_USING_DFS_CROMFS is not set
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# CONFIG_RT_USING_DFS_RAMFS is not set
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# CONFIG_RT_USING_DFS_TMPFS is not set
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# CONFIG_RT_USING_FAL is not set
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#
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# Device Drivers
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#
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CONFIG_RT_USING_DEVICE_IPC=y
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CONFIG_RT_UNAMED_PIPE_NUMBER=64
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# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set
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CONFIG_RT_USING_SERIAL=y
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CONFIG_RT_USING_SERIAL_V1=y
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# CONFIG_RT_USING_SERIAL_V2 is not set
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CONFIG_RT_SERIAL_USING_DMA=y
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CONFIG_RT_SERIAL_RB_BUFSZ=64
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# CONFIG_RT_USING_CAN is not set
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# CONFIG_RT_USING_HWTIMER is not set
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# CONFIG_RT_USING_CPUTIME is not set
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# CONFIG_RT_USING_I2C is not set
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# CONFIG_RT_USING_PHY is not set
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CONFIG_RT_USING_PIN=y
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# CONFIG_RT_USING_ADC is not set
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# CONFIG_RT_USING_DAC is not set
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# CONFIG_RT_USING_NULL is not set
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# CONFIG_RT_USING_ZERO is not set
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# CONFIG_RT_USING_RANDOM is not set
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# CONFIG_RT_USING_PWM is not set
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# CONFIG_RT_USING_MTD_NOR is not set
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# CONFIG_RT_USING_MTD_NAND is not set
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# CONFIG_RT_USING_PM is not set
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# CONFIG_RT_USING_FDT is not set
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# CONFIG_RT_USING_RTC is not set
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# CONFIG_RT_USING_SDIO is not set
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# CONFIG_RT_USING_SPI is not set
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# CONFIG_RT_USING_WDT is not set
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# CONFIG_RT_USING_AUDIO is not set
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# CONFIG_RT_USING_SENSOR is not set
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# CONFIG_RT_USING_TOUCH is not set
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# CONFIG_RT_USING_LCD is not set
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# CONFIG_RT_USING_HWCRYPTO is not set
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# CONFIG_RT_USING_PULSE_ENCODER is not set
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# CONFIG_RT_USING_INPUT_CAPTURE is not set
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# CONFIG_RT_USING_DEV_BUS is not set
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# CONFIG_RT_USING_WIFI is not set
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# CONFIG_RT_USING_VIRTIO is not set
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#
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# Using USB
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#
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# CONFIG_RT_USING_USB is not set
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# CONFIG_RT_USING_USB_HOST is not set
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# CONFIG_RT_USING_USB_DEVICE is not set
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#
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# C/C++ and POSIX layer
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#
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CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
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#
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# POSIX (Portable Operating System Interface) layer
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#
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# CONFIG_RT_USING_POSIX_FS is not set
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# CONFIG_RT_USING_POSIX_DELAY is not set
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# CONFIG_RT_USING_POSIX_CLOCK is not set
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# CONFIG_RT_USING_POSIX_TIMER is not set
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# CONFIG_RT_USING_PTHREADS is not set
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# CONFIG_RT_USING_MODULE is not set
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#
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# Interprocess Communication (IPC)
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#
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# CONFIG_RT_USING_POSIX_PIPE is not set
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# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set
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# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set
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#
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# Socket is in the 'Network' category
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#
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# CONFIG_RT_USING_CPLUSPLUS is not set
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#
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# Network
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#
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# CONFIG_RT_USING_SAL is not set
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# CONFIG_RT_USING_NETDEV is not set
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# CONFIG_RT_USING_LWIP is not set
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# CONFIG_RT_USING_AT is not set
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#
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# Utilities
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#
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# CONFIG_RT_USING_RYM is not set
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# CONFIG_RT_USING_ULOG is not set
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# CONFIG_RT_USING_UTEST is not set
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# CONFIG_RT_USING_VAR_EXPORT is not set
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# CONFIG_RT_USING_ADT is not set
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# CONFIG_RT_USING_RT_LINK is not set
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# CONFIG_RT_USING_VBUS is not set
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#
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# RT-Thread Utestcases
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#
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# CONFIG_RT_USING_UTESTCASES is not set
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#
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||||||
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# RT-Thread online packages
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||||||
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#
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||||||
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||||||
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#
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# IoT - internet of things
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#
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||||||
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# CONFIG_PKG_USING_LWIP is not set
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||||||
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# CONFIG_PKG_USING_LORAWAN_DRIVER is not set
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||||||
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# CONFIG_PKG_USING_PAHOMQTT is not set
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||||||
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# CONFIG_PKG_USING_UMQTT is not set
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||||||
|
# CONFIG_PKG_USING_WEBCLIENT is not set
|
||||||
|
# CONFIG_PKG_USING_WEBNET is not set
|
||||||
|
# CONFIG_PKG_USING_MONGOOSE is not set
|
||||||
|
# CONFIG_PKG_USING_MYMQTT is not set
|
||||||
|
# CONFIG_PKG_USING_KAWAII_MQTT is not set
|
||||||
|
# CONFIG_PKG_USING_BC28_MQTT is not set
|
||||||
|
# CONFIG_PKG_USING_WEBTERMINAL is not set
|
||||||
|
# CONFIG_PKG_USING_LIBMODBUS is not set
|
||||||
|
# CONFIG_PKG_USING_FREEMODBUS is not set
|
||||||
|
# CONFIG_PKG_USING_NANOPB is not set
|
||||||
|
|
||||||
|
#
|
||||||
|
# Wi-Fi
|
||||||
|
#
|
||||||
|
|
||||||
|
#
|
||||||
|
# Marvell WiFi
|
||||||
|
#
|
||||||
|
# CONFIG_PKG_USING_WLANMARVELL is not set
|
||||||
|
|
||||||
|
#
|
||||||
|
# Wiced WiFi
|
||||||
|
#
|
||||||
|
# CONFIG_PKG_USING_WLAN_WICED is not set
|
||||||
|
# CONFIG_PKG_USING_RW007 is not set
|
||||||
|
# CONFIG_PKG_USING_COAP is not set
|
||||||
|
# CONFIG_PKG_USING_NOPOLL is not set
|
||||||
|
# CONFIG_PKG_USING_NETUTILS is not set
|
||||||
|
# CONFIG_PKG_USING_CMUX is not set
|
||||||
|
# CONFIG_PKG_USING_PPP_DEVICE is not set
|
||||||
|
# CONFIG_PKG_USING_AT_DEVICE is not set
|
||||||
|
# CONFIG_PKG_USING_ATSRV_SOCKET is not set
|
||||||
|
# CONFIG_PKG_USING_WIZNET is not set
|
||||||
|
# CONFIG_PKG_USING_ZB_COORDINATOR is not set
|
||||||
|
|
||||||
|
#
|
||||||
|
# IoT Cloud
|
||||||
|
#
|
||||||
|
# CONFIG_PKG_USING_ONENET is not set
|
||||||
|
# CONFIG_PKG_USING_GAGENT_CLOUD is not set
|
||||||
|
# CONFIG_PKG_USING_ALI_IOTKIT is not set
|
||||||
|
# CONFIG_PKG_USING_AZURE is not set
|
||||||
|
# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set
|
||||||
|
# CONFIG_PKG_USING_JIOT-C-SDK is not set
|
||||||
|
# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
|
||||||
|
# CONFIG_PKG_USING_JOYLINK is not set
|
||||||
|
# CONFIG_PKG_USING_EZ_IOT_OS is not set
|
||||||
|
# CONFIG_PKG_USING_IOTSHARP_SDK is not set
|
||||||
|
# CONFIG_PKG_USING_NIMBLE is not set
|
||||||
|
# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set
|
||||||
|
# CONFIG_PKG_USING_OTA_DOWNLOADER is not set
|
||||||
|
# CONFIG_PKG_USING_IPMSG is not set
|
||||||
|
# CONFIG_PKG_USING_LSSDP is not set
|
||||||
|
# CONFIG_PKG_USING_AIRKISS_OPEN is not set
|
||||||
|
# CONFIG_PKG_USING_LIBRWS is not set
|
||||||
|
# CONFIG_PKG_USING_TCPSERVER is not set
|
||||||
|
# CONFIG_PKG_USING_PROTOBUF_C is not set
|
||||||
|
# CONFIG_PKG_USING_DLT645 is not set
|
||||||
|
# CONFIG_PKG_USING_QXWZ is not set
|
||||||
|
# CONFIG_PKG_USING_SMTP_CLIENT is not set
|
||||||
|
# CONFIG_PKG_USING_ABUP_FOTA is not set
|
||||||
|
# CONFIG_PKG_USING_LIBCURL2RTT is not set
|
||||||
|
# CONFIG_PKG_USING_CAPNP is not set
|
||||||
|
# CONFIG_PKG_USING_AGILE_TELNET is not set
|
||||||
|
# CONFIG_PKG_USING_NMEALIB is not set
|
||||||
|
# CONFIG_PKG_USING_PDULIB is not set
|
||||||
|
# CONFIG_PKG_USING_BTSTACK is not set
|
||||||
|
# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set
|
||||||
|
# CONFIG_PKG_USING_WAYZ_IOTKIT is not set
|
||||||
|
# CONFIG_PKG_USING_MAVLINK is not set
|
||||||
|
# CONFIG_PKG_USING_BSAL is not set
|
||||||
|
# CONFIG_PKG_USING_AGILE_MODBUS is not set
|
||||||
|
# CONFIG_PKG_USING_AGILE_FTP is not set
|
||||||
|
# CONFIG_PKG_USING_EMBEDDEDPROTO is not set
|
||||||
|
# CONFIG_PKG_USING_RT_LINK_HW is not set
|
||||||
|
# CONFIG_PKG_USING_LORA_PKT_FWD is not set
|
||||||
|
# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set
|
||||||
|
# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set
|
||||||
|
# CONFIG_PKG_USING_HM is not set
|
||||||
|
# CONFIG_PKG_USING_SMALL_MODBUS is not set
|
||||||
|
# CONFIG_PKG_USING_NET_SERVER is not set
|
||||||
|
# CONFIG_PKG_USING_ZFTP is not set
|
||||||
|
|
||||||
|
#
|
||||||
|
# security packages
|
||||||
|
#
|
||||||
|
# CONFIG_PKG_USING_MBEDTLS is not set
|
||||||
|
# CONFIG_PKG_USING_LIBSODIUM is not set
|
||||||
|
# CONFIG_PKG_USING_LIBHYDROGEN is not set
|
||||||
|
# CONFIG_PKG_USING_TINYCRYPT is not set
|
||||||
|
# CONFIG_PKG_USING_TFM is not set
|
||||||
|
# CONFIG_PKG_USING_YD_CRYPTO is not set
|
||||||
|
|
||||||
|
#
|
||||||
|
# language packages
|
||||||
|
#
|
||||||
|
|
||||||
|
#
|
||||||
|
# JSON: JavaScript Object Notation, a lightweight data-interchange format
|
||||||
|
#
|
||||||
|
# CONFIG_PKG_USING_CJSON is not set
|
||||||
|
# CONFIG_PKG_USING_LJSON is not set
|
||||||
|
# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set
|
||||||
|
# CONFIG_PKG_USING_RAPIDJSON is not set
|
||||||
|
# CONFIG_PKG_USING_JSMN is not set
|
||||||
|
# CONFIG_PKG_USING_AGILE_JSMN is not set
|
||||||
|
# CONFIG_PKG_USING_PARSON is not set
|
||||||
|
|
||||||
|
#
|
||||||
|
# XML: Extensible Markup Language
|
||||||
|
#
|
||||||
|
# CONFIG_PKG_USING_SIMPLE_XML is not set
|
||||||
|
# CONFIG_PKG_USING_EZXML is not set
|
||||||
|
# CONFIG_PKG_USING_LUATOS_SOC is not set
|
||||||
|
# CONFIG_PKG_USING_LUA is not set
|
||||||
|
# CONFIG_PKG_USING_JERRYSCRIPT is not set
|
||||||
|
# CONFIG_PKG_USING_MICROPYTHON is not set
|
||||||
|
# CONFIG_PKG_USING_PIKASCRIPT is not set
|
||||||
|
# CONFIG_PKG_USING_RTT_RUST is not set
|
||||||
|
|
||||||
|
#
|
||||||
|
# multimedia packages
|
||||||
|
#
|
||||||
|
|
||||||
|
#
|
||||||
|
# LVGL: powerful and easy-to-use embedded GUI library
|
||||||
|
#
|
||||||
|
# CONFIG_PKG_USING_LVGL is not set
|
||||||
|
# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
|
||||||
|
# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set
|
||||||
|
# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set
|
||||||
|
|
||||||
|
#
|
||||||
|
# u8g2: a monochrome graphic library
|
||||||
|
#
|
||||||
|
# CONFIG_PKG_USING_U8G2_OFFICIAL is not set
|
||||||
|
# CONFIG_PKG_USING_U8G2 is not set
|
||||||
|
# CONFIG_PKG_USING_OPENMV is not set
|
||||||
|
# CONFIG_PKG_USING_MUPDF is not set
|
||||||
|
# CONFIG_PKG_USING_STEMWIN is not set
|
||||||
|
# CONFIG_PKG_USING_WAVPLAYER is not set
|
||||||
|
# CONFIG_PKG_USING_TJPGD is not set
|
||||||
|
# CONFIG_PKG_USING_PDFGEN is not set
|
||||||
|
# CONFIG_PKG_USING_HELIX is not set
|
||||||
|
# CONFIG_PKG_USING_AZUREGUIX is not set
|
||||||
|
# CONFIG_PKG_USING_TOUCHGFX2RTT is not set
|
||||||
|
# CONFIG_PKG_USING_NUEMWIN is not set
|
||||||
|
# CONFIG_PKG_USING_MP3PLAYER is not set
|
||||||
|
# CONFIG_PKG_USING_TINYJPEG is not set
|
||||||
|
# CONFIG_PKG_USING_UGUI is not set
|
||||||
|
|
||||||
|
#
|
||||||
|
# PainterEngine: A cross-platform graphics application framework written in C language
|
||||||
|
#
|
||||||
|
# CONFIG_PKG_USING_PAINTERENGINE is not set
|
||||||
|
# CONFIG_PKG_USING_PAINTERENGINE_AUX is not set
|
||||||
|
# CONFIG_PKG_USING_MCURSES is not set
|
||||||
|
# CONFIG_PKG_USING_TERMBOX is not set
|
||||||
|
# CONFIG_PKG_USING_VT100 is not set
|
||||||
|
# CONFIG_PKG_USING_QRCODE is not set
|
||||||
|
# CONFIG_PKG_USING_GUIENGINE is not set
|
||||||
|
|
||||||
|
#
|
||||||
|
# tools packages
|
||||||
|
#
|
||||||
|
# CONFIG_PKG_USING_CMBACKTRACE is not set
|
||||||
|
# CONFIG_PKG_USING_EASYFLASH is not set
|
||||||
|
# CONFIG_PKG_USING_EASYLOGGER is not set
|
||||||
|
# CONFIG_PKG_USING_SYSTEMVIEW is not set
|
||||||
|
# CONFIG_PKG_USING_SEGGER_RTT is not set
|
||||||
|
# CONFIG_PKG_USING_RDB is not set
|
||||||
|
# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
|
||||||
|
# CONFIG_PKG_USING_ULOG_FILE is not set
|
||||||
|
# CONFIG_PKG_USING_LOGMGR is not set
|
||||||
|
# CONFIG_PKG_USING_ADBD is not set
|
||||||
|
# CONFIG_PKG_USING_COREMARK is not set
|
||||||
|
# CONFIG_PKG_USING_DHRYSTONE is not set
|
||||||
|
# CONFIG_PKG_USING_MEMORYPERF is not set
|
||||||
|
# CONFIG_PKG_USING_NR_MICRO_SHELL is not set
|
||||||
|
# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set
|
||||||
|
# CONFIG_PKG_USING_LUNAR_CALENDAR is not set
|
||||||
|
# CONFIG_PKG_USING_BS8116A is not set
|
||||||
|
# CONFIG_PKG_USING_GPS_RMC is not set
|
||||||
|
# CONFIG_PKG_USING_URLENCODE is not set
|
||||||
|
# CONFIG_PKG_USING_UMCN is not set
|
||||||
|
# CONFIG_PKG_USING_LWRB2RTT is not set
|
||||||
|
# CONFIG_PKG_USING_CPU_USAGE is not set
|
||||||
|
# CONFIG_PKG_USING_GBK2UTF8 is not set
|
||||||
|
# CONFIG_PKG_USING_VCONSOLE is not set
|
||||||
|
# CONFIG_PKG_USING_KDB is not set
|
||||||
|
# CONFIG_PKG_USING_WAMR is not set
|
||||||
|
# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set
|
||||||
|
# CONFIG_PKG_USING_LWLOG is not set
|
||||||
|
# CONFIG_PKG_USING_ANV_TRACE is not set
|
||||||
|
# CONFIG_PKG_USING_ANV_MEMLEAK is not set
|
||||||
|
# CONFIG_PKG_USING_ANV_TESTSUIT is not set
|
||||||
|
# CONFIG_PKG_USING_ANV_BENCH is not set
|
||||||
|
# CONFIG_PKG_USING_DEVMEM is not set
|
||||||
|
# CONFIG_PKG_USING_REGEX is not set
|
||||||
|
# CONFIG_PKG_USING_MEM_SANDBOX is not set
|
||||||
|
# CONFIG_PKG_USING_SOLAR_TERMS is not set
|
||||||
|
# CONFIG_PKG_USING_GAN_ZHI is not set
|
||||||
|
# CONFIG_PKG_USING_FDT is not set
|
||||||
|
# CONFIG_PKG_USING_CBOX is not set
|
||||||
|
# CONFIG_PKG_USING_SNOWFLAKE is not set
|
||||||
|
# CONFIG_PKG_USING_HASH_MATCH is not set
|
||||||
|
# CONFIG_PKG_USING_FIRE_PID_CURVE is not set
|
||||||
|
# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set
|
||||||
|
|
||||||
|
#
|
||||||
|
# system packages
|
||||||
|
#
|
||||||
|
|
||||||
|
#
|
||||||
|
# enhanced kernel services
|
||||||
|
#
|
||||||
|
# CONFIG_PKG_USING_RT_MEMCPY_CM is not set
|
||||||
|
# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set
|
||||||
|
# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set
|
||||||
|
|
||||||
|
#
|
||||||
|
# acceleration: Assembly language or algorithmic acceleration packages
|
||||||
|
#
|
||||||
|
# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set
|
||||||
|
# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set
|
||||||
|
# CONFIG_PKG_USING_QFPLIB_M3 is not set
|
||||||
|
|
||||||
|
#
|
||||||
|
# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard
|
||||||
|
#
|
||||||
|
# CONFIG_PKG_USING_CMSIS_5 is not set
|
||||||
|
# CONFIG_PKG_USING_CMSIS_RTOS1 is not set
|
||||||
|
# CONFIG_PKG_USING_CMSIS_RTOS2 is not set
|
||||||
|
|
||||||
|
#
|
||||||
|
# Micrium: Micrium software products porting for RT-Thread
|
||||||
|
#
|
||||||
|
# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set
|
||||||
|
# CONFIG_PKG_USING_UCOSII_WRAPPER is not set
|
||||||
|
# CONFIG_PKG_USING_UC_CRC is not set
|
||||||
|
# CONFIG_PKG_USING_UC_CLK is not set
|
||||||
|
# CONFIG_PKG_USING_UC_COMMON is not set
|
||||||
|
# CONFIG_PKG_USING_UC_MODBUS is not set
|
||||||
|
# CONFIG_PKG_USING_RTDUINO is not set
|
||||||
|
# CONFIG_PKG_USING_CAIRO is not set
|
||||||
|
# CONFIG_PKG_USING_PIXMAN is not set
|
||||||
|
# CONFIG_PKG_USING_PARTITION is not set
|
||||||
|
# CONFIG_PKG_USING_PERF_COUNTER is not set
|
||||||
|
# CONFIG_PKG_USING_FLASHDB is not set
|
||||||
|
# CONFIG_PKG_USING_SQLITE is not set
|
||||||
|
# CONFIG_PKG_USING_RTI is not set
|
||||||
|
# CONFIG_PKG_USING_DFS_YAFFS is not set
|
||||||
|
# CONFIG_PKG_USING_LITTLEFS is not set
|
||||||
|
# CONFIG_PKG_USING_DFS_JFFS2 is not set
|
||||||
|
# CONFIG_PKG_USING_DFS_UFFS is not set
|
||||||
|
# CONFIG_PKG_USING_LWEXT4 is not set
|
||||||
|
# CONFIG_PKG_USING_THREAD_POOL is not set
|
||||||
|
# CONFIG_PKG_USING_ROBOTS is not set
|
||||||
|
# CONFIG_PKG_USING_EV is not set
|
||||||
|
# CONFIG_PKG_USING_SYSWATCH is not set
|
||||||
|
# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set
|
||||||
|
# CONFIG_PKG_USING_PLCCORE is not set
|
||||||
|
# CONFIG_PKG_USING_RAMDISK is not set
|
||||||
|
# CONFIG_PKG_USING_MININI is not set
|
||||||
|
# CONFIG_PKG_USING_QBOOT is not set
|
||||||
|
# CONFIG_PKG_USING_PPOOL is not set
|
||||||
|
# CONFIG_PKG_USING_OPENAMP is not set
|
||||||
|
# CONFIG_PKG_USING_LPM is not set
|
||||||
|
# CONFIG_PKG_USING_TLSF is not set
|
||||||
|
# CONFIG_PKG_USING_EVENT_RECORDER is not set
|
||||||
|
# CONFIG_PKG_USING_ARM_2D is not set
|
||||||
|
# CONFIG_PKG_USING_MCUBOOT is not set
|
||||||
|
# CONFIG_PKG_USING_TINYUSB is not set
|
||||||
|
# CONFIG_PKG_USING_CHERRYUSB is not set
|
||||||
|
# CONFIG_PKG_USING_KMULTI_RTIMER is not set
|
||||||
|
# CONFIG_PKG_USING_TFDB is not set
|
||||||
|
# CONFIG_PKG_USING_QPC is not set
|
||||||
|
|
||||||
|
#
|
||||||
|
# peripheral libraries and drivers
|
||||||
|
#
|
||||||
|
# CONFIG_PKG_USING_SENSORS_DRIVERS is not set
|
||||||
|
# CONFIG_PKG_USING_REALTEK_AMEBA is not set
|
||||||
|
# CONFIG_PKG_USING_SHT2X is not set
|
||||||
|
# CONFIG_PKG_USING_SHT3X is not set
|
||||||
|
# CONFIG_PKG_USING_ADT74XX is not set
|
||||||
|
# CONFIG_PKG_USING_AS7341 is not set
|
||||||
|
# CONFIG_PKG_USING_STM32_SDIO is not set
|
||||||
|
# CONFIG_PKG_USING_RTT_ESP_IDF is not set
|
||||||
|
# CONFIG_PKG_USING_ICM20608 is not set
|
||||||
|
# CONFIG_PKG_USING_BUTTON is not set
|
||||||
|
# CONFIG_PKG_USING_PCF8574 is not set
|
||||||
|
# CONFIG_PKG_USING_SX12XX is not set
|
||||||
|
# CONFIG_PKG_USING_SIGNAL_LED is not set
|
||||||
|
# CONFIG_PKG_USING_LEDBLINK is not set
|
||||||
|
# CONFIG_PKG_USING_LITTLED is not set
|
||||||
|
# CONFIG_PKG_USING_LKDGUI is not set
|
||||||
|
# CONFIG_PKG_USING_NRF5X_SDK is not set
|
||||||
|
# CONFIG_PKG_USING_NRFX is not set
|
||||||
|
# CONFIG_PKG_USING_WM_LIBRARIES is not set
|
||||||
|
# CONFIG_PKG_USING_KENDRYTE_SDK is not set
|
||||||
|
# CONFIG_PKG_USING_INFRARED is not set
|
||||||
|
# CONFIG_PKG_USING_MULTI_INFRARED is not set
|
||||||
|
# CONFIG_PKG_USING_AGILE_BUTTON is not set
|
||||||
|
# CONFIG_PKG_USING_AGILE_LED is not set
|
||||||
|
# CONFIG_PKG_USING_AT24CXX is not set
|
||||||
|
# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set
|
||||||
|
# CONFIG_PKG_USING_AD7746 is not set
|
||||||
|
# CONFIG_PKG_USING_PCA9685 is not set
|
||||||
|
# CONFIG_PKG_USING_I2C_TOOLS is not set
|
||||||
|
# CONFIG_PKG_USING_NRF24L01 is not set
|
||||||
|
# CONFIG_PKG_USING_TOUCH_DRIVERS is not set
|
||||||
|
# CONFIG_PKG_USING_MAX17048 is not set
|
||||||
|
# CONFIG_PKG_USING_RPLIDAR is not set
|
||||||
|
# CONFIG_PKG_USING_AS608 is not set
|
||||||
|
# CONFIG_PKG_USING_RC522 is not set
|
||||||
|
# CONFIG_PKG_USING_WS2812B is not set
|
||||||
|
# CONFIG_PKG_USING_EMBARC_BSP is not set
|
||||||
|
# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set
|
||||||
|
# CONFIG_PKG_USING_MULTI_RTIMER is not set
|
||||||
|
# CONFIG_PKG_USING_MAX7219 is not set
|
||||||
|
# CONFIG_PKG_USING_BEEP is not set
|
||||||
|
# CONFIG_PKG_USING_EASYBLINK is not set
|
||||||
|
# CONFIG_PKG_USING_PMS_SERIES is not set
|
||||||
|
# CONFIG_PKG_USING_CAN_YMODEM is not set
|
||||||
|
# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set
|
||||||
|
# CONFIG_PKG_USING_QLED is not set
|
||||||
|
# CONFIG_PKG_USING_PAJ7620 is not set
|
||||||
|
# CONFIG_PKG_USING_AGILE_CONSOLE is not set
|
||||||
|
# CONFIG_PKG_USING_LD3320 is not set
|
||||||
|
# CONFIG_PKG_USING_WK2124 is not set
|
||||||
|
# CONFIG_PKG_USING_LY68L6400 is not set
|
||||||
|
# CONFIG_PKG_USING_DM9051 is not set
|
||||||
|
# CONFIG_PKG_USING_SSD1306 is not set
|
||||||
|
# CONFIG_PKG_USING_QKEY is not set
|
||||||
|
# CONFIG_PKG_USING_RS485 is not set
|
||||||
|
# CONFIG_PKG_USING_RS232 is not set
|
||||||
|
# CONFIG_PKG_USING_NES is not set
|
||||||
|
# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set
|
||||||
|
# CONFIG_PKG_USING_VDEVICE is not set
|
||||||
|
# CONFIG_PKG_USING_SGM706 is not set
|
||||||
|
# CONFIG_PKG_USING_STM32WB55_SDK is not set
|
||||||
|
# CONFIG_PKG_USING_RDA58XX is not set
|
||||||
|
# CONFIG_PKG_USING_LIBNFC is not set
|
||||||
|
# CONFIG_PKG_USING_MFOC is not set
|
||||||
|
# CONFIG_PKG_USING_TMC51XX is not set
|
||||||
|
# CONFIG_PKG_USING_TCA9534 is not set
|
||||||
|
# CONFIG_PKG_USING_KOBUKI is not set
|
||||||
|
# CONFIG_PKG_USING_ROSSERIAL is not set
|
||||||
|
# CONFIG_PKG_USING_MICRO_ROS is not set
|
||||||
|
# CONFIG_PKG_USING_MCP23008 is not set
|
||||||
|
# CONFIG_PKG_USING_BLUETRUM_SDK is not set
|
||||||
|
# CONFIG_PKG_USING_MISAKA_AT24CXX is not set
|
||||||
|
# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set
|
||||||
|
# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set
|
||||||
|
# CONFIG_PKG_USING_BL_MCU_SDK is not set
|
||||||
|
# CONFIG_PKG_USING_SOFT_SERIAL is not set
|
||||||
|
# CONFIG_PKG_USING_MB85RS16 is not set
|
||||||
|
# CONFIG_PKG_USING_CW2015 is not set
|
||||||
|
# CONFIG_PKG_USING_RFM300 is not set
|
||||||
|
# CONFIG_PKG_USING_IO_INPUT_FILTER is not set
|
||||||
|
|
||||||
|
#
|
||||||
|
# AI packages
|
||||||
|
#
|
||||||
|
# CONFIG_PKG_USING_LIBANN is not set
|
||||||
|
# CONFIG_PKG_USING_NNOM is not set
|
||||||
|
# CONFIG_PKG_USING_ONNX_BACKEND is not set
|
||||||
|
# CONFIG_PKG_USING_ONNX_PARSER is not set
|
||||||
|
# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set
|
||||||
|
# CONFIG_PKG_USING_ELAPACK is not set
|
||||||
|
# CONFIG_PKG_USING_ULAPACK is not set
|
||||||
|
# CONFIG_PKG_USING_QUEST is not set
|
||||||
|
# CONFIG_PKG_USING_NAXOS is not set
|
||||||
|
|
||||||
|
#
|
||||||
|
# miscellaneous packages
|
||||||
|
#
|
||||||
|
|
||||||
|
#
|
||||||
|
# project laboratory
|
||||||
|
#
|
||||||
|
|
||||||
|
#
|
||||||
|
# samples: kernel and components samples
|
||||||
|
#
|
||||||
|
# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
|
||||||
|
# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
|
||||||
|
# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
|
||||||
|
# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
|
||||||
|
|
||||||
|
#
|
||||||
|
# entertainment: terminal games and other interesting software packages
|
||||||
|
#
|
||||||
|
# CONFIG_PKG_USING_CMATRIX is not set
|
||||||
|
# CONFIG_PKG_USING_SL is not set
|
||||||
|
# CONFIG_PKG_USING_CAL is not set
|
||||||
|
# CONFIG_PKG_USING_ACLOCK is not set
|
||||||
|
# CONFIG_PKG_USING_THREES is not set
|
||||||
|
# CONFIG_PKG_USING_2048 is not set
|
||||||
|
# CONFIG_PKG_USING_SNAKE is not set
|
||||||
|
# CONFIG_PKG_USING_TETRIS is not set
|
||||||
|
# CONFIG_PKG_USING_DONUT is not set
|
||||||
|
# CONFIG_PKG_USING_COWSAY is not set
|
||||||
|
# CONFIG_PKG_USING_LIBCSV is not set
|
||||||
|
# CONFIG_PKG_USING_OPTPARSE is not set
|
||||||
|
# CONFIG_PKG_USING_FASTLZ is not set
|
||||||
|
# CONFIG_PKG_USING_MINILZO is not set
|
||||||
|
# CONFIG_PKG_USING_QUICKLZ is not set
|
||||||
|
# CONFIG_PKG_USING_LZMA is not set
|
||||||
|
# CONFIG_PKG_USING_MULTIBUTTON is not set
|
||||||
|
# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set
|
||||||
|
# CONFIG_PKG_USING_CANFESTIVAL is not set
|
||||||
|
# CONFIG_PKG_USING_ZLIB is not set
|
||||||
|
# CONFIG_PKG_USING_MINIZIP is not set
|
||||||
|
# CONFIG_PKG_USING_HEATSHRINK is not set
|
||||||
|
# CONFIG_PKG_USING_DSTR is not set
|
||||||
|
# CONFIG_PKG_USING_TINYFRAME is not set
|
||||||
|
# CONFIG_PKG_USING_KENDRYTE_DEMO is not set
|
||||||
|
# CONFIG_PKG_USING_DIGITALCTRL is not set
|
||||||
|
# CONFIG_PKG_USING_UPACKER is not set
|
||||||
|
# CONFIG_PKG_USING_UPARAM is not set
|
||||||
|
# CONFIG_PKG_USING_HELLO is not set
|
||||||
|
# CONFIG_PKG_USING_VI is not set
|
||||||
|
# CONFIG_PKG_USING_KI is not set
|
||||||
|
# CONFIG_PKG_USING_ARMv7M_DWT is not set
|
||||||
|
# CONFIG_PKG_USING_UKAL is not set
|
||||||
|
# CONFIG_PKG_USING_CRCLIB is not set
|
||||||
|
# CONFIG_PKG_USING_LWGPS is not set
|
||||||
|
# CONFIG_PKG_USING_STATE_MACHINE is not set
|
||||||
|
# CONFIG_PKG_USING_DESIGN_PATTERN is not set
|
||||||
|
# CONFIG_PKG_USING_CONTROLLER is not set
|
||||||
|
# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set
|
||||||
|
# CONFIG_PKG_USING_MFBD is not set
|
||||||
|
# CONFIG_PKG_USING_SLCAN2RTT is not set
|
||||||
|
# CONFIG_PKG_USING_SOEM is not set
|
||||||
|
|
||||||
|
#
|
||||||
|
# Hardware Drivers Config
|
||||||
|
#
|
||||||
|
CONFIG_SOC_SERIES_GD32F4xx=y
|
||||||
|
CONFIG_SOC_GD32470Z=y
|
||||||
|
|
||||||
|
#
|
||||||
|
# Onboard Peripheral Drivers
|
||||||
|
#
|
||||||
|
|
||||||
|
#
|
||||||
|
# On-chip Peripheral Drivers
|
||||||
|
#
|
||||||
|
CONFIG_BSP_USING_GPIO=y
|
||||||
|
CONFIG_BSP_USING_UART=y
|
||||||
|
CONFIG_BSP_USING_UART0=y
|
||||||
|
# CONFIG_BSP_UART0_RX_USING_DMA is not set
|
||||||
|
# CONFIG_BSP_USING_UART1 is not set
|
||||||
|
# CONFIG_BSP_USING_UART2 is not set
|
||||||
|
# CONFIG_BSP_USING_UART3 is not set
|
||||||
|
# CONFIG_BSP_USING_UART4 is not set
|
||||||
|
# CONFIG_BSP_USING_UART5 is not set
|
||||||
|
# CONFIG_BSP_USING_UART6 is not set
|
||||||
|
# CONFIG_BSP_USING_UART7 is not set
|
||||||
|
# CONFIG_BSP_USING_SPI is not set
|
||||||
|
# CONFIG_BSP_USING_I2C1 is not set
|
||||||
|
# CONFIG_BSP_USING_ADC is not set
|
||||||
|
# CONFIG_BSP_USING_TIM is not set
|
||||||
|
# CONFIG_BSP_USING_ONCHIP_RTC is not set
|
||||||
|
# CONFIG_BSP_USING_WDT is not set
|
||||||
|
# CONFIG_BSP_USING_SDIO is not set
|
||||||
|
# CONFIG_BSP_USING_USBD is not set
|
||||||
|
# CONFIG_BSP_USING_USBH is not set
|
||||||
|
|
||||||
|
#
|
||||||
|
# Board extended module Drivers
|
||||||
|
#
|
||||||
|
|
@ -0,0 +1,21 @@
|
||||||
|
mainmenu "RT-Thread Configuration"
|
||||||
|
|
||||||
|
config BSP_DIR
|
||||||
|
string
|
||||||
|
option env="BSP_ROOT"
|
||||||
|
default "."
|
||||||
|
|
||||||
|
config RTT_DIR
|
||||||
|
string
|
||||||
|
option env="RTT_ROOT"
|
||||||
|
default "../../../.."
|
||||||
|
|
||||||
|
config PKGS_DIR
|
||||||
|
string
|
||||||
|
option env="PKGS_ROOT"
|
||||||
|
default "packages"
|
||||||
|
|
||||||
|
source "$RTT_DIR/Kconfig"
|
||||||
|
source "$PKGS_DIR/Kconfig"
|
||||||
|
source "../libraries/Kconfig"
|
||||||
|
source "board/Kconfig"
|
||||||
|
|
@ -0,0 +1,116 @@
|
||||||
|
# GD32470-LCKFB梁山派开发板BSP说明
|
||||||
|
|
||||||
|
## 简介
|
||||||
|
|
||||||
|
GD32470Z-LCKFB梁山派是立创开发板推出的一款GD32F470系列的开发板，最高主频高达240M，该开发板具有丰富的板载资源，是基于GD32F470ZGT6的全国产化开源开发板，图片如下：
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
> 2022年12月05号后立创·梁山派开发板主控从GD32F450ZGT6升级到了GD32F470ZGT6 两款芯片兼容主要差别GD32F450ZGT6主频200、SDRAM 256K，GD32F470ZGT6主频240、SDRAM 512K。
|
||||||
|
|
||||||
|
该开发板常用 **板载资源** 如下：
|
||||||
|
|
||||||
|
- GD32F470ZGT6，主频 240MHz，CPU内核：ARM Cortex-M4，1024KB FLASH ，512KB RAM
|
||||||
|
- 常用外设
|
||||||
|
|
||||||
|
- 用户LED ：4个，LED1 (PE3），LED2（PD7），LED3（PG3），LED4（PA5）
|
||||||
|
- 电源指示灯：一个红色LED
|
||||||
|
- 按键：3个，KEY_UP（PA0），RESET(NRST)，BOOT0（PB2）
|
||||||
|
- General TM * 10、Advanced TM * 2、Basic TM * 2
|
||||||
|
- SysTick * 1
|
||||||
|
- 看门狗 * 2
|
||||||
|
- RTC * 1
|
||||||
|
- USART * 4、UART * 4
|
||||||
|
- I2C * 3、I2S * 2
|
||||||
|
- SPI * 6
|
||||||
|
- SDIO * 1
|
||||||
|
- CAN * 2
|
||||||
|
- USBFS+HS
|
||||||
|
- 以太网 * 1
|
||||||
|
- TFT-LCD
|
||||||
|
- EXMC/SDRAM * 1
|
||||||
|
- ADC * 3
|
||||||
|
- DAC * 2
|
||||||
|
- 最多支持114GPIOs
|
||||||
|
- 调试接口：CMSIS-DAP
|
||||||
|
- 支持RGB接口和MCU屏幕接口
|
||||||
|
- 一路SDIO-TF卡
|
||||||
|
- SPI Flash：W25Q64
|
||||||
|
- SDRAM：W9825G6KH-6I
|
||||||
|
- 一路Type-C USB
|
||||||
|
- 调试接口引出了SWD和UART
|
||||||
|
- 双2*20PIN 2.54排针引出了68个可编程IO
|
||||||
|
- 开发板更多信息请查看[立创开发板官网](https://lckfb.com/)
|
||||||
|
|
||||||
|
## 外设支持
|
||||||
|
|
||||||
|
本 BSP 目前对外设的支持情况如下：
|
||||||
|
|
||||||
|
| **片上外设** | **支持情况** | **备注** |
|
||||||
|
|:-------- |:--------:|:-------------------------------- |
|
||||||
|
| GPIO | 支持 | PA0, PA1... ---> PIN: 0, 1...113 |
|
||||||
|
| UART | 支持 | UART0 - UART7 |
|
||||||
|
| **扩展模块** | **支持情况** | **备注** |
|
||||||
|
| 暂无 | 暂不支持 | 暂不支持 |
|
||||||
|
|
||||||
|
## 使用说明
|
||||||
|
|
||||||
|
使用说明分为如下两个章节：
|
||||||
|
|
||||||
|
- 快速上手
|
||||||
|
|
||||||
|
本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。
|
||||||
|
|
||||||
|
- 进阶使用
|
||||||
|
|
||||||
|
本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。
|
||||||
|
|
||||||
|
### 快速上手
|
||||||
|
|
||||||
|
本 BSP 为开发者提供 MDK5工程，支持 GCC 开发环境，也可使用RT-Thread Studio开发。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。
|
||||||
|
|
||||||
|
#### 硬件连接
|
||||||
|
|
||||||
|
使用调试器连接开发板到 PC，使用USB2TTL连接USART0，并给开发板供电。
|
||||||
|
|
||||||
|
#### 编译下载
|
||||||
|
|
||||||
|
双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。
|
||||||
|
|
||||||
|
> 工程默认配置使用 CMSIS-DAP 仿真器下载程序，在通过 CMSIS-DAP 连接开发板的基础上，点击下载按钮即可下载程序到开发板
|
||||||
|
|
||||||
|
#### 运行结果
|
||||||
|
|
||||||
|
下载程序成功之后，系统会自动运行，LED 闪烁。
|
||||||
|
|
||||||
|
连接开发板对应串口到 PC , 在终端工具里打开相应的串口（115200-8-1-N），复位设备后，可以看到 RT-Thread 的输出信息:
|
||||||
|
|
||||||
|
```bash
|
||||||
|
\ | /
|
||||||
|
- RT - Thread Operating System
|
||||||
|
/ | \ 5.0.0 build Mar 3 2023 00:43:44
|
||||||
|
2006 - 2022 Copyright by RT-Thread team
|
||||||
|
msh />
|
||||||
|
```
|
||||||
|
|
||||||
|
### 进阶使用
|
||||||
|
|
||||||
|
此 BSP 默认只开启了 GPIO 和 串口1的功能，如果需使用高级功能，需要利用 ENV 工具对BSP 进行配置，步骤如下：
|
||||||
|
|
||||||
|
1. 在 bsp 下打开 env 工具。
|
||||||
|
|
||||||
|
2. 输入`menuconfig`命令配置工程，配置好之后保存退出。
|
||||||
|
|
||||||
|
3. 输入`pkgs --update`命令更新软件包。
|
||||||
|
|
||||||
|
4. 输入`scons --target=mdk4/mdk5/iar` 命令重新生成工程。
|
||||||
|
|
||||||
|
## 注意事项
|
||||||
|
|
||||||
|
暂无
|
||||||
|
|
||||||
|
## 联系人信息
|
||||||
|
|
||||||
|
维护人:
|
||||||
|
|
||||||
|
- [yuanzihao](https://github.com/zihao-yuan/), 邮箱：<y@yzh.email>
|
||||||
|
|
@ -0,0 +1,15 @@
|
||||||
|
# for module compiling
|
||||||
|
import os
|
||||||
|
Import('RTT_ROOT')
|
||||||
|
from building import *
|
||||||
|
|
||||||
|
cwd = GetCurrentDir()
|
||||||
|
objs = []
|
||||||
|
list = os.listdir(cwd)
|
||||||
|
|
||||||
|
for d in list:
|
||||||
|
path = os.path.join(cwd, d)
|
||||||
|
if os.path.isfile(os.path.join(path, 'SConscript')):
|
||||||
|
objs = objs + SConscript(os.path.join(d, 'SConscript'))
|
||||||
|
|
||||||
|
Return('objs')
|
||||||
|
|
@ -0,0 +1,60 @@
|
||||||
|
import os
|
||||||
|
import sys
|
||||||
|
import rtconfig
|
||||||
|
|
||||||
|
if os.getenv('RTT_ROOT'):
|
||||||
|
RTT_ROOT = os.getenv('RTT_ROOT')
|
||||||
|
else:
|
||||||
|
RTT_ROOT = os.path.normpath(os.getcwd() + '/../../../..')
|
||||||
|
|
||||||
|
sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
|
||||||
|
try:
|
||||||
|
from building import *
|
||||||
|
except:
|
||||||
|
print('Cannot found RT-Thread root directory, please check RTT_ROOT')
|
||||||
|
print(RTT_ROOT)
|
||||||
|
exit(-1)
|
||||||
|
|
||||||
|
TARGET = 'rtthread.' + rtconfig.TARGET_EXT
|
||||||
|
|
||||||
|
DefaultEnvironment(tools=[])
|
||||||
|
env = Environment(tools = ['mingw'],
|
||||||
|
AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
|
||||||
|
CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
|
||||||
|
AR = rtconfig.AR, ARFLAGS = '-rc',
|
||||||
|
CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
|
||||||
|
LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
|
||||||
|
env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
|
||||||
|
|
||||||
|
if rtconfig.PLATFORM in ['iccarm']:
|
||||||
|
env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
|
||||||
|
env.Replace(ARFLAGS = [''])
|
||||||
|
env.Replace(LINKCOM = env["LINKCOM"] + ' --map rtthread.map')
|
||||||
|
|
||||||
|
Export('RTT_ROOT')
|
||||||
|
Export('rtconfig')
|
||||||
|
|
||||||
|
SDK_ROOT = os.path.abspath('./')
|
||||||
|
|
||||||
|
if os.path.exists(SDK_ROOT + '/libraries'):
|
||||||
|
libraries_path_prefix = SDK_ROOT + '/libraries'
|
||||||
|
else:
|
||||||
|
libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries'
|
||||||
|
|
||||||
|
SDK_LIB = libraries_path_prefix
|
||||||
|
Export('SDK_LIB')
|
||||||
|
|
||||||
|
# prepare building environment
|
||||||
|
objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
|
||||||
|
|
||||||
|
gd32_library = 'GD32F4xx_Firmware_Library'
|
||||||
|
rtconfig.BSP_LIBRARY_TYPE = gd32_library
|
||||||
|
|
||||||
|
# include libraries
|
||||||
|
objs.extend(SConscript(os.path.join(libraries_path_prefix, gd32_library, 'SConscript')))
|
||||||
|
|
||||||
|
# include drivers
|
||||||
|
objs.extend(SConscript(os.path.join(libraries_path_prefix, 'gd32_drivers', 'SConscript')))
|
||||||
|
|
||||||
|
# make a building
|
||||||
|
DoBuilding(TARGET, objs)
|
||||||
|
|
@ -0,0 +1,15 @@
|
||||||
|
from building import *
|
||||||
|
import os
|
||||||
|
|
||||||
|
cwd = GetCurrentDir()
|
||||||
|
src = Glob('*.c')
|
||||||
|
CPPPATH = [cwd]
|
||||||
|
|
||||||
|
group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
|
||||||
|
|
||||||
|
list = os.listdir(cwd)
|
||||||
|
for item in list:
|
||||||
|
if os.path.isfile(os.path.join(cwd, item, 'SConscript')):
|
||||||
|
group = group + SConscript(os.path.join(item, 'SConscript'))
|
||||||
|
|
||||||
|
Return('group')
|
||||||
|
|
@ -0,0 +1,36 @@
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2006-2023, RT-Thread Development Team
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
|
*
|
||||||
|
* Change Logs:
|
||||||
|
* Date Author Notes
|
||||||
|
* 2021-08-20 BruceOu first implementation
|
||||||
|
* 2023-03-05 yuanzihao change the LED pins
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <stdio.h>
|
||||||
|
#include <rtthread.h>
|
||||||
|
#include <rtdevice.h>
|
||||||
|
#include <board.h>
|
||||||
|
|
||||||
|
/* defined the LED1 pin: PE3 */
|
||||||
|
#define LED1_PIN GET_PIN(E, 3)
|
||||||
|
|
||||||
|
int main(void)
|
||||||
|
{
|
||||||
|
int count = 1;
|
||||||
|
|
||||||
|
/* set LED1 pin mode to output */
|
||||||
|
rt_pin_mode(LED1_PIN, PIN_MODE_OUTPUT);
|
||||||
|
|
||||||
|
while (count++)
|
||||||
|
{
|
||||||
|
rt_pin_write(LED1_PIN, PIN_HIGH);
|
||||||
|
rt_thread_mdelay(500);
|
||||||
|
rt_pin_write(LED1_PIN, PIN_LOW);
|
||||||
|
rt_thread_mdelay(500);
|
||||||
|
}
|
||||||
|
|
||||||
|
return RT_EOK;
|
||||||
|
}
|
||||||
|
|
@ -0,0 +1,241 @@
|
||||||
|
menu "Hardware Drivers Config"
|
||||||
|
|
||||||
|
config SOC_SERIES_GD32F4xx
|
||||||
|
bool
|
||||||
|
default y
|
||||||
|
|
||||||
|
config SOC_GD32470Z
|
||||||
|
bool
|
||||||
|
select SOC_SERIES_GD32F4xx
|
||||||
|
select RT_USING_COMPONENTS_INIT
|
||||||
|
select RT_USING_USER_MAIN
|
||||||
|
default y
|
||||||
|
|
||||||
|
menu "Onboard Peripheral Drivers"
|
||||||
|
|
||||||
|
endmenu
|
||||||
|
|
||||||
|
menu "On-chip Peripheral Drivers"
|
||||||
|
|
||||||
|
config BSP_USING_GPIO
|
||||||
|
bool "Enable GPIO"
|
||||||
|
select RT_USING_PIN
|
||||||
|
default y
|
||||||
|
|
||||||
|
menuconfig BSP_USING_UART
|
||||||
|
bool "Enable UART"
|
||||||
|
default y
|
||||||
|
select RT_USING_SERIAL
|
||||||
|
if BSP_USING_UART
|
||||||
|
config BSP_USING_UART0
|
||||||
|
bool "Enable UART0"
|
||||||
|
default y
|
||||||
|
|
||||||
|
config BSP_UART0_RX_USING_DMA
|
||||||
|
bool "Enable UART0 RX DMA"
|
||||||
|
depends on BSP_USING_UART0
|
||||||
|
select RT_SERIAL_USING_DMA
|
||||||
|
default n
|
||||||
|
|
||||||
|
config BSP_USING_UART1
|
||||||
|
bool "Enable UART1"
|
||||||
|
default n
|
||||||
|
|
||||||
|
config BSP_UART1_RX_USING_DMA
|
||||||
|
bool "Enable UART1 RX DMA"
|
||||||
|
depends on BSP_USING_UART1
|
||||||
|
select RT_SERIAL_USING_DMA
|
||||||
|
default n
|
||||||
|
|
||||||
|
config BSP_USING_UART2
|
||||||
|
bool "Enable UART2"
|
||||||
|
default n
|
||||||
|
|
||||||
|
config BSP_UART2_RX_USING_DMA
|
||||||
|
bool "Enable UART2 RX DMA"
|
||||||
|
depends on BSP_USING_UART2
|
||||||
|
select RT_SERIAL_USING_DMA
|
||||||
|
default n
|
||||||
|
|
||||||
|
config BSP_USING_UART3
|
||||||
|
bool "Enable UART3"
|
||||||
|
default n
|
||||||
|
|
||||||
|
config BSP_UART3_RX_USING_DMA
|
||||||
|
bool "Enable UART3 RX DMA"
|
||||||
|
depends on BSP_USING_UART3
|
||||||
|
select RT_SERIAL_USING_DMA
|
||||||
|
default n
|
||||||
|
|
||||||
|
config BSP_USING_UART4
|
||||||
|
bool "Enable UART4"
|
||||||
|
default n
|
||||||
|
|
||||||
|
config BSP_UART4_RX_USING_DMA
|
||||||
|
bool "Enable UART4 RX DMA"
|
||||||
|
depends on BSP_USING_UART4
|
||||||
|
select RT_SERIAL_USING_DMA
|
||||||
|
default n
|
||||||
|
|
||||||
|
config BSP_USING_UART5
|
||||||
|
bool "Enable UART5"
|
||||||
|
default n
|
||||||
|
|
||||||
|
config BSP_UART5_RX_USING_DMA
|
||||||
|
bool "Enable UART5 RX DMA"
|
||||||
|
depends on BSP_USING_UART5
|
||||||
|
select RT_SERIAL_USING_DMA
|
||||||
|
default n
|
||||||
|
|
||||||
|
config BSP_USING_UART6
|
||||||
|
bool "Enable UART6"
|
||||||
|
default n
|
||||||
|
|
||||||
|
config BSP_UART6_RX_USING_DMA
|
||||||
|
bool "Enable UART6 RX DMA"
|
||||||
|
depends on BSP_USING_UART6
|
||||||
|
select RT_SERIAL_USING_DMA
|
||||||
|
default n
|
||||||
|
|
||||||
|
config BSP_USING_UART7
|
||||||
|
bool "Enable UART7"
|
||||||
|
default n
|
||||||
|
|
||||||
|
config BSP_UART7_RX_USING_DMA
|
||||||
|
bool "Enable UART7 RX DMA"
|
||||||
|
depends on BSP_USING_UART7
|
||||||
|
select RT_SERIAL_USING_DMA
|
||||||
|
default n
|
||||||
|
endif
|
||||||
|
|
||||||
|
menuconfig BSP_USING_SPI
|
||||||
|
bool "Enable SPI BUS"
|
||||||
|
default n
|
||||||
|
select RT_USING_SPI
|
||||||
|
if BSP_USING_SPI
|
||||||
|
config BSP_USING_SPI1
|
||||||
|
bool "Enable SPI1 BUS"
|
||||||
|
default n
|
||||||
|
|
||||||
|
config BSP_SPI1_TX_USING_DMA
|
||||||
|
bool "Enable SPI1 TX DMA"
|
||||||
|
depends on BSP_USING_SPI1
|
||||||
|
default n
|
||||||
|
|
||||||
|
config BSP_SPI1_RX_USING_DMA
|
||||||
|
bool "Enable SPI1 RX DMA"
|
||||||
|
depends on BSP_USING_SPI1
|
||||||
|
select BSP_SPI1_TX_USING_DMA
|
||||||
|
default n
|
||||||
|
endif
|
||||||
|
|
||||||
|
menuconfig BSP_USING_I2C1
|
||||||
|
bool "Enable I2C1 BUS (software simulation)"
|
||||||
|
default n
|
||||||
|
select RT_USING_I2C
|
||||||
|
select RT_USING_I2C_BITOPS
|
||||||
|
select RT_USING_PIN
|
||||||
|
if BSP_USING_I2C1
|
||||||
|
config BSP_I2C1_SCL_PIN
|
||||||
|
int "i2c1 scl pin number"
|
||||||
|
range 1 216
|
||||||
|
default 24
|
||||||
|
config BSP_I2C1_SDA_PIN
|
||||||
|
int "I2C1 sda pin number"
|
||||||
|
range 1 216
|
||||||
|
default 25
|
||||||
|
endif
|
||||||
|
|
||||||
|
menuconfig BSP_USING_ADC
|
||||||
|
bool "Enable ADC"
|
||||||
|
default n
|
||||||
|
select RT_USING_ADC
|
||||||
|
if BSP_USING_ADC
|
||||||
|
config BSP_USING_ADC0
|
||||||
|
bool "Enable ADC0"
|
||||||
|
default n
|
||||||
|
|
||||||
|
config BSP_USING_ADC1
|
||||||
|
bool "Enable ADC1"
|
||||||
|
default n
|
||||||
|
|
||||||
|
config BSP_USING_ADC2
|
||||||
|
bool "Enable ADC2"
|
||||||
|
default n
|
||||||
|
endif
|
||||||
|
|
||||||
|
menuconfig BSP_USING_TIM
|
||||||
|
bool "Enable timer"
|
||||||
|
default n
|
||||||
|
select RT_USING_HWTIMER
|
||||||
|
if BSP_USING_TIM
|
||||||
|
config BSP_USING_TIM10
|
||||||
|
bool "Enable TIM10"
|
||||||
|
default n
|
||||||
|
|
||||||
|
config BSP_USING_TIM11
|
||||||
|
bool "Enable TIM11"
|
||||||
|
default n
|
||||||
|
|
||||||
|
config BSP_USING_TIM12
|
||||||
|
bool "Enable TIM13"
|
||||||
|
default n
|
||||||
|
endif
|
||||||
|
|
||||||
|
menuconfig BSP_USING_ONCHIP_RTC
|
||||||
|
bool "Enable RTC"
|
||||||
|
select RT_USING_RTC
|
||||||
|
default n
|
||||||
|
if BSP_USING_ONCHIP_RTC
|
||||||
|
choice
|
||||||
|
prompt "Select clock source"
|
||||||
|
default BSP_RTC_USING_LSE
|
||||||
|
|
||||||
|
config BSP_RTC_USING_LSE
|
||||||
|
bool "RTC USING LSE"
|
||||||
|
|
||||||
|
config BSP_RTC_USING_LSI
|
||||||
|
bool "RTC USING LSI"
|
||||||
|
endchoice
|
||||||
|
endif
|
||||||
|
|
||||||
|
config BSP_USING_WDT
|
||||||
|
bool "Enable Watchdog Timer"
|
||||||
|
select RT_USING_WDT
|
||||||
|
default n
|
||||||
|
|
||||||
|
config BSP_USING_SDIO
|
||||||
|
bool "Enable SDIO"
|
||||||
|
select RT_USING_SDIO
|
||||||
|
select RT_USING_DFS
|
||||||
|
default n
|
||||||
|
|
||||||
|
config BSP_USING_USBD
|
||||||
|
bool "Enable USB Device"
|
||||||
|
select RT_USING_USB_DEVICE
|
||||||
|
default n
|
||||||
|
|
||||||
|
menuconfig BSP_USING_USBH
|
||||||
|
bool "Enable USB Host"
|
||||||
|
select RT_USING_USB_HOST
|
||||||
|
default n
|
||||||
|
if BSP_USING_USBH
|
||||||
|
menuconfig RT_USBH_MSTORAGE
|
||||||
|
bool "Enable Udisk Drivers"
|
||||||
|
default n
|
||||||
|
if RT_USBH_MSTORAGE
|
||||||
|
config UDISK_MOUNTPOINT
|
||||||
|
string "Udisk mount dir"
|
||||||
|
default "/"
|
||||||
|
endif
|
||||||
|
endif
|
||||||
|
|
||||||
|
source "../libraries/gd32_drivers/Kconfig"
|
||||||
|
|
||||||
|
endmenu
|
||||||
|
|
||||||
|
menu "Board extended module Drivers"
|
||||||
|
|
||||||
|
endmenu
|
||||||
|
|
||||||
|
endmenu
|
||||||
|
|
@ -0,0 +1,28 @@
|
||||||
|
import os
|
||||||
|
import rtconfig
|
||||||
|
from building import *
|
||||||
|
|
||||||
|
Import('SDK_LIB')
|
||||||
|
|
||||||
|
cwd = GetCurrentDir()
|
||||||
|
|
||||||
|
# add general drivers
|
||||||
|
src = Split('''
|
||||||
|
board.c
|
||||||
|
''')
|
||||||
|
|
||||||
|
path = [cwd]
|
||||||
|
|
||||||
|
startup_path_prefix = SDK_LIB
|
||||||
|
|
||||||
|
if rtconfig.PLATFORM in ['gcc']:
|
||||||
|
src += [startup_path_prefix + '/GD32F4xx_Firmware_Library/CMSIS/GD/GD32F4xx/Source/GCC/startup_gd32f4xx.s']
|
||||||
|
elif rtconfig.PLATFORM in ['armcc', 'armclang']:
|
||||||
|
src += [startup_path_prefix + '/GD32F4xx_Firmware_Library/CMSIS/GD/GD32F4xx/Source/ARM/startup_gd32f4xx.s']
|
||||||
|
elif rtconfig.PLATFORM in ['iccarm']:
|
||||||
|
src += [startup_path_prefix + '/GD32F4xx_Firmware_Library/CMSIS/GD/GD32F4xx/Source/IAR/startup_gd32f4xx.s']
|
||||||
|
|
||||||
|
CPPDEFINES = ['GD32F470']
|
||||||
|
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
|
||||||
|
|
||||||
|
Return('group')
|
||||||
|
|
@ -0,0 +1,85 @@
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2006-2023, RT-Thread Development Team
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
|
*
|
||||||
|
* Change Logs:
|
||||||
|
* Date Author Notes
|
||||||
|
* 2021-08-20 BruceOu first implementation
|
||||||
|
*/
|
||||||
|
#include <stdint.h>
|
||||||
|
#include <rthw.h>
|
||||||
|
#include <rtthread.h>
|
||||||
|
#include <board.h>
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This function is executed in case of error occurrence.
|
||||||
|
* @param None
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void Error_Handler(void)
|
||||||
|
{
|
||||||
|
/* USER CODE BEGIN Error_Handler */
|
||||||
|
/* User can add his own implementation to report the HAL error return state */
|
||||||
|
while (1)
|
||||||
|
{
|
||||||
|
}
|
||||||
|
/* USER CODE END Error_Handler */
|
||||||
|
}
|
||||||
|
|
||||||
|
/** System Clock Configuration
|
||||||
|
*/
|
||||||
|
void SystemClock_Config(void)
|
||||||
|
{
|
||||||
|
SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND);
|
||||||
|
NVIC_SetPriority(SysTick_IRQn, 0);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* This is the timer interrupt service routine.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
void SysTick_Handler(void)
|
||||||
|
{
|
||||||
|
/* enter interrupt */
|
||||||
|
rt_interrupt_enter();
|
||||||
|
|
||||||
|
rt_tick_increase();
|
||||||
|
|
||||||
|
/* leave interrupt */
|
||||||
|
rt_interrupt_leave();
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* This function will initial GD32 board.
|
||||||
|
*/
|
||||||
|
void rt_hw_board_init()
|
||||||
|
{
|
||||||
|
/* NVIC Configuration */
|
||||||
|
#define NVIC_VTOR_MASK 0x3FFFFF80
|
||||||
|
#ifdef VECT_TAB_RAM
|
||||||
|
/* Set the Vector Table base location at 0x10000000 */
|
||||||
|
SCB->VTOR = (0x10000000 & NVIC_VTOR_MASK);
|
||||||
|
#else /* VECT_TAB_FLASH */
|
||||||
|
/* Set the Vector Table base location at 0x08000000 */
|
||||||
|
SCB->VTOR = (0x08000000 & NVIC_VTOR_MASK);
|
||||||
|
#endif
|
||||||
|
|
||||||
|
SystemClock_Config();
|
||||||
|
|
||||||
|
#ifdef RT_USING_COMPONENTS_INIT
|
||||||
|
rt_components_board_init();
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef RT_USING_CONSOLE
|
||||||
|
rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef BSP_USING_SDRAM
|
||||||
|
rt_system_heap_init((void *)EXT_SDRAM_BEGIN, (void *)EXT_SDRAM_END);
|
||||||
|
#else
|
||||||
|
rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
/*@}*/
|
||||||
|
|
@ -0,0 +1,47 @@
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2006-2023, RT-Thread Development Team
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
|
*
|
||||||
|
* Change Logs:
|
||||||
|
* Date Author Notes
|
||||||
|
* 2021-08-20 BruceOu first implementation
|
||||||
|
*/
|
||||||
|
#ifndef __BOARD_H__
|
||||||
|
#define __BOARD_H__
|
||||||
|
|
||||||
|
#include "gd32f4xx.h"
|
||||||
|
#include "drv_usart.h"
|
||||||
|
#include "drv_gpio.h"
|
||||||
|
|
||||||
|
#include "gd32f4xx_exti.h"
|
||||||
|
|
||||||
|
#define EXT_SDRAM_BEGIN (0xC0000000U) /* the begining address of external SDRAM */
|
||||||
|
#define EXT_SDRAM_END (EXT_SDRAM_BEGIN + (32U * 1024 * 1024)) /* the end address of external SDRAM */
|
||||||
|
|
||||||
|
// <o> Internal SRAM memory size[Kbytes] <8-512>
|
||||||
|
// <i>Default: 448
|
||||||
|
#ifdef __ICCARM__
|
||||||
|
// Use *.icf ram symbal, to avoid hardcode.
|
||||||
|
extern char __ICFEDIT_region_RAM_end__;
|
||||||
|
#define GD32_SRAM_END &__ICFEDIT_region_RAM_end__
|
||||||
|
#else
|
||||||
|
#define GD32_SRAM_SIZE 448
|
||||||
|
#define GD32_SRAM_END (0x20000000 + GD32_SRAM_SIZE * 1024)
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef __ARMCC_VERSION
|
||||||
|
extern int Image$$RW_IRAM1$$ZI$$Limit;
|
||||||
|
#define HEAP_BEGIN (&Image$$RW_IRAM1$$ZI$$Limit)
|
||||||
|
#elif __ICCARM__
|
||||||
|
#pragma section="HEAP"
|
||||||
|
#define HEAP_BEGIN (__segment_end("HEAP"))
|
||||||
|
#else
|
||||||
|
extern int __bss_end;
|
||||||
|
#define HEAP_BEGIN (&__bss_end)
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#define HEAP_END GD32_SRAM_END
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
@ -0,0 +1,45 @@
|
||||||
|
/*!
|
||||||
|
\file gd32f4xx_libopt.h
|
||||||
|
\brief library optional for gd32f4xx
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
Copyright (C) 2016 GigaDevice
|
||||||
|
|
||||||
|
2016-10-19, V1.0.0, firmware for GD32F4xx
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef GD32F4XX_LIBOPT_H
|
||||||
|
#define GD32F4XX_LIBOPT_H
|
||||||
|
#include "gd32f4xx_rcu.h"
|
||||||
|
#include "gd32f4xx_adc.h"
|
||||||
|
#include "gd32f4xx_can.h"
|
||||||
|
#include "gd32f4xx_crc.h"
|
||||||
|
#include "gd32f4xx_ctc.h"
|
||||||
|
#include "gd32f4xx_dac.h"
|
||||||
|
#include "gd32f4xx_dbg.h"
|
||||||
|
#include "gd32f4xx_dci.h"
|
||||||
|
#include "gd32f4xx_dma.h"
|
||||||
|
//#include "gd32f4xx_enet.h"
|
||||||
|
#include "gd32f4xx_exmc.h"
|
||||||
|
#include "gd32f4xx_exti.h"
|
||||||
|
#include "gd32f4xx_fmc.h"
|
||||||
|
#include "gd32f4xx_fwdgt.h"
|
||||||
|
#include "gd32f4xx_gpio.h"
|
||||||
|
#include "gd32f4xx_syscfg.h"
|
||||||
|
#include "gd32f4xx_i2c.h"
|
||||||
|
#include "gd32f4xx_ipa.h"
|
||||||
|
#include "gd32f4xx_iref.h"
|
||||||
|
#include "gd32f4xx_pmu.h"
|
||||||
|
#include "gd32f4xx_rcu.h"
|
||||||
|
#include "gd32f4xx_rtc.h"
|
||||||
|
#include "gd32f4xx_sdio.h"
|
||||||
|
#include "gd32f4xx_spi.h"
|
||||||
|
#include "gd32f4xx_timer.h"
|
||||||
|
#include "gd32f4xx_tli.h"
|
||||||
|
#include "gd32f4xx_trng.h"
|
||||||
|
#include "gd32f4xx_usart.h"
|
||||||
|
#include "gd32f4xx_wwdgt.h"
|
||||||
|
#include "gd32f4xx_misc.h"
|
||||||
|
|
||||||
|
#endif /* GD32F4XX_LIBOPT_H */
|
||||||
|
|
@ -0,0 +1,40 @@
|
||||||
|
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||||
|
/*-Editor annotation file-*/
|
||||||
|
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||||
|
/*-Specials-*/
|
||||||
|
define symbol __ICFEDIT_intvec_start__ = 0x08000000;
|
||||||
|
/*-Memory Regions-*/
|
||||||
|
define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
|
||||||
|
define symbol __ICFEDIT_region_ROM_end__ = 0x080FFFFF;
|
||||||
|
define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
|
||||||
|
define symbol __ICFEDIT_region_RAM_end__ = 0x2006FFFF;
|
||||||
|
/*-Sizes-*/
|
||||||
|
define symbol __ICFEDIT_size_cstack__ = 0x2000;
|
||||||
|
define symbol __ICFEDIT_size_heap__ = 0x2000;
|
||||||
|
/**** End of ICF editor section. ###ICF###*/
|
||||||
|
|
||||||
|
export symbol __ICFEDIT_region_RAM_end__;
|
||||||
|
|
||||||
|
define symbol __region_RAM1_start__ = 0x10000000;
|
||||||
|
define symbol __region_RAM1_end__ = 0x1000FFFF;
|
||||||
|
|
||||||
|
define memory mem with size = 4G;
|
||||||
|
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||||
|
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||||
|
define region RAM1_region = mem:[from __region_RAM1_start__ to __region_RAM1_end__];
|
||||||
|
|
||||||
|
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||||
|
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||||
|
|
||||||
|
initialize by copy { readwrite };
|
||||||
|
do not initialize { section .noinit };
|
||||||
|
|
||||||
|
keep { section FSymTab };
|
||||||
|
keep { section VSymTab };
|
||||||
|
keep { section .rti_fn* };
|
||||||
|
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||||
|
|
||||||
|
place in ROM_region { readonly };
|
||||||
|
place in RAM_region { readwrite,
|
||||||
|
block CSTACK, block HEAP };
|
||||||
|
place in RAM1_region { section .sram };
|
||||||
|
|
@ -0,0 +1,142 @@
|
||||||
|
/*
|
||||||
|
* linker script for GD32F4xx with GNU ld
|
||||||
|
* BruceOu 2021-12-14
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Program Entry, set to mark it as "used" and avoid gc */
|
||||||
|
MEMORY
|
||||||
|
{
|
||||||
|
CODE (rx) : ORIGIN = 0x08000000, LENGTH = 1024k /* 1024KB flash */
|
||||||
|
DATA (rw) : ORIGIN = 0x20000000, LENGTH = 448k /* 448KB sram */
|
||||||
|
}
|
||||||
|
ENTRY(Reset_Handler)
|
||||||
|
_system_stack_size = 0x200;
|
||||||
|
|
||||||
|
SECTIONS
|
||||||
|
{
|
||||||
|
.text :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
_stext = .;
|
||||||
|
KEEP(*(.isr_vector)) /* Startup code */
|
||||||
|
. = ALIGN(4);
|
||||||
|
*(.text) /* remaining code */
|
||||||
|
*(.text.*) /* remaining code */
|
||||||
|
*(.rodata) /* read-only data (constants) */
|
||||||
|
*(.rodata*)
|
||||||
|
*(.glue_7)
|
||||||
|
*(.glue_7t)
|
||||||
|
*(.gnu.linkonce.t*)
|
||||||
|
|
||||||
|
/* section information for finsh shell */
|
||||||
|
. = ALIGN(4);
|
||||||
|
__fsymtab_start = .;
|
||||||
|
KEEP(*(FSymTab))
|
||||||
|
__fsymtab_end = .;
|
||||||
|
. = ALIGN(4);
|
||||||
|
__vsymtab_start = .;
|
||||||
|
KEEP(*(VSymTab))
|
||||||
|
__vsymtab_end = .;
|
||||||
|
. = ALIGN(4);
|
||||||
|
|
||||||
|
/* section information for initial. */
|
||||||
|
. = ALIGN(4);
|
||||||
|
__rt_init_start = .;
|
||||||
|
KEEP(*(SORT(.rti_fn*)))
|
||||||
|
__rt_init_end = .;
|
||||||
|
. = ALIGN(4);
|
||||||
|
|
||||||
|
. = ALIGN(4);
|
||||||
|
_etext = .;
|
||||||
|
} > CODE = 0
|
||||||
|
|
||||||
|
/* .ARM.exidx is sorted, so has to go in its own output section. */
|
||||||
|
__exidx_start = .;
|
||||||
|
.ARM.exidx :
|
||||||
|
{
|
||||||
|
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
|
||||||
|
|
||||||
|
/* This is used by the startup in order to initialize the .data secion */
|
||||||
|
_sidata = .;
|
||||||
|
} > CODE
|
||||||
|
__exidx_end = .;
|
||||||
|
|
||||||
|
/* .data section which is used for initialized data */
|
||||||
|
|
||||||
|
.data : AT (_sidata)
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
/* This is used by the startup in order to initialize the .data secion */
|
||||||
|
_sdata = . ;
|
||||||
|
|
||||||
|
*(.data)
|
||||||
|
*(.data.*)
|
||||||
|
*(.gnu.linkonce.d*)
|
||||||
|
|
||||||
|
. = ALIGN(4);
|
||||||
|
/* This is used by the startup in order to initialize the .data secion */
|
||||||
|
_edata = . ;
|
||||||
|
} >DATA
|
||||||
|
|
||||||
|
.stack :
|
||||||
|
{
|
||||||
|
. = . + _system_stack_size;
|
||||||
|
. = ALIGN(4);
|
||||||
|
_estack = .;
|
||||||
|
} >DATA
|
||||||
|
|
||||||
|
__bss_start = .;
|
||||||
|
.bss :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
/* This is used by the startup in order to initialize the .bss secion */
|
||||||
|
_sbss = .;
|
||||||
|
|
||||||
|
*(.bss)
|
||||||
|
*(.bss.*)
|
||||||
|
*(COMMON)
|
||||||
|
|
||||||
|
. = ALIGN(4);
|
||||||
|
/* This is used by the startup in order to initialize the .bss secion */
|
||||||
|
_ebss = . ;
|
||||||
|
|
||||||
|
*(.bss.init)
|
||||||
|
} > DATA
|
||||||
|
__bss_end = .;
|
||||||
|
|
||||||
|
_end = .;
|
||||||
|
|
||||||
|
/* Stabs debugging sections. */
|
||||||
|
.stab 0 : { *(.stab) }
|
||||||
|
.stabstr 0 : { *(.stabstr) }
|
||||||
|
.stab.excl 0 : { *(.stab.excl) }
|
||||||
|
.stab.exclstr 0 : { *(.stab.exclstr) }
|
||||||
|
.stab.index 0 : { *(.stab.index) }
|
||||||
|
.stab.indexstr 0 : { *(.stab.indexstr) }
|
||||||
|
.comment 0 : { *(.comment) }
|
||||||
|
/* DWARF debug sections.
|
||||||
|
* Symbols in the DWARF debugging sections are relative to the beginning
|
||||||
|
* of the section so we begin them at 0. */
|
||||||
|
/* DWARF 1 */
|
||||||
|
.debug 0 : { *(.debug) }
|
||||||
|
.line 0 : { *(.line) }
|
||||||
|
/* GNU DWARF 1 extensions */
|
||||||
|
.debug_srcinfo 0 : { *(.debug_srcinfo) }
|
||||||
|
.debug_sfnames 0 : { *(.debug_sfnames) }
|
||||||
|
/* DWARF 1.1 and DWARF 2 */
|
||||||
|
.debug_aranges 0 : { *(.debug_aranges) }
|
||||||
|
.debug_pubnames 0 : { *(.debug_pubnames) }
|
||||||
|
/* DWARF 2 */
|
||||||
|
.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
|
||||||
|
.debug_abbrev 0 : { *(.debug_abbrev) }
|
||||||
|
.debug_line 0 : { *(.debug_line) }
|
||||||
|
.debug_frame 0 : { *(.debug_frame) }
|
||||||
|
.debug_str 0 : { *(.debug_str) }
|
||||||
|
.debug_loc 0 : { *(.debug_loc) }
|
||||||
|
.debug_macinfo 0 : { *(.debug_macinfo) }
|
||||||
|
/* SGI/MIPS DWARF 2 extensions */
|
||||||
|
.debug_weaknames 0 : { *(.debug_weaknames) }
|
||||||
|
.debug_funcnames 0 : { *(.debug_funcnames) }
|
||||||
|
.debug_typenames 0 : { *(.debug_typenames) }
|
||||||
|
.debug_varnames 0 : { *(.debug_varnames) }
|
||||||
|
}
|
||||||
|
|
@ -0,0 +1,15 @@
|
||||||
|
; *************************************************************
|
||||||
|
; *** Scatter-Loading Description File generated by uVision ***
|
||||||
|
; *************************************************************
|
||||||
|
|
||||||
|
LR_IROM1 0x08000000 0x00100000 { ; load region size_region
|
||||||
|
ER_IROM1 0x08000000 0x00100000 { ; load address = execution address
|
||||||
|
*.o (RESET, +First)
|
||||||
|
*(InRoot$$Sections)
|
||||||
|
.ANY (+RO)
|
||||||
|
}
|
||||||
|
RW_IRAM1 0x20000000 0x00070000 { ; RW data
|
||||||
|
.ANY (+RW +ZI)
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
Binary file not shown.
|
After Width: | Height: | Size: 396 KiB |
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,10 @@
|
||||||
|
<?xml version="1.0" encoding="iso-8859-1"?>
|
||||||
|
|
||||||
|
<workspace>
|
||||||
|
<project>
|
||||||
|
<path>$WS_DIR$\project.ewp</path>
|
||||||
|
</project>
|
||||||
|
<batchBuild/>
|
||||||
|
</workspace>
|
||||||
|
|
||||||
|
|
||||||
|
|
@ -0,0 +1,917 @@
|
||||||
|
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||||
|
<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
|
||||||
|
|
||||||
|
<SchemaVersion>1.0</SchemaVersion>
|
||||||
|
|
||||||
|
<Header>### uVision Project, (C) Keil Software</Header>
|
||||||
|
|
||||||
|
<Extensions>
|
||||||
|
<cExt>*.c</cExt>
|
||||||
|
<aExt>*.s*; *.src; *.a*</aExt>
|
||||||
|
<oExt>*.obj; *.o</oExt>
|
||||||
|
<lExt>*.lib</lExt>
|
||||||
|
<tExt>*.txt; *.h; *.inc; *.md</tExt>
|
||||||
|
<pExt>*.plm</pExt>
|
||||||
|
<CppX>*.cpp</CppX>
|
||||||
|
<nMigrate>0</nMigrate>
|
||||||
|
</Extensions>
|
||||||
|
|
||||||
|
<DaveTm>
|
||||||
|
<dwLowDateTime>0</dwLowDateTime>
|
||||||
|
<dwHighDateTime>0</dwHighDateTime>
|
||||||
|
</DaveTm>
|
||||||
|
|
||||||
|
<Target>
|
||||||
|
<TargetName>rt-thread</TargetName>
|
||||||
|
<ToolsetNumber>0x4</ToolsetNumber>
|
||||||
|
<ToolsetName>ARM-ADS</ToolsetName>
|
||||||
|
<TargetOption>
|
||||||
|
<CLKADS>12000000</CLKADS>
|
||||||
|
<OPTTT>
|
||||||
|
<gFlags>1</gFlags>
|
||||||
|
<BeepAtEnd>1</BeepAtEnd>
|
||||||
|
<RunSim>0</RunSim>
|
||||||
|
<RunTarget>1</RunTarget>
|
||||||
|
<RunAbUc>0</RunAbUc>
|
||||||
|
</OPTTT>
|
||||||
|
<OPTHX>
|
||||||
|
<HexSelection>1</HexSelection>
|
||||||
|
<FlashByte>65535</FlashByte>
|
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||||||
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||||||
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|
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|
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|
||||||
|
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|
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|
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|
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|
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|
||||||
|
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||||||
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<Name>-X"Any" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN1 -FF0GD32F4xx_1MB.FLM -FS08000000 -FL0100000 -FP0($$Device:GD32F470ZG$Flash\GD32F4xx_1MB.FLM)</Name>
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|
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<PathWithFileName>..\libraries\GD32F4xx_Firmware_Library\CMSIS\GD\GD32F4xx\Source\system_gd32f4xx.c</PathWithFileName>
|
||||||
|
<FilenameWithoutPath>system_gd32f4xx.c</FilenameWithoutPath>
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</File>
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</Group>
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|
|
||||||
|
<Group>
|
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|
<GroupName>::CMSIS</GroupName>
|
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|
<tvExp>0</tvExp>
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<tvExpOptDlg>0</tvExpOptDlg>
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<RteFlg>1</RteFlg>
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|
</Group>
|
||||||
|
|
||||||
|
</ProjectOpt>
|
||||||
|
|
@ -0,0 +1,838 @@
|
||||||
|
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||||
|
<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_proj.xsd">
|
||||||
|
<SchemaVersion>1.1</SchemaVersion>
|
||||||
|
<Header>### uVision Project, (C) Keil Software</Header>
|
||||||
|
<Targets>
|
||||||
|
<Target>
|
||||||
|
<TargetName>rt-thread</TargetName>
|
||||||
|
<ToolsetNumber>0x4</ToolsetNumber>
|
||||||
|
<ToolsetName>ARM-ADS</ToolsetName>
|
||||||
|
<uAC6>0</uAC6>
|
||||||
|
<TargetOption>
|
||||||
|
<TargetCommonOption>
|
||||||
|
<Device>GD32F450ZK</Device>
|
||||||
|
<Vendor>GigaDevice</Vendor>
|
||||||
|
<Cpu>IRAM(0x20000000-0x20030000) IRAM2(0x10000000-0x10010000) IROM(0x08000000-0x08300000) CLOCK(25000000) CPUTYPE("Cortex-M4") FPU2</Cpu>
|
||||||
|
<FlashUtilSpec />
|
||||||
|
<StartupFile>"Startup\GD\GD32F4xx\startup_gd32f4xx.s" ("GD32F4xx Startup Code")</StartupFile>
|
||||||
|
<FlashDriverDll>UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC800 -FN1 -FF0GD32F4xx_3MB -FS08000000 -FL0300000)</FlashDriverDll>
|
||||||
|
<DeviceId>0</DeviceId>
|
||||||
|
<RegisterFile>gd32f4xx0.h</RegisterFile>
|
||||||
|
<MemoryEnv />
|
||||||
|
<Cmp />
|
||||||
|
<Asm />
|
||||||
|
<Linker />
|
||||||
|
<OHString />
|
||||||
|
<InfinionOptionDll />
|
||||||
|
<SLE66CMisc />
|
||||||
|
<SLE66AMisc />
|
||||||
|
<SLE66LinkerMisc />
|
||||||
|
<SFDFile>SFD\GD\GD32F4xx\GD32F4xx.SFR</SFDFile>
|
||||||
|
<bCustSvd>0</bCustSvd>
|
||||||
|
<UseEnv>0</UseEnv>
|
||||||
|
<BinPath />
|
||||||
|
<IncludePath />
|
||||||
|
<LibPath />
|
||||||
|
<RegisterFilePath>GD\GD32F4xx\</RegisterFilePath>
|
||||||
|
<DBRegisterFilePath>GD\GD32F4xx\</DBRegisterFilePath>
|
||||||
|
<TargetStatus>
|
||||||
|
<Error>0</Error>
|
||||||
|
<ExitCodeStop>0</ExitCodeStop>
|
||||||
|
<ButtonStop>0</ButtonStop>
|
||||||
|
<NotGenerated>0</NotGenerated>
|
||||||
|
<InvalidFlash>1</InvalidFlash>
|
||||||
|
</TargetStatus>
|
||||||
|
<OutputDirectory>.\output\</OutputDirectory>
|
||||||
|
<OutputName>rtthread</OutputName>
|
||||||
|
<CreateExecutable>1</CreateExecutable>
|
||||||
|
<CreateLib>0</CreateLib>
|
||||||
|
<CreateHexFile>1</CreateHexFile>
|
||||||
|
<DebugInformation>1</DebugInformation>
|
||||||
|
<BrowseInformation>1</BrowseInformation>
|
||||||
|
<ListingPath>.\build\</ListingPath>
|
||||||
|
<HexFormatSelection>1</HexFormatSelection>
|
||||||
|
<Merge32K>0</Merge32K>
|
||||||
|
<CreateBatchFile>0</CreateBatchFile>
|
||||||
|
<BeforeCompile>
|
||||||
|
<RunUserProg1>0</RunUserProg1>
|
||||||
|
<RunUserProg2>0</RunUserProg2>
|
||||||
|
<UserProg1Name />
|
||||||
|
<UserProg2Name />
|
||||||
|
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||||
|
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||||
|
<nStopU1X>0</nStopU1X>
|
||||||
|
<nStopU2X>0</nStopU2X>
|
||||||
|
</BeforeCompile>
|
||||||
|
<BeforeMake>
|
||||||
|
<RunUserProg1>0</RunUserProg1>
|
||||||
|
<RunUserProg2>0</RunUserProg2>
|
||||||
|
<UserProg1Name />
|
||||||
|
<UserProg2Name />
|
||||||
|
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||||
|
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||||
|
<nStopB1X>0</nStopB1X>
|
||||||
|
<nStopB2X>0</nStopB2X>
|
||||||
|
</BeforeMake>
|
||||||
|
<AfterMake>
|
||||||
|
<RunUserProg1>0</RunUserProg1>
|
||||||
|
<RunUserProg2>0</RunUserProg2>
|
||||||
|
<UserProg1Name />
|
||||||
|
<UserProg2Name />
|
||||||
|
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||||
|
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||||
|
<nStopA1X>0</nStopA1X>
|
||||||
|
<nStopA2X>0</nStopA2X>
|
||||||
|
</AfterMake>
|
||||||
|
<SelectedForBatchBuild>0</SelectedForBatchBuild>
|
||||||
|
<SVCSIdString />
|
||||||
|
</TargetCommonOption>
|
||||||
|
<CommonProperty>
|
||||||
|
<UseCPPCompiler>0</UseCPPCompiler>
|
||||||
|
<RVCTCodeConst>0</RVCTCodeConst>
|
||||||
|
<RVCTZI>0</RVCTZI>
|
||||||
|
<RVCTOtherData>0</RVCTOtherData>
|
||||||
|
<ModuleSelection>0</ModuleSelection>
|
||||||
|
<IncludeInBuild>1</IncludeInBuild>
|
||||||
|
<AlwaysBuild>0</AlwaysBuild>
|
||||||
|
<GenerateAssemblyFile>0</GenerateAssemblyFile>
|
||||||
|
<AssembleAssemblyFile>0</AssembleAssemblyFile>
|
||||||
|
<PublicsOnly>0</PublicsOnly>
|
||||||
|
<StopOnExitCode>3</StopOnExitCode>
|
||||||
|
<CustomArgument />
|
||||||
|
<IncludeLibraryModules />
|
||||||
|
<ComprImg>1</ComprImg>
|
||||||
|
</CommonProperty>
|
||||||
|
<DllOption>
|
||||||
|
<SimDllName>SARMCM3.DLL</SimDllName>
|
||||||
|
<SimDllArguments> -REMAP</SimDllArguments>
|
||||||
|
<SimDlgDll>DCM.DLL</SimDlgDll>
|
||||||
|
<SimDlgDllArguments>-pCM3</SimDlgDllArguments>
|
||||||
|
<TargetDllName>SARMCM3.DLL</TargetDllName>
|
||||||
|
<TargetDllArguments />
|
||||||
|
<TargetDlgDll>TCM.DLL</TargetDlgDll>
|
||||||
|
<TargetDlgDllArguments>-pCM3</TargetDlgDllArguments>
|
||||||
|
</DllOption>
|
||||||
|
<DebugOption>
|
||||||
|
<OPTHX>
|
||||||
|
<HexSelection>1</HexSelection>
|
||||||
|
<HexRangeLowAddress>0</HexRangeLowAddress>
|
||||||
|
<HexRangeHighAddress>0</HexRangeHighAddress>
|
||||||
|
<HexOffset>0</HexOffset>
|
||||||
|
<Oh166RecLen>16</Oh166RecLen>
|
||||||
|
</OPTHX>
|
||||||
|
<Simulator>
|
||||||
|
<UseSimulator>0</UseSimulator>
|
||||||
|
<LoadApplicationAtStartup>1</LoadApplicationAtStartup>
|
||||||
|
<RunToMain>1</RunToMain>
|
||||||
|
<RestoreBreakpoints>1</RestoreBreakpoints>
|
||||||
|
<RestoreWatchpoints>1</RestoreWatchpoints>
|
||||||
|
<RestoreMemoryDisplay>1</RestoreMemoryDisplay>
|
||||||
|
<RestoreFunctions>1</RestoreFunctions>
|
||||||
|
<RestoreToolbox>1</RestoreToolbox>
|
||||||
|
<LimitSpeedToRealTime>0</LimitSpeedToRealTime>
|
||||||
|
<RestoreSysVw>1</RestoreSysVw>
|
||||||
|
</Simulator>
|
||||||
|
<Target>
|
||||||
|
<UseTarget>1</UseTarget>
|
||||||
|
<LoadApplicationAtStartup>1</LoadApplicationAtStartup>
|
||||||
|
<RunToMain>1</RunToMain>
|
||||||
|
<RestoreBreakpoints>1</RestoreBreakpoints>
|
||||||
|
<RestoreWatchpoints>1</RestoreWatchpoints>
|
||||||
|
<RestoreMemoryDisplay>1</RestoreMemoryDisplay>
|
||||||
|
<RestoreFunctions>0</RestoreFunctions>
|
||||||
|
<RestoreToolbox>1</RestoreToolbox>
|
||||||
|
<RestoreTracepoints>0</RestoreTracepoints>
|
||||||
|
<RestoreSysVw>1</RestoreSysVw>
|
||||||
|
</Target>
|
||||||
|
<RunDebugAfterBuild>0</RunDebugAfterBuild>
|
||||||
|
<TargetSelection>3</TargetSelection>
|
||||||
|
<SimDlls>
|
||||||
|
<CpuDll />
|
||||||
|
<CpuDllArguments />
|
||||||
|
<PeripheralDll />
|
||||||
|
<PeripheralDllArguments />
|
||||||
|
<InitializationFile />
|
||||||
|
</SimDlls>
|
||||||
|
<TargetDlls>
|
||||||
|
<CpuDll />
|
||||||
|
<CpuDllArguments />
|
||||||
|
<PeripheralDll />
|
||||||
|
<PeripheralDllArguments />
|
||||||
|
<InitializationFile />
|
||||||
|
<Driver>BIN\CMSIS_AGDI.dll</Driver>
|
||||||
|
</TargetDlls>
|
||||||
|
</DebugOption>
|
||||||
|
<Utilities>
|
||||||
|
<Flash1>
|
||||||
|
<UseTargetDll>1</UseTargetDll>
|
||||||
|
<UseExternalTool>0</UseExternalTool>
|
||||||
|
<RunIndependent>0</RunIndependent>
|
||||||
|
<UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
|
||||||
|
<Capability>1</Capability>
|
||||||
|
<DriverSelection>4096</DriverSelection>
|
||||||
|
</Flash1>
|
||||||
|
<bUseTDR>1</bUseTDR>
|
||||||
|
<Flash2>BIN\UL2CM3.DLL</Flash2>
|
||||||
|
<Flash3>"" ()</Flash3>
|
||||||
|
<Flash4 />
|
||||||
|
<pFcarmOut />
|
||||||
|
<pFcarmGrp />
|
||||||
|
<pFcArmRoot />
|
||||||
|
<FcArmLst>0</FcArmLst>
|
||||||
|
</Utilities>
|
||||||
|
<TargetArmAds>
|
||||||
|
<ArmAdsMisc>
|
||||||
|
<GenerateListings>0</GenerateListings>
|
||||||
|
<asHll>1</asHll>
|
||||||
|
<asAsm>1</asAsm>
|
||||||
|
<asMacX>1</asMacX>
|
||||||
|
<asSyms>1</asSyms>
|
||||||
|
<asFals>1</asFals>
|
||||||
|
<asDbgD>1</asDbgD>
|
||||||
|
<asForm>1</asForm>
|
||||||
|
<ldLst>0</ldLst>
|
||||||
|
<ldmm>1</ldmm>
|
||||||
|
<ldXref>1</ldXref>
|
||||||
|
<BigEnd>0</BigEnd>
|
||||||
|
<AdsALst>1</AdsALst>
|
||||||
|
<AdsACrf>1</AdsACrf>
|
||||||
|
<AdsANop>0</AdsANop>
|
||||||
|
<AdsANot>0</AdsANot>
|
||||||
|
<AdsLLst>1</AdsLLst>
|
||||||
|
<AdsLmap>1</AdsLmap>
|
||||||
|
<AdsLcgr>1</AdsLcgr>
|
||||||
|
<AdsLsym>1</AdsLsym>
|
||||||
|
<AdsLszi>1</AdsLszi>
|
||||||
|
<AdsLtoi>1</AdsLtoi>
|
||||||
|
<AdsLsun>1</AdsLsun>
|
||||||
|
<AdsLven>1</AdsLven>
|
||||||
|
<AdsLsxf>1</AdsLsxf>
|
||||||
|
<RvctClst>0</RvctClst>
|
||||||
|
<GenPPlst>0</GenPPlst>
|
||||||
|
<AdsCpuType>"Cortex-M4"</AdsCpuType>
|
||||||
|
<RvctDeviceName />
|
||||||
|
<mOS>0</mOS>
|
||||||
|
<uocRom>0</uocRom>
|
||||||
|
<uocRam>0</uocRam>
|
||||||
|
<hadIROM>1</hadIROM>
|
||||||
|
<hadIRAM>1</hadIRAM>
|
||||||
|
<hadXRAM>0</hadXRAM>
|
||||||
|
<uocXRam>0</uocXRam>
|
||||||
|
<RvdsVP>2</RvdsVP>
|
||||||
|
<hadIRAM2>1</hadIRAM2>
|
||||||
|
<hadIROM2>0</hadIROM2>
|
||||||
|
<StupSel>8</StupSel>
|
||||||
|
<useUlib>1</useUlib>
|
||||||
|
<EndSel>0</EndSel>
|
||||||
|
<uLtcg>0</uLtcg>
|
||||||
|
<nSecure>0</nSecure>
|
||||||
|
<RoSelD>3</RoSelD>
|
||||||
|
<RwSelD>3</RwSelD>
|
||||||
|
<CodeSel>0</CodeSel>
|
||||||
|
<OptFeed>0</OptFeed>
|
||||||
|
<NoZi1>0</NoZi1>
|
||||||
|
<NoZi2>0</NoZi2>
|
||||||
|
<NoZi3>0</NoZi3>
|
||||||
|
<NoZi4>0</NoZi4>
|
||||||
|
<NoZi5>0</NoZi5>
|
||||||
|
<Ro1Chk>0</Ro1Chk>
|
||||||
|
<Ro2Chk>0</Ro2Chk>
|
||||||
|
<Ro3Chk>0</Ro3Chk>
|
||||||
|
<Ir1Chk>1</Ir1Chk>
|
||||||
|
<Ir2Chk>0</Ir2Chk>
|
||||||
|
<Ra1Chk>0</Ra1Chk>
|
||||||
|
<Ra2Chk>0</Ra2Chk>
|
||||||
|
<Ra3Chk>0</Ra3Chk>
|
||||||
|
<Im1Chk>1</Im1Chk>
|
||||||
|
<Im2Chk>0</Im2Chk>
|
||||||
|
<OnChipMemories>
|
||||||
|
<Ocm1>
|
||||||
|
<Type>0</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x0</Size>
|
||||||
|
</Ocm1>
|
||||||
|
<Ocm2>
|
||||||
|
<Type>0</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x0</Size>
|
||||||
|
</Ocm2>
|
||||||
|
<Ocm3>
|
||||||
|
<Type>0</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x0</Size>
|
||||||
|
</Ocm3>
|
||||||
|
<Ocm4>
|
||||||
|
<Type>0</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x0</Size>
|
||||||
|
</Ocm4>
|
||||||
|
<Ocm5>
|
||||||
|
<Type>0</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x0</Size>
|
||||||
|
</Ocm5>
|
||||||
|
<Ocm6>
|
||||||
|
<Type>0</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x0</Size>
|
||||||
|
</Ocm6>
|
||||||
|
<IRAM>
|
||||||
|
<Type>0</Type>
|
||||||
|
<StartAddress>0x20000000</StartAddress>
|
||||||
|
<Size>0x30000</Size>
|
||||||
|
</IRAM>
|
||||||
|
<IROM>
|
||||||
|
<Type>1</Type>
|
||||||
|
<StartAddress>0x8000000</StartAddress>
|
||||||
|
<Size>0x300000</Size>
|
||||||
|
</IROM>
|
||||||
|
<XRAM>
|
||||||
|
<Type>0</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x0</Size>
|
||||||
|
</XRAM>
|
||||||
|
<OCR_RVCT1>
|
||||||
|
<Type>1</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x0</Size>
|
||||||
|
</OCR_RVCT1>
|
||||||
|
<OCR_RVCT2>
|
||||||
|
<Type>1</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x0</Size>
|
||||||
|
</OCR_RVCT2>
|
||||||
|
<OCR_RVCT3>
|
||||||
|
<Type>1</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x0</Size>
|
||||||
|
</OCR_RVCT3>
|
||||||
|
<OCR_RVCT4>
|
||||||
|
<Type>1</Type>
|
||||||
|
<StartAddress>0x8000000</StartAddress>
|
||||||
|
<Size>0x300000</Size>
|
||||||
|
</OCR_RVCT4>
|
||||||
|
<OCR_RVCT5>
|
||||||
|
<Type>1</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x0</Size>
|
||||||
|
</OCR_RVCT5>
|
||||||
|
<OCR_RVCT6>
|
||||||
|
<Type>0</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x0</Size>
|
||||||
|
</OCR_RVCT6>
|
||||||
|
<OCR_RVCT7>
|
||||||
|
<Type>0</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x0</Size>
|
||||||
|
</OCR_RVCT7>
|
||||||
|
<OCR_RVCT8>
|
||||||
|
<Type>0</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x0</Size>
|
||||||
|
</OCR_RVCT8>
|
||||||
|
<OCR_RVCT9>
|
||||||
|
<Type>0</Type>
|
||||||
|
<StartAddress>0x20000000</StartAddress>
|
||||||
|
<Size>0x30000</Size>
|
||||||
|
</OCR_RVCT9>
|
||||||
|
<OCR_RVCT10>
|
||||||
|
<Type>0</Type>
|
||||||
|
<StartAddress>0x10000000</StartAddress>
|
||||||
|
<Size>0x10000</Size>
|
||||||
|
</OCR_RVCT10>
|
||||||
|
</OnChipMemories>
|
||||||
|
<RvctStartVector />
|
||||||
|
</ArmAdsMisc>
|
||||||
|
<Cads>
|
||||||
|
<interw>1</interw>
|
||||||
|
<Optim>1</Optim>
|
||||||
|
<oTime>0</oTime>
|
||||||
|
<SplitLS>0</SplitLS>
|
||||||
|
<OneElfS>1</OneElfS>
|
||||||
|
<Strict>0</Strict>
|
||||||
|
<EnumInt>0</EnumInt>
|
||||||
|
<PlainCh>0</PlainCh>
|
||||||
|
<Ropi>0</Ropi>
|
||||||
|
<Rwpi>0</Rwpi>
|
||||||
|
<wLevel>2</wLevel>
|
||||||
|
<uThumb>0</uThumb>
|
||||||
|
<uSurpInc>0</uSurpInc>
|
||||||
|
<uC99>1</uC99>
|
||||||
|
<uGnu>0</uGnu>
|
||||||
|
<useXO>0</useXO>
|
||||||
|
<v6Lang>1</v6Lang>
|
||||||
|
<v6LangP>1</v6LangP>
|
||||||
|
<vShortEn>1</vShortEn>
|
||||||
|
<vShortWch>1</vShortWch>
|
||||||
|
<v6Lto>0</v6Lto>
|
||||||
|
<v6WtE>0</v6WtE>
|
||||||
|
<v6Rtti>0</v6Rtti>
|
||||||
|
<VariousControls>
|
||||||
|
<MiscControls />
|
||||||
|
<Define>__STDC_LIMIT_MACROS, USE_STDPERIPH_DRIVER, RT_USING_LIBC, __CLK_TCK=RT_TICK_PER_SECOND, GD32F450, __RTTHREAD__, RT_USING_ARM_LIBC</Define>
|
||||||
|
<Undefine />
|
||||||
|
<IncludePath>applications;.;..\..\..\..\components\libc\compilers\common\include;..\..\..\..\components\libc\compilers\common\extension;..\..\..\..\components\libc\compilers\common\extension\fcntl\octal;..\..\..\..\libcpu\arm\common;..\..\..\..\libcpu\arm\cortex-m4;..\..\..\..\components\drivers\include;..\..\..\..\components\drivers\include;..\..\..\..\components\drivers\include;board;..\libraries\gd32_drivers;..\..\..\..\components\dfs\include;..\..\..\..\components\finsh;.;..\..\..\..\include;..\libraries\GD32F4xx_Firmware_Library\CMSIS\GD\GD32F4xx\Include;..\libraries\GD32F4xx_Firmware_Library\CMSIS;..\libraries\GD32F4xx_Firmware_Library\GD32F4xx_standard_peripheral\Include;..\..\..\..\components\libc\posix\io\poll;..\..\..\..\components\libc\posix\io\stdio;..\..\..\..\components\libc\posix\ipc</IncludePath>
|
||||||
|
</VariousControls>
|
||||||
|
</Cads>
|
||||||
|
<Aads>
|
||||||
|
<interw>1</interw>
|
||||||
|
<Ropi>0</Ropi>
|
||||||
|
<Rwpi>0</Rwpi>
|
||||||
|
<thumb>0</thumb>
|
||||||
|
<SplitLS>0</SplitLS>
|
||||||
|
<SwStkChk>0</SwStkChk>
|
||||||
|
<NoWarn>0</NoWarn>
|
||||||
|
<uSurpInc>0</uSurpInc>
|
||||||
|
<useXO>0</useXO>
|
||||||
|
<uClangAs>0</uClangAs>
|
||||||
|
<VariousControls>
|
||||||
|
<MiscControls />
|
||||||
|
<Define />
|
||||||
|
<Undefine />
|
||||||
|
<IncludePath />
|
||||||
|
</VariousControls>
|
||||||
|
</Aads>
|
||||||
|
<LDads>
|
||||||
|
<umfTarg>1</umfTarg>
|
||||||
|
<Ropi>0</Ropi>
|
||||||
|
<Rwpi>0</Rwpi>
|
||||||
|
<noStLib>0</noStLib>
|
||||||
|
<RepFail>1</RepFail>
|
||||||
|
<useFile>0</useFile>
|
||||||
|
<TextAddressRange>0x08000000</TextAddressRange>
|
||||||
|
<DataAddressRange>0x20000000</DataAddressRange>
|
||||||
|
<pXoBase />
|
||||||
|
<ScatterFile />
|
||||||
|
<IncludeLibs />
|
||||||
|
<IncludeLibsPath />
|
||||||
|
<Misc />
|
||||||
|
<LinkerInputFile />
|
||||||
|
<DisabledWarnings />
|
||||||
|
</LDads>
|
||||||
|
</TargetArmAds>
|
||||||
|
</TargetOption>
|
||||||
|
<Groups>
|
||||||
|
<Group>
|
||||||
|
<GroupName>Applications</GroupName>
|
||||||
|
<Files>
|
||||||
|
<File>
|
||||||
|
<FileName>main.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>applications\main.c</FilePath>
|
||||||
|
</File>
|
||||||
|
</Files>
|
||||||
|
</Group>
|
||||||
|
<Group>
|
||||||
|
<GroupName>Compiler</GroupName>
|
||||||
|
<Files>
|
||||||
|
<File>
|
||||||
|
<FileName>syscall_mem.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\..\components\libc\compilers\armlibc\syscall_mem.c</FilePath>
|
||||||
|
</File>
|
||||||
|
</Files>
|
||||||
|
<Files>
|
||||||
|
<File>
|
||||||
|
<FileName>syscalls.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\..\components\libc\compilers\armlibc\syscalls.c</FilePath>
|
||||||
|
</File>
|
||||||
|
</Files>
|
||||||
|
<Files>
|
||||||
|
<File>
|
||||||
|
<FileName>cctype.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\..\components\libc\compilers\common\cctype.c</FilePath>
|
||||||
|
</File>
|
||||||
|
</Files>
|
||||||
|
<Files>
|
||||||
|
<File>
|
||||||
|
<FileName>cstdio.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\..\components\libc\compilers\common\cstdio.c</FilePath>
|
||||||
|
</File>
|
||||||
|
</Files>
|
||||||
|
<Files>
|
||||||
|
<File>
|
||||||
|
<FileName>cstdlib.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\..\components\libc\compilers\common\cstdlib.c</FilePath>
|
||||||
|
</File>
|
||||||
|
</Files>
|
||||||
|
<Files>
|
||||||
|
<File>
|
||||||
|
<FileName>cstring.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\..\components\libc\compilers\common\cstring.c</FilePath>
|
||||||
|
</File>
|
||||||
|
</Files>
|
||||||
|
<Files>
|
||||||
|
<File>
|
||||||
|
<FileName>ctime.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\..\components\libc\compilers\common\ctime.c</FilePath>
|
||||||
|
</File>
|
||||||
|
</Files>
|
||||||
|
<Files>
|
||||||
|
<File>
|
||||||
|
<FileName>cwchar.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\..\components\libc\compilers\common\cwchar.c</FilePath>
|
||||||
|
</File>
|
||||||
|
</Files>
|
||||||
|
</Group>
|
||||||
|
<Group>
|
||||||
|
<GroupName>CPU</GroupName>
|
||||||
|
<Files>
|
||||||
|
<File>
|
||||||
|
<FileName>backtrace.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\..\libcpu\arm\common\backtrace.c</FilePath>
|
||||||
|
</File>
|
||||||
|
</Files>
|
||||||
|
<Files>
|
||||||
|
<File>
|
||||||
|
<FileName>div0.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\..\libcpu\arm\common\div0.c</FilePath>
|
||||||
|
</File>
|
||||||
|
</Files>
|
||||||
|
<Files>
|
||||||
|
<File>
|
||||||
|
<FileName>showmem.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\..\libcpu\arm\common\showmem.c</FilePath>
|
||||||
|
</File>
|
||||||
|
</Files>
|
||||||
|
<Files>
|
||||||
|
<File>
|
||||||
|
<FileName>context_rvds.S</FileName>
|
||||||
|
<FileType>2</FileType>
|
||||||
|
<FilePath>..\..\..\..\libcpu\arm\cortex-m4\context_rvds.S</FilePath>
|
||||||
|
</File>
|
||||||
|
</Files>
|
||||||
|
<Files>
|
||||||
|
<File>
|
||||||
|
<FileName>cpuport.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\..\libcpu\arm\cortex-m4\cpuport.c</FilePath>
|
||||||
|
</File>
|
||||||
|
</Files>
|
||||||
|
</Group>
|
||||||
|
<Group>
|
||||||
|
<GroupName>DeviceDrivers</GroupName>
|
||||||
|
<Files>
|
||||||
|
<File>
|
||||||
|
<FileName>completion.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\..\components\drivers\ipc\completion.c</FilePath>
|
||||||
|
</File>
|
||||||
|
</Files>
|
||||||
|
<Files>
|
||||||
|
<File>
|
||||||
|
<FileName>dataqueue.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\..\components\drivers\ipc\dataqueue.c</FilePath>
|
||||||
|
</File>
|
||||||
|
</Files>
|
||||||
|
<Files>
|
||||||
|
<File>
|
||||||
|
<FileName>pipe.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\..\components\drivers\ipc\pipe.c</FilePath>
|
||||||
|
</File>
|
||||||
|
</Files>
|
||||||
|
<Files>
|
||||||
|
<File>
|
||||||
|
<FileName>ringblk_buf.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\..\components\drivers\ipc\ringblk_buf.c</FilePath>
|
||||||
|
</File>
|
||||||
|
</Files>
|
||||||
|
<Files>
|
||||||
|
<File>
|
||||||
|
<FileName>ringbuffer.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\..\components\drivers\ipc\ringbuffer.c</FilePath>
|
||||||
|
</File>
|
||||||
|
</Files>
|
||||||
|
<Files>
|
||||||
|
<File>
|
||||||
|
<FileName>waitqueue.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\..\components\drivers\ipc\waitqueue.c</FilePath>
|
||||||
|
</File>
|
||||||
|
</Files>
|
||||||
|
<Files>
|
||||||
|
<File>
|
||||||
|
<FileName>workqueue.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\..\components\drivers\ipc\workqueue.c</FilePath>
|
||||||
|
</File>
|
||||||
|
</Files>
|
||||||
|
<Files>
|
||||||
|
<File>
|
||||||
|
<FileName>pin.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\..\components\drivers\misc\pin.c</FilePath>
|
||||||
|
</File>
|
||||||
|
</Files>
|
||||||
|
<Files>
|
||||||
|
<File>
|
||||||
|
<FileName>serial.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\..\components\drivers\serial\serial.c</FilePath>
|
||||||
|
</File>
|
||||||
|
</Files>
|
||||||
|
</Group>
|
||||||
|
<Group>
|
||||||
|
<GroupName>Drivers</GroupName>
|
||||||
|
<Files>
|
||||||
|
<File>
|
||||||
|
<FileName>board.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>board\board.c</FilePath>
|
||||||
|
</File>
|
||||||
|
</Files>
|
||||||
|
<Files>
|
||||||
|
<File>
|
||||||
|
<FileName>startup_gd32f4xx.s</FileName>
|
||||||
|
<FileType>2</FileType>
|
||||||
|
<FilePath>..\libraries\GD32F4xx_Firmware_Library\CMSIS\GD\GD32F4xx\Source\ARM\startup_gd32f4xx.s</FilePath>
|
||||||
|
</File>
|
||||||
|
</Files>
|
||||||
|
<Files>
|
||||||
|
<File>
|
||||||
|
<FileName>drv_gpio.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\libraries\gd32_drivers\drv_gpio.c</FilePath>
|
||||||
|
</File>
|
||||||
|
</Files>
|
||||||
|
<Files>
|
||||||
|
<File>
|
||||||
|
<FileName>drv_usart.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\libraries\gd32_drivers\drv_usart.c</FilePath>
|
||||||
|
</File>
|
||||||
|
</Files>
|
||||||
|
</Group>
|
||||||
|
<Group>
|
||||||
|
<GroupName>Filesystem</GroupName>
|
||||||
|
<Files>
|
||||||
|
<File>
|
||||||
|
<FileName>dfs_posix.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\..\components\dfs\src\dfs_posix.c</FilePath>
|
||||||
|
</File>
|
||||||
|
</Files>
|
||||||
|
<Files>
|
||||||
|
<File>
|
||||||
|
<FileName>dfs_fs.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\..\components\dfs\src\dfs_fs.c</FilePath>
|
||||||
|
</File>
|
||||||
|
</Files>
|
||||||
|
<Files>
|
||||||
|
<File>
|
||||||
|
<FileName>dfs.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\..\components\dfs\src\dfs.c</FilePath>
|
||||||
|
</File>
|
||||||
|
</Files>
|
||||||
|
<Files>
|
||||||
|
<File>
|
||||||
|
<FileName>dfs_file.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\..\components\dfs\src\dfs_file.c</FilePath>
|
||||||
|
</File>
|
||||||
|
</Files>
|
||||||
|
</Group>
|
||||||
|
<Group>
|
||||||
|
<GroupName>Finsh</GroupName>
|
||||||
|
<Files>
|
||||||
|
<File>
|
||||||
|
<FileName>shell.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\..\components\finsh\shell.c</FilePath>
|
||||||
|
</File>
|
||||||
|
</Files>
|
||||||
|
<Files>
|
||||||
|
<File>
|
||||||
|
<FileName>msh.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\..\components\finsh\msh.c</FilePath>
|
||||||
|
</File>
|
||||||
|
</Files>
|
||||||
|
<Files>
|
||||||
|
<File>
|
||||||
|
<FileName>msh_parse.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\..\components\finsh\msh_parse.c</FilePath>
|
||||||
|
</File>
|
||||||
|
</Files>
|
||||||
|
<Files>
|
||||||
|
<File>
|
||||||
|
<FileName>cmd.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\..\components\finsh\cmd.c</FilePath>
|
||||||
|
</File>
|
||||||
|
</Files>
|
||||||
|
<Files>
|
||||||
|
<File>
|
||||||
|
<FileName>msh_file.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\..\components\finsh\msh_file.c</FilePath>
|
||||||
|
</File>
|
||||||
|
</Files>
|
||||||
|
</Group>
|
||||||
|
<Group>
|
||||||
|
<GroupName>Kernel</GroupName>
|
||||||
|
<Files>
|
||||||
|
<File>
|
||||||
|
<FileName>clock.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\..\src\clock.c</FilePath>
|
||||||
|
</File>
|
||||||
|
</Files>
|
||||||
|
<Files>
|
||||||
|
<File>
|
||||||
|
<FileName>components.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\..\src\components.c</FilePath>
|
||||||
|
</File>
|
||||||
|
</Files>
|
||||||
|
<Files>
|
||||||
|
<File>
|
||||||
|
<FileName>device.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\..\src\device.c</FilePath>
|
||||||
|
</File>
|
||||||
|
</Files>
|
||||||
|
<Files>
|
||||||
|
<File>
|
||||||
|
<FileName>idle.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\..\src\idle.c</FilePath>
|
||||||
|
</File>
|
||||||
|
</Files>
|
||||||
|
<Files>
|
||||||
|
<File>
|
||||||
|
<FileName>ipc.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\..\src\ipc.c</FilePath>
|
||||||
|
</File>
|
||||||
|
</Files>
|
||||||
|
<Files>
|
||||||
|
<File>
|
||||||
|
<FileName>irq.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\..\src\irq.c</FilePath>
|
||||||
|
</File>
|
||||||
|
</Files>
|
||||||
|
<Files>
|
||||||
|
<File>
|
||||||
|
<FileName>kservice.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\..\src\kservice.c</FilePath>
|
||||||
|
</File>
|
||||||
|
</Files>
|
||||||
|
<Files>
|
||||||
|
<File>
|
||||||
|
<FileName>mem.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\..\src\mem.c</FilePath>
|
||||||
|
</File>
|
||||||
|
</Files>
|
||||||
|
<Files>
|
||||||
|
<File>
|
||||||
|
<FileName>mempool.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\..\src\mempool.c</FilePath>
|
||||||
|
</File>
|
||||||
|
</Files>
|
||||||
|
<Files>
|
||||||
|
<File>
|
||||||
|
<FileName>object.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\..\src\object.c</FilePath>
|
||||||
|
</File>
|
||||||
|
</Files>
|
||||||
|
<Files>
|
||||||
|
<File>
|
||||||
|
<FileName>scheduler.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\..\src\scheduler.c</FilePath>
|
||||||
|
</File>
|
||||||
|
</Files>
|
||||||
|
<Files>
|
||||||
|
<File>
|
||||||
|
<FileName>thread.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\..\src\thread.c</FilePath>
|
||||||
|
</File>
|
||||||
|
</Files>
|
||||||
|
<Files>
|
||||||
|
<File>
|
||||||
|
<FileName>timer.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\..\src\timer.c</FilePath>
|
||||||
|
</File>
|
||||||
|
</Files>
|
||||||
|
</Group>
|
||||||
|
<Group>
|
||||||
|
<GroupName>Libraries</GroupName>
|
||||||
|
<Files>
|
||||||
|
<File>
|
||||||
|
<FileName>gd32f4xx_syscfg.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\libraries\GD32F4xx_Firmware_Library\GD32F4xx_standard_peripheral\Source\gd32f4xx_syscfg.c</FilePath>
|
||||||
|
</File>
|
||||||
|
</Files>
|
||||||
|
<Files>
|
||||||
|
<File>
|
||||||
|
<FileName>gd32f4xx_exti.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\libraries\GD32F4xx_Firmware_Library\GD32F4xx_standard_peripheral\Source\gd32f4xx_exti.c</FilePath>
|
||||||
|
</File>
|
||||||
|
</Files>
|
||||||
|
<Files>
|
||||||
|
<File>
|
||||||
|
<FileName>gd32f4xx_gpio.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\libraries\GD32F4xx_Firmware_Library\GD32F4xx_standard_peripheral\Source\gd32f4xx_gpio.c</FilePath>
|
||||||
|
</File>
|
||||||
|
</Files>
|
||||||
|
<Files>
|
||||||
|
<File>
|
||||||
|
<FileName>gd32f4xx_rcu.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\libraries\GD32F4xx_Firmware_Library\GD32F4xx_standard_peripheral\Source\gd32f4xx_rcu.c</FilePath>
|
||||||
|
</File>
|
||||||
|
</Files>
|
||||||
|
<Files>
|
||||||
|
<File>
|
||||||
|
<FileName>gd32f4xx_misc.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\libraries\GD32F4xx_Firmware_Library\GD32F4xx_standard_peripheral\Source\gd32f4xx_misc.c</FilePath>
|
||||||
|
</File>
|
||||||
|
</Files>
|
||||||
|
<Files>
|
||||||
|
<File>
|
||||||
|
<FileName>gd32f4xx_usart.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\libraries\GD32F4xx_Firmware_Library\GD32F4xx_standard_peripheral\Source\gd32f4xx_usart.c</FilePath>
|
||||||
|
</File>
|
||||||
|
</Files>
|
||||||
|
<Files>
|
||||||
|
<File>
|
||||||
|
<FileName>system_gd32f4xx.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\libraries\GD32F4xx_Firmware_Library\CMSIS\GD\GD32F4xx\Source\system_gd32f4xx.c</FilePath>
|
||||||
|
</File>
|
||||||
|
</Files>
|
||||||
|
</Group>
|
||||||
|
</Groups>
|
||||||
|
</Target>
|
||||||
|
</Targets>
|
||||||
|
</Project>
|
||||||
|
|
@ -0,0 +1,732 @@
|
||||||
|
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||||
|
<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
|
||||||
|
|
||||||
|
<SchemaVersion>2.1</SchemaVersion>
|
||||||
|
|
||||||
|
<Header>### uVision Project, (C) Keil Software</Header>
|
||||||
|
|
||||||
|
<Targets>
|
||||||
|
<Target>
|
||||||
|
<TargetName>rt-thread</TargetName>
|
||||||
|
<ToolsetNumber>0x4</ToolsetNumber>
|
||||||
|
<ToolsetName>ARM-ADS</ToolsetName>
|
||||||
|
<uAC6>0</uAC6>
|
||||||
|
<TargetOption>
|
||||||
|
<TargetCommonOption>
|
||||||
|
<Device>GD32F470ZG</Device>
|
||||||
|
<Vendor>GigaDevice</Vendor>
|
||||||
|
<PackID>GigaDevice.GD32F4xx_DFP.3.0.0</PackID>
|
||||||
|
<PackURL>http://gd32mcu.com/data/documents/pack/</PackURL>
|
||||||
|
<Cpu>IRAM(0x20000000,0x070000) IRAM2(0x10000000,0x010000) IROM(0x08000000,0x0100000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE</Cpu>
|
||||||
|
<FlashUtilSpec></FlashUtilSpec>
|
||||||
|
<StartupFile></StartupFile>
|
||||||
|
<FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0GD32F4xx_1MB -FS08000000 -FL0100000 -FP0($$Device:GD32F470ZG$Flash\GD32F4xx_1MB.FLM))</FlashDriverDll>
|
||||||
|
<DeviceId>0</DeviceId>
|
||||||
|
<RegisterFile>$$Device:GD32F470ZG$Device\F4XX\Include\gd32f4xx.h</RegisterFile>
|
||||||
|
<MemoryEnv></MemoryEnv>
|
||||||
|
<Cmp></Cmp>
|
||||||
|
<Asm></Asm>
|
||||||
|
<Linker></Linker>
|
||||||
|
<OHString></OHString>
|
||||||
|
<InfinionOptionDll></InfinionOptionDll>
|
||||||
|
<SLE66CMisc></SLE66CMisc>
|
||||||
|
<SLE66AMisc></SLE66AMisc>
|
||||||
|
<SLE66LinkerMisc></SLE66LinkerMisc>
|
||||||
|
<SFDFile>$$Device:GD32F470ZG$SVD\GD32F4xx.svd</SFDFile>
|
||||||
|
<bCustSvd>0</bCustSvd>
|
||||||
|
<UseEnv>0</UseEnv>
|
||||||
|
<BinPath></BinPath>
|
||||||
|
<IncludePath></IncludePath>
|
||||||
|
<LibPath></LibPath>
|
||||||
|
<RegisterFilePath></RegisterFilePath>
|
||||||
|
<DBRegisterFilePath></DBRegisterFilePath>
|
||||||
|
<TargetStatus>
|
||||||
|
<Error>0</Error>
|
||||||
|
<ExitCodeStop>0</ExitCodeStop>
|
||||||
|
<ButtonStop>0</ButtonStop>
|
||||||
|
<NotGenerated>0</NotGenerated>
|
||||||
|
<InvalidFlash>1</InvalidFlash>
|
||||||
|
</TargetStatus>
|
||||||
|
<OutputDirectory>.\build\</OutputDirectory>
|
||||||
|
<OutputName>rtthread</OutputName>
|
||||||
|
<CreateExecutable>1</CreateExecutable>
|
||||||
|
<CreateLib>0</CreateLib>
|
||||||
|
<CreateHexFile>0</CreateHexFile>
|
||||||
|
<DebugInformation>1</DebugInformation>
|
||||||
|
<BrowseInformation>0</BrowseInformation>
|
||||||
|
<ListingPath>.\build\</ListingPath>
|
||||||
|
<HexFormatSelection>1</HexFormatSelection>
|
||||||
|
<Merge32K>0</Merge32K>
|
||||||
|
<CreateBatchFile>0</CreateBatchFile>
|
||||||
|
<BeforeCompile>
|
||||||
|
<RunUserProg1>0</RunUserProg1>
|
||||||
|
<RunUserProg2>0</RunUserProg2>
|
||||||
|
<UserProg1Name></UserProg1Name>
|
||||||
|
<UserProg2Name></UserProg2Name>
|
||||||
|
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||||
|
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||||
|
<nStopU1X>0</nStopU1X>
|
||||||
|
<nStopU2X>0</nStopU2X>
|
||||||
|
</BeforeCompile>
|
||||||
|
<BeforeMake>
|
||||||
|
<RunUserProg1>0</RunUserProg1>
|
||||||
|
<RunUserProg2>0</RunUserProg2>
|
||||||
|
<UserProg1Name></UserProg1Name>
|
||||||
|
<UserProg2Name></UserProg2Name>
|
||||||
|
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||||
|
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||||
|
<nStopB1X>0</nStopB1X>
|
||||||
|
<nStopB2X>0</nStopB2X>
|
||||||
|
</BeforeMake>
|
||||||
|
<AfterMake>
|
||||||
|
<RunUserProg1>1</RunUserProg1>
|
||||||
|
<RunUserProg2>0</RunUserProg2>
|
||||||
|
<UserProg1Name>fromelf --bin !L --output rtthread.bin</UserProg1Name>
|
||||||
|
<UserProg2Name></UserProg2Name>
|
||||||
|
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||||
|
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||||
|
<nStopA1X>0</nStopA1X>
|
||||||
|
<nStopA2X>0</nStopA2X>
|
||||||
|
</AfterMake>
|
||||||
|
<SelectedForBatchBuild>0</SelectedForBatchBuild>
|
||||||
|
<SVCSIdString></SVCSIdString>
|
||||||
|
</TargetCommonOption>
|
||||||
|
<CommonProperty>
|
||||||
|
<UseCPPCompiler>0</UseCPPCompiler>
|
||||||
|
<RVCTCodeConst>0</RVCTCodeConst>
|
||||||
|
<RVCTZI>0</RVCTZI>
|
||||||
|
<RVCTOtherData>0</RVCTOtherData>
|
||||||
|
<ModuleSelection>0</ModuleSelection>
|
||||||
|
<IncludeInBuild>1</IncludeInBuild>
|
||||||
|
<AlwaysBuild>0</AlwaysBuild>
|
||||||
|
<GenerateAssemblyFile>0</GenerateAssemblyFile>
|
||||||
|
<AssembleAssemblyFile>0</AssembleAssemblyFile>
|
||||||
|
<PublicsOnly>0</PublicsOnly>
|
||||||
|
<StopOnExitCode>3</StopOnExitCode>
|
||||||
|
<CustomArgument></CustomArgument>
|
||||||
|
<IncludeLibraryModules></IncludeLibraryModules>
|
||||||
|
<ComprImg>1</ComprImg>
|
||||||
|
</CommonProperty>
|
||||||
|
<DllOption>
|
||||||
|
<SimDllName>SARMCM3.DLL</SimDllName>
|
||||||
|
<SimDllArguments> -REMAP -MPU</SimDllArguments>
|
||||||
|
<SimDlgDll>DCM.DLL</SimDlgDll>
|
||||||
|
<SimDlgDllArguments>-pCM4</SimDlgDllArguments>
|
||||||
|
<TargetDllName>SARMCM3.DLL</TargetDllName>
|
||||||
|
<TargetDllArguments> -MPU</TargetDllArguments>
|
||||||
|
<TargetDlgDll>TCM.DLL</TargetDlgDll>
|
||||||
|
<TargetDlgDllArguments>-pCM4</TargetDlgDllArguments>
|
||||||
|
</DllOption>
|
||||||
|
<DebugOption>
|
||||||
|
<OPTHX>
|
||||||
|
<HexSelection>1</HexSelection>
|
||||||
|
<HexRangeLowAddress>0</HexRangeLowAddress>
|
||||||
|
<HexRangeHighAddress>0</HexRangeHighAddress>
|
||||||
|
<HexOffset>0</HexOffset>
|
||||||
|
<Oh166RecLen>16</Oh166RecLen>
|
||||||
|
</OPTHX>
|
||||||
|
</DebugOption>
|
||||||
|
<Utilities>
|
||||||
|
<Flash1>
|
||||||
|
<UseTargetDll>1</UseTargetDll>
|
||||||
|
<UseExternalTool>0</UseExternalTool>
|
||||||
|
<RunIndependent>0</RunIndependent>
|
||||||
|
<UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
|
||||||
|
<Capability>1</Capability>
|
||||||
|
<DriverSelection>4096</DriverSelection>
|
||||||
|
</Flash1>
|
||||||
|
<bUseTDR>1</bUseTDR>
|
||||||
|
<Flash2>BIN\UL2CM3.DLL</Flash2>
|
||||||
|
<Flash3></Flash3>
|
||||||
|
<Flash4></Flash4>
|
||||||
|
<pFcarmOut></pFcarmOut>
|
||||||
|
<pFcarmGrp></pFcarmGrp>
|
||||||
|
<pFcArmRoot></pFcArmRoot>
|
||||||
|
<FcArmLst>0</FcArmLst>
|
||||||
|
</Utilities>
|
||||||
|
<TargetArmAds>
|
||||||
|
<ArmAdsMisc>
|
||||||
|
<GenerateListings>0</GenerateListings>
|
||||||
|
<asHll>1</asHll>
|
||||||
|
<asAsm>1</asAsm>
|
||||||
|
<asMacX>1</asMacX>
|
||||||
|
<asSyms>1</asSyms>
|
||||||
|
<asFals>1</asFals>
|
||||||
|
<asDbgD>1</asDbgD>
|
||||||
|
<asForm>1</asForm>
|
||||||
|
<ldLst>0</ldLst>
|
||||||
|
<ldmm>1</ldmm>
|
||||||
|
<ldXref>1</ldXref>
|
||||||
|
<BigEnd>0</BigEnd>
|
||||||
|
<AdsALst>1</AdsALst>
|
||||||
|
<AdsACrf>1</AdsACrf>
|
||||||
|
<AdsANop>0</AdsANop>
|
||||||
|
<AdsANot>0</AdsANot>
|
||||||
|
<AdsLLst>1</AdsLLst>
|
||||||
|
<AdsLmap>1</AdsLmap>
|
||||||
|
<AdsLcgr>1</AdsLcgr>
|
||||||
|
<AdsLsym>1</AdsLsym>
|
||||||
|
<AdsLszi>1</AdsLszi>
|
||||||
|
<AdsLtoi>1</AdsLtoi>
|
||||||
|
<AdsLsun>1</AdsLsun>
|
||||||
|
<AdsLven>1</AdsLven>
|
||||||
|
<AdsLsxf>1</AdsLsxf>
|
||||||
|
<RvctClst>0</RvctClst>
|
||||||
|
<GenPPlst>0</GenPPlst>
|
||||||
|
<AdsCpuType>"Cortex-M4"</AdsCpuType>
|
||||||
|
<RvctDeviceName></RvctDeviceName>
|
||||||
|
<mOS>0</mOS>
|
||||||
|
<uocRom>0</uocRom>
|
||||||
|
<uocRam>0</uocRam>
|
||||||
|
<hadIROM>1</hadIROM>
|
||||||
|
<hadIRAM>1</hadIRAM>
|
||||||
|
<hadXRAM>0</hadXRAM>
|
||||||
|
<uocXRam>0</uocXRam>
|
||||||
|
<RvdsVP>2</RvdsVP>
|
||||||
|
<RvdsMve>0</RvdsMve>
|
||||||
|
<RvdsCdeCp>0</RvdsCdeCp>
|
||||||
|
<hadIRAM2>1</hadIRAM2>
|
||||||
|
<hadIROM2>0</hadIROM2>
|
||||||
|
<StupSel>8</StupSel>
|
||||||
|
<useUlib>0</useUlib>
|
||||||
|
<EndSel>0</EndSel>
|
||||||
|
<uLtcg>0</uLtcg>
|
||||||
|
<nSecure>0</nSecure>
|
||||||
|
<RoSelD>3</RoSelD>
|
||||||
|
<RwSelD>4</RwSelD>
|
||||||
|
<CodeSel>0</CodeSel>
|
||||||
|
<OptFeed>0</OptFeed>
|
||||||
|
<NoZi1>0</NoZi1>
|
||||||
|
<NoZi2>0</NoZi2>
|
||||||
|
<NoZi3>0</NoZi3>
|
||||||
|
<NoZi4>0</NoZi4>
|
||||||
|
<NoZi5>0</NoZi5>
|
||||||
|
<Ro1Chk>0</Ro1Chk>
|
||||||
|
<Ro2Chk>0</Ro2Chk>
|
||||||
|
<Ro3Chk>0</Ro3Chk>
|
||||||
|
<Ir1Chk>1</Ir1Chk>
|
||||||
|
<Ir2Chk>0</Ir2Chk>
|
||||||
|
<Ra1Chk>0</Ra1Chk>
|
||||||
|
<Ra2Chk>0</Ra2Chk>
|
||||||
|
<Ra3Chk>0</Ra3Chk>
|
||||||
|
<Im1Chk>1</Im1Chk>
|
||||||
|
<Im2Chk>0</Im2Chk>
|
||||||
|
<OnChipMemories>
|
||||||
|
<Ocm1>
|
||||||
|
<Type>0</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x0</Size>
|
||||||
|
</Ocm1>
|
||||||
|
<Ocm2>
|
||||||
|
<Type>0</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x0</Size>
|
||||||
|
</Ocm2>
|
||||||
|
<Ocm3>
|
||||||
|
<Type>0</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x0</Size>
|
||||||
|
</Ocm3>
|
||||||
|
<Ocm4>
|
||||||
|
<Type>0</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x0</Size>
|
||||||
|
</Ocm4>
|
||||||
|
<Ocm5>
|
||||||
|
<Type>0</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x0</Size>
|
||||||
|
</Ocm5>
|
||||||
|
<Ocm6>
|
||||||
|
<Type>0</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x0</Size>
|
||||||
|
</Ocm6>
|
||||||
|
<IRAM>
|
||||||
|
<Type>0</Type>
|
||||||
|
<StartAddress>0x20000000</StartAddress>
|
||||||
|
<Size>0x70000</Size>
|
||||||
|
</IRAM>
|
||||||
|
<IROM>
|
||||||
|
<Type>1</Type>
|
||||||
|
<StartAddress>0x8000000</StartAddress>
|
||||||
|
<Size>0x100000</Size>
|
||||||
|
</IROM>
|
||||||
|
<XRAM>
|
||||||
|
<Type>0</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x0</Size>
|
||||||
|
</XRAM>
|
||||||
|
<OCR_RVCT1>
|
||||||
|
<Type>1</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x0</Size>
|
||||||
|
</OCR_RVCT1>
|
||||||
|
<OCR_RVCT2>
|
||||||
|
<Type>1</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x0</Size>
|
||||||
|
</OCR_RVCT2>
|
||||||
|
<OCR_RVCT3>
|
||||||
|
<Type>1</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x0</Size>
|
||||||
|
</OCR_RVCT3>
|
||||||
|
<OCR_RVCT4>
|
||||||
|
<Type>1</Type>
|
||||||
|
<StartAddress>0x8000000</StartAddress>
|
||||||
|
<Size>0x100000</Size>
|
||||||
|
</OCR_RVCT4>
|
||||||
|
<OCR_RVCT5>
|
||||||
|
<Type>1</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x0</Size>
|
||||||
|
</OCR_RVCT5>
|
||||||
|
<OCR_RVCT6>
|
||||||
|
<Type>0</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x0</Size>
|
||||||
|
</OCR_RVCT6>
|
||||||
|
<OCR_RVCT7>
|
||||||
|
<Type>0</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x0</Size>
|
||||||
|
</OCR_RVCT7>
|
||||||
|
<OCR_RVCT8>
|
||||||
|
<Type>0</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x0</Size>
|
||||||
|
</OCR_RVCT8>
|
||||||
|
<OCR_RVCT9>
|
||||||
|
<Type>0</Type>
|
||||||
|
<StartAddress>0x20000000</StartAddress>
|
||||||
|
<Size>0x70000</Size>
|
||||||
|
</OCR_RVCT9>
|
||||||
|
<OCR_RVCT10>
|
||||||
|
<Type>0</Type>
|
||||||
|
<StartAddress>0x10000000</StartAddress>
|
||||||
|
<Size>0x10000</Size>
|
||||||
|
</OCR_RVCT10>
|
||||||
|
</OnChipMemories>
|
||||||
|
<RvctStartVector></RvctStartVector>
|
||||||
|
</ArmAdsMisc>
|
||||||
|
<Cads>
|
||||||
|
<interw>1</interw>
|
||||||
|
<Optim>4</Optim>
|
||||||
|
<oTime>0</oTime>
|
||||||
|
<SplitLS>0</SplitLS>
|
||||||
|
<OneElfS>1</OneElfS>
|
||||||
|
<Strict>0</Strict>
|
||||||
|
<EnumInt>0</EnumInt>
|
||||||
|
<PlainCh>0</PlainCh>
|
||||||
|
<Ropi>0</Ropi>
|
||||||
|
<Rwpi>0</Rwpi>
|
||||||
|
<wLevel>0</wLevel>
|
||||||
|
<uThumb>0</uThumb>
|
||||||
|
<uSurpInc>0</uSurpInc>
|
||||||
|
<uC99>1</uC99>
|
||||||
|
<uGnu>0</uGnu>
|
||||||
|
<useXO>0</useXO>
|
||||||
|
<v6Lang>1</v6Lang>
|
||||||
|
<v6LangP>1</v6LangP>
|
||||||
|
<vShortEn>1</vShortEn>
|
||||||
|
<vShortWch>1</vShortWch>
|
||||||
|
<v6Lto>0</v6Lto>
|
||||||
|
<v6WtE>0</v6WtE>
|
||||||
|
<v6Rtti>0</v6Rtti>
|
||||||
|
<VariousControls>
|
||||||
|
<MiscControls></MiscControls>
|
||||||
|
<Define>__STDC_LIMIT_MACROS, RT_USING_ARMLIBC, USE_STDPERIPH_DRIVER, GD32F470, RT_USING_LIBC, __CLK_TCK=RT_TICK_PER_SECOND, __RTTHREAD__</Define>
|
||||||
|
<Undefine></Undefine>
|
||||||
|
<IncludePath>..\..\..\..\components\drivers\include;..\..\..\..\components\dfs\include;..\..\..\..\components\drivers\include;..\..\..\..\components\libc\posix\io\stdio;..\libraries\GD32F4xx_Firmware_Library\GD32F4xx_standard_peripheral\Include;..\..\..\..\components\finsh;..\..\..\..\libcpu\arm\cortex-m4;..\..\..\..\components\libc\compilers\common\include;..\..\..\..\components\libc\compilers\common\extension\fcntl\octal;..\libraries\gd32_drivers;board;..\..\..\..\libcpu\arm\common;..\libraries\GD32F4xx_Firmware_Library\CMSIS;applications;..\libraries\GD32F4xx_Firmware_Library\CMSIS\GD\GD32F4xx\Include;..\..\..\..\components\drivers\include;..\..\..\..\components\libc\compilers\common\extension;..\..\..\..\components\libc\posix\io\poll;..\..\..\..\include;.;..\..\..\..\components\libc\posix\ipc</IncludePath>
|
||||||
|
</VariousControls>
|
||||||
|
</Cads>
|
||||||
|
<Aads>
|
||||||
|
<interw>1</interw>
|
||||||
|
<Ropi>0</Ropi>
|
||||||
|
<Rwpi>0</Rwpi>
|
||||||
|
<thumb>0</thumb>
|
||||||
|
<SplitLS>0</SplitLS>
|
||||||
|
<SwStkChk>0</SwStkChk>
|
||||||
|
<NoWarn>0</NoWarn>
|
||||||
|
<uSurpInc>0</uSurpInc>
|
||||||
|
<useXO>0</useXO>
|
||||||
|
<ClangAsOpt>4</ClangAsOpt>
|
||||||
|
<VariousControls>
|
||||||
|
<MiscControls></MiscControls>
|
||||||
|
<Define></Define>
|
||||||
|
<Undefine></Undefine>
|
||||||
|
<IncludePath></IncludePath>
|
||||||
|
</VariousControls>
|
||||||
|
</Aads>
|
||||||
|
<LDads>
|
||||||
|
<umfTarg>1</umfTarg>
|
||||||
|
<Ropi>0</Ropi>
|
||||||
|
<Rwpi>0</Rwpi>
|
||||||
|
<noStLib>0</noStLib>
|
||||||
|
<RepFail>1</RepFail>
|
||||||
|
<useFile>0</useFile>
|
||||||
|
<TextAddressRange>0x08000000</TextAddressRange>
|
||||||
|
<DataAddressRange>0x20000000</DataAddressRange>
|
||||||
|
<pXoBase></pXoBase>
|
||||||
|
<ScatterFile>.\gd32_rom.ld</ScatterFile>
|
||||||
|
<IncludeLibs></IncludeLibs>
|
||||||
|
<IncludeLibsPath></IncludeLibsPath>
|
||||||
|
<Misc></Misc>
|
||||||
|
<LinkerInputFile></LinkerInputFile>
|
||||||
|
<DisabledWarnings></DisabledWarnings>
|
||||||
|
</LDads>
|
||||||
|
</TargetArmAds>
|
||||||
|
</TargetOption>
|
||||||
|
<Groups>
|
||||||
|
<Group>
|
||||||
|
<GroupName>Applications</GroupName>
|
||||||
|
<Files>
|
||||||
|
<File>
|
||||||
|
<FileName>main.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>applications\main.c</FilePath>
|
||||||
|
</File>
|
||||||
|
</Files>
|
||||||
|
</Group>
|
||||||
|
<Group>
|
||||||
|
<GroupName>Compiler</GroupName>
|
||||||
|
<Files>
|
||||||
|
<File>
|
||||||
|
<FileName>syscall_mem.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\..\components\libc\compilers\armlibc\syscall_mem.c</FilePath>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<FileName>syscalls.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\..\components\libc\compilers\armlibc\syscalls.c</FilePath>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<FileName>cctype.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\..\components\libc\compilers\common\cctype.c</FilePath>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<FileName>cstdio.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\..\components\libc\compilers\common\cstdio.c</FilePath>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<FileName>cstdlib.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\..\components\libc\compilers\common\cstdlib.c</FilePath>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<FileName>cstring.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\..\components\libc\compilers\common\cstring.c</FilePath>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<FileName>ctime.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\..\components\libc\compilers\common\ctime.c</FilePath>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<FileName>cwchar.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\..\components\libc\compilers\common\cwchar.c</FilePath>
|
||||||
|
</File>
|
||||||
|
</Files>
|
||||||
|
</Group>
|
||||||
|
<Group>
|
||||||
|
<GroupName>CPU</GroupName>
|
||||||
|
<Files>
|
||||||
|
<File>
|
||||||
|
<FileName>div0.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\..\libcpu\arm\common\div0.c</FilePath>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<FileName>showmem.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\..\libcpu\arm\common\showmem.c</FilePath>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<FileName>context_rvds.S</FileName>
|
||||||
|
<FileType>2</FileType>
|
||||||
|
<FilePath>..\..\..\..\libcpu\arm\cortex-m4\context_rvds.S</FilePath>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<FileName>cpuport.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\..\libcpu\arm\cortex-m4\cpuport.c</FilePath>
|
||||||
|
</File>
|
||||||
|
</Files>
|
||||||
|
</Group>
|
||||||
|
<Group>
|
||||||
|
<GroupName>DeviceDrivers</GroupName>
|
||||||
|
<Files>
|
||||||
|
<File>
|
||||||
|
<FileName>completion.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\..\components\drivers\ipc\completion.c</FilePath>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<FileName>dataqueue.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\..\components\drivers\ipc\dataqueue.c</FilePath>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<FileName>pipe.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\..\components\drivers\ipc\pipe.c</FilePath>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<FileName>ringblk_buf.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\..\components\drivers\ipc\ringblk_buf.c</FilePath>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<FileName>ringbuffer.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\..\components\drivers\ipc\ringbuffer.c</FilePath>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<FileName>waitqueue.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\..\components\drivers\ipc\waitqueue.c</FilePath>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<FileName>workqueue.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\..\components\drivers\ipc\workqueue.c</FilePath>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<FileName>pin.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\..\components\drivers\misc\pin.c</FilePath>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<FileName>serial.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\..\components\drivers\serial\serial.c</FilePath>
|
||||||
|
</File>
|
||||||
|
</Files>
|
||||||
|
</Group>
|
||||||
|
<Group>
|
||||||
|
<GroupName>Drivers</GroupName>
|
||||||
|
<Files>
|
||||||
|
<File>
|
||||||
|
<FileName>board.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>board\board.c</FilePath>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<FileName>startup_gd32f4xx.s</FileName>
|
||||||
|
<FileType>2</FileType>
|
||||||
|
<FilePath>..\libraries\GD32F4xx_Firmware_Library\CMSIS\GD\GD32F4xx\Source\ARM\startup_gd32f4xx.s</FilePath>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<FileName>drv_gpio.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\libraries\gd32_drivers\drv_gpio.c</FilePath>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<FileName>drv_usart.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\libraries\gd32_drivers\drv_usart.c</FilePath>
|
||||||
|
</File>
|
||||||
|
</Files>
|
||||||
|
</Group>
|
||||||
|
<Group>
|
||||||
|
<GroupName>Filesystem</GroupName>
|
||||||
|
<Files>
|
||||||
|
<File>
|
||||||
|
<FileName>dfs_posix.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\..\components\dfs\src\dfs_posix.c</FilePath>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<FileName>dfs_fs.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\..\components\dfs\src\dfs_fs.c</FilePath>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<FileName>dfs.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\..\components\dfs\src\dfs.c</FilePath>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<FileName>dfs_file.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\..\components\dfs\src\dfs_file.c</FilePath>
|
||||||
|
</File>
|
||||||
|
</Files>
|
||||||
|
</Group>
|
||||||
|
<Group>
|
||||||
|
<GroupName>Finsh</GroupName>
|
||||||
|
<Files>
|
||||||
|
<File>
|
||||||
|
<FileName>shell.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\..\components\finsh\shell.c</FilePath>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<FileName>msh.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\..\components\finsh\msh.c</FilePath>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<FileName>msh_parse.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\..\components\finsh\msh_parse.c</FilePath>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<FileName>cmd.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\..\components\finsh\cmd.c</FilePath>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<FileName>msh_file.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\..\components\finsh\msh_file.c</FilePath>
|
||||||
|
</File>
|
||||||
|
</Files>
|
||||||
|
</Group>
|
||||||
|
<Group>
|
||||||
|
<GroupName>Kernel</GroupName>
|
||||||
|
<Files>
|
||||||
|
<File>
|
||||||
|
<FileName>clock.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\..\src\clock.c</FilePath>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<FileName>components.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\..\src\components.c</FilePath>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<FileName>device.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\..\src\device.c</FilePath>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<FileName>idle.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\..\src\idle.c</FilePath>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<FileName>ipc.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\..\src\ipc.c</FilePath>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<FileName>irq.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\..\src\irq.c</FilePath>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<FileName>kservice.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\..\src\kservice.c</FilePath>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<FileName>mem.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\..\src\mem.c</FilePath>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<FileName>mempool.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\..\src\mempool.c</FilePath>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<FileName>object.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\..\src\object.c</FilePath>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<FileName>scheduler.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\..\src\scheduler.c</FilePath>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<FileName>thread.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\..\src\thread.c</FilePath>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<FileName>timer.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\..\src\timer.c</FilePath>
|
||||||
|
</File>
|
||||||
|
</Files>
|
||||||
|
</Group>
|
||||||
|
<Group>
|
||||||
|
<GroupName>Libraries</GroupName>
|
||||||
|
<Files>
|
||||||
|
<File>
|
||||||
|
<FileName>gd32f4xx_syscfg.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\libraries\GD32F4xx_Firmware_Library\GD32F4xx_standard_peripheral\Source\gd32f4xx_syscfg.c</FilePath>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<FileName>gd32f4xx_exti.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\libraries\GD32F4xx_Firmware_Library\GD32F4xx_standard_peripheral\Source\gd32f4xx_exti.c</FilePath>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<FileName>gd32f4xx_gpio.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\libraries\GD32F4xx_Firmware_Library\GD32F4xx_standard_peripheral\Source\gd32f4xx_gpio.c</FilePath>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<FileName>gd32f4xx_rcu.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\libraries\GD32F4xx_Firmware_Library\GD32F4xx_standard_peripheral\Source\gd32f4xx_rcu.c</FilePath>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<FileName>gd32f4xx_misc.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\libraries\GD32F4xx_Firmware_Library\GD32F4xx_standard_peripheral\Source\gd32f4xx_misc.c</FilePath>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<FileName>gd32f4xx_usart.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\libraries\GD32F4xx_Firmware_Library\GD32F4xx_standard_peripheral\Source\gd32f4xx_usart.c</FilePath>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<FileName>system_gd32f4xx.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\libraries\GD32F4xx_Firmware_Library\CMSIS\GD\GD32F4xx\Source\system_gd32f4xx.c</FilePath>
|
||||||
|
</File>
|
||||||
|
</Files>
|
||||||
|
</Group>
|
||||||
|
<Group>
|
||||||
|
<GroupName>::CMSIS</GroupName>
|
||||||
|
</Group>
|
||||||
|
</Groups>
|
||||||
|
</Target>
|
||||||
|
</Targets>
|
||||||
|
|
||||||
|
<RTE>
|
||||||
|
<apis/>
|
||||||
|
<components>
|
||||||
|
<component Cclass="CMSIS" Cgroup="CORE" Cvendor="ARM" Cversion="5.5.0" condition="ARMv6_7_8-M Device">
|
||||||
|
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.8.0"/>
|
||||||
|
<targetInfos>
|
||||||
|
<targetInfo name="rt-thread"/>
|
||||||
|
</targetInfos>
|
||||||
|
</component>
|
||||||
|
</components>
|
||||||
|
<files/>
|
||||||
|
</RTE>
|
||||||
|
|
||||||
|
<LayerInfo>
|
||||||
|
<Layers>
|
||||||
|
<Layer>
|
||||||
|
<LayName><Project Info></LayName>
|
||||||
|
<LayTarg>0</LayTarg>
|
||||||
|
<LayPrjMark>1</LayPrjMark>
|
||||||
|
</Layer>
|
||||||
|
</Layers>
|
||||||
|
</LayerInfo>
|
||||||
|
|
||||||
|
</Project>
|
||||||
|
|
@ -0,0 +1,201 @@
|
||||||
|
#ifndef RT_CONFIG_H__
|
||||||
|
#define RT_CONFIG_H__
|
||||||
|
|
||||||
|
/* Automatically generated file; DO NOT EDIT. */
|
||||||
|
/* RT-Thread Configuration */
|
||||||
|
|
||||||
|
/* RT-Thread Kernel */
|
||||||
|
|
||||||
|
#define RT_NAME_MAX 8
|
||||||
|
#define RT_ALIGN_SIZE 8
|
||||||
|
#define RT_THREAD_PRIORITY_32
|
||||||
|
#define RT_THREAD_PRIORITY_MAX 32
|
||||||
|
#define RT_TICK_PER_SECOND 1000
|
||||||
|
#define RT_USING_OVERFLOW_CHECK
|
||||||
|
#define RT_USING_HOOK
|
||||||
|
#define RT_HOOK_USING_FUNC_PTR
|
||||||
|
#define RT_USING_IDLE_HOOK
|
||||||
|
#define RT_IDLE_HOOK_LIST_SIZE 4
|
||||||
|
#define IDLE_THREAD_STACK_SIZE 256
|
||||||
|
#define RT_USING_TIMER_SOFT
|
||||||
|
#define RT_TIMER_THREAD_PRIO 4
|
||||||
|
#define RT_TIMER_THREAD_STACK_SIZE 512
|
||||||
|
|
||||||
|
/* kservice optimization */
|
||||||
|
|
||||||
|
#define RT_KSERVICE_USING_STDLIB
|
||||||
|
#define RT_DEBUG
|
||||||
|
|
||||||
|
/* Inter-Thread communication */
|
||||||
|
|
||||||
|
#define RT_USING_SEMAPHORE
|
||||||
|
#define RT_USING_MUTEX
|
||||||
|
#define RT_USING_EVENT
|
||||||
|
#define RT_USING_MAILBOX
|
||||||
|
#define RT_USING_MESSAGEQUEUE
|
||||||
|
|
||||||
|
/* Memory Management */
|
||||||
|
|
||||||
|
#define RT_PAGE_MAX_ORDER 11
|
||||||
|
#define RT_USING_MEMPOOL
|
||||||
|
#define RT_USING_SMALL_MEM
|
||||||
|
#define RT_USING_SMALL_MEM_AS_HEAP
|
||||||
|
#define RT_USING_HEAP
|
||||||
|
|
||||||
|
/* Kernel Device Object */
|
||||||
|
|
||||||
|
#define RT_USING_DEVICE
|
||||||
|
#define RT_USING_CONSOLE
|
||||||
|
#define RT_CONSOLEBUF_SIZE 128
|
||||||
|
#define RT_CONSOLE_DEVICE_NAME "uart0"
|
||||||
|
#define RT_VER_NUM 0x50000
|
||||||
|
|
||||||
|
/* RT-Thread Components */
|
||||||
|
|
||||||
|
#define RT_USING_COMPONENTS_INIT
|
||||||
|
#define RT_USING_USER_MAIN
|
||||||
|
#define RT_MAIN_THREAD_STACK_SIZE 2048
|
||||||
|
#define RT_MAIN_THREAD_PRIORITY 10
|
||||||
|
#define RT_USING_MSH
|
||||||
|
#define RT_USING_FINSH
|
||||||
|
#define FINSH_USING_MSH
|
||||||
|
#define FINSH_THREAD_NAME "tshell"
|
||||||
|
#define FINSH_THREAD_PRIORITY 20
|
||||||
|
#define FINSH_THREAD_STACK_SIZE 4096
|
||||||
|
#define FINSH_USING_HISTORY
|
||||||
|
#define FINSH_HISTORY_LINES 5
|
||||||
|
#define FINSH_USING_SYMTAB
|
||||||
|
#define FINSH_CMD_SIZE 80
|
||||||
|
#define MSH_USING_BUILT_IN_COMMANDS
|
||||||
|
#define FINSH_USING_DESCRIPTION
|
||||||
|
#define FINSH_ARG_MAX 10
|
||||||
|
#define RT_USING_DFS
|
||||||
|
#define DFS_USING_POSIX
|
||||||
|
#define DFS_USING_WORKDIR
|
||||||
|
#define DFS_FILESYSTEMS_MAX 4
|
||||||
|
#define DFS_FILESYSTEM_TYPES_MAX 4
|
||||||
|
#define DFS_FD_MAX 16
|
||||||
|
|
||||||
|
/* Device Drivers */
|
||||||
|
|
||||||
|
#define RT_USING_DEVICE_IPC
|
||||||
|
#define RT_UNAMED_PIPE_NUMBER 64
|
||||||
|
#define RT_USING_SERIAL
|
||||||
|
#define RT_USING_SERIAL_V1
|
||||||
|
#define RT_SERIAL_USING_DMA
|
||||||
|
#define RT_SERIAL_RB_BUFSZ 64
|
||||||
|
#define RT_USING_PIN
|
||||||
|
|
||||||
|
/* Using USB */
|
||||||
|
|
||||||
|
|
||||||
|
/* C/C++ and POSIX layer */
|
||||||
|
|
||||||
|
#define RT_LIBC_DEFAULT_TIMEZONE 8
|
||||||
|
|
||||||
|
/* POSIX (Portable Operating System Interface) layer */
|
||||||
|
|
||||||
|
|
||||||
|
/* Interprocess Communication (IPC) */
|
||||||
|
|
||||||
|
|
||||||
|
/* Socket is in the 'Network' category */
|
||||||
|
|
||||||
|
|
||||||
|
/* Network */
|
||||||
|
|
||||||
|
|
||||||
|
/* Utilities */
|
||||||
|
|
||||||
|
|
||||||
|
/* RT-Thread Utestcases */
|
||||||
|
|
||||||
|
|
||||||
|
/* RT-Thread online packages */
|
||||||
|
|
||||||
|
/* IoT - internet of things */
|
||||||
|
|
||||||
|
|
||||||
|
/* Wi-Fi */
|
||||||
|
|
||||||
|
/* Marvell WiFi */
|
||||||
|
|
||||||
|
|
||||||
|
/* Wiced WiFi */
|
||||||
|
|
||||||
|
|
||||||
|
/* IoT Cloud */
|
||||||
|
|
||||||
|
|
||||||
|
/* security packages */
|
||||||
|
|
||||||
|
|
||||||
|
/* language packages */
|
||||||
|
|
||||||
|
/* JSON: JavaScript Object Notation, a lightweight data-interchange format */
|
||||||
|
|
||||||
|
|
||||||
|
/* XML: Extensible Markup Language */
|
||||||
|
|
||||||
|
|
||||||
|
/* multimedia packages */
|
||||||
|
|
||||||
|
/* LVGL: powerful and easy-to-use embedded GUI library */
|
||||||
|
|
||||||
|
|
||||||
|
/* u8g2: a monochrome graphic library */
|
||||||
|
|
||||||
|
|
||||||
|
/* PainterEngine: A cross-platform graphics application framework written in C language */
|
||||||
|
|
||||||
|
|
||||||
|
/* tools packages */
|
||||||
|
|
||||||
|
|
||||||
|
/* system packages */
|
||||||
|
|
||||||
|
/* enhanced kernel services */
|
||||||
|
|
||||||
|
|
||||||
|
/* acceleration: Assembly language or algorithmic acceleration packages */
|
||||||
|
|
||||||
|
|
||||||
|
/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
|
||||||
|
|
||||||
|
|
||||||
|
/* Micrium: Micrium software products porting for RT-Thread */
|
||||||
|
|
||||||
|
|
||||||
|
/* peripheral libraries and drivers */
|
||||||
|
|
||||||
|
|
||||||
|
/* AI packages */
|
||||||
|
|
||||||
|
|
||||||
|
/* miscellaneous packages */
|
||||||
|
|
||||||
|
/* project laboratory */
|
||||||
|
|
||||||
|
/* samples: kernel and components samples */
|
||||||
|
|
||||||
|
|
||||||
|
/* entertainment: terminal games and other interesting software packages */
|
||||||
|
|
||||||
|
|
||||||
|
/* Hardware Drivers Config */
|
||||||
|
|
||||||
|
#define SOC_SERIES_GD32F4xx
|
||||||
|
#define SOC_GD32470Z
|
||||||
|
|
||||||
|
/* Onboard Peripheral Drivers */
|
||||||
|
|
||||||
|
/* On-chip Peripheral Drivers */
|
||||||
|
|
||||||
|
#define BSP_USING_GPIO
|
||||||
|
#define BSP_USING_UART
|
||||||
|
#define BSP_USING_UART0
|
||||||
|
|
||||||
|
/* Board extended module Drivers */
|
||||||
|
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
@ -0,0 +1,150 @@
|
||||||
|
import os
|
||||||
|
|
||||||
|
# toolchains options
|
||||||
|
ARCH='arm'
|
||||||
|
CPU='cortex-m4'
|
||||||
|
CROSS_TOOL='keil'
|
||||||
|
|
||||||
|
# bsp lib config
|
||||||
|
BSP_LIBRARY_TYPE = None
|
||||||
|
|
||||||
|
if os.getenv('RTT_CC'):
|
||||||
|
CROSS_TOOL = os.getenv('RTT_CC')
|
||||||
|
if os.getenv('RTT_ROOT'):
|
||||||
|
RTT_ROOT = os.getenv('RTT_ROOT')
|
||||||
|
|
||||||
|
# cross_tool provides the cross compiler
|
||||||
|
# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR
|
||||||
|
if CROSS_TOOL == 'gcc':
|
||||||
|
PLATFORM = 'gcc'
|
||||||
|
EXEC_PATH = r'C:\Users\XXYYZZ'
|
||||||
|
elif CROSS_TOOL == 'keil':
|
||||||
|
PLATFORM = 'armcc'
|
||||||
|
EXEC_PATH = r'C:/Keil_v5'
|
||||||
|
elif CROSS_TOOL == 'iar':
|
||||||
|
PLATFORM = 'iccarm'
|
||||||
|
EXEC_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.3'
|
||||||
|
|
||||||
|
if os.getenv('RTT_EXEC_PATH'):
|
||||||
|
EXEC_PATH = os.getenv('RTT_EXEC_PATH')
|
||||||
|
|
||||||
|
BUILD = 'debug'
|
||||||
|
|
||||||
|
if PLATFORM == 'gcc':
|
||||||
|
# toolchains
|
||||||
|
PREFIX = 'arm-none-eabi-'
|
||||||
|
CC = PREFIX + 'gcc'
|
||||||
|
AS = PREFIX + 'gcc'
|
||||||
|
AR = PREFIX + 'ar'
|
||||||
|
CXX = PREFIX + 'g++'
|
||||||
|
LINK = PREFIX + 'gcc'
|
||||||
|
TARGET_EXT = 'elf'
|
||||||
|
SIZE = PREFIX + 'size'
|
||||||
|
OBJDUMP = PREFIX + 'objdump'
|
||||||
|
OBJCPY = PREFIX + 'objcopy'
|
||||||
|
|
||||||
|
DEVICE = ' -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections -DGD32F450'
|
||||||
|
CFLAGS = DEVICE + ' -Dgcc'
|
||||||
|
AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb '
|
||||||
|
LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.ld'
|
||||||
|
|
||||||
|
CPATH = ''
|
||||||
|
LPATH = ''
|
||||||
|
|
||||||
|
if BUILD == 'debug':
|
||||||
|
CFLAGS += ' -O0 -gdwarf-2 -g'
|
||||||
|
AFLAGS += ' -gdwarf-2'
|
||||||
|
else:
|
||||||
|
CFLAGS += ' -O2'
|
||||||
|
|
||||||
|
CXXFLAGS = CFLAGS
|
||||||
|
|
||||||
|
POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
|
||||||
|
|
||||||
|
elif PLATFORM == 'armcc':
|
||||||
|
# toolchains
|
||||||
|
CC = 'armcc'
|
||||||
|
CXX = 'armcc'
|
||||||
|
AS = 'armasm'
|
||||||
|
AR = 'armar'
|
||||||
|
LINK = 'armlink'
|
||||||
|
TARGET_EXT = 'axf'
|
||||||
|
|
||||||
|
DEVICE = ' --cpu Cortex-M4.fp '
|
||||||
|
CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99'
|
||||||
|
AFLAGS = DEVICE + ' --apcs=interwork '
|
||||||
|
LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict'
|
||||||
|
CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include'
|
||||||
|
LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib'
|
||||||
|
|
||||||
|
CFLAGS += ' -D__MICROLIB '
|
||||||
|
AFLAGS += ' --pd "__MICROLIB SETA 1" '
|
||||||
|
LFLAGS += ' --library_type=microlib '
|
||||||
|
EXEC_PATH += '/ARM/ARMCC/bin/'
|
||||||
|
|
||||||
|
if BUILD == 'debug':
|
||||||
|
CFLAGS += ' -g -O0'
|
||||||
|
AFLAGS += ' -g'
|
||||||
|
else:
|
||||||
|
CFLAGS += ' -O2'
|
||||||
|
|
||||||
|
CXXFLAGS = CFLAGS
|
||||||
|
CFLAGS += ' -std=c99'
|
||||||
|
|
||||||
|
POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET'
|
||||||
|
|
||||||
|
elif PLATFORM == 'iccarm':
|
||||||
|
# toolchains
|
||||||
|
CC = 'iccarm'
|
||||||
|
CXX = 'iccarm'
|
||||||
|
AS = 'iasmarm'
|
||||||
|
AR = 'iarchive'
|
||||||
|
LINK = 'ilinkarm'
|
||||||
|
TARGET_EXT = 'out'
|
||||||
|
|
||||||
|
DEVICE = '-Dewarm'
|
||||||
|
|
||||||
|
CFLAGS = DEVICE
|
||||||
|
CFLAGS += ' --diag_suppress Pa050'
|
||||||
|
CFLAGS += ' --no_cse'
|
||||||
|
CFLAGS += ' --no_unroll'
|
||||||
|
CFLAGS += ' --no_inline'
|
||||||
|
CFLAGS += ' --no_code_motion'
|
||||||
|
CFLAGS += ' --no_tbaa'
|
||||||
|
CFLAGS += ' --no_clustering'
|
||||||
|
CFLAGS += ' --no_scheduling'
|
||||||
|
CFLAGS += ' --endian=little'
|
||||||
|
CFLAGS += ' --cpu=Cortex-M4'
|
||||||
|
CFLAGS += ' -e'
|
||||||
|
CFLAGS += ' --fpu=VFPv4_sp'
|
||||||
|
CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"'
|
||||||
|
CFLAGS += ' --silent'
|
||||||
|
|
||||||
|
AFLAGS = DEVICE
|
||||||
|
AFLAGS += ' -s+'
|
||||||
|
AFLAGS += ' -w+'
|
||||||
|
AFLAGS += ' -r'
|
||||||
|
AFLAGS += ' --cpu Cortex-M4'
|
||||||
|
AFLAGS += ' --fpu VFPv4_sp'
|
||||||
|
AFLAGS += ' -S'
|
||||||
|
|
||||||
|
if BUILD == 'debug':
|
||||||
|
CFLAGS += ' --debug'
|
||||||
|
CFLAGS += ' -On'
|
||||||
|
else:
|
||||||
|
CFLAGS += ' -Oh'
|
||||||
|
|
||||||
|
LFLAGS = ' --config "board/linker_scripts/link.icf"'
|
||||||
|
LFLAGS += ' --entry __iar_program_start'
|
||||||
|
|
||||||
|
CXXFLAGS = CFLAGS
|
||||||
|
|
||||||
|
EXEC_PATH = EXEC_PATH + '/arm/bin/'
|
||||||
|
POST_ACTION = 'ielftool --bin $TARGET rtthread.bin'
|
||||||
|
|
||||||
|
def dist_handle(BSP_ROOT, dist_dir):
|
||||||
|
import sys
|
||||||
|
cwd_path = os.getcwd()
|
||||||
|
sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools'))
|
||||||
|
from sdk_dist import dist_do_building
|
||||||
|
dist_do_building(BSP_ROOT, dist_dir)
|
||||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,185 @@
|
||||||
|
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||||
|
<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
|
||||||
|
|
||||||
|
<SchemaVersion>1.0</SchemaVersion>
|
||||||
|
|
||||||
|
<Header>### uVision Project, (C) Keil Software</Header>
|
||||||
|
|
||||||
|
<Extensions>
|
||||||
|
<cExt>*.c</cExt>
|
||||||
|
<aExt>*.s*; *.src; *.a*</aExt>
|
||||||
|
<oExt>*.obj; *.o</oExt>
|
||||||
|
<lExt>*.lib</lExt>
|
||||||
|
<tExt>*.txt; *.h; *.inc; *.md</tExt>
|
||||||
|
<pExt>*.plm</pExt>
|
||||||
|
<CppX>*.cpp</CppX>
|
||||||
|
<nMigrate>0</nMigrate>
|
||||||
|
</Extensions>
|
||||||
|
|
||||||
|
<DaveTm>
|
||||||
|
<dwLowDateTime>0</dwLowDateTime>
|
||||||
|
<dwHighDateTime>0</dwHighDateTime>
|
||||||
|
</DaveTm>
|
||||||
|
|
||||||
|
<Target>
|
||||||
|
<TargetName>rt-thread</TargetName>
|
||||||
|
<ToolsetNumber>0x4</ToolsetNumber>
|
||||||
|
<ToolsetName>ARM-ADS</ToolsetName>
|
||||||
|
<TargetOption>
|
||||||
|
<CLKADS>12000000</CLKADS>
|
||||||
|
<OPTTT>
|
||||||
|
<gFlags>1</gFlags>
|
||||||
|
<BeepAtEnd>1</BeepAtEnd>
|
||||||
|
<RunSim>0</RunSim>
|
||||||
|
<RunTarget>1</RunTarget>
|
||||||
|
<RunAbUc>0</RunAbUc>
|
||||||
|
</OPTTT>
|
||||||
|
<OPTHX>
|
||||||
|
<HexSelection>1</HexSelection>
|
||||||
|
<FlashByte>65535</FlashByte>
|
||||||
|
<HexRangeLowAddress>0</HexRangeLowAddress>
|
||||||
|
<HexRangeHighAddress>0</HexRangeHighAddress>
|
||||||
|
<HexOffset>0</HexOffset>
|
||||||
|
</OPTHX>
|
||||||
|
<OPTLEX>
|
||||||
|
<PageWidth>79</PageWidth>
|
||||||
|
<PageLength>66</PageLength>
|
||||||
|
<TabStop>8</TabStop>
|
||||||
|
<ListingPath>.\build\</ListingPath>
|
||||||
|
</OPTLEX>
|
||||||
|
<ListingPage>
|
||||||
|
<CreateCListing>1</CreateCListing>
|
||||||
|
<CreateAListing>1</CreateAListing>
|
||||||
|
<CreateLListing>1</CreateLListing>
|
||||||
|
<CreateIListing>0</CreateIListing>
|
||||||
|
<AsmCond>1</AsmCond>
|
||||||
|
<AsmSymb>1</AsmSymb>
|
||||||
|
<AsmXref>0</AsmXref>
|
||||||
|
<CCond>1</CCond>
|
||||||
|
<CCode>0</CCode>
|
||||||
|
<CListInc>0</CListInc>
|
||||||
|
<CSymb>0</CSymb>
|
||||||
|
<LinkerCodeListing>0</LinkerCodeListing>
|
||||||
|
</ListingPage>
|
||||||
|
<OPTXL>
|
||||||
|
<LMap>1</LMap>
|
||||||
|
<LComments>1</LComments>
|
||||||
|
<LGenerateSymbols>1</LGenerateSymbols>
|
||||||
|
<LLibSym>1</LLibSym>
|
||||||
|
<LLines>1</LLines>
|
||||||
|
<LLocSym>1</LLocSym>
|
||||||
|
<LPubSym>1</LPubSym>
|
||||||
|
<LXref>0</LXref>
|
||||||
|
<LExpSel>0</LExpSel>
|
||||||
|
</OPTXL>
|
||||||
|
<OPTFL>
|
||||||
|
<tvExp>1</tvExp>
|
||||||
|
<tvExpOptDlg>0</tvExpOptDlg>
|
||||||
|
<IsCurrentTarget>1</IsCurrentTarget>
|
||||||
|
</OPTFL>
|
||||||
|
<CpuCode>255</CpuCode>
|
||||||
|
<DebugOpt>
|
||||||
|
<uSim>0</uSim>
|
||||||
|
<uTrg>1</uTrg>
|
||||||
|
<sLdApp>1</sLdApp>
|
||||||
|
<sGomain>1</sGomain>
|
||||||
|
<sRbreak>1</sRbreak>
|
||||||
|
<sRwatch>1</sRwatch>
|
||||||
|
<sRmem>1</sRmem>
|
||||||
|
<sRfunc>1</sRfunc>
|
||||||
|
<sRbox>1</sRbox>
|
||||||
|
<tLdApp>1</tLdApp>
|
||||||
|
<tGomain>1</tGomain>
|
||||||
|
<tRbreak>1</tRbreak>
|
||||||
|
<tRwatch>1</tRwatch>
|
||||||
|
<tRmem>1</tRmem>
|
||||||
|
<tRfunc>0</tRfunc>
|
||||||
|
<tRbox>1</tRbox>
|
||||||
|
<tRtrace>1</tRtrace>
|
||||||
|
<sRSysVw>1</sRSysVw>
|
||||||
|
<tRSysVw>1</tRSysVw>
|
||||||
|
<sRunDeb>0</sRunDeb>
|
||||||
|
<sLrtime>0</sLrtime>
|
||||||
|
<bEvRecOn>1</bEvRecOn>
|
||||||
|
<bSchkAxf>0</bSchkAxf>
|
||||||
|
<bTchkAxf>0</bTchkAxf>
|
||||||
|
<nTsel>3</nTsel>
|
||||||
|
<sDll></sDll>
|
||||||
|
<sDllPa></sDllPa>
|
||||||
|
<sDlgDll></sDlgDll>
|
||||||
|
<sDlgPa></sDlgPa>
|
||||||
|
<sIfile></sIfile>
|
||||||
|
<tDll></tDll>
|
||||||
|
<tDllPa></tDllPa>
|
||||||
|
<tDlgDll></tDlgDll>
|
||||||
|
<tDlgPa></tDlgPa>
|
||||||
|
<tIfile></tIfile>
|
||||||
|
<pMon>BIN\CMSIS_AGDI.dll</pMon>
|
||||||
|
</DebugOpt>
|
||||||
|
<TargetDriverDllRegistry>
|
||||||
|
<SetRegEntry>
|
||||||
|
<Number>0</Number>
|
||||||
|
<Key>UL2CM3</Key>
|
||||||
|
<Name>UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0GD32F4xx_1MB -FL0100000 -FS08000000 -FP0($$Device:GD32F470ZG$Flash\GD32F4xx_1MB.FLM)</Name>
|
||||||
|
</SetRegEntry>
|
||||||
|
<SetRegEntry>
|
||||||
|
<Number>0</Number>
|
||||||
|
<Key>CMSIS_AGDI</Key>
|
||||||
|
<Name>-X"Any" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN1 -FF0GD32F4xx_1MB.FLM -FS08000000 -FL0100000 -FP0($$Device:GD32F470ZG$Flash\GD32F4xx_1MB.FLM)</Name>
|
||||||
|
</SetRegEntry>
|
||||||
|
</TargetDriverDllRegistry>
|
||||||
|
<Breakpoint/>
|
||||||
|
<Tracepoint>
|
||||||
|
<THDelay>0</THDelay>
|
||||||
|
</Tracepoint>
|
||||||
|
<DebugFlag>
|
||||||
|
<trace>0</trace>
|
||||||
|
<periodic>0</periodic>
|
||||||
|
<aLwin>0</aLwin>
|
||||||
|
<aCover>0</aCover>
|
||||||
|
<aSer1>0</aSer1>
|
||||||
|
<aSer2>0</aSer2>
|
||||||
|
<aPa>0</aPa>
|
||||||
|
<viewmode>0</viewmode>
|
||||||
|
<vrSel>0</vrSel>
|
||||||
|
<aSym>0</aSym>
|
||||||
|
<aTbox>0</aTbox>
|
||||||
|
<AscS1>0</AscS1>
|
||||||
|
<AscS2>0</AscS2>
|
||||||
|
<AscS3>0</AscS3>
|
||||||
|
<aSer3>0</aSer3>
|
||||||
|
<eProf>0</eProf>
|
||||||
|
<aLa>0</aLa>
|
||||||
|
<aPa1>0</aPa1>
|
||||||
|
<AscS4>0</AscS4>
|
||||||
|
<aSer4>0</aSer4>
|
||||||
|
<StkLoc>0</StkLoc>
|
||||||
|
<TrcWin>0</TrcWin>
|
||||||
|
<newCpu>0</newCpu>
|
||||||
|
<uProt>0</uProt>
|
||||||
|
</DebugFlag>
|
||||||
|
<LintExecutable></LintExecutable>
|
||||||
|
<LintConfigFile></LintConfigFile>
|
||||||
|
<bLintAuto>0</bLintAuto>
|
||||||
|
<bAutoGenD>0</bAutoGenD>
|
||||||
|
<LntExFlags>0</LntExFlags>
|
||||||
|
<pMisraName></pMisraName>
|
||||||
|
<pszMrule></pszMrule>
|
||||||
|
<pSingCmds></pSingCmds>
|
||||||
|
<pMultCmds></pMultCmds>
|
||||||
|
<pMisraNamep></pMisraNamep>
|
||||||
|
<pszMrulep></pszMrulep>
|
||||||
|
<pSingCmdsp></pSingCmdsp>
|
||||||
|
<pMultCmdsp></pMultCmdsp>
|
||||||
|
</TargetOption>
|
||||||
|
</Target>
|
||||||
|
|
||||||
|
<Group>
|
||||||
|
<GroupName>::CMSIS</GroupName>
|
||||||
|
<tvExp>0</tvExp>
|
||||||
|
<tvExpOptDlg>0</tvExpOptDlg>
|
||||||
|
<cbSel>0</cbSel>
|
||||||
|
<RteFlg>1</RteFlg>
|
||||||
|
</Group>
|
||||||
|
|
||||||
|
</ProjectOpt>
|
||||||
|
|
@ -0,0 +1,628 @@
|
||||||
|
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||||
|
<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_proj.xsd">
|
||||||
|
|
||||||
|
<SchemaVersion>1.1</SchemaVersion>
|
||||||
|
|
||||||
|
<Header>### uVision Project, (C) Keil Software</Header>
|
||||||
|
|
||||||
|
<Targets>
|
||||||
|
<Target>
|
||||||
|
<TargetName>rt-thread</TargetName>
|
||||||
|
<ToolsetNumber>0x4</ToolsetNumber>
|
||||||
|
<ToolsetName>ARM-ADS</ToolsetName>
|
||||||
|
<uAC6>0</uAC6>
|
||||||
|
<TargetOption>
|
||||||
|
<TargetCommonOption>
|
||||||
|
<Device>GD32F450ZK</Device>
|
||||||
|
<Vendor>GigaDevice</Vendor>
|
||||||
|
<Cpu>IRAM(0x20000000-0x20030000) IRAM2(0x10000000-0x10010000) IROM(0x08000000-0x08300000) CLOCK(25000000) CPUTYPE("Cortex-M4") FPU2</Cpu>
|
||||||
|
<FlashUtilSpec></FlashUtilSpec>
|
||||||
|
<StartupFile>"Startup\GD\GD32F4xx\startup_gd32f4xx.s" ("GD32F4xx Startup Code")</StartupFile>
|
||||||
|
<FlashDriverDll>UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC800 -FN1 -FF0GD32F4xx_3MB -FS08000000 -FL0300000)</FlashDriverDll>
|
||||||
|
<DeviceId>0</DeviceId>
|
||||||
|
<RegisterFile>gd32f4xx0.h</RegisterFile>
|
||||||
|
<MemoryEnv></MemoryEnv>
|
||||||
|
<Cmp></Cmp>
|
||||||
|
<Asm></Asm>
|
||||||
|
<Linker></Linker>
|
||||||
|
<OHString></OHString>
|
||||||
|
<InfinionOptionDll></InfinionOptionDll>
|
||||||
|
<SLE66CMisc></SLE66CMisc>
|
||||||
|
<SLE66AMisc></SLE66AMisc>
|
||||||
|
<SLE66LinkerMisc></SLE66LinkerMisc>
|
||||||
|
<SFDFile>SFD\GD\GD32F4xx\GD32F4xx.SFR</SFDFile>
|
||||||
|
<bCustSvd>0</bCustSvd>
|
||||||
|
<UseEnv>0</UseEnv>
|
||||||
|
<BinPath></BinPath>
|
||||||
|
<IncludePath></IncludePath>
|
||||||
|
<LibPath></LibPath>
|
||||||
|
<RegisterFilePath>GD\GD32F4xx\</RegisterFilePath>
|
||||||
|
<DBRegisterFilePath>GD\GD32F4xx\</DBRegisterFilePath>
|
||||||
|
<TargetStatus>
|
||||||
|
<Error>0</Error>
|
||||||
|
<ExitCodeStop>0</ExitCodeStop>
|
||||||
|
<ButtonStop>0</ButtonStop>
|
||||||
|
<NotGenerated>0</NotGenerated>
|
||||||
|
<InvalidFlash>1</InvalidFlash>
|
||||||
|
</TargetStatus>
|
||||||
|
<OutputDirectory>.\output\</OutputDirectory>
|
||||||
|
<OutputName>rtthread</OutputName>
|
||||||
|
<CreateExecutable>1</CreateExecutable>
|
||||||
|
<CreateLib>0</CreateLib>
|
||||||
|
<CreateHexFile>1</CreateHexFile>
|
||||||
|
<DebugInformation>1</DebugInformation>
|
||||||
|
<BrowseInformation>1</BrowseInformation>
|
||||||
|
<ListingPath>.\build\</ListingPath>
|
||||||
|
<HexFormatSelection>1</HexFormatSelection>
|
||||||
|
<Merge32K>0</Merge32K>
|
||||||
|
<CreateBatchFile>0</CreateBatchFile>
|
||||||
|
<BeforeCompile>
|
||||||
|
<RunUserProg1>0</RunUserProg1>
|
||||||
|
<RunUserProg2>0</RunUserProg2>
|
||||||
|
<UserProg1Name></UserProg1Name>
|
||||||
|
<UserProg2Name></UserProg2Name>
|
||||||
|
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||||
|
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||||
|
<nStopU1X>0</nStopU1X>
|
||||||
|
<nStopU2X>0</nStopU2X>
|
||||||
|
</BeforeCompile>
|
||||||
|
<BeforeMake>
|
||||||
|
<RunUserProg1>0</RunUserProg1>
|
||||||
|
<RunUserProg2>0</RunUserProg2>
|
||||||
|
<UserProg1Name></UserProg1Name>
|
||||||
|
<UserProg2Name></UserProg2Name>
|
||||||
|
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||||
|
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||||
|
<nStopB1X>0</nStopB1X>
|
||||||
|
<nStopB2X>0</nStopB2X>
|
||||||
|
</BeforeMake>
|
||||||
|
<AfterMake>
|
||||||
|
<RunUserProg1>0</RunUserProg1>
|
||||||
|
<RunUserProg2>0</RunUserProg2>
|
||||||
|
<UserProg1Name></UserProg1Name>
|
||||||
|
<UserProg2Name></UserProg2Name>
|
||||||
|
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||||
|
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||||
|
<nStopA1X>0</nStopA1X>
|
||||||
|
<nStopA2X>0</nStopA2X>
|
||||||
|
</AfterMake>
|
||||||
|
<SelectedForBatchBuild>0</SelectedForBatchBuild>
|
||||||
|
<SVCSIdString></SVCSIdString>
|
||||||
|
</TargetCommonOption>
|
||||||
|
<CommonProperty>
|
||||||
|
<UseCPPCompiler>0</UseCPPCompiler>
|
||||||
|
<RVCTCodeConst>0</RVCTCodeConst>
|
||||||
|
<RVCTZI>0</RVCTZI>
|
||||||
|
<RVCTOtherData>0</RVCTOtherData>
|
||||||
|
<ModuleSelection>0</ModuleSelection>
|
||||||
|
<IncludeInBuild>1</IncludeInBuild>
|
||||||
|
<AlwaysBuild>0</AlwaysBuild>
|
||||||
|
<GenerateAssemblyFile>0</GenerateAssemblyFile>
|
||||||
|
<AssembleAssemblyFile>0</AssembleAssemblyFile>
|
||||||
|
<PublicsOnly>0</PublicsOnly>
|
||||||
|
<StopOnExitCode>3</StopOnExitCode>
|
||||||
|
<CustomArgument></CustomArgument>
|
||||||
|
<IncludeLibraryModules></IncludeLibraryModules>
|
||||||
|
<ComprImg>1</ComprImg>
|
||||||
|
</CommonProperty>
|
||||||
|
<DllOption>
|
||||||
|
<SimDllName>SARMCM3.DLL</SimDllName>
|
||||||
|
<SimDllArguments> -REMAP</SimDllArguments>
|
||||||
|
<SimDlgDll>DCM.DLL</SimDlgDll>
|
||||||
|
<SimDlgDllArguments>-pCM3</SimDlgDllArguments>
|
||||||
|
<TargetDllName>SARMCM3.DLL</TargetDllName>
|
||||||
|
<TargetDllArguments></TargetDllArguments>
|
||||||
|
<TargetDlgDll>TCM.DLL</TargetDlgDll>
|
||||||
|
<TargetDlgDllArguments>-pCM3</TargetDlgDllArguments>
|
||||||
|
</DllOption>
|
||||||
|
<DebugOption>
|
||||||
|
<OPTHX>
|
||||||
|
<HexSelection>1</HexSelection>
|
||||||
|
<HexRangeLowAddress>0</HexRangeLowAddress>
|
||||||
|
<HexRangeHighAddress>0</HexRangeHighAddress>
|
||||||
|
<HexOffset>0</HexOffset>
|
||||||
|
<Oh166RecLen>16</Oh166RecLen>
|
||||||
|
</OPTHX>
|
||||||
|
<Simulator>
|
||||||
|
<UseSimulator>0</UseSimulator>
|
||||||
|
<LoadApplicationAtStartup>1</LoadApplicationAtStartup>
|
||||||
|
<RunToMain>1</RunToMain>
|
||||||
|
<RestoreBreakpoints>1</RestoreBreakpoints>
|
||||||
|
<RestoreWatchpoints>1</RestoreWatchpoints>
|
||||||
|
<RestoreMemoryDisplay>1</RestoreMemoryDisplay>
|
||||||
|
<RestoreFunctions>1</RestoreFunctions>
|
||||||
|
<RestoreToolbox>1</RestoreToolbox>
|
||||||
|
<LimitSpeedToRealTime>0</LimitSpeedToRealTime>
|
||||||
|
<RestoreSysVw>1</RestoreSysVw>
|
||||||
|
</Simulator>
|
||||||
|
<Target>
|
||||||
|
<UseTarget>1</UseTarget>
|
||||||
|
<LoadApplicationAtStartup>1</LoadApplicationAtStartup>
|
||||||
|
<RunToMain>1</RunToMain>
|
||||||
|
<RestoreBreakpoints>1</RestoreBreakpoints>
|
||||||
|
<RestoreWatchpoints>1</RestoreWatchpoints>
|
||||||
|
<RestoreMemoryDisplay>1</RestoreMemoryDisplay>
|
||||||
|
<RestoreFunctions>0</RestoreFunctions>
|
||||||
|
<RestoreToolbox>1</RestoreToolbox>
|
||||||
|
<RestoreTracepoints>0</RestoreTracepoints>
|
||||||
|
<RestoreSysVw>1</RestoreSysVw>
|
||||||
|
</Target>
|
||||||
|
<RunDebugAfterBuild>0</RunDebugAfterBuild>
|
||||||
|
<TargetSelection>3</TargetSelection>
|
||||||
|
<SimDlls>
|
||||||
|
<CpuDll></CpuDll>
|
||||||
|
<CpuDllArguments></CpuDllArguments>
|
||||||
|
<PeripheralDll></PeripheralDll>
|
||||||
|
<PeripheralDllArguments></PeripheralDllArguments>
|
||||||
|
<InitializationFile></InitializationFile>
|
||||||
|
</SimDlls>
|
||||||
|
<TargetDlls>
|
||||||
|
<CpuDll></CpuDll>
|
||||||
|
<CpuDllArguments></CpuDllArguments>
|
||||||
|
<PeripheralDll></PeripheralDll>
|
||||||
|
<PeripheralDllArguments></PeripheralDllArguments>
|
||||||
|
<InitializationFile></InitializationFile>
|
||||||
|
<Driver>BIN\CMSIS_AGDI.dll</Driver>
|
||||||
|
</TargetDlls>
|
||||||
|
</DebugOption>
|
||||||
|
<Utilities>
|
||||||
|
<Flash1>
|
||||||
|
<UseTargetDll>1</UseTargetDll>
|
||||||
|
<UseExternalTool>0</UseExternalTool>
|
||||||
|
<RunIndependent>0</RunIndependent>
|
||||||
|
<UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
|
||||||
|
<Capability>1</Capability>
|
||||||
|
<DriverSelection>4096</DriverSelection>
|
||||||
|
</Flash1>
|
||||||
|
<bUseTDR>1</bUseTDR>
|
||||||
|
<Flash2>BIN\UL2CM3.DLL</Flash2>
|
||||||
|
<Flash3>"" ()</Flash3>
|
||||||
|
<Flash4></Flash4>
|
||||||
|
<pFcarmOut></pFcarmOut>
|
||||||
|
<pFcarmGrp></pFcarmGrp>
|
||||||
|
<pFcArmRoot></pFcArmRoot>
|
||||||
|
<FcArmLst>0</FcArmLst>
|
||||||
|
</Utilities>
|
||||||
|
<TargetArmAds>
|
||||||
|
<ArmAdsMisc>
|
||||||
|
<GenerateListings>0</GenerateListings>
|
||||||
|
<asHll>1</asHll>
|
||||||
|
<asAsm>1</asAsm>
|
||||||
|
<asMacX>1</asMacX>
|
||||||
|
<asSyms>1</asSyms>
|
||||||
|
<asFals>1</asFals>
|
||||||
|
<asDbgD>1</asDbgD>
|
||||||
|
<asForm>1</asForm>
|
||||||
|
<ldLst>0</ldLst>
|
||||||
|
<ldmm>1</ldmm>
|
||||||
|
<ldXref>1</ldXref>
|
||||||
|
<BigEnd>0</BigEnd>
|
||||||
|
<AdsALst>1</AdsALst>
|
||||||
|
<AdsACrf>1</AdsACrf>
|
||||||
|
<AdsANop>0</AdsANop>
|
||||||
|
<AdsANot>0</AdsANot>
|
||||||
|
<AdsLLst>1</AdsLLst>
|
||||||
|
<AdsLmap>1</AdsLmap>
|
||||||
|
<AdsLcgr>1</AdsLcgr>
|
||||||
|
<AdsLsym>1</AdsLsym>
|
||||||
|
<AdsLszi>1</AdsLszi>
|
||||||
|
<AdsLtoi>1</AdsLtoi>
|
||||||
|
<AdsLsun>1</AdsLsun>
|
||||||
|
<AdsLven>1</AdsLven>
|
||||||
|
<AdsLsxf>1</AdsLsxf>
|
||||||
|
<RvctClst>0</RvctClst>
|
||||||
|
<GenPPlst>0</GenPPlst>
|
||||||
|
<AdsCpuType>"Cortex-M4"</AdsCpuType>
|
||||||
|
<RvctDeviceName></RvctDeviceName>
|
||||||
|
<mOS>0</mOS>
|
||||||
|
<uocRom>0</uocRom>
|
||||||
|
<uocRam>0</uocRam>
|
||||||
|
<hadIROM>1</hadIROM>
|
||||||
|
<hadIRAM>1</hadIRAM>
|
||||||
|
<hadXRAM>0</hadXRAM>
|
||||||
|
<uocXRam>0</uocXRam>
|
||||||
|
<RvdsVP>2</RvdsVP>
|
||||||
|
<hadIRAM2>1</hadIRAM2>
|
||||||
|
<hadIROM2>0</hadIROM2>
|
||||||
|
<StupSel>8</StupSel>
|
||||||
|
<useUlib>1</useUlib>
|
||||||
|
<EndSel>0</EndSel>
|
||||||
|
<uLtcg>0</uLtcg>
|
||||||
|
<nSecure>0</nSecure>
|
||||||
|
<RoSelD>3</RoSelD>
|
||||||
|
<RwSelD>3</RwSelD>
|
||||||
|
<CodeSel>0</CodeSel>
|
||||||
|
<OptFeed>0</OptFeed>
|
||||||
|
<NoZi1>0</NoZi1>
|
||||||
|
<NoZi2>0</NoZi2>
|
||||||
|
<NoZi3>0</NoZi3>
|
||||||
|
<NoZi4>0</NoZi4>
|
||||||
|
<NoZi5>0</NoZi5>
|
||||||
|
<Ro1Chk>0</Ro1Chk>
|
||||||
|
<Ro2Chk>0</Ro2Chk>
|
||||||
|
<Ro3Chk>0</Ro3Chk>
|
||||||
|
<Ir1Chk>1</Ir1Chk>
|
||||||
|
<Ir2Chk>0</Ir2Chk>
|
||||||
|
<Ra1Chk>0</Ra1Chk>
|
||||||
|
<Ra2Chk>0</Ra2Chk>
|
||||||
|
<Ra3Chk>0</Ra3Chk>
|
||||||
|
<Im1Chk>1</Im1Chk>
|
||||||
|
<Im2Chk>0</Im2Chk>
|
||||||
|
<OnChipMemories>
|
||||||
|
<Ocm1>
|
||||||
|
<Type>0</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x0</Size>
|
||||||
|
</Ocm1>
|
||||||
|
<Ocm2>
|
||||||
|
<Type>0</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x0</Size>
|
||||||
|
</Ocm2>
|
||||||
|
<Ocm3>
|
||||||
|
<Type>0</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x0</Size>
|
||||||
|
</Ocm3>
|
||||||
|
<Ocm4>
|
||||||
|
<Type>0</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x0</Size>
|
||||||
|
</Ocm4>
|
||||||
|
<Ocm5>
|
||||||
|
<Type>0</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x0</Size>
|
||||||
|
</Ocm5>
|
||||||
|
<Ocm6>
|
||||||
|
<Type>0</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x0</Size>
|
||||||
|
</Ocm6>
|
||||||
|
<IRAM>
|
||||||
|
<Type>0</Type>
|
||||||
|
<StartAddress>0x20000000</StartAddress>
|
||||||
|
<Size>0x30000</Size>
|
||||||
|
</IRAM>
|
||||||
|
<IROM>
|
||||||
|
<Type>1</Type>
|
||||||
|
<StartAddress>0x8000000</StartAddress>
|
||||||
|
<Size>0x300000</Size>
|
||||||
|
</IROM>
|
||||||
|
<XRAM>
|
||||||
|
<Type>0</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x0</Size>
|
||||||
|
</XRAM>
|
||||||
|
<OCR_RVCT1>
|
||||||
|
<Type>1</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x0</Size>
|
||||||
|
</OCR_RVCT1>
|
||||||
|
<OCR_RVCT2>
|
||||||
|
<Type>1</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x0</Size>
|
||||||
|
</OCR_RVCT2>
|
||||||
|
<OCR_RVCT3>
|
||||||
|
<Type>1</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x0</Size>
|
||||||
|
</OCR_RVCT3>
|
||||||
|
<OCR_RVCT4>
|
||||||
|
<Type>1</Type>
|
||||||
|
<StartAddress>0x8000000</StartAddress>
|
||||||
|
<Size>0x300000</Size>
|
||||||
|
</OCR_RVCT4>
|
||||||
|
<OCR_RVCT5>
|
||||||
|
<Type>1</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x0</Size>
|
||||||
|
</OCR_RVCT5>
|
||||||
|
<OCR_RVCT6>
|
||||||
|
<Type>0</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x0</Size>
|
||||||
|
</OCR_RVCT6>
|
||||||
|
<OCR_RVCT7>
|
||||||
|
<Type>0</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x0</Size>
|
||||||
|
</OCR_RVCT7>
|
||||||
|
<OCR_RVCT8>
|
||||||
|
<Type>0</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x0</Size>
|
||||||
|
</OCR_RVCT8>
|
||||||
|
<OCR_RVCT9>
|
||||||
|
<Type>0</Type>
|
||||||
|
<StartAddress>0x20000000</StartAddress>
|
||||||
|
<Size>0x30000</Size>
|
||||||
|
</OCR_RVCT9>
|
||||||
|
<OCR_RVCT10>
|
||||||
|
<Type>0</Type>
|
||||||
|
<StartAddress>0x10000000</StartAddress>
|
||||||
|
<Size>0x10000</Size>
|
||||||
|
</OCR_RVCT10>
|
||||||
|
</OnChipMemories>
|
||||||
|
<RvctStartVector></RvctStartVector>
|
||||||
|
</ArmAdsMisc>
|
||||||
|
<Cads>
|
||||||
|
<interw>1</interw>
|
||||||
|
<Optim>1</Optim>
|
||||||
|
<oTime>0</oTime>
|
||||||
|
<SplitLS>0</SplitLS>
|
||||||
|
<OneElfS>1</OneElfS>
|
||||||
|
<Strict>0</Strict>
|
||||||
|
<EnumInt>0</EnumInt>
|
||||||
|
<PlainCh>0</PlainCh>
|
||||||
|
<Ropi>0</Ropi>
|
||||||
|
<Rwpi>0</Rwpi>
|
||||||
|
<wLevel>2</wLevel>
|
||||||
|
<uThumb>0</uThumb>
|
||||||
|
<uSurpInc>0</uSurpInc>
|
||||||
|
<uC99>1</uC99>
|
||||||
|
<uGnu>0</uGnu>
|
||||||
|
<useXO>0</useXO>
|
||||||
|
<v6Lang>1</v6Lang>
|
||||||
|
<v6LangP>1</v6LangP>
|
||||||
|
<vShortEn>1</vShortEn>
|
||||||
|
<vShortWch>1</vShortWch>
|
||||||
|
<v6Lto>0</v6Lto>
|
||||||
|
<v6WtE>0</v6WtE>
|
||||||
|
<v6Rtti>0</v6Rtti>
|
||||||
|
<VariousControls>
|
||||||
|
<MiscControls></MiscControls>
|
||||||
|
<Define></Define>
|
||||||
|
<Undefine></Undefine>
|
||||||
|
<IncludePath>..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Include;..\..\..\Library\Firmware\CMSIS\GD\GD32F4xx\Include;..\..\..\Library\Utilities;..\</IncludePath>
|
||||||
|
</VariousControls>
|
||||||
|
</Cads>
|
||||||
|
<Aads>
|
||||||
|
<interw>1</interw>
|
||||||
|
<Ropi>0</Ropi>
|
||||||
|
<Rwpi>0</Rwpi>
|
||||||
|
<thumb>0</thumb>
|
||||||
|
<SplitLS>0</SplitLS>
|
||||||
|
<SwStkChk>0</SwStkChk>
|
||||||
|
<NoWarn>0</NoWarn>
|
||||||
|
<uSurpInc>0</uSurpInc>
|
||||||
|
<useXO>0</useXO>
|
||||||
|
<uClangAs>0</uClangAs>
|
||||||
|
<VariousControls>
|
||||||
|
<MiscControls></MiscControls>
|
||||||
|
<Define></Define>
|
||||||
|
<Undefine></Undefine>
|
||||||
|
<IncludePath></IncludePath>
|
||||||
|
</VariousControls>
|
||||||
|
</Aads>
|
||||||
|
<LDads>
|
||||||
|
<umfTarg>1</umfTarg>
|
||||||
|
<Ropi>0</Ropi>
|
||||||
|
<Rwpi>0</Rwpi>
|
||||||
|
<noStLib>0</noStLib>
|
||||||
|
<RepFail>1</RepFail>
|
||||||
|
<useFile>0</useFile>
|
||||||
|
<TextAddressRange>0x08000000</TextAddressRange>
|
||||||
|
<DataAddressRange>0x20000000</DataAddressRange>
|
||||||
|
<pXoBase></pXoBase>
|
||||||
|
<ScatterFile></ScatterFile>
|
||||||
|
<IncludeLibs></IncludeLibs>
|
||||||
|
<IncludeLibsPath></IncludeLibsPath>
|
||||||
|
<Misc></Misc>
|
||||||
|
<LinkerInputFile></LinkerInputFile>
|
||||||
|
<DisabledWarnings></DisabledWarnings>
|
||||||
|
</LDads>
|
||||||
|
</TargetArmAds>
|
||||||
|
</TargetOption>
|
||||||
|
<Groups>
|
||||||
|
<Group>
|
||||||
|
<GroupName>Application</GroupName>
|
||||||
|
<Files>
|
||||||
|
<File>
|
||||||
|
<FileName>main.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\main.c</FilePath>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<FileName>gd32f4xx_it.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\gd32f4xx_it.c</FilePath>
|
||||||
|
</File>
|
||||||
|
</Files>
|
||||||
|
</Group>
|
||||||
|
<Group>
|
||||||
|
<GroupName>CMSIS</GroupName>
|
||||||
|
<Files>
|
||||||
|
<File>
|
||||||
|
<FileName>system_gd32f4xx.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\Library\Firmware\CMSIS\GD\GD32F4xx\Source\system_gd32f4xx.c</FilePath>
|
||||||
|
</File>
|
||||||
|
</Files>
|
||||||
|
</Group>
|
||||||
|
<Group>
|
||||||
|
<GroupName>GD32F4xx_Peripherals</GroupName>
|
||||||
|
<Files>
|
||||||
|
<File>
|
||||||
|
<FileName>gd32f4xx_adc.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_adc.c</FilePath>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<FileName>gd32f4xx_can.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_can.c</FilePath>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<FileName>gd32f4xx_crc.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_crc.c</FilePath>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<FileName>gd32f4xx_ctc.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_ctc.c</FilePath>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<FileName>gd32f4xx_dac.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_dac.c</FilePath>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<FileName>gd32f4xx_dbg.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_dbg.c</FilePath>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<FileName>gd32f4xx_dci.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_dci.c</FilePath>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<FileName>gd32f4xx_dma.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_dma.c</FilePath>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<FileName>gd32f4xx_enet.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_enet.c</FilePath>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<FileName>gd32f4xx_exmc.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_exmc.c</FilePath>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<FileName>gd32f4xx_exti.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_exti.c</FilePath>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<FileName>gd32f4xx_fmc.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_fmc.c</FilePath>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<FileName>gd32f4xx_fwdgt.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_fwdgt.c</FilePath>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<FileName>gd32f4xx_gpio.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_gpio.c</FilePath>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<FileName>gd32f4xx_i2c.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_i2c.c</FilePath>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<FileName>gd32f4xx_ipa.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_ipa.c</FilePath>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<FileName>gd32f4xx_iref.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_iref.c</FilePath>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<FileName>gd32f4xx_misc.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_misc.c</FilePath>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<FileName>gd32f4xx_pmu.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_pmu.c</FilePath>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<FileName>gd32f4xx_rcu.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_rcu.c</FilePath>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<FileName>gd32f4xx_rtc.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_rtc.c</FilePath>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<FileName>gd32f4xx_sdio.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_sdio.c</FilePath>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<FileName>gd32f4xx_spi.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_spi.c</FilePath>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<FileName>gd32f4xx_syscfg.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_syscfg.c</FilePath>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<FileName>gd32f4xx_timer.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_timer.c</FilePath>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<FileName>gd32f4xx_tli.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_tli.c</FilePath>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<FileName>gd32f4xx_trng.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_trng.c</FilePath>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<FileName>gd32f4xx_usart.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_usart.c</FilePath>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<FileName>gd32f4xx_wwdgt.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_wwdgt.c</FilePath>
|
||||||
|
</File>
|
||||||
|
</Files>
|
||||||
|
</Group>
|
||||||
|
<Group>
|
||||||
|
<GroupName>GD32F4xx_EVAL</GroupName>
|
||||||
|
<Files>
|
||||||
|
<File>
|
||||||
|
<FileName>gd32f450z_eval.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\Library\Utilities\gd32f450z_eval.c</FilePath>
|
||||||
|
</File>
|
||||||
|
</Files>
|
||||||
|
</Group>
|
||||||
|
<Group>
|
||||||
|
<GroupName>Startup</GroupName>
|
||||||
|
<Files>
|
||||||
|
<File>
|
||||||
|
<FileName>startup_gd32f4xx.s</FileName>
|
||||||
|
<FileType>2</FileType>
|
||||||
|
<FilePath>..\..\..\Library\Firmware\CMSIS\GD\GD32F4xx\Source\ARM\startup_gd32f4xx.s</FilePath>
|
||||||
|
</File>
|
||||||
|
</Files>
|
||||||
|
</Group>
|
||||||
|
<Group>
|
||||||
|
<GroupName>Doc</GroupName>
|
||||||
|
<Files>
|
||||||
|
<File>
|
||||||
|
<FileName>readme.txt</FileName>
|
||||||
|
<FileType>5</FileType>
|
||||||
|
<FilePath>..\readme.txt</FilePath>
|
||||||
|
</File>
|
||||||
|
</Files>
|
||||||
|
</Group>
|
||||||
|
</Groups>
|
||||||
|
</Target>
|
||||||
|
</Targets>
|
||||||
|
|
||||||
|
</Project>
|
||||||
|
|
@ -0,0 +1,412 @@
|
||||||
|
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||||
|
<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
|
||||||
|
|
||||||
|
<SchemaVersion>2.1</SchemaVersion>
|
||||||
|
|
||||||
|
<Header>### uVision Project, (C) Keil Software</Header>
|
||||||
|
|
||||||
|
<Targets>
|
||||||
|
<Target>
|
||||||
|
<TargetName>rt-thread</TargetName>
|
||||||
|
<ToolsetNumber>0x4</ToolsetNumber>
|
||||||
|
<ToolsetName>ARM-ADS</ToolsetName>
|
||||||
|
<uAC6>0</uAC6>
|
||||||
|
<TargetOption>
|
||||||
|
<TargetCommonOption>
|
||||||
|
<Device>GD32F470ZG</Device>
|
||||||
|
<Vendor>GigaDevice</Vendor>
|
||||||
|
<PackID>GigaDevice.GD32F4xx_DFP.3.0.0</PackID>
|
||||||
|
<PackURL>http://gd32mcu.com/data/documents/pack/</PackURL>
|
||||||
|
<Cpu>IRAM(0x20000000,0x070000) IRAM2(0x10000000,0x010000) IROM(0x08000000,0x0100000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE</Cpu>
|
||||||
|
<FlashUtilSpec></FlashUtilSpec>
|
||||||
|
<StartupFile></StartupFile>
|
||||||
|
<FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0GD32F4xx_1MB -FS08000000 -FL0100000 -FP0($$Device:GD32F470ZG$Flash\GD32F4xx_1MB.FLM))</FlashDriverDll>
|
||||||
|
<DeviceId>0</DeviceId>
|
||||||
|
<RegisterFile>$$Device:GD32F470ZG$Device\F4XX\Include\gd32f4xx.h</RegisterFile>
|
||||||
|
<MemoryEnv></MemoryEnv>
|
||||||
|
<Cmp></Cmp>
|
||||||
|
<Asm></Asm>
|
||||||
|
<Linker></Linker>
|
||||||
|
<OHString></OHString>
|
||||||
|
<InfinionOptionDll></InfinionOptionDll>
|
||||||
|
<SLE66CMisc></SLE66CMisc>
|
||||||
|
<SLE66AMisc></SLE66AMisc>
|
||||||
|
<SLE66LinkerMisc></SLE66LinkerMisc>
|
||||||
|
<SFDFile>$$Device:GD32F470ZG$SVD\GD32F4xx.svd</SFDFile>
|
||||||
|
<bCustSvd>0</bCustSvd>
|
||||||
|
<UseEnv>0</UseEnv>
|
||||||
|
<BinPath></BinPath>
|
||||||
|
<IncludePath></IncludePath>
|
||||||
|
<LibPath></LibPath>
|
||||||
|
<RegisterFilePath></RegisterFilePath>
|
||||||
|
<DBRegisterFilePath></DBRegisterFilePath>
|
||||||
|
<TargetStatus>
|
||||||
|
<Error>0</Error>
|
||||||
|
<ExitCodeStop>0</ExitCodeStop>
|
||||||
|
<ButtonStop>0</ButtonStop>
|
||||||
|
<NotGenerated>0</NotGenerated>
|
||||||
|
<InvalidFlash>1</InvalidFlash>
|
||||||
|
</TargetStatus>
|
||||||
|
<OutputDirectory>.\build\</OutputDirectory>
|
||||||
|
<OutputName>rtthread</OutputName>
|
||||||
|
<CreateExecutable>1</CreateExecutable>
|
||||||
|
<CreateLib>0</CreateLib>
|
||||||
|
<CreateHexFile>0</CreateHexFile>
|
||||||
|
<DebugInformation>1</DebugInformation>
|
||||||
|
<BrowseInformation>0</BrowseInformation>
|
||||||
|
<ListingPath>.\build\</ListingPath>
|
||||||
|
<HexFormatSelection>1</HexFormatSelection>
|
||||||
|
<Merge32K>0</Merge32K>
|
||||||
|
<CreateBatchFile>0</CreateBatchFile>
|
||||||
|
<BeforeCompile>
|
||||||
|
<RunUserProg1>0</RunUserProg1>
|
||||||
|
<RunUserProg2>0</RunUserProg2>
|
||||||
|
<UserProg1Name></UserProg1Name>
|
||||||
|
<UserProg2Name></UserProg2Name>
|
||||||
|
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||||
|
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||||
|
<nStopU1X>0</nStopU1X>
|
||||||
|
<nStopU2X>0</nStopU2X>
|
||||||
|
</BeforeCompile>
|
||||||
|
<BeforeMake>
|
||||||
|
<RunUserProg1>0</RunUserProg1>
|
||||||
|
<RunUserProg2>0</RunUserProg2>
|
||||||
|
<UserProg1Name></UserProg1Name>
|
||||||
|
<UserProg2Name></UserProg2Name>
|
||||||
|
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||||
|
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||||
|
<nStopB1X>0</nStopB1X>
|
||||||
|
<nStopB2X>0</nStopB2X>
|
||||||
|
</BeforeMake>
|
||||||
|
<AfterMake>
|
||||||
|
<RunUserProg1>1</RunUserProg1>
|
||||||
|
<RunUserProg2>0</RunUserProg2>
|
||||||
|
<UserProg1Name>fromelf --bin !L --output rtthread.bin</UserProg1Name>
|
||||||
|
<UserProg2Name></UserProg2Name>
|
||||||
|
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||||
|
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||||
|
<nStopA1X>0</nStopA1X>
|
||||||
|
<nStopA2X>0</nStopA2X>
|
||||||
|
</AfterMake>
|
||||||
|
<SelectedForBatchBuild>0</SelectedForBatchBuild>
|
||||||
|
<SVCSIdString></SVCSIdString>
|
||||||
|
</TargetCommonOption>
|
||||||
|
<CommonProperty>
|
||||||
|
<UseCPPCompiler>0</UseCPPCompiler>
|
||||||
|
<RVCTCodeConst>0</RVCTCodeConst>
|
||||||
|
<RVCTZI>0</RVCTZI>
|
||||||
|
<RVCTOtherData>0</RVCTOtherData>
|
||||||
|
<ModuleSelection>0</ModuleSelection>
|
||||||
|
<IncludeInBuild>1</IncludeInBuild>
|
||||||
|
<AlwaysBuild>0</AlwaysBuild>
|
||||||
|
<GenerateAssemblyFile>0</GenerateAssemblyFile>
|
||||||
|
<AssembleAssemblyFile>0</AssembleAssemblyFile>
|
||||||
|
<PublicsOnly>0</PublicsOnly>
|
||||||
|
<StopOnExitCode>3</StopOnExitCode>
|
||||||
|
<CustomArgument></CustomArgument>
|
||||||
|
<IncludeLibraryModules></IncludeLibraryModules>
|
||||||
|
<ComprImg>1</ComprImg>
|
||||||
|
</CommonProperty>
|
||||||
|
<DllOption>
|
||||||
|
<SimDllName>SARMCM3.DLL</SimDllName>
|
||||||
|
<SimDllArguments> -REMAP -MPU</SimDllArguments>
|
||||||
|
<SimDlgDll>DCM.DLL</SimDlgDll>
|
||||||
|
<SimDlgDllArguments>-pCM4</SimDlgDllArguments>
|
||||||
|
<TargetDllName>SARMCM3.DLL</TargetDllName>
|
||||||
|
<TargetDllArguments> -MPU</TargetDllArguments>
|
||||||
|
<TargetDlgDll>TCM.DLL</TargetDlgDll>
|
||||||
|
<TargetDlgDllArguments>-pCM4</TargetDlgDllArguments>
|
||||||
|
</DllOption>
|
||||||
|
<DebugOption>
|
||||||
|
<OPTHX>
|
||||||
|
<HexSelection>1</HexSelection>
|
||||||
|
<HexRangeLowAddress>0</HexRangeLowAddress>
|
||||||
|
<HexRangeHighAddress>0</HexRangeHighAddress>
|
||||||
|
<HexOffset>0</HexOffset>
|
||||||
|
<Oh166RecLen>16</Oh166RecLen>
|
||||||
|
</OPTHX>
|
||||||
|
</DebugOption>
|
||||||
|
<Utilities>
|
||||||
|
<Flash1>
|
||||||
|
<UseTargetDll>1</UseTargetDll>
|
||||||
|
<UseExternalTool>0</UseExternalTool>
|
||||||
|
<RunIndependent>0</RunIndependent>
|
||||||
|
<UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
|
||||||
|
<Capability>1</Capability>
|
||||||
|
<DriverSelection>4096</DriverSelection>
|
||||||
|
</Flash1>
|
||||||
|
<bUseTDR>1</bUseTDR>
|
||||||
|
<Flash2>BIN\UL2CM3.DLL</Flash2>
|
||||||
|
<Flash3></Flash3>
|
||||||
|
<Flash4></Flash4>
|
||||||
|
<pFcarmOut></pFcarmOut>
|
||||||
|
<pFcarmGrp></pFcarmGrp>
|
||||||
|
<pFcArmRoot></pFcArmRoot>
|
||||||
|
<FcArmLst>0</FcArmLst>
|
||||||
|
</Utilities>
|
||||||
|
<TargetArmAds>
|
||||||
|
<ArmAdsMisc>
|
||||||
|
<GenerateListings>0</GenerateListings>
|
||||||
|
<asHll>1</asHll>
|
||||||
|
<asAsm>1</asAsm>
|
||||||
|
<asMacX>1</asMacX>
|
||||||
|
<asSyms>1</asSyms>
|
||||||
|
<asFals>1</asFals>
|
||||||
|
<asDbgD>1</asDbgD>
|
||||||
|
<asForm>1</asForm>
|
||||||
|
<ldLst>0</ldLst>
|
||||||
|
<ldmm>1</ldmm>
|
||||||
|
<ldXref>1</ldXref>
|
||||||
|
<BigEnd>0</BigEnd>
|
||||||
|
<AdsALst>1</AdsALst>
|
||||||
|
<AdsACrf>1</AdsACrf>
|
||||||
|
<AdsANop>0</AdsANop>
|
||||||
|
<AdsANot>0</AdsANot>
|
||||||
|
<AdsLLst>1</AdsLLst>
|
||||||
|
<AdsLmap>1</AdsLmap>
|
||||||
|
<AdsLcgr>1</AdsLcgr>
|
||||||
|
<AdsLsym>1</AdsLsym>
|
||||||
|
<AdsLszi>1</AdsLszi>
|
||||||
|
<AdsLtoi>1</AdsLtoi>
|
||||||
|
<AdsLsun>1</AdsLsun>
|
||||||
|
<AdsLven>1</AdsLven>
|
||||||
|
<AdsLsxf>1</AdsLsxf>
|
||||||
|
<RvctClst>0</RvctClst>
|
||||||
|
<GenPPlst>0</GenPPlst>
|
||||||
|
<AdsCpuType>"Cortex-M4"</AdsCpuType>
|
||||||
|
<RvctDeviceName></RvctDeviceName>
|
||||||
|
<mOS>0</mOS>
|
||||||
|
<uocRom>0</uocRom>
|
||||||
|
<uocRam>0</uocRam>
|
||||||
|
<hadIROM>1</hadIROM>
|
||||||
|
<hadIRAM>1</hadIRAM>
|
||||||
|
<hadXRAM>0</hadXRAM>
|
||||||
|
<uocXRam>0</uocXRam>
|
||||||
|
<RvdsVP>2</RvdsVP>
|
||||||
|
<RvdsMve>0</RvdsMve>
|
||||||
|
<RvdsCdeCp>0</RvdsCdeCp>
|
||||||
|
<hadIRAM2>1</hadIRAM2>
|
||||||
|
<hadIROM2>0</hadIROM2>
|
||||||
|
<StupSel>8</StupSel>
|
||||||
|
<useUlib>0</useUlib>
|
||||||
|
<EndSel>0</EndSel>
|
||||||
|
<uLtcg>0</uLtcg>
|
||||||
|
<nSecure>0</nSecure>
|
||||||
|
<RoSelD>3</RoSelD>
|
||||||
|
<RwSelD>4</RwSelD>
|
||||||
|
<CodeSel>0</CodeSel>
|
||||||
|
<OptFeed>0</OptFeed>
|
||||||
|
<NoZi1>0</NoZi1>
|
||||||
|
<NoZi2>0</NoZi2>
|
||||||
|
<NoZi3>0</NoZi3>
|
||||||
|
<NoZi4>0</NoZi4>
|
||||||
|
<NoZi5>0</NoZi5>
|
||||||
|
<Ro1Chk>0</Ro1Chk>
|
||||||
|
<Ro2Chk>0</Ro2Chk>
|
||||||
|
<Ro3Chk>0</Ro3Chk>
|
||||||
|
<Ir1Chk>1</Ir1Chk>
|
||||||
|
<Ir2Chk>0</Ir2Chk>
|
||||||
|
<Ra1Chk>0</Ra1Chk>
|
||||||
|
<Ra2Chk>0</Ra2Chk>
|
||||||
|
<Ra3Chk>0</Ra3Chk>
|
||||||
|
<Im1Chk>1</Im1Chk>
|
||||||
|
<Im2Chk>0</Im2Chk>
|
||||||
|
<OnChipMemories>
|
||||||
|
<Ocm1>
|
||||||
|
<Type>0</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x0</Size>
|
||||||
|
</Ocm1>
|
||||||
|
<Ocm2>
|
||||||
|
<Type>0</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x0</Size>
|
||||||
|
</Ocm2>
|
||||||
|
<Ocm3>
|
||||||
|
<Type>0</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x0</Size>
|
||||||
|
</Ocm3>
|
||||||
|
<Ocm4>
|
||||||
|
<Type>0</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x0</Size>
|
||||||
|
</Ocm4>
|
||||||
|
<Ocm5>
|
||||||
|
<Type>0</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x0</Size>
|
||||||
|
</Ocm5>
|
||||||
|
<Ocm6>
|
||||||
|
<Type>0</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x0</Size>
|
||||||
|
</Ocm6>
|
||||||
|
<IRAM>
|
||||||
|
<Type>0</Type>
|
||||||
|
<StartAddress>0x20000000</StartAddress>
|
||||||
|
<Size>0x70000</Size>
|
||||||
|
</IRAM>
|
||||||
|
<IROM>
|
||||||
|
<Type>1</Type>
|
||||||
|
<StartAddress>0x8000000</StartAddress>
|
||||||
|
<Size>0x100000</Size>
|
||||||
|
</IROM>
|
||||||
|
<XRAM>
|
||||||
|
<Type>0</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x0</Size>
|
||||||
|
</XRAM>
|
||||||
|
<OCR_RVCT1>
|
||||||
|
<Type>1</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x0</Size>
|
||||||
|
</OCR_RVCT1>
|
||||||
|
<OCR_RVCT2>
|
||||||
|
<Type>1</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x0</Size>
|
||||||
|
</OCR_RVCT2>
|
||||||
|
<OCR_RVCT3>
|
||||||
|
<Type>1</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x0</Size>
|
||||||
|
</OCR_RVCT3>
|
||||||
|
<OCR_RVCT4>
|
||||||
|
<Type>1</Type>
|
||||||
|
<StartAddress>0x8000000</StartAddress>
|
||||||
|
<Size>0x100000</Size>
|
||||||
|
</OCR_RVCT4>
|
||||||
|
<OCR_RVCT5>
|
||||||
|
<Type>1</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x0</Size>
|
||||||
|
</OCR_RVCT5>
|
||||||
|
<OCR_RVCT6>
|
||||||
|
<Type>0</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x0</Size>
|
||||||
|
</OCR_RVCT6>
|
||||||
|
<OCR_RVCT7>
|
||||||
|
<Type>0</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x0</Size>
|
||||||
|
</OCR_RVCT7>
|
||||||
|
<OCR_RVCT8>
|
||||||
|
<Type>0</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x0</Size>
|
||||||
|
</OCR_RVCT8>
|
||||||
|
<OCR_RVCT9>
|
||||||
|
<Type>0</Type>
|
||||||
|
<StartAddress>0x20000000</StartAddress>
|
||||||
|
<Size>0x70000</Size>
|
||||||
|
</OCR_RVCT9>
|
||||||
|
<OCR_RVCT10>
|
||||||
|
<Type>0</Type>
|
||||||
|
<StartAddress>0x10000000</StartAddress>
|
||||||
|
<Size>0x10000</Size>
|
||||||
|
</OCR_RVCT10>
|
||||||
|
</OnChipMemories>
|
||||||
|
<RvctStartVector></RvctStartVector>
|
||||||
|
</ArmAdsMisc>
|
||||||
|
<Cads>
|
||||||
|
<interw>1</interw>
|
||||||
|
<Optim>4</Optim>
|
||||||
|
<oTime>0</oTime>
|
||||||
|
<SplitLS>0</SplitLS>
|
||||||
|
<OneElfS>1</OneElfS>
|
||||||
|
<Strict>0</Strict>
|
||||||
|
<EnumInt>0</EnumInt>
|
||||||
|
<PlainCh>0</PlainCh>
|
||||||
|
<Ropi>0</Ropi>
|
||||||
|
<Rwpi>0</Rwpi>
|
||||||
|
<wLevel>0</wLevel>
|
||||||
|
<uThumb>0</uThumb>
|
||||||
|
<uSurpInc>0</uSurpInc>
|
||||||
|
<uC99>1</uC99>
|
||||||
|
<uGnu>0</uGnu>
|
||||||
|
<useXO>0</useXO>
|
||||||
|
<v6Lang>1</v6Lang>
|
||||||
|
<v6LangP>1</v6LangP>
|
||||||
|
<vShortEn>1</vShortEn>
|
||||||
|
<vShortWch>1</vShortWch>
|
||||||
|
<v6Lto>0</v6Lto>
|
||||||
|
<v6WtE>0</v6WtE>
|
||||||
|
<v6Rtti>0</v6Rtti>
|
||||||
|
<VariousControls>
|
||||||
|
<MiscControls></MiscControls>
|
||||||
|
<Define></Define>
|
||||||
|
<Undefine></Undefine>
|
||||||
|
<IncludePath></IncludePath>
|
||||||
|
</VariousControls>
|
||||||
|
</Cads>
|
||||||
|
<Aads>
|
||||||
|
<interw>1</interw>
|
||||||
|
<Ropi>0</Ropi>
|
||||||
|
<Rwpi>0</Rwpi>
|
||||||
|
<thumb>0</thumb>
|
||||||
|
<SplitLS>0</SplitLS>
|
||||||
|
<SwStkChk>0</SwStkChk>
|
||||||
|
<NoWarn>0</NoWarn>
|
||||||
|
<uSurpInc>0</uSurpInc>
|
||||||
|
<useXO>0</useXO>
|
||||||
|
<ClangAsOpt>4</ClangAsOpt>
|
||||||
|
<VariousControls>
|
||||||
|
<MiscControls></MiscControls>
|
||||||
|
<Define></Define>
|
||||||
|
<Undefine></Undefine>
|
||||||
|
<IncludePath></IncludePath>
|
||||||
|
</VariousControls>
|
||||||
|
</Aads>
|
||||||
|
<LDads>
|
||||||
|
<umfTarg>1</umfTarg>
|
||||||
|
<Ropi>0</Ropi>
|
||||||
|
<Rwpi>0</Rwpi>
|
||||||
|
<noStLib>0</noStLib>
|
||||||
|
<RepFail>1</RepFail>
|
||||||
|
<useFile>0</useFile>
|
||||||
|
<TextAddressRange>0x08000000</TextAddressRange>
|
||||||
|
<DataAddressRange>0x20000000</DataAddressRange>
|
||||||
|
<pXoBase></pXoBase>
|
||||||
|
<ScatterFile>.\gd32_rom.ld</ScatterFile>
|
||||||
|
<IncludeLibs></IncludeLibs>
|
||||||
|
<IncludeLibsPath></IncludeLibsPath>
|
||||||
|
<Misc></Misc>
|
||||||
|
<LinkerInputFile></LinkerInputFile>
|
||||||
|
<DisabledWarnings></DisabledWarnings>
|
||||||
|
</LDads>
|
||||||
|
</TargetArmAds>
|
||||||
|
</TargetOption>
|
||||||
|
<Groups>
|
||||||
|
<Group>
|
||||||
|
<GroupName>::CMSIS</GroupName>
|
||||||
|
</Group>
|
||||||
|
</Groups>
|
||||||
|
</Target>
|
||||||
|
</Targets>
|
||||||
|
|
||||||
|
<RTE>
|
||||||
|
<apis/>
|
||||||
|
<components>
|
||||||
|
<component Cclass="CMSIS" Cgroup="CORE" Cvendor="ARM" Cversion="5.5.0" condition="ARMv6_7_8-M Device">
|
||||||
|
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.8.0"/>
|
||||||
|
<targetInfos>
|
||||||
|
<targetInfo name="rt-thread"/>
|
||||||
|
</targetInfos>
|
||||||
|
</component>
|
||||||
|
</components>
|
||||||
|
<files/>
|
||||||
|
</RTE>
|
||||||
|
|
||||||
|
<LayerInfo>
|
||||||
|
<Layers>
|
||||||
|
<Layer>
|
||||||
|
<LayName><Project Info></LayName>
|
||||||
|
<LayTarg>0</LayTarg>
|
||||||
|
<LayPrjMark>1</LayPrjMark>
|
||||||
|
</Layer>
|
||||||
|
</Layers>
|
||||||
|
</LayerInfo>
|
||||||
|
|
||||||
|
</Project>
|
||||||
|
|
@ -0,0 +1,9 @@
|
||||||
|
# files format check exclude path, please follow the instructions below to modify;
|
||||||
|
# If you need to exclude an entire folder, add the folder path in dir_path;
|
||||||
|
# If you need to exclude a file, add the path to the file in file_path.
|
||||||
|
|
||||||
|
dir_path:
|
||||||
|
- GD32F10x_Firmware_Library
|
||||||
|
- GD32F20x_Firmware_Library
|
||||||
|
- GD32F30x_Firmware_Library
|
||||||
|
- GD32F4xx_Firmware_Library
|
||||||
|
|
@ -42,13 +42,16 @@ OF SUCH DAMAGE.
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
/* define GD32F4xx */
|
/* define GD32F4xx */
|
||||||
#if !defined (GD32F450) && !defined (GD32F405) && !defined (GD32F407)
|
#if !defined (GD32F450) && !defined (GD32F405) && !defined (GD32F407) && !defined (GD32F470) && !defined (GD32F425) && !defined (GD32F427)
|
||||||
/* #define GD32F450 */
|
/* #define GD32F450 */
|
||||||
/* #define GD32F405 */
|
/* #define GD32F405 */
|
||||||
/* #define GD32F407 */
|
/* #define GD32F407 */
|
||||||
|
/* #define GD32F470 */
|
||||||
|
/* #define GD32F425 */
|
||||||
|
/* #define GD32F427 */
|
||||||
#endif /* define GD32F4xx */
|
#endif /* define GD32F4xx */
|
||||||
|
|
||||||
#if !defined (GD32F450) && !defined (GD32F405) && !defined (GD32F407)
|
#if !defined (GD32F450) && !defined (GD32F405) && !defined (GD32F407) && !defined (GD32F470) && !defined (GD32F425) && !defined (GD32F427)
|
||||||
#error "Please select the target GD32F4xx device in gd32f4xx.h file"
|
#error "Please select the target GD32F4xx device in gd32f4xx.h file"
|
||||||
#endif /* undefine GD32F4xx tip */
|
#endif /* undefine GD32F4xx tip */
|
||||||
|
|
||||||
|
|
@ -163,7 +166,7 @@ typedef enum IRQn
|
||||||
TIMER7_Channel_IRQn = 46, /*!< TIMER7 channel capture compare interrupt */
|
TIMER7_Channel_IRQn = 46, /*!< TIMER7 channel capture compare interrupt */
|
||||||
DMA0_Channel7_IRQn = 47, /*!< DMA0 channel7 interrupt */
|
DMA0_Channel7_IRQn = 47, /*!< DMA0 channel7 interrupt */
|
||||||
|
|
||||||
#if defined (GD32F450)
|
#if defined (GD32F450) || defined (GD32F470)
|
||||||
EXMC_IRQn = 48, /*!< EXMC interrupt */
|
EXMC_IRQn = 48, /*!< EXMC interrupt */
|
||||||
SDIO_IRQn = 49, /*!< SDIO interrupt */
|
SDIO_IRQn = 49, /*!< SDIO interrupt */
|
||||||
TIMER4_IRQn = 50, /*!< TIMER4 interrupt */
|
TIMER4_IRQn = 50, /*!< TIMER4 interrupt */
|
||||||
|
|
@ -205,9 +208,9 @@ typedef enum IRQn
|
||||||
TLI_IRQn = 88, /*!< TLI interrupt */
|
TLI_IRQn = 88, /*!< TLI interrupt */
|
||||||
TLI_ER_IRQn = 89, /*!< TLI error interrupt */
|
TLI_ER_IRQn = 89, /*!< TLI error interrupt */
|
||||||
IPA_IRQn = 90, /*!< IPA interrupt */
|
IPA_IRQn = 90, /*!< IPA interrupt */
|
||||||
#endif /* GD32F450 */
|
#endif /* GD32F450 and GD32F470 */
|
||||||
|
|
||||||
#if defined (GD32F405)
|
#if defined (GD32F405) || defined (GD32F425)
|
||||||
SDIO_IRQn = 49, /*!< SDIO interrupt */
|
SDIO_IRQn = 49, /*!< SDIO interrupt */
|
||||||
TIMER4_IRQn = 50, /*!< TIMER4 interrupt */
|
TIMER4_IRQn = 50, /*!< TIMER4 interrupt */
|
||||||
SPI2_IRQn = 51, /*!< SPI2 interrupt */
|
SPI2_IRQn = 51, /*!< SPI2 interrupt */
|
||||||
|
|
@ -238,9 +241,9 @@ typedef enum IRQn
|
||||||
DCI_IRQn = 78, /*!< DCI interrupt */
|
DCI_IRQn = 78, /*!< DCI interrupt */
|
||||||
TRNG_IRQn = 80, /*!< TRNG interrupt */
|
TRNG_IRQn = 80, /*!< TRNG interrupt */
|
||||||
FPU_IRQn = 81, /*!< FPU interrupt */
|
FPU_IRQn = 81, /*!< FPU interrupt */
|
||||||
#endif /* GD32F405 */
|
#endif /* GD32F405 and GD32F425 */
|
||||||
|
|
||||||
#if defined (GD32F407)
|
#if defined (GD32F407) || defined (GD32F427)
|
||||||
EXMC_IRQn = 48, /*!< EXMC interrupt */
|
EXMC_IRQn = 48, /*!< EXMC interrupt */
|
||||||
SDIO_IRQn = 49, /*!< SDIO interrupt */
|
SDIO_IRQn = 49, /*!< SDIO interrupt */
|
||||||
TIMER4_IRQn = 50, /*!< TIMER4 interrupt */
|
TIMER4_IRQn = 50, /*!< TIMER4 interrupt */
|
||||||
|
|
@ -274,7 +277,7 @@ typedef enum IRQn
|
||||||
DCI_IRQn = 78, /*!< DCI interrupt */
|
DCI_IRQn = 78, /*!< DCI interrupt */
|
||||||
TRNG_IRQn = 80, /*!< TRNG interrupt */
|
TRNG_IRQn = 80, /*!< TRNG interrupt */
|
||||||
FPU_IRQn = 81, /*!< FPU interrupt */
|
FPU_IRQn = 81, /*!< FPU interrupt */
|
||||||
#endif /* GD32F407 */
|
#endif /* GD32F407 and GD32F427 */
|
||||||
|
|
||||||
} IRQn_Type;
|
} IRQn_Type;
|
||||||
|
|
||||||
|
|
@ -285,7 +288,6 @@ typedef enum IRQn
|
||||||
|
|
||||||
/* enum definitions */
|
/* enum definitions */
|
||||||
typedef enum {DISABLE = 0, ENABLE = !DISABLE} EventStatus, ControlStatus;
|
typedef enum {DISABLE = 0, ENABLE = !DISABLE} EventStatus, ControlStatus;
|
||||||
typedef enum {FALSE = 0, TRUE = !FALSE} bool;
|
|
||||||
typedef enum {RESET = 0, SET = !RESET} FlagStatus;
|
typedef enum {RESET = 0, SET = !RESET} FlagStatus;
|
||||||
typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrStatus;
|
typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrStatus;
|
||||||
|
|
||||||
|
|
@ -360,7 +362,7 @@ typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrStatus;
|
||||||
#include "gd32f4xx_libopt.h"
|
#include "gd32f4xx_libopt.h"
|
||||||
#endif /* USE_STDPERIPH_DRIVER */
|
#endif /* USE_STDPERIPH_DRIVER */
|
||||||
|
|
||||||
#ifdef cplusplus
|
#ifdef __cplusplus
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
#endif
|
#endif
|
||||||
|
|
|
||||||
|
|
@ -0,0 +1,423 @@
|
||||||
|
;/*!
|
||||||
|
; \file startup_gd32f405_425.s
|
||||||
|
; \brief start up file
|
||||||
|
;
|
||||||
|
; \version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
||||||
|
; \version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
||||||
|
; \version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
||||||
|
; \version 2022-03-09, V3.0.0, firmware for GD32F4xx
|
||||||
|
;*/
|
||||||
|
;
|
||||||
|
;/*
|
||||||
|
; Copyright (c) 2022, GigaDevice Semiconductor Inc.
|
||||||
|
;
|
||||||
|
; Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
;are permitted provided that the following conditions are met:
|
||||||
|
;
|
||||||
|
; 1. Redistributions of source code must retain the above copyright notice, this
|
||||||
|
; list of conditions and the following disclaimer.
|
||||||
|
; 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
; this list of conditions and the following disclaimer in the documentation
|
||||||
|
; and/or other materials provided with the distribution.
|
||||||
|
; 3. Neither the name of the copyright holder nor the names of its contributors
|
||||||
|
; may be used to endorse or promote products derived from this software without
|
||||||
|
; specific prior written permission.
|
||||||
|
;
|
||||||
|
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
;AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||||
|
;WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||||
|
;IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||||
|
;INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||||
|
;NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||||
|
;PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||||
|
;WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||||
|
;ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||||
|
;OF SUCH DAMAGE.
|
||||||
|
;*/
|
||||||
|
|
||||||
|
; <h> Stack Configuration
|
||||||
|
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||||
|
; </h>
|
||||||
|
|
||||||
|
Stack_Size EQU 0x00000400
|
||||||
|
|
||||||
|
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
||||||
|
Stack_Mem SPACE Stack_Size
|
||||||
|
__initial_sp
|
||||||
|
|
||||||
|
|
||||||
|
; <h> Heap Configuration
|
||||||
|
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||||
|
; </h>
|
||||||
|
|
||||||
|
Heap_Size EQU 0x00000400
|
||||||
|
|
||||||
|
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||||
|
__heap_base
|
||||||
|
Heap_Mem SPACE Heap_Size
|
||||||
|
__heap_limit
|
||||||
|
|
||||||
|
PRESERVE8
|
||||||
|
THUMB
|
||||||
|
|
||||||
|
; /* reset Vector Mapped to at Address 0 */
|
||||||
|
AREA RESET, DATA, READONLY
|
||||||
|
EXPORT __Vectors
|
||||||
|
EXPORT __Vectors_End
|
||||||
|
EXPORT __Vectors_Size
|
||||||
|
|
||||||
|
__Vectors DCD __initial_sp ; Top of Stack
|
||||||
|
DCD Reset_Handler ; Reset Handler
|
||||||
|
DCD NMI_Handler ; NMI Handler
|
||||||
|
DCD HardFault_Handler ; Hard Fault Handler
|
||||||
|
DCD MemManage_Handler ; MPU Fault Handler
|
||||||
|
DCD BusFault_Handler ; Bus Fault Handler
|
||||||
|
DCD UsageFault_Handler ; Usage Fault Handler
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD SVC_Handler ; SVCall Handler
|
||||||
|
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD PendSV_Handler ; PendSV Handler
|
||||||
|
DCD SysTick_Handler ; SysTick Handler
|
||||||
|
|
||||||
|
; /* external interrupts handler */
|
||||||
|
DCD WWDGT_IRQHandler ; 16:Window Watchdog Timer
|
||||||
|
DCD LVD_IRQHandler ; 17:LVD through EXTI Line detect
|
||||||
|
DCD TAMPER_STAMP_IRQHandler ; 18:Tamper and TimeStamp through EXTI Line detect
|
||||||
|
DCD RTC_WKUP_IRQHandler ; 19:RTC Wakeup through EXTI Line
|
||||||
|
DCD FMC_IRQHandler ; 20:FMC
|
||||||
|
DCD RCU_CTC_IRQHandler ; 21:RCU and CTC
|
||||||
|
DCD EXTI0_IRQHandler ; 22:EXTI Line 0
|
||||||
|
DCD EXTI1_IRQHandler ; 23:EXTI Line 1
|
||||||
|
DCD EXTI2_IRQHandler ; 24:EXTI Line 2
|
||||||
|
DCD EXTI3_IRQHandler ; 25:EXTI Line 3
|
||||||
|
DCD EXTI4_IRQHandler ; 26:EXTI Line 4
|
||||||
|
DCD DMA0_Channel0_IRQHandler ; 27:DMA0 Channel0
|
||||||
|
DCD DMA0_Channel1_IRQHandler ; 28:DMA0 Channel1
|
||||||
|
DCD DMA0_Channel2_IRQHandler ; 29:DMA0 Channel2
|
||||||
|
DCD DMA0_Channel3_IRQHandler ; 30:DMA0 Channel3
|
||||||
|
DCD DMA0_Channel4_IRQHandler ; 31:DMA0 Channel4
|
||||||
|
DCD DMA0_Channel5_IRQHandler ; 32:DMA0 Channel5
|
||||||
|
DCD DMA0_Channel6_IRQHandler ; 33:DMA0 Channel6
|
||||||
|
DCD ADC_IRQHandler ; 34:ADC
|
||||||
|
DCD CAN0_TX_IRQHandler ; 35:CAN0 TX
|
||||||
|
DCD CAN0_RX0_IRQHandler ; 36:CAN0 RX0
|
||||||
|
DCD CAN0_RX1_IRQHandler ; 37:CAN0 RX1
|
||||||
|
DCD CAN0_EWMC_IRQHandler ; 38:CAN0 EWMC
|
||||||
|
DCD EXTI5_9_IRQHandler ; 39:EXTI5 to EXTI9
|
||||||
|
DCD TIMER0_BRK_TIMER8_IRQHandler ; 40:TIMER0 Break and TIMER8
|
||||||
|
DCD TIMER0_UP_TIMER9_IRQHandler ; 41:TIMER0 Update and TIMER9
|
||||||
|
DCD TIMER0_TRG_CMT_TIMER10_IRQHandler ; 42:TIMER0 Trigger and Commutation and TIMER10
|
||||||
|
DCD TIMER0_Channel_IRQHandler ; 43:TIMER0 Channel Capture Compare
|
||||||
|
DCD TIMER1_IRQHandler ; 44:TIMER1
|
||||||
|
DCD TIMER2_IRQHandler ; 45:TIMER2
|
||||||
|
DCD TIMER3_IRQHandler ; 46:TIMER3
|
||||||
|
DCD I2C0_EV_IRQHandler ; 47:I2C0 Event
|
||||||
|
DCD I2C0_ER_IRQHandler ; 48:I2C0 Error
|
||||||
|
DCD I2C1_EV_IRQHandler ; 49:I2C1 Event
|
||||||
|
DCD I2C1_ER_IRQHandler ; 50:I2C1 Error
|
||||||
|
DCD SPI0_IRQHandler ; 51:SPI0
|
||||||
|
DCD SPI1_IRQHandler ; 52:SPI1
|
||||||
|
DCD USART0_IRQHandler ; 53:USART0
|
||||||
|
DCD USART1_IRQHandler ; 54:USART1
|
||||||
|
DCD USART2_IRQHandler ; 55:USART2
|
||||||
|
DCD EXTI10_15_IRQHandler ; 56:EXTI10 to EXTI15
|
||||||
|
DCD RTC_Alarm_IRQHandler ; 57:RTC Alarm
|
||||||
|
DCD USBFS_WKUP_IRQHandler ; 58:USBFS Wakeup
|
||||||
|
DCD TIMER7_BRK_TIMER11_IRQHandler ; 59:TIMER7 Break and TIMER11
|
||||||
|
DCD TIMER7_UP_TIMER12_IRQHandler ; 60:TIMER7 Update and TIMER12
|
||||||
|
DCD TIMER7_TRG_CMT_TIMER13_IRQHandler ; 61:TIMER7 Trigger and Commutation and TIMER13
|
||||||
|
DCD TIMER7_Channel_IRQHandler ; 62:TIMER7 Channel Capture Compare
|
||||||
|
DCD DMA0_Channel7_IRQHandler ; 63:DMA0 Channel7
|
||||||
|
DCD 0 ; 64:Reserved
|
||||||
|
DCD SDIO_IRQHandler ; 65:SDIO
|
||||||
|
DCD TIMER4_IRQHandler ; 66:TIMER4
|
||||||
|
DCD SPI2_IRQHandler ; 67:SPI2
|
||||||
|
DCD UART3_IRQHandler ; 68:UART3
|
||||||
|
DCD UART4_IRQHandler ; 69:UART4
|
||||||
|
DCD TIMER5_DAC_IRQHandler ; 70:TIMER5 and DAC0 DAC1 Underrun error
|
||||||
|
DCD TIMER6_IRQHandler ; 71:TIMER6
|
||||||
|
DCD DMA1_Channel0_IRQHandler ; 72:DMA1 Channel0
|
||||||
|
DCD DMA1_Channel1_IRQHandler ; 73:DMA1 Channel1
|
||||||
|
DCD DMA1_Channel2_IRQHandler ; 74:DMA1 Channel2
|
||||||
|
DCD DMA1_Channel3_IRQHandler ; 75:DMA1 Channel3
|
||||||
|
DCD DMA1_Channel4_IRQHandler ; 76:DMA1 Channel4
|
||||||
|
DCD 0 ; 77:Reserved
|
||||||
|
DCD 0 ; 78:Reserved
|
||||||
|
DCD CAN1_TX_IRQHandler ; 79:CAN1 TX
|
||||||
|
DCD CAN1_RX0_IRQHandler ; 80:CAN1 RX0
|
||||||
|
DCD CAN1_RX1_IRQHandler ; 81:CAN1 RX1
|
||||||
|
DCD CAN1_EWMC_IRQHandler ; 82:CAN1 EWMC
|
||||||
|
DCD USBFS_IRQHandler ; 83:USBFS
|
||||||
|
DCD DMA1_Channel5_IRQHandler ; 84:DMA1 Channel5
|
||||||
|
DCD DMA1_Channel6_IRQHandler ; 85:DMA1 Channel6
|
||||||
|
DCD DMA1_Channel7_IRQHandler ; 86:DMA1 Channel7
|
||||||
|
DCD USART5_IRQHandler ; 87:USART5
|
||||||
|
DCD I2C2_EV_IRQHandler ; 88:I2C2 Event
|
||||||
|
DCD I2C2_ER_IRQHandler ; 89:I2C2 Error
|
||||||
|
DCD USBHS_EP1_Out_IRQHandler ; 90:USBHS Endpoint 1 Out
|
||||||
|
DCD USBHS_EP1_In_IRQHandler ; 91:USBHS Endpoint 1 in
|
||||||
|
DCD USBHS_WKUP_IRQHandler ; 92:USBHS Wakeup through EXTI Line
|
||||||
|
DCD USBHS_IRQHandler ; 93:USBHS
|
||||||
|
DCD DCI_IRQHandler ; 94:DCI
|
||||||
|
DCD 0 ; 95:Reserved
|
||||||
|
DCD TRNG_IRQHandler ; 96:TRNG
|
||||||
|
DCD FPU_IRQHandler ; 97:FPU
|
||||||
|
|
||||||
|
__Vectors_End
|
||||||
|
|
||||||
|
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||||
|
|
||||||
|
AREA |.text|, CODE, READONLY
|
||||||
|
|
||||||
|
;/* reset Handler */
|
||||||
|
Reset_Handler PROC
|
||||||
|
EXPORT Reset_Handler [WEAK]
|
||||||
|
IMPORT SystemInit
|
||||||
|
IMPORT __main
|
||||||
|
LDR R0, =SystemInit
|
||||||
|
BLX R0
|
||||||
|
LDR R0, =__main
|
||||||
|
BX R0
|
||||||
|
ENDP
|
||||||
|
|
||||||
|
;/* dummy Exception Handlers */
|
||||||
|
NMI_Handler PROC
|
||||||
|
EXPORT NMI_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
HardFault_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT HardFault_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
MemManage_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT MemManage_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
BusFault_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT BusFault_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
UsageFault_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT UsageFault_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
SVC_Handler PROC
|
||||||
|
EXPORT SVC_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
DebugMon_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT DebugMon_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
PendSV_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT PendSV_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
SysTick_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT SysTick_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
|
||||||
|
Default_Handler PROC
|
||||||
|
; /* external interrupts handler */
|
||||||
|
EXPORT WWDGT_IRQHandler [WEAK]
|
||||||
|
EXPORT LVD_IRQHandler [WEAK]
|
||||||
|
EXPORT TAMPER_STAMP_IRQHandler [WEAK]
|
||||||
|
EXPORT RTC_WKUP_IRQHandler [WEAK]
|
||||||
|
EXPORT FMC_IRQHandler [WEAK]
|
||||||
|
EXPORT RCU_CTC_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI0_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI1_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI2_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI3_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI4_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA0_Channel0_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA0_Channel1_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA0_Channel2_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA0_Channel3_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA0_Channel4_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA0_Channel5_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA0_Channel6_IRQHandler [WEAK]
|
||||||
|
EXPORT ADC_IRQHandler [WEAK]
|
||||||
|
EXPORT CAN0_TX_IRQHandler [WEAK]
|
||||||
|
EXPORT CAN0_RX0_IRQHandler [WEAK]
|
||||||
|
EXPORT CAN0_RX1_IRQHandler [WEAK]
|
||||||
|
EXPORT CAN0_EWMC_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI5_9_IRQHandler [WEAK]
|
||||||
|
EXPORT TIMER0_BRK_TIMER8_IRQHandler [WEAK]
|
||||||
|
EXPORT TIMER0_UP_TIMER9_IRQHandler [WEAK]
|
||||||
|
EXPORT TIMER0_TRG_CMT_TIMER10_IRQHandler [WEAK]
|
||||||
|
EXPORT TIMER0_Channel_IRQHandler [WEAK]
|
||||||
|
EXPORT TIMER1_IRQHandler [WEAK]
|
||||||
|
EXPORT TIMER2_IRQHandler [WEAK]
|
||||||
|
EXPORT TIMER3_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C0_EV_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C0_ER_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C1_EV_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C1_ER_IRQHandler [WEAK]
|
||||||
|
EXPORT SPI0_IRQHandler [WEAK]
|
||||||
|
EXPORT SPI1_IRQHandler [WEAK]
|
||||||
|
EXPORT USART0_IRQHandler [WEAK]
|
||||||
|
EXPORT USART1_IRQHandler [WEAK]
|
||||||
|
EXPORT USART2_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI10_15_IRQHandler [WEAK]
|
||||||
|
EXPORT RTC_Alarm_IRQHandler [WEAK]
|
||||||
|
EXPORT USBFS_WKUP_IRQHandler [WEAK]
|
||||||
|
EXPORT TIMER7_BRK_TIMER11_IRQHandler [WEAK]
|
||||||
|
EXPORT TIMER7_UP_TIMER12_IRQHandler [WEAK]
|
||||||
|
EXPORT TIMER7_TRG_CMT_TIMER13_IRQHandler [WEAK]
|
||||||
|
EXPORT TIMER7_Channel_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA0_Channel7_IRQHandler [WEAK]
|
||||||
|
EXPORT SDIO_IRQHandler [WEAK]
|
||||||
|
EXPORT TIMER4_IRQHandler [WEAK]
|
||||||
|
EXPORT SPI2_IRQHandler [WEAK]
|
||||||
|
EXPORT UART3_IRQHandler [WEAK]
|
||||||
|
EXPORT UART4_IRQHandler [WEAK]
|
||||||
|
EXPORT TIMER5_DAC_IRQHandler [WEAK]
|
||||||
|
EXPORT TIMER6_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel0_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel1_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel2_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel3_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel4_IRQHandler [WEAK]
|
||||||
|
EXPORT CAN1_TX_IRQHandler [WEAK]
|
||||||
|
EXPORT CAN1_RX0_IRQHandler [WEAK]
|
||||||
|
EXPORT CAN1_RX1_IRQHandler [WEAK]
|
||||||
|
EXPORT CAN1_EWMC_IRQHandler [WEAK]
|
||||||
|
EXPORT USBFS_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel5_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel6_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel7_IRQHandler [WEAK]
|
||||||
|
EXPORT USART5_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C2_EV_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C2_ER_IRQHandler [WEAK]
|
||||||
|
EXPORT USBHS_EP1_Out_IRQHandler [WEAK]
|
||||||
|
EXPORT USBHS_EP1_In_IRQHandler [WEAK]
|
||||||
|
EXPORT USBHS_WKUP_IRQHandler [WEAK]
|
||||||
|
EXPORT USBHS_IRQHandler [WEAK]
|
||||||
|
EXPORT DCI_IRQHandler [WEAK]
|
||||||
|
EXPORT TRNG_IRQHandler [WEAK]
|
||||||
|
EXPORT FPU_IRQHandler [WEAK]
|
||||||
|
|
||||||
|
;/* external interrupts handler */
|
||||||
|
WWDGT_IRQHandler
|
||||||
|
LVD_IRQHandler
|
||||||
|
TAMPER_STAMP_IRQHandler
|
||||||
|
RTC_WKUP_IRQHandler
|
||||||
|
FMC_IRQHandler
|
||||||
|
RCU_CTC_IRQHandler
|
||||||
|
EXTI0_IRQHandler
|
||||||
|
EXTI1_IRQHandler
|
||||||
|
EXTI2_IRQHandler
|
||||||
|
EXTI3_IRQHandler
|
||||||
|
EXTI4_IRQHandler
|
||||||
|
DMA0_Channel0_IRQHandler
|
||||||
|
DMA0_Channel1_IRQHandler
|
||||||
|
DMA0_Channel2_IRQHandler
|
||||||
|
DMA0_Channel3_IRQHandler
|
||||||
|
DMA0_Channel4_IRQHandler
|
||||||
|
DMA0_Channel5_IRQHandler
|
||||||
|
DMA0_Channel6_IRQHandler
|
||||||
|
ADC_IRQHandler
|
||||||
|
CAN0_TX_IRQHandler
|
||||||
|
CAN0_RX0_IRQHandler
|
||||||
|
CAN0_RX1_IRQHandler
|
||||||
|
CAN0_EWMC_IRQHandler
|
||||||
|
EXTI5_9_IRQHandler
|
||||||
|
TIMER0_BRK_TIMER8_IRQHandler
|
||||||
|
TIMER0_UP_TIMER9_IRQHandler
|
||||||
|
TIMER0_TRG_CMT_TIMER10_IRQHandler
|
||||||
|
TIMER0_Channel_IRQHandler
|
||||||
|
TIMER1_IRQHandler
|
||||||
|
TIMER2_IRQHandler
|
||||||
|
TIMER3_IRQHandler
|
||||||
|
I2C0_EV_IRQHandler
|
||||||
|
I2C0_ER_IRQHandler
|
||||||
|
I2C1_EV_IRQHandler
|
||||||
|
I2C1_ER_IRQHandler
|
||||||
|
SPI0_IRQHandler
|
||||||
|
SPI1_IRQHandler
|
||||||
|
USART0_IRQHandler
|
||||||
|
USART1_IRQHandler
|
||||||
|
USART2_IRQHandler
|
||||||
|
EXTI10_15_IRQHandler
|
||||||
|
RTC_Alarm_IRQHandler
|
||||||
|
USBFS_WKUP_IRQHandler
|
||||||
|
TIMER7_BRK_TIMER11_IRQHandler
|
||||||
|
TIMER7_UP_TIMER12_IRQHandler
|
||||||
|
TIMER7_TRG_CMT_TIMER13_IRQHandler
|
||||||
|
TIMER7_Channel_IRQHandler
|
||||||
|
DMA0_Channel7_IRQHandler
|
||||||
|
SDIO_IRQHandler
|
||||||
|
TIMER4_IRQHandler
|
||||||
|
SPI2_IRQHandler
|
||||||
|
UART3_IRQHandler
|
||||||
|
UART4_IRQHandler
|
||||||
|
TIMER5_DAC_IRQHandler
|
||||||
|
TIMER6_IRQHandler
|
||||||
|
DMA1_Channel0_IRQHandler
|
||||||
|
DMA1_Channel1_IRQHandler
|
||||||
|
DMA1_Channel2_IRQHandler
|
||||||
|
DMA1_Channel3_IRQHandler
|
||||||
|
DMA1_Channel4_IRQHandler
|
||||||
|
CAN1_TX_IRQHandler
|
||||||
|
CAN1_RX0_IRQHandler
|
||||||
|
CAN1_RX1_IRQHandler
|
||||||
|
CAN1_EWMC_IRQHandler
|
||||||
|
USBFS_IRQHandler
|
||||||
|
DMA1_Channel5_IRQHandler
|
||||||
|
DMA1_Channel6_IRQHandler
|
||||||
|
DMA1_Channel7_IRQHandler
|
||||||
|
USART5_IRQHandler
|
||||||
|
I2C2_EV_IRQHandler
|
||||||
|
I2C2_ER_IRQHandler
|
||||||
|
USBHS_EP1_Out_IRQHandler
|
||||||
|
USBHS_EP1_In_IRQHandler
|
||||||
|
USBHS_WKUP_IRQHandler
|
||||||
|
USBHS_IRQHandler
|
||||||
|
DCI_IRQHandler
|
||||||
|
TRNG_IRQHandler
|
||||||
|
FPU_IRQHandler
|
||||||
|
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
|
||||||
|
ALIGN
|
||||||
|
|
||||||
|
; user Initial Stack & Heap
|
||||||
|
|
||||||
|
IF :DEF:__MICROLIB
|
||||||
|
|
||||||
|
EXPORT __initial_sp
|
||||||
|
EXPORT __heap_base
|
||||||
|
EXPORT __heap_limit
|
||||||
|
|
||||||
|
ELSE
|
||||||
|
|
||||||
|
IMPORT __use_two_region_memory
|
||||||
|
EXPORT __user_initial_stackheap
|
||||||
|
|
||||||
|
__user_initial_stackheap PROC
|
||||||
|
LDR R0, = Heap_Mem
|
||||||
|
LDR R1, =(Stack_Mem + Stack_Size)
|
||||||
|
LDR R2, = (Heap_Mem + Heap_Size)
|
||||||
|
LDR R3, = Stack_Mem
|
||||||
|
BX LR
|
||||||
|
ENDP
|
||||||
|
|
||||||
|
ALIGN
|
||||||
|
|
||||||
|
ENDIF
|
||||||
|
|
||||||
|
END
|
||||||
|
|
@ -0,0 +1,429 @@
|
||||||
|
;/*!
|
||||||
|
; \file startup_gd32f407_427.s
|
||||||
|
; \brief start up file
|
||||||
|
;
|
||||||
|
; \version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
||||||
|
; \version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
||||||
|
; \version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
||||||
|
; \version 2022-03-09, V3.0.0, firmware for GD32F4xx
|
||||||
|
;*/
|
||||||
|
;
|
||||||
|
;/*
|
||||||
|
; Copyright (c) 2022, GigaDevice Semiconductor Inc.
|
||||||
|
;
|
||||||
|
; Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
;are permitted provided that the following conditions are met:
|
||||||
|
;
|
||||||
|
; 1. Redistributions of source code must retain the above copyright notice, this
|
||||||
|
; list of conditions and the following disclaimer.
|
||||||
|
; 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
; this list of conditions and the following disclaimer in the documentation
|
||||||
|
; and/or other materials provided with the distribution.
|
||||||
|
; 3. Neither the name of the copyright holder nor the names of its contributors
|
||||||
|
; may be used to endorse or promote products derived from this software without
|
||||||
|
; specific prior written permission.
|
||||||
|
;
|
||||||
|
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
;AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||||
|
;WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||||
|
;IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||||
|
;INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||||
|
;NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||||
|
;PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||||
|
;WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||||
|
;ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||||
|
;OF SUCH DAMAGE.
|
||||||
|
;*/
|
||||||
|
|
||||||
|
; <h> Stack Configuration
|
||||||
|
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||||
|
; </h>
|
||||||
|
|
||||||
|
Stack_Size EQU 0x00000400
|
||||||
|
|
||||||
|
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
||||||
|
Stack_Mem SPACE Stack_Size
|
||||||
|
__initial_sp
|
||||||
|
|
||||||
|
|
||||||
|
; <h> Heap Configuration
|
||||||
|
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||||
|
; </h>
|
||||||
|
|
||||||
|
Heap_Size EQU 0x00000400
|
||||||
|
|
||||||
|
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||||
|
__heap_base
|
||||||
|
Heap_Mem SPACE Heap_Size
|
||||||
|
__heap_limit
|
||||||
|
|
||||||
|
PRESERVE8
|
||||||
|
THUMB
|
||||||
|
|
||||||
|
; /* reset Vector Mapped to at Address 0 */
|
||||||
|
AREA RESET, DATA, READONLY
|
||||||
|
EXPORT __Vectors
|
||||||
|
EXPORT __Vectors_End
|
||||||
|
EXPORT __Vectors_Size
|
||||||
|
|
||||||
|
__Vectors DCD __initial_sp ; Top of Stack
|
||||||
|
DCD Reset_Handler ; Reset Handler
|
||||||
|
DCD NMI_Handler ; NMI Handler
|
||||||
|
DCD HardFault_Handler ; Hard Fault Handler
|
||||||
|
DCD MemManage_Handler ; MPU Fault Handler
|
||||||
|
DCD BusFault_Handler ; Bus Fault Handler
|
||||||
|
DCD UsageFault_Handler ; Usage Fault Handler
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD SVC_Handler ; SVCall Handler
|
||||||
|
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD PendSV_Handler ; PendSV Handler
|
||||||
|
DCD SysTick_Handler ; SysTick Handler
|
||||||
|
|
||||||
|
; /* external interrupts handler */
|
||||||
|
DCD WWDGT_IRQHandler ; 16:Window Watchdog Timer
|
||||||
|
DCD LVD_IRQHandler ; 17:LVD through EXTI Line detect
|
||||||
|
DCD TAMPER_STAMP_IRQHandler ; 18:Tamper and TimeStamp through EXTI Line detect
|
||||||
|
DCD RTC_WKUP_IRQHandler ; 19:RTC Wakeup through EXTI Line
|
||||||
|
DCD FMC_IRQHandler ; 20:FMC
|
||||||
|
DCD RCU_CTC_IRQHandler ; 21:RCU and CTC
|
||||||
|
DCD EXTI0_IRQHandler ; 22:EXTI Line 0
|
||||||
|
DCD EXTI1_IRQHandler ; 23:EXTI Line 1
|
||||||
|
DCD EXTI2_IRQHandler ; 24:EXTI Line 2
|
||||||
|
DCD EXTI3_IRQHandler ; 25:EXTI Line 3
|
||||||
|
DCD EXTI4_IRQHandler ; 26:EXTI Line 4
|
||||||
|
DCD DMA0_Channel0_IRQHandler ; 27:DMA0 Channel0
|
||||||
|
DCD DMA0_Channel1_IRQHandler ; 28:DMA0 Channel1
|
||||||
|
DCD DMA0_Channel2_IRQHandler ; 29:DMA0 Channel2
|
||||||
|
DCD DMA0_Channel3_IRQHandler ; 30:DMA0 Channel3
|
||||||
|
DCD DMA0_Channel4_IRQHandler ; 31:DMA0 Channel4
|
||||||
|
DCD DMA0_Channel5_IRQHandler ; 32:DMA0 Channel5
|
||||||
|
DCD DMA0_Channel6_IRQHandler ; 33:DMA0 Channel6
|
||||||
|
DCD ADC_IRQHandler ; 34:ADC
|
||||||
|
DCD CAN0_TX_IRQHandler ; 35:CAN0 TX
|
||||||
|
DCD CAN0_RX0_IRQHandler ; 36:CAN0 RX0
|
||||||
|
DCD CAN0_RX1_IRQHandler ; 37:CAN0 RX1
|
||||||
|
DCD CAN0_EWMC_IRQHandler ; 38:CAN0 EWMC
|
||||||
|
DCD EXTI5_9_IRQHandler ; 39:EXTI5 to EXTI9
|
||||||
|
DCD TIMER0_BRK_TIMER8_IRQHandler ; 40:TIMER0 Break and TIMER8
|
||||||
|
DCD TIMER0_UP_TIMER9_IRQHandler ; 41:TIMER0 Update and TIMER9
|
||||||
|
DCD TIMER0_TRG_CMT_TIMER10_IRQHandler ; 42:TIMER0 Trigger and Commutation and TIMER10
|
||||||
|
DCD TIMER0_Channel_IRQHandler ; 43:TIMER0 Channel Capture Compare
|
||||||
|
DCD TIMER1_IRQHandler ; 44:TIMER1
|
||||||
|
DCD TIMER2_IRQHandler ; 45:TIMER2
|
||||||
|
DCD TIMER3_IRQHandler ; 46:TIMER3
|
||||||
|
DCD I2C0_EV_IRQHandler ; 47:I2C0 Event
|
||||||
|
DCD I2C0_ER_IRQHandler ; 48:I2C0 Error
|
||||||
|
DCD I2C1_EV_IRQHandler ; 49:I2C1 Event
|
||||||
|
DCD I2C1_ER_IRQHandler ; 50:I2C1 Error
|
||||||
|
DCD SPI0_IRQHandler ; 51:SPI0
|
||||||
|
DCD SPI1_IRQHandler ; 52:SPI1
|
||||||
|
DCD USART0_IRQHandler ; 53:USART0
|
||||||
|
DCD USART1_IRQHandler ; 54:USART1
|
||||||
|
DCD USART2_IRQHandler ; 55:USART2
|
||||||
|
DCD EXTI10_15_IRQHandler ; 56:EXTI10 to EXTI15
|
||||||
|
DCD RTC_Alarm_IRQHandler ; 57:RTC Alarm
|
||||||
|
DCD USBFS_WKUP_IRQHandler ; 58:USBFS Wakeup
|
||||||
|
DCD TIMER7_BRK_TIMER11_IRQHandler ; 59:TIMER7 Break and TIMER11
|
||||||
|
DCD TIMER7_UP_TIMER12_IRQHandler ; 60:TIMER7 Update and TIMER12
|
||||||
|
DCD TIMER7_TRG_CMT_TIMER13_IRQHandler ; 61:TIMER7 Trigger and Commutation and TIMER13
|
||||||
|
DCD TIMER7_Channel_IRQHandler ; 62:TIMER7 Capture Compare
|
||||||
|
DCD DMA0_Channel7_IRQHandler ; 63:DMA0 Channel7
|
||||||
|
DCD EXMC_IRQHandler ; 64:EXMC
|
||||||
|
DCD SDIO_IRQHandler ; 65:SDIO
|
||||||
|
DCD TIMER4_IRQHandler ; 66:TIMER4
|
||||||
|
DCD SPI2_IRQHandler ; 67:SPI2
|
||||||
|
DCD UART3_IRQHandler ; 68:UART3
|
||||||
|
DCD UART4_IRQHandler ; 69:UART4
|
||||||
|
DCD TIMER5_DAC_IRQHandler ; 70:TIMER5 and DAC0 DAC1 Underrun error
|
||||||
|
DCD TIMER6_IRQHandler ; 71:TIMER6
|
||||||
|
DCD DMA1_Channel0_IRQHandler ; 72:DMA1 Channel0
|
||||||
|
DCD DMA1_Channel1_IRQHandler ; 73:DMA1 Channel1
|
||||||
|
DCD DMA1_Channel2_IRQHandler ; 74:DMA1 Channel2
|
||||||
|
DCD DMA1_Channel3_IRQHandler ; 75:DMA1 Channel3
|
||||||
|
DCD DMA1_Channel4_IRQHandler ; 76:DMA1 Channel4
|
||||||
|
DCD ENET_IRQHandler ; 77:Ethernet
|
||||||
|
DCD ENET_WKUP_IRQHandler ; 78:Ethernet Wakeup through EXTI Line
|
||||||
|
DCD CAN1_TX_IRQHandler ; 79:CAN1 TX
|
||||||
|
DCD CAN1_RX0_IRQHandler ; 80:CAN1 RX0
|
||||||
|
DCD CAN1_RX1_IRQHandler ; 81:CAN1 RX1
|
||||||
|
DCD CAN1_EWMC_IRQHandler ; 82:CAN1 EWMC
|
||||||
|
DCD USBFS_IRQHandler ; 83:USBFS
|
||||||
|
DCD DMA1_Channel5_IRQHandler ; 84:DMA1 Channel5
|
||||||
|
DCD DMA1_Channel6_IRQHandler ; 85:DMA1 Channel6
|
||||||
|
DCD DMA1_Channel7_IRQHandler ; 86:DMA1 Channel7
|
||||||
|
DCD USART5_IRQHandler ; 87:USART5
|
||||||
|
DCD I2C2_EV_IRQHandler ; 88:I2C2 Event
|
||||||
|
DCD I2C2_ER_IRQHandler ; 89:I2C2 Error
|
||||||
|
DCD USBHS_EP1_Out_IRQHandler ; 90:USBHS Endpoint 1 Out
|
||||||
|
DCD USBHS_EP1_In_IRQHandler ; 91:USBHS Endpoint 1 in
|
||||||
|
DCD USBHS_WKUP_IRQHandler ; 92:USBHS Wakeup through EXTI Line
|
||||||
|
DCD USBHS_IRQHandler ; 93:USBHS
|
||||||
|
DCD DCI_IRQHandler ; 94:DCI
|
||||||
|
DCD 0 ; 95:Reserved
|
||||||
|
DCD TRNG_IRQHandler ; 96:TRNG
|
||||||
|
DCD FPU_IRQHandler ; 97:FPU
|
||||||
|
|
||||||
|
__Vectors_End
|
||||||
|
|
||||||
|
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||||
|
|
||||||
|
AREA |.text|, CODE, READONLY
|
||||||
|
|
||||||
|
;/* reset Handler */
|
||||||
|
Reset_Handler PROC
|
||||||
|
EXPORT Reset_Handler [WEAK]
|
||||||
|
IMPORT SystemInit
|
||||||
|
IMPORT __main
|
||||||
|
LDR R0, =SystemInit
|
||||||
|
BLX R0
|
||||||
|
LDR R0, =__main
|
||||||
|
BX R0
|
||||||
|
ENDP
|
||||||
|
|
||||||
|
;/* dummy Exception Handlers */
|
||||||
|
NMI_Handler PROC
|
||||||
|
EXPORT NMI_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
HardFault_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT HardFault_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
MemManage_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT MemManage_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
BusFault_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT BusFault_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
UsageFault_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT UsageFault_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
SVC_Handler PROC
|
||||||
|
EXPORT SVC_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
DebugMon_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT DebugMon_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
PendSV_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT PendSV_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
SysTick_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT SysTick_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
|
||||||
|
Default_Handler PROC
|
||||||
|
; /* external interrupts handler */
|
||||||
|
EXPORT WWDGT_IRQHandler [WEAK]
|
||||||
|
EXPORT LVD_IRQHandler [WEAK]
|
||||||
|
EXPORT TAMPER_STAMP_IRQHandler [WEAK]
|
||||||
|
EXPORT RTC_WKUP_IRQHandler [WEAK]
|
||||||
|
EXPORT FMC_IRQHandler [WEAK]
|
||||||
|
EXPORT RCU_CTC_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI0_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI1_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI2_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI3_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI4_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA0_Channel0_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA0_Channel1_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA0_Channel2_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA0_Channel3_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA0_Channel4_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA0_Channel5_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA0_Channel6_IRQHandler [WEAK]
|
||||||
|
EXPORT ADC_IRQHandler [WEAK]
|
||||||
|
EXPORT CAN0_TX_IRQHandler [WEAK]
|
||||||
|
EXPORT CAN0_RX0_IRQHandler [WEAK]
|
||||||
|
EXPORT CAN0_RX1_IRQHandler [WEAK]
|
||||||
|
EXPORT CAN0_EWMC_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI5_9_IRQHandler [WEAK]
|
||||||
|
EXPORT TIMER0_BRK_TIMER8_IRQHandler [WEAK]
|
||||||
|
EXPORT TIMER0_UP_TIMER9_IRQHandler [WEAK]
|
||||||
|
EXPORT TIMER0_TRG_CMT_TIMER10_IRQHandler [WEAK]
|
||||||
|
EXPORT TIMER0_Channel_IRQHandler [WEAK]
|
||||||
|
EXPORT TIMER1_IRQHandler [WEAK]
|
||||||
|
EXPORT TIMER2_IRQHandler [WEAK]
|
||||||
|
EXPORT TIMER3_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C0_EV_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C0_ER_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C1_EV_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C1_ER_IRQHandler [WEAK]
|
||||||
|
EXPORT SPI0_IRQHandler [WEAK]
|
||||||
|
EXPORT SPI1_IRQHandler [WEAK]
|
||||||
|
EXPORT USART0_IRQHandler [WEAK]
|
||||||
|
EXPORT USART1_IRQHandler [WEAK]
|
||||||
|
EXPORT USART2_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI10_15_IRQHandler [WEAK]
|
||||||
|
EXPORT RTC_Alarm_IRQHandler [WEAK]
|
||||||
|
EXPORT USBFS_WKUP_IRQHandler [WEAK]
|
||||||
|
EXPORT TIMER7_BRK_TIMER11_IRQHandler [WEAK]
|
||||||
|
EXPORT TIMER7_UP_TIMER12_IRQHandler [WEAK]
|
||||||
|
EXPORT TIMER7_TRG_CMT_TIMER13_IRQHandler [WEAK]
|
||||||
|
EXPORT TIMER7_Channel_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA0_Channel7_IRQHandler [WEAK]
|
||||||
|
EXPORT EXMC_IRQHandler [WEAK]
|
||||||
|
EXPORT SDIO_IRQHandler [WEAK]
|
||||||
|
EXPORT TIMER4_IRQHandler [WEAK]
|
||||||
|
EXPORT SPI2_IRQHandler [WEAK]
|
||||||
|
EXPORT UART3_IRQHandler [WEAK]
|
||||||
|
EXPORT UART4_IRQHandler [WEAK]
|
||||||
|
EXPORT TIMER5_DAC_IRQHandler [WEAK]
|
||||||
|
EXPORT TIMER6_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel0_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel1_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel2_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel3_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel4_IRQHandler [WEAK]
|
||||||
|
EXPORT ENET_IRQHandler [WEAK]
|
||||||
|
EXPORT ENET_WKUP_IRQHandler [WEAK]
|
||||||
|
EXPORT CAN1_TX_IRQHandler [WEAK]
|
||||||
|
EXPORT CAN1_RX0_IRQHandler [WEAK]
|
||||||
|
EXPORT CAN1_RX1_IRQHandler [WEAK]
|
||||||
|
EXPORT CAN1_EWMC_IRQHandler [WEAK]
|
||||||
|
EXPORT USBFS_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel5_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel6_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel7_IRQHandler [WEAK]
|
||||||
|
EXPORT USART5_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C2_EV_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C2_ER_IRQHandler [WEAK]
|
||||||
|
EXPORT USBHS_EP1_Out_IRQHandler [WEAK]
|
||||||
|
EXPORT USBHS_EP1_In_IRQHandler [WEAK]
|
||||||
|
EXPORT USBHS_WKUP_IRQHandler [WEAK]
|
||||||
|
EXPORT USBHS_IRQHandler [WEAK]
|
||||||
|
EXPORT DCI_IRQHandler [WEAK]
|
||||||
|
EXPORT TRNG_IRQHandler [WEAK]
|
||||||
|
EXPORT FPU_IRQHandler [WEAK]
|
||||||
|
|
||||||
|
;/* external interrupts handler */
|
||||||
|
WWDGT_IRQHandler
|
||||||
|
LVD_IRQHandler
|
||||||
|
TAMPER_STAMP_IRQHandler
|
||||||
|
RTC_WKUP_IRQHandler
|
||||||
|
FMC_IRQHandler
|
||||||
|
RCU_CTC_IRQHandler
|
||||||
|
EXTI0_IRQHandler
|
||||||
|
EXTI1_IRQHandler
|
||||||
|
EXTI2_IRQHandler
|
||||||
|
EXTI3_IRQHandler
|
||||||
|
EXTI4_IRQHandler
|
||||||
|
DMA0_Channel0_IRQHandler
|
||||||
|
DMA0_Channel1_IRQHandler
|
||||||
|
DMA0_Channel2_IRQHandler
|
||||||
|
DMA0_Channel3_IRQHandler
|
||||||
|
DMA0_Channel4_IRQHandler
|
||||||
|
DMA0_Channel5_IRQHandler
|
||||||
|
DMA0_Channel6_IRQHandler
|
||||||
|
ADC_IRQHandler
|
||||||
|
CAN0_TX_IRQHandler
|
||||||
|
CAN0_RX0_IRQHandler
|
||||||
|
CAN0_RX1_IRQHandler
|
||||||
|
CAN0_EWMC_IRQHandler
|
||||||
|
EXTI5_9_IRQHandler
|
||||||
|
TIMER0_BRK_TIMER8_IRQHandler
|
||||||
|
TIMER0_UP_TIMER9_IRQHandler
|
||||||
|
TIMER0_TRG_CMT_TIMER10_IRQHandler
|
||||||
|
TIMER0_Channel_IRQHandler
|
||||||
|
TIMER1_IRQHandler
|
||||||
|
TIMER2_IRQHandler
|
||||||
|
TIMER3_IRQHandler
|
||||||
|
I2C0_EV_IRQHandler
|
||||||
|
I2C0_ER_IRQHandler
|
||||||
|
I2C1_EV_IRQHandler
|
||||||
|
I2C1_ER_IRQHandler
|
||||||
|
SPI0_IRQHandler
|
||||||
|
SPI1_IRQHandler
|
||||||
|
USART0_IRQHandler
|
||||||
|
USART1_IRQHandler
|
||||||
|
USART2_IRQHandler
|
||||||
|
EXTI10_15_IRQHandler
|
||||||
|
RTC_Alarm_IRQHandler
|
||||||
|
USBFS_WKUP_IRQHandler
|
||||||
|
TIMER7_BRK_TIMER11_IRQHandler
|
||||||
|
TIMER7_UP_TIMER12_IRQHandler
|
||||||
|
TIMER7_TRG_CMT_TIMER13_IRQHandler
|
||||||
|
TIMER7_Channel_IRQHandler
|
||||||
|
DMA0_Channel7_IRQHandler
|
||||||
|
EXMC_IRQHandler
|
||||||
|
SDIO_IRQHandler
|
||||||
|
TIMER4_IRQHandler
|
||||||
|
SPI2_IRQHandler
|
||||||
|
UART3_IRQHandler
|
||||||
|
UART4_IRQHandler
|
||||||
|
TIMER5_DAC_IRQHandler
|
||||||
|
TIMER6_IRQHandler
|
||||||
|
DMA1_Channel0_IRQHandler
|
||||||
|
DMA1_Channel1_IRQHandler
|
||||||
|
DMA1_Channel2_IRQHandler
|
||||||
|
DMA1_Channel3_IRQHandler
|
||||||
|
DMA1_Channel4_IRQHandler
|
||||||
|
ENET_IRQHandler
|
||||||
|
ENET_WKUP_IRQHandler
|
||||||
|
CAN1_TX_IRQHandler
|
||||||
|
CAN1_RX0_IRQHandler
|
||||||
|
CAN1_RX1_IRQHandler
|
||||||
|
CAN1_EWMC_IRQHandler
|
||||||
|
USBFS_IRQHandler
|
||||||
|
DMA1_Channel5_IRQHandler
|
||||||
|
DMA1_Channel6_IRQHandler
|
||||||
|
DMA1_Channel7_IRQHandler
|
||||||
|
USART5_IRQHandler
|
||||||
|
I2C2_EV_IRQHandler
|
||||||
|
I2C2_ER_IRQHandler
|
||||||
|
USBHS_EP1_Out_IRQHandler
|
||||||
|
USBHS_EP1_In_IRQHandler
|
||||||
|
USBHS_WKUP_IRQHandler
|
||||||
|
USBHS_IRQHandler
|
||||||
|
DCI_IRQHandler
|
||||||
|
TRNG_IRQHandler
|
||||||
|
FPU_IRQHandler
|
||||||
|
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
|
||||||
|
ALIGN
|
||||||
|
|
||||||
|
; user Initial Stack & Heap
|
||||||
|
|
||||||
|
IF :DEF:__MICROLIB
|
||||||
|
|
||||||
|
EXPORT __initial_sp
|
||||||
|
EXPORT __heap_base
|
||||||
|
EXPORT __heap_limit
|
||||||
|
|
||||||
|
ELSE
|
||||||
|
|
||||||
|
IMPORT __use_two_region_memory
|
||||||
|
EXPORT __user_initial_stackheap
|
||||||
|
|
||||||
|
__user_initial_stackheap PROC
|
||||||
|
LDR R0, = Heap_Mem
|
||||||
|
LDR R1, =(Stack_Mem + Stack_Size)
|
||||||
|
LDR R2, = (Heap_Mem + Heap_Size)
|
||||||
|
LDR R3, = Stack_Mem
|
||||||
|
BX LR
|
||||||
|
ENDP
|
||||||
|
|
||||||
|
ALIGN
|
||||||
|
|
||||||
|
ENDIF
|
||||||
|
|
||||||
|
END
|
||||||
|
|
@ -0,0 +1,454 @@
|
||||||
|
;/*!
|
||||||
|
; \file startup_gd32f450_470.s
|
||||||
|
; \brief start up file
|
||||||
|
;
|
||||||
|
; \version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
||||||
|
; \version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
||||||
|
; \version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
||||||
|
; \version 2022-03-09, V3.0.0, firmware for GD32F4xx
|
||||||
|
;*/
|
||||||
|
;
|
||||||
|
;/*
|
||||||
|
; Copyright (c) 2022, GigaDevice Semiconductor Inc.
|
||||||
|
;
|
||||||
|
; Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
;are permitted provided that the following conditions are met:
|
||||||
|
;
|
||||||
|
; 1. Redistributions of source code must retain the above copyright notice, this
|
||||||
|
; list of conditions and the following disclaimer.
|
||||||
|
; 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
; this list of conditions and the following disclaimer in the documentation
|
||||||
|
; and/or other materials provided with the distribution.
|
||||||
|
; 3. Neither the name of the copyright holder nor the names of its contributors
|
||||||
|
; may be used to endorse or promote products derived from this software without
|
||||||
|
; specific prior written permission.
|
||||||
|
;
|
||||||
|
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
;AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||||
|
;WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||||
|
;IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||||
|
;INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||||
|
;NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||||
|
;PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||||
|
;WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||||
|
;ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||||
|
;OF SUCH DAMAGE.
|
||||||
|
;*/
|
||||||
|
|
||||||
|
; <h> Stack Configuration
|
||||||
|
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||||
|
; </h>
|
||||||
|
|
||||||
|
Stack_Size EQU 0x00000400
|
||||||
|
|
||||||
|
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
||||||
|
Stack_Mem SPACE Stack_Size
|
||||||
|
__initial_sp
|
||||||
|
|
||||||
|
|
||||||
|
; <h> Heap Configuration
|
||||||
|
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||||
|
; </h>
|
||||||
|
|
||||||
|
Heap_Size EQU 0x00000400
|
||||||
|
|
||||||
|
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||||
|
__heap_base
|
||||||
|
Heap_Mem SPACE Heap_Size
|
||||||
|
__heap_limit
|
||||||
|
|
||||||
|
PRESERVE8
|
||||||
|
THUMB
|
||||||
|
|
||||||
|
; /* reset Vector Mapped to at Address 0 */
|
||||||
|
AREA RESET, DATA, READONLY
|
||||||
|
EXPORT __Vectors
|
||||||
|
EXPORT __Vectors_End
|
||||||
|
EXPORT __Vectors_Size
|
||||||
|
|
||||||
|
__Vectors DCD __initial_sp ; Top of Stack
|
||||||
|
DCD Reset_Handler ; Reset Handler
|
||||||
|
DCD NMI_Handler ; NMI Handler
|
||||||
|
DCD HardFault_Handler ; Hard Fault Handler
|
||||||
|
DCD MemManage_Handler ; MPU Fault Handler
|
||||||
|
DCD BusFault_Handler ; Bus Fault Handler
|
||||||
|
DCD UsageFault_Handler ; Usage Fault Handler
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD SVC_Handler ; SVCall Handler
|
||||||
|
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD PendSV_Handler ; PendSV Handler
|
||||||
|
DCD SysTick_Handler ; SysTick Handler
|
||||||
|
|
||||||
|
; /* external interrupts handler */
|
||||||
|
DCD WWDGT_IRQHandler ; 16:Window Watchdog Timer
|
||||||
|
DCD LVD_IRQHandler ; 17:LVD through EXTI Line detect
|
||||||
|
DCD TAMPER_STAMP_IRQHandler ; 18:Tamper and TimeStamp through EXTI Line detect
|
||||||
|
DCD RTC_WKUP_IRQHandler ; 19:RTC Wakeup through EXTI Line
|
||||||
|
DCD FMC_IRQHandler ; 20:FMC
|
||||||
|
DCD RCU_CTC_IRQHandler ; 21:RCU and CTC
|
||||||
|
DCD EXTI0_IRQHandler ; 22:EXTI Line 0
|
||||||
|
DCD EXTI1_IRQHandler ; 23:EXTI Line 1
|
||||||
|
DCD EXTI2_IRQHandler ; 24:EXTI Line 2
|
||||||
|
DCD EXTI3_IRQHandler ; 25:EXTI Line 3
|
||||||
|
DCD EXTI4_IRQHandler ; 26:EXTI Line 4
|
||||||
|
DCD DMA0_Channel0_IRQHandler ; 27:DMA0 Channel0
|
||||||
|
DCD DMA0_Channel1_IRQHandler ; 28:DMA0 Channel1
|
||||||
|
DCD DMA0_Channel2_IRQHandler ; 29:DMA0 Channel2
|
||||||
|
DCD DMA0_Channel3_IRQHandler ; 30:DMA0 Channel3
|
||||||
|
DCD DMA0_Channel4_IRQHandler ; 31:DMA0 Channel4
|
||||||
|
DCD DMA0_Channel5_IRQHandler ; 32:DMA0 Channel5
|
||||||
|
DCD DMA0_Channel6_IRQHandler ; 33:DMA0 Channel6
|
||||||
|
DCD ADC_IRQHandler ; 34:ADC
|
||||||
|
DCD CAN0_TX_IRQHandler ; 35:CAN0 TX
|
||||||
|
DCD CAN0_RX0_IRQHandler ; 36:CAN0 RX0
|
||||||
|
DCD CAN0_RX1_IRQHandler ; 37:CAN0 RX1
|
||||||
|
DCD CAN0_EWMC_IRQHandler ; 38:CAN0 EWMC
|
||||||
|
DCD EXTI5_9_IRQHandler ; 39:EXTI5 to EXTI9
|
||||||
|
DCD TIMER0_BRK_TIMER8_IRQHandler ; 40:TIMER0 Break and TIMER8
|
||||||
|
DCD TIMER0_UP_TIMER9_IRQHandler ; 41:TIMER0 Update and TIMER9
|
||||||
|
DCD TIMER0_TRG_CMT_TIMER10_IRQHandler ; 42:TIMER0 Trigger and Commutation and TIMER10
|
||||||
|
DCD TIMER0_Channel_IRQHandler ; 43:TIMER0 Capture Compare
|
||||||
|
DCD TIMER1_IRQHandler ; 44:TIMER1
|
||||||
|
DCD TIMER2_IRQHandler ; 45:TIMER2
|
||||||
|
DCD TIMER3_IRQHandler ; 46:TIMER3
|
||||||
|
DCD I2C0_EV_IRQHandler ; 47:I2C0 Event
|
||||||
|
DCD I2C0_ER_IRQHandler ; 48:I2C0 Error
|
||||||
|
DCD I2C1_EV_IRQHandler ; 49:I2C1 Event
|
||||||
|
DCD I2C1_ER_IRQHandler ; 50:I2C1 Error
|
||||||
|
DCD SPI0_IRQHandler ; 51:SPI0
|
||||||
|
DCD SPI1_IRQHandler ; 52:SPI1
|
||||||
|
DCD USART0_IRQHandler ; 53:USART0
|
||||||
|
DCD USART1_IRQHandler ; 54:USART1
|
||||||
|
DCD USART2_IRQHandler ; 55:USART2
|
||||||
|
DCD EXTI10_15_IRQHandler ; 56:EXTI10 to EXTI15
|
||||||
|
DCD RTC_Alarm_IRQHandler ; 57:RTC Alarm
|
||||||
|
DCD USBFS_WKUP_IRQHandler ; 58:USBFS Wakeup
|
||||||
|
DCD TIMER7_BRK_TIMER11_IRQHandler ; 59:TIMER7 Break and TIMER11
|
||||||
|
DCD TIMER7_UP_TIMER12_IRQHandler ; 60:TIMER7 Update and TIMER12
|
||||||
|
DCD TIMER7_TRG_CMT_TIMER13_IRQHandler ; 61:TIMER7 Trigger and Commutation and TIMER13
|
||||||
|
DCD TIMER7_Channel_IRQHandler ; 62:TIMER7 Channel Capture Compare
|
||||||
|
DCD DMA0_Channel7_IRQHandler ; 63:DMA0 Channel7
|
||||||
|
DCD EXMC_IRQHandler ; 64:EXMC
|
||||||
|
DCD SDIO_IRQHandler ; 65:SDIO
|
||||||
|
DCD TIMER4_IRQHandler ; 66:TIMER4
|
||||||
|
DCD SPI2_IRQHandler ; 67:SPI2
|
||||||
|
DCD UART3_IRQHandler ; 68:UART3
|
||||||
|
DCD UART4_IRQHandler ; 69:UART4
|
||||||
|
DCD TIMER5_DAC_IRQHandler ; 70:TIMER5 and DAC0 DAC1 Underrun error
|
||||||
|
DCD TIMER6_IRQHandler ; 71:TIMER6
|
||||||
|
DCD DMA1_Channel0_IRQHandler ; 72:DMA1 Channel0
|
||||||
|
DCD DMA1_Channel1_IRQHandler ; 73:DMA1 Channel1
|
||||||
|
DCD DMA1_Channel2_IRQHandler ; 74:DMA1 Channel2
|
||||||
|
DCD DMA1_Channel3_IRQHandler ; 75:DMA1 Channel3
|
||||||
|
DCD DMA1_Channel4_IRQHandler ; 76:DMA1 Channel4
|
||||||
|
DCD ENET_IRQHandler ; 77:Ethernet
|
||||||
|
DCD ENET_WKUP_IRQHandler ; 78:Ethernet Wakeup through EXTI Line
|
||||||
|
DCD CAN1_TX_IRQHandler ; 79:CAN1 TX
|
||||||
|
DCD CAN1_RX0_IRQHandler ; 80:CAN1 RX0
|
||||||
|
DCD CAN1_RX1_IRQHandler ; 81:CAN1 RX1
|
||||||
|
DCD CAN1_EWMC_IRQHandler ; 82:CAN1 EWMC
|
||||||
|
DCD USBFS_IRQHandler ; 83:USBFS
|
||||||
|
DCD DMA1_Channel5_IRQHandler ; 84:DMA1 Channel5
|
||||||
|
DCD DMA1_Channel6_IRQHandler ; 85:DMA1 Channel6
|
||||||
|
DCD DMA1_Channel7_IRQHandler ; 86:DMA1 Channel7
|
||||||
|
DCD USART5_IRQHandler ; 87:USART5
|
||||||
|
DCD I2C2_EV_IRQHandler ; 88:I2C2 Event
|
||||||
|
DCD I2C2_ER_IRQHandler ; 89:I2C2 Error
|
||||||
|
DCD USBHS_EP1_Out_IRQHandler ; 90:USBHS Endpoint 1 Out
|
||||||
|
DCD USBHS_EP1_In_IRQHandler ; 91:USBHS Endpoint 1 in
|
||||||
|
DCD USBHS_WKUP_IRQHandler ; 92:USBHS Wakeup through EXTI Line
|
||||||
|
DCD USBHS_IRQHandler ; 93:USBHS
|
||||||
|
DCD DCI_IRQHandler ; 94:DCI
|
||||||
|
DCD 0 ; 95:Reserved
|
||||||
|
DCD TRNG_IRQHandler ; 96:TRNG
|
||||||
|
DCD FPU_IRQHandler ; 97:FPU
|
||||||
|
DCD UART6_IRQHandler ; 98:UART6
|
||||||
|
DCD UART7_IRQHandler ; 99:UART7
|
||||||
|
DCD SPI3_IRQHandler ; 100:SPI3
|
||||||
|
DCD SPI4_IRQHandler ; 101:SPI4
|
||||||
|
DCD SPI5_IRQHandler ; 102:SPI5
|
||||||
|
DCD 0 ; 103:Reserved
|
||||||
|
DCD TLI_IRQHandler ; 104:TLI
|
||||||
|
DCD TLI_ER_IRQHandler ; 105:TLI Error
|
||||||
|
DCD IPA_IRQHandler ; 106:IPA
|
||||||
|
|
||||||
|
__Vectors_End
|
||||||
|
|
||||||
|
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||||
|
|
||||||
|
AREA |.text|, CODE, READONLY
|
||||||
|
|
||||||
|
;/* reset Handler */
|
||||||
|
Reset_Handler PROC
|
||||||
|
EXPORT Reset_Handler [WEAK]
|
||||||
|
IMPORT SystemInit
|
||||||
|
IMPORT __main
|
||||||
|
LDR R0, =SystemInit
|
||||||
|
BLX R0
|
||||||
|
LDR R0, =__main
|
||||||
|
BX R0
|
||||||
|
ENDP
|
||||||
|
|
||||||
|
;/* dummy Exception Handlers */
|
||||||
|
NMI_Handler PROC
|
||||||
|
EXPORT NMI_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
HardFault_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT HardFault_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
MemManage_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT MemManage_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
BusFault_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT BusFault_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
UsageFault_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT UsageFault_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
SVC_Handler PROC
|
||||||
|
EXPORT SVC_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
DebugMon_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT DebugMon_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
PendSV_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT PendSV_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
SysTick_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT SysTick_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
|
||||||
|
Default_Handler PROC
|
||||||
|
; /* external interrupts handler */
|
||||||
|
EXPORT WWDGT_IRQHandler [WEAK]
|
||||||
|
EXPORT LVD_IRQHandler [WEAK]
|
||||||
|
EXPORT TAMPER_STAMP_IRQHandler [WEAK]
|
||||||
|
EXPORT RTC_WKUP_IRQHandler [WEAK]
|
||||||
|
EXPORT FMC_IRQHandler [WEAK]
|
||||||
|
EXPORT RCU_CTC_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI0_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI1_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI2_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI3_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI4_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA0_Channel0_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA0_Channel1_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA0_Channel2_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA0_Channel3_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA0_Channel4_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA0_Channel5_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA0_Channel6_IRQHandler [WEAK]
|
||||||
|
EXPORT ADC_IRQHandler [WEAK]
|
||||||
|
EXPORT CAN0_TX_IRQHandler [WEAK]
|
||||||
|
EXPORT CAN0_RX0_IRQHandler [WEAK]
|
||||||
|
EXPORT CAN0_RX1_IRQHandler [WEAK]
|
||||||
|
EXPORT CAN0_EWMC_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI5_9_IRQHandler [WEAK]
|
||||||
|
EXPORT TIMER0_BRK_TIMER8_IRQHandler [WEAK]
|
||||||
|
EXPORT TIMER0_UP_TIMER9_IRQHandler [WEAK]
|
||||||
|
EXPORT TIMER0_TRG_CMT_TIMER10_IRQHandler [WEAK]
|
||||||
|
EXPORT TIMER0_Channel_IRQHandler [WEAK]
|
||||||
|
EXPORT TIMER1_IRQHandler [WEAK]
|
||||||
|
EXPORT TIMER2_IRQHandler [WEAK]
|
||||||
|
EXPORT TIMER3_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C0_EV_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C0_ER_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C1_EV_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C1_ER_IRQHandler [WEAK]
|
||||||
|
EXPORT SPI0_IRQHandler [WEAK]
|
||||||
|
EXPORT SPI1_IRQHandler [WEAK]
|
||||||
|
EXPORT USART0_IRQHandler [WEAK]
|
||||||
|
EXPORT USART1_IRQHandler [WEAK]
|
||||||
|
EXPORT USART2_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI10_15_IRQHandler [WEAK]
|
||||||
|
EXPORT RTC_Alarm_IRQHandler [WEAK]
|
||||||
|
EXPORT USBFS_WKUP_IRQHandler [WEAK]
|
||||||
|
EXPORT TIMER7_BRK_TIMER11_IRQHandler [WEAK]
|
||||||
|
EXPORT TIMER7_UP_TIMER12_IRQHandler [WEAK]
|
||||||
|
EXPORT TIMER7_TRG_CMT_TIMER13_IRQHandler [WEAK]
|
||||||
|
EXPORT TIMER7_Channel_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA0_Channel7_IRQHandler [WEAK]
|
||||||
|
EXPORT EXMC_IRQHandler [WEAK]
|
||||||
|
EXPORT SDIO_IRQHandler [WEAK]
|
||||||
|
EXPORT TIMER4_IRQHandler [WEAK]
|
||||||
|
EXPORT SPI2_IRQHandler [WEAK]
|
||||||
|
EXPORT UART3_IRQHandler [WEAK]
|
||||||
|
EXPORT UART4_IRQHandler [WEAK]
|
||||||
|
EXPORT TIMER5_DAC_IRQHandler [WEAK]
|
||||||
|
EXPORT TIMER6_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel0_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel1_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel2_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel3_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel4_IRQHandler [WEAK]
|
||||||
|
EXPORT ENET_IRQHandler [WEAK]
|
||||||
|
EXPORT ENET_WKUP_IRQHandler [WEAK]
|
||||||
|
EXPORT CAN1_TX_IRQHandler [WEAK]
|
||||||
|
EXPORT CAN1_RX0_IRQHandler [WEAK]
|
||||||
|
EXPORT CAN1_RX1_IRQHandler [WEAK]
|
||||||
|
EXPORT CAN1_EWMC_IRQHandler [WEAK]
|
||||||
|
EXPORT USBFS_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel5_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel6_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel7_IRQHandler [WEAK]
|
||||||
|
EXPORT USART5_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C2_EV_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C2_ER_IRQHandler [WEAK]
|
||||||
|
EXPORT USBHS_EP1_Out_IRQHandler [WEAK]
|
||||||
|
EXPORT USBHS_EP1_In_IRQHandler [WEAK]
|
||||||
|
EXPORT USBHS_WKUP_IRQHandler [WEAK]
|
||||||
|
EXPORT USBHS_IRQHandler [WEAK]
|
||||||
|
EXPORT DCI_IRQHandler [WEAK]
|
||||||
|
EXPORT TRNG_IRQHandler [WEAK]
|
||||||
|
EXPORT FPU_IRQHandler [WEAK]
|
||||||
|
EXPORT UART6_IRQHandler [WEAK]
|
||||||
|
EXPORT UART7_IRQHandler [WEAK]
|
||||||
|
EXPORT SPI3_IRQHandler [WEAK]
|
||||||
|
EXPORT SPI4_IRQHandler [WEAK]
|
||||||
|
EXPORT SPI5_IRQHandler [WEAK]
|
||||||
|
EXPORT TLI_IRQHandler [WEAK]
|
||||||
|
EXPORT TLI_ER_IRQHandler [WEAK]
|
||||||
|
EXPORT IPA_IRQHandler [WEAK]
|
||||||
|
|
||||||
|
;/* external interrupts handler */
|
||||||
|
WWDGT_IRQHandler
|
||||||
|
LVD_IRQHandler
|
||||||
|
TAMPER_STAMP_IRQHandler
|
||||||
|
RTC_WKUP_IRQHandler
|
||||||
|
FMC_IRQHandler
|
||||||
|
RCU_CTC_IRQHandler
|
||||||
|
EXTI0_IRQHandler
|
||||||
|
EXTI1_IRQHandler
|
||||||
|
EXTI2_IRQHandler
|
||||||
|
EXTI3_IRQHandler
|
||||||
|
EXTI4_IRQHandler
|
||||||
|
DMA0_Channel0_IRQHandler
|
||||||
|
DMA0_Channel1_IRQHandler
|
||||||
|
DMA0_Channel2_IRQHandler
|
||||||
|
DMA0_Channel3_IRQHandler
|
||||||
|
DMA0_Channel4_IRQHandler
|
||||||
|
DMA0_Channel5_IRQHandler
|
||||||
|
DMA0_Channel6_IRQHandler
|
||||||
|
ADC_IRQHandler
|
||||||
|
CAN0_TX_IRQHandler
|
||||||
|
CAN0_RX0_IRQHandler
|
||||||
|
CAN0_RX1_IRQHandler
|
||||||
|
CAN0_EWMC_IRQHandler
|
||||||
|
EXTI5_9_IRQHandler
|
||||||
|
TIMER0_BRK_TIMER8_IRQHandler
|
||||||
|
TIMER0_UP_TIMER9_IRQHandler
|
||||||
|
TIMER0_TRG_CMT_TIMER10_IRQHandler
|
||||||
|
TIMER0_Channel_IRQHandler
|
||||||
|
TIMER1_IRQHandler
|
||||||
|
TIMER2_IRQHandler
|
||||||
|
TIMER3_IRQHandler
|
||||||
|
I2C0_EV_IRQHandler
|
||||||
|
I2C0_ER_IRQHandler
|
||||||
|
I2C1_EV_IRQHandler
|
||||||
|
I2C1_ER_IRQHandler
|
||||||
|
SPI0_IRQHandler
|
||||||
|
SPI1_IRQHandler
|
||||||
|
USART0_IRQHandler
|
||||||
|
USART1_IRQHandler
|
||||||
|
USART2_IRQHandler
|
||||||
|
EXTI10_15_IRQHandler
|
||||||
|
RTC_Alarm_IRQHandler
|
||||||
|
USBFS_WKUP_IRQHandler
|
||||||
|
TIMER7_BRK_TIMER11_IRQHandler
|
||||||
|
TIMER7_UP_TIMER12_IRQHandler
|
||||||
|
TIMER7_TRG_CMT_TIMER13_IRQHandler
|
||||||
|
TIMER7_Channel_IRQHandler
|
||||||
|
DMA0_Channel7_IRQHandler
|
||||||
|
EXMC_IRQHandler
|
||||||
|
SDIO_IRQHandler
|
||||||
|
TIMER4_IRQHandler
|
||||||
|
SPI2_IRQHandler
|
||||||
|
UART3_IRQHandler
|
||||||
|
UART4_IRQHandler
|
||||||
|
TIMER5_DAC_IRQHandler
|
||||||
|
TIMER6_IRQHandler
|
||||||
|
DMA1_Channel0_IRQHandler
|
||||||
|
DMA1_Channel1_IRQHandler
|
||||||
|
DMA1_Channel2_IRQHandler
|
||||||
|
DMA1_Channel3_IRQHandler
|
||||||
|
DMA1_Channel4_IRQHandler
|
||||||
|
ENET_IRQHandler
|
||||||
|
ENET_WKUP_IRQHandler
|
||||||
|
CAN1_TX_IRQHandler
|
||||||
|
CAN1_RX0_IRQHandler
|
||||||
|
CAN1_RX1_IRQHandler
|
||||||
|
CAN1_EWMC_IRQHandler
|
||||||
|
USBFS_IRQHandler
|
||||||
|
DMA1_Channel5_IRQHandler
|
||||||
|
DMA1_Channel6_IRQHandler
|
||||||
|
DMA1_Channel7_IRQHandler
|
||||||
|
USART5_IRQHandler
|
||||||
|
I2C2_EV_IRQHandler
|
||||||
|
I2C2_ER_IRQHandler
|
||||||
|
USBHS_EP1_Out_IRQHandler
|
||||||
|
USBHS_EP1_In_IRQHandler
|
||||||
|
USBHS_WKUP_IRQHandler
|
||||||
|
USBHS_IRQHandler
|
||||||
|
DCI_IRQHandler
|
||||||
|
TRNG_IRQHandler
|
||||||
|
FPU_IRQHandler
|
||||||
|
UART6_IRQHandler
|
||||||
|
UART7_IRQHandler
|
||||||
|
SPI3_IRQHandler
|
||||||
|
SPI4_IRQHandler
|
||||||
|
SPI5_IRQHandler
|
||||||
|
TLI_IRQHandler
|
||||||
|
TLI_ER_IRQHandler
|
||||||
|
IPA_IRQHandler
|
||||||
|
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
|
||||||
|
ALIGN
|
||||||
|
|
||||||
|
; user Initial Stack & Heap
|
||||||
|
|
||||||
|
IF :DEF:__MICROLIB
|
||||||
|
|
||||||
|
EXPORT __initial_sp
|
||||||
|
EXPORT __heap_base
|
||||||
|
EXPORT __heap_limit
|
||||||
|
|
||||||
|
ELSE
|
||||||
|
|
||||||
|
IMPORT __use_two_region_memory
|
||||||
|
EXPORT __user_initial_stackheap
|
||||||
|
|
||||||
|
__user_initial_stackheap PROC
|
||||||
|
LDR R0, = Heap_Mem
|
||||||
|
LDR R1, =(Stack_Mem + Stack_Size)
|
||||||
|
LDR R2, = (Heap_Mem + Heap_Size)
|
||||||
|
LDR R3, = Stack_Mem
|
||||||
|
BX LR
|
||||||
|
ENDP
|
||||||
|
|
||||||
|
ALIGN
|
||||||
|
|
||||||
|
ENDIF
|
||||||
|
|
||||||
|
END
|
||||||
|
|
@ -0,0 +1,602 @@
|
||||||
|
;/*!
|
||||||
|
; \file startup_gd32f405_425.s
|
||||||
|
; \brief start up file
|
||||||
|
;
|
||||||
|
; \version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
||||||
|
; \version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
||||||
|
; \version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
||||||
|
; \version 2022-03-09, V3.0.0, firmware for GD32F4xx
|
||||||
|
;*/
|
||||||
|
;
|
||||||
|
;/*
|
||||||
|
; Copyright (c) 2022, GigaDevice Semiconductor Inc.
|
||||||
|
;
|
||||||
|
; Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
;are permitted provided that the following conditions are met:
|
||||||
|
;
|
||||||
|
; 1. Redistributions of source code must retain the above copyright notice, this
|
||||||
|
; list of conditions and the following disclaimer.
|
||||||
|
; 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
; this list of conditions and the following disclaimer in the documentation
|
||||||
|
; and/or other materials provided with the distribution.
|
||||||
|
; 3. Neither the name of the copyright holder nor the names of its contributors
|
||||||
|
; may be used to endorse or promote products derived from this software without
|
||||||
|
; specific prior written permission.
|
||||||
|
;
|
||||||
|
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
;AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||||
|
;WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||||
|
;IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||||
|
;INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||||
|
;NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||||
|
;PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||||
|
;WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||||
|
;ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||||
|
;OF SUCH DAMAGE.
|
||||||
|
;*/
|
||||||
|
|
||||||
|
MODULE ?cstartup
|
||||||
|
|
||||||
|
;; Forward declaration of sections.
|
||||||
|
SECTION CSTACK:DATA:NOROOT(3)
|
||||||
|
|
||||||
|
SECTION .intvec:CODE:NOROOT(2)
|
||||||
|
|
||||||
|
EXTERN __iar_program_start
|
||||||
|
EXTERN SystemInit
|
||||||
|
PUBLIC __vector_table
|
||||||
|
|
||||||
|
DATA
|
||||||
|
__vector_table
|
||||||
|
DCD sfe(CSTACK) ; top of stack
|
||||||
|
DCD Reset_Handler ; Vector Number 1,Reset Handler
|
||||||
|
|
||||||
|
DCD NMI_Handler ; Vector Number 2,NMI Handler
|
||||||
|
DCD HardFault_Handler ; Vector Number 3,Hard Fault Handler
|
||||||
|
DCD MemManage_Handler ; Vector Number 4,MPU Fault Handler
|
||||||
|
DCD BusFault_Handler ; Vector Number 5,Bus Fault Handler
|
||||||
|
DCD UsageFault_Handler ; Vector Number 6,Usage Fault Handler
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD SVC_Handler ; Vector Number 11,SVCall Handler
|
||||||
|
DCD DebugMon_Handler ; Vector Number 12,Debug Monitor Handler
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD PendSV_Handler ; Vector Number 14,PendSV Handler
|
||||||
|
DCD SysTick_Handler ; Vector Number 15,SysTick Handler
|
||||||
|
|
||||||
|
; External Interrupts
|
||||||
|
DCD WWDGT_IRQHandler ; 16:Window Watchdog Timer
|
||||||
|
DCD LVD_IRQHandler ; 17:LVD through EXTI Line detect
|
||||||
|
DCD TAMPER_STAMP_IRQHandler ; 18:Tamper and TimeStamp through EXTI Line detect
|
||||||
|
DCD RTC_WKUP_IRQHandler ; 19:RTC Wakeup through EXTI Line
|
||||||
|
DCD FMC_IRQHandler ; 20:FMC
|
||||||
|
DCD RCU_CTC_IRQHandler ; 21:RCU and CTC
|
||||||
|
DCD EXTI0_IRQHandler ; 22:EXTI Line 0
|
||||||
|
DCD EXTI1_IRQHandler ; 23:EXTI Line 1
|
||||||
|
DCD EXTI2_IRQHandler ; 24:EXTI Line 2
|
||||||
|
DCD EXTI3_IRQHandler ; 25:EXTI Line 3
|
||||||
|
DCD EXTI4_IRQHandler ; 26:EXTI Line 4
|
||||||
|
DCD DMA0_Channel0_IRQHandler ; 27:DMA0 Channel0
|
||||||
|
DCD DMA0_Channel1_IRQHandler ; 28:DMA0 Channel1
|
||||||
|
DCD DMA0_Channel2_IRQHandler ; 29:DMA0 Channel2
|
||||||
|
DCD DMA0_Channel3_IRQHandler ; 30:DMA0 Channel3
|
||||||
|
DCD DMA0_Channel4_IRQHandler ; 31:DMA0 Channel4
|
||||||
|
DCD DMA0_Channel5_IRQHandler ; 32:DMA0 Channel5
|
||||||
|
DCD DMA0_Channel6_IRQHandler ; 33:DMA0 Channel6
|
||||||
|
DCD ADC_IRQHandler ; 34:ADC
|
||||||
|
DCD CAN0_TX_IRQHandler ; 35:CAN0 TX
|
||||||
|
DCD CAN0_RX0_IRQHandler ; 36:CAN0 RX0
|
||||||
|
DCD CAN0_RX1_IRQHandler ; 37:CAN0 RX1
|
||||||
|
DCD CAN0_EWMC_IRQHandler ; 38:CAN0 EWMC
|
||||||
|
DCD EXTI5_9_IRQHandler ; 39:EXTI5 to EXTI9
|
||||||
|
DCD TIMER0_BRK_TIMER8_IRQHandler ; 40:TIMER0 Break and TIMER8
|
||||||
|
DCD TIMER0_UP_TIMER9_IRQHandler ; 41:TIMER0 Update and TIMER9
|
||||||
|
DCD TIMER0_TRG_CMT_TIMER10_IRQHandler ; 42:TIMER0 Trigger and Commucation and TIMER10
|
||||||
|
DCD TIMER0_Channel_IRQHandler ; 43:TIMER0 Capture Compare
|
||||||
|
DCD TIMER1_IRQHandler ; 44:TIMER1
|
||||||
|
DCD TIMER2_IRQHandler ; 45:TIMER2
|
||||||
|
DCD TIMER3_IRQHandler ; 46:TIMER3
|
||||||
|
DCD I2C0_EV_IRQHandler ; 47:I2C0 Event
|
||||||
|
DCD I2C0_ER_IRQHandler ; 48:I2C0 Error
|
||||||
|
DCD I2C1_EV_IRQHandler ; 49:I2C1 Event
|
||||||
|
DCD I2C1_ER_IRQHandler ; 50:I2C1 Error
|
||||||
|
DCD SPI0_IRQHandler ; 51:SPI0
|
||||||
|
DCD SPI1_IRQHandler ; 52:SPI1
|
||||||
|
DCD USART0_IRQHandler ; 53:USART0
|
||||||
|
DCD USART1_IRQHandler ; 54:USART1
|
||||||
|
DCD USART2_IRQHandler ; 55:USART2
|
||||||
|
DCD EXTI10_15_IRQHandler ; 56:EXTI10 to EXTI15
|
||||||
|
DCD RTC_Alarm_IRQHandler ; 57:RTC Alarm
|
||||||
|
DCD USBFS_WKUP_IRQHandler ; 58:USBFS Wakeup
|
||||||
|
DCD TIMER7_BRK_TIMER11_IRQHandler ; 59:TIMER7 Break and TIMER11
|
||||||
|
DCD TIMER7_UP_TIMER12_IRQHandler ; 60:TIMER7 Update and TIMER12
|
||||||
|
DCD TIMER7_TRG_CMT_TIMER13_IRQHandler ; 61:TIMER7 Trigger and Commucation and TIMER13
|
||||||
|
DCD TIMER7_Channel_IRQHandler ; 62:TIMER7 Capture Compare
|
||||||
|
DCD DMA0_Channel7_IRQHandler ; 63:DMA0 Channel7
|
||||||
|
DCD 0 ; 64:Reserved
|
||||||
|
DCD SDIO_IRQHandler ; 65:SDIO
|
||||||
|
DCD TIMER4_IRQHandler ; 66:TIMER4
|
||||||
|
DCD SPI2_IRQHandler ; 67:SPI2
|
||||||
|
DCD UART3_IRQHandler ; 68:UART3
|
||||||
|
DCD UART4_IRQHandler ; 69:UART4
|
||||||
|
DCD TIMER5_DAC_IRQHandler ; 70:TIMER5 and DAC0 DAC1 Underrun error
|
||||||
|
DCD TIMER6_IRQHandler ; 71:TIMER6
|
||||||
|
DCD DMA1_Channel0_IRQHandler ; 72:DMA1 Channel0
|
||||||
|
DCD DMA1_Channel1_IRQHandler ; 73:DMA1 Channel1
|
||||||
|
DCD DMA1_Channel2_IRQHandler ; 74:DMA1 Channel2
|
||||||
|
DCD DMA1_Channel3_IRQHandler ; 75:DMA1 Channel3
|
||||||
|
DCD DMA1_Channel4_IRQHandler ; 76:DMA1 Channel4
|
||||||
|
DCD 0 ; 77:Reserved
|
||||||
|
DCD 0 ; 78:Reserved
|
||||||
|
DCD CAN1_TX_IRQHandler ; 79:CAN1 TX
|
||||||
|
DCD CAN1_RX0_IRQHandler ; 80:CAN1 RX0
|
||||||
|
DCD CAN1_RX1_IRQHandler ; 81:CAN1 RX1
|
||||||
|
DCD CAN1_EWMC_IRQHandler ; 82:CAN1 EWMC
|
||||||
|
DCD USBFS_IRQHandler ; 83:USBFS
|
||||||
|
DCD DMA1_Channel5_IRQHandler ; 84:DMA1 Channel5
|
||||||
|
DCD DMA1_Channel6_IRQHandler ; 85:DMA1 Channel6
|
||||||
|
DCD DMA1_Channel7_IRQHandler ; 86:DMA1 Channel7
|
||||||
|
DCD USART5_IRQHandler ; 87:USART5
|
||||||
|
DCD I2C2_EV_IRQHandler ; 88:I2C2 Event
|
||||||
|
DCD I2C2_ER_IRQHandler ; 89:I2C2 Error
|
||||||
|
DCD USBHS_EP1_Out_IRQHandler ; 90:USBHS Endpoint 1 Out
|
||||||
|
DCD USBHS_EP1_In_IRQHandler ; 91:USBHS Endpoint 1 in
|
||||||
|
DCD USBHS_WKUP_IRQHandler ; 92:USBHS Wakeup through EXTI Line
|
||||||
|
DCD USBHS_IRQHandler ; 93:USBHS
|
||||||
|
DCD DCI_IRQHandler ; 94:DCI
|
||||||
|
DCD 0 ; 95:Reserved
|
||||||
|
DCD TRNG_IRQHandler ; 96:TRNG
|
||||||
|
DCD FPU_IRQHandler ; 97:FPU
|
||||||
|
|
||||||
|
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||||
|
;;
|
||||||
|
;; Default interrupt handlers.
|
||||||
|
;;
|
||||||
|
THUMB
|
||||||
|
|
||||||
|
PUBWEAK Reset_Handler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(2)
|
||||||
|
Reset_Handler
|
||||||
|
LDR R0, =SystemInit
|
||||||
|
BLX R0
|
||||||
|
LDR R0, =__iar_program_start
|
||||||
|
BX R0
|
||||||
|
|
||||||
|
PUBWEAK NMI_Handler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
NMI_Handler
|
||||||
|
B NMI_Handler
|
||||||
|
|
||||||
|
PUBWEAK HardFault_Handler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
HardFault_Handler
|
||||||
|
B HardFault_Handler
|
||||||
|
|
||||||
|
PUBWEAK MemManage_Handler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
MemManage_Handler
|
||||||
|
B MemManage_Handler
|
||||||
|
|
||||||
|
PUBWEAK BusFault_Handler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
BusFault_Handler
|
||||||
|
B BusFault_Handler
|
||||||
|
|
||||||
|
PUBWEAK UsageFault_Handler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
UsageFault_Handler
|
||||||
|
B UsageFault_Handler
|
||||||
|
|
||||||
|
PUBWEAK SVC_Handler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
SVC_Handler
|
||||||
|
B SVC_Handler
|
||||||
|
|
||||||
|
PUBWEAK DebugMon_Handler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
DebugMon_Handler
|
||||||
|
B DebugMon_Handler
|
||||||
|
|
||||||
|
PUBWEAK PendSV_Handler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
PendSV_Handler
|
||||||
|
B PendSV_Handler
|
||||||
|
|
||||||
|
PUBWEAK SysTick_Handler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
SysTick_Handler
|
||||||
|
B SysTick_Handler
|
||||||
|
|
||||||
|
PUBWEAK WWDGT_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
WWDGT_IRQHandler
|
||||||
|
B WWDGT_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK LVD_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
LVD_IRQHandler
|
||||||
|
B LVD_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK TAMPER_STAMP_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
TAMPER_STAMP_IRQHandler
|
||||||
|
B TAMPER_STAMP_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK RTC_WKUP_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
RTC_WKUP_IRQHandler
|
||||||
|
B RTC_WKUP_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK FMC_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
FMC_IRQHandler
|
||||||
|
B FMC_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK RCU_CTC_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
RCU_CTC_IRQHandler
|
||||||
|
B RCU_CTC_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK EXTI0_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
EXTI0_IRQHandler
|
||||||
|
B EXTI0_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK EXTI1_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
EXTI1_IRQHandler
|
||||||
|
B EXTI1_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK EXTI2_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
EXTI2_IRQHandler
|
||||||
|
B EXTI2_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK EXTI3_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
EXTI3_IRQHandler
|
||||||
|
B EXTI3_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK EXTI4_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
EXTI4_IRQHandler
|
||||||
|
B EXTI4_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA0_Channel0_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
DMA0_Channel0_IRQHandler
|
||||||
|
B DMA0_Channel0_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA0_Channel1_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
DMA0_Channel1_IRQHandler
|
||||||
|
B DMA0_Channel1_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA0_Channel2_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
DMA0_Channel2_IRQHandler
|
||||||
|
B DMA0_Channel2_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA0_Channel3_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
DMA0_Channel3_IRQHandler
|
||||||
|
B DMA0_Channel3_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA0_Channel4_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
DMA0_Channel4_IRQHandler
|
||||||
|
B DMA0_Channel4_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA0_Channel5_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
DMA0_Channel5_IRQHandler
|
||||||
|
B DMA0_Channel5_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA0_Channel6_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
DMA0_Channel6_IRQHandler
|
||||||
|
B DMA0_Channel6_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK ADC_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
ADC_IRQHandler
|
||||||
|
B ADC_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK CAN0_TX_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
CAN0_TX_IRQHandler
|
||||||
|
B CAN0_TX_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK CAN0_RX0_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
CAN0_RX0_IRQHandler
|
||||||
|
B CAN0_RX0_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK CAN0_RX1_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
CAN0_RX1_IRQHandler
|
||||||
|
B CAN0_RX1_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK CAN0_EWMC_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
CAN0_EWMC_IRQHandler
|
||||||
|
B CAN0_EWMC_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK EXTI5_9_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
EXTI5_9_IRQHandler
|
||||||
|
B EXTI5_9_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK TIMER0_BRK_TIMER8_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
TIMER0_BRK_TIMER8_IRQHandler
|
||||||
|
B TIMER0_BRK_TIMER8_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK TIMER0_UP_TIMER9_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
TIMER0_UP_TIMER9_IRQHandler
|
||||||
|
B TIMER0_UP_TIMER9_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK TIMER0_TRG_CMT_TIMER10_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
TIMER0_TRG_CMT_TIMER10_IRQHandler
|
||||||
|
B TIMER0_TRG_CMT_TIMER10_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK TIMER0_Channel_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
TIMER0_Channel_IRQHandler
|
||||||
|
B TIMER0_Channel_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK TIMER1_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
TIMER1_IRQHandler
|
||||||
|
B TIMER1_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK TIMER2_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
TIMER2_IRQHandler
|
||||||
|
B TIMER2_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK TIMER3_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
TIMER3_IRQHandler
|
||||||
|
B TIMER3_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK I2C0_EV_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
I2C0_EV_IRQHandler
|
||||||
|
B I2C0_EV_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK I2C0_ER_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
I2C0_ER_IRQHandler
|
||||||
|
B I2C0_ER_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK I2C1_EV_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
I2C1_EV_IRQHandler
|
||||||
|
B I2C1_EV_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK I2C1_ER_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
I2C1_ER_IRQHandler
|
||||||
|
B I2C1_ER_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK SPI0_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
SPI0_IRQHandler
|
||||||
|
B SPI0_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK SPI1_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
SPI1_IRQHandler
|
||||||
|
B SPI1_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK USART0_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
USART0_IRQHandler
|
||||||
|
B USART0_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK USART1_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
USART1_IRQHandler
|
||||||
|
B USART1_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK USART2_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
USART2_IRQHandler
|
||||||
|
B USART2_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK EXTI10_15_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
EXTI10_15_IRQHandler
|
||||||
|
B EXTI10_15_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK RTC_Alarm_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
RTC_Alarm_IRQHandler
|
||||||
|
B RTC_Alarm_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK USBFS_WKUP_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
USBFS_WKUP_IRQHandler
|
||||||
|
B USBFS_WKUP_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK TIMER7_BRK_TIMER11_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
TIMER7_BRK_TIMER11_IRQHandler
|
||||||
|
B TIMER7_BRK_TIMER11_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK TIMER7_UP_TIMER12_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
TIMER7_UP_TIMER12_IRQHandler
|
||||||
|
B TIMER7_UP_TIMER12_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK TIMER7_TRG_CMT_TIMER13_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
TIMER7_TRG_CMT_TIMER13_IRQHandler
|
||||||
|
B TIMER7_TRG_CMT_TIMER13_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK TIMER7_Channel_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
TIMER7_Channel_IRQHandler
|
||||||
|
B TIMER7_Channel_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA0_Channel7_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
DMA0_Channel7_IRQHandler
|
||||||
|
B DMA0_Channel7_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK SDIO_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
SDIO_IRQHandler
|
||||||
|
B SDIO_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK TIMER4_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
TIMER4_IRQHandler
|
||||||
|
B TIMER4_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK SPI2_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
SPI2_IRQHandler
|
||||||
|
B SPI2_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK UART3_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
UART3_IRQHandler
|
||||||
|
B UART3_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK UART4_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
UART4_IRQHandler
|
||||||
|
B UART4_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK TIMER5_DAC_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
TIMER5_DAC_IRQHandler
|
||||||
|
B TIMER5_DAC_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK TIMER6_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
TIMER6_IRQHandler
|
||||||
|
B TIMER6_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA1_Channel0_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
DMA1_Channel0_IRQHandler
|
||||||
|
B DMA1_Channel0_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA1_Channel1_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
DMA1_Channel1_IRQHandler
|
||||||
|
B DMA1_Channel1_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA1_Channel2_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
DMA1_Channel2_IRQHandler
|
||||||
|
B DMA1_Channel2_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA1_Channel3_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
DMA1_Channel3_IRQHandler
|
||||||
|
B DMA1_Channel3_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA1_Channel4_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
DMA1_Channel4_IRQHandler
|
||||||
|
B DMA1_Channel4_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK CAN1_TX_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
CAN1_TX_IRQHandler
|
||||||
|
B CAN1_TX_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK CAN1_RX0_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
CAN1_RX0_IRQHandler
|
||||||
|
B CAN1_RX0_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK CAN1_RX1_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
CAN1_RX1_IRQHandler
|
||||||
|
B CAN1_RX1_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK CAN1_EWMC_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
CAN1_EWMC_IRQHandler
|
||||||
|
B CAN1_EWMC_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK USBFS_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
USBFS_IRQHandler
|
||||||
|
B USBFS_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA1_Channel5_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
DMA1_Channel5_IRQHandler
|
||||||
|
B DMA1_Channel5_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA1_Channel6_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
DMA1_Channel6_IRQHandler
|
||||||
|
B DMA1_Channel6_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA1_Channel7_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
DMA1_Channel7_IRQHandler
|
||||||
|
B DMA1_Channel7_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK USART5_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
USART5_IRQHandler
|
||||||
|
B USART5_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK I2C2_EV_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
I2C2_EV_IRQHandler
|
||||||
|
B I2C2_EV_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK I2C2_ER_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
I2C2_ER_IRQHandler
|
||||||
|
B I2C2_ER_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK USBHS_EP1_Out_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
USBHS_EP1_Out_IRQHandler
|
||||||
|
B USBHS_EP1_Out_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK USBHS_EP1_In_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
USBHS_EP1_In_IRQHandler
|
||||||
|
B USBHS_EP1_In_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK USBHS_WKUP_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
USBHS_WKUP_IRQHandler
|
||||||
|
B USBHS_WKUP_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK USBHS_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
USBHS_IRQHandler
|
||||||
|
B USBHS_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DCI_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
DCI_IRQHandler
|
||||||
|
B DCI_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK TRNG_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
TRNG_IRQHandler
|
||||||
|
B TRNG_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK FPU_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
FPU_IRQHandler
|
||||||
|
B FPU_IRQHandler
|
||||||
|
|
||||||
|
END
|
||||||
|
|
@ -0,0 +1,617 @@
|
||||||
|
;/*!
|
||||||
|
; \file startup_gd32f407_427.s
|
||||||
|
; \brief start up file
|
||||||
|
;
|
||||||
|
; \version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
||||||
|
; \version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
||||||
|
; \version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
||||||
|
; \version 2022-03-09, V3.0.0, firmware for GD32F4xx
|
||||||
|
;*/
|
||||||
|
;
|
||||||
|
;/*
|
||||||
|
; Copyright (c) 2022, GigaDevice Semiconductor Inc.
|
||||||
|
;
|
||||||
|
; Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
;are permitted provided that the following conditions are met:
|
||||||
|
;
|
||||||
|
; 1. Redistributions of source code must retain the above copyright notice, this
|
||||||
|
; list of conditions and the following disclaimer.
|
||||||
|
; 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
; this list of conditions and the following disclaimer in the documentation
|
||||||
|
; and/or other materials provided with the distribution.
|
||||||
|
; 3. Neither the name of the copyright holder nor the names of its contributors
|
||||||
|
; may be used to endorse or promote products derived from this software without
|
||||||
|
; specific prior written permission.
|
||||||
|
;
|
||||||
|
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
;AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||||
|
;WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||||
|
;IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||||
|
;INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||||
|
;NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||||
|
;PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||||
|
;WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||||
|
;ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||||
|
;OF SUCH DAMAGE.
|
||||||
|
;*/
|
||||||
|
|
||||||
|
MODULE ?cstartup
|
||||||
|
|
||||||
|
;; Forward declaration of sections.
|
||||||
|
SECTION CSTACK:DATA:NOROOT(3)
|
||||||
|
|
||||||
|
SECTION .intvec:CODE:NOROOT(2)
|
||||||
|
|
||||||
|
EXTERN __iar_program_start
|
||||||
|
EXTERN SystemInit
|
||||||
|
PUBLIC __vector_table
|
||||||
|
|
||||||
|
DATA
|
||||||
|
__vector_table
|
||||||
|
DCD sfe(CSTACK) ; top of stack
|
||||||
|
DCD Reset_Handler ; Vector Number 1,Reset Handler
|
||||||
|
|
||||||
|
DCD NMI_Handler ; Vector Number 2,NMI Handler
|
||||||
|
DCD HardFault_Handler ; Vector Number 3,Hard Fault Handler
|
||||||
|
DCD MemManage_Handler ; Vector Number 4,MPU Fault Handler
|
||||||
|
DCD BusFault_Handler ; Vector Number 5,Bus Fault Handler
|
||||||
|
DCD UsageFault_Handler ; Vector Number 6,Usage Fault Handler
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD SVC_Handler ; Vector Number 11,SVCall Handler
|
||||||
|
DCD DebugMon_Handler ; Vector Number 12,Debug Monitor Handler
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD PendSV_Handler ; Vector Number 14,PendSV Handler
|
||||||
|
DCD SysTick_Handler ; Vector Number 15,SysTick Handler
|
||||||
|
|
||||||
|
; External Interrupts
|
||||||
|
DCD WWDGT_IRQHandler ; 16:Window Watchdog Timer
|
||||||
|
DCD LVD_IRQHandler ; 17:LVD through EXTI Line detect
|
||||||
|
DCD TAMPER_STAMP_IRQHandler ; 18:Tamper and TimeStamp through EXTI Line detect
|
||||||
|
DCD RTC_WKUP_IRQHandler ; 19:RTC Wakeup through EXTI Line
|
||||||
|
DCD FMC_IRQHandler ; 20:FMC
|
||||||
|
DCD RCU_CTC_IRQHandler ; 21:RCU and CTC
|
||||||
|
DCD EXTI0_IRQHandler ; 22:EXTI Line 0
|
||||||
|
DCD EXTI1_IRQHandler ; 23:EXTI Line 1
|
||||||
|
DCD EXTI2_IRQHandler ; 24:EXTI Line 2
|
||||||
|
DCD EXTI3_IRQHandler ; 25:EXTI Line 3
|
||||||
|
DCD EXTI4_IRQHandler ; 26:EXTI Line 4
|
||||||
|
DCD DMA0_Channel0_IRQHandler ; 27:DMA0 Channel0
|
||||||
|
DCD DMA0_Channel1_IRQHandler ; 28:DMA0 Channel1
|
||||||
|
DCD DMA0_Channel2_IRQHandler ; 29:DMA0 Channel2
|
||||||
|
DCD DMA0_Channel3_IRQHandler ; 30:DMA0 Channel3
|
||||||
|
DCD DMA0_Channel4_IRQHandler ; 31:DMA0 Channel4
|
||||||
|
DCD DMA0_Channel5_IRQHandler ; 32:DMA0 Channel5
|
||||||
|
DCD DMA0_Channel6_IRQHandler ; 33:DMA0 Channel6
|
||||||
|
DCD ADC_IRQHandler ; 34:ADC
|
||||||
|
DCD CAN0_TX_IRQHandler ; 35:CAN0 TX
|
||||||
|
DCD CAN0_RX0_IRQHandler ; 36:CAN0 RX0
|
||||||
|
DCD CAN0_RX1_IRQHandler ; 37:CAN0 RX1
|
||||||
|
DCD CAN0_EWMC_IRQHandler ; 38:CAN0 EWMC
|
||||||
|
DCD EXTI5_9_IRQHandler ; 39:EXTI5 to EXTI9
|
||||||
|
DCD TIMER0_BRK_TIMER8_IRQHandler ; 40:TIMER0 Break and TIMER8
|
||||||
|
DCD TIMER0_UP_TIMER9_IRQHandler ; 41:TIMER0 Update and TIMER9
|
||||||
|
DCD TIMER0_TRG_CMT_TIMER10_IRQHandler ; 42:TIMER0 Trigger and Commucation and TIMER10
|
||||||
|
DCD TIMER0_Channel_IRQHandler ; 43:TIMER0 Capture Compare
|
||||||
|
DCD TIMER1_IRQHandler ; 44:TIMER1
|
||||||
|
DCD TIMER2_IRQHandler ; 45:TIMER2
|
||||||
|
DCD TIMER3_IRQHandler ; 46:TIMER3
|
||||||
|
DCD I2C0_EV_IRQHandler ; 47:I2C0 Event
|
||||||
|
DCD I2C0_ER_IRQHandler ; 48:I2C0 Error
|
||||||
|
DCD I2C1_EV_IRQHandler ; 49:I2C1 Event
|
||||||
|
DCD I2C1_ER_IRQHandler ; 50:I2C1 Error
|
||||||
|
DCD SPI0_IRQHandler ; 51:SPI0
|
||||||
|
DCD SPI1_IRQHandler ; 52:SPI1
|
||||||
|
DCD USART0_IRQHandler ; 53:USART0
|
||||||
|
DCD USART1_IRQHandler ; 54:USART1
|
||||||
|
DCD USART2_IRQHandler ; 55:USART2
|
||||||
|
DCD EXTI10_15_IRQHandler ; 56:EXTI10 to EXTI15
|
||||||
|
DCD RTC_Alarm_IRQHandler ; 57:RTC Alarm
|
||||||
|
DCD USBFS_WKUP_IRQHandler ; 58:USBFS Wakeup
|
||||||
|
DCD TIMER7_BRK_TIMER11_IRQHandler ; 59:TIMER7 Break and TIMER11
|
||||||
|
DCD TIMER7_UP_TIMER12_IRQHandler ; 60:TIMER7 Update and TIMER12
|
||||||
|
DCD TIMER7_TRG_CMT_TIMER13_IRQHandler ; 61:TIMER7 Trigger and Commucation and TIMER13
|
||||||
|
DCD TIMER7_Channel_IRQHandler ; 62:TIMER7 Channel Capture Compare
|
||||||
|
DCD DMA0_Channel7_IRQHandler ; 63:DMA0 Channel7
|
||||||
|
DCD EXMC_IRQHandler ; 64:EXMC
|
||||||
|
DCD SDIO_IRQHandler ; 65:SDIO
|
||||||
|
DCD TIMER4_IRQHandler ; 66:TIMER4
|
||||||
|
DCD SPI2_IRQHandler ; 67:SPI2
|
||||||
|
DCD UART3_IRQHandler ; 68:UART3
|
||||||
|
DCD UART4_IRQHandler ; 69:UART4
|
||||||
|
DCD TIMER5_DAC_IRQHandler ; 70:TIMER5 and DAC0 DAC1 Underrun error
|
||||||
|
DCD TIMER6_IRQHandler ; 71:TIMER6
|
||||||
|
DCD DMA1_Channel0_IRQHandler ; 72:DMA1 Channel0
|
||||||
|
DCD DMA1_Channel1_IRQHandler ; 73:DMA1 Channel1
|
||||||
|
DCD DMA1_Channel2_IRQHandler ; 74:DMA1 Channel2
|
||||||
|
DCD DMA1_Channel3_IRQHandler ; 75:DMA1 Channel3
|
||||||
|
DCD DMA1_Channel4_IRQHandler ; 76:DMA1 Channel4
|
||||||
|
DCD ENET_IRQHandler ; 77:Ethernet
|
||||||
|
DCD ENET_WKUP_IRQHandler ; 78:Ethernet Wakeup through EXTI Line
|
||||||
|
DCD CAN1_TX_IRQHandler ; 79:CAN1 TX
|
||||||
|
DCD CAN1_RX0_IRQHandler ; 80:CAN1 RX0
|
||||||
|
DCD CAN1_RX1_IRQHandler ; 81:CAN1 RX1
|
||||||
|
DCD CAN1_EWMC_IRQHandler ; 82:CAN1 EWMC
|
||||||
|
DCD USBFS_IRQHandler ; 83:USBFS
|
||||||
|
DCD DMA1_Channel5_IRQHandler ; 84:DMA1 Channel5
|
||||||
|
DCD DMA1_Channel6_IRQHandler ; 85:DMA1 Channel6
|
||||||
|
DCD DMA1_Channel7_IRQHandler ; 86:DMA1 Channel7
|
||||||
|
DCD USART5_IRQHandler ; 87:USART5
|
||||||
|
DCD I2C2_EV_IRQHandler ; 88:I2C2 Event
|
||||||
|
DCD I2C2_ER_IRQHandler ; 89:I2C2 Error
|
||||||
|
DCD USBHS_EP1_Out_IRQHandler ; 90:USBHS Endpoint 1 Out
|
||||||
|
DCD USBHS_EP1_In_IRQHandler ; 91:USBHS Endpoint 1 in
|
||||||
|
DCD USBHS_WKUP_IRQHandler ; 92:USBHS Wakeup through EXTI Line
|
||||||
|
DCD USBHS_IRQHandler ; 93:USBHS
|
||||||
|
DCD DCI_IRQHandler ; 94:DCI
|
||||||
|
DCD 0 ; 95:Reserved
|
||||||
|
DCD TRNG_IRQHandler ; 96:TRNG
|
||||||
|
DCD FPU_IRQHandler ; 97:FPU
|
||||||
|
|
||||||
|
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||||
|
;;
|
||||||
|
;; Default interrupt handlers.
|
||||||
|
;;
|
||||||
|
THUMB
|
||||||
|
|
||||||
|
PUBWEAK Reset_Handler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(2)
|
||||||
|
Reset_Handler
|
||||||
|
LDR R0, =SystemInit
|
||||||
|
BLX R0
|
||||||
|
LDR R0, =__iar_program_start
|
||||||
|
BX R0
|
||||||
|
|
||||||
|
PUBWEAK NMI_Handler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
NMI_Handler
|
||||||
|
B NMI_Handler
|
||||||
|
|
||||||
|
PUBWEAK HardFault_Handler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
HardFault_Handler
|
||||||
|
B HardFault_Handler
|
||||||
|
|
||||||
|
PUBWEAK MemManage_Handler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
MemManage_Handler
|
||||||
|
B MemManage_Handler
|
||||||
|
|
||||||
|
PUBWEAK BusFault_Handler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
BusFault_Handler
|
||||||
|
B BusFault_Handler
|
||||||
|
|
||||||
|
PUBWEAK UsageFault_Handler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
UsageFault_Handler
|
||||||
|
B UsageFault_Handler
|
||||||
|
|
||||||
|
PUBWEAK SVC_Handler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
SVC_Handler
|
||||||
|
B SVC_Handler
|
||||||
|
|
||||||
|
PUBWEAK DebugMon_Handler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
DebugMon_Handler
|
||||||
|
B DebugMon_Handler
|
||||||
|
|
||||||
|
PUBWEAK PendSV_Handler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
PendSV_Handler
|
||||||
|
B PendSV_Handler
|
||||||
|
|
||||||
|
PUBWEAK SysTick_Handler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
SysTick_Handler
|
||||||
|
B SysTick_Handler
|
||||||
|
|
||||||
|
PUBWEAK WWDGT_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
WWDGT_IRQHandler
|
||||||
|
B WWDGT_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK LVD_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
LVD_IRQHandler
|
||||||
|
B LVD_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK TAMPER_STAMP_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
TAMPER_STAMP_IRQHandler
|
||||||
|
B TAMPER_STAMP_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK RTC_WKUP_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
RTC_WKUP_IRQHandler
|
||||||
|
B RTC_WKUP_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK FMC_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
FMC_IRQHandler
|
||||||
|
B FMC_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK RCU_CTC_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
RCU_CTC_IRQHandler
|
||||||
|
B RCU_CTC_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK EXTI0_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
EXTI0_IRQHandler
|
||||||
|
B EXTI0_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK EXTI1_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
EXTI1_IRQHandler
|
||||||
|
B EXTI1_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK EXTI2_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
EXTI2_IRQHandler
|
||||||
|
B EXTI2_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK EXTI3_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
EXTI3_IRQHandler
|
||||||
|
B EXTI3_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK EXTI4_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
EXTI4_IRQHandler
|
||||||
|
B EXTI4_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA0_Channel0_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
DMA0_Channel0_IRQHandler
|
||||||
|
B DMA0_Channel0_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA0_Channel1_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
DMA0_Channel1_IRQHandler
|
||||||
|
B DMA0_Channel1_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA0_Channel2_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
DMA0_Channel2_IRQHandler
|
||||||
|
B DMA0_Channel2_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA0_Channel3_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
DMA0_Channel3_IRQHandler
|
||||||
|
B DMA0_Channel3_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA0_Channel4_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
DMA0_Channel4_IRQHandler
|
||||||
|
B DMA0_Channel4_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA0_Channel5_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
DMA0_Channel5_IRQHandler
|
||||||
|
B DMA0_Channel5_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA0_Channel6_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
DMA0_Channel6_IRQHandler
|
||||||
|
B DMA0_Channel6_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK ADC_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
ADC_IRQHandler
|
||||||
|
B ADC_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK CAN0_TX_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
CAN0_TX_IRQHandler
|
||||||
|
B CAN0_TX_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK CAN0_RX0_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
CAN0_RX0_IRQHandler
|
||||||
|
B CAN0_RX0_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK CAN0_RX1_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
CAN0_RX1_IRQHandler
|
||||||
|
B CAN0_RX1_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK CAN0_EWMC_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
CAN0_EWMC_IRQHandler
|
||||||
|
B CAN0_EWMC_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK EXTI5_9_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
EXTI5_9_IRQHandler
|
||||||
|
B EXTI5_9_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK TIMER0_BRK_TIMER8_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
TIMER0_BRK_TIMER8_IRQHandler
|
||||||
|
B TIMER0_BRK_TIMER8_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK TIMER0_UP_TIMER9_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
TIMER0_UP_TIMER9_IRQHandler
|
||||||
|
B TIMER0_UP_TIMER9_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK TIMER0_TRG_CMT_TIMER10_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
TIMER0_TRG_CMT_TIMER10_IRQHandler
|
||||||
|
B TIMER0_TRG_CMT_TIMER10_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK TIMER0_Channel_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
TIMER0_Channel_IRQHandler
|
||||||
|
B TIMER0_Channel_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK TIMER1_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
TIMER1_IRQHandler
|
||||||
|
B TIMER1_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK TIMER2_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
TIMER2_IRQHandler
|
||||||
|
B TIMER2_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK TIMER3_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
TIMER3_IRQHandler
|
||||||
|
B TIMER3_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK I2C0_EV_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
I2C0_EV_IRQHandler
|
||||||
|
B I2C0_EV_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK I2C0_ER_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
I2C0_ER_IRQHandler
|
||||||
|
B I2C0_ER_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK I2C1_EV_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
I2C1_EV_IRQHandler
|
||||||
|
B I2C1_EV_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK I2C1_ER_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
I2C1_ER_IRQHandler
|
||||||
|
B I2C1_ER_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK SPI0_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
SPI0_IRQHandler
|
||||||
|
B SPI0_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK SPI1_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
SPI1_IRQHandler
|
||||||
|
B SPI1_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK USART0_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
USART0_IRQHandler
|
||||||
|
B USART0_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK USART1_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
USART1_IRQHandler
|
||||||
|
B USART1_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK USART2_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
USART2_IRQHandler
|
||||||
|
B USART2_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK EXTI10_15_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
EXTI10_15_IRQHandler
|
||||||
|
B EXTI10_15_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK RTC_Alarm_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
RTC_Alarm_IRQHandler
|
||||||
|
B RTC_Alarm_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK USBFS_WKUP_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
USBFS_WKUP_IRQHandler
|
||||||
|
B USBFS_WKUP_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK TIMER7_BRK_TIMER11_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
TIMER7_BRK_TIMER11_IRQHandler
|
||||||
|
B TIMER7_BRK_TIMER11_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK TIMER7_UP_TIMER12_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
TIMER7_UP_TIMER12_IRQHandler
|
||||||
|
B TIMER7_UP_TIMER12_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK TIMER7_TRG_CMT_TIMER13_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
TIMER7_TRG_CMT_TIMER13_IRQHandler
|
||||||
|
B TIMER7_TRG_CMT_TIMER13_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK TIMER7_Channel_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
TIMER7_Channel_IRQHandler
|
||||||
|
B TIMER7_Channel_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA0_Channel7_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
DMA0_Channel7_IRQHandler
|
||||||
|
B DMA0_Channel7_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK EXMC_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
EXMC_IRQHandler
|
||||||
|
B EXMC_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK SDIO_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
SDIO_IRQHandler
|
||||||
|
B SDIO_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK TIMER4_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
TIMER4_IRQHandler
|
||||||
|
B TIMER4_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK SPI2_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
SPI2_IRQHandler
|
||||||
|
B SPI2_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK UART3_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
UART3_IRQHandler
|
||||||
|
B UART3_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK UART4_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
UART4_IRQHandler
|
||||||
|
B UART4_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK TIMER5_DAC_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
TIMER5_DAC_IRQHandler
|
||||||
|
B TIMER5_DAC_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK TIMER6_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
TIMER6_IRQHandler
|
||||||
|
B TIMER6_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA1_Channel0_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
DMA1_Channel0_IRQHandler
|
||||||
|
B DMA1_Channel0_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA1_Channel1_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
DMA1_Channel1_IRQHandler
|
||||||
|
B DMA1_Channel1_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA1_Channel2_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
DMA1_Channel2_IRQHandler
|
||||||
|
B DMA1_Channel2_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA1_Channel3_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
DMA1_Channel3_IRQHandler
|
||||||
|
B DMA1_Channel3_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA1_Channel4_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
DMA1_Channel4_IRQHandler
|
||||||
|
B DMA1_Channel4_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK ENET_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
ENET_IRQHandler
|
||||||
|
B ENET_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK ENET_WKUP_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
ENET_WKUP_IRQHandler
|
||||||
|
B ENET_WKUP_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK CAN1_TX_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
CAN1_TX_IRQHandler
|
||||||
|
B CAN1_TX_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK CAN1_RX0_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
CAN1_RX0_IRQHandler
|
||||||
|
B CAN1_RX0_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK CAN1_RX1_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
CAN1_RX1_IRQHandler
|
||||||
|
B CAN1_RX1_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK CAN1_EWMC_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
CAN1_EWMC_IRQHandler
|
||||||
|
B CAN1_EWMC_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK USBFS_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
USBFS_IRQHandler
|
||||||
|
B USBFS_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA1_Channel5_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
DMA1_Channel5_IRQHandler
|
||||||
|
B DMA1_Channel5_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA1_Channel6_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
DMA1_Channel6_IRQHandler
|
||||||
|
B DMA1_Channel6_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA1_Channel7_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
DMA1_Channel7_IRQHandler
|
||||||
|
B DMA1_Channel7_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK USART5_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
USART5_IRQHandler
|
||||||
|
B USART5_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK I2C2_EV_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
I2C2_EV_IRQHandler
|
||||||
|
B I2C2_EV_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK I2C2_ER_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
I2C2_ER_IRQHandler
|
||||||
|
B I2C2_ER_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK USBHS_EP1_Out_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
USBHS_EP1_Out_IRQHandler
|
||||||
|
B USBHS_EP1_Out_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK USBHS_EP1_In_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
USBHS_EP1_In_IRQHandler
|
||||||
|
B USBHS_EP1_In_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK USBHS_WKUP_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
USBHS_WKUP_IRQHandler
|
||||||
|
B USBHS_WKUP_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK USBHS_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
USBHS_IRQHandler
|
||||||
|
B USBHS_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DCI_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
DCI_IRQHandler
|
||||||
|
B DCI_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK TRNG_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
TRNG_IRQHandler
|
||||||
|
B TRNG_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK FPU_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
FPU_IRQHandler
|
||||||
|
B FPU_IRQHandler
|
||||||
|
|
||||||
|
END
|
||||||
|
|
@ -0,0 +1,666 @@
|
||||||
|
;/*!
|
||||||
|
; \file startup_gd32f450_470.s
|
||||||
|
; \brief start up file
|
||||||
|
;
|
||||||
|
; \version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
||||||
|
; \version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
||||||
|
; \version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
||||||
|
; \version 2022-03-09, V3.0.0, firmware for GD32F4xx
|
||||||
|
;*/
|
||||||
|
;
|
||||||
|
;/*
|
||||||
|
; Copyright (c) 2022, GigaDevice Semiconductor Inc.
|
||||||
|
;
|
||||||
|
; Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
;are permitted provided that the following conditions are met:
|
||||||
|
;
|
||||||
|
; 1. Redistributions of source code must retain the above copyright notice, this
|
||||||
|
; list of conditions and the following disclaimer.
|
||||||
|
; 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
; this list of conditions and the following disclaimer in the documentation
|
||||||
|
; and/or other materials provided with the distribution.
|
||||||
|
; 3. Neither the name of the copyright holder nor the names of its contributors
|
||||||
|
; may be used to endorse or promote products derived from this software without
|
||||||
|
; specific prior written permission.
|
||||||
|
;
|
||||||
|
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
;AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||||
|
;WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||||
|
;IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||||
|
;INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||||
|
;NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||||
|
;PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||||
|
;WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||||
|
;ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||||
|
;OF SUCH DAMAGE.
|
||||||
|
;*/
|
||||||
|
|
||||||
|
MODULE ?cstartup
|
||||||
|
|
||||||
|
;; Forward declaration of sections.
|
||||||
|
SECTION CSTACK:DATA:NOROOT(3)
|
||||||
|
|
||||||
|
SECTION .intvec:CODE:NOROOT(2)
|
||||||
|
|
||||||
|
EXTERN __iar_program_start
|
||||||
|
EXTERN SystemInit
|
||||||
|
PUBLIC __vector_table
|
||||||
|
|
||||||
|
DATA
|
||||||
|
__vector_table
|
||||||
|
DCD sfe(CSTACK) ; top of stack
|
||||||
|
DCD Reset_Handler ; Vector Number 1,Reset Handler
|
||||||
|
|
||||||
|
DCD NMI_Handler ; Vector Number 2,NMI Handler
|
||||||
|
DCD HardFault_Handler ; Vector Number 3,Hard Fault Handler
|
||||||
|
DCD MemManage_Handler ; Vector Number 4,MPU Fault Handler
|
||||||
|
DCD BusFault_Handler ; Vector Number 5,Bus Fault Handler
|
||||||
|
DCD UsageFault_Handler ; Vector Number 6,Usage Fault Handler
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD SVC_Handler ; Vector Number 11,SVCall Handler
|
||||||
|
DCD DebugMon_Handler ; Vector Number 12,Debug Monitor Handler
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD PendSV_Handler ; Vector Number 14,PendSV Handler
|
||||||
|
DCD SysTick_Handler ; Vector Number 15,SysTick Handler
|
||||||
|
|
||||||
|
; External Interrupts
|
||||||
|
DCD WWDGT_IRQHandler ; 16:Window Watchdog Timer
|
||||||
|
DCD LVD_IRQHandler ; 17:LVD through EXTI Line detect
|
||||||
|
DCD TAMPER_STAMP_IRQHandler ; 18:Tamper and TimeStamp through EXTI Line detect
|
||||||
|
DCD RTC_WKUP_IRQHandler ; 19:RTC Wakeup through EXTI Line
|
||||||
|
DCD FMC_IRQHandler ; 20:FMC
|
||||||
|
DCD RCU_CTC_IRQHandler ; 21:RCU and CTC
|
||||||
|
DCD EXTI0_IRQHandler ; 22:EXTI Line 0
|
||||||
|
DCD EXTI1_IRQHandler ; 23:EXTI Line 1
|
||||||
|
DCD EXTI2_IRQHandler ; 24:EXTI Line 2
|
||||||
|
DCD EXTI3_IRQHandler ; 25:EXTI Line 3
|
||||||
|
DCD EXTI4_IRQHandler ; 26:EXTI Line 4
|
||||||
|
DCD DMA0_Channel0_IRQHandler ; 27:DMA0 Channel0
|
||||||
|
DCD DMA0_Channel1_IRQHandler ; 28:DMA0 Channel1
|
||||||
|
DCD DMA0_Channel2_IRQHandler ; 29:DMA0 Channel2
|
||||||
|
DCD DMA0_Channel3_IRQHandler ; 30:DMA0 Channel3
|
||||||
|
DCD DMA0_Channel4_IRQHandler ; 31:DMA0 Channel4
|
||||||
|
DCD DMA0_Channel5_IRQHandler ; 32:DMA0 Channel5
|
||||||
|
DCD DMA0_Channel6_IRQHandler ; 33:DMA0 Channel6
|
||||||
|
DCD ADC_IRQHandler ; 34:ADC
|
||||||
|
DCD CAN0_TX_IRQHandler ; 35:CAN0 TX
|
||||||
|
DCD CAN0_RX0_IRQHandler ; 36:CAN0 RX0
|
||||||
|
DCD CAN0_RX1_IRQHandler ; 37:CAN0 RX1
|
||||||
|
DCD CAN0_EWMC_IRQHandler ; 38:CAN0 EWMC
|
||||||
|
DCD EXTI5_9_IRQHandler ; 39:EXTI5 to EXTI9
|
||||||
|
DCD TIMER0_BRK_TIMER8_IRQHandler ; 40:TIMER0 Break and TIMER8
|
||||||
|
DCD TIMER0_UP_TIMER9_IRQHandler ; 41:TIMER0 Update and TIMER9
|
||||||
|
DCD TIMER0_TRG_CMT_TIMER10_IRQHandler ; 42:TIMER0 Trigger and Commucation and TIMER10
|
||||||
|
DCD TIMER0_Channel_IRQHandler ; 43:TIMER0 Channel Capture Compare
|
||||||
|
DCD TIMER1_IRQHandler ; 44:TIMER1
|
||||||
|
DCD TIMER2_IRQHandler ; 45:TIMER2
|
||||||
|
DCD TIMER3_IRQHandler ; 46:TIMER3
|
||||||
|
DCD I2C0_EV_IRQHandler ; 47:I2C0 Event
|
||||||
|
DCD I2C0_ER_IRQHandler ; 48:I2C0 Error
|
||||||
|
DCD I2C1_EV_IRQHandler ; 49:I2C1 Event
|
||||||
|
DCD I2C1_ER_IRQHandler ; 50:I2C1 Error
|
||||||
|
DCD SPI0_IRQHandler ; 51:SPI0
|
||||||
|
DCD SPI1_IRQHandler ; 52:SPI1
|
||||||
|
DCD USART0_IRQHandler ; 53:USART0
|
||||||
|
DCD USART1_IRQHandler ; 54:USART1
|
||||||
|
DCD USART2_IRQHandler ; 55:USART2
|
||||||
|
DCD EXTI10_15_IRQHandler ; 56:EXTI10 to EXTI15
|
||||||
|
DCD RTC_Alarm_IRQHandler ; 57:RTC Alarm
|
||||||
|
DCD USBFS_WKUP_IRQHandler ; 58:USBFS Wakeup
|
||||||
|
DCD TIMER7_BRK_TIMER11_IRQHandler ; 59:TIMER7 Break and TIMER11
|
||||||
|
DCD TIMER7_UP_TIMER12_IRQHandler ; 60:TIMER7 Update and TIMER12
|
||||||
|
DCD TIMER7_TRG_CMT_TIMER13_IRQHandler ; 61:TIMER7 Trigger and Commucation and TIMER13
|
||||||
|
DCD TIMER7_Channel_IRQHandler ; 62:TIMER7 Channel Capture Compare
|
||||||
|
DCD DMA0_Channel7_IRQHandler ; 63:DMA0 Channel7
|
||||||
|
DCD EXMC_IRQHandler ; 64:EXMC
|
||||||
|
DCD SDIO_IRQHandler ; 65:SDIO
|
||||||
|
DCD TIMER4_IRQHandler ; 66:TIMER4
|
||||||
|
DCD SPI2_IRQHandler ; 67:SPI2
|
||||||
|
DCD UART3_IRQHandler ; 68:UART3
|
||||||
|
DCD UART4_IRQHandler ; 69:UART4
|
||||||
|
DCD TIMER5_DAC_IRQHandler ; 70:TIMER5 and DAC0 DAC1 Underrun error
|
||||||
|
DCD TIMER6_IRQHandler ; 71:TIMER6
|
||||||
|
DCD DMA1_Channel0_IRQHandler ; 72:DMA1 Channel0
|
||||||
|
DCD DMA1_Channel1_IRQHandler ; 73:DMA1 Channel1
|
||||||
|
DCD DMA1_Channel2_IRQHandler ; 74:DMA1 Channel2
|
||||||
|
DCD DMA1_Channel3_IRQHandler ; 75:DMA1 Channel3
|
||||||
|
DCD DMA1_Channel4_IRQHandler ; 76:DMA1 Channel4
|
||||||
|
DCD ENET_IRQHandler ; 77:Ethernet
|
||||||
|
DCD ENET_WKUP_IRQHandler ; 78:Ethernet Wakeup through EXTI Line
|
||||||
|
DCD CAN1_TX_IRQHandler ; 79:CAN1 TX
|
||||||
|
DCD CAN1_RX0_IRQHandler ; 80:CAN1 RX0
|
||||||
|
DCD CAN1_RX1_IRQHandler ; 81:CAN1 RX1
|
||||||
|
DCD CAN1_EWMC_IRQHandler ; 82:CAN1 EWMC
|
||||||
|
DCD USBFS_IRQHandler ; 83:USBFS
|
||||||
|
DCD DMA1_Channel5_IRQHandler ; 84:DMA1 Channel5
|
||||||
|
DCD DMA1_Channel6_IRQHandler ; 85:DMA1 Channel6
|
||||||
|
DCD DMA1_Channel7_IRQHandler ; 86:DMA1 Channel7
|
||||||
|
DCD USART5_IRQHandler ; 87:USART5
|
||||||
|
DCD I2C2_EV_IRQHandler ; 88:I2C2 Event
|
||||||
|
DCD I2C2_ER_IRQHandler ; 89:I2C2 Error
|
||||||
|
DCD USBHS_EP1_Out_IRQHandler ; 90:USBHS Endpoint 1 Out
|
||||||
|
DCD USBHS_EP1_In_IRQHandler ; 91:USBHS Endpoint 1 in
|
||||||
|
DCD USBHS_WKUP_IRQHandler ; 92:USBHS Wakeup through EXTI Line
|
||||||
|
DCD USBHS_IRQHandler ; 93:USBHS
|
||||||
|
DCD DCI_IRQHandler ; 94:DCI
|
||||||
|
DCD 0 ; 95:Reserved
|
||||||
|
DCD TRNG_IRQHandler ; 96:TRNG
|
||||||
|
DCD FPU_IRQHandler ; 97:FPU
|
||||||
|
DCD UART6_IRQHandler ; 98:UART6
|
||||||
|
DCD UART7_IRQHandler ; 99:UART7
|
||||||
|
DCD SPI3_IRQHandler ; 100:SPI3
|
||||||
|
DCD SPI4_IRQHandler ; 101:SPI4
|
||||||
|
DCD SPI5_IRQHandler ; 102:SPI5
|
||||||
|
DCD 0 ; 103:Reserved
|
||||||
|
DCD TLI_IRQHandler ; 104:TLI
|
||||||
|
DCD TLI_ER_IRQHandler ; 105:TLI Error
|
||||||
|
DCD IPA_IRQHandler ; 106:IPA
|
||||||
|
|
||||||
|
|
||||||
|
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||||
|
;;
|
||||||
|
;; Default interrupt handlers.
|
||||||
|
;;
|
||||||
|
THUMB
|
||||||
|
|
||||||
|
PUBWEAK Reset_Handler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(2)
|
||||||
|
Reset_Handler
|
||||||
|
LDR R0, =SystemInit
|
||||||
|
BLX R0
|
||||||
|
LDR R0, =__iar_program_start
|
||||||
|
BX R0
|
||||||
|
|
||||||
|
PUBWEAK NMI_Handler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
NMI_Handler
|
||||||
|
B NMI_Handler
|
||||||
|
|
||||||
|
PUBWEAK HardFault_Handler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
HardFault_Handler
|
||||||
|
B HardFault_Handler
|
||||||
|
|
||||||
|
PUBWEAK MemManage_Handler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
MemManage_Handler
|
||||||
|
B MemManage_Handler
|
||||||
|
|
||||||
|
PUBWEAK BusFault_Handler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
BusFault_Handler
|
||||||
|
B BusFault_Handler
|
||||||
|
|
||||||
|
PUBWEAK UsageFault_Handler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
UsageFault_Handler
|
||||||
|
B UsageFault_Handler
|
||||||
|
|
||||||
|
PUBWEAK SVC_Handler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
SVC_Handler
|
||||||
|
B SVC_Handler
|
||||||
|
|
||||||
|
PUBWEAK DebugMon_Handler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
DebugMon_Handler
|
||||||
|
B DebugMon_Handler
|
||||||
|
|
||||||
|
PUBWEAK PendSV_Handler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
PendSV_Handler
|
||||||
|
B PendSV_Handler
|
||||||
|
|
||||||
|
PUBWEAK SysTick_Handler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
SysTick_Handler
|
||||||
|
B SysTick_Handler
|
||||||
|
|
||||||
|
PUBWEAK WWDGT_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
WWDGT_IRQHandler
|
||||||
|
B WWDGT_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK LVD_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
LVD_IRQHandler
|
||||||
|
B LVD_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK TAMPER_STAMP_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
TAMPER_STAMP_IRQHandler
|
||||||
|
B TAMPER_STAMP_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK RTC_WKUP_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
RTC_WKUP_IRQHandler
|
||||||
|
B RTC_WKUP_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK FMC_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
FMC_IRQHandler
|
||||||
|
B FMC_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK RCU_CTC_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
RCU_CTC_IRQHandler
|
||||||
|
B RCU_CTC_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK EXTI0_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
EXTI0_IRQHandler
|
||||||
|
B EXTI0_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK EXTI1_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
EXTI1_IRQHandler
|
||||||
|
B EXTI1_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK EXTI2_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
EXTI2_IRQHandler
|
||||||
|
B EXTI2_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK EXTI3_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
EXTI3_IRQHandler
|
||||||
|
B EXTI3_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK EXTI4_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
EXTI4_IRQHandler
|
||||||
|
B EXTI4_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA0_Channel0_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
DMA0_Channel0_IRQHandler
|
||||||
|
B DMA0_Channel0_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA0_Channel1_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
DMA0_Channel1_IRQHandler
|
||||||
|
B DMA0_Channel1_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA0_Channel2_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
DMA0_Channel2_IRQHandler
|
||||||
|
B DMA0_Channel2_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA0_Channel3_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
DMA0_Channel3_IRQHandler
|
||||||
|
B DMA0_Channel3_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA0_Channel4_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
DMA0_Channel4_IRQHandler
|
||||||
|
B DMA0_Channel4_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA0_Channel5_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
DMA0_Channel5_IRQHandler
|
||||||
|
B DMA0_Channel5_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA0_Channel6_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
DMA0_Channel6_IRQHandler
|
||||||
|
B DMA0_Channel6_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK ADC_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
ADC_IRQHandler
|
||||||
|
B ADC_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK CAN0_TX_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
CAN0_TX_IRQHandler
|
||||||
|
B CAN0_TX_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK CAN0_RX0_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
CAN0_RX0_IRQHandler
|
||||||
|
B CAN0_RX0_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK CAN0_RX1_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
CAN0_RX1_IRQHandler
|
||||||
|
B CAN0_RX1_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK CAN0_EWMC_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
CAN0_EWMC_IRQHandler
|
||||||
|
B CAN0_EWMC_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK EXTI5_9_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
EXTI5_9_IRQHandler
|
||||||
|
B EXTI5_9_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK TIMER0_BRK_TIMER8_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
TIMER0_BRK_TIMER8_IRQHandler
|
||||||
|
B TIMER0_BRK_TIMER8_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK TIMER0_UP_TIMER9_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
TIMER0_UP_TIMER9_IRQHandler
|
||||||
|
B TIMER0_UP_TIMER9_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK TIMER0_TRG_CMT_TIMER10_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
TIMER0_TRG_CMT_TIMER10_IRQHandler
|
||||||
|
B TIMER0_TRG_CMT_TIMER10_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK TIMER0_Channel_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
TIMER0_Channel_IRQHandler
|
||||||
|
B TIMER0_Channel_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK TIMER1_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
TIMER1_IRQHandler
|
||||||
|
B TIMER1_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK TIMER2_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
TIMER2_IRQHandler
|
||||||
|
B TIMER2_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK TIMER3_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
TIMER3_IRQHandler
|
||||||
|
B TIMER3_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK I2C0_EV_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
I2C0_EV_IRQHandler
|
||||||
|
B I2C0_EV_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK I2C0_ER_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
I2C0_ER_IRQHandler
|
||||||
|
B I2C0_ER_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK I2C1_EV_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
I2C1_EV_IRQHandler
|
||||||
|
B I2C1_EV_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK I2C1_ER_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
I2C1_ER_IRQHandler
|
||||||
|
B I2C1_ER_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK SPI0_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
SPI0_IRQHandler
|
||||||
|
B SPI0_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK SPI1_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
SPI1_IRQHandler
|
||||||
|
B SPI1_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK USART0_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
USART0_IRQHandler
|
||||||
|
B USART0_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK USART1_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
USART1_IRQHandler
|
||||||
|
B USART1_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK USART2_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
USART2_IRQHandler
|
||||||
|
B USART2_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK EXTI10_15_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
EXTI10_15_IRQHandler
|
||||||
|
B EXTI10_15_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK RTC_Alarm_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
RTC_Alarm_IRQHandler
|
||||||
|
B RTC_Alarm_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK USBFS_WKUP_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
USBFS_WKUP_IRQHandler
|
||||||
|
B USBFS_WKUP_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK TIMER7_BRK_TIMER11_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
TIMER7_BRK_TIMER11_IRQHandler
|
||||||
|
B TIMER7_BRK_TIMER11_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK TIMER7_UP_TIMER12_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
TIMER7_UP_TIMER12_IRQHandler
|
||||||
|
B TIMER7_UP_TIMER12_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK TIMER7_TRG_CMT_TIMER13_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
TIMER7_TRG_CMT_TIMER13_IRQHandler
|
||||||
|
B TIMER7_TRG_CMT_TIMER13_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK TIMER7_Channel_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
TIMER7_Channel_IRQHandler
|
||||||
|
B TIMER7_Channel_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA0_Channel7_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
DMA0_Channel7_IRQHandler
|
||||||
|
B DMA0_Channel7_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK EXMC_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
EXMC_IRQHandler
|
||||||
|
B EXMC_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK SDIO_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
SDIO_IRQHandler
|
||||||
|
B SDIO_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK TIMER4_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
TIMER4_IRQHandler
|
||||||
|
B TIMER4_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK SPI2_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
SPI2_IRQHandler
|
||||||
|
B SPI2_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK UART3_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
UART3_IRQHandler
|
||||||
|
B UART3_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK UART4_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
UART4_IRQHandler
|
||||||
|
B UART4_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK TIMER5_DAC_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
TIMER5_DAC_IRQHandler
|
||||||
|
B TIMER5_DAC_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK TIMER6_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
TIMER6_IRQHandler
|
||||||
|
B TIMER6_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA1_Channel0_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
DMA1_Channel0_IRQHandler
|
||||||
|
B DMA1_Channel0_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA1_Channel1_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
DMA1_Channel1_IRQHandler
|
||||||
|
B DMA1_Channel1_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA1_Channel2_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
DMA1_Channel2_IRQHandler
|
||||||
|
B DMA1_Channel2_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA1_Channel3_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
DMA1_Channel3_IRQHandler
|
||||||
|
B DMA1_Channel3_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA1_Channel4_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
DMA1_Channel4_IRQHandler
|
||||||
|
B DMA1_Channel4_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK ENET_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
ENET_IRQHandler
|
||||||
|
B ENET_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK ENET_WKUP_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
ENET_WKUP_IRQHandler
|
||||||
|
B ENET_WKUP_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK CAN1_TX_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
CAN1_TX_IRQHandler
|
||||||
|
B CAN1_TX_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK CAN1_RX0_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
CAN1_RX0_IRQHandler
|
||||||
|
B CAN1_RX0_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK CAN1_RX1_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
CAN1_RX1_IRQHandler
|
||||||
|
B CAN1_RX1_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK CAN1_EWMC_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
CAN1_EWMC_IRQHandler
|
||||||
|
B CAN1_EWMC_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK USBFS_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
USBFS_IRQHandler
|
||||||
|
B USBFS_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA1_Channel5_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
DMA1_Channel5_IRQHandler
|
||||||
|
B DMA1_Channel5_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA1_Channel6_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
DMA1_Channel6_IRQHandler
|
||||||
|
B DMA1_Channel6_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA1_Channel7_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
DMA1_Channel7_IRQHandler
|
||||||
|
B DMA1_Channel7_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK USART5_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
USART5_IRQHandler
|
||||||
|
B USART5_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK I2C2_EV_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
I2C2_EV_IRQHandler
|
||||||
|
B I2C2_EV_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK I2C2_ER_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
I2C2_ER_IRQHandler
|
||||||
|
B I2C2_ER_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK USBHS_EP1_Out_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
USBHS_EP1_Out_IRQHandler
|
||||||
|
B USBHS_EP1_Out_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK USBHS_EP1_In_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
USBHS_EP1_In_IRQHandler
|
||||||
|
B USBHS_EP1_In_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK USBHS_WKUP_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
USBHS_WKUP_IRQHandler
|
||||||
|
B USBHS_WKUP_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK USBHS_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
USBHS_IRQHandler
|
||||||
|
B USBHS_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DCI_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
DCI_IRQHandler
|
||||||
|
B DCI_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK TRNG_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
TRNG_IRQHandler
|
||||||
|
B TRNG_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK FPU_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
FPU_IRQHandler
|
||||||
|
B FPU_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK UART6_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
UART6_IRQHandler
|
||||||
|
B UART6_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK UART7_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
UART7_IRQHandler
|
||||||
|
B UART7_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK SPI3_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
SPI3_IRQHandler
|
||||||
|
B SPI3_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK SPI4_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
SPI4_IRQHandler
|
||||||
|
B SPI4_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK SPI5_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
SPI5_IRQHandler
|
||||||
|
B SPI5_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK TLI_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
TLI_IRQHandler
|
||||||
|
B TLI_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK TLI_ER_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
TLI_ER_IRQHandler
|
||||||
|
B TLI_ER_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK IPA_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
IPA_IRQHandler
|
||||||
|
B IPA_IRQHandler
|
||||||
|
END
|
||||||
|
|
@ -52,13 +52,25 @@
|
||||||
//#define __SYSTEM_CLOCK_200M_PLL_IRC16M (uint32_t)(200000000)
|
//#define __SYSTEM_CLOCK_200M_PLL_IRC16M (uint32_t)(200000000)
|
||||||
//#define __SYSTEM_CLOCK_200M_PLL_8M_HXTAL (uint32_t)(200000000)
|
//#define __SYSTEM_CLOCK_200M_PLL_8M_HXTAL (uint32_t)(200000000)
|
||||||
#define __SYSTEM_CLOCK_200M_PLL_25M_HXTAL (uint32_t)(200000000)
|
#define __SYSTEM_CLOCK_200M_PLL_25M_HXTAL (uint32_t)(200000000)
|
||||||
|
//#define __SYSTEM_CLOCK_240M_PLL_IRC16M (uint32_t)(240000000)
|
||||||
|
//#define __SYSTEM_CLOCK_240M_PLL_8M_HXTAL (uint32_t)(240000000)
|
||||||
|
//#define __SYSTEM_CLOCK_240M_PLL_25M_HXTAL (uint32_t)(240000000)
|
||||||
|
|
||||||
|
#define RCU_MODIFY(__delay) do{ \
|
||||||
|
volatile uint32_t i; \
|
||||||
|
if(0 != __delay){ \
|
||||||
|
RCU_CFG0 |= RCU_AHB_CKSYS_DIV2; \
|
||||||
|
for(i=0; i<__delay; i++){ \
|
||||||
|
} \
|
||||||
|
RCU_CFG0 |= RCU_AHB_CKSYS_DIV4; \
|
||||||
|
for(i=0; i<__delay; i++){ \
|
||||||
|
} \
|
||||||
|
} \
|
||||||
|
}while(0)
|
||||||
|
|
||||||
#define SEL_IRC16M 0x00U
|
#define SEL_IRC16M 0x00U
|
||||||
#define SEL_HXTAL 0x01U
|
#define SEL_HXTAL 0x01U
|
||||||
#define SEL_PLLP 0x02U
|
#define SEL_PLLP 0x02U
|
||||||
#define RCU_MODIFY {volatile uint32_t i; \
|
|
||||||
RCU_CFG0 |= RCU_AHB_CKSYS_DIV2; \
|
|
||||||
for(i=0;i<50000;i++);}
|
|
||||||
|
|
||||||
/* set the system clock frequency and declare the system clock configuration function */
|
/* set the system clock frequency and declare the system clock configuration function */
|
||||||
#ifdef __SYSTEM_CLOCK_IRC16M
|
#ifdef __SYSTEM_CLOCK_IRC16M
|
||||||
|
|
@ -94,6 +106,15 @@ static void system_clock_200m_8m_hxtal(void);
|
||||||
#elif defined (__SYSTEM_CLOCK_200M_PLL_25M_HXTAL)
|
#elif defined (__SYSTEM_CLOCK_200M_PLL_25M_HXTAL)
|
||||||
uint32_t SystemCoreClock = __SYSTEM_CLOCK_200M_PLL_25M_HXTAL;
|
uint32_t SystemCoreClock = __SYSTEM_CLOCK_200M_PLL_25M_HXTAL;
|
||||||
static void system_clock_200m_25m_hxtal(void);
|
static void system_clock_200m_25m_hxtal(void);
|
||||||
|
#elif defined (__SYSTEM_CLOCK_240M_PLL_IRC16M)
|
||||||
|
uint32_t SystemCoreClock = __SYSTEM_CLOCK_240M_PLL_IRC16M;
|
||||||
|
static void system_clock_240m_irc16m(void);
|
||||||
|
#elif defined (__SYSTEM_CLOCK_240M_PLL_8M_HXTAL)
|
||||||
|
uint32_t SystemCoreClock = __SYSTEM_CLOCK_240M_PLL_8M_HXTAL;
|
||||||
|
static void system_clock_240m_8m_hxtal(void);
|
||||||
|
#elif defined (__SYSTEM_CLOCK_240M_PLL_25M_HXTAL)
|
||||||
|
uint32_t SystemCoreClock = __SYSTEM_CLOCK_240M_PLL_25M_HXTAL;
|
||||||
|
static void system_clock_240m_25m_hxtal(void);
|
||||||
|
|
||||||
#endif /* __SYSTEM_CLOCK_IRC16M */
|
#endif /* __SYSTEM_CLOCK_IRC16M */
|
||||||
|
|
||||||
|
|
@ -108,33 +129,40 @@ static void system_clock_config(void);
|
||||||
*/
|
*/
|
||||||
void SystemInit (void)
|
void SystemInit (void)
|
||||||
{
|
{
|
||||||
/* FPU settings ------------------------------------------------------------*/
|
/* FPU settings */
|
||||||
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
|
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
|
||||||
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
|
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
|
||||||
#endif
|
#endif
|
||||||
/* Reset the RCU clock configuration to the default reset state ------------*/
|
/* Reset the RCU clock configuration to the default reset state */
|
||||||
/* Set IRC16MEN bit */
|
/* Set IRC16MEN bit */
|
||||||
RCU_CTL |= RCU_CTL_IRC16MEN;
|
RCU_CTL |= RCU_CTL_IRC16MEN;
|
||||||
|
while(0U == (RCU_CTL & RCU_CTL_IRC16MSTB)){
|
||||||
|
}
|
||||||
|
RCU_MODIFY(0x50);
|
||||||
|
|
||||||
RCU_MODIFY
|
RCU_CFG0 &= ~RCU_CFG0_SCS;
|
||||||
|
|
||||||
/* Reset CFG0 register */
|
|
||||||
RCU_CFG0 = 0x00000000U;
|
|
||||||
|
|
||||||
/* Reset HXTALEN, CKMEN and PLLEN bits */
|
/* Reset HXTALEN, CKMEN and PLLEN bits */
|
||||||
RCU_CTL &= ~(RCU_CTL_PLLEN | RCU_CTL_CKMEN | RCU_CTL_HXTALEN);
|
RCU_CTL &= ~(RCU_CTL_PLLEN | RCU_CTL_CKMEN | RCU_CTL_HXTALEN);
|
||||||
|
|
||||||
/* Reset PLLCFGR register */
|
|
||||||
RCU_PLL = 0x24003010U;
|
|
||||||
|
|
||||||
/* Reset HSEBYP bit */
|
/* Reset HSEBYP bit */
|
||||||
RCU_CTL &= ~(RCU_CTL_HXTALBPS);
|
RCU_CTL &= ~(RCU_CTL_HXTALBPS);
|
||||||
|
|
||||||
|
/* Reset CFG0 register */
|
||||||
|
RCU_CFG0 = 0x00000000U;
|
||||||
|
|
||||||
|
/* wait until IRC16M is selected as system clock */
|
||||||
|
while(0 != (RCU_CFG0 & RCU_SCSS_IRC16M)){
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Reset PLLCFGR register */
|
||||||
|
RCU_PLL = 0x24003010U;
|
||||||
|
|
||||||
/* Disable all interrupts */
|
/* Disable all interrupts */
|
||||||
RCU_INT = 0x00000000U;
|
RCU_INT = 0x00000000U;
|
||||||
|
|
||||||
/* Configure the System clock source, PLL Multiplier and Divider factors,
|
/* Configure the System clock source, PLL Multiplier and Divider factors,
|
||||||
AHB/APBx prescalers and Flash settings ----------------------------------*/
|
AHB/APBx prescalers and Flash settings */
|
||||||
system_clock_config();
|
system_clock_config();
|
||||||
}
|
}
|
||||||
/*!
|
/*!
|
||||||
|
|
@ -167,6 +195,12 @@ static void system_clock_config(void)
|
||||||
system_clock_200m_8m_hxtal();
|
system_clock_200m_8m_hxtal();
|
||||||
#elif defined (__SYSTEM_CLOCK_200M_PLL_25M_HXTAL)
|
#elif defined (__SYSTEM_CLOCK_200M_PLL_25M_HXTAL)
|
||||||
system_clock_200m_25m_hxtal();
|
system_clock_200m_25m_hxtal();
|
||||||
|
#elif defined (__SYSTEM_CLOCK_240M_PLL_IRC16M)
|
||||||
|
system_clock_240m_irc16m();
|
||||||
|
#elif defined (__SYSTEM_CLOCK_240M_PLL_8M_HXTAL)
|
||||||
|
system_clock_240m_8m_hxtal();
|
||||||
|
#elif defined (__SYSTEM_CLOCK_240M_PLL_25M_HXTAL)
|
||||||
|
system_clock_240m_25m_hxtal();
|
||||||
#endif /* __SYSTEM_CLOCK_IRC16M */
|
#endif /* __SYSTEM_CLOCK_IRC16M */
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
@ -864,6 +898,209 @@ static void system_clock_200m_25m_hxtal(void)
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
#elif defined (__SYSTEM_CLOCK_240M_PLL_IRC16M)
|
||||||
|
/*!
|
||||||
|
\brief configure the system clock to 240M by PLL which selects IRC16M as its clock source
|
||||||
|
\param[in] none
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
static void system_clock_240m_irc16m(void)
|
||||||
|
{
|
||||||
|
uint32_t timeout = 0U;
|
||||||
|
uint32_t stab_flag = 0U;
|
||||||
|
|
||||||
|
/* enable IRC16M */
|
||||||
|
RCU_CTL |= RCU_CTL_IRC16MEN;
|
||||||
|
|
||||||
|
/* wait until IRC16M is stable or the startup time is longer than IRC16M_STARTUP_TIMEOUT */
|
||||||
|
do{
|
||||||
|
timeout++;
|
||||||
|
stab_flag = (RCU_CTL & RCU_CTL_IRC16MSTB);
|
||||||
|
}while((0U == stab_flag) && (IRC16M_STARTUP_TIMEOUT != timeout));
|
||||||
|
|
||||||
|
/* if fail */
|
||||||
|
if(0U == (RCU_CTL & RCU_CTL_IRC16MSTB)){
|
||||||
|
while(1){
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
RCU_APB1EN |= RCU_APB1EN_PMUEN;
|
||||||
|
PMU_CTL |= PMU_CTL_LDOVS;
|
||||||
|
|
||||||
|
/* IRC16M is stable */
|
||||||
|
/* AHB = SYSCLK */
|
||||||
|
RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
|
||||||
|
/* APB2 = AHB/2 */
|
||||||
|
RCU_CFG0 |= RCU_APB2_CKAHB_DIV2;
|
||||||
|
/* APB1 = AHB/4 */
|
||||||
|
RCU_CFG0 |= RCU_APB1_CKAHB_DIV4;
|
||||||
|
|
||||||
|
/* Configure the main PLL, PSC = 16, PLL_N = 480, PLL_P = 2, PLL_Q = 10 */
|
||||||
|
RCU_PLL = (16U | (480U << 6U) | (((2U >> 1U) - 1U) << 16U) |
|
||||||
|
(RCU_PLLSRC_IRC16M) | (10U << 24U));
|
||||||
|
|
||||||
|
/* enable PLL */
|
||||||
|
RCU_CTL |= RCU_CTL_PLLEN;
|
||||||
|
|
||||||
|
/* wait until PLL is stable */
|
||||||
|
while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Enable the high-drive to extend the clock frequency to 240 Mhz */
|
||||||
|
PMU_CTL |= PMU_CTL_HDEN;
|
||||||
|
while(0U == (PMU_CS & PMU_CS_HDRF)){
|
||||||
|
}
|
||||||
|
|
||||||
|
/* select the high-drive mode */
|
||||||
|
PMU_CTL |= PMU_CTL_HDS;
|
||||||
|
while(0U == (PMU_CS & PMU_CS_HDSRF)){
|
||||||
|
}
|
||||||
|
|
||||||
|
/* select PLL as system clock */
|
||||||
|
RCU_CFG0 &= ~RCU_CFG0_SCS;
|
||||||
|
RCU_CFG0 |= RCU_CKSYSSRC_PLLP;
|
||||||
|
|
||||||
|
/* wait until PLL is selected as system clock */
|
||||||
|
while(0U == (RCU_CFG0 & RCU_SCSS_PLLP)){
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
#elif defined (__SYSTEM_CLOCK_240M_PLL_8M_HXTAL)
|
||||||
|
/*!
|
||||||
|
\brief configure the system clock to 240M by PLL which selects HXTAL(8M) as its clock source
|
||||||
|
\param[in] none
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
static void system_clock_240m_8m_hxtal(void)
|
||||||
|
{
|
||||||
|
uint32_t timeout = 0U;
|
||||||
|
uint32_t stab_flag = 0U;
|
||||||
|
|
||||||
|
/* enable HXTAL */
|
||||||
|
RCU_CTL |= RCU_CTL_HXTALEN;
|
||||||
|
|
||||||
|
/* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */
|
||||||
|
do{
|
||||||
|
timeout++;
|
||||||
|
stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB);
|
||||||
|
}while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));
|
||||||
|
|
||||||
|
/* if fail */
|
||||||
|
if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){
|
||||||
|
while(1){
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
RCU_APB1EN |= RCU_APB1EN_PMUEN;
|
||||||
|
PMU_CTL |= PMU_CTL_LDOVS;
|
||||||
|
|
||||||
|
/* HXTAL is stable */
|
||||||
|
/* AHB = SYSCLK */
|
||||||
|
RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
|
||||||
|
/* APB2 = AHB/2 */
|
||||||
|
RCU_CFG0 |= RCU_APB2_CKAHB_DIV2;
|
||||||
|
/* APB1 = AHB/4 */
|
||||||
|
RCU_CFG0 |= RCU_APB1_CKAHB_DIV4;
|
||||||
|
|
||||||
|
/* Configure the main PLL, PSC = 8, PLL_N = 480, PLL_P = 2, PLL_Q = 10 */
|
||||||
|
RCU_PLL = (8U | (480U << 6U) | (((2U >> 1U) - 1U) << 16U) |
|
||||||
|
(RCU_PLLSRC_HXTAL) | (10U << 24U));
|
||||||
|
|
||||||
|
/* enable PLL */
|
||||||
|
RCU_CTL |= RCU_CTL_PLLEN;
|
||||||
|
|
||||||
|
/* wait until PLL is stable */
|
||||||
|
while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Enable the high-drive to extend the clock frequency to 240 Mhz */
|
||||||
|
PMU_CTL |= PMU_CTL_HDEN;
|
||||||
|
while(0U == (PMU_CS & PMU_CS_HDRF)){
|
||||||
|
}
|
||||||
|
|
||||||
|
/* select the high-drive mode */
|
||||||
|
PMU_CTL |= PMU_CTL_HDS;
|
||||||
|
while(0U == (PMU_CS & PMU_CS_HDSRF)){
|
||||||
|
}
|
||||||
|
|
||||||
|
/* select PLL as system clock */
|
||||||
|
RCU_CFG0 &= ~RCU_CFG0_SCS;
|
||||||
|
RCU_CFG0 |= RCU_CKSYSSRC_PLLP;
|
||||||
|
|
||||||
|
/* wait until PLL is selected as system clock */
|
||||||
|
while(0U == (RCU_CFG0 & RCU_SCSS_PLLP)){
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
#elif defined (__SYSTEM_CLOCK_240M_PLL_25M_HXTAL)
|
||||||
|
/*!
|
||||||
|
\brief configure the system clock to 240M by PLL which selects HXTAL(25M) as its clock source
|
||||||
|
\param[in] none
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
static void system_clock_240m_25m_hxtal(void)
|
||||||
|
{
|
||||||
|
uint32_t timeout = 0U;
|
||||||
|
uint32_t stab_flag = 0U;
|
||||||
|
|
||||||
|
/* enable HXTAL */
|
||||||
|
RCU_CTL |= RCU_CTL_HXTALEN;
|
||||||
|
|
||||||
|
/* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */
|
||||||
|
do{
|
||||||
|
timeout++;
|
||||||
|
stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB);
|
||||||
|
}while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));
|
||||||
|
|
||||||
|
/* if fail */
|
||||||
|
if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){
|
||||||
|
while(1){
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
RCU_APB1EN |= RCU_APB1EN_PMUEN;
|
||||||
|
PMU_CTL |= PMU_CTL_LDOVS;
|
||||||
|
|
||||||
|
/* HXTAL is stable */
|
||||||
|
/* AHB = SYSCLK */
|
||||||
|
RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
|
||||||
|
/* APB2 = AHB/2 */
|
||||||
|
RCU_CFG0 |= RCU_APB2_CKAHB_DIV2;
|
||||||
|
/* APB1 = AHB/4 */
|
||||||
|
RCU_CFG0 |= RCU_APB1_CKAHB_DIV4;
|
||||||
|
|
||||||
|
/* Configure the main PLL, PSC = 25, PLL_N = 480, PLL_P = 2, PLL_Q = 10 */
|
||||||
|
RCU_PLL = (25U | (480U << 6U) | (((2U >> 1U) - 1U) << 16U) |
|
||||||
|
(RCU_PLLSRC_HXTAL) | (10U << 24U));
|
||||||
|
|
||||||
|
/* enable PLL */
|
||||||
|
RCU_CTL |= RCU_CTL_PLLEN;
|
||||||
|
|
||||||
|
/* wait until PLL is stable */
|
||||||
|
while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Enable the high-drive to extend the clock frequency to 240 Mhz */
|
||||||
|
PMU_CTL |= PMU_CTL_HDEN;
|
||||||
|
while(0U == (PMU_CS & PMU_CS_HDRF)){
|
||||||
|
}
|
||||||
|
|
||||||
|
/* select the high-drive mode */
|
||||||
|
PMU_CTL |= PMU_CTL_HDS;
|
||||||
|
while(0U == (PMU_CS & PMU_CS_HDSRF)){
|
||||||
|
}
|
||||||
|
|
||||||
|
/* select PLL as system clock */
|
||||||
|
RCU_CFG0 &= ~RCU_CFG0_SCS;
|
||||||
|
RCU_CFG0 |= RCU_CKSYSSRC_PLLP;
|
||||||
|
|
||||||
|
/* wait until PLL is selected as system clock */
|
||||||
|
while(0U == (RCU_CFG0 & RCU_SCSS_PLLP)){
|
||||||
|
}
|
||||||
|
}
|
||||||
#endif /* __SYSTEM_CLOCK_IRC16M */
|
#endif /* __SYSTEM_CLOCK_IRC16M */
|
||||||
/*!
|
/*!
|
||||||
\brief update the SystemCoreClock with current core clock retrieved from cpu registers
|
\brief update the SystemCoreClock with current core clock retrieved from cpu registers
|
||||||
|
|
|
||||||
|
|
@ -1,39 +1,25 @@
|
||||||
/**************************************************************************//**
|
/**************************************************************************//**
|
||||||
* @file core_cmFunc.h
|
* @file core_cmFunc.h
|
||||||
* @brief CMSIS Cortex-M Core Function Access Header File
|
* @brief CMSIS Cortex-M Core Function Access Header File
|
||||||
* @version V4.10
|
* @version V3.01
|
||||||
* @date 18. March 2015
|
* @date 06. March 2012
|
||||||
*
|
*
|
||||||
* @note
|
* @note
|
||||||
|
* Copyright (C) 2009-2012 ARM Limited. All rights reserved.
|
||||||
|
*
|
||||||
|
* @par
|
||||||
|
* ARM Limited (ARM) is supplying this software for use with Cortex-M
|
||||||
|
* processor based microcontrollers. This file can be freely distributed
|
||||||
|
* within development tools that are supporting such ARM based processors.
|
||||||
|
*
|
||||||
|
* @par
|
||||||
|
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||||
|
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||||
|
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||||
|
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||||
|
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||||
*
|
*
|
||||||
******************************************************************************/
|
******************************************************************************/
|
||||||
/* Copyright (c) 2009 - 2015 ARM LIMITED
|
|
||||||
|
|
||||||
All rights reserved.
|
|
||||||
Redistribution and use in source and binary forms, with or without
|
|
||||||
modification, are permitted provided that the following conditions are met:
|
|
||||||
- Redistributions of source code must retain the above copyright
|
|
||||||
notice, this list of conditions and the following disclaimer.
|
|
||||||
- Redistributions in binary form must reproduce the above copyright
|
|
||||||
notice, this list of conditions and the following disclaimer in the
|
|
||||||
documentation and/or other materials provided with the distribution.
|
|
||||||
- Neither the name of ARM nor the names of its contributors may be used
|
|
||||||
to endorse or promote products derived from this software without
|
|
||||||
specific prior written permission.
|
|
||||||
*
|
|
||||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
|
||||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
|
||||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
|
||||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
|
||||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
|
||||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
|
||||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
|
||||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
|
||||||
POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
---------------------------------------------------------------------------*/
|
|
||||||
|
|
||||||
|
|
||||||
#ifndef __CORE_CMFUNC_H
|
#ifndef __CORE_CMFUNC_H
|
||||||
#define __CORE_CMFUNC_H
|
#define __CORE_CMFUNC_H
|
||||||
|
|
@ -198,7 +184,7 @@ __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
|
#if (__CORTEX_M >= 0x03)
|
||||||
|
|
||||||
/** \brief Enable FIQ
|
/** \brief Enable FIQ
|
||||||
|
|
||||||
|
|
@ -242,20 +228,6 @@ __STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
/** \brief Set Base Priority with condition
|
|
||||||
|
|
||||||
This function assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
|
|
||||||
or the new value increases the BASEPRI priority level.
|
|
||||||
|
|
||||||
\param [in] basePri Base Priority value to set
|
|
||||||
*/
|
|
||||||
__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
|
|
||||||
{
|
|
||||||
register uint32_t __regBasePriMax __ASM("basepri_max");
|
|
||||||
__regBasePriMax = (basePri & 0xff);
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
/** \brief Get Fault Mask
|
/** \brief Get Fault Mask
|
||||||
|
|
||||||
This function returns the current value of the Fault Mask register.
|
This function returns the current value of the Fault Mask register.
|
||||||
|
|
@ -281,10 +253,10 @@ __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
|
||||||
__regFaultMask = (faultMask & (uint32_t)1);
|
__regFaultMask = (faultMask & (uint32_t)1);
|
||||||
}
|
}
|
||||||
|
|
||||||
#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
|
#endif /* (__CORTEX_M >= 0x03) */
|
||||||
|
|
||||||
|
|
||||||
#if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
|
#if (__CORTEX_M == 0x04)
|
||||||
|
|
||||||
/** \brief Get FPSCR
|
/** \brief Get FPSCR
|
||||||
|
|
||||||
|
|
@ -317,7 +289,19 @@ __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
|
||||||
#endif
|
#endif
|
||||||
}
|
}
|
||||||
|
|
||||||
#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
|
#endif /* (__CORTEX_M == 0x04) */
|
||||||
|
|
||||||
|
|
||||||
|
#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
|
||||||
|
/* IAR iccarm specific functions */
|
||||||
|
|
||||||
|
#include <cmsis_iar.h>
|
||||||
|
|
||||||
|
|
||||||
|
#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
|
||||||
|
/* TI CCS specific functions */
|
||||||
|
|
||||||
|
#include <cmsis_ccs.h>
|
||||||
|
|
||||||
|
|
||||||
#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
|
#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
|
||||||
|
|
@ -330,7 +314,7 @@ __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
|
||||||
*/
|
*/
|
||||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
|
__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
|
||||||
{
|
{
|
||||||
__ASM volatile ("cpsie i" : : : "memory");
|
__ASM volatile ("cpsie i");
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
|
|
@ -341,7 +325,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
|
||||||
*/
|
*/
|
||||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
|
__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
|
||||||
{
|
{
|
||||||
__ASM volatile ("cpsid i" : : : "memory");
|
__ASM volatile ("cpsid i");
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
|
|
@ -368,7 +352,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
|
||||||
*/
|
*/
|
||||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
|
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
|
||||||
{
|
{
|
||||||
__ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
|
__ASM volatile ("MSR control, %0" : : "r" (control) );
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
|
|
@ -440,7 +424,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
|
||||||
*/
|
*/
|
||||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
|
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
|
||||||
{
|
{
|
||||||
__ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
|
__ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) );
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
|
|
@ -467,7 +451,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
|
||||||
*/
|
*/
|
||||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
|
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
|
||||||
{
|
{
|
||||||
__ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
|
__ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) );
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
|
|
@ -494,7 +478,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
|
||||||
*/
|
*/
|
||||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
|
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
|
||||||
{
|
{
|
||||||
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
|
__ASM volatile ("MSR primask, %0" : : "r" (priMask) );
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
|
|
@ -507,7 +491,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t p
|
||||||
*/
|
*/
|
||||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
|
__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
|
||||||
{
|
{
|
||||||
__ASM volatile ("cpsie f" : : : "memory");
|
__ASM volatile ("cpsie f");
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
|
|
@ -518,7 +502,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
|
||||||
*/
|
*/
|
||||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
|
__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
|
||||||
{
|
{
|
||||||
__ASM volatile ("cpsid f" : : : "memory");
|
__ASM volatile ("cpsid f");
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
|
|
@ -532,7 +516,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
|
||||||
{
|
{
|
||||||
uint32_t result;
|
uint32_t result;
|
||||||
|
|
||||||
__ASM volatile ("MRS %0, basepri" : "=r" (result) );
|
__ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
|
||||||
return(result);
|
return(result);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
@ -545,20 +529,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
|
||||||
*/
|
*/
|
||||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
|
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
|
||||||
{
|
{
|
||||||
__ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
|
__ASM volatile ("MSR basepri, %0" : : "r" (value) );
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
/** \brief Set Base Priority with condition
|
|
||||||
|
|
||||||
This function assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
|
|
||||||
or the new value increases the BASEPRI priority level.
|
|
||||||
|
|
||||||
\param [in] basePri Base Priority value to set
|
|
||||||
*/
|
|
||||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value)
|
|
||||||
{
|
|
||||||
__ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory");
|
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
|
|
@ -585,13 +556,13 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void
|
||||||
*/
|
*/
|
||||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
|
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
|
||||||
{
|
{
|
||||||
__ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
|
__ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );
|
||||||
}
|
}
|
||||||
|
|
||||||
#endif /* (__CORTEX_M >= 0x03) */
|
#endif /* (__CORTEX_M >= 0x03) */
|
||||||
|
|
||||||
|
|
||||||
#if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
|
#if (__CORTEX_M == 0x04)
|
||||||
|
|
||||||
/** \brief Get FPSCR
|
/** \brief Get FPSCR
|
||||||
|
|
||||||
|
|
@ -604,10 +575,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
|
||||||
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
|
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
|
||||||
uint32_t result;
|
uint32_t result;
|
||||||
|
|
||||||
/* Empty asm statement works as a scheduling barrier */
|
|
||||||
__ASM volatile ("");
|
|
||||||
__ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
|
__ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
|
||||||
__ASM volatile ("");
|
|
||||||
return(result);
|
return(result);
|
||||||
#else
|
#else
|
||||||
return(0);
|
return(0);
|
||||||
|
|
@ -624,41 +592,25 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
|
||||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
|
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
|
||||||
{
|
{
|
||||||
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
|
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
|
||||||
/* Empty asm statement works as a scheduling barrier */
|
__ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) );
|
||||||
__ASM volatile ("");
|
|
||||||
__ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
|
|
||||||
__ASM volatile ("");
|
|
||||||
#endif
|
#endif
|
||||||
}
|
}
|
||||||
|
|
||||||
#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
|
#endif /* (__CORTEX_M == 0x04) */
|
||||||
|
|
||||||
|
|
||||||
#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
|
|
||||||
/* IAR iccarm specific functions */
|
|
||||||
#include <cmsis_iar.h>
|
|
||||||
|
|
||||||
|
|
||||||
#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
|
|
||||||
/* TI CCS specific functions */
|
|
||||||
#include <cmsis_ccs.h>
|
|
||||||
|
|
||||||
|
|
||||||
#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
|
#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
|
||||||
/* TASKING carm specific functions */
|
/* TASKING carm specific functions */
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* The CMSIS functions have been implemented as intrinsics in the compiler.
|
* The CMSIS functions have been implemented as intrinsics in the compiler.
|
||||||
* Please use "carm -?i" to get an up to date list of all intrinsics,
|
* Please use "carm -?i" to get an up to date list of all instrinsics,
|
||||||
* Including the CMSIS ones.
|
* Including the CMSIS ones.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
|
|
||||||
#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
|
|
||||||
/* Cosmic specific functions */
|
|
||||||
#include <cmsis_csm.h>
|
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
/*@} end of CMSIS_Core_RegAccFunctions */
|
/*@} end of CMSIS_Core_RegAccFunctions */
|
||||||
|
|
||||||
|
|
||||||
#endif /* __CORE_CMFUNC_H */
|
#endif /* __CORE_CMFUNC_H */
|
||||||
|
|
|
||||||
|
|
@ -1,39 +1,25 @@
|
||||||
/**************************************************************************//**
|
/**************************************************************************//**
|
||||||
* @file core_cmInstr.h
|
* @file core_cmInstr.h
|
||||||
* @brief CMSIS Cortex-M Core Instruction Access Header File
|
* @brief CMSIS Cortex-M Core Instruction Access Header File
|
||||||
* @version V4.10
|
* @version V3.01
|
||||||
* @date 18. March 2015
|
* @date 06. March 2012
|
||||||
*
|
*
|
||||||
* @note
|
* @note
|
||||||
|
* Copyright (C) 2009-2012 ARM Limited. All rights reserved.
|
||||||
|
*
|
||||||
|
* @par
|
||||||
|
* ARM Limited (ARM) is supplying this software for use with Cortex-M
|
||||||
|
* processor based microcontrollers. This file can be freely distributed
|
||||||
|
* within development tools that are supporting such ARM based processors.
|
||||||
|
*
|
||||||
|
* @par
|
||||||
|
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||||
|
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||||
|
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||||
|
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||||
|
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||||
*
|
*
|
||||||
******************************************************************************/
|
******************************************************************************/
|
||||||
/* Copyright (c) 2009 - 2014 ARM LIMITED
|
|
||||||
|
|
||||||
All rights reserved.
|
|
||||||
Redistribution and use in source and binary forms, with or without
|
|
||||||
modification, are permitted provided that the following conditions are met:
|
|
||||||
- Redistributions of source code must retain the above copyright
|
|
||||||
notice, this list of conditions and the following disclaimer.
|
|
||||||
- Redistributions in binary form must reproduce the above copyright
|
|
||||||
notice, this list of conditions and the following disclaimer in the
|
|
||||||
documentation and/or other materials provided with the distribution.
|
|
||||||
- Neither the name of ARM nor the names of its contributors may be used
|
|
||||||
to endorse or promote products derived from this software without
|
|
||||||
specific prior written permission.
|
|
||||||
*
|
|
||||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
|
||||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
|
||||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
|
||||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
|
||||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
|
||||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
|
||||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
|
||||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
|
||||||
POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
---------------------------------------------------------------------------*/
|
|
||||||
|
|
||||||
|
|
||||||
#ifndef __CORE_CMINSTR_H
|
#ifndef __CORE_CMINSTR_H
|
||||||
#define __CORE_CMINSTR_H
|
#define __CORE_CMINSTR_H
|
||||||
|
|
@ -89,33 +75,24 @@
|
||||||
so that all instructions following the ISB are fetched from cache or
|
so that all instructions following the ISB are fetched from cache or
|
||||||
memory, after the instruction has been completed.
|
memory, after the instruction has been completed.
|
||||||
*/
|
*/
|
||||||
#define __ISB() do {\
|
#define __ISB() __isb(0xF)
|
||||||
__schedule_barrier();\
|
|
||||||
__isb(0xF);\
|
|
||||||
__schedule_barrier();\
|
|
||||||
} while (0)
|
|
||||||
|
|
||||||
/** \brief Data Synchronization Barrier
|
/** \brief Data Synchronization Barrier
|
||||||
|
|
||||||
This function acts as a special kind of Data Memory Barrier.
|
This function acts as a special kind of Data Memory Barrier.
|
||||||
It completes when all explicit memory accesses before this instruction complete.
|
It completes when all explicit memory accesses before this instruction complete.
|
||||||
*/
|
*/
|
||||||
#define __DSB() do {\
|
#define __DSB() __dsb(0xF)
|
||||||
__schedule_barrier();\
|
|
||||||
__dsb(0xF);\
|
|
||||||
__schedule_barrier();\
|
|
||||||
} while (0)
|
|
||||||
|
|
||||||
/** \brief Data Memory Barrier
|
/** \brief Data Memory Barrier
|
||||||
|
|
||||||
This function ensures the apparent order of the explicit memory operations before
|
This function ensures the apparent order of the explicit memory operations before
|
||||||
and after the instruction, without ensuring their completion.
|
and after the instruction, without ensuring their completion.
|
||||||
*/
|
*/
|
||||||
#define __DMB() do {\
|
#define __DMB() __dmb(0xF)
|
||||||
__schedule_barrier();\
|
|
||||||
__dmb(0xF);\
|
|
||||||
__schedule_barrier();\
|
|
||||||
} while (0)
|
|
||||||
|
|
||||||
/** \brief Reverse byte order (32 bit)
|
/** \brief Reverse byte order (32 bit)
|
||||||
|
|
||||||
|
|
@ -134,13 +111,12 @@
|
||||||
\param [in] value Value to reverse
|
\param [in] value Value to reverse
|
||||||
\return Reversed value
|
\return Reversed value
|
||||||
*/
|
*/
|
||||||
#ifndef __NO_EMBEDDED_ASM
|
|
||||||
__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
|
__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
|
||||||
{
|
{
|
||||||
rev16 r0, r0
|
rev16 r0, r0
|
||||||
bx lr
|
bx lr
|
||||||
}
|
}
|
||||||
#endif
|
|
||||||
|
|
||||||
/** \brief Reverse byte order in signed short value
|
/** \brief Reverse byte order in signed short value
|
||||||
|
|
||||||
|
|
@ -149,13 +125,11 @@ __attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(u
|
||||||
\param [in] value Value to reverse
|
\param [in] value Value to reverse
|
||||||
\return Reversed value
|
\return Reversed value
|
||||||
*/
|
*/
|
||||||
#ifndef __NO_EMBEDDED_ASM
|
|
||||||
__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
|
__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
|
||||||
{
|
{
|
||||||
revsh r0, r0
|
revsh r0, r0
|
||||||
bx lr
|
bx lr
|
||||||
}
|
}
|
||||||
#endif
|
|
||||||
|
|
||||||
|
|
||||||
/** \brief Rotate Right in unsigned value (32 bit)
|
/** \brief Rotate Right in unsigned value (32 bit)
|
||||||
|
|
@ -169,16 +143,7 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in
|
||||||
#define __ROR __ror
|
#define __ROR __ror
|
||||||
|
|
||||||
|
|
||||||
/** \brief Breakpoint
|
#if (__CORTEX_M >= 0x03)
|
||||||
|
|
||||||
This function causes the processor to enter Debug state.
|
|
||||||
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
|
|
||||||
|
|
||||||
\param [in] value is ignored by the processor.
|
|
||||||
If required, a debugger can use it to store additional information about the breakpoint.
|
|
||||||
*/
|
|
||||||
#define __BKPT(value) __breakpoint(value)
|
|
||||||
|
|
||||||
|
|
||||||
/** \brief Reverse bit order of value
|
/** \brief Reverse bit order of value
|
||||||
|
|
||||||
|
|
@ -187,42 +152,12 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in
|
||||||
\param [in] value Value to reverse
|
\param [in] value Value to reverse
|
||||||
\return Reversed value
|
\return Reversed value
|
||||||
*/
|
*/
|
||||||
#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
|
|
||||||
#define __RBIT __rbit
|
#define __RBIT __rbit
|
||||||
#else
|
|
||||||
__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
|
|
||||||
{
|
|
||||||
uint32_t result;
|
|
||||||
int32_t s = 4 /*sizeof(v)*/ * 8 - 1; // extra shift needed at end
|
|
||||||
|
|
||||||
result = value; // r will be reversed bits of v; first get LSB of v
|
|
||||||
for (value >>= 1; value; value >>= 1)
|
|
||||||
{
|
|
||||||
result <<= 1;
|
|
||||||
result |= value & 1;
|
|
||||||
s--;
|
|
||||||
}
|
|
||||||
result <<= s; // shift when v's highest bits are zero
|
|
||||||
return(result);
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
|
|
||||||
/** \brief Count leading zeros
|
|
||||||
|
|
||||||
This function counts the number of leading zeros of a data value.
|
|
||||||
|
|
||||||
\param [in] value Value to count the leading zeros
|
|
||||||
\return number of leading zeros in value
|
|
||||||
*/
|
|
||||||
#define __CLZ __clz
|
|
||||||
|
|
||||||
|
|
||||||
#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
|
|
||||||
|
|
||||||
/** \brief LDR Exclusive (8 bit)
|
/** \brief LDR Exclusive (8 bit)
|
||||||
|
|
||||||
This function executes a exclusive LDR instruction for 8 bit value.
|
This function performs a exclusive LDR command for 8 bit value.
|
||||||
|
|
||||||
\param [in] ptr Pointer to data
|
\param [in] ptr Pointer to data
|
||||||
\return value of type uint8_t at (*ptr)
|
\return value of type uint8_t at (*ptr)
|
||||||
|
|
@ -232,7 +167,7 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
|
||||||
|
|
||||||
/** \brief LDR Exclusive (16 bit)
|
/** \brief LDR Exclusive (16 bit)
|
||||||
|
|
||||||
This function executes a exclusive LDR instruction for 16 bit values.
|
This function performs a exclusive LDR command for 16 bit values.
|
||||||
|
|
||||||
\param [in] ptr Pointer to data
|
\param [in] ptr Pointer to data
|
||||||
\return value of type uint16_t at (*ptr)
|
\return value of type uint16_t at (*ptr)
|
||||||
|
|
@ -242,7 +177,7 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
|
||||||
|
|
||||||
/** \brief LDR Exclusive (32 bit)
|
/** \brief LDR Exclusive (32 bit)
|
||||||
|
|
||||||
This function executes a exclusive LDR instruction for 32 bit values.
|
This function performs a exclusive LDR command for 32 bit values.
|
||||||
|
|
||||||
\param [in] ptr Pointer to data
|
\param [in] ptr Pointer to data
|
||||||
\return value of type uint32_t at (*ptr)
|
\return value of type uint32_t at (*ptr)
|
||||||
|
|
@ -252,7 +187,7 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
|
||||||
|
|
||||||
/** \brief STR Exclusive (8 bit)
|
/** \brief STR Exclusive (8 bit)
|
||||||
|
|
||||||
This function executes a exclusive STR instruction for 8 bit values.
|
This function performs a exclusive STR command for 8 bit values.
|
||||||
|
|
||||||
\param [in] value Value to store
|
\param [in] value Value to store
|
||||||
\param [in] ptr Pointer to location
|
\param [in] ptr Pointer to location
|
||||||
|
|
@ -264,7 +199,7 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
|
||||||
|
|
||||||
/** \brief STR Exclusive (16 bit)
|
/** \brief STR Exclusive (16 bit)
|
||||||
|
|
||||||
This function executes a exclusive STR instruction for 16 bit values.
|
This function performs a exclusive STR command for 16 bit values.
|
||||||
|
|
||||||
\param [in] value Value to store
|
\param [in] value Value to store
|
||||||
\param [in] ptr Pointer to location
|
\param [in] ptr Pointer to location
|
||||||
|
|
@ -276,7 +211,7 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
|
||||||
|
|
||||||
/** \brief STR Exclusive (32 bit)
|
/** \brief STR Exclusive (32 bit)
|
||||||
|
|
||||||
This function executes a exclusive STR instruction for 32 bit values.
|
This function performs a exclusive STR command for 32 bit values.
|
||||||
|
|
||||||
\param [in] value Value to store
|
\param [in] value Value to store
|
||||||
\param [in] ptr Pointer to location
|
\param [in] ptr Pointer to location
|
||||||
|
|
@ -316,99 +251,34 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
|
||||||
#define __USAT __usat
|
#define __USAT __usat
|
||||||
|
|
||||||
|
|
||||||
/** \brief Rotate Right with Extend (32 bit)
|
/** \brief Count leading zeros
|
||||||
|
|
||||||
This function moves each bit of a bitstring right by one bit.
|
This function counts the number of leading zeros of a data value.
|
||||||
The carry input is shifted in at the left end of the bitstring.
|
|
||||||
|
|
||||||
\param [in] value Value to rotate
|
\param [in] value Value to count the leading zeros
|
||||||
\return Rotated value
|
\return number of leading zeros in value
|
||||||
*/
|
*/
|
||||||
#ifndef __NO_EMBEDDED_ASM
|
#define __CLZ __clz
|
||||||
__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
|
|
||||||
{
|
#endif /* (__CORTEX_M >= 0x03) */
|
||||||
rrx r0, r0
|
|
||||||
bx lr
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
|
|
||||||
/** \brief LDRT Unprivileged (8 bit)
|
|
||||||
|
|
||||||
This function executes a Unprivileged LDRT instruction for 8 bit value.
|
#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
|
||||||
|
/* IAR iccarm specific functions */
|
||||||
|
|
||||||
\param [in] ptr Pointer to data
|
#include <cmsis_iar.h>
|
||||||
\return value of type uint8_t at (*ptr)
|
|
||||||
*/
|
|
||||||
#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
|
|
||||||
|
|
||||||
|
|
||||||
/** \brief LDRT Unprivileged (16 bit)
|
#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
|
||||||
|
/* TI CCS specific functions */
|
||||||
|
|
||||||
This function executes a Unprivileged LDRT instruction for 16 bit values.
|
#include <cmsis_ccs.h>
|
||||||
|
|
||||||
\param [in] ptr Pointer to data
|
|
||||||
\return value of type uint16_t at (*ptr)
|
|
||||||
*/
|
|
||||||
#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
|
|
||||||
|
|
||||||
|
|
||||||
/** \brief LDRT Unprivileged (32 bit)
|
|
||||||
|
|
||||||
This function executes a Unprivileged LDRT instruction for 32 bit values.
|
|
||||||
|
|
||||||
\param [in] ptr Pointer to data
|
|
||||||
\return value of type uint32_t at (*ptr)
|
|
||||||
*/
|
|
||||||
#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
|
|
||||||
|
|
||||||
|
|
||||||
/** \brief STRT Unprivileged (8 bit)
|
|
||||||
|
|
||||||
This function executes a Unprivileged STRT instruction for 8 bit values.
|
|
||||||
|
|
||||||
\param [in] value Value to store
|
|
||||||
\param [in] ptr Pointer to location
|
|
||||||
*/
|
|
||||||
#define __STRBT(value, ptr) __strt(value, ptr)
|
|
||||||
|
|
||||||
|
|
||||||
/** \brief STRT Unprivileged (16 bit)
|
|
||||||
|
|
||||||
This function executes a Unprivileged STRT instruction for 16 bit values.
|
|
||||||
|
|
||||||
\param [in] value Value to store
|
|
||||||
\param [in] ptr Pointer to location
|
|
||||||
*/
|
|
||||||
#define __STRHT(value, ptr) __strt(value, ptr)
|
|
||||||
|
|
||||||
|
|
||||||
/** \brief STRT Unprivileged (32 bit)
|
|
||||||
|
|
||||||
This function executes a Unprivileged STRT instruction for 32 bit values.
|
|
||||||
|
|
||||||
\param [in] value Value to store
|
|
||||||
\param [in] ptr Pointer to location
|
|
||||||
*/
|
|
||||||
#define __STRT(value, ptr) __strt(value, ptr)
|
|
||||||
|
|
||||||
#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
|
|
||||||
|
|
||||||
|
|
||||||
#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
|
#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
|
||||||
/* GNU gcc specific functions */
|
/* GNU gcc specific functions */
|
||||||
|
|
||||||
/* Define macros for porting to both thumb1 and thumb2.
|
|
||||||
* For thumb1, use low register (r0-r7), specified by constrant "l"
|
|
||||||
* Otherwise, use general registers, specified by constrant "r" */
|
|
||||||
#if defined (__thumb__) && !defined (__thumb2__)
|
|
||||||
#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
|
|
||||||
#define __CMSIS_GCC_USE_REG(r) "l" (r)
|
|
||||||
#else
|
|
||||||
#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
|
|
||||||
#define __CMSIS_GCC_USE_REG(r) "r" (r)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/** \brief No Operation
|
/** \brief No Operation
|
||||||
|
|
||||||
No Operation does nothing. This instruction can be used for code alignment purposes.
|
No Operation does nothing. This instruction can be used for code alignment purposes.
|
||||||
|
|
@ -459,7 +329,7 @@ __attribute__((always_inline)) __STATIC_INLINE void __SEV(void)
|
||||||
*/
|
*/
|
||||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)
|
__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)
|
||||||
{
|
{
|
||||||
__ASM volatile ("isb 0xF":::"memory");
|
__ASM volatile ("isb");
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
|
|
@ -470,7 +340,7 @@ __attribute__((always_inline)) __STATIC_INLINE void __ISB(void)
|
||||||
*/
|
*/
|
||||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)
|
__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)
|
||||||
{
|
{
|
||||||
__ASM volatile ("dsb 0xF":::"memory");
|
__ASM volatile ("dsb");
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
|
|
@ -481,7 +351,7 @@ __attribute__((always_inline)) __STATIC_INLINE void __DSB(void)
|
||||||
*/
|
*/
|
||||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
|
__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
|
||||||
{
|
{
|
||||||
__ASM volatile ("dmb 0xF":::"memory");
|
__ASM volatile ("dmb");
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
|
|
@ -494,14 +364,10 @@ __attribute__((always_inline)) __STATIC_INLINE void __DMB(void)
|
||||||
*/
|
*/
|
||||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)
|
||||||
{
|
{
|
||||||
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
|
|
||||||
return __builtin_bswap32(value);
|
|
||||||
#else
|
|
||||||
uint32_t result;
|
uint32_t result;
|
||||||
|
|
||||||
__ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
|
__ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
|
||||||
return(result);
|
return(result);
|
||||||
#endif
|
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
|
|
@ -516,7 +382,7 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)
|
||||||
{
|
{
|
||||||
uint32_t result;
|
uint32_t result;
|
||||||
|
|
||||||
__ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
|
__ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );
|
||||||
return(result);
|
return(result);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
@ -530,14 +396,10 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)
|
||||||
*/
|
*/
|
||||||
__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)
|
__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)
|
||||||
{
|
{
|
||||||
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
|
|
||||||
return (short)__builtin_bswap16(value);
|
|
||||||
#else
|
|
||||||
uint32_t result;
|
uint32_t result;
|
||||||
|
|
||||||
__ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
|
__ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );
|
||||||
return(result);
|
return(result);
|
||||||
#endif
|
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
|
|
@ -551,20 +413,13 @@ __attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)
|
||||||
*/
|
*/
|
||||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
|
||||||
{
|
{
|
||||||
return (op1 >> op2) | (op1 << (32 - op2));
|
|
||||||
|
__ASM volatile ("ror %0, %0, %1" : "+r" (op1) : "r" (op2) );
|
||||||
|
return(op1);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
/** \brief Breakpoint
|
#if (__CORTEX_M >= 0x03)
|
||||||
|
|
||||||
This function causes the processor to enter Debug state.
|
|
||||||
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
|
|
||||||
|
|
||||||
\param [in] value is ignored by the processor.
|
|
||||||
If required, a debugger can use it to store additional information about the breakpoint.
|
|
||||||
*/
|
|
||||||
#define __BKPT(value) __ASM volatile ("bkpt "#value)
|
|
||||||
|
|
||||||
|
|
||||||
/** \brief Reverse bit order of value
|
/** \brief Reverse bit order of value
|
||||||
|
|
||||||
|
|
@ -577,85 +432,46 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
|
||||||
{
|
{
|
||||||
uint32_t result;
|
uint32_t result;
|
||||||
|
|
||||||
#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
|
|
||||||
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
||||||
#else
|
|
||||||
int32_t s = 4 /*sizeof(v)*/ * 8 - 1; // extra shift needed at end
|
|
||||||
|
|
||||||
result = value; // r will be reversed bits of v; first get LSB of v
|
|
||||||
for (value >>= 1; value; value >>= 1)
|
|
||||||
{
|
|
||||||
result <<= 1;
|
|
||||||
result |= value & 1;
|
|
||||||
s--;
|
|
||||||
}
|
|
||||||
result <<= s; // shift when v's highest bits are zero
|
|
||||||
#endif
|
|
||||||
return(result);
|
return(result);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
/** \brief Count leading zeros
|
|
||||||
|
|
||||||
This function counts the number of leading zeros of a data value.
|
|
||||||
|
|
||||||
\param [in] value Value to count the leading zeros
|
|
||||||
\return number of leading zeros in value
|
|
||||||
*/
|
|
||||||
#define __CLZ __builtin_clz
|
|
||||||
|
|
||||||
|
|
||||||
#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
|
|
||||||
|
|
||||||
/** \brief LDR Exclusive (8 bit)
|
/** \brief LDR Exclusive (8 bit)
|
||||||
|
|
||||||
This function executes a exclusive LDR instruction for 8 bit value.
|
This function performs a exclusive LDR command for 8 bit value.
|
||||||
|
|
||||||
\param [in] ptr Pointer to data
|
\param [in] ptr Pointer to data
|
||||||
\return value of type uint8_t at (*ptr)
|
\return value of type uint8_t at (*ptr)
|
||||||
*/
|
*/
|
||||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
|
||||||
{
|
{
|
||||||
uint32_t result;
|
uint8_t result;
|
||||||
|
|
||||||
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
|
__ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );
|
||||||
__ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
|
return(result);
|
||||||
#else
|
|
||||||
/* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
|
|
||||||
accepted by assembler. So has to use following less efficient pattern.
|
|
||||||
*/
|
|
||||||
__ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
|
|
||||||
#endif
|
|
||||||
return ((uint8_t) result); /* Add explicit type cast here */
|
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
/** \brief LDR Exclusive (16 bit)
|
/** \brief LDR Exclusive (16 bit)
|
||||||
|
|
||||||
This function executes a exclusive LDR instruction for 16 bit values.
|
This function performs a exclusive LDR command for 16 bit values.
|
||||||
|
|
||||||
\param [in] ptr Pointer to data
|
\param [in] ptr Pointer to data
|
||||||
\return value of type uint16_t at (*ptr)
|
\return value of type uint16_t at (*ptr)
|
||||||
*/
|
*/
|
||||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
|
||||||
{
|
{
|
||||||
uint32_t result;
|
uint16_t result;
|
||||||
|
|
||||||
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
|
__ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );
|
||||||
__ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
|
return(result);
|
||||||
#else
|
|
||||||
/* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
|
|
||||||
accepted by assembler. So has to use following less efficient pattern.
|
|
||||||
*/
|
|
||||||
__ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
|
|
||||||
#endif
|
|
||||||
return ((uint16_t) result); /* Add explicit type cast here */
|
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
/** \brief LDR Exclusive (32 bit)
|
/** \brief LDR Exclusive (32 bit)
|
||||||
|
|
||||||
This function executes a exclusive LDR instruction for 32 bit values.
|
This function performs a exclusive LDR command for 32 bit values.
|
||||||
|
|
||||||
\param [in] ptr Pointer to data
|
\param [in] ptr Pointer to data
|
||||||
\return value of type uint32_t at (*ptr)
|
\return value of type uint32_t at (*ptr)
|
||||||
|
|
@ -664,14 +480,14 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32
|
||||||
{
|
{
|
||||||
uint32_t result;
|
uint32_t result;
|
||||||
|
|
||||||
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
__ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );
|
||||||
return(result);
|
return(result);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
/** \brief STR Exclusive (8 bit)
|
/** \brief STR Exclusive (8 bit)
|
||||||
|
|
||||||
This function executes a exclusive STR instruction for 8 bit values.
|
This function performs a exclusive STR command for 8 bit values.
|
||||||
|
|
||||||
\param [in] value Value to store
|
\param [in] value Value to store
|
||||||
\param [in] ptr Pointer to location
|
\param [in] ptr Pointer to location
|
||||||
|
|
@ -682,14 +498,14 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value,
|
||||||
{
|
{
|
||||||
uint32_t result;
|
uint32_t result;
|
||||||
|
|
||||||
__ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
|
__ASM volatile ("strexb %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
|
||||||
return(result);
|
return(result);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
/** \brief STR Exclusive (16 bit)
|
/** \brief STR Exclusive (16 bit)
|
||||||
|
|
||||||
This function executes a exclusive STR instruction for 16 bit values.
|
This function performs a exclusive STR command for 16 bit values.
|
||||||
|
|
||||||
\param [in] value Value to store
|
\param [in] value Value to store
|
||||||
\param [in] ptr Pointer to location
|
\param [in] ptr Pointer to location
|
||||||
|
|
@ -700,14 +516,14 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value,
|
||||||
{
|
{
|
||||||
uint32_t result;
|
uint32_t result;
|
||||||
|
|
||||||
__ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
|
__ASM volatile ("strexh %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
|
||||||
return(result);
|
return(result);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
/** \brief STR Exclusive (32 bit)
|
/** \brief STR Exclusive (32 bit)
|
||||||
|
|
||||||
This function executes a exclusive STR instruction for 32 bit values.
|
This function performs a exclusive STR command for 32 bit values.
|
||||||
|
|
||||||
\param [in] value Value to store
|
\param [in] value Value to store
|
||||||
\param [in] ptr Pointer to location
|
\param [in] ptr Pointer to location
|
||||||
|
|
@ -718,7 +534,7 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value,
|
||||||
{
|
{
|
||||||
uint32_t result;
|
uint32_t result;
|
||||||
|
|
||||||
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
__ASM volatile ("strex %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
|
||||||
return(result);
|
return(result);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
@ -730,7 +546,7 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value,
|
||||||
*/
|
*/
|
||||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
|
__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
|
||||||
{
|
{
|
||||||
__ASM volatile ("clrex" ::: "memory");
|
__ASM volatile ("clrex");
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
|
|
@ -766,149 +582,35 @@ __attribute__((always_inline)) __STATIC_INLINE void __CLREX(void)
|
||||||
})
|
})
|
||||||
|
|
||||||
|
|
||||||
/** \brief Rotate Right with Extend (32 bit)
|
/** \brief Count leading zeros
|
||||||
|
|
||||||
This function moves each bit of a bitstring right by one bit.
|
This function counts the number of leading zeros of a data value.
|
||||||
The carry input is shifted in at the left end of the bitstring.
|
|
||||||
|
|
||||||
\param [in] value Value to rotate
|
\param [in] value Value to count the leading zeros
|
||||||
\return Rotated value
|
\return number of leading zeros in value
|
||||||
*/
|
*/
|
||||||
__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value)
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
|
||||||
{
|
{
|
||||||
uint32_t result;
|
uint8_t result;
|
||||||
|
|
||||||
__ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
|
__ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
|
||||||
return(result);
|
return(result);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
#endif /* (__CORTEX_M >= 0x03) */
|
||||||
/** \brief LDRT Unprivileged (8 bit)
|
|
||||||
|
|
||||||
This function executes a Unprivileged LDRT instruction for 8 bit value.
|
|
||||||
|
|
||||||
\param [in] ptr Pointer to data
|
|
||||||
\return value of type uint8_t at (*ptr)
|
|
||||||
*/
|
|
||||||
__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr)
|
|
||||||
{
|
|
||||||
uint32_t result;
|
|
||||||
|
|
||||||
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
|
|
||||||
__ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
||||||
#else
|
|
||||||
/* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
|
|
||||||
accepted by assembler. So has to use following less efficient pattern.
|
|
||||||
*/
|
|
||||||
__ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
|
|
||||||
#endif
|
|
||||||
return ((uint8_t) result); /* Add explicit type cast here */
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
/** \brief LDRT Unprivileged (16 bit)
|
|
||||||
|
|
||||||
This function executes a Unprivileged LDRT instruction for 16 bit values.
|
|
||||||
|
|
||||||
\param [in] ptr Pointer to data
|
|
||||||
\return value of type uint16_t at (*ptr)
|
|
||||||
*/
|
|
||||||
__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr)
|
|
||||||
{
|
|
||||||
uint32_t result;
|
|
||||||
|
|
||||||
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
|
|
||||||
__ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
||||||
#else
|
|
||||||
/* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
|
|
||||||
accepted by assembler. So has to use following less efficient pattern.
|
|
||||||
*/
|
|
||||||
__ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
|
|
||||||
#endif
|
|
||||||
return ((uint16_t) result); /* Add explicit type cast here */
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
/** \brief LDRT Unprivileged (32 bit)
|
|
||||||
|
|
||||||
This function executes a Unprivileged LDRT instruction for 32 bit values.
|
|
||||||
|
|
||||||
\param [in] ptr Pointer to data
|
|
||||||
\return value of type uint32_t at (*ptr)
|
|
||||||
*/
|
|
||||||
__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr)
|
|
||||||
{
|
|
||||||
uint32_t result;
|
|
||||||
|
|
||||||
__ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
||||||
return(result);
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
/** \brief STRT Unprivileged (8 bit)
|
|
||||||
|
|
||||||
This function executes a Unprivileged STRT instruction for 8 bit values.
|
|
||||||
|
|
||||||
\param [in] value Value to store
|
|
||||||
\param [in] ptr Pointer to location
|
|
||||||
*/
|
|
||||||
__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr)
|
|
||||||
{
|
|
||||||
__ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
/** \brief STRT Unprivileged (16 bit)
|
|
||||||
|
|
||||||
This function executes a Unprivileged STRT instruction for 16 bit values.
|
|
||||||
|
|
||||||
\param [in] value Value to store
|
|
||||||
\param [in] ptr Pointer to location
|
|
||||||
*/
|
|
||||||
__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr)
|
|
||||||
{
|
|
||||||
__ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
/** \brief STRT Unprivileged (32 bit)
|
|
||||||
|
|
||||||
This function executes a Unprivileged STRT instruction for 32 bit values.
|
|
||||||
|
|
||||||
\param [in] value Value to store
|
|
||||||
\param [in] ptr Pointer to location
|
|
||||||
*/
|
|
||||||
__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr)
|
|
||||||
{
|
|
||||||
__ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) );
|
|
||||||
}
|
|
||||||
|
|
||||||
#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
|
|
||||||
|
|
||||||
|
|
||||||
#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
|
|
||||||
/* IAR iccarm specific functions */
|
|
||||||
#include <cmsis_iar.h>
|
|
||||||
|
|
||||||
|
|
||||||
#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
|
|
||||||
/* TI CCS specific functions */
|
|
||||||
#include <cmsis_ccs.h>
|
|
||||||
|
|
||||||
|
|
||||||
#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
|
#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
|
||||||
/* TASKING carm specific functions */
|
/* TASKING carm specific functions */
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* The CMSIS functions have been implemented as intrinsics in the compiler.
|
* The CMSIS functions have been implemented as intrinsics in the compiler.
|
||||||
* Please use "carm -?i" to get an up to date list of all intrinsics,
|
* Please use "carm -?i" to get an up to date list of all intrinsics,
|
||||||
* Including the CMSIS ones.
|
* Including the CMSIS ones.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
|
|
||||||
#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
|
|
||||||
/* Cosmic specific functions */
|
|
||||||
#include <cmsis_csm.h>
|
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
|
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
|
||||||
|
|
|
||||||
|
|
@ -5,10 +5,11 @@
|
||||||
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
||||||
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
||||||
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
||||||
|
\version 2022-03-09, V3.0.0, firmware for GD32F4xx
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/*
|
/*
|
||||||
Copyright (c) 2020, GigaDevice Semiconductor Inc.
|
Copyright (c) 2022, GigaDevice Semiconductor Inc.
|
||||||
|
|
||||||
Redistribution and use in source and binary forms, with or without modification,
|
Redistribution and use in source and binary forms, with or without modification,
|
||||||
are permitted provided that the following conditions are met:
|
are permitted provided that the following conditions are met:
|
||||||
|
|
@ -56,19 +57,19 @@ OF SUCH DAMAGE.
|
||||||
#define ADC_IOFF3(adcx) REG32((adcx) + 0x20U) /*!< ADC inserted channel data offset register 3 */
|
#define ADC_IOFF3(adcx) REG32((adcx) + 0x20U) /*!< ADC inserted channel data offset register 3 */
|
||||||
#define ADC_WDHT(adcx) REG32((adcx) + 0x24U) /*!< ADC watchdog high threshold register */
|
#define ADC_WDHT(adcx) REG32((adcx) + 0x24U) /*!< ADC watchdog high threshold register */
|
||||||
#define ADC_WDLT(adcx) REG32((adcx) + 0x28U) /*!< ADC watchdog low threshold register */
|
#define ADC_WDLT(adcx) REG32((adcx) + 0x28U) /*!< ADC watchdog low threshold register */
|
||||||
#define ADC_RSQ0(adcx) REG32((adcx) + 0x2CU) /*!< ADC regular sequence register 0 */
|
#define ADC_RSQ0(adcx) REG32((adcx) + 0x2CU) /*!< ADC routine sequence register 0 */
|
||||||
#define ADC_RSQ1(adcx) REG32((adcx) + 0x30U) /*!< ADC regular sequence register 1 */
|
#define ADC_RSQ1(adcx) REG32((adcx) + 0x30U) /*!< ADC routine sequence register 1 */
|
||||||
#define ADC_RSQ2(adcx) REG32((adcx) + 0x34U) /*!< ADC regular sequence register 2 */
|
#define ADC_RSQ2(adcx) REG32((adcx) + 0x34U) /*!< ADC routine sequence register 2 */
|
||||||
#define ADC_ISQ(adcx) REG32((adcx) + 0x38U) /*!< ADC inserted sequence register */
|
#define ADC_ISQ(adcx) REG32((adcx) + 0x38U) /*!< ADC inserted sequence register */
|
||||||
#define ADC_IDATA0(adcx) REG32((adcx) + 0x3CU) /*!< ADC inserted data register 0 */
|
#define ADC_IDATA0(adcx) REG32((adcx) + 0x3CU) /*!< ADC inserted data register 0 */
|
||||||
#define ADC_IDATA1(adcx) REG32((adcx) + 0x40U) /*!< ADC inserted data register 1 */
|
#define ADC_IDATA1(adcx) REG32((adcx) + 0x40U) /*!< ADC inserted data register 1 */
|
||||||
#define ADC_IDATA2(adcx) REG32((adcx) + 0x44U) /*!< ADC inserted data register 2 */
|
#define ADC_IDATA2(adcx) REG32((adcx) + 0x44U) /*!< ADC inserted data register 2 */
|
||||||
#define ADC_IDATA3(adcx) REG32((adcx) + 0x48U) /*!< ADC inserted data register 3 */
|
#define ADC_IDATA3(adcx) REG32((adcx) + 0x48U) /*!< ADC inserted data register 3 */
|
||||||
#define ADC_RDATA(adcx) REG32((adcx) + 0x4CU) /*!< ADC regular data register */
|
#define ADC_RDATA(adcx) REG32((adcx) + 0x4CU) /*!< ADC routine data register */
|
||||||
#define ADC_OVSAMPCTL(adcx) REG32((adcx) + 0x80U) /*!< ADC oversampling control register */
|
#define ADC_OVSAMPCTL(adcx) REG32((adcx) + 0x80U) /*!< ADC oversampling control register */
|
||||||
#define ADC_SSTAT REG32((ADC_BASE) + 0x300U) /*!< ADC summary status register */
|
#define ADC_SSTAT REG32((ADC_BASE) + 0x300U) /*!< ADC summary status register */
|
||||||
#define ADC_SYNCCTL REG32((ADC_BASE) + 0x304U) /*!< ADC synchronization control register */
|
#define ADC_SYNCCTL REG32((ADC_BASE) + 0x304U) /*!< ADC synchronization control register */
|
||||||
#define ADC_SYNCDATA REG32((ADC_BASE) + 0x308U) /*!< ADC synchronization regular data register */
|
#define ADC_SYNCDATA REG32((ADC_BASE) + 0x308U) /*!< ADC synchronization routine data register */
|
||||||
|
|
||||||
/* bits definitions */
|
/* bits definitions */
|
||||||
/* ADC_STAT */
|
/* ADC_STAT */
|
||||||
|
|
@ -76,8 +77,8 @@ OF SUCH DAMAGE.
|
||||||
#define ADC_STAT_EOC BIT(1) /*!< end of conversion */
|
#define ADC_STAT_EOC BIT(1) /*!< end of conversion */
|
||||||
#define ADC_STAT_EOIC BIT(2) /*!< inserted channel end of conversion */
|
#define ADC_STAT_EOIC BIT(2) /*!< inserted channel end of conversion */
|
||||||
#define ADC_STAT_STIC BIT(3) /*!< inserted channel start flag */
|
#define ADC_STAT_STIC BIT(3) /*!< inserted channel start flag */
|
||||||
#define ADC_STAT_STRC BIT(4) /*!< regular channel start flag */
|
#define ADC_STAT_STRC BIT(4) /*!< routine channel start flag */
|
||||||
#define ADC_STAT_ROVF BIT(5) /*!< regular data register overflow */
|
#define ADC_STAT_ROVF BIT(5) /*!< routine data register overflow */
|
||||||
|
|
||||||
/* ADC_CTL0 */
|
/* ADC_CTL0 */
|
||||||
#define ADC_CTL0_WDCHSEL BITS(0,4) /*!< analog watchdog channel select bits */
|
#define ADC_CTL0_WDCHSEL BITS(0,4) /*!< analog watchdog channel select bits */
|
||||||
|
|
@ -86,12 +87,12 @@ OF SUCH DAMAGE.
|
||||||
#define ADC_CTL0_EOICIE BIT(7) /*!< interrupt enable for inserted channels */
|
#define ADC_CTL0_EOICIE BIT(7) /*!< interrupt enable for inserted channels */
|
||||||
#define ADC_CTL0_SM BIT(8) /*!< scan mode */
|
#define ADC_CTL0_SM BIT(8) /*!< scan mode */
|
||||||
#define ADC_CTL0_WDSC BIT(9) /*!< when in scan mode, analog watchdog is effective on a single channel */
|
#define ADC_CTL0_WDSC BIT(9) /*!< when in scan mode, analog watchdog is effective on a single channel */
|
||||||
#define ADC_CTL0_ICA BIT(10) /*!< automatic inserted group conversion */
|
#define ADC_CTL0_ICA BIT(10) /*!< automatic inserted sequence conversion */
|
||||||
#define ADC_CTL0_DISRC BIT(11) /*!< discontinuous mode on regular channels */
|
#define ADC_CTL0_DISRC BIT(11) /*!< discontinuous mode on routine channels */
|
||||||
#define ADC_CTL0_DISIC BIT(12) /*!< discontinuous mode on inserted channels */
|
#define ADC_CTL0_DISIC BIT(12) /*!< discontinuous mode on inserted channels */
|
||||||
#define ADC_CTL0_DISNUM BITS(13,15) /*!< discontinuous mode channel count */
|
#define ADC_CTL0_DISNUM BITS(13,15) /*!< discontinuous mode channel count */
|
||||||
#define ADC_CTL0_IWDEN BIT(22) /*!< analog watchdog enable on inserted channels */
|
#define ADC_CTL0_IWDEN BIT(22) /*!< analog watchdog enable on inserted channels */
|
||||||
#define ADC_CTL0_RWDEN BIT(23) /*!< analog watchdog enable on regular channels */
|
#define ADC_CTL0_RWDEN BIT(23) /*!< analog watchdog enable on routine channels */
|
||||||
#define ADC_CTL0_DRES BITS(24,25) /*!< ADC data resolution */
|
#define ADC_CTL0_DRES BITS(24,25) /*!< ADC data resolution */
|
||||||
#define ADC_CTL0_ROVFIE BIT(26) /*!< interrupt enable for ROVF */
|
#define ADC_CTL0_ROVFIE BIT(26) /*!< interrupt enable for ROVF */
|
||||||
|
|
||||||
|
|
@ -104,12 +105,12 @@ OF SUCH DAMAGE.
|
||||||
#define ADC_CTL1_DDM BIT(9) /*!< DMA disable mode */
|
#define ADC_CTL1_DDM BIT(9) /*!< DMA disable mode */
|
||||||
#define ADC_CTL1_EOCM BIT(10) /*!< end of conversion mode */
|
#define ADC_CTL1_EOCM BIT(10) /*!< end of conversion mode */
|
||||||
#define ADC_CTL1_DAL BIT(11) /*!< data alignment */
|
#define ADC_CTL1_DAL BIT(11) /*!< data alignment */
|
||||||
#define ADC_CTL1_ETSIC BITS(16,19) /*!< external event select for inserted group */
|
#define ADC_CTL1_ETSIC BITS(16,19) /*!< external event select for inserted sequence */
|
||||||
#define ADC_CTL1_ETMIC BITS(20,21) /*!< external trigger conversion mode for inserted channels */
|
#define ADC_CTL1_ETMIC BITS(20,21) /*!< external trigger conversion mode for inserted channels */
|
||||||
#define ADC_CTL1_SWICST BIT(22) /*!< start conversion of inserted channels */
|
#define ADC_CTL1_SWICST BIT(22) /*!< start conversion of inserted channels */
|
||||||
#define ADC_CTL1_ETSRC BITS(24,27) /*!< external event select for regular group */
|
#define ADC_CTL1_ETSRC BITS(24,27) /*!< external event select for routine sequence */
|
||||||
#define ADC_CTL1_ETMRC BITS(28,29) /*!< external trigger conversion mode for regular channels */
|
#define ADC_CTL1_ETMRC BITS(28,29) /*!< external trigger conversion mode for routine channels */
|
||||||
#define ADC_CTL1_SWRCST BIT(30) /*!< start conversion of regular channels */
|
#define ADC_CTL1_SWRCST BIT(30) /*!< start conversion of routine channels */
|
||||||
|
|
||||||
/* ADC_SAMPTx x=0..1 */
|
/* ADC_SAMPTx x=0..1 */
|
||||||
#define ADC_SAMPTX_SPTN BITS(0,2) /*!< channel x sample time selection */
|
#define ADC_SAMPTX_SPTN BITS(0,2) /*!< channel x sample time selection */
|
||||||
|
|
@ -124,18 +125,18 @@ OF SUCH DAMAGE.
|
||||||
#define ADC_WDLT_WDLT BITS(0,11) /*!< analog watchdog low threshold */
|
#define ADC_WDLT_WDLT BITS(0,11) /*!< analog watchdog low threshold */
|
||||||
|
|
||||||
/* ADC_RSQx */
|
/* ADC_RSQx */
|
||||||
#define ADC_RSQX_RSQN BITS(0,4) /*!< x conversion in regular sequence */
|
#define ADC_RSQX_RSQN BITS(0,4) /*!< x conversion in routine sequence */
|
||||||
#define ADC_RSQ0_RL BITS(20,23) /*!< regular channel sequence length */
|
#define ADC_RSQ0_RL BITS(20,23) /*!< routine channel sequence length */
|
||||||
|
|
||||||
/* ADC_ISQ */
|
/* ADC_ISQ */
|
||||||
#define ADC_ISQ_ISQN BITS(0,4) /*!< x conversion in regular sequence */
|
#define ADC_ISQ_ISQN BITS(0,4) /*!< x conversion in inserted sequence */
|
||||||
#define ADC_ISQ_IL BITS(20,21) /*!< inserted sequence length */
|
#define ADC_ISQ_IL BITS(20,21) /*!< inserted sequence length */
|
||||||
|
|
||||||
/* ADC_IDATAx x=0..3*/
|
/* ADC_IDATAx x=0..3*/
|
||||||
#define ADC_IDATAX_IDATAN BITS(0,15) /*!< inserted data x */
|
#define ADC_IDATAX_IDATAN BITS(0,15) /*!< inserted data x */
|
||||||
|
|
||||||
/* ADC_RDATA */
|
/* ADC_RDATA */
|
||||||
#define ADC_RDATA_RDATA BITS(0,15) /*!< regular data */
|
#define ADC_RDATA_RDATA BITS(0,15) /*!< routine data */
|
||||||
|
|
||||||
/* ADC_OVSAMPCTL */
|
/* ADC_OVSAMPCTL */
|
||||||
#define ADC_OVSAMPCTL_OVSEN BIT(0) /*!< oversampling enable */
|
#define ADC_OVSAMPCTL_OVSEN BIT(0) /*!< oversampling enable */
|
||||||
|
|
@ -173,8 +174,8 @@ OF SUCH DAMAGE.
|
||||||
#define ADC_SYNCCTL_TSVREN BIT(23) /*!< channel 16 (temperature sensor) and 17 (internal reference voltage) enable of ADC0 */
|
#define ADC_SYNCCTL_TSVREN BIT(23) /*!< channel 16 (temperature sensor) and 17 (internal reference voltage) enable of ADC0 */
|
||||||
|
|
||||||
/* ADC_SYNCDATA */
|
/* ADC_SYNCDATA */
|
||||||
#define ADC_SYNCDATA_SYNCDATA0 BITS(0,15) /*!< regular data1 in ADC synchronization mode */
|
#define ADC_SYNCDATA_SYNCDATA0 BITS(0,15) /*!< routine data1 in ADC synchronization mode */
|
||||||
#define ADC_SYNCDATA_SYNCDATA1 BITS(16,31) /*!< regular data2 in ADC synchronization mode */
|
#define ADC_SYNCDATA_SYNCDATA1 BITS(16,31) /*!< routine data2 in ADC synchronization mode */
|
||||||
|
|
||||||
/* constants definitions */
|
/* constants definitions */
|
||||||
/* ADC status flag */
|
/* ADC status flag */
|
||||||
|
|
@ -182,15 +183,15 @@ OF SUCH DAMAGE.
|
||||||
#define ADC_FLAG_EOC ADC_STAT_EOC /*!< end of conversion */
|
#define ADC_FLAG_EOC ADC_STAT_EOC /*!< end of conversion */
|
||||||
#define ADC_FLAG_EOIC ADC_STAT_EOIC /*!< inserted channel end of conversion */
|
#define ADC_FLAG_EOIC ADC_STAT_EOIC /*!< inserted channel end of conversion */
|
||||||
#define ADC_FLAG_STIC ADC_STAT_STIC /*!< inserted channel start flag */
|
#define ADC_FLAG_STIC ADC_STAT_STIC /*!< inserted channel start flag */
|
||||||
#define ADC_FLAG_STRC ADC_STAT_STRC /*!< regular channel start flag */
|
#define ADC_FLAG_STRC ADC_STAT_STRC /*!< routine channel start flag */
|
||||||
#define ADC_FLAG_ROVF ADC_STAT_ROVF /*!< regular data register overflow */
|
#define ADC_FLAG_ROVF ADC_STAT_ROVF /*!< routine data register overflow */
|
||||||
|
|
||||||
/* adc_ctl0 register value */
|
/* adc_ctl0 register value */
|
||||||
#define CTL0_DISNUM(regval) (BITS(13,15) & ((uint32_t)(regval) << 13)) /*!< write value to ADC_CTL0_DISNUM bit field */
|
#define CTL0_DISNUM(regval) (BITS(13,15) & ((uint32_t)(regval) << 13)) /*!< write value to ADC_CTL0_DISNUM bit field */
|
||||||
|
|
||||||
/* ADC special function definitions */
|
/* ADC special function definitions */
|
||||||
#define ADC_SCAN_MODE ADC_CTL0_SM /*!< scan mode */
|
#define ADC_SCAN_MODE ADC_CTL0_SM /*!< scan mode */
|
||||||
#define ADC_INSERTED_CHANNEL_AUTO ADC_CTL0_ICA /*!< inserted channel group convert automatically */
|
#define ADC_INSERTED_CHANNEL_AUTO ADC_CTL0_ICA /*!< inserted sequence convert automatically */
|
||||||
#define ADC_CONTINUOUS_MODE ADC_CTL1_CTN /*!< continuous mode */
|
#define ADC_CONTINUOUS_MODE ADC_CTL1_CTN /*!< continuous mode */
|
||||||
|
|
||||||
/* temperature sensor channel, internal reference voltage channel, VBAT channel */
|
/* temperature sensor channel, internal reference voltage channel, VBAT channel */
|
||||||
|
|
@ -200,47 +201,47 @@ OF SUCH DAMAGE.
|
||||||
/* ADC synchronization mode */
|
/* ADC synchronization mode */
|
||||||
#define SYNCCTL_SYNCM(regval) (BITS(0,4) & ((uint32_t)(regval))) /*!< write value to ADC_CTL0_SYNCM bit field */
|
#define SYNCCTL_SYNCM(regval) (BITS(0,4) & ((uint32_t)(regval))) /*!< write value to ADC_CTL0_SYNCM bit field */
|
||||||
#define ADC_SYNC_MODE_INDEPENDENT SYNCCTL_SYNCM(0) /*!< ADC synchronization mode disabled.All the ADCs work independently */
|
#define ADC_SYNC_MODE_INDEPENDENT SYNCCTL_SYNCM(0) /*!< ADC synchronization mode disabled.All the ADCs work independently */
|
||||||
#define ADC_DAUL_REGULAL_PARALLEL_INSERTED_PARALLEL SYNCCTL_SYNCM(1) /*!< ADC0 and ADC1 work in combined regular parallel & inserted parallel mode. ADC2 works independently */
|
#define ADC_DAUL_ROUTINE_PARALLEL_INSERTED_PARALLEL SYNCCTL_SYNCM(1) /*!< ADC0 and ADC1 work in combined routine parallel & inserted parallel mode. ADC2 works independently */
|
||||||
#define ADC_DAUL_REGULAL_PARALLEL_INSERTED_ROTATION SYNCCTL_SYNCM(2) /*!< ADC0 and ADC1 work in combined regular parallel & trigger rotation mode. ADC2 works independently */
|
#define ADC_DAUL_ROUTINE_PARALLEL_INSERTED_ROTATION SYNCCTL_SYNCM(2) /*!< ADC0 and ADC1 work in combined routine parallel & trigger rotation mode. ADC2 works independently */
|
||||||
#define ADC_DAUL_INSERTED_PARALLEL SYNCCTL_SYNCM(5) /*!< ADC0 and ADC1 work in inserted parallel mode. ADC2 works independently */
|
#define ADC_DAUL_INSERTED_PARALLEL SYNCCTL_SYNCM(5) /*!< ADC0 and ADC1 work in inserted parallel mode. ADC2 works independently */
|
||||||
#define ADC_DAUL_REGULAL_PARALLEL SYNCCTL_SYNCM(6) /*!< ADC0 and ADC1 work in regular parallel mode. ADC2 works independently */
|
#define ADC_DAUL_ROUTINE_PARALLEL SYNCCTL_SYNCM(6) /*!< ADC0 and ADC1 work in routine parallel mode. ADC2 works independently */
|
||||||
#define ADC_DAUL_REGULAL_FOLLOW_UP SYNCCTL_SYNCM(7) /*!< ADC0 and ADC1 work in follow-up mode. ADC2 works independently */
|
#define ADC_DAUL_ROUTINE_FOLLOW_UP SYNCCTL_SYNCM(7) /*!< ADC0 and ADC1 work in follow-up mode. ADC2 works independently */
|
||||||
#define ADC_DAUL_INSERTED_TRRIGGER_ROTATION SYNCCTL_SYNCM(9) /*!< ADC0 and ADC1 work in trigger rotation mode. ADC2 works independently */
|
#define ADC_DAUL_INSERTED_TRRIGGER_ROTATION SYNCCTL_SYNCM(9) /*!< ADC0 and ADC1 work in trigger rotation mode. ADC2 works independently */
|
||||||
#define ADC_ALL_REGULAL_PARALLEL_INSERTED_PARALLEL SYNCCTL_SYNCM(17) /*!< all ADCs work in combined regular parallel & inserted parallel mode */
|
#define ADC_ALL_ROUTINE_PARALLEL_INSERTED_PARALLEL SYNCCTL_SYNCM(17) /*!< all ADCs work in combined routine parallel & inserted parallel mode */
|
||||||
#define ADC_ALL_REGULAL_PARALLEL_INSERTED_ROTATION SYNCCTL_SYNCM(18) /*!< all ADCs work in combined regular parallel & trigger rotation mode */
|
#define ADC_ALL_ROUTINE_PARALLEL_INSERTED_ROTATION SYNCCTL_SYNCM(18) /*!< all ADCs work in combined routine parallel & trigger rotation mode */
|
||||||
#define ADC_ALL_INSERTED_PARALLEL SYNCCTL_SYNCM(21) /*!< all ADCs work in inserted parallel mode */
|
#define ADC_ALL_INSERTED_PARALLEL SYNCCTL_SYNCM(21) /*!< all ADCs work in inserted parallel mode */
|
||||||
#define ADC_ALL_REGULAL_PARALLEL SYNCCTL_SYNCM(22) /*!< all ADCs work in regular parallel mode */
|
#define ADC_ALL_ROUTINE_PARALLEL SYNCCTL_SYNCM(22) /*!< all ADCs work in routine parallel mode */
|
||||||
#define ADC_ALL_REGULAL_FOLLOW_UP SYNCCTL_SYNCM(23) /*!< all ADCs work in follow-up mode */
|
#define ADC_ALL_ROUTINE_FOLLOW_UP SYNCCTL_SYNCM(23) /*!< all ADCs work in follow-up mode */
|
||||||
#define ADC_ALL_INSERTED_TRRIGGER_ROTATION SYNCCTL_SYNCM(25) /*!< all ADCs work in trigger rotation mode */
|
#define ADC_ALL_INSERTED_TRRIGGER_ROTATION SYNCCTL_SYNCM(25) /*!< all ADCs work in trigger rotation mode */
|
||||||
|
|
||||||
/* ADC data alignment */
|
/* ADC data alignment */
|
||||||
#define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000U) /*!< LSB alignment */
|
#define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000U) /*!< LSB alignment */
|
||||||
#define ADC_DATAALIGN_LEFT ADC_CTL1_DAL /*!< MSB alignment */
|
#define ADC_DATAALIGN_LEFT ADC_CTL1_DAL /*!< MSB alignment */
|
||||||
|
|
||||||
/* external trigger mode for regular and inserted channel */
|
/* external trigger mode for routine and inserted channel */
|
||||||
#define EXTERNAL_TRIGGER_DISABLE ((uint32_t)0x00000000U) /*!< external trigger disable */
|
#define EXTERNAL_TRIGGER_DISABLE ((uint32_t)0x00000000U) /*!< external trigger disable */
|
||||||
#define EXTERNAL_TRIGGER_RISING ((uint32_t)0x00000001U) /*!< rising edge of external trigger */
|
#define EXTERNAL_TRIGGER_RISING ((uint32_t)0x00000001U) /*!< rising edge of external trigger */
|
||||||
#define EXTERNAL_TRIGGER_FALLING ((uint32_t)0x00000002U) /*!< falling edge of external trigger */
|
#define EXTERNAL_TRIGGER_FALLING ((uint32_t)0x00000002U) /*!< falling edge of external trigger */
|
||||||
#define EXTERNAL_TRIGGER_RISING_FALLING ((uint32_t)0x00000003U) /*!< rising and falling edge of external trigger */
|
#define EXTERNAL_TRIGGER_RISING_FALLING ((uint32_t)0x00000003U) /*!< rising and falling edge of external trigger */
|
||||||
|
|
||||||
/* ADC external trigger select for regular channel */
|
/* ADC external trigger select for routine channel */
|
||||||
#define CTL1_ETSRC(regval) (BITS(24,27) & ((uint32_t)(regval) << 24))
|
#define CTL1_ETSRC(regval) (BITS(24,27) & ((uint32_t)(regval) << 24))
|
||||||
#define ADC_EXTTRIG_REGULAR_T0_CH0 CTL1_ETSRC(0) /*!< timer 0 CC0 event select */
|
#define ADC_EXTTRIG_ROUTINE_T0_CH0 CTL1_ETSRC(0) /*!< timer 0 CC0 event select */
|
||||||
#define ADC_EXTTRIG_REGULAR_T0_CH1 CTL1_ETSRC(1) /*!< timer 0 CC1 event select */
|
#define ADC_EXTTRIG_ROUTINE_T0_CH1 CTL1_ETSRC(1) /*!< timer 0 CC1 event select */
|
||||||
#define ADC_EXTTRIG_REGULAR_T0_CH2 CTL1_ETSRC(2) /*!< timer 0 CC2 event select */
|
#define ADC_EXTTRIG_ROUTINE_T0_CH2 CTL1_ETSRC(2) /*!< timer 0 CC2 event select */
|
||||||
#define ADC_EXTTRIG_REGULAR_T1_CH1 CTL1_ETSRC(3) /*!< timer 1 CC1 event select */
|
#define ADC_EXTTRIG_ROUTINE_T1_CH1 CTL1_ETSRC(3) /*!< timer 1 CC1 event select */
|
||||||
#define ADC_EXTTRIG_REGULAR_T1_CH2 CTL1_ETSRC(4) /*!< timer 1 CC2 event select */
|
#define ADC_EXTTRIG_ROUTINE_T1_CH2 CTL1_ETSRC(4) /*!< timer 1 CC2 event select */
|
||||||
#define ADC_EXTTRIG_REGULAR_T1_CH3 CTL1_ETSRC(5) /*!< timer 1 CC3 event select */
|
#define ADC_EXTTRIG_ROUTINE_T1_CH3 CTL1_ETSRC(5) /*!< timer 1 CC3 event select */
|
||||||
#define ADC_EXTTRIG_REGULAR_T1_TRGO CTL1_ETSRC(6) /*!< timer 1 TRGO event select */
|
#define ADC_EXTTRIG_ROUTINE_T1_TRGO CTL1_ETSRC(6) /*!< timer 1 TRGO event select */
|
||||||
#define ADC_EXTTRIG_REGULAR_T2_CH0 CTL1_ETSRC(7) /*!< timer 2 CC0 event select */
|
#define ADC_EXTTRIG_ROUTINE_T2_CH0 CTL1_ETSRC(7) /*!< timer 2 CC0 event select */
|
||||||
#define ADC_EXTTRIG_REGULAR_T2_TRGO CTL1_ETSRC(8) /*!< timer 2 TRGO event select */
|
#define ADC_EXTTRIG_ROUTINE_T2_TRGO CTL1_ETSRC(8) /*!< timer 2 TRGO event select */
|
||||||
#define ADC_EXTTRIG_REGULAR_T3_CH3 CTL1_ETSRC(9) /*!< timer 3 CC3 event select */
|
#define ADC_EXTTRIG_ROUTINE_T3_CH3 CTL1_ETSRC(9) /*!< timer 3 CC3 event select */
|
||||||
#define ADC_EXTTRIG_REGULAR_T4_CH0 CTL1_ETSRC(10) /*!< timer 4 CC0 event select */
|
#define ADC_EXTTRIG_ROUTINE_T4_CH0 CTL1_ETSRC(10) /*!< timer 4 CC0 event select */
|
||||||
#define ADC_EXTTRIG_REGULAR_T4_CH1 CTL1_ETSRC(11) /*!< timer 4 CC1 event select */
|
#define ADC_EXTTRIG_ROUTINE_T4_CH1 CTL1_ETSRC(11) /*!< timer 4 CC1 event select */
|
||||||
#define ADC_EXTTRIG_REGULAR_T4_CH2 CTL1_ETSRC(12) /*!< timer 4 CC2 event select */
|
#define ADC_EXTTRIG_ROUTINE_T4_CH2 CTL1_ETSRC(12) /*!< timer 4 CC2 event select */
|
||||||
#define ADC_EXTTRIG_REGULAR_T7_CH0 CTL1_ETSRC(13) /*!< timer 7 CC0 event select */
|
#define ADC_EXTTRIG_ROUTINE_T7_CH0 CTL1_ETSRC(13) /*!< timer 7 CC0 event select */
|
||||||
#define ADC_EXTTRIG_REGULAR_T7_TRGO CTL1_ETSRC(14) /*!< timer 7 TRGO event select */
|
#define ADC_EXTTRIG_ROUTINE_T7_TRGO CTL1_ETSRC(14) /*!< timer 7 TRGO event select */
|
||||||
#define ADC_EXTTRIG_REGULAR_EXTI_11 CTL1_ETSRC(15) /*!< extiline 11 select */
|
#define ADC_EXTTRIG_ROUTINE_EXTI_11 CTL1_ETSRC(15) /*!< extiline 11 select */
|
||||||
|
|
||||||
/* ADC external trigger select for inserted channel */
|
/* ADC external trigger select for inserted channel */
|
||||||
#define CTL1_ETSIC(regval) (BITS(16,19) & ((uint32_t)(regval) << 16))
|
#define CTL1_ETSIC(regval) (BITS(16,19) & ((uint32_t)(regval) << 16))
|
||||||
|
|
@ -318,15 +319,15 @@ OF SUCH DAMAGE.
|
||||||
#define ADC_OVERSAMPLING_RATIO_MUL128 OVSAMPCTL_OVSR(6) /*!< oversampling ratio multiple 128 */
|
#define ADC_OVERSAMPLING_RATIO_MUL128 OVSAMPCTL_OVSR(6) /*!< oversampling ratio multiple 128 */
|
||||||
#define ADC_OVERSAMPLING_RATIO_MUL256 OVSAMPCTL_OVSR(7) /*!< oversampling ratio multiple 256 */
|
#define ADC_OVERSAMPLING_RATIO_MUL256 OVSAMPCTL_OVSR(7) /*!< oversampling ratio multiple 256 */
|
||||||
|
|
||||||
/* triggered Oversampling */
|
/* triggered oversampling */
|
||||||
#define ADC_OVERSAMPLING_ALL_CONVERT ((uint32_t)0x00000000U) /*!< all oversampled conversions for a channel are done consecutively after a trigger */
|
#define ADC_OVERSAMPLING_ALL_CONVERT ((uint32_t)0x00000000U) /*!< all oversampled conversions for a channel are done consecutively after a trigger */
|
||||||
#define ADC_OVERSAMPLING_ONE_CONVERT ADC_OVSAMPCTL_TOVS /*!< each oversampled conversion for a channel needs a trigger */
|
#define ADC_OVERSAMPLING_ONE_CONVERT ADC_OVSAMPCTL_TOVS /*!< each oversampled conversion for a channel needs a trigger */
|
||||||
|
|
||||||
/* ADC channel group definitions */
|
/* ADC channel sequence definitions */
|
||||||
#define ADC_REGULAR_CHANNEL ((uint8_t)0x01U) /*!< adc regular channel group */
|
#define ADC_ROUTINE_CHANNEL ((uint8_t)0x01U) /*!< adc routine sequence */
|
||||||
#define ADC_INSERTED_CHANNEL ((uint8_t)0x02U) /*!< adc inserted channel group */
|
#define ADC_INSERTED_CHANNEL ((uint8_t)0x02U) /*!< adc inserted sequence */
|
||||||
#define ADC_REGULAR_INSERTED_CHANNEL ((uint8_t)0x03U) /*!< both regular and inserted channel group */
|
#define ADC_ROUTINE_INSERTED_CHANNEL ((uint8_t)0x03U) /*!< both routine and inserted sequence */
|
||||||
#define ADC_CHANNEL_DISCON_DISABLE ((uint8_t)0x04U) /*!< disable discontinuous mode of regular & inserted channel */
|
#define ADC_CHANNEL_DISCON_DISABLE ((uint8_t)0x04U) /*!< disable discontinuous mode of routine & inserted sequence */
|
||||||
|
|
||||||
/* ADC inserted channel definitions */
|
/* ADC inserted channel definitions */
|
||||||
#define ADC_INSERTED_CHANNEL_0 ((uint8_t)0x00U) /*!< adc inserted channel 0 */
|
#define ADC_INSERTED_CHANNEL_0 ((uint8_t)0x00U) /*!< adc inserted channel 0 */
|
||||||
|
|
@ -357,15 +358,15 @@ OF SUCH DAMAGE.
|
||||||
|
|
||||||
/* ADC interrupt flag */
|
/* ADC interrupt flag */
|
||||||
#define ADC_INT_WDE ADC_CTL0_WDEIE /*!< analog watchdog event interrupt */
|
#define ADC_INT_WDE ADC_CTL0_WDEIE /*!< analog watchdog event interrupt */
|
||||||
#define ADC_INT_EOC ADC_CTL0_EOCIE /*!< end of group conversion interrupt */
|
#define ADC_INT_EOC ADC_CTL0_EOCIE /*!< end of sequence conversion interrupt */
|
||||||
#define ADC_INT_EOIC ADC_CTL0_EOICIE /*!< end of inserted group conversion interrupt */
|
#define ADC_INT_EOIC ADC_CTL0_EOICIE /*!< end of inserted sequence conversion interrupt */
|
||||||
#define ADC_INT_ROVF ADC_CTL0_ROVFIE /*!< regular data register overflow */
|
#define ADC_INT_ROVF ADC_CTL0_ROVFIE /*!< routine data register overflow */
|
||||||
|
|
||||||
/* ADC interrupt flag */
|
/* ADC interrupt flag */
|
||||||
#define ADC_INT_FLAG_WDE ADC_STAT_WDE /*!< analog watchdog event interrupt */
|
#define ADC_INT_FLAG_WDE ADC_STAT_WDE /*!< analog watchdog event interrupt */
|
||||||
#define ADC_INT_FLAG_EOC ADC_STAT_EOC /*!< end of group conversion interrupt */
|
#define ADC_INT_FLAG_EOC ADC_STAT_EOC /*!< end of sequence conversion interrupt */
|
||||||
#define ADC_INT_FLAG_EOIC ADC_STAT_EOIC /*!< end of inserted group conversion interrupt */
|
#define ADC_INT_FLAG_EOIC ADC_STAT_EOIC /*!< end of inserted sequence conversion interrupt */
|
||||||
#define ADC_INT_FLAG_ROVF ADC_STAT_ROVF /*!< regular data register overflow */
|
#define ADC_INT_FLAG_ROVF ADC_STAT_ROVF /*!< routine data register overflow */
|
||||||
|
|
||||||
/* configure the ADC clock for all the ADCs */
|
/* configure the ADC clock for all the ADCs */
|
||||||
#define SYNCCTL_ADCCK(regval) (BITS(16,18) & ((uint32_t)(regval) << 16))
|
#define SYNCCTL_ADCCK(regval) (BITS(16,18) & ((uint32_t)(regval) << 16))
|
||||||
|
|
@ -402,8 +403,8 @@ OF SUCH DAMAGE.
|
||||||
#define ADC_SYNC_DMA_MODE1 ((uint32_t)0x00008000U) /*!< ADC synchronization DMA mode 1 */
|
#define ADC_SYNC_DMA_MODE1 ((uint32_t)0x00008000U) /*!< ADC synchronization DMA mode 1 */
|
||||||
|
|
||||||
/* end of conversion mode */
|
/* end of conversion mode */
|
||||||
#define ADC_EOC_SET_SEQUENCE ((uint8_t)0x00U) /*!< only at the end of a sequence of regular conversions, the EOC bit is set */
|
#define ADC_EOC_SET_SEQUENCE ((uint8_t)0x00U) /*!< only at the end of a sequence of routine conversions, the EOC bit is set */
|
||||||
#define ADC_EOC_SET_CONVERSION ((uint8_t)0x01U) /*!< at the end of each regular conversion, the EOC bit is set */
|
#define ADC_EOC_SET_CONVERSION ((uint8_t)0x01U) /*!< at the end of each routine conversion, the EOC bit is set */
|
||||||
|
|
||||||
/* function declarations */
|
/* function declarations */
|
||||||
/* initialization config */
|
/* initialization config */
|
||||||
|
|
@ -437,35 +438,35 @@ void adc_oversample_mode_disable(uint32_t adc_periph);
|
||||||
void adc_dma_mode_enable(uint32_t adc_periph);
|
void adc_dma_mode_enable(uint32_t adc_periph);
|
||||||
/* disable DMA request */
|
/* disable DMA request */
|
||||||
void adc_dma_mode_disable(uint32_t adc_periph);
|
void adc_dma_mode_disable(uint32_t adc_periph);
|
||||||
/* when DMA=1, the DMA engine issues a request at end of each regular conversion */
|
/* when DMA=1, the DMA engine issues a request at end of each routine conversion */
|
||||||
void adc_dma_request_after_last_enable(uint32_t adc_periph);
|
void adc_dma_request_after_last_enable(uint32_t adc_periph);
|
||||||
/* the DMA engine is disabled after the end of transfer signal from DMA controller is detected */
|
/* the DMA engine is disabled after the end of transfer signal from DMA controller is detected */
|
||||||
void adc_dma_request_after_last_disable(uint32_t adc_periph);
|
void adc_dma_request_after_last_disable(uint32_t adc_periph);
|
||||||
|
|
||||||
/* regular group and inserted group config */
|
/* routine sequence and inserted sequence config */
|
||||||
/* configure ADC discontinuous mode */
|
/* configure ADC discontinuous mode */
|
||||||
void adc_discontinuous_mode_config(uint32_t adc_periph , uint8_t adc_channel_group , uint8_t length);
|
void adc_discontinuous_mode_config(uint32_t adc_periph , uint8_t adc_sequence , uint8_t length);
|
||||||
/* configure the length of regular channel group or inserted channel group */
|
/* configure the length of routine sequence or inserted sequence */
|
||||||
void adc_channel_length_config(uint32_t adc_periph , uint8_t adc_channel_group , uint32_t length);
|
void adc_channel_length_config(uint32_t adc_periph , uint8_t adc_sequence , uint32_t length);
|
||||||
/* configure ADC regular channel */
|
/* configure ADC routine channel */
|
||||||
void adc_regular_channel_config(uint32_t adc_periph , uint8_t rank , uint8_t adc_channel , uint32_t sample_time);
|
void adc_routine_channel_config(uint32_t adc_periph , uint8_t rank , uint8_t adc_channel , uint32_t sample_time);
|
||||||
/* configure ADC inserted channel */
|
/* configure ADC inserted channel */
|
||||||
void adc_inserted_channel_config(uint32_t adc_periph , uint8_t rank , uint8_t adc_channel , uint32_t sample_time);
|
void adc_inserted_channel_config(uint32_t adc_periph , uint8_t rank , uint8_t adc_channel , uint32_t sample_time);
|
||||||
/* configure ADC inserted channel offset */
|
/* configure ADC inserted channel offset */
|
||||||
void adc_inserted_channel_offset_config(uint32_t adc_periph , uint8_t inserted_channel , uint16_t offset);
|
void adc_inserted_channel_offset_config(uint32_t adc_periph , uint8_t inserted_channel , uint16_t offset);
|
||||||
/* configure ADC external trigger source */
|
/* configure ADC external trigger source */
|
||||||
void adc_external_trigger_source_config(uint32_t adc_periph , uint8_t adc_channel_group , uint32_t external_trigger_source);
|
void adc_external_trigger_source_config(uint32_t adc_periph , uint8_t adc_sequence , uint32_t external_trigger_source);
|
||||||
/* enable ADC external trigger */
|
/* enable ADC external trigger */
|
||||||
void adc_external_trigger_config(uint32_t adc_periph , uint8_t adc_channel_group , uint32_t trigger_mode);
|
void adc_external_trigger_config(uint32_t adc_periph , uint8_t adc_sequence , uint32_t trigger_mode);
|
||||||
/* enable ADC software trigger */
|
/* enable ADC software trigger */
|
||||||
void adc_software_trigger_enable(uint32_t adc_periph , uint8_t adc_channel_group);
|
void adc_software_trigger_enable(uint32_t adc_periph , uint8_t adc_sequence);
|
||||||
/* configure end of conversion mode */
|
/* configure end of conversion mode */
|
||||||
void adc_end_of_conversion_config(uint32_t adc_periph , uint8_t end_selection);
|
void adc_end_of_conversion_config(uint32_t adc_periph , uint8_t end_selection);
|
||||||
|
|
||||||
/* get channel data */
|
/* get channel data */
|
||||||
/* read ADC regular group data register */
|
/* read ADC routine data register */
|
||||||
uint16_t adc_regular_data_read(uint32_t adc_periph);
|
uint16_t adc_routine_data_read(uint32_t adc_periph);
|
||||||
/* read ADC inserted group data register */
|
/* read ADC inserted data register */
|
||||||
uint16_t adc_inserted_data_read(uint32_t adc_periph , uint8_t inserted_channel);
|
uint16_t adc_inserted_data_read(uint32_t adc_periph , uint8_t inserted_channel);
|
||||||
|
|
||||||
/* watchdog config */
|
/* watchdog config */
|
||||||
|
|
@ -473,10 +474,10 @@ uint16_t adc_inserted_data_read(uint32_t adc_periph , uint8_t inserted_channel);
|
||||||
void adc_watchdog_single_channel_disable(uint32_t adc_periph );
|
void adc_watchdog_single_channel_disable(uint32_t adc_periph );
|
||||||
/* enable ADC analog watchdog single channel */
|
/* enable ADC analog watchdog single channel */
|
||||||
void adc_watchdog_single_channel_enable(uint32_t adc_periph , uint8_t adc_channel);
|
void adc_watchdog_single_channel_enable(uint32_t adc_periph , uint8_t adc_channel);
|
||||||
/* configure ADC analog watchdog group channel */
|
/* configure ADC analog watchdog sequence */
|
||||||
void adc_watchdog_group_channel_enable(uint32_t adc_periph , uint8_t adc_channel_group);
|
void adc_watchdog_sequence_channel_enable(uint32_t adc_periph , uint8_t adc_sequence);
|
||||||
/* disable ADC analog watchdog */
|
/* disable ADC analog watchdog */
|
||||||
void adc_watchdog_disable(uint32_t adc_periph , uint8_t adc_channel_group);
|
void adc_watchdog_disable(uint32_t adc_periph , uint8_t adc_sequence);
|
||||||
/* configure ADC analog watchdog threshold */
|
/* configure ADC analog watchdog threshold */
|
||||||
void adc_watchdog_threshold_config(uint32_t adc_periph , uint16_t low_threshold , uint16_t high_threshold);
|
void adc_watchdog_threshold_config(uint32_t adc_periph , uint16_t low_threshold , uint16_t high_threshold);
|
||||||
|
|
||||||
|
|
@ -486,7 +487,7 @@ FlagStatus adc_flag_get(uint32_t adc_periph , uint32_t adc_flag);
|
||||||
/* clear the ADC flag bits */
|
/* clear the ADC flag bits */
|
||||||
void adc_flag_clear(uint32_t adc_periph , uint32_t adc_flag);
|
void adc_flag_clear(uint32_t adc_periph , uint32_t adc_flag);
|
||||||
/* get the bit state of ADCx software start conversion */
|
/* get the bit state of ADCx software start conversion */
|
||||||
FlagStatus adc_regular_software_startconv_flag_get(uint32_t adc_periph);
|
FlagStatus adc_routine_software_startconv_flag_get(uint32_t adc_periph);
|
||||||
/* get the bit state of ADCx software inserted channel start conversion */
|
/* get the bit state of ADCx software inserted channel start conversion */
|
||||||
FlagStatus adc_inserted_software_startconv_flag_get(uint32_t adc_periph);
|
FlagStatus adc_inserted_software_startconv_flag_get(uint32_t adc_periph);
|
||||||
/* get the ADC interrupt bits */
|
/* get the ADC interrupt bits */
|
||||||
|
|
@ -509,7 +510,7 @@ void adc_sync_dma_config(uint32_t dma_mode );
|
||||||
void adc_sync_dma_request_after_last_enable(void);
|
void adc_sync_dma_request_after_last_enable(void);
|
||||||
/* configure ADC sync DMA engine issues requests according to the SYNCDMA bits */
|
/* configure ADC sync DMA engine issues requests according to the SYNCDMA bits */
|
||||||
void adc_sync_dma_request_after_last_disable(void);
|
void adc_sync_dma_request_after_last_disable(void);
|
||||||
/* read ADC sync regular data register */
|
/* read ADC sync routine data register */
|
||||||
uint32_t adc_sync_regular_data_read(void);
|
uint32_t adc_sync_routine_data_read(void);
|
||||||
|
|
||||||
#endif /* GD32F4XX_ADC_H */
|
#endif /* GD32F4XX_ADC_H */
|
||||||
|
|
|
||||||
|
|
@ -6,10 +6,11 @@
|
||||||
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
||||||
\version 2019-11-27, V2.0.1, firmware for GD32F4xx
|
\version 2019-11-27, V2.0.1, firmware for GD32F4xx
|
||||||
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
||||||
|
\version 2022-03-09, V3.0.0, firmware for GD32F4xx
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/*
|
/*
|
||||||
Copyright (c) 2020, GigaDevice Semiconductor Inc.
|
Copyright (c) 2022, GigaDevice Semiconductor Inc.
|
||||||
|
|
||||||
Redistribution and use in source and binary forms, with or without modification,
|
Redistribution and use in source and binary forms, with or without modification,
|
||||||
are permitted provided that the following conditions are met:
|
are permitted provided that the following conditions are met:
|
||||||
|
|
@ -35,6 +36,7 @@ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSI
|
||||||
OF SUCH DAMAGE.
|
OF SUCH DAMAGE.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
|
|
||||||
#ifndef GD32F4XX_CAN_H
|
#ifndef GD32F4XX_CAN_H
|
||||||
#define GD32F4XX_CAN_H
|
#define GD32F4XX_CAN_H
|
||||||
|
|
||||||
|
|
@ -45,95 +47,95 @@ OF SUCH DAMAGE.
|
||||||
#define CAN1 (CAN0 + 0x00000400U) /*!< CAN1 base address */
|
#define CAN1 (CAN0 + 0x00000400U) /*!< CAN1 base address */
|
||||||
|
|
||||||
/* registers definitions */
|
/* registers definitions */
|
||||||
#define CAN_CTL(canx) REG32((canx) + 0x00U) /*!< CAN control register */
|
#define CAN_CTL(canx) REG32((canx) + 0x00000000U) /*!< CAN control register */
|
||||||
#define CAN_STAT(canx) REG32((canx) + 0x04U) /*!< CAN status register */
|
#define CAN_STAT(canx) REG32((canx) + 0x00000004U) /*!< CAN status register */
|
||||||
#define CAN_TSTAT(canx) REG32((canx) + 0x08U) /*!< CAN transmit status register*/
|
#define CAN_TSTAT(canx) REG32((canx) + 0x00000008U) /*!< CAN transmit status register*/
|
||||||
#define CAN_RFIFO0(canx) REG32((canx) + 0x0CU) /*!< CAN receive FIFO0 register */
|
#define CAN_RFIFO0(canx) REG32((canx) + 0x0000000CU) /*!< CAN receive FIFO0 register */
|
||||||
#define CAN_RFIFO1(canx) REG32((canx) + 0x10U) /*!< CAN receive FIFO1 register */
|
#define CAN_RFIFO1(canx) REG32((canx) + 0x00000010U) /*!< CAN receive FIFO1 register */
|
||||||
#define CAN_INTEN(canx) REG32((canx) + 0x14U) /*!< CAN interrupt enable register */
|
#define CAN_INTEN(canx) REG32((canx) + 0x00000014U) /*!< CAN interrupt enable register */
|
||||||
#define CAN_ERR(canx) REG32((canx) + 0x18U) /*!< CAN error register */
|
#define CAN_ERR(canx) REG32((canx) + 0x00000018U) /*!< CAN error register */
|
||||||
#define CAN_BT(canx) REG32((canx) + 0x1CU) /*!< CAN bit timing register */
|
#define CAN_BT(canx) REG32((canx) + 0x0000001CU) /*!< CAN bit timing register */
|
||||||
#define CAN_TMI0(canx) REG32((canx) + 0x180U) /*!< CAN transmit mailbox0 identifier register */
|
#define CAN_TMI0(canx) REG32((canx) + 0x00000180U) /*!< CAN transmit mailbox0 identifier register */
|
||||||
#define CAN_TMP0(canx) REG32((canx) + 0x184U) /*!< CAN transmit mailbox0 property register */
|
#define CAN_TMP0(canx) REG32((canx) + 0x00000184U) /*!< CAN transmit mailbox0 property register */
|
||||||
#define CAN_TMDATA00(canx) REG32((canx) + 0x188U) /*!< CAN transmit mailbox0 data0 register */
|
#define CAN_TMDATA00(canx) REG32((canx) + 0x00000188U) /*!< CAN transmit mailbox0 data0 register */
|
||||||
#define CAN_TMDATA10(canx) REG32((canx) + 0x18CU) /*!< CAN transmit mailbox0 data1 register */
|
#define CAN_TMDATA10(canx) REG32((canx) + 0x0000018CU) /*!< CAN transmit mailbox0 data1 register */
|
||||||
#define CAN_TMI1(canx) REG32((canx) + 0x190U) /*!< CAN transmit mailbox1 identifier register */
|
#define CAN_TMI1(canx) REG32((canx) + 0x00000190U) /*!< CAN transmit mailbox1 identifier register */
|
||||||
#define CAN_TMP1(canx) REG32((canx) + 0x194U) /*!< CAN transmit mailbox1 property register */
|
#define CAN_TMP1(canx) REG32((canx) + 0x00000194U) /*!< CAN transmit mailbox1 property register */
|
||||||
#define CAN_TMDATA01(canx) REG32((canx) + 0x198U) /*!< CAN transmit mailbox1 data0 register */
|
#define CAN_TMDATA01(canx) REG32((canx) + 0x00000198U) /*!< CAN transmit mailbox1 data0 register */
|
||||||
#define CAN_TMDATA11(canx) REG32((canx) + 0x19CU) /*!< CAN transmit mailbox1 data1 register */
|
#define CAN_TMDATA11(canx) REG32((canx) + 0x0000019CU) /*!< CAN transmit mailbox1 data1 register */
|
||||||
#define CAN_TMI2(canx) REG32((canx) + 0x1A0U) /*!< CAN transmit mailbox2 identifier register */
|
#define CAN_TMI2(canx) REG32((canx) + 0x000001A0U) /*!< CAN transmit mailbox2 identifier register */
|
||||||
#define CAN_TMP2(canx) REG32((canx) + 0x1A4U) /*!< CAN transmit mailbox2 property register */
|
#define CAN_TMP2(canx) REG32((canx) + 0x000001A4U) /*!< CAN transmit mailbox2 property register */
|
||||||
#define CAN_TMDATA02(canx) REG32((canx) + 0x1A8U) /*!< CAN transmit mailbox2 data0 register */
|
#define CAN_TMDATA02(canx) REG32((canx) + 0x000001A8U) /*!< CAN transmit mailbox2 data0 register */
|
||||||
#define CAN_TMDATA12(canx) REG32((canx) + 0x1ACU) /*!< CAN transmit mailbox2 data1 register */
|
#define CAN_TMDATA12(canx) REG32((canx) + 0x000001ACU) /*!< CAN transmit mailbox2 data1 register */
|
||||||
#define CAN_RFIFOMI0(canx) REG32((canx) + 0x1B0U) /*!< CAN receive FIFO0 mailbox identifier register */
|
#define CAN_RFIFOMI0(canx) REG32((canx) + 0x000001B0U) /*!< CAN receive FIFO0 mailbox identifier register */
|
||||||
#define CAN_RFIFOMP0(canx) REG32((canx) + 0x1B4U) /*!< CAN receive FIFO0 mailbox property register */
|
#define CAN_RFIFOMP0(canx) REG32((canx) + 0x000001B4U) /*!< CAN receive FIFO0 mailbox property register */
|
||||||
#define CAN_RFIFOMDATA00(canx) REG32((canx) + 0x1B8U) /*!< CAN receive FIFO0 mailbox data0 register */
|
#define CAN_RFIFOMDATA00(canx) REG32((canx) + 0x000001B8U) /*!< CAN receive FIFO0 mailbox data0 register */
|
||||||
#define CAN_RFIFOMDATA10(canx) REG32((canx) + 0x1BCU) /*!< CAN receive FIFO0 mailbox data1 register */
|
#define CAN_RFIFOMDATA10(canx) REG32((canx) + 0x000001BCU) /*!< CAN receive FIFO0 mailbox data1 register */
|
||||||
#define CAN_RFIFOMI1(canx) REG32((canx) + 0x1C0U) /*!< CAN receive FIFO1 mailbox identifier register */
|
#define CAN_RFIFOMI1(canx) REG32((canx) + 0x000001C0U) /*!< CAN receive FIFO1 mailbox identifier register */
|
||||||
#define CAN_RFIFOMP1(canx) REG32((canx) + 0x1C4U) /*!< CAN receive FIFO1 mailbox property register */
|
#define CAN_RFIFOMP1(canx) REG32((canx) + 0x000001C4U) /*!< CAN receive FIFO1 mailbox property register */
|
||||||
#define CAN_RFIFOMDATA01(canx) REG32((canx) + 0x1C8U) /*!< CAN receive FIFO1 mailbox data0 register */
|
#define CAN_RFIFOMDATA01(canx) REG32((canx) + 0x000001C8U) /*!< CAN receive FIFO1 mailbox data0 register */
|
||||||
#define CAN_RFIFOMDATA11(canx) REG32((canx) + 0x1CCU) /*!< CAN receive FIFO1 mailbox data1 register */
|
#define CAN_RFIFOMDATA11(canx) REG32((canx) + 0x000001CCU) /*!< CAN receive FIFO1 mailbox data1 register */
|
||||||
#define CAN_FCTL(canx) REG32((canx) + 0x200U) /*!< CAN filter control register */
|
#define CAN_FCTL(canx) REG32((canx) + 0x00000200U) /*!< CAN filter control register */
|
||||||
#define CAN_FMCFG(canx) REG32((canx) + 0x204U) /*!< CAN filter mode register */
|
#define CAN_FMCFG(canx) REG32((canx) + 0x00000204U) /*!< CAN filter mode register */
|
||||||
#define CAN_FSCFG(canx) REG32((canx) + 0x20CU) /*!< CAN filter scale register */
|
#define CAN_FSCFG(canx) REG32((canx) + 0x0000020CU) /*!< CAN filter scale register */
|
||||||
#define CAN_FAFIFO(canx) REG32((canx) + 0x214U) /*!< CAN filter associated FIFO register */
|
#define CAN_FAFIFO(canx) REG32((canx) + 0x00000214U) /*!< CAN filter associated FIFO register */
|
||||||
#define CAN_FW(canx) REG32((canx) + 0x21CU) /*!< CAN filter working register */
|
#define CAN_FW(canx) REG32((canx) + 0x0000021CU) /*!< CAN filter working register */
|
||||||
#define CAN_F0DATA0(canx) REG32((canx) + 0x240U) /*!< CAN filter 0 data 0 register */
|
#define CAN_F0DATA0(canx) REG32((canx) + 0x00000240U) /*!< CAN filter 0 data 0 register */
|
||||||
#define CAN_F1DATA0(canx) REG32((canx) + 0x248U) /*!< CAN filter 1 data 0 register */
|
#define CAN_F1DATA0(canx) REG32((canx) + 0x00000248U) /*!< CAN filter 1 data 0 register */
|
||||||
#define CAN_F2DATA0(canx) REG32((canx) + 0x250U) /*!< CAN filter 2 data 0 register */
|
#define CAN_F2DATA0(canx) REG32((canx) + 0x00000250U) /*!< CAN filter 2 data 0 register */
|
||||||
#define CAN_F3DATA0(canx) REG32((canx) + 0x258U) /*!< CAN filter 3 data 0 register */
|
#define CAN_F3DATA0(canx) REG32((canx) + 0x00000258U) /*!< CAN filter 3 data 0 register */
|
||||||
#define CAN_F4DATA0(canx) REG32((canx) + 0x260U) /*!< CAN filter 4 data 0 register */
|
#define CAN_F4DATA0(canx) REG32((canx) + 0x00000260U) /*!< CAN filter 4 data 0 register */
|
||||||
#define CAN_F5DATA0(canx) REG32((canx) + 0x268U) /*!< CAN filter 5 data 0 register */
|
#define CAN_F5DATA0(canx) REG32((canx) + 0x00000268U) /*!< CAN filter 5 data 0 register */
|
||||||
#define CAN_F6DATA0(canx) REG32((canx) + 0x270U) /*!< CAN filter 6 data 0 register */
|
#define CAN_F6DATA0(canx) REG32((canx) + 0x00000270U) /*!< CAN filter 6 data 0 register */
|
||||||
#define CAN_F7DATA0(canx) REG32((canx) + 0x278U) /*!< CAN filter 7 data 0 register */
|
#define CAN_F7DATA0(canx) REG32((canx) + 0x00000278U) /*!< CAN filter 7 data 0 register */
|
||||||
#define CAN_F8DATA0(canx) REG32((canx) + 0x280U) /*!< CAN filter 8 data 0 register */
|
#define CAN_F8DATA0(canx) REG32((canx) + 0x00000280U) /*!< CAN filter 8 data 0 register */
|
||||||
#define CAN_F9DATA0(canx) REG32((canx) + 0x288U) /*!< CAN filter 9 data 0 register */
|
#define CAN_F9DATA0(canx) REG32((canx) + 0x00000288U) /*!< CAN filter 9 data 0 register */
|
||||||
#define CAN_F10DATA0(canx) REG32((canx) + 0x290U) /*!< CAN filter 10 data 0 register */
|
#define CAN_F10DATA0(canx) REG32((canx) + 0x00000290U) /*!< CAN filter 10 data 0 register */
|
||||||
#define CAN_F11DATA0(canx) REG32((canx) + 0x298U) /*!< CAN filter 11 data 0 register */
|
#define CAN_F11DATA0(canx) REG32((canx) + 0x00000298U) /*!< CAN filter 11 data 0 register */
|
||||||
#define CAN_F12DATA0(canx) REG32((canx) + 0x2A0U) /*!< CAN filter 12 data 0 register */
|
#define CAN_F12DATA0(canx) REG32((canx) + 0x000002A0U) /*!< CAN filter 12 data 0 register */
|
||||||
#define CAN_F13DATA0(canx) REG32((canx) + 0x2A8U) /*!< CAN filter 13 data 0 register */
|
#define CAN_F13DATA0(canx) REG32((canx) + 0x000002A8U) /*!< CAN filter 13 data 0 register */
|
||||||
#define CAN_F14DATA0(canx) REG32((canx) + 0x2B0U) /*!< CAN filter 14 data 0 register */
|
#define CAN_F14DATA0(canx) REG32((canx) + 0x000002B0U) /*!< CAN filter 14 data 0 register */
|
||||||
#define CAN_F15DATA0(canx) REG32((canx) + 0x2B8U) /*!< CAN filter 15 data 0 register */
|
#define CAN_F15DATA0(canx) REG32((canx) + 0x000002B8U) /*!< CAN filter 15 data 0 register */
|
||||||
#define CAN_F16DATA0(canx) REG32((canx) + 0x2C0U) /*!< CAN filter 16 data 0 register */
|
#define CAN_F16DATA0(canx) REG32((canx) + 0x000002C0U) /*!< CAN filter 16 data 0 register */
|
||||||
#define CAN_F17DATA0(canx) REG32((canx) + 0x2C8U) /*!< CAN filter 17 data 0 register */
|
#define CAN_F17DATA0(canx) REG32((canx) + 0x000002C8U) /*!< CAN filter 17 data 0 register */
|
||||||
#define CAN_F18DATA0(canx) REG32((canx) + 0x2D0U) /*!< CAN filter 18 data 0 register */
|
#define CAN_F18DATA0(canx) REG32((canx) + 0x000002D0U) /*!< CAN filter 18 data 0 register */
|
||||||
#define CAN_F19DATA0(canx) REG32((canx) + 0x2D8U) /*!< CAN filter 19 data 0 register */
|
#define CAN_F19DATA0(canx) REG32((canx) + 0x000002D8U) /*!< CAN filter 19 data 0 register */
|
||||||
#define CAN_F20DATA0(canx) REG32((canx) + 0x2E0U) /*!< CAN filter 20 data 0 register */
|
#define CAN_F20DATA0(canx) REG32((canx) + 0x000002E0U) /*!< CAN filter 20 data 0 register */
|
||||||
#define CAN_F21DATA0(canx) REG32((canx) + 0x2E8U) /*!< CAN filter 21 data 0 register */
|
#define CAN_F21DATA0(canx) REG32((canx) + 0x000002E8U) /*!< CAN filter 21 data 0 register */
|
||||||
#define CAN_F22DATA0(canx) REG32((canx) + 0x2F0U) /*!< CAN filter 22 data 0 register */
|
#define CAN_F22DATA0(canx) REG32((canx) + 0x000002F0U) /*!< CAN filter 22 data 0 register */
|
||||||
#define CAN_F23DATA0(canx) REG32((canx) + 0x3F8U) /*!< CAN filter 23 data 0 register */
|
#define CAN_F23DATA0(canx) REG32((canx) + 0x000003F8U) /*!< CAN filter 23 data 0 register */
|
||||||
#define CAN_F24DATA0(canx) REG32((canx) + 0x300U) /*!< CAN filter 24 data 0 register */
|
#define CAN_F24DATA0(canx) REG32((canx) + 0x00000300U) /*!< CAN filter 24 data 0 register */
|
||||||
#define CAN_F25DATA0(canx) REG32((canx) + 0x308U) /*!< CAN filter 25 data 0 register */
|
#define CAN_F25DATA0(canx) REG32((canx) + 0x00000308U) /*!< CAN filter 25 data 0 register */
|
||||||
#define CAN_F26DATA0(canx) REG32((canx) + 0x310U) /*!< CAN filter 26 data 0 register */
|
#define CAN_F26DATA0(canx) REG32((canx) + 0x00000310U) /*!< CAN filter 26 data 0 register */
|
||||||
#define CAN_F27DATA0(canx) REG32((canx) + 0x318U) /*!< CAN filter 27 data 0 register */
|
#define CAN_F27DATA0(canx) REG32((canx) + 0x00000318U) /*!< CAN filter 27 data 0 register */
|
||||||
#define CAN_F0DATA1(canx) REG32((canx) + 0x244U) /*!< CAN filter 0 data 1 register */
|
#define CAN_F0DATA1(canx) REG32((canx) + 0x00000244U) /*!< CAN filter 0 data 1 register */
|
||||||
#define CAN_F1DATA1(canx) REG32((canx) + 0x24CU) /*!< CAN filter 1 data 1 register */
|
#define CAN_F1DATA1(canx) REG32((canx) + 0x0000024CU) /*!< CAN filter 1 data 1 register */
|
||||||
#define CAN_F2DATA1(canx) REG32((canx) + 0x254U) /*!< CAN filter 2 data 1 register */
|
#define CAN_F2DATA1(canx) REG32((canx) + 0x00000254U) /*!< CAN filter 2 data 1 register */
|
||||||
#define CAN_F3DATA1(canx) REG32((canx) + 0x25CU) /*!< CAN filter 3 data 1 register */
|
#define CAN_F3DATA1(canx) REG32((canx) + 0x0000025CU) /*!< CAN filter 3 data 1 register */
|
||||||
#define CAN_F4DATA1(canx) REG32((canx) + 0x264U) /*!< CAN filter 4 data 1 register */
|
#define CAN_F4DATA1(canx) REG32((canx) + 0x00000264U) /*!< CAN filter 4 data 1 register */
|
||||||
#define CAN_F5DATA1(canx) REG32((canx) + 0x26CU) /*!< CAN filter 5 data 1 register */
|
#define CAN_F5DATA1(canx) REG32((canx) + 0x0000026CU) /*!< CAN filter 5 data 1 register */
|
||||||
#define CAN_F6DATA1(canx) REG32((canx) + 0x274U) /*!< CAN filter 6 data 1 register */
|
#define CAN_F6DATA1(canx) REG32((canx) + 0x00000274U) /*!< CAN filter 6 data 1 register */
|
||||||
#define CAN_F7DATA1(canx) REG32((canx) + 0x27CU) /*!< CAN filter 7 data 1 register */
|
#define CAN_F7DATA1(canx) REG32((canx) + 0x0000027CU) /*!< CAN filter 7 data 1 register */
|
||||||
#define CAN_F8DATA1(canx) REG32((canx) + 0x284U) /*!< CAN filter 8 data 1 register */
|
#define CAN_F8DATA1(canx) REG32((canx) + 0x00000284U) /*!< CAN filter 8 data 1 register */
|
||||||
#define CAN_F9DATA1(canx) REG32((canx) + 0x28CU) /*!< CAN filter 9 data 1 register */
|
#define CAN_F9DATA1(canx) REG32((canx) + 0x0000028CU) /*!< CAN filter 9 data 1 register */
|
||||||
#define CAN_F10DATA1(canx) REG32((canx) + 0x294U) /*!< CAN filter 10 data 1 register */
|
#define CAN_F10DATA1(canx) REG32((canx) + 0x00000294U) /*!< CAN filter 10 data 1 register */
|
||||||
#define CAN_F11DATA1(canx) REG32((canx) + 0x29CU) /*!< CAN filter 11 data 1 register */
|
#define CAN_F11DATA1(canx) REG32((canx) + 0x0000029CU) /*!< CAN filter 11 data 1 register */
|
||||||
#define CAN_F12DATA1(canx) REG32((canx) + 0x2A4U) /*!< CAN filter 12 data 1 register */
|
#define CAN_F12DATA1(canx) REG32((canx) + 0x000002A4U) /*!< CAN filter 12 data 1 register */
|
||||||
#define CAN_F13DATA1(canx) REG32((canx) + 0x2ACU) /*!< CAN filter 13 data 1 register */
|
#define CAN_F13DATA1(canx) REG32((canx) + 0x000002ACU) /*!< CAN filter 13 data 1 register */
|
||||||
#define CAN_F14DATA1(canx) REG32((canx) + 0x2B4U) /*!< CAN filter 14 data 1 register */
|
#define CAN_F14DATA1(canx) REG32((canx) + 0x000002B4U) /*!< CAN filter 14 data 1 register */
|
||||||
#define CAN_F15DATA1(canx) REG32((canx) + 0x2BCU) /*!< CAN filter 15 data 1 register */
|
#define CAN_F15DATA1(canx) REG32((canx) + 0x000002BCU) /*!< CAN filter 15 data 1 register */
|
||||||
#define CAN_F16DATA1(canx) REG32((canx) + 0x2C4U) /*!< CAN filter 16 data 1 register */
|
#define CAN_F16DATA1(canx) REG32((canx) + 0x000002C4U) /*!< CAN filter 16 data 1 register */
|
||||||
#define CAN_F17DATA1(canx) REG32((canx) + 0x24CU) /*!< CAN filter 17 data 1 register */
|
#define CAN_F17DATA1(canx) REG32((canx) + 0x0000024CU) /*!< CAN filter 17 data 1 register */
|
||||||
#define CAN_F18DATA1(canx) REG32((canx) + 0x2D4U) /*!< CAN filter 18 data 1 register */
|
#define CAN_F18DATA1(canx) REG32((canx) + 0x000002D4U) /*!< CAN filter 18 data 1 register */
|
||||||
#define CAN_F19DATA1(canx) REG32((canx) + 0x2DCU) /*!< CAN filter 19 data 1 register */
|
#define CAN_F19DATA1(canx) REG32((canx) + 0x000002DCU) /*!< CAN filter 19 data 1 register */
|
||||||
#define CAN_F20DATA1(canx) REG32((canx) + 0x2E4U) /*!< CAN filter 20 data 1 register */
|
#define CAN_F20DATA1(canx) REG32((canx) + 0x000002E4U) /*!< CAN filter 20 data 1 register */
|
||||||
#define CAN_F21DATA1(canx) REG32((canx) + 0x2ECU) /*!< CAN filter 21 data 1 register */
|
#define CAN_F21DATA1(canx) REG32((canx) + 0x000002ECU) /*!< CAN filter 21 data 1 register */
|
||||||
#define CAN_F22DATA1(canx) REG32((canx) + 0x2F4U) /*!< CAN filter 22 data 1 register */
|
#define CAN_F22DATA1(canx) REG32((canx) + 0x000002F4U) /*!< CAN filter 22 data 1 register */
|
||||||
#define CAN_F23DATA1(canx) REG32((canx) + 0x2FCU) /*!< CAN filter 23 data 1 register */
|
#define CAN_F23DATA1(canx) REG32((canx) + 0x000002FCU) /*!< CAN filter 23 data 1 register */
|
||||||
#define CAN_F24DATA1(canx) REG32((canx) + 0x304U) /*!< CAN filter 24 data 1 register */
|
#define CAN_F24DATA1(canx) REG32((canx) + 0x00000304U) /*!< CAN filter 24 data 1 register */
|
||||||
#define CAN_F25DATA1(canx) REG32((canx) + 0x30CU) /*!< CAN filter 25 data 1 register */
|
#define CAN_F25DATA1(canx) REG32((canx) + 0x0000030CU) /*!< CAN filter 25 data 1 register */
|
||||||
#define CAN_F26DATA1(canx) REG32((canx) + 0x314U) /*!< CAN filter 26 data 1 register */
|
#define CAN_F26DATA1(canx) REG32((canx) + 0x00000314U) /*!< CAN filter 26 data 1 register */
|
||||||
#define CAN_F27DATA1(canx) REG32((canx) + 0x31CU) /*!< CAN filter 27 data 1 register */
|
#define CAN_F27DATA1(canx) REG32((canx) + 0x0000031CU) /*!< CAN filter 27 data 1 register */
|
||||||
|
|
||||||
/* CAN transmit mailbox bank */
|
/* CAN transmit mailbox bank */
|
||||||
#define CAN_TMI(canx, bank) REG32((canx) + 0x180U + ((bank) * 0x10U)) /*!< CAN transmit mailbox identifier register */
|
#define CAN_TMI(canx, bank) REG32((canx) + 0x180U + ((bank) * 0x10U)) /*!< CAN transmit mailbox identifier register */
|
||||||
|
|
@ -145,7 +147,7 @@ OF SUCH DAMAGE.
|
||||||
#define CAN_FDATA0(canx, bank) REG32((canx) + 0x240U + ((bank) * 0x8U) + 0x0U) /*!< CAN filter data 0 register */
|
#define CAN_FDATA0(canx, bank) REG32((canx) + 0x240U + ((bank) * 0x8U) + 0x0U) /*!< CAN filter data 0 register */
|
||||||
#define CAN_FDATA1(canx, bank) REG32((canx) + 0x240U + ((bank) * 0x8U) + 0x4U) /*!< CAN filter data 1 register */
|
#define CAN_FDATA1(canx, bank) REG32((canx) + 0x240U + ((bank) * 0x8U) + 0x4U) /*!< CAN filter data 1 register */
|
||||||
|
|
||||||
/* CAN receive fifo mailbox bank */
|
/* CAN receive FIFO mailbox bank */
|
||||||
#define CAN_RFIFOMI(canx, bank) REG32((canx) + 0x1B0U + ((bank) * 0x10U)) /*!< CAN receive FIFO mailbox identifier register */
|
#define CAN_RFIFOMI(canx, bank) REG32((canx) + 0x1B0U + ((bank) * 0x10U)) /*!< CAN receive FIFO mailbox identifier register */
|
||||||
#define CAN_RFIFOMP(canx, bank) REG32((canx) + 0x1B4U + ((bank) * 0x10U)) /*!< CAN receive FIFO mailbox property register */
|
#define CAN_RFIFOMP(canx, bank) REG32((canx) + 0x1B4U + ((bank) * 0x10U)) /*!< CAN receive FIFO mailbox property register */
|
||||||
#define CAN_RFIFOMDATA0(canx, bank) REG32((canx) + 0x1B8U + ((bank) * 0x10U)) /*!< CAN receive FIFO mailbox data0 register */
|
#define CAN_RFIFOMDATA0(canx, bank) REG32((canx) + 0x1B8U + ((bank) * 0x10U)) /*!< CAN receive FIFO mailbox data0 register */
|
||||||
|
|
@ -309,7 +311,7 @@ OF SUCH DAMAGE.
|
||||||
/* CAN_FxDATAy */
|
/* CAN_FxDATAy */
|
||||||
#define CAN_FDATA_FD(regval) BIT(regval) /*!< filter data */
|
#define CAN_FDATA_FD(regval) BIT(regval) /*!< filter data */
|
||||||
|
|
||||||
/* consts definitions */
|
/* constants definitions */
|
||||||
/* define the CAN bit position and its register index offset */
|
/* define the CAN bit position and its register index offset */
|
||||||
#define CAN_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))
|
#define CAN_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))
|
||||||
#define CAN_REG_VAL(canx, offset) (REG32((canx) + ((uint32_t)(offset) >> 6)))
|
#define CAN_REG_VAL(canx, offset) (REG32((canx) + ((uint32_t)(offset) >> 6)))
|
||||||
|
|
@ -328,8 +330,7 @@ OF SUCH DAMAGE.
|
||||||
#define ERR_REG_OFFSET ((uint8_t)0x18U) /*!< ERR register offset */
|
#define ERR_REG_OFFSET ((uint8_t)0x18U) /*!< ERR register offset */
|
||||||
|
|
||||||
/* CAN flags */
|
/* CAN flags */
|
||||||
typedef enum
|
typedef enum {
|
||||||
{
|
|
||||||
/* flags in STAT register */
|
/* flags in STAT register */
|
||||||
CAN_FLAG_RXL = CAN_REGIDX_BIT(STAT_REG_OFFSET, 11U), /*!< RX level */
|
CAN_FLAG_RXL = CAN_REGIDX_BIT(STAT_REG_OFFSET, 11U), /*!< RX level */
|
||||||
CAN_FLAG_LASTRX = CAN_REGIDX_BIT(STAT_REG_OFFSET, 10U), /*!< last sample value of RX pin */
|
CAN_FLAG_LASTRX = CAN_REGIDX_BIT(STAT_REG_OFFSET, 10U), /*!< last sample value of RX pin */
|
||||||
|
|
@ -341,9 +342,9 @@ typedef enum
|
||||||
CAN_FLAG_SLPWS = CAN_REGIDX_BIT(STAT_REG_OFFSET, 1U), /*!< sleep working state */
|
CAN_FLAG_SLPWS = CAN_REGIDX_BIT(STAT_REG_OFFSET, 1U), /*!< sleep working state */
|
||||||
CAN_FLAG_IWS = CAN_REGIDX_BIT(STAT_REG_OFFSET, 0U), /*!< initial working state */
|
CAN_FLAG_IWS = CAN_REGIDX_BIT(STAT_REG_OFFSET, 0U), /*!< initial working state */
|
||||||
/* flags in TSTAT register */
|
/* flags in TSTAT register */
|
||||||
CAN_FLAG_TMLS2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 31U), /*!< transmit mailbox 2 last sending in Tx FIFO */
|
CAN_FLAG_TMLS2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 31U), /*!< transmit mailbox 2 last sending in TX FIFO */
|
||||||
CAN_FLAG_TMLS1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 30U), /*!< transmit mailbox 1 last sending in Tx FIFO */
|
CAN_FLAG_TMLS1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 30U), /*!< transmit mailbox 1 last sending in TX FIFO */
|
||||||
CAN_FLAG_TMLS0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 29U), /*!< transmit mailbox 0 last sending in Tx FIFO */
|
CAN_FLAG_TMLS0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 29U), /*!< transmit mailbox 0 last sending in TX FIFO */
|
||||||
CAN_FLAG_TME2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 28U), /*!< transmit mailbox 2 empty */
|
CAN_FLAG_TME2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 28U), /*!< transmit mailbox 2 empty */
|
||||||
CAN_FLAG_TME1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 27U), /*!< transmit mailbox 1 empty */
|
CAN_FLAG_TME1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 27U), /*!< transmit mailbox 1 empty */
|
||||||
CAN_FLAG_TME0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 26U), /*!< transmit mailbox 0 empty */
|
CAN_FLAG_TME0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 26U), /*!< transmit mailbox 0 empty */
|
||||||
|
|
@ -372,8 +373,7 @@ typedef enum
|
||||||
} can_flag_enum;
|
} can_flag_enum;
|
||||||
|
|
||||||
/* CAN interrupt flags */
|
/* CAN interrupt flags */
|
||||||
typedef enum
|
typedef enum {
|
||||||
{
|
|
||||||
/* interrupt flags in STAT register */
|
/* interrupt flags in STAT register */
|
||||||
CAN_INT_FLAG_SLPIF = CAN_REGIDX_BITS(STAT_REG_OFFSET, 4U, 17U), /*!< status change interrupt flag of sleep working mode entering */
|
CAN_INT_FLAG_SLPIF = CAN_REGIDX_BITS(STAT_REG_OFFSET, 4U, 17U), /*!< status change interrupt flag of sleep working mode entering */
|
||||||
CAN_INT_FLAG_WUIF = CAN_REGIDX_BITS(STAT_REG_OFFSET, 3U, 16), /*!< status change interrupt flag of wakeup from sleep working mode */
|
CAN_INT_FLAG_WUIF = CAN_REGIDX_BITS(STAT_REG_OFFSET, 3U, 16), /*!< status change interrupt flag of wakeup from sleep working mode */
|
||||||
|
|
@ -389,7 +389,7 @@ typedef enum
|
||||||
/* interrupt flags in RFIFO0 register */
|
/* interrupt flags in RFIFO0 register */
|
||||||
CAN_INT_FLAG_RFO1 = CAN_REGIDX_BITS(RFIFO1_REG_OFFSET, 4U, 6U), /*!< receive FIFO1 overfull interrupt flag */
|
CAN_INT_FLAG_RFO1 = CAN_REGIDX_BITS(RFIFO1_REG_OFFSET, 4U, 6U), /*!< receive FIFO1 overfull interrupt flag */
|
||||||
CAN_INT_FLAG_RFF1 = CAN_REGIDX_BITS(RFIFO1_REG_OFFSET, 3U, 5U), /*!< receive FIFO1 full interrupt flag */
|
CAN_INT_FLAG_RFF1 = CAN_REGIDX_BITS(RFIFO1_REG_OFFSET, 3U, 5U), /*!< receive FIFO1 full interrupt flag */
|
||||||
CAN_INT_FLAG_RFL1 = CAN_REGIDX_BITS(RFIFO1_REG_OFFSET, 2U, 4U), /*!< receive FIFO0 not empty interrupt flag */
|
CAN_INT_FLAG_RFL1 = CAN_REGIDX_BITS(RFIFO1_REG_OFFSET, 2U, 4U), /*!< receive FIFO1 not empty interrupt flag */
|
||||||
/* interrupt flags in ERR register */
|
/* interrupt flags in ERR register */
|
||||||
CAN_INT_FLAG_ERRN = CAN_REGIDX_BITS(ERR_REG_OFFSET, 3U, 11U), /*!< error number interrupt flag */
|
CAN_INT_FLAG_ERRN = CAN_REGIDX_BITS(ERR_REG_OFFSET, 3U, 11U), /*!< error number interrupt flag */
|
||||||
CAN_INT_FLAG_BOERR = CAN_REGIDX_BITS(ERR_REG_OFFSET, 2U, 10U), /*!< bus-off error interrupt flag */
|
CAN_INT_FLAG_BOERR = CAN_REGIDX_BITS(ERR_REG_OFFSET, 2U, 10U), /*!< bus-off error interrupt flag */
|
||||||
|
|
@ -397,9 +397,8 @@ typedef enum
|
||||||
CAN_INT_FLAG_WERR = CAN_REGIDX_BITS(ERR_REG_OFFSET, 0U, 8U), /*!< warning error interrupt flag */
|
CAN_INT_FLAG_WERR = CAN_REGIDX_BITS(ERR_REG_OFFSET, 0U, 8U), /*!< warning error interrupt flag */
|
||||||
} can_interrupt_flag_enum;
|
} can_interrupt_flag_enum;
|
||||||
|
|
||||||
/* CAN initiliaze parameters struct */
|
/* CAN initiliaze parameters structure */
|
||||||
typedef struct
|
typedef struct {
|
||||||
{
|
|
||||||
uint8_t working_mode; /*!< CAN working mode */
|
uint8_t working_mode; /*!< CAN working mode */
|
||||||
uint8_t resync_jump_width; /*!< CAN resynchronization jump width */
|
uint8_t resync_jump_width; /*!< CAN resynchronization jump width */
|
||||||
uint8_t time_segment_1; /*!< time segment 1 */
|
uint8_t time_segment_1; /*!< time segment 1 */
|
||||||
|
|
@ -407,15 +406,14 @@ typedef struct
|
||||||
ControlStatus time_triggered; /*!< time triggered communication mode */
|
ControlStatus time_triggered; /*!< time triggered communication mode */
|
||||||
ControlStatus auto_bus_off_recovery; /*!< automatic bus-off recovery */
|
ControlStatus auto_bus_off_recovery; /*!< automatic bus-off recovery */
|
||||||
ControlStatus auto_wake_up; /*!< automatic wake-up mode */
|
ControlStatus auto_wake_up; /*!< automatic wake-up mode */
|
||||||
ControlStatus no_auto_retrans; /*!< automatic retransmission mode disable */
|
ControlStatus auto_retrans; /*!< automatic retransmission mode */
|
||||||
ControlStatus rec_fifo_overwrite; /*!< receive FIFO overwrite mode */
|
ControlStatus rec_fifo_overwrite; /*!< receive FIFO overwrite mode */
|
||||||
ControlStatus trans_fifo_order; /*!< transmit FIFO order */
|
ControlStatus trans_fifo_order; /*!< transmit FIFO order */
|
||||||
uint16_t prescaler; /*!< baudrate prescaler */
|
uint16_t prescaler; /*!< baudrate prescaler */
|
||||||
} can_parameter_struct;
|
} can_parameter_struct;
|
||||||
|
|
||||||
/* CAN transmit message struct */
|
/* CAN transmit message structure */
|
||||||
typedef struct
|
typedef struct {
|
||||||
{
|
|
||||||
uint32_t tx_sfid; /*!< standard format frame identifier */
|
uint32_t tx_sfid; /*!< standard format frame identifier */
|
||||||
uint32_t tx_efid; /*!< extended format frame identifier */
|
uint32_t tx_efid; /*!< extended format frame identifier */
|
||||||
uint8_t tx_ff; /*!< format of frame, standard or extended format */
|
uint8_t tx_ff; /*!< format of frame, standard or extended format */
|
||||||
|
|
@ -424,9 +422,8 @@ typedef struct
|
||||||
uint8_t tx_data[8]; /*!< transmit data */
|
uint8_t tx_data[8]; /*!< transmit data */
|
||||||
} can_trasnmit_message_struct;
|
} can_trasnmit_message_struct;
|
||||||
|
|
||||||
/* CAN receive message struct */
|
/* CAN receive message structure */
|
||||||
typedef struct
|
typedef struct {
|
||||||
{
|
|
||||||
uint32_t rx_sfid; /*!< standard format frame identifier */
|
uint32_t rx_sfid; /*!< standard format frame identifier */
|
||||||
uint32_t rx_efid; /*!< extended format frame identifier */
|
uint32_t rx_efid; /*!< extended format frame identifier */
|
||||||
uint8_t rx_ff; /*!< format of frame, standard or extended format */
|
uint8_t rx_ff; /*!< format of frame, standard or extended format */
|
||||||
|
|
@ -436,9 +433,8 @@ typedef struct
|
||||||
uint8_t rx_fi; /*!< filtering index */
|
uint8_t rx_fi; /*!< filtering index */
|
||||||
} can_receive_message_struct;
|
} can_receive_message_struct;
|
||||||
|
|
||||||
/* CAN filter parameters struct */
|
/* CAN filter parameters structure */
|
||||||
typedef struct
|
typedef struct {
|
||||||
{
|
|
||||||
uint16_t filter_list_high; /*!< filter list number high bits */
|
uint16_t filter_list_high; /*!< filter list number high bits */
|
||||||
uint16_t filter_list_low; /*!< filter list number low bits */
|
uint16_t filter_list_low; /*!< filter list number low bits */
|
||||||
uint16_t filter_mask_high; /*!< filter mask number high bits */
|
uint16_t filter_mask_high; /*!< filter mask number high bits */
|
||||||
|
|
@ -451,8 +447,7 @@ typedef struct
|
||||||
} can_filter_parameter_struct;
|
} can_filter_parameter_struct;
|
||||||
|
|
||||||
/* CAN errors */
|
/* CAN errors */
|
||||||
typedef enum
|
typedef enum {
|
||||||
{
|
|
||||||
CAN_ERROR_NONE = 0, /*!< no error */
|
CAN_ERROR_NONE = 0, /*!< no error */
|
||||||
CAN_ERROR_FILL, /*!< fill error */
|
CAN_ERROR_FILL, /*!< fill error */
|
||||||
CAN_ERROR_FORMATE, /*!< format error */
|
CAN_ERROR_FORMATE, /*!< format error */
|
||||||
|
|
@ -464,16 +459,14 @@ typedef enum
|
||||||
} can_error_enum;
|
} can_error_enum;
|
||||||
|
|
||||||
/* transmit states */
|
/* transmit states */
|
||||||
typedef enum
|
typedef enum {
|
||||||
{
|
|
||||||
CAN_TRANSMIT_FAILED = 0U, /*!< CAN transmitted failure */
|
CAN_TRANSMIT_FAILED = 0U, /*!< CAN transmitted failure */
|
||||||
CAN_TRANSMIT_OK = 1U, /*!< CAN transmitted success */
|
CAN_TRANSMIT_OK = 1U, /*!< CAN transmitted success */
|
||||||
CAN_TRANSMIT_PENDING = 2U, /*!< CAN transmitted pending */
|
CAN_TRANSMIT_PENDING = 2U, /*!< CAN transmitted pending */
|
||||||
CAN_TRANSMIT_NOMAILBOX = 4U, /*!< no empty mailbox to be used for CAN */
|
CAN_TRANSMIT_NOMAILBOX = 4U, /*!< no empty mailbox to be used for CAN */
|
||||||
} can_transmit_state_enum;
|
} can_transmit_state_enum;
|
||||||
|
|
||||||
typedef enum
|
typedef enum {
|
||||||
{
|
|
||||||
CAN_INIT_STRUCT = 0, /* CAN initiliaze parameters struct */
|
CAN_INIT_STRUCT = 0, /* CAN initiliaze parameters struct */
|
||||||
CAN_FILTER_STRUCT, /* CAN filter parameters struct */
|
CAN_FILTER_STRUCT, /* CAN filter parameters struct */
|
||||||
CAN_TX_MESSAGE_STRUCT, /* CAN transmit message struct */
|
CAN_TX_MESSAGE_STRUCT, /* CAN transmit message struct */
|
||||||
|
|
@ -537,7 +530,7 @@ typedef enum
|
||||||
/* receive mailbox extended identifier */
|
/* receive mailbox extended identifier */
|
||||||
#define GET_RFIFOMI_EFID(regval) GET_BITS((uint32_t)(regval), 3U, 31U)
|
#define GET_RFIFOMI_EFID(regval) GET_BITS((uint32_t)(regval), 3U, 31U)
|
||||||
|
|
||||||
/* receive mailbox standrad identifier*/
|
/* receive mailbox standard identifier */
|
||||||
#define GET_RFIFOMI_SFID(regval) GET_BITS((uint32_t)(regval), 21U, 31U)
|
#define GET_RFIFOMI_SFID(regval) GET_BITS((uint32_t)(regval), 21U, 31U)
|
||||||
|
|
||||||
/* receive data length */
|
/* receive data length */
|
||||||
|
|
@ -581,7 +574,7 @@ typedef enum
|
||||||
|
|
||||||
/* CAN errors */
|
/* CAN errors */
|
||||||
#define ERR_ERRN(regval) (BITS(4,6) & ((uint32_t)(regval) << 4))
|
#define ERR_ERRN(regval) (BITS(4,6) & ((uint32_t)(regval) << 4))
|
||||||
#define CAN_ERRN_0 ERR_ERRN(0U) /* no error */
|
#define CAN_ERRN_0 ERR_ERRN(0U) /*!< no error */
|
||||||
#define CAN_ERRN_1 ERR_ERRN(1U) /*!< fill error */
|
#define CAN_ERRN_1 ERR_ERRN(1U) /*!< fill error */
|
||||||
#define CAN_ERRN_2 ERR_ERRN(2U) /*!< format error */
|
#define CAN_ERRN_2 ERR_ERRN(2U) /*!< format error */
|
||||||
#define CAN_ERRN_3 ERR_ERRN(3U) /*!< ACK error */
|
#define CAN_ERRN_3 ERR_ERRN(3U) /*!< ACK error */
|
||||||
|
|
@ -642,11 +635,11 @@ typedef enum
|
||||||
#define CAN_FF_STANDARD ((uint32_t)0x00000000U) /*!< standard frame */
|
#define CAN_FF_STANDARD ((uint32_t)0x00000000U) /*!< standard frame */
|
||||||
#define CAN_FF_EXTENDED ((uint32_t)0x00000004U) /*!< extended frame */
|
#define CAN_FF_EXTENDED ((uint32_t)0x00000004U) /*!< extended frame */
|
||||||
|
|
||||||
/* CAN receive fifo */
|
/* CAN receive FIFO */
|
||||||
#define CAN_FIFO0 ((uint8_t)0x00U) /*!< receive FIFO0 */
|
#define CAN_FIFO0 ((uint8_t)0x00U) /*!< receive FIFO0 */
|
||||||
#define CAN_FIFO1 ((uint8_t)0x01U) /*!< receive FIFO1 */
|
#define CAN_FIFO1 ((uint8_t)0x01U) /*!< receive FIFO1 */
|
||||||
|
|
||||||
/* frame number of receive fifo */
|
/* frame number of receive FIFO */
|
||||||
#define CAN_RFIF_RFL_MASK ((uint32_t)0x00000003U) /*!< mask for frame number in receive FIFOx */
|
#define CAN_RFIF_RFL_MASK ((uint32_t)0x00000003U) /*!< mask for frame number in receive FIFOx */
|
||||||
|
|
||||||
#define CAN_SFID_MASK ((uint32_t)0x000007FFU) /*!< mask of standard identifier */
|
#define CAN_SFID_MASK ((uint32_t)0x000007FFU) /*!< mask of standard identifier */
|
||||||
|
|
@ -692,15 +685,18 @@ typedef enum
|
||||||
#define CAN_INT_SLPW CAN_INTEN_SLPWIE /*!< sleep working interrupt enable */
|
#define CAN_INT_SLPW CAN_INTEN_SLPWIE /*!< sleep working interrupt enable */
|
||||||
|
|
||||||
/* function declarations */
|
/* function declarations */
|
||||||
|
/* initialization functions */
|
||||||
/* deinitialize CAN */
|
/* deinitialize CAN */
|
||||||
void can_deinit(uint32_t can_periph);
|
void can_deinit(uint32_t can_periph);
|
||||||
/* initialize CAN struct */
|
/* initialize CAN structure */
|
||||||
void can_struct_para_init(can_struct_type_enum type, void *p_struct);
|
void can_struct_para_init(can_struct_type_enum type, void *p_struct);
|
||||||
/* initialize CAN */
|
/* initialize CAN */
|
||||||
ErrStatus can_init(uint32_t can_periph, can_parameter_struct *can_parameter_init);
|
ErrStatus can_init(uint32_t can_periph, can_parameter_struct *can_parameter_init);
|
||||||
/* CAN filter init */
|
/* CAN filter initialization */
|
||||||
void can_filter_init(can_filter_parameter_struct *can_filter_parameter_init);
|
void can_filter_init(can_filter_parameter_struct *can_filter_parameter_init);
|
||||||
/* set can1 fliter start bank number */
|
|
||||||
|
/* function configuration */
|
||||||
|
/* set can1 filter start bank number */
|
||||||
void can1_filter_start_bank(uint8_t start_bank);
|
void can1_filter_start_bank(uint8_t start_bank);
|
||||||
/* enable functions */
|
/* enable functions */
|
||||||
/* CAN debug freeze enable */
|
/* CAN debug freeze enable */
|
||||||
|
|
@ -721,7 +717,7 @@ can_transmit_state_enum can_transmit_states(uint32_t can_periph, uint8_t mailbox
|
||||||
void can_transmission_stop(uint32_t can_periph, uint8_t mailbox_number);
|
void can_transmission_stop(uint32_t can_periph, uint8_t mailbox_number);
|
||||||
/* CAN receive message */
|
/* CAN receive message */
|
||||||
void can_message_receive(uint32_t can_periph, uint8_t fifo_number, can_receive_message_struct *receive_message);
|
void can_message_receive(uint32_t can_periph, uint8_t fifo_number, can_receive_message_struct *receive_message);
|
||||||
/* CAN release fifo */
|
/* CAN release FIFO */
|
||||||
void can_fifo_release(uint32_t can_periph, uint8_t fifo_number);
|
void can_fifo_release(uint32_t can_periph, uint8_t fifo_number);
|
||||||
/* CAN receive message length */
|
/* CAN receive message length */
|
||||||
uint8_t can_receive_message_length_get(uint32_t can_periph, uint8_t fifo_number);
|
uint8_t can_receive_message_length_get(uint32_t can_periph, uint8_t fifo_number);
|
||||||
|
|
@ -730,21 +726,22 @@ ErrStatus can_working_mode_set(uint32_t can_periph, uint8_t working_mode);
|
||||||
/* CAN wakeup from sleep mode */
|
/* CAN wakeup from sleep mode */
|
||||||
ErrStatus can_wakeup(uint32_t can_periph);
|
ErrStatus can_wakeup(uint32_t can_periph);
|
||||||
|
|
||||||
/* CAN get error */
|
/* CAN get error type */
|
||||||
can_error_enum can_error_get(uint32_t can_periph);
|
can_error_enum can_error_get(uint32_t can_periph);
|
||||||
/* get CAN receive error number */
|
/* get CAN receive error number */
|
||||||
uint8_t can_receive_error_number_get(uint32_t can_periph);
|
uint8_t can_receive_error_number_get(uint32_t can_periph);
|
||||||
/* get CAN transmit error number */
|
/* get CAN transmit error number */
|
||||||
uint8_t can_transmit_error_number_get(uint32_t can_periph);
|
uint8_t can_transmit_error_number_get(uint32_t can_periph);
|
||||||
|
|
||||||
/* CAN interrupt enable */
|
/* interrupt & flag functions */
|
||||||
void can_interrupt_enable(uint32_t can_periph, uint32_t interrupt);
|
|
||||||
/* CAN interrupt disable */
|
|
||||||
void can_interrupt_disable(uint32_t can_periph, uint32_t interrupt);
|
|
||||||
/* CAN get flag state */
|
/* CAN get flag state */
|
||||||
FlagStatus can_flag_get(uint32_t can_periph, can_flag_enum flag);
|
FlagStatus can_flag_get(uint32_t can_periph, can_flag_enum flag);
|
||||||
/* CAN clear flag state */
|
/* CAN clear flag state */
|
||||||
void can_flag_clear(uint32_t can_periph, can_flag_enum flag);
|
void can_flag_clear(uint32_t can_periph, can_flag_enum flag);
|
||||||
|
/* CAN interrupt enable */
|
||||||
|
void can_interrupt_enable(uint32_t can_periph, uint32_t interrupt);
|
||||||
|
/* CAN interrupt disable */
|
||||||
|
void can_interrupt_disable(uint32_t can_periph, uint32_t interrupt);
|
||||||
/* CAN get interrupt flag state */
|
/* CAN get interrupt flag state */
|
||||||
FlagStatus can_interrupt_flag_get(uint32_t can_periph, can_interrupt_flag_enum flag);
|
FlagStatus can_interrupt_flag_get(uint32_t can_periph, can_interrupt_flag_enum flag);
|
||||||
/* CAN clear interrupt flag state */
|
/* CAN clear interrupt flag state */
|
||||||
|
|
|
||||||
|
|
@ -5,10 +5,11 @@
|
||||||
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
||||||
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
||||||
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
||||||
|
\version 2022-03-09, V3.0.0, firmware for GD32F4xx
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/*
|
/*
|
||||||
Copyright (c) 2020, GigaDevice Semiconductor Inc.
|
Copyright (c) 2022, GigaDevice Semiconductor Inc.
|
||||||
|
|
||||||
Redistribution and use in source and binary forms, with or without modification,
|
Redistribution and use in source and binary forms, with or without modification,
|
||||||
are permitted provided that the following conditions are met:
|
are permitted provided that the following conditions are met:
|
||||||
|
|
@ -40,12 +41,12 @@ OF SUCH DAMAGE.
|
||||||
#include "gd32f4xx.h"
|
#include "gd32f4xx.h"
|
||||||
|
|
||||||
/* CRC definitions */
|
/* CRC definitions */
|
||||||
#define CRC CRC_BASE
|
#define CRC CRC_BASE /*!< CRC base address */
|
||||||
|
|
||||||
/* registers definitions */
|
/* registers definitions */
|
||||||
#define CRC_DATA REG32(CRC + 0x00U) /*!< CRC data register */
|
#define CRC_DATA REG32(CRC + 0x00000000U) /*!< CRC data register */
|
||||||
#define CRC_FDATA REG32(CRC + 0x04U) /*!< CRC free data register */
|
#define CRC_FDATA REG32(CRC + 0x00000004U) /*!< CRC free data register */
|
||||||
#define CRC_CTL REG32(CRC + 0x08U) /*!< CRC control register */
|
#define CRC_CTL REG32(CRC + 0x00000008U) /*!< CRC control register */
|
||||||
|
|
||||||
/* bits definitions */
|
/* bits definitions */
|
||||||
/* CRC_DATA */
|
/* CRC_DATA */
|
||||||
|
|
|
||||||
|
|
@ -5,10 +5,11 @@
|
||||||
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
||||||
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
||||||
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
||||||
|
\version 2022-03-09, V3.0.0, firmware for GD32F4xx
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/*
|
/*
|
||||||
Copyright (c) 2020, GigaDevice Semiconductor Inc.
|
Copyright (c) 2022, GigaDevice Semiconductor Inc.
|
||||||
|
|
||||||
Redistribution and use in source and binary forms, with or without modification,
|
Redistribution and use in source and binary forms, with or without modification,
|
||||||
are permitted provided that the following conditions are met:
|
are permitted provided that the following conditions are met:
|
||||||
|
|
@ -64,7 +65,6 @@ OF SUCH DAMAGE.
|
||||||
#define CTC_CTL1_CKLIM BITS(16,23) /*!< clock trim base limit value */
|
#define CTC_CTL1_CKLIM BITS(16,23) /*!< clock trim base limit value */
|
||||||
#define CTC_CTL1_REFPSC BITS(24,26) /*!< reference signal source prescaler */
|
#define CTC_CTL1_REFPSC BITS(24,26) /*!< reference signal source prescaler */
|
||||||
#define CTC_CTL1_REFSEL BITS(28,29) /*!< reference signal source selection */
|
#define CTC_CTL1_REFSEL BITS(28,29) /*!< reference signal source selection */
|
||||||
#define CTC_CTL1_USBSOFSEL BIT(30) /*!< USBFS or USBHS SOF signal selection */
|
|
||||||
#define CTC_CTL1_REFPOL BIT(31) /*!< reference signal source polarity */
|
#define CTC_CTL1_REFPOL BIT(31) /*!< reference signal source polarity */
|
||||||
|
|
||||||
/* CTC_STAT */
|
/* CTC_STAT */
|
||||||
|
|
@ -93,15 +93,10 @@ OF SUCH DAMAGE.
|
||||||
#define CTC_REFSOURCE_POLARITY_FALLING CTC_CTL1_REFPOL /*!< reference signal source polarity is falling edge*/
|
#define CTC_REFSOURCE_POLARITY_FALLING CTC_CTL1_REFPOL /*!< reference signal source polarity is falling edge*/
|
||||||
#define CTC_REFSOURCE_POLARITY_RISING ((uint32_t)0x00000000U) /*!< reference signal source polarity is rising edge*/
|
#define CTC_REFSOURCE_POLARITY_RISING ((uint32_t)0x00000000U) /*!< reference signal source polarity is rising edge*/
|
||||||
|
|
||||||
/* USBFS or USBHS SOF signal selection definitions */
|
|
||||||
#define CTC_USBSOFSEL_USBHS CTC_CTL1_USBSOFSEL /*!< USBHS SOF signal is selected*/
|
|
||||||
#define CTC_USBSOFSEL_USBFS ((uint32_t)0x00000000U) /*!< USBFS SOF signal is selected*/
|
|
||||||
|
|
||||||
/* reference signal source selection definitions */
|
/* reference signal source selection definitions */
|
||||||
#define CTL1_REFSEL(regval) (BITS(28,29) & ((uint32_t)(regval) << 28))
|
#define CTL1_REFSEL(regval) (BITS(28,29) & ((uint32_t)(regval) << 28))
|
||||||
#define CTC_REFSOURCE_GPIO CTL1_REFSEL(0) /*!< GPIO is selected */
|
#define CTC_REFSOURCE_GPIO CTL1_REFSEL(0) /*!< GPIO is selected */
|
||||||
#define CTC_REFSOURCE_LXTAL CTL1_REFSEL(1) /*!< LXTAL is clock selected */
|
#define CTC_REFSOURCE_LXTAL CTL1_REFSEL(1) /*!< LXTAL is clock selected */
|
||||||
#define CTC_REFSOURCE_USBSOF CTL1_REFSEL(2) /*!< USBSOF is selected */
|
|
||||||
|
|
||||||
/* reference signal source prescaler definitions */
|
/* reference signal source prescaler definitions */
|
||||||
#define CTL1_REFPSC(regval) (BITS(24,26) & ((uint32_t)(regval) << 24))
|
#define CTL1_REFPSC(regval) (BITS(24,26) & ((uint32_t)(regval) << 24))
|
||||||
|
|
@ -155,8 +150,6 @@ void ctc_hardware_trim_mode_config(uint32_t hardmode);
|
||||||
|
|
||||||
/* configure reference signal source polarity */
|
/* configure reference signal source polarity */
|
||||||
void ctc_refsource_polarity_config(uint32_t polarity);
|
void ctc_refsource_polarity_config(uint32_t polarity);
|
||||||
/* select USBFS or USBHS SOF signal */
|
|
||||||
void ctc_usbsof_signal_select(uint32_t usbsof);
|
|
||||||
/* select reference signal source */
|
/* select reference signal source */
|
||||||
void ctc_refsource_signal_select(uint32_t refs);
|
void ctc_refsource_signal_select(uint32_t refs);
|
||||||
/* configure reference signal source prescaler */
|
/* configure reference signal source prescaler */
|
||||||
|
|
|
||||||
|
|
@ -5,10 +5,11 @@
|
||||||
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
||||||
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
||||||
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
||||||
|
\version 2022-03-09, V3.0.0, firmware for GD32F4xx
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/*
|
/*
|
||||||
Copyright (c) 2020, GigaDevice Semiconductor Inc.
|
Copyright (c) 2022, GigaDevice Semiconductor Inc.
|
||||||
|
|
||||||
Redistribution and use in source and binary forms, with or without modification,
|
Redistribution and use in source and binary forms, with or without modification,
|
||||||
are permitted provided that the following conditions are met:
|
are permitted provided that the following conditions are met:
|
||||||
|
|
@ -254,14 +255,14 @@ void dac_concurrent_interrupt_enable(void);
|
||||||
void dac_concurrent_interrupt_disable(void);
|
void dac_concurrent_interrupt_disable(void);
|
||||||
|
|
||||||
/* DAC interrupt configuration */
|
/* DAC interrupt configuration */
|
||||||
/* enable DAC interrupt(DAC DMA underrun interrupt) */
|
|
||||||
void dac_interrupt_enable(uint32_t dac_periph);
|
|
||||||
/* disable DAC interrupt(DAC DMA underrun interrupt) */
|
|
||||||
void dac_interrupt_disable(uint32_t dac_periph);
|
|
||||||
/* get the specified DAC flag(DAC DMA underrun flag) */
|
/* get the specified DAC flag(DAC DMA underrun flag) */
|
||||||
FlagStatus dac_flag_get(uint32_t dac_periph);
|
FlagStatus dac_flag_get(uint32_t dac_periph);
|
||||||
/* clear the specified DAC flag(DAC DMA underrun flag) */
|
/* clear the specified DAC flag(DAC DMA underrun flag) */
|
||||||
void dac_flag_clear(uint32_t dac_periph);
|
void dac_flag_clear(uint32_t dac_periph);
|
||||||
|
/* enable DAC interrupt(DAC DMA underrun interrupt) */
|
||||||
|
void dac_interrupt_enable(uint32_t dac_periph);
|
||||||
|
/* disable DAC interrupt(DAC DMA underrun interrupt) */
|
||||||
|
void dac_interrupt_disable(uint32_t dac_periph);
|
||||||
/* get the specified DAC interrupt flag(DAC DMA underrun interrupt flag) */
|
/* get the specified DAC interrupt flag(DAC DMA underrun interrupt flag) */
|
||||||
FlagStatus dac_interrupt_flag_get(uint32_t dac_periph);
|
FlagStatus dac_interrupt_flag_get(uint32_t dac_periph);
|
||||||
/* clear the specified DAC interrupt flag(DAC DMA underrun interrupt flag) */
|
/* clear the specified DAC interrupt flag(DAC DMA underrun interrupt flag) */
|
||||||
|
|
|
||||||
|
|
@ -5,10 +5,11 @@
|
||||||
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
||||||
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
||||||
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
||||||
|
\version 2022-03-09, V3.0.0, firmware for GD32F4xx
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/*
|
/*
|
||||||
Copyright (c) 2020, GigaDevice Semiconductor Inc.
|
Copyright (c) 2022, GigaDevice Semiconductor Inc.
|
||||||
|
|
||||||
Redistribution and use in source and binary forms, with or without modification,
|
Redistribution and use in source and binary forms, with or without modification,
|
||||||
are permitted provided that the following conditions are met:
|
are permitted provided that the following conditions are met:
|
||||||
|
|
@ -57,7 +58,6 @@ OF SUCH DAMAGE.
|
||||||
#define DBG_CTL0_DSLP_HOLD BIT(1) /*!< keep debugger connection during deepsleep mode */
|
#define DBG_CTL0_DSLP_HOLD BIT(1) /*!< keep debugger connection during deepsleep mode */
|
||||||
#define DBG_CTL0_STB_HOLD BIT(2) /*!< keep debugger connection during standby mode */
|
#define DBG_CTL0_STB_HOLD BIT(2) /*!< keep debugger connection during standby mode */
|
||||||
#define DBG_CTL0_TRACE_IOEN BIT(5) /*!< enable trace pin assignment */
|
#define DBG_CTL0_TRACE_IOEN BIT(5) /*!< enable trace pin assignment */
|
||||||
#define DBG_CTL0_TRACE_MODE BITS(6,7) /*!< trace pin mode selection */
|
|
||||||
|
|
||||||
/* DBG_CTL1 */
|
/* DBG_CTL1 */
|
||||||
#define DBG_CTL1_TIMER1_HOLD BIT(0) /*!< hold TIMER1 counter when core is halted */
|
#define DBG_CTL1_TIMER1_HOLD BIT(0) /*!< hold TIMER1 counter when core is halted */
|
||||||
|
|
@ -129,12 +129,6 @@ typedef enum
|
||||||
DBG_TIMER10_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL2, 18U) /*!< hold TIMER10 counter when core is halted */
|
DBG_TIMER10_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL2, 18U) /*!< hold TIMER10 counter when core is halted */
|
||||||
}dbg_periph_enum;
|
}dbg_periph_enum;
|
||||||
|
|
||||||
#define CTL0_TRACE_MODE(regval) (BITS(6,7)&((uint32_t)(regval)<<6))
|
|
||||||
#define TRACE_MODE_ASYNC CTL0_TRACE_MODE(0) /*!< trace pin used for async mode */
|
|
||||||
#define TRACE_MODE_SYNC_DATASIZE_1 CTL0_TRACE_MODE(1) /*!< trace pin used for sync mode and data size is 1 */
|
|
||||||
#define TRACE_MODE_SYNC_DATASIZE_2 CTL0_TRACE_MODE(2) /*!< trace pin used for sync mode and data size is 2 */
|
|
||||||
#define TRACE_MODE_SYNC_DATASIZE_4 CTL0_TRACE_MODE(3) /*!< trace pin used for sync mode and data size is 4 */
|
|
||||||
|
|
||||||
/* function declarations */
|
/* function declarations */
|
||||||
/* deinitialize the DBG */
|
/* deinitialize the DBG */
|
||||||
void dbg_deinit(void);
|
void dbg_deinit(void);
|
||||||
|
|
@ -155,7 +149,5 @@ void dbg_periph_disable(dbg_periph_enum dbg_periph);
|
||||||
void dbg_trace_pin_enable(void);
|
void dbg_trace_pin_enable(void);
|
||||||
/* disable trace pin assignment */
|
/* disable trace pin assignment */
|
||||||
void dbg_trace_pin_disable(void);
|
void dbg_trace_pin_disable(void);
|
||||||
/* set trace pin mode */
|
|
||||||
void dbg_trace_pin_mode_set(uint32_t trace_mode);
|
|
||||||
|
|
||||||
#endif /* GD32F4XX_DBG_H */
|
#endif /* GD32F4XX_DBG_H */
|
||||||
|
|
|
||||||
|
|
@ -5,10 +5,11 @@
|
||||||
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
||||||
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
||||||
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
||||||
|
\version 2022-03-09, V3.0.0, firmware for GD32F4xx
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/*
|
/*
|
||||||
Copyright (c) 2020, GigaDevice Semiconductor Inc.
|
Copyright (c) 2022, GigaDevice Semiconductor Inc.
|
||||||
|
|
||||||
Redistribution and use in source and binary forms, with or without modification,
|
Redistribution and use in source and binary forms, with or without modification,
|
||||||
are permitted provided that the following conditions are met:
|
are permitted provided that the following conditions are met:
|
||||||
|
|
|
||||||
|
|
@ -1,14 +1,14 @@
|
||||||
/*!
|
/*!
|
||||||
\file gd32f4xx_dma.c
|
\file gd32f4xx_dma.h
|
||||||
\brief definitions for the DMA
|
\brief definitions for the DMA
|
||||||
|
|
||||||
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
||||||
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
||||||
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
||||||
|
\version 2022-03-09, V3.0.0, firmware for GD32F4xx
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/*
|
/*
|
||||||
Copyright (c) 2020, GigaDevice Semiconductor Inc.
|
Copyright (c) 2022, GigaDevice Semiconductor Inc.
|
||||||
|
|
||||||
Redistribution and use in source and binary forms, with or without modification,
|
Redistribution and use in source and binary forms, with or without modification,
|
||||||
are permitted provided that the following conditions are met:
|
are permitted provided that the following conditions are met:
|
||||||
|
|
@ -41,69 +41,69 @@ OF SUCH DAMAGE.
|
||||||
|
|
||||||
/* DMA definitions */
|
/* DMA definitions */
|
||||||
#define DMA0 (DMA_BASE) /*!< DMA0 base address */
|
#define DMA0 (DMA_BASE) /*!< DMA0 base address */
|
||||||
#define DMA1 (DMA_BASE + 0x0400U) /*!< DMA1 base address */
|
#define DMA1 (DMA_BASE + 0x00000400U) /*!< DMA1 base address */
|
||||||
|
|
||||||
/* registers definitions */
|
/* registers definitions */
|
||||||
#define DMA_INTF0(dmax) REG32((dmax) + 0x00U) /*!< DMA interrupt flag register 0 */
|
#define DMA_INTF0(dmax) REG32((dmax) + 0x00000000U) /*!< DMA interrupt flag register 0 */
|
||||||
#define DMA_INTF1(dmax) REG32((dmax) + 0x04U) /*!< DMA interrupt flag register 1 */
|
#define DMA_INTF1(dmax) REG32((dmax) + 0x00000004U) /*!< DMA interrupt flag register 1 */
|
||||||
#define DMA_INTC0(dmax) REG32((dmax) + 0x08U) /*!< DMA interrupt flag clear register 0 */
|
#define DMA_INTC0(dmax) REG32((dmax) + 0x00000008U) /*!< DMA interrupt flag clear register 0 */
|
||||||
#define DMA_INTC1(dmax) REG32((dmax) + 0x0CU) /*!< DMA interrupt flag clear register 1 */
|
#define DMA_INTC1(dmax) REG32((dmax) + 0x0000000CU) /*!< DMA interrupt flag clear register 1 */
|
||||||
|
|
||||||
#define DMA_CH0CTL(dmax) REG32((dmax) + 0x10U) /*!< DMA channel 0 control register */
|
#define DMA_CH0CTL(dmax) REG32((dmax) + 0x00000010U) /*!< DMA channel 0 control register */
|
||||||
#define DMA_CH0CNT(dmax) REG32((dmax) + 0x14U) /*!< DMA channel 0 counter register */
|
#define DMA_CH0CNT(dmax) REG32((dmax) + 0x00000014U) /*!< DMA channel 0 counter register */
|
||||||
#define DMA_CH0PADDR(dmax) REG32((dmax) + 0x18U) /*!< DMA channel 0 peripheral base address register */
|
#define DMA_CH0PADDR(dmax) REG32((dmax) + 0x00000018U) /*!< DMA channel 0 peripheral base address register */
|
||||||
#define DMA_CH0M0ADDR(dmax) REG32((dmax) + 0x1CU) /*!< DMA channel 0 memory 0 base address register */
|
#define DMA_CH0M0ADDR(dmax) REG32((dmax) + 0x0000001CU) /*!< DMA channel 0 memory 0 base address register */
|
||||||
#define DMA_CH0M1ADDR(dmax) REG32((dmax) + 0x20U) /*!< DMA channel 0 memory 1 base address register */
|
#define DMA_CH0M1ADDR(dmax) REG32((dmax) + 0x00000020U) /*!< DMA channel 0 memory 1 base address register */
|
||||||
#define DMA_CH0FCTL(dmax) REG32((dmax) + 0x24U) /*!< DMA channel 0 FIFO control register */
|
#define DMA_CH0FCTL(dmax) REG32((dmax) + 0x00000024U) /*!< DMA channel 0 FIFO control register */
|
||||||
|
|
||||||
#define DMA_CH1CTL(dmax) REG32((dmax) + 0x28U) /*!< DMA channel 1 control register */
|
#define DMA_CH1CTL(dmax) REG32((dmax) + 0x00000028U) /*!< DMA channel 1 control register */
|
||||||
#define DMA_CH1CNT(dmax) REG32((dmax) + 0x2CU) /*!< DMA channel 1 counter register */
|
#define DMA_CH1CNT(dmax) REG32((dmax) + 0x0000002CU) /*!< DMA channel 1 counter register */
|
||||||
#define DMA_CH1PADDR(dmax) REG32((dmax) + 0x30U) /*!< DMA channel 1 peripheral base address register */
|
#define DMA_CH1PADDR(dmax) REG32((dmax) + 0x00000030U) /*!< DMA channel 1 peripheral base address register */
|
||||||
#define DMA_CH1M0ADDR(dmax) REG32((dmax) + 0x34U) /*!< DMA channel 1 memory 0 base address register */
|
#define DMA_CH1M0ADDR(dmax) REG32((dmax) + 0x00000034U) /*!< DMA channel 1 memory 0 base address register */
|
||||||
#define DMA_CH1M1ADDR(dmax) REG32((dmax) + 0x38U) /*!< DMA channel 1 memory 1 base address register */
|
#define DMA_CH1M1ADDR(dmax) REG32((dmax) + 0x00000038U) /*!< DMA channel 1 memory 1 base address register */
|
||||||
#define DMA_CH1FCTL(dmax) REG32((dmax) + 0x3CU) /*!< DMA channel 1 FIFO control register */
|
#define DMA_CH1FCTL(dmax) REG32((dmax) + 0x0000003CU) /*!< DMA channel 1 FIFO control register */
|
||||||
|
|
||||||
#define DMA_CH2CTL(dmax) REG32((dmax) + 0x40U) /*!< DMA channel 2 control register */
|
#define DMA_CH2CTL(dmax) REG32((dmax) + 0x00000040U) /*!< DMA channel 2 control register */
|
||||||
#define DMA_CH2CNT(dmax) REG32((dmax) + 0x44U) /*!< DMA channel 2 counter register */
|
#define DMA_CH2CNT(dmax) REG32((dmax) + 0x00000044U) /*!< DMA channel 2 counter register */
|
||||||
#define DMA_CH2PADDR(dmax) REG32((dmax) + 0x48U) /*!< DMA channel 2 peripheral base address register */
|
#define DMA_CH2PADDR(dmax) REG32((dmax) + 0x00000048U) /*!< DMA channel 2 peripheral base address register */
|
||||||
#define DMA_CH2M0ADDR(dmax) REG32((dmax) + 0x4CU) /*!< DMA channel 2 memory 0 base address register */
|
#define DMA_CH2M0ADDR(dmax) REG32((dmax) + 0x0000004CU) /*!< DMA channel 2 memory 0 base address register */
|
||||||
#define DMA_CH2M1ADDR(dmax) REG32((dmax) + 0x50U) /*!< DMA channel 2 memory 1 base address register */
|
#define DMA_CH2M1ADDR(dmax) REG32((dmax) + 0x00000050U) /*!< DMA channel 2 memory 1 base address register */
|
||||||
#define DMA_CH2FCTL(dmax) REG32((dmax) + 0x54U) /*!< DMA channel 2 FIFO control register */
|
#define DMA_CH2FCTL(dmax) REG32((dmax) + 0x00000054U) /*!< DMA channel 2 FIFO control register */
|
||||||
|
|
||||||
#define DMA_CH3CTL(dmax) REG32((dmax) + 0x58U) /*!< DMA channel 3 control register */
|
#define DMA_CH3CTL(dmax) REG32((dmax) + 0x00000058U) /*!< DMA channel 3 control register */
|
||||||
#define DMA_CH3CNT(dmax) REG32((dmax) + 0x5CU) /*!< DMA channel 3 counter register */
|
#define DMA_CH3CNT(dmax) REG32((dmax) + 0x0000005CU) /*!< DMA channel 3 counter register */
|
||||||
#define DMA_CH3PADDR(dmax) REG32((dmax) + 0x60U) /*!< DMA channel 3 peripheral base address register */
|
#define DMA_CH3PADDR(dmax) REG32((dmax) + 0x00000060U) /*!< DMA channel 3 peripheral base address register */
|
||||||
#define DMA_CH3M0ADDR(dmax) REG32((dmax) + 0x64U) /*!< DMA channel 3 memory 0 base address register */
|
#define DMA_CH3M0ADDR(dmax) REG32((dmax) + 0x00000064U) /*!< DMA channel 3 memory 0 base address register */
|
||||||
#define DMA_CH3M1ADDR(dmax) REG32((dmax) + 0x68U) /*!< DMA channel 3 memory 1 base address register */
|
#define DMA_CH3M1ADDR(dmax) REG32((dmax) + 0x00000068U) /*!< DMA channel 3 memory 1 base address register */
|
||||||
#define DMA_CH3FCTL(dmax) REG32((dmax) + 0x6CU) /*!< DMA channel 3 FIFO control register */
|
#define DMA_CH3FCTL(dmax) REG32((dmax) + 0x0000006CU) /*!< DMA channel 3 FIFO control register */
|
||||||
|
|
||||||
#define DMA_CH4CTL(dmax) REG32((dmax) + 0x70U) /*!< DMA channel 4 control register */
|
#define DMA_CH4CTL(dmax) REG32((dmax) + 0x00000070U) /*!< DMA channel 4 control register */
|
||||||
#define DMA_CH4CNT(dmax) REG32((dmax) + 0x74U) /*!< DMA channel 4 counter register */
|
#define DMA_CH4CNT(dmax) REG32((dmax) + 0x00000074U) /*!< DMA channel 4 counter register */
|
||||||
#define DMA_CH4PADDR(dmax) REG32((dmax) + 0x78U) /*!< DMA channel 4 peripheral base address register */
|
#define DMA_CH4PADDR(dmax) REG32((dmax) + 0x00000078U) /*!< DMA channel 4 peripheral base address register */
|
||||||
#define DMA_CH4M0ADDR(dmax) REG32((dmax) + 0x7CU) /*!< DMA channel 4 memory 0 base address register */
|
#define DMA_CH4M0ADDR(dmax) REG32((dmax) + 0x0000007CU) /*!< DMA channel 4 memory 0 base address register */
|
||||||
#define DMA_CH4M1ADDR(dmax) REG32((dmax) + 0x80U) /*!< DMA channel 4 memory 1 base address register */
|
#define DMA_CH4M1ADDR(dmax) REG32((dmax) + 0x00000080U) /*!< DMA channel 4 memory 1 base address register */
|
||||||
#define DMA_CH4FCTL(dmax) REG32((dmax) + 0x84U) /*!< DMA channel 4 FIFO control register */
|
#define DMA_CH4FCTL(dmax) REG32((dmax) + 0x00000084U) /*!< DMA channel 4 FIFO control register */
|
||||||
|
|
||||||
#define DMA_CH5CTL(dmax) REG32((dmax) + 0x88U) /*!< DMA channel 5 control register */
|
#define DMA_CH5CTL(dmax) REG32((dmax) + 0x00000088U) /*!< DMA channel 5 control register */
|
||||||
#define DMA_CH5CNT(dmax) REG32((dmax) + 0x8CU) /*!< DMA channel 5 counter register */
|
#define DMA_CH5CNT(dmax) REG32((dmax) + 0x0000008CU) /*!< DMA channel 5 counter register */
|
||||||
#define DMA_CH5PADDR(dmax) REG32((dmax) + 0x90U) /*!< DMA channel 5 peripheral base address register */
|
#define DMA_CH5PADDR(dmax) REG32((dmax) + 0x00000090U) /*!< DMA channel 5 peripheral base address register */
|
||||||
#define DMA_CH5M0ADDR(dmax) REG32((dmax) + 0x94U) /*!< DMA channel 5 memory 0 base address register */
|
#define DMA_CH5M0ADDR(dmax) REG32((dmax) + 0x00000094U) /*!< DMA channel 5 memory 0 base address register */
|
||||||
#define DMA_CH5M1ADDR(dmax) REG32((dmax) + 0x98U) /*!< DMA channel 5 memory 1 base address register */
|
#define DMA_CH5M1ADDR(dmax) REG32((dmax) + 0x00000098U) /*!< DMA channel 5 memory 1 base address register */
|
||||||
#define DMA_CH5FCTL(dmax) REG32((dmax) + 0x9CU) /*!< DMA channel 5 FIFO control register */
|
#define DMA_CH5FCTL(dmax) REG32((dmax) + 0x0000009CU) /*!< DMA channel 5 FIFO control register */
|
||||||
|
|
||||||
#define DMA_CH6CTL(dmax) REG32((dmax) + 0xA0U) /*!< DMA channel 6 control register */
|
#define DMA_CH6CTL(dmax) REG32((dmax) + 0x000000A0U) /*!< DMA channel 6 control register */
|
||||||
#define DMA_CH6CNT(dmax) REG32((dmax) + 0xA4U) /*!< DMA channel 6 counter register */
|
#define DMA_CH6CNT(dmax) REG32((dmax) + 0x000000A4U) /*!< DMA channel 6 counter register */
|
||||||
#define DMA_CH6PADDR(dmax) REG32((dmax) + 0xA8U) /*!< DMA channel 6 peripheral base address register */
|
#define DMA_CH6PADDR(dmax) REG32((dmax) + 0x000000A8U) /*!< DMA channel 6 peripheral base address register */
|
||||||
#define DMA_CH6M0ADDR(dmax) REG32((dmax) + 0xACU) /*!< DMA channel 6 memory 0 base address register */
|
#define DMA_CH6M0ADDR(dmax) REG32((dmax) + 0x000000ACU) /*!< DMA channel 6 memory 0 base address register */
|
||||||
#define DMA_CH6M1ADDR(dmax) REG32((dmax) + 0xB0U) /*!< DMA channel 6 memory 1 base address register */
|
#define DMA_CH6M1ADDR(dmax) REG32((dmax) + 0x000000B0U) /*!< DMA channel 6 memory 1 base address register */
|
||||||
#define DMA_CH6FCTL(dmax) REG32((dmax) + 0xB4U) /*!< DMA channel 6 FIFO control register */
|
#define DMA_CH6FCTL(dmax) REG32((dmax) + 0x000000B4U) /*!< DMA channel 6 FIFO control register */
|
||||||
|
|
||||||
#define DMA_CH7CTL(dmax) REG32((dmax) + 0xB8U) /*!< DMA channel 7 control register */
|
#define DMA_CH7CTL(dmax) REG32((dmax) + 0x000000B8U) /*!< DMA channel 7 control register */
|
||||||
#define DMA_CH7CNT(dmax) REG32((dmax) + 0xBCU) /*!< DMA channel 7 counter register */
|
#define DMA_CH7CNT(dmax) REG32((dmax) + 0x000000BCU) /*!< DMA channel 7 counter register */
|
||||||
#define DMA_CH7PADDR(dmax) REG32((dmax) + 0xC0U) /*!< DMA channel 7 peripheral base address register */
|
#define DMA_CH7PADDR(dmax) REG32((dmax) + 0x000000C0U) /*!< DMA channel 7 peripheral base address register */
|
||||||
#define DMA_CH7M0ADDR(dmax) REG32((dmax) + 0xC4U) /*!< DMA channel 7 memory 0 base address register */
|
#define DMA_CH7M0ADDR(dmax) REG32((dmax) + 0x000000C4U) /*!< DMA channel 7 memory 0 base address register */
|
||||||
#define DMA_CH7M1ADDR(dmax) REG32((dmax) + 0xC8U) /*!< DMA channel 7 memory 1 base address register */
|
#define DMA_CH7M1ADDR(dmax) REG32((dmax) + 0x000000C8U) /*!< DMA channel 7 memory 1 base address register */
|
||||||
#define DMA_CH7FCTL(dmax) REG32((dmax) + 0xCCU) /*!< DMA channel 7 FIFO control register */
|
#define DMA_CH7FCTL(dmax) REG32((dmax) + 0x000000CCU) /*!< DMA channel 7 FIFO control register */
|
||||||
|
|
||||||
/* bits definitions */
|
/* bits definitions */
|
||||||
/* DMA_INTF */
|
/* DMA_INTF */
|
||||||
|
|
@ -416,13 +416,13 @@ uint32_t dma_fifo_status_get(uint32_t dma_periph, dma_channel_enum channelx);
|
||||||
FlagStatus dma_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag);
|
FlagStatus dma_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag);
|
||||||
/* clear DMA a channel flag */
|
/* clear DMA a channel flag */
|
||||||
void dma_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag);
|
void dma_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag);
|
||||||
/* check DMA flag is set or not */
|
|
||||||
FlagStatus dma_interrupt_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t interrupt);
|
|
||||||
/* clear DMA a channel flag */
|
|
||||||
void dma_interrupt_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t interrupt);
|
|
||||||
/* enable DMA interrupt */
|
/* enable DMA interrupt */
|
||||||
void dma_interrupt_enable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source);
|
void dma_interrupt_enable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source);
|
||||||
/* disable DMA interrupt */
|
/* disable DMA interrupt */
|
||||||
void dma_interrupt_disable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source);
|
void dma_interrupt_disable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source);
|
||||||
|
/* check DMA flag is set or not */
|
||||||
|
FlagStatus dma_interrupt_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t interrupt);
|
||||||
|
/* clear DMA a channel flag */
|
||||||
|
void dma_interrupt_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t interrupt);
|
||||||
|
|
||||||
#endif /* GD32F4XX_DMA_H */
|
#endif /* GD32F4XX_DMA_H */
|
||||||
|
|
|
||||||
|
|
@ -5,10 +5,11 @@
|
||||||
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
||||||
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
||||||
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
||||||
|
\version 2022-03-09, V3.0.0, firmware for GD32F4xx
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/*
|
/*
|
||||||
Copyright (c) 2020, GigaDevice Semiconductor Inc.
|
Copyright (c) 2022, GigaDevice Semiconductor Inc.
|
||||||
|
|
||||||
Redistribution and use in source and binary forms, with or without modification,
|
Redistribution and use in source and binary forms, with or without modification,
|
||||||
are permitted provided that the following conditions are met:
|
are permitted provided that the following conditions are met:
|
||||||
|
|
@ -123,7 +124,7 @@ OF SUCH DAMAGE.
|
||||||
#define ENET_MAC_HLH REG32((ENET) + 0x0008U) /*!< ethernet MAC hash list high register */
|
#define ENET_MAC_HLH REG32((ENET) + 0x0008U) /*!< ethernet MAC hash list high register */
|
||||||
#define ENET_MAC_HLL REG32((ENET) + 0x000CU) /*!< ethernet MAC hash list low register */
|
#define ENET_MAC_HLL REG32((ENET) + 0x000CU) /*!< ethernet MAC hash list low register */
|
||||||
#define ENET_MAC_PHY_CTL REG32((ENET) + 0x0010U) /*!< ethernet MAC PHY control register */
|
#define ENET_MAC_PHY_CTL REG32((ENET) + 0x0010U) /*!< ethernet MAC PHY control register */
|
||||||
#define ENET_MAC_PHY_DATA REG32((ENET) + 0x0014U) /*!< ethernet MAC MII data register */
|
#define ENET_MAC_PHY_DATA REG32((ENET) + 0x0014U) /*!< ethernet MAC PHY data register */
|
||||||
#define ENET_MAC_FCTL REG32((ENET) + 0x0018U) /*!< ethernet MAC flow control register */
|
#define ENET_MAC_FCTL REG32((ENET) + 0x0018U) /*!< ethernet MAC flow control register */
|
||||||
#define ENET_MAC_VLT REG32((ENET) + 0x001CU) /*!< ethernet MAC VLAN tag register */
|
#define ENET_MAC_VLT REG32((ENET) + 0x001CU) /*!< ethernet MAC VLAN tag register */
|
||||||
#define ENET_MAC_RWFF REG32((ENET) + 0x0028U) /*!< ethernet MAC remote wakeup frame filter register */
|
#define ENET_MAC_RWFF REG32((ENET) + 0x0028U) /*!< ethernet MAC remote wakeup frame filter register */
|
||||||
|
|
@ -1112,7 +1113,7 @@ typedef struct
|
||||||
#define ENET_MDC_HCLK_DIV62 MAC_PHY_CTL_CLR(1) /*!< HCLK:100-150 MHz; MDC clock= HCLK/62 */
|
#define ENET_MDC_HCLK_DIV62 MAC_PHY_CTL_CLR(1) /*!< HCLK:100-150 MHz; MDC clock= HCLK/62 */
|
||||||
#define ENET_MDC_HCLK_DIV16 MAC_PHY_CTL_CLR(2) /*!< HCLK:20-35 MHz; MDC clock= HCLK/16 */
|
#define ENET_MDC_HCLK_DIV16 MAC_PHY_CTL_CLR(2) /*!< HCLK:20-35 MHz; MDC clock= HCLK/16 */
|
||||||
#define ENET_MDC_HCLK_DIV26 MAC_PHY_CTL_CLR(3) /*!< HCLK:35-60 MHz; MDC clock= HCLK/26 */
|
#define ENET_MDC_HCLK_DIV26 MAC_PHY_CTL_CLR(3) /*!< HCLK:35-60 MHz; MDC clock= HCLK/26 */
|
||||||
#define ENET_MDC_HCLK_DIV102 MAC_PHY_CTL_CLR(4) /*!< HCLK:150-200 MHz; MDC clock= HCLK/102 */
|
#define ENET_MDC_HCLK_DIV102 MAC_PHY_CTL_CLR(4) /*!< HCLK:150-240 MHz; MDC clock= HCLK/102 */
|
||||||
|
|
||||||
#define MAC_PHY_CTL_PR(regval) (BITS(6,10) & ((uint32_t)(regval) << 6)) /*!< write value to ENET_MAC_PHY_CTL_PR bit field */
|
#define MAC_PHY_CTL_PR(regval) (BITS(6,10) & ((uint32_t)(regval) << 6)) /*!< write value to ENET_MAC_PHY_CTL_PR bit field */
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -5,10 +5,12 @@
|
||||||
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
||||||
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
||||||
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
||||||
|
\version 2022-03-09, V3.0.0, firmware for GD32F4xx
|
||||||
|
\version 2022-06-08, V3.0.1, firmware for GD32F4xx
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/*
|
/*
|
||||||
Copyright (c) 2020, GigaDevice Semiconductor Inc.
|
Copyright (c) 2022, GigaDevice Semiconductor Inc.
|
||||||
|
|
||||||
Redistribution and use in source and binary forms, with or without modification,
|
Redistribution and use in source and binary forms, with or without modification,
|
||||||
are permitted provided that the following conditions are met:
|
are permitted provided that the following conditions are met:
|
||||||
|
|
@ -113,13 +115,13 @@ OF SUCH DAMAGE.
|
||||||
#define EXMC_SNCTL_NRWTPOL BIT(9) /*!< NWAIT signal polarity */
|
#define EXMC_SNCTL_NRWTPOL BIT(9) /*!< NWAIT signal polarity */
|
||||||
#define EXMC_SNCTL_WRAPEN BIT(10) /*!< wrapped burst mode enable */
|
#define EXMC_SNCTL_WRAPEN BIT(10) /*!< wrapped burst mode enable */
|
||||||
#define EXMC_SNCTL_NRWTCFG BIT(11) /*!< NWAIT signal configuration, only work in synchronous mode */
|
#define EXMC_SNCTL_NRWTCFG BIT(11) /*!< NWAIT signal configuration, only work in synchronous mode */
|
||||||
#define EXMC_SNCTL_WREN BIT(12) /*!< write enable */
|
#define EXMC_SNCTL_WEN BIT(12) /*!< write enable */
|
||||||
#define EXMC_SNCTL_NRWTEN BIT(13) /*!< NWAIT signal enable */
|
#define EXMC_SNCTL_NRWTEN BIT(13) /*!< NWAIT signal enable */
|
||||||
#define EXMC_SNCTL_EXMODEN BIT(14) /*!< extended mode enable */
|
#define EXMC_SNCTL_EXMODEN BIT(14) /*!< extended mode enable */
|
||||||
#define EXMC_SNCTL_ASYNCWAIT BIT(15) /*!< asynchronous wait enable */
|
#define EXMC_SNCTL_ASYNCWTEN BIT(15) /*!< asynchronous wait enable */
|
||||||
#define EXMC_SNCTL_CPS BITS(16,18) /*!< CRAM page size */
|
#define EXMC_SNCTL_CPS BITS(16,18) /*!< CRAM page size */
|
||||||
#define EXMC_SNCTL_SYNCWR BIT(19) /*!< synchronous write config */
|
#define EXMC_SNCTL_SYNCWR BIT(19) /*!< synchronous write configuration */
|
||||||
#define EXMC_SNCTL_CCK BIT(20) /*!< consecutive clock config */
|
#define EXMC_SNCTL_CCK BIT(20) /*!< consecutive clock configuration */
|
||||||
|
|
||||||
/* EXMC_SNTCFGx,x=0..3 */
|
/* EXMC_SNTCFGx,x=0..3 */
|
||||||
#define EXMC_SNTCFG_ASET BITS(0,3) /*!< asynchronous address setup time */
|
#define EXMC_SNTCFG_ASET BITS(0,3) /*!< asynchronous address setup time */
|
||||||
|
|
@ -207,7 +209,7 @@ OF SUCH DAMAGE.
|
||||||
/* EXMC_SDARI */
|
/* EXMC_SDARI */
|
||||||
#define EXMC_SDARI_REC BIT(0) /*!< refresh error flag clear */
|
#define EXMC_SDARI_REC BIT(0) /*!< refresh error flag clear */
|
||||||
#define EXMC_SDARI_ARINTV BITS(1,13) /*!< auto-refresh interval */
|
#define EXMC_SDARI_ARINTV BITS(1,13) /*!< auto-refresh interval */
|
||||||
#define EXMC_SDARI_REIE BIT(14) /*!< interrupt refresh error enable */
|
#define EXMC_SDARI_REIE BIT(14) /*!< refresh error interrupt enable */
|
||||||
|
|
||||||
/* EXMC_SDSTAT */
|
/* EXMC_SDSTAT */
|
||||||
#define EXMC_SDSDAT_REIF BIT(0) /*!< refresh error interrupt flag */
|
#define EXMC_SDSDAT_REIF BIT(0) /*!< refresh error interrupt flag */
|
||||||
|
|
@ -278,7 +280,7 @@ typedef struct
|
||||||
exmc_norsram_timing_parameter_struct* write_timing; /*!< timing parameters for write when the extendedmode is used. */
|
exmc_norsram_timing_parameter_struct* write_timing; /*!< timing parameters for write when the extendedmode is used. */
|
||||||
}exmc_norsram_parameter_struct;
|
}exmc_norsram_parameter_struct;
|
||||||
|
|
||||||
/* EXMC NAND/PC card timing initialize struct */
|
/* EXMC NAND/PC card timing initialize structure */
|
||||||
typedef struct
|
typedef struct
|
||||||
{
|
{
|
||||||
uint32_t databus_hiztime; /*!< configure the dadtabus HiZ time for write operation */
|
uint32_t databus_hiztime; /*!< configure the dadtabus HiZ time for write operation */
|
||||||
|
|
@ -287,7 +289,7 @@ typedef struct
|
||||||
uint32_t setuptime; /*!< configure the address setup time */
|
uint32_t setuptime; /*!< configure the address setup time */
|
||||||
}exmc_nand_pccard_timing_parameter_struct;
|
}exmc_nand_pccard_timing_parameter_struct;
|
||||||
|
|
||||||
/* EXMC NAND initialize struct */
|
/* EXMC NAND initialize structure */
|
||||||
typedef struct
|
typedef struct
|
||||||
{
|
{
|
||||||
uint32_t nand_bank; /*!< select the bank of NAND */
|
uint32_t nand_bank; /*!< select the bank of NAND */
|
||||||
|
|
@ -301,7 +303,7 @@ typedef struct
|
||||||
exmc_nand_pccard_timing_parameter_struct* attribute_space_timing; /*!< the timing parameters for NAND flash attribute space */
|
exmc_nand_pccard_timing_parameter_struct* attribute_space_timing; /*!< the timing parameters for NAND flash attribute space */
|
||||||
}exmc_nand_parameter_struct;
|
}exmc_nand_parameter_struct;
|
||||||
|
|
||||||
/* EXMC PC card initialize struct */
|
/* EXMC PC card initialize structure */
|
||||||
typedef struct
|
typedef struct
|
||||||
{
|
{
|
||||||
uint32_t atr_latency; /*!< configure the latency of ALE low to RB low */
|
uint32_t atr_latency; /*!< configure the latency of ALE low to RB low */
|
||||||
|
|
@ -312,7 +314,7 @@ typedef struct
|
||||||
exmc_nand_pccard_timing_parameter_struct* io_space_timing; /*!< the timing parameters for PC card IO space */
|
exmc_nand_pccard_timing_parameter_struct* io_space_timing; /*!< the timing parameters for PC card IO space */
|
||||||
}exmc_pccard_parameter_struct;
|
}exmc_pccard_parameter_struct;
|
||||||
|
|
||||||
/* EXMC SDRAM timing initialize struct */
|
/* EXMC SDRAM timing initialize structure */
|
||||||
typedef struct
|
typedef struct
|
||||||
{
|
{
|
||||||
uint32_t row_to_column_delay; /*!< configure the row to column delay */
|
uint32_t row_to_column_delay; /*!< configure the row to column delay */
|
||||||
|
|
@ -324,12 +326,12 @@ typedef struct
|
||||||
uint32_t load_mode_register_delay; /*!< configure the load mode register delay */
|
uint32_t load_mode_register_delay; /*!< configure the load mode register delay */
|
||||||
}exmc_sdram_timing_parameter_struct;
|
}exmc_sdram_timing_parameter_struct;
|
||||||
|
|
||||||
/* EXMC SDRAM initialize struct */
|
/* EXMC SDRAM initialize structure */
|
||||||
typedef struct
|
typedef struct
|
||||||
{
|
{
|
||||||
uint32_t sdram_device; /*!< device of SDRAM */
|
uint32_t sdram_device; /*!< device of SDRAM */
|
||||||
uint32_t pipeline_read_delay; /*!< the delay for reading data after CAS latency in HCLK clock cycles */
|
uint32_t pipeline_read_delay; /*!< the delay for reading data after CAS latency in HCLK clock cycles */
|
||||||
uint32_t brust_read_switch; /*!< enable or disable the burst read */
|
uint32_t burst_read_switch; /*!< enable or disable the burst read */
|
||||||
uint32_t sdclock_config; /*!< the SDCLK memory clock for both SDRAM banks */
|
uint32_t sdclock_config; /*!< the SDCLK memory clock for both SDRAM banks */
|
||||||
uint32_t write_protection; /*!< enable or disable SDRAM bank write protection function */
|
uint32_t write_protection; /*!< enable or disable SDRAM bank write protection function */
|
||||||
uint32_t cas_latency; /*!< configure the SDRAM CAS latency */
|
uint32_t cas_latency; /*!< configure the SDRAM CAS latency */
|
||||||
|
|
@ -340,7 +342,7 @@ typedef struct
|
||||||
exmc_sdram_timing_parameter_struct* timing; /*!< the timing parameters for write and read SDRAM */
|
exmc_sdram_timing_parameter_struct* timing; /*!< the timing parameters for write and read SDRAM */
|
||||||
}exmc_sdram_parameter_struct;
|
}exmc_sdram_parameter_struct;
|
||||||
|
|
||||||
/* EXMC SDRAM command initialize struct */
|
/* EXMC SDRAM command initialize structure */
|
||||||
typedef struct
|
typedef struct
|
||||||
{
|
{
|
||||||
uint32_t mode_register_content; /*!< the SDRAM mode register content */
|
uint32_t mode_register_content; /*!< the SDRAM mode register content */
|
||||||
|
|
@ -349,7 +351,7 @@ typedef struct
|
||||||
uint32_t command; /*!< the commands that will be sent to SDRAM */
|
uint32_t command; /*!< the commands that will be sent to SDRAM */
|
||||||
}exmc_sdram_command_parameter_struct;
|
}exmc_sdram_command_parameter_struct;
|
||||||
|
|
||||||
/* EXMC SQPISRAM initialize struct */
|
/* EXMC SQPISRAM initialize structure */
|
||||||
typedef struct{
|
typedef struct{
|
||||||
uint32_t sample_polarity; /*!< read data sample polarity */
|
uint32_t sample_polarity; /*!< read data sample polarity */
|
||||||
uint32_t id_length; /*!< SPI PSRAM ID length */
|
uint32_t id_length; /*!< SPI PSRAM ID length */
|
||||||
|
|
@ -357,7 +359,7 @@ typedef struct{
|
||||||
uint32_t command_bits; /*!< bit number of SPI PSRAM command phase */
|
uint32_t command_bits; /*!< bit number of SPI PSRAM command phase */
|
||||||
}exmc_sqpipsram_parameter_struct;
|
}exmc_sqpipsram_parameter_struct;
|
||||||
|
|
||||||
/* EXMC_register address */
|
/* EXMC register address */
|
||||||
#define EXMC_SNCTL(region) REG32(EXMC + 0x08U*((uint32_t)(region))) /*!< EXMC SRAM/NOR flash control registers, region = 0,1,2,3 */
|
#define EXMC_SNCTL(region) REG32(EXMC + 0x08U*((uint32_t)(region))) /*!< EXMC SRAM/NOR flash control registers, region = 0,1,2,3 */
|
||||||
#define EXMC_SNTCFG(region) REG32(EXMC + 0x04U + 0x08U*((uint32_t)(region))) /*!< EXMC SRAM/NOR flash timing configuration registers, region = 0,1,2,3 */
|
#define EXMC_SNTCFG(region) REG32(EXMC + 0x04U + 0x08U*((uint32_t)(region))) /*!< EXMC SRAM/NOR flash timing configuration registers, region = 0,1,2,3 */
|
||||||
#define EXMC_SNWTCFG(region) REG32(EXMC + 0x104U + 0x08U*((uint32_t)(region))) /*!< EXMC SRAM/NOR flash write timing configuration registers, region = 0,1,2,3 */
|
#define EXMC_SNWTCFG(region) REG32(EXMC + 0x104U + 0x08U*((uint32_t)(region))) /*!< EXMC SRAM/NOR flash write timing configuration registers, region = 0,1,2,3 */
|
||||||
|
|
@ -418,6 +420,7 @@ typedef struct{
|
||||||
|
|
||||||
/* synchronous clock divide ratio */
|
/* synchronous clock divide ratio */
|
||||||
#define SNTCFG_CKDIV(regval) (BITS(20,23) & ((uint32_t)(regval) << 20))
|
#define SNTCFG_CKDIV(regval) (BITS(20,23) & ((uint32_t)(regval) << 20))
|
||||||
|
#define EXMC_SYN_CLOCK_RATIO_DISABLE SNTCFG_CKDIV(0) /*!< EXMC_CLK disable */
|
||||||
#define EXMC_SYN_CLOCK_RATIO_2_CLK SNTCFG_CKDIV(1) /*!< EXMC_CLK = 2*HCLK */
|
#define EXMC_SYN_CLOCK_RATIO_2_CLK SNTCFG_CKDIV(1) /*!< EXMC_CLK = 2*HCLK */
|
||||||
#define EXMC_SYN_CLOCK_RATIO_3_CLK SNTCFG_CKDIV(2) /*!< EXMC_CLK = 3*HCLK */
|
#define EXMC_SYN_CLOCK_RATIO_3_CLK SNTCFG_CKDIV(2) /*!< EXMC_CLK = 3*HCLK */
|
||||||
#define EXMC_SYN_CLOCK_RATIO_4_CLK SNTCFG_CKDIV(3) /*!< EXMC_CLK = 4*HCLK */
|
#define EXMC_SYN_CLOCK_RATIO_4_CLK SNTCFG_CKDIV(3) /*!< EXMC_CLK = 4*HCLK */
|
||||||
|
|
@ -541,7 +544,7 @@ typedef struct{
|
||||||
#define EXMC_SDRAM_AUTO_REFLESH_14_SDCLK SDCMD_NARF(13) /*!< 14 auto-refresh cycles */
|
#define EXMC_SDRAM_AUTO_REFLESH_14_SDCLK SDCMD_NARF(13) /*!< 14 auto-refresh cycles */
|
||||||
#define EXMC_SDRAM_AUTO_REFLESH_15_SDCLK SDCMD_NARF(14) /*!< 15 auto-refresh cycles */
|
#define EXMC_SDRAM_AUTO_REFLESH_15_SDCLK SDCMD_NARF(14) /*!< 15 auto-refresh cycles */
|
||||||
|
|
||||||
/* SDRAM command select */
|
/* SDRAM command selection */
|
||||||
#define SDCMD_CMD(regval) (BITS(0,2) & ((uint32_t)(regval) << 0))
|
#define SDCMD_CMD(regval) (BITS(0,2) & ((uint32_t)(regval) << 0))
|
||||||
#define EXMC_SDRAM_NORMAL_OPERATION SDCMD_CMD(0) /*!< normal operation command */
|
#define EXMC_SDRAM_NORMAL_OPERATION SDCMD_CMD(0) /*!< normal operation command */
|
||||||
#define EXMC_SDRAM_CLOCK_ENABLE SDCMD_CMD(1) /*!< clock enable command */
|
#define EXMC_SDRAM_CLOCK_ENABLE SDCMD_CMD(1) /*!< clock enable command */
|
||||||
|
|
@ -661,13 +664,13 @@ typedef struct{
|
||||||
#define EXMC_SDRAM_2_INTER_BANK ((uint32_t)0x00000000U) /*!< 2 internal banks */
|
#define EXMC_SDRAM_2_INTER_BANK ((uint32_t)0x00000000U) /*!< 2 internal banks */
|
||||||
#define EXMC_SDRAM_4_INTER_BANK EXMC_SDCTL_NBK /*!< 4 internal banks */
|
#define EXMC_SDRAM_4_INTER_BANK EXMC_SDCTL_NBK /*!< 4 internal banks */
|
||||||
|
|
||||||
/* SDRAM device0 select */
|
/* SDRAM device0 selection */
|
||||||
#define EXMC_SDRAM_DEVICE0_UNSELECT ((uint32_t)0x00000000U) /*!< SDRAM device0 unselect */
|
#define EXMC_SDRAM_DEVICE0_UNSELECT ((uint32_t)0x00000000U) /*!< unselect SDRAM device0 */
|
||||||
#define EXMC_SDRAM_DEVICE0_SELECT EXMC_SDCMD_DS0 /*!< SDRAM device0 select */
|
#define EXMC_SDRAM_DEVICE0_SELECT EXMC_SDCMD_DS0 /*!< select SDRAM device0 */
|
||||||
|
|
||||||
/* SDRAM device1 select */
|
/* SDRAM device1 selection */
|
||||||
#define EXMC_SDRAM_DEVICE1_UNSELECT ((uint32_t)0x00000000U) /*!< SDRAM device1 unselect */
|
#define EXMC_SDRAM_DEVICE1_UNSELECT ((uint32_t)0x00000000U) /*!< unselect SDRAM device1 */
|
||||||
#define EXMC_SDRAM_DEVICE1_SELECT EXMC_SDCMD_DS1 /*!< SDRAM device1 select */
|
#define EXMC_SDRAM_DEVICE1_SELECT EXMC_SDCMD_DS1 /*!< select SDRAM device1 */
|
||||||
|
|
||||||
/* SDRAM device status */
|
/* SDRAM device status */
|
||||||
#define EXMC_SDRAM_DEVICE_NORMAL ((uint32_t)0x00000000U) /*!< normal status */
|
#define EXMC_SDRAM_DEVICE_NORMAL ((uint32_t)0x00000000U) /*!< normal status */
|
||||||
|
|
@ -716,7 +719,7 @@ void exmc_norsram_disable(uint32_t exmc_norsram_region);
|
||||||
/* NAND */
|
/* NAND */
|
||||||
/* deinitialize EXMC NAND bank */
|
/* deinitialize EXMC NAND bank */
|
||||||
void exmc_nand_deinit(uint32_t exmc_nand_bank);
|
void exmc_nand_deinit(uint32_t exmc_nand_bank);
|
||||||
/* initialize exmc_norsram_parameter_struct with the default values */
|
/* initialize exmc_nand_parameter_struct with the default values */
|
||||||
void exmc_nand_struct_para_init(exmc_nand_parameter_struct* exmc_nand_init_struct);
|
void exmc_nand_struct_para_init(exmc_nand_parameter_struct* exmc_nand_init_struct);
|
||||||
/* initialize EXMC NAND bank */
|
/* initialize EXMC NAND bank */
|
||||||
void exmc_nand_init(exmc_nand_parameter_struct* exmc_nand_init_struct);
|
void exmc_nand_init(exmc_nand_parameter_struct* exmc_nand_init_struct);
|
||||||
|
|
@ -742,6 +745,8 @@ void exmc_sdram_deinit(uint32_t exmc_sdram_device);
|
||||||
void exmc_sdram_struct_para_init(exmc_sdram_parameter_struct* exmc_sdram_init_struct);
|
void exmc_sdram_struct_para_init(exmc_sdram_parameter_struct* exmc_sdram_init_struct);
|
||||||
/* initialize EXMC SDRAM device */
|
/* initialize EXMC SDRAM device */
|
||||||
void exmc_sdram_init(exmc_sdram_parameter_struct* exmc_sdram_init_struct);
|
void exmc_sdram_init(exmc_sdram_parameter_struct* exmc_sdram_init_struct);
|
||||||
|
/* initialize exmc_sdram_command_parameter_struct with the default values */
|
||||||
|
void exmc_sdram_struct_command_para_init(exmc_sdram_command_parameter_struct *exmc_sdram_command_init_struct);
|
||||||
/* SQPIPSRAM */
|
/* SQPIPSRAM */
|
||||||
/* deinitialize EXMC SQPIPSRAM */
|
/* deinitialize EXMC SQPIPSRAM */
|
||||||
void exmc_sqpipsram_deinit(void);
|
void exmc_sqpipsram_deinit(void);
|
||||||
|
|
@ -772,7 +777,7 @@ void exmc_sdram_command_config(exmc_sdram_command_parameter_struct* exmc_sdram_c
|
||||||
void exmc_sdram_refresh_count_set(uint32_t exmc_count);
|
void exmc_sdram_refresh_count_set(uint32_t exmc_count);
|
||||||
/* set the number of successive auto-refresh command */
|
/* set the number of successive auto-refresh command */
|
||||||
void exmc_sdram_autorefresh_number_set(uint32_t exmc_number);
|
void exmc_sdram_autorefresh_number_set(uint32_t exmc_number);
|
||||||
/* config the write protection function */
|
/* configure the write protection function */
|
||||||
void exmc_sdram_write_protection_config(uint32_t exmc_sdram_device, ControlStatus newvalue);
|
void exmc_sdram_write_protection_config(uint32_t exmc_sdram_device, ControlStatus newvalue);
|
||||||
/* get the status of SDRAM device0 or device1 */
|
/* get the status of SDRAM device0 or device1 */
|
||||||
uint32_t exmc_sdram_bankstatus_get(uint32_t exmc_sdram_device);
|
uint32_t exmc_sdram_bankstatus_get(uint32_t exmc_sdram_device);
|
||||||
|
|
|
||||||
|
|
@ -1,14 +1,14 @@
|
||||||
/*!
|
/*!
|
||||||
\file gd32f4xx_exti.h
|
\file gd32f4xx_exti.h
|
||||||
\brief definitions for the EXTI
|
\brief definitions for the EXTI
|
||||||
|
|
||||||
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
||||||
\version 2018-12-12, V2.0.1, firmware for GD32F4xx
|
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
||||||
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
||||||
|
\version 2022-03-09, V3.0.0, firmware for GD32F4xx
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/*
|
/*
|
||||||
Copyright (c) 2020, GigaDevice Semiconductor Inc.
|
Copyright (c) 2022, GigaDevice Semiconductor Inc.
|
||||||
|
|
||||||
Redistribution and use in source and binary forms, with or without modification,
|
Redistribution and use in source and binary forms, with or without modification,
|
||||||
are permitted provided that the following conditions are met:
|
are permitted provided that the following conditions are met:
|
||||||
|
|
@ -177,34 +177,33 @@ OF SUCH DAMAGE.
|
||||||
#define EXTI_SWIEV_SWIEV22 BIT(22) /*!< software interrupt/event request from line 22 */
|
#define EXTI_SWIEV_SWIEV22 BIT(22) /*!< software interrupt/event request from line 22 */
|
||||||
|
|
||||||
/* EXTI_PD */
|
/* EXTI_PD */
|
||||||
#define EXTI_PD_PD0 BIT(0) /*!< interrupt/event pending status from line 0 */
|
#define EXTI_PD_PD0 BIT(0) /*!< interrupt pending status from line 0 */
|
||||||
#define EXTI_PD_PD1 BIT(1) /*!< interrupt/event pending status from line 1 */
|
#define EXTI_PD_PD1 BIT(1) /*!< interrupt pending status from line 1 */
|
||||||
#define EXTI_PD_PD2 BIT(2) /*!< interrupt/event pending status from line 2 */
|
#define EXTI_PD_PD2 BIT(2) /*!< interrupt pending status from line 2 */
|
||||||
#define EXTI_PD_PD3 BIT(3) /*!< interrupt/event pending status from line 3 */
|
#define EXTI_PD_PD3 BIT(3) /*!< interrupt pending status from line 3 */
|
||||||
#define EXTI_PD_PD4 BIT(4) /*!< interrupt/event pending status from line 4 */
|
#define EXTI_PD_PD4 BIT(4) /*!< interrupt pending status from line 4 */
|
||||||
#define EXTI_PD_PD5 BIT(5) /*!< interrupt/event pending status from line 5 */
|
#define EXTI_PD_PD5 BIT(5) /*!< interrupt pending status from line 5 */
|
||||||
#define EXTI_PD_PD6 BIT(6) /*!< interrupt/event pending status from line 6 */
|
#define EXTI_PD_PD6 BIT(6) /*!< interrupt pending status from line 6 */
|
||||||
#define EXTI_PD_PD7 BIT(7) /*!< interrupt/event pending status from line 7 */
|
#define EXTI_PD_PD7 BIT(7) /*!< interrupt pending status from line 7 */
|
||||||
#define EXTI_PD_PD8 BIT(8) /*!< interrupt/event pending status from line 8 */
|
#define EXTI_PD_PD8 BIT(8) /*!< interrupt pending status from line 8 */
|
||||||
#define EXTI_PD_PD9 BIT(9) /*!< interrupt/event pending status from line 9 */
|
#define EXTI_PD_PD9 BIT(9) /*!< interrupt pending status from line 9 */
|
||||||
#define EXTI_PD_PD10 BIT(10) /*!< interrupt/event pending status from line 10 */
|
#define EXTI_PD_PD10 BIT(10) /*!< interrupt pending status from line 10 */
|
||||||
#define EXTI_PD_PD11 BIT(11) /*!< interrupt/event pending status from line 11 */
|
#define EXTI_PD_PD11 BIT(11) /*!< interrupt pending status from line 11 */
|
||||||
#define EXTI_PD_PD12 BIT(12) /*!< interrupt/event pending status from line 12 */
|
#define EXTI_PD_PD12 BIT(12) /*!< interrupt pending status from line 12 */
|
||||||
#define EXTI_PD_PD13 BIT(13) /*!< interrupt/event pending status from line 13 */
|
#define EXTI_PD_PD13 BIT(13) /*!< interrupt pending status from line 13 */
|
||||||
#define EXTI_PD_PD14 BIT(14) /*!< interrupt/event pending status from line 14 */
|
#define EXTI_PD_PD14 BIT(14) /*!< interrupt pending status from line 14 */
|
||||||
#define EXTI_PD_PD15 BIT(15) /*!< interrupt/event pending status from line 15 */
|
#define EXTI_PD_PD15 BIT(15) /*!< interrupt pending status from line 15 */
|
||||||
#define EXTI_PD_PD16 BIT(16) /*!< interrupt/event pending status from line 16 */
|
#define EXTI_PD_PD16 BIT(16) /*!< interrupt pending status from line 16 */
|
||||||
#define EXTI_PD_PD17 BIT(17) /*!< interrupt/event pending status from line 17 */
|
#define EXTI_PD_PD17 BIT(17) /*!< interrupt pending status from line 17 */
|
||||||
#define EXTI_PD_PD18 BIT(18) /*!< interrupt/event pending status from line 18 */
|
#define EXTI_PD_PD18 BIT(18) /*!< interrupt pending status from line 18 */
|
||||||
#define EXTI_PD_PD19 BIT(19) /*!< interrupt/event pending status from line 19 */
|
#define EXTI_PD_PD19 BIT(19) /*!< interrupt pending status from line 19 */
|
||||||
#define EXTI_PD_PD20 BIT(20) /*!< interrupt/event pending status from line 20 */
|
#define EXTI_PD_PD20 BIT(20) /*!< interrupt pending status from line 20 */
|
||||||
#define EXTI_PD_PD21 BIT(21) /*!< interrupt/event pending status from line 21 */
|
#define EXTI_PD_PD21 BIT(21) /*!< interrupt pending status from line 21 */
|
||||||
#define EXTI_PD_PD22 BIT(22) /*!< interrupt/event pending status from line 22 */
|
#define EXTI_PD_PD22 BIT(22) /*!< interrupt pending status from line 22 */
|
||||||
|
|
||||||
/* constants definitions */
|
/* constants definitions */
|
||||||
/* EXTI line number */
|
/* EXTI line number */
|
||||||
typedef enum
|
typedef enum {
|
||||||
{
|
|
||||||
EXTI_0 = BIT(0), /*!< EXTI line 0 */
|
EXTI_0 = BIT(0), /*!< EXTI line 0 */
|
||||||
EXTI_1 = BIT(1), /*!< EXTI line 1 */
|
EXTI_1 = BIT(1), /*!< EXTI line 1 */
|
||||||
EXTI_2 = BIT(2), /*!< EXTI line 2 */
|
EXTI_2 = BIT(2), /*!< EXTI line 2 */
|
||||||
|
|
@ -227,19 +226,17 @@ typedef enum
|
||||||
EXTI_19 = BIT(19), /*!< EXTI line 19 */
|
EXTI_19 = BIT(19), /*!< EXTI line 19 */
|
||||||
EXTI_20 = BIT(20), /*!< EXTI line 20 */
|
EXTI_20 = BIT(20), /*!< EXTI line 20 */
|
||||||
EXTI_21 = BIT(21), /*!< EXTI line 21 */
|
EXTI_21 = BIT(21), /*!< EXTI line 21 */
|
||||||
EXTI_22 = BIT(22), /*!< EXTI line 22 */
|
EXTI_22 = BIT(22) /*!< EXTI line 22 */
|
||||||
} exti_line_enum;
|
} exti_line_enum;
|
||||||
|
|
||||||
/* external interrupt and event */
|
/* external interrupt and event */
|
||||||
typedef enum
|
typedef enum {
|
||||||
{
|
|
||||||
EXTI_INTERRUPT = 0, /*!< EXTI interrupt mode */
|
EXTI_INTERRUPT = 0, /*!< EXTI interrupt mode */
|
||||||
EXTI_EVENT /*!< EXTI event mode */
|
EXTI_EVENT /*!< EXTI event mode */
|
||||||
} exti_mode_enum;
|
} exti_mode_enum;
|
||||||
|
|
||||||
/* interrupt trigger mode */
|
/* interrupt trigger mode */
|
||||||
typedef enum
|
typedef enum {
|
||||||
{
|
|
||||||
EXTI_TRIG_RISING = 0, /*!< EXTI rising edge trigger */
|
EXTI_TRIG_RISING = 0, /*!< EXTI rising edge trigger */
|
||||||
EXTI_TRIG_FALLING, /*!< EXTI falling edge trigger */
|
EXTI_TRIG_FALLING, /*!< EXTI falling edge trigger */
|
||||||
EXTI_TRIG_BOTH, /*!< EXTI rising and falling edge trigger */
|
EXTI_TRIG_BOTH, /*!< EXTI rising and falling edge trigger */
|
||||||
|
|
@ -249,7 +246,7 @@ typedef enum
|
||||||
/* function declarations */
|
/* function declarations */
|
||||||
/* deinitialize the EXTI */
|
/* deinitialize the EXTI */
|
||||||
void exti_deinit(void);
|
void exti_deinit(void);
|
||||||
/* enable the configuration of EXTI initialize */
|
/* initialize the EXTI line x */
|
||||||
void exti_init(exti_line_enum linex, exti_mode_enum mode, exti_trig_type_enum trig_type);
|
void exti_init(exti_line_enum linex, exti_mode_enum mode, exti_trig_type_enum trig_type);
|
||||||
/* enable the interrupts from EXTI line x */
|
/* enable the interrupts from EXTI line x */
|
||||||
void exti_interrupt_enable(exti_line_enum linex);
|
void exti_interrupt_enable(exti_line_enum linex);
|
||||||
|
|
@ -259,19 +256,19 @@ void exti_interrupt_disable(exti_line_enum linex);
|
||||||
void exti_event_enable(exti_line_enum linex);
|
void exti_event_enable(exti_line_enum linex);
|
||||||
/* disable the events from EXTI line x */
|
/* disable the events from EXTI line x */
|
||||||
void exti_event_disable(exti_line_enum linex);
|
void exti_event_disable(exti_line_enum linex);
|
||||||
/* EXTI software interrupt event enable */
|
/* enable the software interrupt event from EXTI line x */
|
||||||
void exti_software_interrupt_enable(exti_line_enum linex);
|
void exti_software_interrupt_enable(exti_line_enum linex);
|
||||||
/* EXTI software interrupt event disable */
|
/* disable the software interrupt event from EXTI line x */
|
||||||
void exti_software_interrupt_disable(exti_line_enum linex);
|
void exti_software_interrupt_disable(exti_line_enum linex);
|
||||||
|
|
||||||
/* interrupt & flag functions */
|
/* interrupt & flag functions */
|
||||||
/* get EXTI lines pending flag */
|
/* get EXTI line x interrupt pending flag */
|
||||||
FlagStatus exti_flag_get(exti_line_enum linex);
|
FlagStatus exti_flag_get(exti_line_enum linex);
|
||||||
/* clear EXTI lines pending flag */
|
/* clear EXTI line x interrupt pending flag */
|
||||||
void exti_flag_clear(exti_line_enum linex);
|
void exti_flag_clear(exti_line_enum linex);
|
||||||
/* get EXTI lines flag when the interrupt flag is set */
|
/* get EXTI line x interrupt pending flag */
|
||||||
FlagStatus exti_interrupt_flag_get(exti_line_enum linex);
|
FlagStatus exti_interrupt_flag_get(exti_line_enum linex);
|
||||||
/* clear EXTI lines pending flag */
|
/* clear EXTI line x interrupt pending flag */
|
||||||
void exti_interrupt_flag_clear(exti_line_enum linex);
|
void exti_interrupt_flag_clear(exti_line_enum linex);
|
||||||
|
|
||||||
#endif /* GD32F4XX_EXTI_H */
|
#endif /* GD32F4XX_EXTI_H */
|
||||||
|
|
|
||||||
|
|
@ -5,10 +5,12 @@
|
||||||
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
||||||
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
||||||
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
||||||
|
\version 2020-12-20, V2.1.1, firmware for GD32F4xx
|
||||||
|
\version 2022-03-09, V3.0.0, firmware for GD32F4xx
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/*
|
/*
|
||||||
Copyright (c) 2020, GigaDevice Semiconductor Inc.
|
Copyright (c) 2022, GigaDevice Semiconductor Inc.
|
||||||
|
|
||||||
Redistribution and use in source and binary forms, with or without modification,
|
Redistribution and use in source and binary forms, with or without modification,
|
||||||
are permitted provided that the following conditions are met:
|
are permitted provided that the following conditions are met:
|
||||||
|
|
@ -45,15 +47,17 @@ OF SUCH DAMAGE.
|
||||||
#define OB OB_BASE /*!< option byte base address */
|
#define OB OB_BASE /*!< option byte base address */
|
||||||
|
|
||||||
/* registers definitions */
|
/* registers definitions */
|
||||||
#define FMC_WS REG32((FMC) + 0x0000U) /*!< FMC wait state register */
|
#define FMC_WS REG32((FMC) + 0x00000000U) /*!< FMC wait state register */
|
||||||
#define FMC_KEY REG32((FMC) + 0x0004U) /*!< FMC unlock key register */
|
#define FMC_KEY REG32((FMC) + 0x00000004U) /*!< FMC unlock key register */
|
||||||
#define FMC_OBKEY REG32((FMC) + 0x0008U) /*!< FMC option byte unlock key register */
|
#define FMC_OBKEY REG32((FMC) + 0x00000008U) /*!< FMC option byte unlock key register */
|
||||||
#define FMC_STAT REG32((FMC) + 0x000CU) /*!< FMC status register */
|
#define FMC_STAT REG32((FMC) + 0x0000000CU) /*!< FMC status register */
|
||||||
#define FMC_CTL REG32((FMC) + 0x0010U) /*!< FMC control register */
|
#define FMC_CTL REG32((FMC) + 0x00000010U) /*!< FMC control register */
|
||||||
#define FMC_OBCTL0 REG32((FMC) + 0x0014U) /*!< FMC option byte control register 0 */
|
#define FMC_OBCTL0 REG32((FMC) + 0x00000014U) /*!< FMC option byte control register 0 */
|
||||||
#define FMC_OBCTL1 REG32((FMC) + 0x0018U) /*!< FMC option byte control register 1 */
|
#define FMC_OBCTL1 REG32((FMC) + 0x00000018U) /*!< FMC option byte control register 1 */
|
||||||
#define FMC_WSEN REG32((FMC) + 0x00FCU) /*!< FMC wait state enable register */
|
#define FMC_PECFG REG32((FMC) + 0x00000020U) /*!< FMC page erase configuration register */
|
||||||
#define FMC_PID REG32((FMC) + 0x0100U) /*!< FMC product ID register */
|
#define FMC_PEKEY REG32((FMC) + 0x00000024U) /*!< FMC unlock page erase key register */
|
||||||
|
#define FMC_WSEN REG32((FMC) + 0x000000FCU) /*!< FMC wait state enable register */
|
||||||
|
#define FMC_PID REG32((FMC) + 0x00000100U) /*!< FMC product ID register */
|
||||||
|
|
||||||
#define OB_WP1 REG32((OB) + 0x00000008U) /*!< option byte write protection 1 */
|
#define OB_WP1 REG32((OB) + 0x00000008U) /*!< option byte write protection 1 */
|
||||||
#define OB_USER REG32((OB) + 0x00010000U) /*!< option byte user value*/
|
#define OB_USER REG32((OB) + 0x00010000U) /*!< option byte user value*/
|
||||||
|
|
@ -107,6 +111,13 @@ OF SUCH DAMAGE.
|
||||||
/* FMC_OBCTL1 */
|
/* FMC_OBCTL1 */
|
||||||
#define FMC_OBCTL1_WP1 BITS(16,27) /*!< erase/program protection of each sector when DRP is 0 */
|
#define FMC_OBCTL1_WP1 BITS(16,27) /*!< erase/program protection of each sector when DRP is 0 */
|
||||||
|
|
||||||
|
/* FMC_PECFG */
|
||||||
|
#define FMC_PE_EN BIT(31) /*!< the enable bit of page erase function */
|
||||||
|
#define FMC_PE_ADDR BITS(0,28) /*!< page erase address */
|
||||||
|
|
||||||
|
/* FMC_PEKEY */
|
||||||
|
#define FMC_PE_KEY BITS(0,31) /*!< FMC_PECFG unlock key value */
|
||||||
|
|
||||||
/* FMC_WSEN */
|
/* FMC_WSEN */
|
||||||
#define FMC_WSEN_WSEN BIT(0) /*!< FMC wait state enable bit */
|
#define FMC_WSEN_WSEN BIT(0) /*!< FMC wait state enable bit */
|
||||||
|
|
||||||
|
|
@ -115,21 +126,21 @@ OF SUCH DAMAGE.
|
||||||
|
|
||||||
/* constants definitions */
|
/* constants definitions */
|
||||||
/* fmc state */
|
/* fmc state */
|
||||||
typedef enum
|
typedef enum {
|
||||||
{
|
FMC_READY = 0, /*!< the operation has been completed */
|
||||||
FMC_READY, /*!< the operation has been completed */
|
|
||||||
FMC_BUSY, /*!< the operation is in progress */
|
FMC_BUSY, /*!< the operation is in progress */
|
||||||
FMC_RDDERR, /*!< read D-bus protection error */
|
FMC_RDDERR, /*!< read D-bus protection error */
|
||||||
FMC_PGSERR, /*!< program sequence error */
|
FMC_PGSERR, /*!< program sequence error */
|
||||||
FMC_PGMERR, /*!< program size not match error */
|
FMC_PGMERR, /*!< program size not match error */
|
||||||
FMC_WPERR, /*!< erase/program protection error */
|
FMC_WPERR, /*!< erase/program protection error */
|
||||||
FMC_OPERR, /*!< operation error */
|
FMC_OPERR, /*!< operation error */
|
||||||
FMC_PGERR, /*!< program error */
|
FMC_TOERR /*!< timeout error */
|
||||||
} fmc_state_enum;
|
} fmc_state_enum;
|
||||||
|
|
||||||
/* unlock key */
|
/* unlock key */
|
||||||
#define UNLOCK_KEY0 ((uint32_t)0x45670123U) /*!< unlock key 0 */
|
#define UNLOCK_KEY0 ((uint32_t)0x45670123U) /*!< unlock key 0 */
|
||||||
#define UNLOCK_KEY1 ((uint32_t)0xCDEF89ABU) /*!< unlock key 1 */
|
#define UNLOCK_KEY1 ((uint32_t)0xCDEF89ABU) /*!< unlock key 1 */
|
||||||
|
#define UNLOCK_PE_KEY ((uint32_t)0xA9B8C7D6U) /*!< unlock page erase function key */
|
||||||
|
|
||||||
#define OB_UNLOCK_KEY0 ((uint32_t)0x08192A3BU) /*!< ob unlock key 0 */
|
#define OB_UNLOCK_KEY0 ((uint32_t)0x08192A3BU) /*!< ob unlock key 0 */
|
||||||
#define OB_UNLOCK_KEY1 ((uint32_t)0x4C5D6E7FU) /*!< ob unlock key 1 */
|
#define OB_UNLOCK_KEY1 ((uint32_t)0x4C5D6E7FU) /*!< ob unlock key 1 */
|
||||||
|
|
@ -241,14 +252,15 @@ typedef enum
|
||||||
#define OB_DRP_21 ((uint32_t)0x02000000U) /*!< D-bus read protection protection of sector 21 */
|
#define OB_DRP_21 ((uint32_t)0x02000000U) /*!< D-bus read protection protection of sector 21 */
|
||||||
#define OB_DRP_22 ((uint32_t)0x04000000U) /*!< D-bus read protection protection of sector 22 */
|
#define OB_DRP_22 ((uint32_t)0x04000000U) /*!< D-bus read protection protection of sector 22 */
|
||||||
#define OB_DRP_23_27 ((uint32_t)0x08000000U) /*!< D-bus read protection protection of sector 23~27 */
|
#define OB_DRP_23_27 ((uint32_t)0x08000000U) /*!< D-bus read protection protection of sector 23~27 */
|
||||||
|
#define OB_DRP_ALL ((uint32_t)0x0FFF0FFFU) /*!< D-bus read protection protection of all sectors */
|
||||||
|
|
||||||
/* double banks or single bank selection when flash size is 1M bytes */
|
/* double banks or single bank selection when flash size is 1M bytes */
|
||||||
#define OBCTL0_DBS(regval) (BIT(30) & ((uint32_t)(regval)<<30))
|
#define OBCTL0_DBS(regval) (BIT(30) & ((uint32_t)(regval) << 30U))
|
||||||
#define OB_DBS_DISABLE OBCTL0_DBS(0) /*!< single bank when flash size is 1M bytes */
|
#define OB_DBS_DISABLE OBCTL0_DBS(0) /*!< single bank when flash size is 1M bytes */
|
||||||
#define OB_DBS_ENABLE OBCTL0_DBS(1) /*!< double bank when flash size is 1M bytes */
|
#define OB_DBS_ENABLE OBCTL0_DBS(1) /*!< double bank when flash size is 1M bytes */
|
||||||
|
|
||||||
/* option bytes D-bus read protection mode */
|
/* option bytes D-bus read protection mode */
|
||||||
#define OBCTL0_DRP(regval) (BIT(31) & ((uint32_t)(regval)<<31))
|
#define OBCTL0_DRP(regval) (BIT(31) & ((uint32_t)(regval) << 31U))
|
||||||
#define OB_DRP_DISABLE OBCTL0_DRP(0) /*!< the WPx bits used as erase/program protection of each sector */
|
#define OB_DRP_DISABLE OBCTL0_DRP(0) /*!< the WPx bits used as erase/program protection of each sector */
|
||||||
#define OB_DRP_ENABLE OBCTL0_DRP(1) /*!< the WPx bits used as erase/program protection and D-bus read protection of each sector */
|
#define OB_DRP_ENABLE OBCTL0_DRP(1) /*!< the WPx bits used as erase/program protection and D-bus read protection of each sector */
|
||||||
|
|
||||||
|
|
@ -285,7 +297,7 @@ typedef enum
|
||||||
|
|
||||||
|
|
||||||
/* FMC program size */
|
/* FMC program size */
|
||||||
#define CTL_PSZ(regval) (BITS(8,9) & ((uint32_t)(regval))<< 8)
|
#define CTL_PSZ(regval) (BITS(8,9) & ((uint32_t)(regval))<< 8U)
|
||||||
#define CTL_PSZ_BYTE CTL_PSZ(0) /*!< FMC program by byte access */
|
#define CTL_PSZ_BYTE CTL_PSZ(0) /*!< FMC program by byte access */
|
||||||
#define CTL_PSZ_HALF_WORD CTL_PSZ(1) /*!< FMC program by half-word access */
|
#define CTL_PSZ_HALF_WORD CTL_PSZ(1) /*!< FMC program by half-word access */
|
||||||
#define CTL_PSZ_WORD CTL_PSZ(2) /*!< FMC program by word access */
|
#define CTL_PSZ_WORD CTL_PSZ(2) /*!< FMC program by word access */
|
||||||
|
|
@ -295,13 +307,25 @@ typedef enum
|
||||||
#define FMC_INT_ERR ((uint32_t)0x02000000U) /*!< enable FMC error interrupt */
|
#define FMC_INT_ERR ((uint32_t)0x02000000U) /*!< enable FMC error interrupt */
|
||||||
|
|
||||||
/* FMC flags */
|
/* FMC flags */
|
||||||
#define FMC_FLAG_END ((uint32_t)0x00000001U) /*!< FMC end of operation flag bit */
|
#define FMC_FLAG_END FMC_STAT_END /*!< FMC end of operation flag bit */
|
||||||
#define FMC_FLAG_OPERR ((uint32_t)0x00000002U) /*!< FMC operation error flag bit */
|
#define FMC_FLAG_OPERR FMC_STAT_OPERR /*!< FMC operation error flag bit */
|
||||||
#define FMC_FLAG_WPERR ((uint32_t)0x00000010U) /*!< FMC erase/program protection error flag bit */
|
#define FMC_FLAG_WPERR FMC_STAT_WPERR /*!< FMC erase/program protection error flag bit */
|
||||||
#define FMC_FLAG_PGMERR ((uint32_t)0x00000040U) /*!< FMC program size not match error flag bit */
|
#define FMC_FLAG_PGMERR FMC_STAT_PGMERR /*!< FMC program size not match error flag bit */
|
||||||
#define FMC_FLAG_PGSERR ((uint32_t)0x00000080U) /*!< FMC program sequence error flag bit */
|
#define FMC_FLAG_PGSERR FMC_STAT_PGSERR /*!< FMC program sequence error flag bit */
|
||||||
#define FMC_FLAG_RDDERR ((uint32_t)0x00000100U) /*!< FMC read D-bus protection error flag bit */
|
#define FMC_FLAG_RDDERR FMC_STAT_RDDERR /*!< FMC read D-bus protection error flag bit */
|
||||||
#define FMC_FLAG_BUSY ((uint32_t)0x00010000U) /*!< FMC busy flag */
|
#define FMC_FLAG_BUSY FMC_STAT_BUSY /*!< FMC busy flag */
|
||||||
|
|
||||||
|
/* FMC interrupt flags */
|
||||||
|
#define FMC_INT_FLAG_END FMC_STAT_END /*!< FMC end of operation interrupt flag */
|
||||||
|
#define FMC_INT_FLAG_OPERR FMC_STAT_OPERR /*!< FMC operation error interrupt flag */
|
||||||
|
#define FMC_INT_FLAG_WPERR FMC_STAT_WPERR /*!< FMC erase/program protection error interrupt flag */
|
||||||
|
#define FMC_INT_FLAG_PGMERR FMC_STAT_PGMERR /*!< FMC program size not match error interrupt flag */
|
||||||
|
#define FMC_INT_FLAG_PGSERR FMC_STAT_PGSERR /*!< FMC program sequence error interrupt flag */
|
||||||
|
#define FMC_INT_FLAG_RDDERR FMC_STAT_RDDERR /*!< FMC read D-bus protection error interrupt flag */
|
||||||
|
|
||||||
|
|
||||||
|
/* FMC time out */
|
||||||
|
#define FMC_TIMEOUT_COUNT ((uint32_t)0x4FFFFFFFU) /*!< count to judge of FMC timeout */
|
||||||
|
|
||||||
/* function declarations */
|
/* function declarations */
|
||||||
/* FMC main memory programming functions */
|
/* FMC main memory programming functions */
|
||||||
|
|
@ -311,6 +335,10 @@ void fmc_wscnt_set(uint32_t wscnt);
|
||||||
void fmc_unlock(void);
|
void fmc_unlock(void);
|
||||||
/* lock the main FMC operation */
|
/* lock the main FMC operation */
|
||||||
void fmc_lock(void);
|
void fmc_lock(void);
|
||||||
|
#if defined (GD32F425) || defined (GD32F427) || defined (GD32F470)
|
||||||
|
/* FMC erase page */
|
||||||
|
fmc_state_enum fmc_page_erase(uint32_t page_addr);
|
||||||
|
#endif
|
||||||
/* FMC erase sector */
|
/* FMC erase sector */
|
||||||
fmc_state_enum fmc_sector_erase(uint32_t fmc_sector);
|
fmc_state_enum fmc_sector_erase(uint32_t fmc_sector);
|
||||||
/* FMC erase whole chip */
|
/* FMC erase whole chip */
|
||||||
|
|
@ -336,22 +364,22 @@ void ob_start(void);
|
||||||
/* erase option byte */
|
/* erase option byte */
|
||||||
void ob_erase(void);
|
void ob_erase(void);
|
||||||
/* enable write protect */
|
/* enable write protect */
|
||||||
void ob_write_protection_enable(uint32_t ob_wp);
|
ErrStatus ob_write_protection_enable(uint32_t ob_wp);
|
||||||
/* disable write protect */
|
/* disable write protect */
|
||||||
void ob_write_protection_disable(uint32_t ob_wp);
|
ErrStatus ob_write_protection_disable(uint32_t ob_wp);
|
||||||
/* enable erase/program protection and D-bus read protection */
|
/* enable erase/program protection and D-bus read protection */
|
||||||
void ob_drp_enable(uint32_t ob_drp);
|
void ob_drp_enable(uint32_t ob_drp);
|
||||||
/* disable erase/program protection and D-bus read protection */
|
/* disable erase/program protection and D-bus read protection */
|
||||||
void ob_drp_disable(uint32_t ob_drp);
|
void ob_drp_disable(void);
|
||||||
/* set the option byte security protection level */
|
/* configure security protection level */
|
||||||
void ob_security_protection_config(uint8_t ob_spc);
|
void ob_security_protection_config(uint8_t ob_spc);
|
||||||
/* write the FMC option byte user */
|
/* program the FMC user option byte */
|
||||||
void ob_user_write(uint32_t ob_fwdgt, uint32_t ob_deepsleep, uint32_t ob_stdby);
|
void ob_user_write(uint32_t ob_fwdgt, uint32_t ob_deepsleep, uint32_t ob_stdby);
|
||||||
/* option byte BOR threshold value */
|
/* program the option byte BOR threshold value */
|
||||||
void ob_user_bor_threshold(uint32_t ob_bor_th);
|
void ob_user_bor_threshold(uint32_t ob_bor_th);
|
||||||
/* configure the boot mode */
|
/* configure the boot mode */
|
||||||
void ob_boot_mode_config(uint32_t boot_mode);
|
void ob_boot_mode_config(uint32_t boot_mode);
|
||||||
/* get the FMC option byte user */
|
/* get the FMC user option byte */
|
||||||
uint8_t ob_user_get(void);
|
uint8_t ob_user_get(void);
|
||||||
/* get the FMC option byte write protection */
|
/* get the FMC option byte write protection */
|
||||||
uint16_t ob_write_protection0_get(void);
|
uint16_t ob_write_protection0_get(void);
|
||||||
|
|
@ -363,21 +391,25 @@ uint16_t ob_drp0_get(void);
|
||||||
uint16_t ob_drp1_get(void);
|
uint16_t ob_drp1_get(void);
|
||||||
/* get option byte security protection code value */
|
/* get option byte security protection code value */
|
||||||
FlagStatus ob_spc_get(void);
|
FlagStatus ob_spc_get(void);
|
||||||
/* get the FMC threshold value */
|
/* get the FMC option byte BOR threshold value */
|
||||||
uint8_t ob_user_bor_threshold_get(void);
|
uint8_t ob_user_bor_threshold_get(void);
|
||||||
|
|
||||||
/* FMC interrupts and flags management functions */
|
/* FMC interrupts and flags management functions */
|
||||||
/* enable FMC interrupt */
|
|
||||||
void fmc_interrupt_enable(uint32_t fmc_int);
|
|
||||||
/* disable FMC interrupt */
|
|
||||||
void fmc_interrupt_disable(uint32_t fmc_int);
|
|
||||||
/* get flag set or reset */
|
/* get flag set or reset */
|
||||||
FlagStatus fmc_flag_get(uint32_t fmc_flag);
|
FlagStatus fmc_flag_get(uint32_t fmc_flag);
|
||||||
/* clear the FMC pending flag */
|
/* clear the FMC pending flag */
|
||||||
void fmc_flag_clear(uint32_t fmc_flag);
|
void fmc_flag_clear(uint32_t fmc_flag);
|
||||||
/* return the FMC state */
|
/* enable FMC interrupt */
|
||||||
|
void fmc_interrupt_enable(uint32_t fmc_int);
|
||||||
|
/* disable FMC interrupt */
|
||||||
|
void fmc_interrupt_disable(uint32_t fmc_int);
|
||||||
|
/* get FMC interrupt flag set or reset */
|
||||||
|
FlagStatus fmc_interrupt_flag_get(uint32_t fmc_int_flag);
|
||||||
|
/* clear the FMC interrupt flag */
|
||||||
|
void fmc_interrupt_flag_clear(uint32_t fmc_int_flag);
|
||||||
|
/* get the FMC state */
|
||||||
fmc_state_enum fmc_state_get(void);
|
fmc_state_enum fmc_state_get(void);
|
||||||
/* check FMC ready or not */
|
/* check whether FMC is ready or not */
|
||||||
fmc_state_enum fmc_ready_wait(void);
|
fmc_state_enum fmc_ready_wait(uint32_t timeout);
|
||||||
|
|
||||||
#endif /* GD32F4XX_FMC_H */
|
#endif /* GD32F4XX_FMC_H */
|
||||||
|
|
|
||||||
|
|
@ -5,10 +5,11 @@
|
||||||
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
||||||
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
||||||
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
||||||
|
\version 2022-03-09, V3.0.0, firmware for GD32F4xx
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/*
|
/*
|
||||||
Copyright (c) 2020, GigaDevice Semiconductor Inc.
|
Copyright (c) 2022, GigaDevice Semiconductor Inc.
|
||||||
|
|
||||||
Redistribution and use in source and binary forms, with or without modification,
|
Redistribution and use in source and binary forms, with or without modification,
|
||||||
are permitted provided that the following conditions are met:
|
are permitted provided that the following conditions are met:
|
||||||
|
|
@ -40,7 +41,7 @@ OF SUCH DAMAGE.
|
||||||
#include "gd32f4xx.h"
|
#include "gd32f4xx.h"
|
||||||
|
|
||||||
/* FWDGT definitions */
|
/* FWDGT definitions */
|
||||||
#define FWDGT FWDGT_BASE
|
#define FWDGT FWDGT_BASE /*!< FWDGT base address */
|
||||||
|
|
||||||
/* registers definitions */
|
/* registers definitions */
|
||||||
#define FWDGT_CTL REG32((FWDGT) + 0x00U) /*!< FWDGT control register */
|
#define FWDGT_CTL REG32((FWDGT) + 0x00U) /*!< FWDGT control register */
|
||||||
|
|
@ -87,6 +88,9 @@ OF SUCH DAMAGE.
|
||||||
#define FWDGT_FLAG_PUD FWDGT_STAT_PUD /*!< FWDGT prescaler divider value update flag */
|
#define FWDGT_FLAG_PUD FWDGT_STAT_PUD /*!< FWDGT prescaler divider value update flag */
|
||||||
#define FWDGT_FLAG_RUD FWDGT_STAT_RUD /*!< FWDGT counter reload value update flag */
|
#define FWDGT_FLAG_RUD FWDGT_STAT_RUD /*!< FWDGT counter reload value update flag */
|
||||||
|
|
||||||
|
/* write value to FWDGT_RLD_RLD bit field */
|
||||||
|
#define RLD_RLD(regval) (BITS(0,11) & ((uint32_t)(regval) << 0))
|
||||||
|
|
||||||
/* function declarations */
|
/* function declarations */
|
||||||
/* enable write access to FWDGT_PSC and FWDGT_RLD */
|
/* enable write access to FWDGT_PSC and FWDGT_RLD */
|
||||||
void fwdgt_write_enable(void);
|
void fwdgt_write_enable(void);
|
||||||
|
|
@ -95,6 +99,10 @@ void fwdgt_write_disable(void);
|
||||||
/* start the free watchdog timer counter */
|
/* start the free watchdog timer counter */
|
||||||
void fwdgt_enable(void);
|
void fwdgt_enable(void);
|
||||||
|
|
||||||
|
/* configure the free watchdog timer counter prescaler value */
|
||||||
|
ErrStatus fwdgt_prescaler_value_config(uint16_t prescaler_value);
|
||||||
|
/* configure the free watchdog timer counter reload value */
|
||||||
|
ErrStatus fwdgt_reload_value_config(uint16_t reload_value);
|
||||||
/* reload the counter of FWDGT */
|
/* reload the counter of FWDGT */
|
||||||
void fwdgt_counter_reload(void);
|
void fwdgt_counter_reload(void);
|
||||||
/* configure counter reload value, and prescaler divider value */
|
/* configure counter reload value, and prescaler divider value */
|
||||||
|
|
|
||||||
|
|
@ -5,10 +5,11 @@
|
||||||
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
||||||
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
||||||
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
||||||
|
\version 2022-03-09, V3.0.0, firmware for GD32F4xx
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/*
|
/*
|
||||||
Copyright (c) 2020, GigaDevice Semiconductor Inc.
|
Copyright (c) 2022, GigaDevice Semiconductor Inc.
|
||||||
|
|
||||||
Redistribution and use in source and binary forms, with or without modification,
|
Redistribution and use in source and binary forms, with or without modification,
|
||||||
are permitted provided that the following conditions are met:
|
are permitted provided that the following conditions are met:
|
||||||
|
|
@ -57,7 +58,7 @@ OF SUCH DAMAGE.
|
||||||
#define GPIO_PUD(gpiox) REG32((gpiox) + 0x0CU) /*!< GPIO port pull-up/pull-down register */
|
#define GPIO_PUD(gpiox) REG32((gpiox) + 0x0CU) /*!< GPIO port pull-up/pull-down register */
|
||||||
#define GPIO_ISTAT(gpiox) REG32((gpiox) + 0x10U) /*!< GPIO port input status register */
|
#define GPIO_ISTAT(gpiox) REG32((gpiox) + 0x10U) /*!< GPIO port input status register */
|
||||||
#define GPIO_OCTL(gpiox) REG32((gpiox) + 0x14U) /*!< GPIO port output control register */
|
#define GPIO_OCTL(gpiox) REG32((gpiox) + 0x14U) /*!< GPIO port output control register */
|
||||||
#define GPIO_BOP(gpiox) REG32((gpiox) + 0x18U) /*!< GPIO port bit operation register */
|
#define GPIO_BOP(gpiox) REG32((gpiox) + 0x18U) /*!< GPIO port bit operate register */
|
||||||
#define GPIO_LOCK(gpiox) REG32((gpiox) + 0x1CU) /*!< GPIO port configuration lock register */
|
#define GPIO_LOCK(gpiox) REG32((gpiox) + 0x1CU) /*!< GPIO port configuration lock register */
|
||||||
#define GPIO_AFSEL0(gpiox) REG32((gpiox) + 0x20U) /*!< GPIO alternate function selected register 0 */
|
#define GPIO_AFSEL0(gpiox) REG32((gpiox) + 0x20U) /*!< GPIO alternate function selected register 0 */
|
||||||
#define GPIO_AFSEL1(gpiox) REG32((gpiox) + 0x24U) /*!< GPIO alternate function selected register 1 */
|
#define GPIO_AFSEL1(gpiox) REG32((gpiox) + 0x24U) /*!< GPIO alternate function selected register 1 */
|
||||||
|
|
@ -156,22 +157,22 @@ OF SUCH DAMAGE.
|
||||||
#define GPIO_ISTAT_ISTAT15 BIT(15) /*!< pin 15 input status */
|
#define GPIO_ISTAT_ISTAT15 BIT(15) /*!< pin 15 input status */
|
||||||
|
|
||||||
/* GPIO_OCTL */
|
/* GPIO_OCTL */
|
||||||
#define GPIO_OCTL_OCTL0 BIT(0) /*!< pin 0 output bit */
|
#define GPIO_OCTL_OCTL0 BIT(0) /*!< pin 0 output control bit */
|
||||||
#define GPIO_OCTL_OCTL1 BIT(1) /*!< pin 1 output bit */
|
#define GPIO_OCTL_OCTL1 BIT(1) /*!< pin 1 output control bit */
|
||||||
#define GPIO_OCTL_OCTL2 BIT(2) /*!< pin 2 output bit */
|
#define GPIO_OCTL_OCTL2 BIT(2) /*!< pin 2 output control bit */
|
||||||
#define GPIO_OCTL_OCTL3 BIT(3) /*!< pin 3 output bit */
|
#define GPIO_OCTL_OCTL3 BIT(3) /*!< pin 3 output control bit */
|
||||||
#define GPIO_OCTL_OCTL4 BIT(4) /*!< pin 4 output bit */
|
#define GPIO_OCTL_OCTL4 BIT(4) /*!< pin 4 output control bit */
|
||||||
#define GPIO_OCTL_OCTL5 BIT(5) /*!< pin 5 output bit */
|
#define GPIO_OCTL_OCTL5 BIT(5) /*!< pin 5 output control bit */
|
||||||
#define GPIO_OCTL_OCTL6 BIT(6) /*!< pin 6 output bit */
|
#define GPIO_OCTL_OCTL6 BIT(6) /*!< pin 6 output control bit */
|
||||||
#define GPIO_OCTL_OCTL7 BIT(7) /*!< pin 7 output bit */
|
#define GPIO_OCTL_OCTL7 BIT(7) /*!< pin 7 output control bit */
|
||||||
#define GPIO_OCTL_OCTL8 BIT(8) /*!< pin 8 output bit */
|
#define GPIO_OCTL_OCTL8 BIT(8) /*!< pin 8 output control bit */
|
||||||
#define GPIO_OCTL_OCTL9 BIT(9) /*!< pin 9 output bit */
|
#define GPIO_OCTL_OCTL9 BIT(9) /*!< pin 9 output control bit */
|
||||||
#define GPIO_OCTL_OCTL10 BIT(10) /*!< pin 10 output bit */
|
#define GPIO_OCTL_OCTL10 BIT(10) /*!< pin 10 output control bit */
|
||||||
#define GPIO_OCTL_OCTL11 BIT(11) /*!< pin 11 output bit */
|
#define GPIO_OCTL_OCTL11 BIT(11) /*!< pin 11 output control bit */
|
||||||
#define GPIO_OCTL_OCTL12 BIT(12) /*!< pin 12 output bit */
|
#define GPIO_OCTL_OCTL12 BIT(12) /*!< pin 12 output control bit */
|
||||||
#define GPIO_OCTL_OCTL13 BIT(13) /*!< pin 13 output bit */
|
#define GPIO_OCTL_OCTL13 BIT(13) /*!< pin 13 output control bit */
|
||||||
#define GPIO_OCTL_OCTL14 BIT(14) /*!< pin 14 output bit */
|
#define GPIO_OCTL_OCTL14 BIT(14) /*!< pin 14 output control bit */
|
||||||
#define GPIO_OCTL_OCTL15 BIT(15) /*!< pin 15 output bit */
|
#define GPIO_OCTL_OCTL15 BIT(15) /*!< pin 15 output control bit */
|
||||||
|
|
||||||
/* GPIO_BOP */
|
/* GPIO_BOP */
|
||||||
#define GPIO_BOP_BOP0 BIT(0) /*!< pin 0 set bit */
|
#define GPIO_BOP_BOP0 BIT(0) /*!< pin 0 set bit */
|
||||||
|
|
@ -224,7 +225,7 @@ OF SUCH DAMAGE.
|
||||||
#define GPIO_LOCK_LK13 BIT(13) /*!< pin 13 lock bit */
|
#define GPIO_LOCK_LK13 BIT(13) /*!< pin 13 lock bit */
|
||||||
#define GPIO_LOCK_LK14 BIT(14) /*!< pin 14 lock bit */
|
#define GPIO_LOCK_LK14 BIT(14) /*!< pin 14 lock bit */
|
||||||
#define GPIO_LOCK_LK15 BIT(15) /*!< pin 15 lock bit */
|
#define GPIO_LOCK_LK15 BIT(15) /*!< pin 15 lock bit */
|
||||||
#define GPIO_LOCK_LKK BIT(16) /*!< pin sequence lock key */
|
#define GPIO_LOCK_LKK BIT(16) /*!< pin lock sequence key */
|
||||||
|
|
||||||
/* GPIO_AFSEL0 */
|
/* GPIO_AFSEL0 */
|
||||||
#define GPIO_AFSEL0_SEL0 BITS(0,3) /*!< pin 0 alternate function selected */
|
#define GPIO_AFSEL0_SEL0 BITS(0,3) /*!< pin 0 alternate function selected */
|
||||||
|
|
@ -344,7 +345,7 @@ typedef FlagStatus bit_status;
|
||||||
#define GPIO_OSPEED_2MHZ GPIO_OSPEED_LEVEL0 /*!< output max speed 2MHz */
|
#define GPIO_OSPEED_2MHZ GPIO_OSPEED_LEVEL0 /*!< output max speed 2MHz */
|
||||||
#define GPIO_OSPEED_25MHZ GPIO_OSPEED_LEVEL1 /*!< output max speed 25MHz */
|
#define GPIO_OSPEED_25MHZ GPIO_OSPEED_LEVEL1 /*!< output max speed 25MHz */
|
||||||
#define GPIO_OSPEED_50MHZ GPIO_OSPEED_LEVEL2 /*!< output max speed 50MHz */
|
#define GPIO_OSPEED_50MHZ GPIO_OSPEED_LEVEL2 /*!< output max speed 50MHz */
|
||||||
#define GPIO_OSPEED_200MHZ GPIO_OSPEED_LEVEL3 /*!< output max speed 200MHz */
|
#define GPIO_OSPEED_MAX GPIO_OSPEED_LEVEL3 /*!< GPIO very high output speed, max speed more than 50MHz */
|
||||||
|
|
||||||
/* GPIO alternate function values */
|
/* GPIO alternate function values */
|
||||||
#define GPIO_AFR_SET(n, af) ((uint32_t)((uint32_t)(af) << (4U * (n))))
|
#define GPIO_AFR_SET(n, af) ((uint32_t)((uint32_t)(af) << (4U * (n))))
|
||||||
|
|
|
||||||
|
|
@ -6,10 +6,11 @@
|
||||||
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
||||||
\version 2019-04-16, V2.0.1, firmware for GD32F4xx
|
\version 2019-04-16, V2.0.1, firmware for GD32F4xx
|
||||||
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
||||||
|
\version 2022-03-09, V3.0.0, firmware for GD32F4xx
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/*
|
/*
|
||||||
Copyright (c) 2020, GigaDevice Semiconductor Inc.
|
Copyright (c) 2022, GigaDevice Semiconductor Inc.
|
||||||
|
|
||||||
Redistribution and use in source and binary forms, with or without modification,
|
Redistribution and use in source and binary forms, with or without modification,
|
||||||
are permitted provided that the following conditions are met:
|
are permitted provided that the following conditions are met:
|
||||||
|
|
@ -35,7 +36,6 @@ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSI
|
||||||
OF SUCH DAMAGE.
|
OF SUCH DAMAGE.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
|
|
||||||
#ifndef GD32F4XX_I2C_H
|
#ifndef GD32F4XX_I2C_H
|
||||||
#define GD32F4XX_I2C_H
|
#define GD32F4XX_I2C_H
|
||||||
|
|
||||||
|
|
@ -43,21 +43,21 @@ OF SUCH DAMAGE.
|
||||||
|
|
||||||
/* I2Cx(x=0,1,2) definitions */
|
/* I2Cx(x=0,1,2) definitions */
|
||||||
#define I2C0 I2C_BASE /*!< I2C0 base address */
|
#define I2C0 I2C_BASE /*!< I2C0 base address */
|
||||||
#define I2C1 (I2C_BASE+0x400U) /*!< I2C1 base address */
|
#define I2C1 (I2C_BASE + 0x00000400U) /*!< I2C1 base address */
|
||||||
#define I2C2 (I2C_BASE+0x800U) /*!< I2C2 base address */
|
#define I2C2 (I2C_BASE + 0x00000800U) /*!< I2C2 base address */
|
||||||
|
|
||||||
/* registers definitions */
|
/* registers definitions */
|
||||||
#define I2C_CTL0(i2cx) REG32((i2cx) + 0x00U) /*!< I2C control register 0 */
|
#define I2C_CTL0(i2cx) REG32((i2cx) + 0x00000000U) /*!< I2C control register 0 */
|
||||||
#define I2C_CTL1(i2cx) REG32((i2cx) + 0x04U) /*!< I2C control register 1 */
|
#define I2C_CTL1(i2cx) REG32((i2cx) + 0x00000004U) /*!< I2C control register 1 */
|
||||||
#define I2C_SADDR0(i2cx) REG32((i2cx) + 0x08U) /*!< I2C slave address register 0 */
|
#define I2C_SADDR0(i2cx) REG32((i2cx) + 0x00000008U) /*!< I2C slave address register 0 */
|
||||||
#define I2C_SADDR1(i2cx) REG32((i2cx) + 0x0CU) /*!< I2C slave address register 1 */
|
#define I2C_SADDR1(i2cx) REG32((i2cx) + 0x0000000CU) /*!< I2C slave address register 1 */
|
||||||
#define I2C_DATA(i2cx) REG32((i2cx) + 0x10U) /*!< I2C transfer buffer register */
|
#define I2C_DATA(i2cx) REG32((i2cx) + 0x00000010U) /*!< I2C transfer buffer register */
|
||||||
#define I2C_STAT0(i2cx) REG32((i2cx) + 0x14U) /*!< I2C transfer status register 0 */
|
#define I2C_STAT0(i2cx) REG32((i2cx) + 0x00000014U) /*!< I2C transfer status register 0 */
|
||||||
#define I2C_STAT1(i2cx) REG32((i2cx) + 0x18U) /*!< I2C transfer status register */
|
#define I2C_STAT1(i2cx) REG32((i2cx) + 0x00000018U) /*!< I2C transfer status register */
|
||||||
#define I2C_CKCFG(i2cx) REG32((i2cx) + 0x1CU) /*!< I2C clock configure register */
|
#define I2C_CKCFG(i2cx) REG32((i2cx) + 0x0000001CU) /*!< I2C clock configure register */
|
||||||
#define I2C_RT(i2cx) REG32((i2cx) + 0x20U) /*!< I2C rise time register */
|
#define I2C_RT(i2cx) REG32((i2cx) + 0x00000020U) /*!< I2C rise time register */
|
||||||
#define I2C_FCTL(i2cx) REG32((i2cx) + 0x24U) /*!< I2C filter control register */
|
#define I2C_FCTL(i2cx) REG32((i2cx) + 0x00000024U) /*!< I2C filter control register */
|
||||||
#define I2C_SAMCS(i2cx) REG32((i2cx) + 0x80U) /*!< I2C SAM control and status register */
|
#define I2C_SAMCS(i2cx) REG32((i2cx) + 0x00000080U) /*!< I2C SAM control and status register */
|
||||||
|
|
||||||
/* bits definitions */
|
/* bits definitions */
|
||||||
/* I2Cx_CTL0 */
|
/* I2Cx_CTL0 */
|
||||||
|
|
@ -144,16 +144,99 @@ OF SUCH DAMAGE.
|
||||||
#define I2C_SAMCS_RFRIE BIT(7) /*!< rxframe rise interrupt enable */
|
#define I2C_SAMCS_RFRIE BIT(7) /*!< rxframe rise interrupt enable */
|
||||||
#define I2C_SAMCS_TXF BIT(8) /*!< level of txframe signal */
|
#define I2C_SAMCS_TXF BIT(8) /*!< level of txframe signal */
|
||||||
#define I2C_SAMCS_RXF BIT(9) /*!< level of rxframe signal */
|
#define I2C_SAMCS_RXF BIT(9) /*!< level of rxframe signal */
|
||||||
#define I2C_SAMCS_TFF BIT(12) /*!< txframe fall flag, cleared by software write 0 */
|
#define I2C_SAMCS_TFF BIT(12) /*!< txframe fall flag */
|
||||||
#define I2C_SAMCS_TFR BIT(13) /*!< txframe rise flag, cleared by software write 0 */
|
#define I2C_SAMCS_TFR BIT(13) /*!< txframe rise flag */
|
||||||
#define I2C_SAMCS_RFF BIT(14) /*!< rxframe fall flag, cleared by software write 0 */
|
#define I2C_SAMCS_RFF BIT(14) /*!< rxframe fall flag */
|
||||||
#define I2C_SAMCS_RFR BIT(15) /*!< rxframe rise flag, cleared by software write 0 */
|
#define I2C_SAMCS_RFR BIT(15) /*!< rxframe rise flag */
|
||||||
|
|
||||||
/* constants definitions */
|
/* constants definitions */
|
||||||
|
/* define the I2C bit position and its register index offset */
|
||||||
|
#define I2C_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))
|
||||||
|
#define I2C_REG_VAL(i2cx, offset) (REG32((i2cx) + (((uint32_t)(offset) & 0x0000FFFFU) >> 6)))
|
||||||
|
#define I2C_BIT_POS(val) ((uint32_t)(val) & 0x0000001FU)
|
||||||
|
#define I2C_REGIDX_BIT2(regidx, bitpos, regidx2, bitpos2) (((uint32_t)(regidx2) << 22) | (uint32_t)((bitpos2) << 16)\
|
||||||
|
| (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)))
|
||||||
|
#define I2C_REG_VAL2(i2cx, offset) (REG32((i2cx) + ((uint32_t)(offset) >> 22)))
|
||||||
|
#define I2C_BIT_POS2(val) (((uint32_t)(val) & 0x001F0000U) >> 16)
|
||||||
|
|
||||||
|
/* register offset */
|
||||||
|
#define I2C_CTL1_REG_OFFSET ((uint32_t)0x00000004U) /*!< CTL1 register offset */
|
||||||
|
#define I2C_STAT0_REG_OFFSET ((uint32_t)0x00000014U) /*!< STAT0 register offset */
|
||||||
|
#define I2C_STAT1_REG_OFFSET ((uint32_t)0x00000018U) /*!< STAT1 register offset */
|
||||||
|
#define I2C_SAMCS_REG_OFFSET ((uint32_t)0x00000080U) /*!< SAMCS register offset */
|
||||||
|
|
||||||
|
/* I2C flags */
|
||||||
|
typedef enum {
|
||||||
|
/* flags in STAT0 register */
|
||||||
|
I2C_FLAG_SBSEND = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 0U), /*!< start condition sent out in master mode */
|
||||||
|
I2C_FLAG_ADDSEND = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 1U), /*!< address is sent in master mode or received and matches in slave mode */
|
||||||
|
I2C_FLAG_BTC = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 2U), /*!< byte transmission finishes */
|
||||||
|
I2C_FLAG_ADD10SEND = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 3U), /*!< header of 10-bit address is sent in master mode */
|
||||||
|
I2C_FLAG_STPDET = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 4U), /*!< stop condition detected in slave mode */
|
||||||
|
I2C_FLAG_RBNE = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 6U), /*!< I2C_DATA is not empty during receiving */
|
||||||
|
I2C_FLAG_TBE = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 7U), /*!< I2C_DATA is empty during transmitting */
|
||||||
|
I2C_FLAG_BERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 8U), /*!< a bus error occurs indication a unexpected start or stop condition on I2C bus */
|
||||||
|
I2C_FLAG_LOSTARB = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 9U), /*!< arbitration lost in master mode */
|
||||||
|
I2C_FLAG_AERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 10U), /*!< acknowledge error */
|
||||||
|
I2C_FLAG_OUERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 11U), /*!< over-run or under-run situation occurs in slave mode */
|
||||||
|
I2C_FLAG_PECERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 12U), /*!< PEC error when receiving data */
|
||||||
|
I2C_FLAG_SMBTO = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 14U), /*!< timeout signal in SMBus mode */
|
||||||
|
I2C_FLAG_SMBALT = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 15U), /*!< SMBus alert status */
|
||||||
|
/* flags in STAT1 register */
|
||||||
|
I2C_FLAG_MASTER = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 0U), /*!< a flag indicating whether I2C block is in master or slave mode */
|
||||||
|
I2C_FLAG_I2CBSY = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 1U), /*!< busy flag */
|
||||||
|
I2C_FLAG_TR = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 2U), /*!< whether the I2C is a transmitter or a receiver */
|
||||||
|
I2C_FLAG_RXGC = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 4U), /*!< general call address (00h) received */
|
||||||
|
I2C_FLAG_DEFSMB = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 5U), /*!< default address of SMBus device */
|
||||||
|
I2C_FLAG_HSTSMB = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 6U), /*!< SMBus host header detected in slave mode */
|
||||||
|
I2C_FLAG_DUMOD = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 7U), /*!< dual flag in slave mode indicating which address is matched in dual-address mode */
|
||||||
|
/* flags in SAMCS register */
|
||||||
|
I2C_FLAG_TFF = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 12U), /*!< txframe fall flag */
|
||||||
|
I2C_FLAG_TFR = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 13U), /*!< txframe rise flag */
|
||||||
|
I2C_FLAG_RFF = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 14U), /*!< rxframe fall flag */
|
||||||
|
I2C_FLAG_RFR = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 15U) /*!< rxframe rise flag */
|
||||||
|
} i2c_flag_enum;
|
||||||
|
|
||||||
|
/* I2C interrupt flags */
|
||||||
|
typedef enum {
|
||||||
|
/* interrupt flags in CTL1 register */
|
||||||
|
I2C_INT_FLAG_SBSEND = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 0U), /*!< start condition sent out in master mode interrupt flag */
|
||||||
|
I2C_INT_FLAG_ADDSEND = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 1U), /*!< address is sent in master mode or received and matches in slave mode interrupt flag */
|
||||||
|
I2C_INT_FLAG_BTC = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 2U), /*!< byte transmission finishes interrupt flag */
|
||||||
|
I2C_INT_FLAG_ADD10SEND = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 3U), /*!< header of 10-bit address is sent in master mode interrupt flag */
|
||||||
|
I2C_INT_FLAG_STPDET = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 4U), /*!< stop condition detected in slave mode interrupt flag */
|
||||||
|
I2C_INT_FLAG_RBNE = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 6U), /*!< I2C_DATA is not Empty during receiving interrupt flag */
|
||||||
|
I2C_INT_FLAG_TBE = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 7U), /*!< I2C_DATA is empty during transmitting interrupt flag */
|
||||||
|
I2C_INT_FLAG_BERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 8U), /*!< a bus error occurs indication a unexpected start or stop condition on I2C bus interrupt flag */
|
||||||
|
I2C_INT_FLAG_LOSTARB = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 9U), /*!< arbitration lost in master mode interrupt flag */
|
||||||
|
I2C_INT_FLAG_AERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 10U), /*!< acknowledge error interrupt flag */
|
||||||
|
I2C_INT_FLAG_OUERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 11U), /*!< over-run or under-run situation occurs in slave mode interrupt flag */
|
||||||
|
I2C_INT_FLAG_PECERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 12U), /*!< PEC error when receiving data interrupt flag */
|
||||||
|
I2C_INT_FLAG_SMBTO = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 14U), /*!< timeout signal in SMBus mode interrupt flag */
|
||||||
|
I2C_INT_FLAG_SMBALT = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 15U), /*!< SMBus alert status interrupt flag */
|
||||||
|
/* interrupt flags in SAMCS register */
|
||||||
|
I2C_INT_FLAG_TFF = I2C_REGIDX_BIT2(I2C_SAMCS_REG_OFFSET, 4U, I2C_SAMCS_REG_OFFSET, 12U), /*!< txframe fall interrupt flag */
|
||||||
|
I2C_INT_FLAG_TFR = I2C_REGIDX_BIT2(I2C_SAMCS_REG_OFFSET, 5U, I2C_SAMCS_REG_OFFSET, 13U), /*!< txframe rise interrupt flag */
|
||||||
|
I2C_INT_FLAG_RFF = I2C_REGIDX_BIT2(I2C_SAMCS_REG_OFFSET, 6U, I2C_SAMCS_REG_OFFSET, 14U), /*!< rxframe fall interrupt flag */
|
||||||
|
I2C_INT_FLAG_RFR = I2C_REGIDX_BIT2(I2C_SAMCS_REG_OFFSET, 7U, I2C_SAMCS_REG_OFFSET, 15U) /*!< rxframe rise interrupt flag */
|
||||||
|
} i2c_interrupt_flag_enum;
|
||||||
|
|
||||||
|
/* I2C interrupt */
|
||||||
|
typedef enum {
|
||||||
|
/* interrupt in CTL1 register */
|
||||||
|
I2C_INT_ERR = I2C_REGIDX_BIT(I2C_CTL1_REG_OFFSET, 8U), /*!< error interrupt */
|
||||||
|
I2C_INT_EV = I2C_REGIDX_BIT(I2C_CTL1_REG_OFFSET, 9U), /*!< event interrupt */
|
||||||
|
I2C_INT_BUF = I2C_REGIDX_BIT(I2C_CTL1_REG_OFFSET, 10U), /*!< buffer interrupt */
|
||||||
|
/* interrupt in SAMCS register */
|
||||||
|
I2C_INT_TFF = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 4U), /*!< txframe fall interrupt */
|
||||||
|
I2C_INT_TFR = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 5U), /*!< txframe rise interrupt */
|
||||||
|
I2C_INT_RFF = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 6U), /*!< rxframe fall interrupt */
|
||||||
|
I2C_INT_RFR = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 7U) /*!< rxframe rise interrupt */
|
||||||
|
} i2c_interrupt_enum;
|
||||||
|
|
||||||
/* the digital noise filter can filter spikes's length */
|
/* the digital noise filter can filter spikes's length */
|
||||||
typedef enum {
|
typedef enum {
|
||||||
I2C_DF_DISABLE, /*!< disable digital noise filter */
|
I2C_DF_DISABLE = 0, /*!< disable digital noise filter */
|
||||||
I2C_DF_1PCLK, /*!< enable digital noise filter and the maximum filtered spiker's length 1 PCLK1 */
|
I2C_DF_1PCLK, /*!< enable digital noise filter and the maximum filtered spiker's length 1 PCLK1 */
|
||||||
I2C_DF_2PCLKS, /*!< enable digital noise filter and the maximum filtered spiker's length 2 PCLK1 */
|
I2C_DF_2PCLKS, /*!< enable digital noise filter and the maximum filtered spiker's length 2 PCLK1 */
|
||||||
I2C_DF_3PCLKS, /*!< enable digital noise filter and the maximum filtered spiker's length 3 PCLK1 */
|
I2C_DF_3PCLKS, /*!< enable digital noise filter and the maximum filtered spiker's length 3 PCLK1 */
|
||||||
|
|
@ -171,94 +254,6 @@ typedef enum {
|
||||||
I2C_DF_15PCLKS /*!< enable digital noise filter and the maximum filtered spiker's length 15 PCLK1 */
|
I2C_DF_15PCLKS /*!< enable digital noise filter and the maximum filtered spiker's length 15 PCLK1 */
|
||||||
} i2c_digital_filter_enum;
|
} i2c_digital_filter_enum;
|
||||||
|
|
||||||
/* constants definitions */
|
|
||||||
/* define the I2C bit position and its register index offset */
|
|
||||||
#define I2C_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))
|
|
||||||
#define I2C_REG_VAL(i2cx, offset) (REG32((i2cx) + (((uint32_t)(offset) & 0xFFFFU) >> 6)))
|
|
||||||
#define I2C_BIT_POS(val) ((uint32_t)(val) & 0x1FU)
|
|
||||||
#define I2C_REGIDX_BIT2(regidx, bitpos, regidx2, bitpos2) (((uint32_t)(regidx2) << 22) | (uint32_t)((bitpos2) << 16)\
|
|
||||||
| (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)))
|
|
||||||
#define I2C_REG_VAL2(i2cx, offset) (REG32((i2cx) + ((uint32_t)(offset) >> 22)))
|
|
||||||
#define I2C_BIT_POS2(val) (((uint32_t)(val) & 0x1F0000U) >> 16)
|
|
||||||
|
|
||||||
/* register offset */
|
|
||||||
#define I2C_CTL1_REG_OFFSET 0x04U /*!< CTL1 register offset */
|
|
||||||
#define I2C_STAT0_REG_OFFSET 0x14U /*!< STAT0 register offset */
|
|
||||||
#define I2C_STAT1_REG_OFFSET 0x18U /*!< STAT1 register offset */
|
|
||||||
#define I2C_SAMCS_REG_OFFSET 0x80U /*!< SAMCS register offset */
|
|
||||||
|
|
||||||
/* I2C flags */
|
|
||||||
typedef enum
|
|
||||||
{
|
|
||||||
/* flags in STAT0 register */
|
|
||||||
I2C_FLAG_SBSEND = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 0U), /*!< start condition sent out in master mode */
|
|
||||||
I2C_FLAG_ADDSEND = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 1U), /*!< address is sent in master mode or received and matches in slave mode */
|
|
||||||
I2C_FLAG_BTC = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 2U), /*!< byte transmission finishes */
|
|
||||||
I2C_FLAG_ADD10SEND = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 3U), /*!< header of 10-bit address is sent in master mode */
|
|
||||||
I2C_FLAG_STPDET = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 4U), /*!< stop condition detected in slave mode */
|
|
||||||
I2C_FLAG_RBNE = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 6U), /*!< I2C_DATA is not Empty during receiving */
|
|
||||||
I2C_FLAG_TBE = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 7U), /*!< I2C_DATA is empty during transmitting */
|
|
||||||
I2C_FLAG_BERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 8U), /*!< a bus error occurs indication a unexpected start or stop condition on I2C bus */
|
|
||||||
I2C_FLAG_LOSTARB = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 9U), /*!< arbitration lost in master mode */
|
|
||||||
I2C_FLAG_AERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 10U), /*!< acknowledge error */
|
|
||||||
I2C_FLAG_OUERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 11U), /*!< over-run or under-run situation occurs in slave mode */
|
|
||||||
I2C_FLAG_PECERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 12U), /*!< PEC error when receiving data */
|
|
||||||
I2C_FLAG_SMBTO = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 14U), /*!< timeout signal in SMBus mode */
|
|
||||||
I2C_FLAG_SMBALT = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 15U), /*!< SMBus alert status */
|
|
||||||
/* flags in STAT1 register */
|
|
||||||
I2C_FLAG_MASTER = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 0U), /*!< a flag indicating whether I2C block is in master or slave mode */
|
|
||||||
I2C_FLAG_I2CBSY = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 1U), /*!< busy flag */
|
|
||||||
I2C_FLAG_TRS = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 2U), /*!< whether the I2C is a transmitter or a receiver */
|
|
||||||
I2C_FLAG_RXGC = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 4U), /*!< general call address (00h) received */
|
|
||||||
I2C_FLAG_DEFSMB = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 5U), /*!< default address of SMBus device */
|
|
||||||
I2C_FLAG_HSTSMB = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 6U), /*!< SMBus host header detected in slave mode */
|
|
||||||
I2C_FLAG_DUMOD = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 7U), /*!< dual flag in slave mode indicating which address is matched in dual-address mode */
|
|
||||||
/* flags in SAMCS register */
|
|
||||||
I2C_FLAG_TFF = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 12U), /*!< txframe fall flag */
|
|
||||||
I2C_FLAG_TFR = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 13U), /*!< txframe rise flag */
|
|
||||||
I2C_FLAG_RFF = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 14U), /*!< rxframe fall flag */
|
|
||||||
I2C_FLAG_RFR = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 15U) /*!< rxframe rise flag */
|
|
||||||
}i2c_flag_enum;
|
|
||||||
|
|
||||||
/* I2C interrupt flags */
|
|
||||||
typedef enum
|
|
||||||
{
|
|
||||||
/* interrupt flags in CTL1 register */
|
|
||||||
I2C_INT_FLAG_SBSEND = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 0U), /*!< start condition sent out in master mode interrupt flag */
|
|
||||||
I2C_INT_FLAG_ADDSEND = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 1U), /*!< address is sent in master mode or received and matches in slave mode interrupt flag */
|
|
||||||
I2C_INT_FLAG_BTC = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 2U), /*!< byte transmission finishes */
|
|
||||||
I2C_INT_FLAG_ADD10SEND = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 3U), /*!< header of 10-bit address is sent in master mode interrupt flag */
|
|
||||||
I2C_INT_FLAG_STPDET = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 4U), /*!< stop condition detected in slave mode interrupt flag */
|
|
||||||
I2C_INT_FLAG_RBNE = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 6U), /*!< I2C_DATA is not Empty during receiving interrupt flag */
|
|
||||||
I2C_INT_FLAG_TBE = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 7U), /*!< I2C_DATA is empty during transmitting interrupt flag */
|
|
||||||
I2C_INT_FLAG_BERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 8U), /*!< a bus error occurs indication a unexpected start or stop condition on I2C bus interrupt flag */
|
|
||||||
I2C_INT_FLAG_LOSTARB = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 9U), /*!< arbitration lost in master mode interrupt flag */
|
|
||||||
I2C_INT_FLAG_AERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 10U), /*!< acknowledge error interrupt flag */
|
|
||||||
I2C_INT_FLAG_OUERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 11U), /*!< over-run or under-run situation occurs in slave mode interrupt flag */
|
|
||||||
I2C_INT_FLAG_PECERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 12U), /*!< PEC error when receiving data interrupt flag */
|
|
||||||
I2C_INT_FLAG_SMBTO = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 14U), /*!< timeout signal in SMBus mode interrupt flag */
|
|
||||||
I2C_INT_FLAG_SMBALT = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 15U), /*!< SMBus Alert status interrupt flag */
|
|
||||||
/* interrupt flags in SAMCS register */
|
|
||||||
I2C_INT_FLAG_TFF = I2C_REGIDX_BIT2(I2C_SAMCS_REG_OFFSET, 4U, I2C_SAMCS_REG_OFFSET, 12U), /*!< txframe fall interrupt flag */
|
|
||||||
I2C_INT_FLAG_TFR = I2C_REGIDX_BIT2(I2C_SAMCS_REG_OFFSET, 5U, I2C_SAMCS_REG_OFFSET, 13U), /*!< txframe rise interrupt flag */
|
|
||||||
I2C_INT_FLAG_RFF = I2C_REGIDX_BIT2(I2C_SAMCS_REG_OFFSET, 6U, I2C_SAMCS_REG_OFFSET, 14U), /*!< rxframe fall interrupt flag */
|
|
||||||
I2C_INT_FLAG_RFR = I2C_REGIDX_BIT2(I2C_SAMCS_REG_OFFSET, 7U, I2C_SAMCS_REG_OFFSET, 15U) /*!< rxframe rise interrupt flag */
|
|
||||||
}i2c_interrupt_flag_enum;
|
|
||||||
|
|
||||||
/* I2C interrupt enable or disable */
|
|
||||||
typedef enum
|
|
||||||
{
|
|
||||||
/* interrupt in CTL1 register */
|
|
||||||
I2C_INT_ERR = I2C_REGIDX_BIT(I2C_CTL1_REG_OFFSET, 8U), /*!< error interrupt enable */
|
|
||||||
I2C_INT_EV = I2C_REGIDX_BIT(I2C_CTL1_REG_OFFSET, 9U), /*!< event interrupt enable */
|
|
||||||
I2C_INT_BUF = I2C_REGIDX_BIT(I2C_CTL1_REG_OFFSET, 10U), /*!< buffer interrupt enable */
|
|
||||||
/* interrupt in SAMCS register */
|
|
||||||
I2C_INT_TFF = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 4U), /*!< txframe fall interrupt enable */
|
|
||||||
I2C_INT_TFR = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 5U), /*!< txframe rise interrupt enable */
|
|
||||||
I2C_INT_RFF = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 6U), /*!< rxframe fall interrupt enable */
|
|
||||||
I2C_INT_RFR = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 7U) /*!< rxframe rise interrupt enable */
|
|
||||||
}i2c_interrupt_enum;
|
|
||||||
|
|
||||||
/* SMBus/I2C mode switch and SMBus type selection */
|
/* SMBus/I2C mode switch and SMBus type selection */
|
||||||
#define I2C_I2CMODE_ENABLE ((uint32_t)0x00000000U) /*!< I2C mode */
|
#define I2C_I2CMODE_ENABLE ((uint32_t)0x00000000U) /*!< I2C mode */
|
||||||
#define I2C_SMBUSMODE_ENABLE I2C_CTL0_SMBEN /*!< SMBus mode */
|
#define I2C_SMBUSMODE_ENABLE I2C_CTL0_SMBEN /*!< SMBus mode */
|
||||||
|
|
@ -273,54 +268,50 @@ typedef enum
|
||||||
|
|
||||||
/* whether or not to send an ACK */
|
/* whether or not to send an ACK */
|
||||||
#define I2C_ACK_DISABLE ((uint32_t)0x00000000U) /*!< ACK will be not sent */
|
#define I2C_ACK_DISABLE ((uint32_t)0x00000000U) /*!< ACK will be not sent */
|
||||||
#define I2C_ACK_ENABLE ((uint32_t)0x00000001U) /*!< ACK will be sent */
|
#define I2C_ACK_ENABLE I2C_CTL0_ACKEN /*!< ACK will be sent */
|
||||||
|
|
||||||
/* I2C POAP position*/
|
/* I2C POAP position*/
|
||||||
#define I2C_ACKPOS_NEXT ((uint32_t)0x00000000U) /*!< ACKEN bit decides whether or not to send ACK for the next byte */
|
#define I2C_ACKPOS_CURRENT ((uint32_t)0x00000000U) /*!< ACKEN bit decides whether or not to send ACK or not for the current byte */
|
||||||
#define I2C_ACKPOS_CURRENT ((uint32_t)0x00000001U) /*!< ACKEN bit decides whether or not to send ACK or not for the current byte */
|
#define I2C_ACKPOS_NEXT I2C_CTL0_POAP /*!< ACKEN bit decides whether or not to send ACK for the next byte */
|
||||||
|
|
||||||
/* I2C dual-address mode switch */
|
|
||||||
#define I2C_DUADEN_DISABLE ((uint32_t)0x00000000U) /*!< dual-address mode disabled */
|
|
||||||
#define I2C_DUADEN_ENABLE ((uint32_t)0x00000001U) /*!< dual-address mode enabled */
|
|
||||||
|
|
||||||
/* whether or not to stretch SCL low */
|
/* whether or not to stretch SCL low */
|
||||||
#define I2C_SCLSTRETCH_ENABLE ((uint32_t)0x00000000U) /*!< SCL stretching is enabled */
|
#define I2C_SCLSTRETCH_ENABLE ((uint32_t)0x00000000U) /*!< enable SCL stretching */
|
||||||
#define I2C_SCLSTRETCH_DISABLE I2C_CTL0_SS /*!< SCL stretching is disabled */
|
#define I2C_SCLSTRETCH_DISABLE I2C_CTL0_SS /*!< disable SCL stretching */
|
||||||
|
|
||||||
/* whether or not to response to a general call */
|
/* whether or not to response to a general call */
|
||||||
#define I2C_GCEN_ENABLE I2C_CTL0_GCEN /*!< slave will response to a general call */
|
#define I2C_GCEN_ENABLE I2C_CTL0_GCEN /*!< slave will response to a general call */
|
||||||
#define I2C_GCEN_DISABLE ((uint32_t)0x00000000U) /*!< slave will not response to a general call */
|
#define I2C_GCEN_DISABLE ((uint32_t)0x00000000U) /*!< slave will not response to a general call */
|
||||||
|
|
||||||
/* software reset I2C */
|
/* software reset I2C */
|
||||||
#define I2C_SRESET_SET I2C_CTL0_SRESET /*!< I2C is under reset */
|
|
||||||
#define I2C_SRESET_RESET ((uint32_t)0x00000000U) /*!< I2C is not under reset */
|
#define I2C_SRESET_RESET ((uint32_t)0x00000000U) /*!< I2C is not under reset */
|
||||||
|
#define I2C_SRESET_SET I2C_CTL0_SRESET /*!< I2C is under reset */
|
||||||
|
|
||||||
/* I2C DMA mode configure */
|
/* I2C DMA mode configure */
|
||||||
/* DMA mode switch */
|
/* DMA mode switch */
|
||||||
#define I2C_DMA_ON I2C_CTL1_DMAON /*!< DMA mode enabled */
|
#define I2C_DMA_OFF ((uint32_t)0x00000000U) /*!< disable DMA mode */
|
||||||
#define I2C_DMA_OFF ((uint32_t)0x00000000U) /*!< DMA mode disabled */
|
#define I2C_DMA_ON I2C_CTL1_DMAON /*!< enable DMA mode */
|
||||||
|
|
||||||
/* flag indicating DMA last transfer */
|
/* flag indicating DMA last transfer */
|
||||||
#define I2C_DMALST_ON I2C_CTL1_DMALST /*!< next DMA EOT is the last transfer */
|
|
||||||
#define I2C_DMALST_OFF ((uint32_t)0x00000000U) /*!< next DMA EOT is not the last transfer */
|
#define I2C_DMALST_OFF ((uint32_t)0x00000000U) /*!< next DMA EOT is not the last transfer */
|
||||||
|
#define I2C_DMALST_ON I2C_CTL1_DMALST /*!< next DMA EOT is the last transfer */
|
||||||
|
|
||||||
/* I2C PEC configure */
|
/* I2C PEC configure */
|
||||||
/* PEC enable */
|
/* PEC enable */
|
||||||
#define I2C_PEC_ENABLE I2C_CTL0_PECEN /*!< PEC calculation on */
|
|
||||||
#define I2C_PEC_DISABLE ((uint32_t)0x00000000U) /*!< PEC calculation off */
|
#define I2C_PEC_DISABLE ((uint32_t)0x00000000U) /*!< PEC calculation off */
|
||||||
|
#define I2C_PEC_ENABLE I2C_CTL0_PECEN /*!< PEC calculation on */
|
||||||
|
|
||||||
/* PEC transfer */
|
/* PEC transfer */
|
||||||
#define I2C_PECTRANS_ENABLE I2C_CTL0_PECTRANS /*!< transfer PEC */
|
|
||||||
#define I2C_PECTRANS_DISABLE ((uint32_t)0x00000000U) /*!< not transfer PEC value */
|
#define I2C_PECTRANS_DISABLE ((uint32_t)0x00000000U) /*!< not transfer PEC value */
|
||||||
|
#define I2C_PECTRANS_ENABLE I2C_CTL0_PECTRANS /*!< transfer PEC value */
|
||||||
|
|
||||||
/* I2C SMBus configure */
|
/* I2C SMBus configure */
|
||||||
/* issue or not alert through SMBA pin */
|
/* issue or not alert through SMBA pin */
|
||||||
#define I2C_SALTSEND_ENABLE I2C_CTL0_SALT /*!< issue alert through SMBA pin */
|
|
||||||
#define I2C_SALTSEND_DISABLE ((uint32_t)0x00000000U) /*!< not issue alert through SMBA */
|
#define I2C_SALTSEND_DISABLE ((uint32_t)0x00000000U) /*!< not issue alert through SMBA */
|
||||||
|
#define I2C_SALTSEND_ENABLE I2C_CTL0_SALT /*!< issue alert through SMBA pin */
|
||||||
|
|
||||||
/* ARP protocol in SMBus switch */
|
/* ARP protocol in SMBus switch */
|
||||||
#define I2C_ARP_ENABLE I2C_CTL0_ARPEN /*!< ARP is enabled */
|
#define I2C_ARP_DISABLE ((uint32_t)0x00000000U) /*!< disable ARP */
|
||||||
#define I2C_ARP_DISABLE ((uint32_t)0x00000000U) /*!< ARP is disabled */
|
#define I2C_ARP_ENABLE I2C_CTL0_ARPEN /*!< enable ARP */
|
||||||
|
|
||||||
/* transmit I2C data */
|
/* transmit I2C data */
|
||||||
#define DATA_TRANS(regval) (BITS(0,7) & ((uint32_t)(regval) << 0))
|
#define DATA_TRANS(regval) (BITS(0,7) & ((uint32_t)(regval) << 0))
|
||||||
|
|
@ -329,21 +320,24 @@ typedef enum
|
||||||
#define DATA_RECV(regval) GET_BITS((uint32_t)(regval), 0, 7)
|
#define DATA_RECV(regval) GET_BITS((uint32_t)(regval), 0, 7)
|
||||||
|
|
||||||
/* I2C duty cycle in fast mode */
|
/* I2C duty cycle in fast mode */
|
||||||
#define I2C_DTCY_2 ((uint32_t)0x00000000U) /*!< I2C fast mode Tlow/Thigh = 2 */
|
#define I2C_DTCY_2 ((uint32_t)0x00000000U) /*!< T_low/T_high = 2 in fast mode */
|
||||||
#define I2C_DTCY_16_9 I2C_CKCFG_DTCY /*!< I2C fast mode Tlow/Thigh = 16/9 */
|
#define I2C_DTCY_16_9 I2C_CKCFG_DTCY /*!< T_low/T_high = 16/9 in fast mode */
|
||||||
|
|
||||||
/* address mode for the I2C slave */
|
/* address mode for the I2C slave */
|
||||||
#define I2C_ADDFORMAT_7BITS ((uint32_t)0x00000000U) /*!< address:7 bits */
|
#define I2C_ADDFORMAT_7BITS ((uint32_t)0x00000000U) /*!< address format is 7 bits */
|
||||||
#define I2C_ADDFORMAT_10BITS I2C_SADDR0_ADDFORMAT /*!< address:10 bits */
|
#define I2C_ADDFORMAT_10BITS I2C_SADDR0_ADDFORMAT /*!< address format is 10 bits */
|
||||||
|
|
||||||
/* function declarations */
|
/* function declarations */
|
||||||
|
/* initialization functions */
|
||||||
/* reset I2C */
|
/* reset I2C */
|
||||||
void i2c_deinit(uint32_t i2c_periph);
|
void i2c_deinit(uint32_t i2c_periph);
|
||||||
/* configure I2C clock */
|
/* configure I2C clock */
|
||||||
void i2c_clock_config(uint32_t i2c_periph, uint32_t clkspeed, uint32_t dutycyc);
|
void i2c_clock_config(uint32_t i2c_periph, uint32_t clkspeed, uint32_t dutycyc);
|
||||||
/* configure I2C address */
|
/* configure I2C address */
|
||||||
void i2c_mode_addr_config(uint32_t i2c_periph, uint32_t mode, uint32_t addformat, uint32_t addr);
|
void i2c_mode_addr_config(uint32_t i2c_periph, uint32_t mode, uint32_t addformat, uint32_t addr);
|
||||||
/* SMBus type selection */
|
|
||||||
|
/* application function declarations */
|
||||||
|
/* select SMBus type */
|
||||||
void i2c_smbus_type_config(uint32_t i2c_periph, uint32_t type);
|
void i2c_smbus_type_config(uint32_t i2c_periph, uint32_t type);
|
||||||
/* whether or not to send an ACK */
|
/* whether or not to send an ACK */
|
||||||
void i2c_ack_config(uint32_t i2c_periph, uint32_t ack);
|
void i2c_ack_config(uint32_t i2c_periph, uint32_t ack);
|
||||||
|
|
@ -359,7 +353,6 @@ void i2c_dualaddr_disable(uint32_t i2c_periph);
|
||||||
void i2c_enable(uint32_t i2c_periph);
|
void i2c_enable(uint32_t i2c_periph);
|
||||||
/* disable I2C */
|
/* disable I2C */
|
||||||
void i2c_disable(uint32_t i2c_periph);
|
void i2c_disable(uint32_t i2c_periph);
|
||||||
|
|
||||||
/* generate a START condition on I2C bus */
|
/* generate a START condition on I2C bus */
|
||||||
void i2c_start_on_bus(uint32_t i2c_periph);
|
void i2c_start_on_bus(uint32_t i2c_periph);
|
||||||
/* generate a STOP condition on I2C bus */
|
/* generate a STOP condition on I2C bus */
|
||||||
|
|
@ -368,35 +361,32 @@ void i2c_stop_on_bus(uint32_t i2c_periph);
|
||||||
void i2c_data_transmit(uint32_t i2c_periph, uint8_t data);
|
void i2c_data_transmit(uint32_t i2c_periph, uint8_t data);
|
||||||
/* I2C receive data function */
|
/* I2C receive data function */
|
||||||
uint8_t i2c_data_receive(uint32_t i2c_periph);
|
uint8_t i2c_data_receive(uint32_t i2c_periph);
|
||||||
/* enable I2C DMA mode */
|
/* configure I2C DMA mode */
|
||||||
void i2c_dma_enable(uint32_t i2c_periph, uint32_t dmastate);
|
void i2c_dma_config(uint32_t i2c_periph, uint32_t dmastate);
|
||||||
/* configure whether next DMA EOT is DMA last transfer or not */
|
/* configure whether next DMA EOT is DMA last transfer or not */
|
||||||
void i2c_dma_last_transfer_config(uint32_t i2c_periph, uint32_t dmalast);
|
void i2c_dma_last_transfer_config(uint32_t i2c_periph, uint32_t dmalast);
|
||||||
/* whether to stretch SCL low when data is not ready in slave mode */
|
/* whether to stretch SCL low when data is not ready in slave mode */
|
||||||
void i2c_stretch_scl_low_config(uint32_t i2c_periph, uint32_t stretchpara);
|
void i2c_stretch_scl_low_config(uint32_t i2c_periph, uint32_t stretchpara);
|
||||||
/* whether or not to response to a general call */
|
/* whether or not to response to a general call */
|
||||||
void i2c_slave_response_to_gcall_config(uint32_t i2c_periph, uint32_t gcallpara);
|
void i2c_slave_response_to_gcall_config(uint32_t i2c_periph, uint32_t gcallpara);
|
||||||
/* software reset I2C */
|
/* configure software reset of I2C */
|
||||||
void i2c_software_reset_config(uint32_t i2c_periph, uint32_t sreset);
|
void i2c_software_reset_config(uint32_t i2c_periph, uint32_t sreset);
|
||||||
|
/* configure I2C PEC calculation */
|
||||||
/* I2C PEC calculation on or off */
|
void i2c_pec_config(uint32_t i2c_periph, uint32_t pecstate);
|
||||||
void i2c_pec_enable(uint32_t i2c_periph, uint32_t pecstate);
|
/* configure whether to transfer PEC value */
|
||||||
/* I2C whether to transfer PEC value */
|
void i2c_pec_transfer_config(uint32_t i2c_periph, uint32_t pecpara);
|
||||||
void i2c_pec_transfer_enable(uint32_t i2c_periph, uint32_t pecpara);
|
/* get packet error checking value */
|
||||||
/* packet error checking value */
|
|
||||||
uint8_t i2c_pec_value_get(uint32_t i2c_periph);
|
uint8_t i2c_pec_value_get(uint32_t i2c_periph);
|
||||||
/* I2C issue alert through SMBA pin */
|
/* configure I2C alert through SMBA pin */
|
||||||
void i2c_smbus_issue_alert(uint32_t i2c_periph, uint32_t smbuspara);
|
void i2c_smbus_alert_config(uint32_t i2c_periph, uint32_t smbuspara);
|
||||||
/* I2C ARP protocol in SMBus switch */
|
/* configure I2C ARP protocol in SMBus */
|
||||||
void i2c_smbus_arp_enable(uint32_t i2c_periph, uint32_t arpstate);
|
void i2c_smbus_arp_config(uint32_t i2c_periph, uint32_t arpstate);
|
||||||
|
/* disable analog noise filter */
|
||||||
/* I2C analog noise filter disable */
|
|
||||||
void i2c_analog_noise_filter_disable(uint32_t i2c_periph);
|
void i2c_analog_noise_filter_disable(uint32_t i2c_periph);
|
||||||
/* I2C analog noise filter enable */
|
/* enable analog noise filter */
|
||||||
void i2c_analog_noise_filter_enable(uint32_t i2c_periph);
|
void i2c_analog_noise_filter_enable(uint32_t i2c_periph);
|
||||||
/* digital noise filter */
|
/* configure digital noise filter */
|
||||||
void i2c_digital_noise_filter_config(uint32_t i2c_periph, i2c_digital_filter_enum dfilterpara);
|
void i2c_digital_noise_filter_config(uint32_t i2c_periph, i2c_digital_filter_enum dfilterpara);
|
||||||
|
|
||||||
/* enable SAM_V interface */
|
/* enable SAM_V interface */
|
||||||
void i2c_sam_enable(uint32_t i2c_periph);
|
void i2c_sam_enable(uint32_t i2c_periph);
|
||||||
/* disable SAM_V interface */
|
/* disable SAM_V interface */
|
||||||
|
|
@ -406,17 +396,18 @@ void i2c_sam_timeout_enable(uint32_t i2c_periph);
|
||||||
/* disable SAM_V interface timeout detect */
|
/* disable SAM_V interface timeout detect */
|
||||||
void i2c_sam_timeout_disable(uint32_t i2c_periph);
|
void i2c_sam_timeout_disable(uint32_t i2c_periph);
|
||||||
|
|
||||||
/* check I2C flag is set or not */
|
/* interrupt & flag functions */
|
||||||
|
/* get I2C flag status */
|
||||||
FlagStatus i2c_flag_get(uint32_t i2c_periph, i2c_flag_enum flag);
|
FlagStatus i2c_flag_get(uint32_t i2c_periph, i2c_flag_enum flag);
|
||||||
/* clear I2C flag */
|
/* clear I2C flag status */
|
||||||
void i2c_flag_clear(uint32_t i2c_periph, i2c_flag_enum flag);
|
void i2c_flag_clear(uint32_t i2c_periph, i2c_flag_enum flag);
|
||||||
/* enable I2C interrupt */
|
/* enable I2C interrupt */
|
||||||
void i2c_interrupt_enable(uint32_t i2c_periph, i2c_interrupt_enum interrupt);
|
void i2c_interrupt_enable(uint32_t i2c_periph, i2c_interrupt_enum interrupt);
|
||||||
/* disable I2C interrupt */
|
/* disable I2C interrupt */
|
||||||
void i2c_interrupt_disable(uint32_t i2c_periph, i2c_interrupt_enum interrupt);
|
void i2c_interrupt_disable(uint32_t i2c_periph, i2c_interrupt_enum interrupt);
|
||||||
/* check I2C interrupt flag */
|
/* get I2C interrupt flag status */
|
||||||
FlagStatus i2c_interrupt_flag_get(uint32_t i2c_periph, i2c_interrupt_flag_enum int_flag);
|
FlagStatus i2c_interrupt_flag_get(uint32_t i2c_periph, i2c_interrupt_flag_enum int_flag);
|
||||||
/* clear I2C interrupt flag */
|
/* clear I2C interrupt flag status */
|
||||||
void i2c_interrupt_flag_clear(uint32_t i2c_periph, i2c_interrupt_flag_enum int_flag);
|
void i2c_interrupt_flag_clear(uint32_t i2c_periph, i2c_interrupt_flag_enum int_flag);
|
||||||
|
|
||||||
#endif /* GD32F4XX_I2C_H */
|
#endif /* GD32F4XX_I2C_H */
|
||||||
|
|
|
||||||
|
|
@ -5,10 +5,11 @@
|
||||||
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
||||||
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
||||||
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
||||||
|
\version 2022-03-09, V3.0.0, firmware for GD32F4xx
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/*
|
/*
|
||||||
Copyright (c) 2020, GigaDevice Semiconductor Inc.
|
Copyright (c) 2022, GigaDevice Semiconductor Inc.
|
||||||
|
|
||||||
Redistribution and use in source and binary forms, with or without modification,
|
Redistribution and use in source and binary forms, with or without modification,
|
||||||
are permitted provided that the following conditions are met:
|
are permitted provided that the following conditions are met:
|
||||||
|
|
@ -44,26 +45,26 @@ OF SUCH DAMAGE.
|
||||||
|
|
||||||
/* bits definitions */
|
/* bits definitions */
|
||||||
/* registers definitions */
|
/* registers definitions */
|
||||||
#define IPA_CTL REG32(IPA + 0x00U) /*!< IPA control register */
|
#define IPA_CTL REG32(IPA + 0x00000000U) /*!< IPA control register */
|
||||||
#define IPA_INTF REG32(IPA + 0x04U) /*!< IPA interrupt flag register */
|
#define IPA_INTF REG32(IPA + 0x00000004U) /*!< IPA interrupt flag register */
|
||||||
#define IPA_INTC REG32(IPA + 0x08U) /*!< IPA interrupt flag clear register */
|
#define IPA_INTC REG32(IPA + 0x00000008U) /*!< IPA interrupt flag clear register */
|
||||||
#define IPA_FMADDR REG32(IPA + 0x0CU) /*!< IPA foreground memory base address register */
|
#define IPA_FMADDR REG32(IPA + 0x0000000CU) /*!< IPA foreground memory base address register */
|
||||||
#define IPA_FLOFF REG32(IPA + 0x10U) /*!< IPA foreground line offset register */
|
#define IPA_FLOFF REG32(IPA + 0x00000010U) /*!< IPA foreground line offset register */
|
||||||
#define IPA_BMADDR REG32(IPA + 0x14U) /*!< IPA background memory base address register */
|
#define IPA_BMADDR REG32(IPA + 0x00000014U) /*!< IPA background memory base address register */
|
||||||
#define IPA_BLOFF REG32(IPA + 0x18U) /*!< IPA background line offset register */
|
#define IPA_BLOFF REG32(IPA + 0x00000018U) /*!< IPA background line offset register */
|
||||||
#define IPA_FPCTL REG32(IPA + 0x1CU) /*!< IPA foreground pixel control register */
|
#define IPA_FPCTL REG32(IPA + 0x0000001CU) /*!< IPA foreground pixel control register */
|
||||||
#define IPA_FPV REG32(IPA + 0x20U) /*!< IPA foreground pixel value register */
|
#define IPA_FPV REG32(IPA + 0x00000020U) /*!< IPA foreground pixel value register */
|
||||||
#define IPA_BPCTL REG32(IPA + 0x24U) /*!< IPA background pixel control register */
|
#define IPA_BPCTL REG32(IPA + 0x00000024U) /*!< IPA background pixel control register */
|
||||||
#define IPA_BPV REG32(IPA + 0x28U) /*!< IPA background pixel value register */
|
#define IPA_BPV REG32(IPA + 0x00000028U) /*!< IPA background pixel value register */
|
||||||
#define IPA_FLMADDR REG32(IPA + 0x2CU) /*!< IPA foreground LUT memory base address register */
|
#define IPA_FLMADDR REG32(IPA + 0x0000002CU) /*!< IPA foreground LUT memory base address register */
|
||||||
#define IPA_BLMADDR REG32(IPA + 0x30U) /*!< IPA background LUT memory base address register */
|
#define IPA_BLMADDR REG32(IPA + 0x00000030U) /*!< IPA background LUT memory base address register */
|
||||||
#define IPA_DPCTL REG32(IPA + 0x34U) /*!< IPA destination pixel control register */
|
#define IPA_DPCTL REG32(IPA + 0x00000034U) /*!< IPA destination pixel control register */
|
||||||
#define IPA_DPV REG32(IPA + 0x38U) /*!< IPA destination pixel value register */
|
#define IPA_DPV REG32(IPA + 0x00000038U) /*!< IPA destination pixel value register */
|
||||||
#define IPA_DMADDR REG32(IPA + 0x3CU) /*!< IPA destination memory base address register */
|
#define IPA_DMADDR REG32(IPA + 0x0000003CU) /*!< IPA destination memory base address register */
|
||||||
#define IPA_DLOFF REG32(IPA + 0x40U) /*!< IPA destination line offset register */
|
#define IPA_DLOFF REG32(IPA + 0x00000040U) /*!< IPA destination line offset register */
|
||||||
#define IPA_IMS REG32(IPA + 0x44U) /*!< IPA image size register */
|
#define IPA_IMS REG32(IPA + 0x00000044U) /*!< IPA image size register */
|
||||||
#define IPA_LM REG32(IPA + 0x48U) /*!< IPA line mark register */
|
#define IPA_LM REG32(IPA + 0x00000048U) /*!< IPA line mark register */
|
||||||
#define IPA_ITCTL REG32(IPA + 0x4CU) /*!< IPA inter-timer control register */
|
#define IPA_ITCTL REG32(IPA + 0x0000004CU) /*!< IPA inter-timer control register */
|
||||||
|
|
||||||
/* IPA_CTL */
|
/* IPA_CTL */
|
||||||
#define IPA_CTL_TEN BIT(0) /*!< transfer enable */
|
#define IPA_CTL_TEN BIT(0) /*!< transfer enable */
|
||||||
|
|
@ -189,8 +190,7 @@ OF SUCH DAMAGE.
|
||||||
|
|
||||||
/* constants definitions */
|
/* constants definitions */
|
||||||
/* IPA foreground parameter struct definitions */
|
/* IPA foreground parameter struct definitions */
|
||||||
typedef struct
|
typedef struct {
|
||||||
{
|
|
||||||
uint32_t foreground_memaddr; /*!< foreground memory base address */
|
uint32_t foreground_memaddr; /*!< foreground memory base address */
|
||||||
uint32_t foreground_lineoff; /*!< foreground line offset */
|
uint32_t foreground_lineoff; /*!< foreground line offset */
|
||||||
uint32_t foreground_prealpha; /*!< foreground pre-defined alpha value */
|
uint32_t foreground_prealpha; /*!< foreground pre-defined alpha value */
|
||||||
|
|
@ -202,8 +202,7 @@ typedef struct
|
||||||
} ipa_foreground_parameter_struct;
|
} ipa_foreground_parameter_struct;
|
||||||
|
|
||||||
/* IPA background parameter struct definitions */
|
/* IPA background parameter struct definitions */
|
||||||
typedef struct
|
typedef struct {
|
||||||
{
|
|
||||||
uint32_t background_memaddr; /*!< background memory base address */
|
uint32_t background_memaddr; /*!< background memory base address */
|
||||||
uint32_t background_lineoff; /*!< background line offset */
|
uint32_t background_lineoff; /*!< background line offset */
|
||||||
uint32_t background_prealpha; /*!< background pre-defined alpha value */
|
uint32_t background_prealpha; /*!< background pre-defined alpha value */
|
||||||
|
|
@ -215,8 +214,7 @@ typedef struct
|
||||||
} ipa_background_parameter_struct;
|
} ipa_background_parameter_struct;
|
||||||
|
|
||||||
/* IPA destination parameter struct definitions */
|
/* IPA destination parameter struct definitions */
|
||||||
typedef struct
|
typedef struct {
|
||||||
{
|
|
||||||
uint32_t destination_memaddr; /*!< destination memory base address */
|
uint32_t destination_memaddr; /*!< destination memory base address */
|
||||||
uint32_t destination_lineoff; /*!< destination line offset */
|
uint32_t destination_lineoff; /*!< destination line offset */
|
||||||
uint32_t destination_prealpha; /*!< destination pre-defined alpha value */
|
uint32_t destination_prealpha; /*!< destination pre-defined alpha value */
|
||||||
|
|
@ -229,8 +227,7 @@ typedef struct
|
||||||
} ipa_destination_parameter_struct;
|
} ipa_destination_parameter_struct;
|
||||||
|
|
||||||
/* destination pixel format */
|
/* destination pixel format */
|
||||||
typedef enum
|
typedef enum {
|
||||||
{
|
|
||||||
IPA_DPF_ARGB8888, /*!< destination pixel format ARGB8888 */
|
IPA_DPF_ARGB8888, /*!< destination pixel format ARGB8888 */
|
||||||
IPA_DPF_RGB888, /*!< destination pixel format RGB888 */
|
IPA_DPF_RGB888, /*!< destination pixel format RGB888 */
|
||||||
IPA_DPF_RGB565, /*!< destination pixel format RGB565 */
|
IPA_DPF_RGB565, /*!< destination pixel format RGB565 */
|
||||||
|
|
|
||||||
|
|
@ -5,10 +5,11 @@
|
||||||
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
||||||
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
||||||
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
||||||
|
\version 2022-03-09, V3.0.0, firmware for GD32F4xx
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/*
|
/*
|
||||||
Copyright (c) 2020, GigaDevice Semiconductor Inc.
|
Copyright (c) 2022, GigaDevice Semiconductor Inc.
|
||||||
|
|
||||||
Redistribution and use in source and binary forms, with or without modification,
|
Redistribution and use in source and binary forms, with or without modification,
|
||||||
are permitted provided that the following conditions are met:
|
are permitted provided that the following conditions are met:
|
||||||
|
|
@ -167,7 +168,7 @@ OF SUCH DAMAGE.
|
||||||
#define IREF_SINK_CURRENT IREF_CURRENT(1) /*!< IREF sink current */
|
#define IREF_SINK_CURRENT IREF_CURRENT(1) /*!< IREF sink current */
|
||||||
|
|
||||||
/* function declarations */
|
/* function declarations */
|
||||||
/* deinit IREF */
|
/* deinitialize IREF */
|
||||||
void iref_deinit(void);
|
void iref_deinit(void);
|
||||||
/* enable IREF */
|
/* enable IREF */
|
||||||
void iref_enable(void);
|
void iref_enable(void);
|
||||||
|
|
|
||||||
|
|
@ -1,14 +1,14 @@
|
||||||
/*!
|
/*!
|
||||||
\file gd32f4xx_misc.h
|
\file gd32f4xx_misc.h
|
||||||
\brief definitions for the MISC
|
\brief definitions for the MISC
|
||||||
|
|
||||||
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
||||||
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
||||||
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
||||||
|
\version 2022-03-09, V3.0.0, firmware for GD32F4xx
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/*
|
/*
|
||||||
Copyright (c) 2020, GigaDevice Semiconductor Inc.
|
Copyright (c) 2022, GigaDevice Semiconductor Inc.
|
||||||
|
|
||||||
Redistribution and use in source and binary forms, with or without modification,
|
Redistribution and use in source and binary forms, with or without modification,
|
||||||
are permitted provided that the following conditions are met:
|
are permitted provided that the following conditions are met:
|
||||||
|
|
|
||||||
|
|
@ -5,10 +5,11 @@
|
||||||
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
||||||
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
||||||
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
||||||
|
\version 2022-03-09, V3.0.0, firmware for GD32F4xx
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/*
|
/*
|
||||||
Copyright (c) 2020, GigaDevice Semiconductor Inc.
|
Copyright (c) 2022, GigaDevice Semiconductor Inc.
|
||||||
|
|
||||||
Redistribution and use in source and binary forms, with or without modification,
|
Redistribution and use in source and binary forms, with or without modification,
|
||||||
are permitted provided that the following conditions are met:
|
are permitted provided that the following conditions are met:
|
||||||
|
|
@ -44,8 +45,8 @@ OF SUCH DAMAGE.
|
||||||
#define PMU PMU_BASE /*!< PMU base address */
|
#define PMU PMU_BASE /*!< PMU base address */
|
||||||
|
|
||||||
/* registers definitions */
|
/* registers definitions */
|
||||||
#define PMU_CTL REG32((PMU) + 0x00U) /*!< PMU control register */
|
#define PMU_CTL REG32((PMU) + 0x00000000U) /*!< PMU control register */
|
||||||
#define PMU_CS REG32((PMU) + 0x04U) /*!< PMU control and status register */
|
#define PMU_CS REG32((PMU) + 0x00000004U) /*!< PMU control and status register */
|
||||||
|
|
||||||
/* bits definitions */
|
/* bits definitions */
|
||||||
/* PMU_CTL */
|
/* PMU_CTL */
|
||||||
|
|
@ -73,9 +74,13 @@ OF SUCH DAMAGE.
|
||||||
#define PMU_CS_LDOVSRF BIT(14) /*!< LDO voltage select ready flag */
|
#define PMU_CS_LDOVSRF BIT(14) /*!< LDO voltage select ready flag */
|
||||||
#define PMU_CS_HDRF BIT(16) /*!< high-driver ready flag */
|
#define PMU_CS_HDRF BIT(16) /*!< high-driver ready flag */
|
||||||
#define PMU_CS_HDSRF BIT(17) /*!< high-driver switch ready flag */
|
#define PMU_CS_HDSRF BIT(17) /*!< high-driver switch ready flag */
|
||||||
#define PMU_CS_LDRF BITS(18,19) /*!< Low-driver mode ready flag */
|
#define PMU_CS_LDRF BITS(18,19) /*!< low-driver mode ready flag */
|
||||||
|
|
||||||
/* constants definitions */
|
/* constants definitions */
|
||||||
|
/* PMU ldo definitions */
|
||||||
|
#define PMU_LDO_NORMAL ((uint32_t)0x00000000U) /*!< LDO normal work when PMU enter deep-sleep mode */
|
||||||
|
#define PMU_LDO_LOWPOWER PMU_CTL_LDOLP /*!< LDO work at low power status when PMU enter deep-sleep mode */
|
||||||
|
|
||||||
/* PMU low voltage detector threshold definitions */
|
/* PMU low voltage detector threshold definitions */
|
||||||
#define CTL_LVDT(regval) (BITS(5,7)&((uint32_t)(regval)<<5))
|
#define CTL_LVDT(regval) (BITS(5,7)&((uint32_t)(regval)<<5))
|
||||||
#define PMU_LVDT_0 CTL_LVDT(0) /*!< voltage threshold is 2.1V */
|
#define PMU_LVDT_0 CTL_LVDT(0) /*!< voltage threshold is 2.1V */
|
||||||
|
|
@ -87,22 +92,6 @@ OF SUCH DAMAGE.
|
||||||
#define PMU_LVDT_6 CTL_LVDT(6) /*!< voltage threshold is 3.0V */
|
#define PMU_LVDT_6 CTL_LVDT(6) /*!< voltage threshold is 3.0V */
|
||||||
#define PMU_LVDT_7 CTL_LVDT(7) /*!< voltage threshold is 3.1V */
|
#define PMU_LVDT_7 CTL_LVDT(7) /*!< voltage threshold is 3.1V */
|
||||||
|
|
||||||
/* PMU LDO output voltage select definitions */
|
|
||||||
#define CTL_LDOVS(regval) (BITS(14,15)&((uint32_t)(regval)<<14))
|
|
||||||
#define PMU_LDOVS_LOW CTL_LDOVS(1) /*!< LDO output voltage low mode */
|
|
||||||
#define PMU_LDOVS_MID CTL_LDOVS(2) /*!< LDO output voltage mid mode */
|
|
||||||
#define PMU_LDOVS_HIGH CTL_LDOVS(3) /*!< LDO output voltage high mode */
|
|
||||||
|
|
||||||
/* PMU low-driver mode enable in deep-sleep mode */
|
|
||||||
#define CTL_LDEN(regval) (BITS(18,19)&((uint32_t)(regval)<<18))
|
|
||||||
#define PMU_LOWDRIVER_DISABLE CTL_LDEN(0) /*!< low-driver mode disable in deep-sleep mode */
|
|
||||||
#define PMU_LOWDRIVER_ENABLE CTL_LDEN(3) /*!< low-driver mode enable in deep-sleep mode */
|
|
||||||
|
|
||||||
/* PMU high-driver mode switch */
|
|
||||||
#define CTL_HDS(regval) (BIT(17)&((uint32_t)(regval)<<17))
|
|
||||||
#define PMU_HIGHDR_SWITCH_NONE CTL_HDS(0) /*!< no high-driver mode switch */
|
|
||||||
#define PMU_HIGHDR_SWITCH_EN CTL_HDS(1) /*!< high-driver mode switch */
|
|
||||||
|
|
||||||
/* PMU low-driver mode when use low power LDO */
|
/* PMU low-driver mode when use low power LDO */
|
||||||
#define CTL_LDLP(regval) (BIT(10)&((uint32_t)(regval)<<10))
|
#define CTL_LDLP(regval) (BIT(10)&((uint32_t)(regval)<<10))
|
||||||
#define PMU_NORMALDR_LOWPWR CTL_LDLP(0) /*!< normal driver when use low power LDO */
|
#define PMU_NORMALDR_LOWPWR CTL_LDLP(0) /*!< normal driver when use low power LDO */
|
||||||
|
|
@ -113,16 +102,33 @@ OF SUCH DAMAGE.
|
||||||
#define PMU_NORMALDR_NORMALPWR CTL_LDNP(0) /*!< normal driver when use normal power LDO */
|
#define PMU_NORMALDR_NORMALPWR CTL_LDNP(0) /*!< normal driver when use normal power LDO */
|
||||||
#define PMU_LOWDR_NORMALPWR CTL_LDNP(1) /*!< low-driver mode enabled when LDEN is 11 and use normal power LDO */
|
#define PMU_LOWDR_NORMALPWR CTL_LDNP(1) /*!< low-driver mode enabled when LDEN is 11 and use normal power LDO */
|
||||||
|
|
||||||
/* PMU low power mode ready flag definitions */
|
/* PMU LDO output voltage select definitions */
|
||||||
#define CS_LDRF(regval) (BITS(18,19)&((uint32_t)(regval)<<18))
|
#define CTL_LDOVS(regval) (BITS(14,15)&((uint32_t)(regval)<<14))
|
||||||
#define PMU_LDRF_NORMAL CS_LDRF(0) /*!< normal driver in deep-sleep mode */
|
#define PMU_LDOVS_LOW CTL_LDOVS(1) /*!< LDO output voltage low mode */
|
||||||
#define PMU_LDRF_LOWDRIVER CS_LDRF(3) /*!< low-driver mode in deep-sleep mode */
|
#define PMU_LDOVS_MID CTL_LDOVS(2) /*!< LDO output voltage mid mode */
|
||||||
|
#define PMU_LDOVS_HIGH CTL_LDOVS(3) /*!< LDO output voltage high mode */
|
||||||
|
|
||||||
|
|
||||||
|
/* PMU high-driver mode switch */
|
||||||
|
#define CTL_HDS(regval) (BIT(17)&((uint32_t)(regval)<<17))
|
||||||
|
#define PMU_HIGHDR_SWITCH_NONE CTL_HDS(0) /*!< no high-driver mode switch */
|
||||||
|
#define PMU_HIGHDR_SWITCH_EN CTL_HDS(1) /*!< high-driver mode switch */
|
||||||
|
|
||||||
|
/* PMU low-driver mode enable in deep-sleep mode */
|
||||||
|
#define CTL_LDEN(regval) (BITS(18,19)&((uint32_t)(regval)<<18))
|
||||||
|
#define PMU_LOWDRIVER_DISABLE CTL_LDEN(0) /*!< low-driver mode disable in deep-sleep mode */
|
||||||
|
#define PMU_LOWDRIVER_ENABLE CTL_LDEN(3) /*!< low-driver mode enable in deep-sleep mode */
|
||||||
|
|
||||||
/* PMU backup SRAM LDO on or off */
|
/* PMU backup SRAM LDO on or off */
|
||||||
#define CS_BLDOON(regval) (BIT(9)&((uint32_t)(regval)<<9))
|
#define CS_BLDOON(regval) (BIT(9)&((uint32_t)(regval)<<9))
|
||||||
#define PMU_BLDOON_OFF CS_BLDOON(0) /*!< backup SRAM LDO off */
|
#define PMU_BLDOON_OFF CS_BLDOON(0) /*!< backup SRAM LDO off */
|
||||||
#define PMU_BLDOON_ON CS_BLDOON(1) /*!< the backup SRAM LDO on */
|
#define PMU_BLDOON_ON CS_BLDOON(1) /*!< the backup SRAM LDO on */
|
||||||
|
|
||||||
|
/* PMU low power mode ready flag definitions */
|
||||||
|
#define CS_LDRF(regval) (BITS(18,19)&((uint32_t)(regval)<<18))
|
||||||
|
#define PMU_LDRF_NORMAL CS_LDRF(0) /*!< normal driver in deep-sleep mode */
|
||||||
|
#define PMU_LDRF_LOWDRIVER CS_LDRF(3) /*!< low-driver mode in deep-sleep mode */
|
||||||
|
|
||||||
/* PMU flag definitions */
|
/* PMU flag definitions */
|
||||||
#define PMU_FLAG_WAKEUP PMU_CS_WUF /*!< wakeup flag status */
|
#define PMU_FLAG_WAKEUP PMU_CS_WUF /*!< wakeup flag status */
|
||||||
#define PMU_FLAG_STANDBY PMU_CS_STBF /*!< standby flag status */
|
#define PMU_FLAG_STANDBY PMU_CS_STBF /*!< standby flag status */
|
||||||
|
|
@ -133,10 +139,6 @@ OF SUCH DAMAGE.
|
||||||
#define PMU_FLAG_HDSRF PMU_CS_HDSRF /*!< high-driver switch ready flag */
|
#define PMU_FLAG_HDSRF PMU_CS_HDSRF /*!< high-driver switch ready flag */
|
||||||
#define PMU_FLAG_LDRF PMU_CS_LDRF /*!< low-driver mode ready flag */
|
#define PMU_FLAG_LDRF PMU_CS_LDRF /*!< low-driver mode ready flag */
|
||||||
|
|
||||||
/* PMU ldo definitions */
|
|
||||||
#define PMU_LDO_NORMAL ((uint32_t)0x00000000U) /*!< LDO normal work when PMU enter deepsleep mode */
|
|
||||||
#define PMU_LDO_LOWPOWER PMU_CTL_LDOLP /*!< LDO work at low power status when PMU enter deepsleep mode */
|
|
||||||
|
|
||||||
/* PMU flag reset definitions */
|
/* PMU flag reset definitions */
|
||||||
#define PMU_FLAG_RESET_WAKEUP ((uint8_t)0x00U) /*!< wakeup flag reset */
|
#define PMU_FLAG_RESET_WAKEUP ((uint8_t)0x00U) /*!< wakeup flag reset */
|
||||||
#define PMU_FLAG_RESET_STANDBY ((uint8_t)0x01U) /*!< standby flag reset */
|
#define PMU_FLAG_RESET_STANDBY ((uint8_t)0x01U) /*!< standby flag reset */
|
||||||
|
|
@ -146,54 +148,59 @@ OF SUCH DAMAGE.
|
||||||
#define WFE_CMD ((uint8_t)0x01U) /*!< use WFE command */
|
#define WFE_CMD ((uint8_t)0x01U) /*!< use WFE command */
|
||||||
|
|
||||||
/* function declarations */
|
/* function declarations */
|
||||||
/* reset PMU register */
|
/* reset PMU registers */
|
||||||
void pmu_deinit(void);
|
void pmu_deinit(void);
|
||||||
|
|
||||||
|
/* LVD functions */
|
||||||
/* select low voltage detector threshold */
|
/* select low voltage detector threshold */
|
||||||
void pmu_lvd_select(uint32_t lvdt_n);
|
void pmu_lvd_select(uint32_t lvdt_n);
|
||||||
/* LDO output voltage select */
|
/* disable PMU lvd */
|
||||||
void pmu_ldo_output_select(uint32_t ldo_output);
|
|
||||||
/* PMU lvd disable */
|
|
||||||
void pmu_lvd_disable(void);
|
void pmu_lvd_disable(void);
|
||||||
|
|
||||||
/* functions of low-driver mode and high-driver mode in deep-sleep mode */
|
/* LDO functions */
|
||||||
/* high-driver mode switch */
|
/* select LDO output voltage */
|
||||||
void pmu_highdriver_switch_select(uint32_t highdr_switch);
|
void pmu_ldo_output_select(uint32_t ldo_output);
|
||||||
/* high-driver mode enable */
|
|
||||||
|
/* functions of low-driver mode and high-driver mode */
|
||||||
|
/* enable high-driver mode */
|
||||||
void pmu_highdriver_mode_enable(void);
|
void pmu_highdriver_mode_enable(void);
|
||||||
/* high-driver mode disable */
|
/* disable high-driver mode */
|
||||||
void pmu_highdriver_mode_disable(void);
|
void pmu_highdriver_mode_disable(void);
|
||||||
/* low-driver mode enable in deep-sleep mode */
|
/* switch high-driver mode */
|
||||||
void pmu_low_driver_mode_enable(uint32_t lowdr_mode);
|
void pmu_highdriver_switch_select(uint32_t highdr_switch);
|
||||||
/* in deep-sleep mode, low-driver mode when use low power LDO */
|
/* enable low-driver mode in deep-sleep */
|
||||||
void pmu_lowdriver_lowpower_config(uint32_t mode);
|
void pmu_lowdriver_mode_enable(void);
|
||||||
/* in deep-sleep mode, low-driver mode when use normal power LDO */
|
/* disable low-driver mode in deep-sleep */
|
||||||
void pmu_lowdriver_normalpower_config(uint32_t mode);
|
void pmu_lowdriver_mode_disable(void);
|
||||||
|
/* in deep-sleep mode, driver mode when use low power LDO */
|
||||||
|
void pmu_lowpower_driver_config(uint32_t mode);
|
||||||
|
/* in deep-sleep mode, driver mode when use normal power LDO */
|
||||||
|
void pmu_normalpower_driver_config(uint32_t mode);
|
||||||
|
|
||||||
/* set PMU mode */
|
/* set PMU mode */
|
||||||
/* PMU work at sleep mode */
|
/* PMU work in sleep mode */
|
||||||
void pmu_to_sleepmode(uint8_t sleepmodecmd);
|
void pmu_to_sleepmode(uint8_t sleepmodecmd);
|
||||||
/* PMU work at deepsleep mode */
|
/* PMU work in deepsleep mode */
|
||||||
void pmu_to_deepsleepmode(uint32_t ldo, uint8_t deepsleepmodecmd);
|
void pmu_to_deepsleepmode(uint32_t ldo, uint32_t lowdrive, uint8_t deepsleepmodecmd);
|
||||||
/* PMU work at standby mode */
|
/* PMU work in standby mode */
|
||||||
void pmu_to_standbymode(uint8_t standbymodecmd);
|
void pmu_to_standbymode(void);
|
||||||
/* PMU wakeup pin enable */
|
/* enable PMU wakeup pin */
|
||||||
void pmu_wakeup_pin_enable(void);
|
void pmu_wakeup_pin_enable(void);
|
||||||
/* PMU wakeup pin disable */
|
/* disable PMU wakeup pin */
|
||||||
void pmu_wakeup_pin_disable(void);
|
void pmu_wakeup_pin_disable(void);
|
||||||
|
|
||||||
/* backup related functions */
|
/* backup related functions */
|
||||||
/* backup SRAM LDO on */
|
/* backup SRAM LDO on */
|
||||||
void pmu_backup_ldo_config(uint32_t bkp_ldo);
|
void pmu_backup_ldo_config(uint32_t bkp_ldo);
|
||||||
/* backup domain write enable */
|
/* enable write access to the registers in backup domain */
|
||||||
void pmu_backup_write_enable(void);
|
void pmu_backup_write_enable(void);
|
||||||
/* backup domain write disable */
|
/* disable write access to the registers in backup domain */
|
||||||
void pmu_backup_write_disable(void);
|
void pmu_backup_write_disable(void);
|
||||||
|
|
||||||
/* flag functions */
|
/* flag functions */
|
||||||
/* reset flag bit */
|
/* get flag state */
|
||||||
void pmu_flag_reset(uint32_t flag_reset);
|
FlagStatus pmu_flag_get(uint32_t flag);
|
||||||
/* get flag status */
|
/* clear flag bit */
|
||||||
FlagStatus pmu_flag_get(uint32_t pmu_flag);
|
void pmu_flag_clear(uint32_t flag);
|
||||||
|
|
||||||
#endif /* GD32F4XX_PMU_H */
|
#endif /* GD32F4XX_PMU_H */
|
||||||
|
|
|
||||||
|
|
@ -5,10 +5,11 @@
|
||||||
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
||||||
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
||||||
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
||||||
|
\version 2022-03-09, V3.0.0, firmware for GD32F4xx
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/*
|
/*
|
||||||
Copyright (c) 2020, GigaDevice Semiconductor Inc.
|
Copyright (c) 2022, GigaDevice Semiconductor Inc.
|
||||||
|
|
||||||
Redistribution and use in source and binary forms, with or without modification,
|
Redistribution and use in source and binary forms, with or without modification,
|
||||||
are permitted provided that the following conditions are met:
|
are permitted provided that the following conditions are met:
|
||||||
|
|
@ -397,13 +398,11 @@ OF SUCH DAMAGE.
|
||||||
|
|
||||||
/* RCU_PLLI2S */
|
/* RCU_PLLI2S */
|
||||||
#define RCU_PLLI2S_PLLI2SN BITS(6,14) /*!< the PLLI2S VCO clock multi factor */
|
#define RCU_PLLI2S_PLLI2SN BITS(6,14) /*!< the PLLI2S VCO clock multi factor */
|
||||||
#define RCU_PLLI2S_PLLI2SQ BITS(24,27) /*!< the PLLI2S Q output frequency division factor from PLLI2S VCO clock */
|
|
||||||
#define RCU_PLLI2S_PLLI2SR BITS(28,30) /*!< the PLLI2S R output frequency division factor from PLLI2S VCO clock */
|
#define RCU_PLLI2S_PLLI2SR BITS(28,30) /*!< the PLLI2S R output frequency division factor from PLLI2S VCO clock */
|
||||||
|
|
||||||
/* RCU_PLLSAI */
|
/* RCU_PLLSAI */
|
||||||
#define RCU_PLLSAI_PLLSAIN BITS(6,14) /*!< the PLLSAI VCO clock multi factor */
|
#define RCU_PLLSAI_PLLSAIN BITS(6,14) /*!< the PLLSAI VCO clock multi factor */
|
||||||
#define RCU_PLLSAI_PLLSAIP BITS(16,17) /*!< the PLLSAI P output frequency division factor from PLLSAI VCO clock */
|
#define RCU_PLLSAI_PLLSAIP BITS(16,17) /*!< the PLLSAI P output frequency division factor from PLLSAI VCO clock */
|
||||||
#define RCU_PLLSAI_PLLSAIQ BITS(24,27) /*!< the PLLSAI Q output frequency division factor from PLLSAI VCO clock */
|
|
||||||
#define RCU_PLLSAI_PLLSAIR BITS(28,30) /*!< the PLLSAI R output frequency division factor from PLLSAI VCO clock */
|
#define RCU_PLLSAI_PLLSAIR BITS(28,30) /*!< the PLLSAI R output frequency division factor from PLLSAI VCO clock */
|
||||||
|
|
||||||
/* RCU_CFG1 */
|
/* RCU_CFG1 */
|
||||||
|
|
@ -1068,13 +1067,14 @@ typedef enum
|
||||||
|
|
||||||
/* Deep-sleep mode voltage */
|
/* Deep-sleep mode voltage */
|
||||||
#define DSV_DSLPVS(regval) (BITS(0,2) & ((uint32_t)(regval) << 0))
|
#define DSV_DSLPVS(regval) (BITS(0,2) & ((uint32_t)(regval) << 0))
|
||||||
#define RCU_DEEPSLEEP_V_1_2 DSV_DSLPVS(0) /*!< core voltage is 1.2V in deep-sleep mode */
|
#define RCU_DEEPSLEEP_V_0 DSV_DSLPVS(0) /*!< core voltage is default value in deep-sleep mode */
|
||||||
#define RCU_DEEPSLEEP_V_1_1 DSV_DSLPVS(1) /*!< core voltage is 1.1V in deep-sleep mode */
|
#define RCU_DEEPSLEEP_V_1 DSV_DSLPVS(1) /*!< core voltage is (default value-0.1)V in deep-sleep mode(customers are not recommended to use it)*/
|
||||||
#define RCU_DEEPSLEEP_V_1_0 DSV_DSLPVS(2) /*!< core voltage is 1.0V in deep-sleep mode */
|
#define RCU_DEEPSLEEP_V_2 DSV_DSLPVS(2) /*!< core voltage is (default value-0.2)V in deep-sleep mode(customers are not recommended to use it)*/
|
||||||
#define RCU_DEEPSLEEP_V_0_9 DSV_DSLPVS(3) /*!< core voltage is 0.9V in deep-sleep mode */
|
#define RCU_DEEPSLEEP_V_3 DSV_DSLPVS(3) /*!< core voltage is (default value-0.3)V in deep-sleep mode(customers are not recommended to use it)*/
|
||||||
|
|
||||||
|
|
||||||
/* function declarations */
|
/* function declarations */
|
||||||
|
/* peripherals clock configure functions */
|
||||||
/* deinitialize the RCU */
|
/* deinitialize the RCU */
|
||||||
void rcu_deinit(void);
|
void rcu_deinit(void);
|
||||||
/* enable the peripherals clock */
|
/* enable the peripherals clock */
|
||||||
|
|
@ -1094,6 +1094,7 @@ void rcu_bkp_reset_enable(void);
|
||||||
/* disable the BKP reset */
|
/* disable the BKP reset */
|
||||||
void rcu_bkp_reset_disable(void);
|
void rcu_bkp_reset_disable(void);
|
||||||
|
|
||||||
|
/* system and peripherals clock source, system reset configure functions */
|
||||||
/* configure the system clock source */
|
/* configure the system clock source */
|
||||||
void rcu_system_clock_source_config(uint32_t ck_sys);
|
void rcu_system_clock_source_config(uint32_t ck_sys);
|
||||||
/* get the system clock source */
|
/* get the system clock source */
|
||||||
|
|
@ -1129,7 +1130,43 @@ void rcu_timer_clock_prescaler_config(uint32_t timer_clock_prescaler);
|
||||||
/* configure the TLI clock division selection */
|
/* configure the TLI clock division selection */
|
||||||
void rcu_tli_clock_div_config(uint32_t pllsai_r_div);
|
void rcu_tli_clock_div_config(uint32_t pllsai_r_div);
|
||||||
|
|
||||||
|
/* LXTAL, IRC8M, PLL and other oscillator configure functions */
|
||||||
|
/* configure the LXTAL drive capability */
|
||||||
|
void rcu_lxtal_drive_capability_config(uint32_t lxtal_dricap);
|
||||||
|
/* wait for oscillator stabilization flags is SET or oscillator startup is timeout */
|
||||||
|
ErrStatus rcu_osci_stab_wait(rcu_osci_type_enum osci);
|
||||||
|
/* turn on the oscillator */
|
||||||
|
void rcu_osci_on(rcu_osci_type_enum osci);
|
||||||
|
/* turn off the oscillator */
|
||||||
|
void rcu_osci_off(rcu_osci_type_enum osci);
|
||||||
|
/* enable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it */
|
||||||
|
void rcu_osci_bypass_mode_enable(rcu_osci_type_enum osci);
|
||||||
|
/* disable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it */
|
||||||
|
void rcu_osci_bypass_mode_disable(rcu_osci_type_enum osci);
|
||||||
|
/* set the IRC16M adjust value */
|
||||||
|
void rcu_irc16m_adjust_value_set(uint32_t irc16m_adjval);
|
||||||
|
/* configure the spread spectrum modulation for the main PLL clock */
|
||||||
|
void rcu_spread_spectrum_config(uint32_t spread_spectrum_type, uint32_t modstep, uint32_t modcnt);
|
||||||
|
/* enable the spread spectrum modulation for the main PLL clock */
|
||||||
|
void rcu_spread_spectrum_enable(void);
|
||||||
|
/* disable the spread spectrum modulation for the main PLL clock */
|
||||||
|
void rcu_spread_spectrum_disable(void);
|
||||||
|
|
||||||
|
/* clock monitor configure functions */
|
||||||
|
/* enable the HXTAL clock monitor */
|
||||||
|
void rcu_hxtal_clock_monitor_enable(void);
|
||||||
|
/* disable the HXTAL clock monitor */
|
||||||
|
void rcu_hxtal_clock_monitor_disable(void);
|
||||||
|
|
||||||
|
/* voltage configure and clock frequency get functions */
|
||||||
|
/* unlock the voltage key */
|
||||||
|
void rcu_voltage_key_unlock(void);
|
||||||
|
/* set the deep sleep mode voltage */
|
||||||
|
void rcu_deepsleep_voltage_set(uint32_t dsvol);
|
||||||
|
/* get the system clock, bus and peripheral clock frequency */
|
||||||
|
uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock);
|
||||||
|
|
||||||
|
/* flag & interrupt functions */
|
||||||
/* get the clock stabilization and periphral reset flags */
|
/* get the clock stabilization and periphral reset flags */
|
||||||
FlagStatus rcu_flag_get(rcu_flag_enum flag);
|
FlagStatus rcu_flag_get(rcu_flag_enum flag);
|
||||||
/* clear the reset flag */
|
/* clear the reset flag */
|
||||||
|
|
@ -1143,37 +1180,4 @@ void rcu_interrupt_enable(rcu_int_enum interrupt);
|
||||||
/* disable the stabilization interrupt */
|
/* disable the stabilization interrupt */
|
||||||
void rcu_interrupt_disable(rcu_int_enum interrupt);
|
void rcu_interrupt_disable(rcu_int_enum interrupt);
|
||||||
|
|
||||||
/* configure the LXTAL drive capability */
|
|
||||||
void rcu_lxtal_drive_capability_config(uint32_t lxtal_dricap);
|
|
||||||
/* wait for oscillator stabilization flags is SET or oscillator startup is timeout */
|
|
||||||
ErrStatus rcu_osci_stab_wait(rcu_osci_type_enum osci);
|
|
||||||
/* turn on the oscillator */
|
|
||||||
void rcu_osci_on(rcu_osci_type_enum osci);
|
|
||||||
/* turn off the oscillator */
|
|
||||||
void rcu_osci_off(rcu_osci_type_enum osci);
|
|
||||||
/* enable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it */
|
|
||||||
void rcu_osci_bypass_mode_enable(rcu_osci_type_enum osci);
|
|
||||||
/* disable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it */
|
|
||||||
void rcu_osci_bypass_mode_disable(rcu_osci_type_enum osci);
|
|
||||||
/* enable the HXTAL clock monitor */
|
|
||||||
void rcu_hxtal_clock_monitor_enable(void);
|
|
||||||
/* disable the HXTAL clock monitor */
|
|
||||||
void rcu_hxtal_clock_monitor_disable(void);
|
|
||||||
|
|
||||||
/* set the IRC16M adjust value */
|
|
||||||
void rcu_irc16m_adjust_value_set(uint32_t irc16m_adjval);
|
|
||||||
/* configure the spread spectrum modulation for the main PLL clock */
|
|
||||||
void rcu_spread_spectrum_config(uint32_t spread_spectrum_type, uint32_t modstep, uint32_t modcnt);
|
|
||||||
/* enable the spread spectrum modulation for the main PLL clock */
|
|
||||||
void rcu_spread_spectrum_enable(void);
|
|
||||||
/* disable the spread spectrum modulation for the main PLL clock */
|
|
||||||
void rcu_spread_spectrum_disable(void);
|
|
||||||
/* unlock the voltage key */
|
|
||||||
void rcu_voltage_key_unlock(void);
|
|
||||||
/* set the deep sleep mode voltage */
|
|
||||||
void rcu_deepsleep_voltage_set(uint32_t dsvol);
|
|
||||||
|
|
||||||
/* get the system clock, bus and peripheral clock frequency */
|
|
||||||
uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock);
|
|
||||||
|
|
||||||
#endif /* GD32F4XX_RCU_H */
|
#endif /* GD32F4XX_RCU_H */
|
||||||
|
|
|
||||||
|
|
@ -5,10 +5,11 @@
|
||||||
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
||||||
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
||||||
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
||||||
|
\version 2022-03-09, V3.0.0, firmware for GD32F4xx
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/*
|
/*
|
||||||
Copyright (c) 2020, GigaDevice Semiconductor Inc.
|
Copyright (c) 2022, GigaDevice Semiconductor Inc.
|
||||||
|
|
||||||
Redistribution and use in source and binary forms, with or without modification,
|
Redistribution and use in source and binary forms, with or without modification,
|
||||||
are permitted provided that the following conditions are met:
|
are permitted provided that the following conditions are met:
|
||||||
|
|
|
||||||
|
|
@ -5,10 +5,11 @@
|
||||||
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
||||||
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
||||||
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
||||||
|
\version 2022-03-09, V3.0.0, firmware for GD32F4xx
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/*
|
/*
|
||||||
Copyright (c) 2020, GigaDevice Semiconductor Inc.
|
Copyright (c) 2022, GigaDevice Semiconductor Inc.
|
||||||
|
|
||||||
Redistribution and use in source and binary forms, with or without modification,
|
Redistribution and use in source and binary forms, with or without modification,
|
||||||
are permitted provided that the following conditions are met:
|
are permitted provided that the following conditions are met:
|
||||||
|
|
@ -43,24 +44,24 @@ OF SUCH DAMAGE.
|
||||||
#define SDIO SDIO_BASE
|
#define SDIO SDIO_BASE
|
||||||
|
|
||||||
/* registers definitions */
|
/* registers definitions */
|
||||||
#define SDIO_PWRCTL REG32(SDIO + 0x00U) /*!< SDIO power control register */
|
#define SDIO_PWRCTL REG32(SDIO + 0x00000000U) /*!< SDIO power control register */
|
||||||
#define SDIO_CLKCTL REG32(SDIO + 0x04U) /*!< SDIO clock control register */
|
#define SDIO_CLKCTL REG32(SDIO + 0x00000004U) /*!< SDIO clock control register */
|
||||||
#define SDIO_CMDAGMT REG32(SDIO + 0x08U) /*!< SDIO command argument register */
|
#define SDIO_CMDAGMT REG32(SDIO + 0x00000008U) /*!< SDIO command argument register */
|
||||||
#define SDIO_CMDCTL REG32(SDIO + 0x0CU) /*!< SDIO command control register */
|
#define SDIO_CMDCTL REG32(SDIO + 0x0000000CU) /*!< SDIO command control register */
|
||||||
#define SDIO_RSPCMDIDX REG32(SDIO + 0x10U) /*!< SDIO command index response register */
|
#define SDIO_RSPCMDIDX REG32(SDIO + 0x00000010U) /*!< SDIO command index response register */
|
||||||
#define SDIO_RESP0 REG32(SDIO + 0x14U) /*!< SDIO response register 0 */
|
#define SDIO_RESP0 REG32(SDIO + 0x00000014U) /*!< SDIO response register 0 */
|
||||||
#define SDIO_RESP1 REG32(SDIO + 0x18U) /*!< SDIO response register 1 */
|
#define SDIO_RESP1 REG32(SDIO + 0x00000018U) /*!< SDIO response register 1 */
|
||||||
#define SDIO_RESP2 REG32(SDIO + 0x1CU) /*!< SDIO response register 2 */
|
#define SDIO_RESP2 REG32(SDIO + 0x0000001CU) /*!< SDIO response register 2 */
|
||||||
#define SDIO_RESP3 REG32(SDIO + 0x20U) /*!< SDIO response register 3 */
|
#define SDIO_RESP3 REG32(SDIO + 0x00000020U) /*!< SDIO response register 3 */
|
||||||
#define SDIO_DATATO REG32(SDIO + 0x24U) /*!< SDIO data timeout register */
|
#define SDIO_DATATO REG32(SDIO + 0x00000024U) /*!< SDIO data timeout register */
|
||||||
#define SDIO_DATALEN REG32(SDIO + 0x28U) /*!< SDIO data length register */
|
#define SDIO_DATALEN REG32(SDIO + 0x00000028U) /*!< SDIO data length register */
|
||||||
#define SDIO_DATACTL REG32(SDIO + 0x2CU) /*!< SDIO data control register */
|
#define SDIO_DATACTL REG32(SDIO + 0x0000002CU) /*!< SDIO data control register */
|
||||||
#define SDIO_DATACNT REG32(SDIO + 0x30U) /*!< SDIO data counter register */
|
#define SDIO_DATACNT REG32(SDIO + 0x00000030U) /*!< SDIO data counter register */
|
||||||
#define SDIO_STAT REG32(SDIO + 0x34U) /*!< SDIO status register */
|
#define SDIO_STAT REG32(SDIO + 0x00000034U) /*!< SDIO status register */
|
||||||
#define SDIO_INTC REG32(SDIO + 0x38U) /*!< SDIO interrupt clear register */
|
#define SDIO_INTC REG32(SDIO + 0x00000038U) /*!< SDIO interrupt clear register */
|
||||||
#define SDIO_INTEN REG32(SDIO + 0x3CU) /*!< SDIO interrupt enable register */
|
#define SDIO_INTEN REG32(SDIO + 0x0000003CU) /*!< SDIO interrupt enable register */
|
||||||
#define SDIO_FIFOCNT REG32(SDIO + 0x48U) /*!< SDIO FIFO counter register */
|
#define SDIO_FIFOCNT REG32(SDIO + 0x00000048U) /*!< SDIO FIFO counter register */
|
||||||
#define SDIO_FIFO REG32(SDIO + 0x80U) /*!< SDIO FIFO data register */
|
#define SDIO_FIFO REG32(SDIO + 0x00000080U) /*!< SDIO FIFO data register */
|
||||||
|
|
||||||
/* bits definitions */
|
/* bits definitions */
|
||||||
/* SDIO_PWRCTL */
|
/* SDIO_PWRCTL */
|
||||||
|
|
|
||||||
|
|
@ -5,10 +5,11 @@
|
||||||
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
||||||
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
||||||
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
||||||
|
\version 2022-03-09, V3.0.0, firmware for GD32F4xx
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/*
|
/*
|
||||||
Copyright (c) 2020, GigaDevice Semiconductor Inc.
|
Copyright (c) 2022, GigaDevice Semiconductor Inc.
|
||||||
|
|
||||||
Redistribution and use in source and binary forms, with or without modification,
|
Redistribution and use in source and binary forms, with or without modification,
|
||||||
are permitted provided that the following conditions are met:
|
are permitted provided that the following conditions are met:
|
||||||
|
|
@ -53,27 +54,27 @@ OF SUCH DAMAGE.
|
||||||
#define I2S2_ADD (I2S_ADD_BASE + 0x00000C00U)
|
#define I2S2_ADD (I2S_ADD_BASE + 0x00000C00U)
|
||||||
|
|
||||||
/* SPI registers definitions */
|
/* SPI registers definitions */
|
||||||
#define SPI_CTL0(spix) REG32((spix) + 0x00U) /*!< SPI control register 0 */
|
#define SPI_CTL0(spix) REG32((spix) + 0x00000000U) /*!< SPI control register 0 */
|
||||||
#define SPI_CTL1(spix) REG32((spix) + 0x04U) /*!< SPI control register 1*/
|
#define SPI_CTL1(spix) REG32((spix) + 0x00000004U) /*!< SPI control register 1*/
|
||||||
#define SPI_STAT(spix) REG32((spix) + 0x08U) /*!< SPI status register */
|
#define SPI_STAT(spix) REG32((spix) + 0x00000008U) /*!< SPI status register */
|
||||||
#define SPI_DATA(spix) REG32((spix) + 0x0CU) /*!< SPI data register */
|
#define SPI_DATA(spix) REG32((spix) + 0x0000000CU) /*!< SPI data register */
|
||||||
#define SPI_CRCPOLY(spix) REG32((spix) + 0x10U) /*!< SPI CRC polynomial register */
|
#define SPI_CRCPOLY(spix) REG32((spix) + 0x00000010U) /*!< SPI CRC polynomial register */
|
||||||
#define SPI_RCRC(spix) REG32((spix) + 0x14U) /*!< SPI receive CRC register */
|
#define SPI_RCRC(spix) REG32((spix) + 0x00000014U) /*!< SPI receive CRC register */
|
||||||
#define SPI_TCRC(spix) REG32((spix) + 0x18U) /*!< SPI transmit CRC register */
|
#define SPI_TCRC(spix) REG32((spix) + 0x00000018U) /*!< SPI transmit CRC register */
|
||||||
#define SPI_I2SCTL(spix) REG32((spix) + 0x1CU) /*!< SPI I2S control register */
|
#define SPI_I2SCTL(spix) REG32((spix) + 0x0000001CU) /*!< SPI I2S control register */
|
||||||
#define SPI_I2SPSC(spix) REG32((spix) + 0x20U) /*!< SPI I2S clock prescaler register */
|
#define SPI_I2SPSC(spix) REG32((spix) + 0x00000020U) /*!< SPI I2S clock prescaler register */
|
||||||
#define SPI_QCTL(spix) REG32((spix) + 0x80U) /*!< SPI quad mode control register */
|
#define SPI_QCTL(spix) REG32((spix) + 0x00000080U) /*!< SPI quad mode control register */
|
||||||
|
|
||||||
/* I2S_ADD registers definitions */
|
/* I2S_ADD registers definitions */
|
||||||
#define I2S_ADD_CTL0(i2sx_add) REG32((i2sx_add) + 0x00U) /*!< I2S_ADD control register 0 */
|
#define I2S_ADD_CTL0(i2sx_add) REG32((i2sx_add) + 0x00000000U) /*!< I2S_ADD control register 0 */
|
||||||
#define I2S_ADD_CTL1(i2sx_add) REG32((i2sx_add) + 0x04U) /*!< I2S_ADD control register 1*/
|
#define I2S_ADD_CTL1(i2sx_add) REG32((i2sx_add) + 0x00000004U) /*!< I2S_ADD control register 1*/
|
||||||
#define I2S_ADD_STAT(i2sx_add) REG32((i2sx_add) + 0x08U) /*!< I2S_ADD status register */
|
#define I2S_ADD_STAT(i2sx_add) REG32((i2sx_add) + 0x00000008U) /*!< I2S_ADD status register */
|
||||||
#define I2S_ADD_DATA(i2sx_add) REG32((i2sx_add) + 0x0CU) /*!< I2S_ADD data register */
|
#define I2S_ADD_DATA(i2sx_add) REG32((i2sx_add) + 0x0000000CU) /*!< I2S_ADD data register */
|
||||||
#define I2S_ADD_CRCPOLY(i2sx_add) REG32((i2sx_add) + 0x10U) /*!< I2S_ADD CRC polynomial register */
|
#define I2S_ADD_CRCPOLY(i2sx_add) REG32((i2sx_add) + 0x00000010U) /*!< I2S_ADD CRC polynomial register */
|
||||||
#define I2S_ADD_RCRC(i2sx_add) REG32((i2sx_add) + 0x14U) /*!< I2S_ADD receive CRC register */
|
#define I2S_ADD_RCRC(i2sx_add) REG32((i2sx_add) + 0x00000014U) /*!< I2S_ADD receive CRC register */
|
||||||
#define I2S_ADD_TCRC(i2sx_add) REG32((i2sx_add) + 0x18U) /*!< I2S_ADD transmit CRC register */
|
#define I2S_ADD_TCRC(i2sx_add) REG32((i2sx_add) + 0x00000018U) /*!< I2S_ADD transmit CRC register */
|
||||||
#define I2S_ADD_I2SCTL(i2sx_add) REG32((i2sx_add) + 0x1CU) /*!< I2S_ADD I2S control register */
|
#define I2S_ADD_I2SCTL(i2sx_add) REG32((i2sx_add) + 0x0000001CU) /*!< I2S_ADD I2S control register */
|
||||||
#define I2S_ADD_I2SPSC(i2sx_add) REG32((i2sx_add) + 0x20U) /*!< I2S_ADD I2S clock prescaler register */
|
#define I2S_ADD_I2SPSC(i2sx_add) REG32((i2sx_add) + 0x00000020U) /*!< I2S_ADD I2S clock prescaler register */
|
||||||
|
|
||||||
/* bits definitions */
|
/* bits definitions */
|
||||||
/* SPI_CTL0 */
|
/* SPI_CTL0 */
|
||||||
|
|
@ -146,8 +147,7 @@ OF SUCH DAMAGE.
|
||||||
|
|
||||||
/* constants definitions */
|
/* constants definitions */
|
||||||
/* SPI and I2S parameter struct definitions */
|
/* SPI and I2S parameter struct definitions */
|
||||||
typedef struct
|
typedef struct {
|
||||||
{
|
|
||||||
uint32_t device_mode; /*!< SPI master or slave */
|
uint32_t device_mode; /*!< SPI master or slave */
|
||||||
uint32_t trans_mode; /*!< SPI transtype */
|
uint32_t trans_mode; /*!< SPI transtype */
|
||||||
uint32_t frame_size; /*!< SPI frame size */
|
uint32_t frame_size; /*!< SPI frame size */
|
||||||
|
|
@ -283,7 +283,7 @@ typedef struct
|
||||||
/* initialization functions */
|
/* initialization functions */
|
||||||
/* deinitialize SPI and I2S */
|
/* deinitialize SPI and I2S */
|
||||||
void spi_i2s_deinit(uint32_t spi_periph);
|
void spi_i2s_deinit(uint32_t spi_periph);
|
||||||
/* initialize the parameters of SPI struct with the default values */
|
/* initialize the parameters of SPI struct with default values */
|
||||||
void spi_struct_para_init(spi_parameter_struct *spi_struct);
|
void spi_struct_para_init(spi_parameter_struct *spi_struct);
|
||||||
/* initialize SPI parameter */
|
/* initialize SPI parameter */
|
||||||
void spi_init(uint32_t spi_periph, spi_parameter_struct *spi_struct);
|
void spi_init(uint32_t spi_periph, spi_parameter_struct *spi_struct);
|
||||||
|
|
@ -312,9 +312,9 @@ void spi_nss_internal_high(uint32_t spi_periph);
|
||||||
void spi_nss_internal_low(uint32_t spi_periph);
|
void spi_nss_internal_low(uint32_t spi_periph);
|
||||||
|
|
||||||
/* SPI DMA functions */
|
/* SPI DMA functions */
|
||||||
/* enable SPI DMA */
|
/* enable SPI DMA send or receive */
|
||||||
void spi_dma_enable(uint32_t spi_periph, uint8_t spi_dma);
|
void spi_dma_enable(uint32_t spi_periph, uint8_t spi_dma);
|
||||||
/* disable SPI DMA */
|
/* diable SPI DMA send or receive */
|
||||||
void spi_dma_disable(uint32_t spi_periph, uint8_t spi_dma);
|
void spi_dma_disable(uint32_t spi_periph, uint8_t spi_dma);
|
||||||
|
|
||||||
/* SPI/I2S transfer configure functions */
|
/* SPI/I2S transfer configure functions */
|
||||||
|
|
@ -326,6 +326,10 @@ void spi_i2s_data_transmit(uint32_t spi_periph,uint16_t data);
|
||||||
uint16_t spi_i2s_data_receive(uint32_t spi_periph);
|
uint16_t spi_i2s_data_receive(uint32_t spi_periph);
|
||||||
/* configure SPI bidirectional transfer direction */
|
/* configure SPI bidirectional transfer direction */
|
||||||
void spi_bidirectional_transfer_config(uint32_t spi_periph, uint32_t transfer_direction);
|
void spi_bidirectional_transfer_config(uint32_t spi_periph, uint32_t transfer_direction);
|
||||||
|
/* configure i2s full duplex mode */
|
||||||
|
void i2s_full_duplex_mode_config(uint32_t i2s_add_periph, uint32_t i2s_mode, uint32_t i2s_standard, uint32_t i2s_ckpl, uint32_t i2s_frameformat);
|
||||||
|
/* clear TI Mode Format Error flag status */
|
||||||
|
void spi_i2s_format_error_clear(uint32_t spi_periph, uint32_t flag);
|
||||||
|
|
||||||
/* SPI CRC functions */
|
/* SPI CRC functions */
|
||||||
/* set SPI CRC polynomial */
|
/* set SPI CRC polynomial */
|
||||||
|
|
@ -340,6 +344,8 @@ void spi_crc_off(uint32_t spi_periph);
|
||||||
void spi_crc_next(uint32_t spi_periph);
|
void spi_crc_next(uint32_t spi_periph);
|
||||||
/* get SPI CRC send value or receive value */
|
/* get SPI CRC send value or receive value */
|
||||||
uint16_t spi_crc_get(uint32_t spi_periph, uint8_t spi_crc);
|
uint16_t spi_crc_get(uint32_t spi_periph, uint8_t spi_crc);
|
||||||
|
/* clear SPI CRC error flag status */
|
||||||
|
void spi_crc_error_clear(uint32_t spi_periph);
|
||||||
|
|
||||||
/* SPI TI mode functions */
|
/* SPI TI mode functions */
|
||||||
/* enable SPI TI mode */
|
/* enable SPI TI mode */
|
||||||
|
|
@ -347,33 +353,28 @@ void spi_ti_mode_enable(uint32_t spi_periph);
|
||||||
/* disable SPI TI mode */
|
/* disable SPI TI mode */
|
||||||
void spi_ti_mode_disable(uint32_t spi_periph);
|
void spi_ti_mode_disable(uint32_t spi_periph);
|
||||||
|
|
||||||
/* configure i2s full duplex mode */
|
|
||||||
void i2s_full_duplex_mode_config(uint32_t i2s_add_periph,uint32_t i2s_mode,uint32_t i2s_standard,uint32_t i2s_ckpl,uint32_t i2s_frameformat);
|
|
||||||
|
|
||||||
/* quad wire SPI functions */
|
/* quad wire SPI functions */
|
||||||
/* enable quad wire SPI */
|
/* enable quad wire SPI */
|
||||||
void qspi_enable(uint32_t spi_periph);
|
void spi_quad_enable(uint32_t spi_periph);
|
||||||
/* disable quad wire SPI */
|
/* disable quad wire SPI */
|
||||||
void qspi_disable(uint32_t spi_periph);
|
void spi_quad_disable(uint32_t spi_periph);
|
||||||
/* enable quad wire SPI write */
|
/* enable quad wire SPI write */
|
||||||
void qspi_write_enable(uint32_t spi_periph);
|
void spi_quad_write_enable(uint32_t spi_periph);
|
||||||
/* enable quad wire SPI read */
|
/* enable quad wire SPI read */
|
||||||
void qspi_read_enable(uint32_t spi_periph);
|
void spi_quad_read_enable(uint32_t spi_periph);
|
||||||
/* enable quad wire SPI_IO2 and SPI_IO3 pin output */
|
/* enable SPI_IO2 and SPI_IO3 pin output */
|
||||||
void qspi_io23_output_enable(uint32_t spi_periph);
|
void spi_quad_io23_output_enable(uint32_t spi_periph);
|
||||||
/* disable quad wire SPI_IO2 and SPI_IO3 pin output */
|
/* disable SPI_IO2 and SPI_IO3 pin output */
|
||||||
void qspi_io23_output_disable(uint32_t spi_periph);
|
void spi_quad_io23_output_disable(uint32_t spi_periph);
|
||||||
|
|
||||||
/* flag & interrupt functions */
|
/* flag and interrupt functions */
|
||||||
/* enable SPI interrupt */
|
|
||||||
void spi_i2s_interrupt_enable(uint32_t spi_periph,uint8_t spi_i2s_int);
|
|
||||||
/* disable SPI interrupt */
|
|
||||||
void spi_i2s_interrupt_disable(uint32_t spi_periph,uint8_t spi_i2s_int);
|
|
||||||
/* get SPI and I2S interrupt status*/
|
|
||||||
FlagStatus spi_i2s_interrupt_flag_get(uint32_t spi_periph,uint8_t spi_i2s_int);
|
|
||||||
/* get SPI and I2S flag status */
|
/* get SPI and I2S flag status */
|
||||||
FlagStatus spi_i2s_flag_get(uint32_t spi_periph,uint32_t spi_i2s_flag);
|
FlagStatus spi_i2s_flag_get(uint32_t spi_periph, uint32_t flag);
|
||||||
/* clear SPI CRC error flag status */
|
/* enable SPI and I2S interrupt */
|
||||||
void spi_crc_error_clear(uint32_t spi_periph);
|
void spi_i2s_interrupt_enable(uint32_t spi_periph, uint8_t interrupt);
|
||||||
|
/* disable SPI and I2S interrupt */
|
||||||
|
void spi_i2s_interrupt_disable(uint32_t spi_periph, uint8_t interrupt);
|
||||||
|
/* get SPI and I2S interrupt status*/
|
||||||
|
FlagStatus spi_i2s_interrupt_flag_get(uint32_t spi_periph, uint8_t interrupt);
|
||||||
|
|
||||||
#endif /* GD32F4XX_SPI_H */
|
#endif /* GD32F4XX_SPI_H */
|
||||||
|
|
|
||||||
|
|
@ -5,10 +5,11 @@
|
||||||
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
||||||
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
||||||
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
||||||
|
\version 2022-03-09, V3.0.0, firmware for GD32F4xx
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/*
|
/*
|
||||||
Copyright (c) 2020, GigaDevice Semiconductor Inc.
|
Copyright (c) 2022, GigaDevice Semiconductor Inc.
|
||||||
|
|
||||||
Redistribution and use in source and binary forms, with or without modification,
|
Redistribution and use in source and binary forms, with or without modification,
|
||||||
are permitted provided that the following conditions are met:
|
are permitted provided that the following conditions are met:
|
||||||
|
|
|
||||||
|
|
@ -5,11 +5,11 @@
|
||||||
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
||||||
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
||||||
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
||||||
|
\version 2022-03-09, V3.0.0, firmware for GD32F4xx
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/*
|
/*
|
||||||
Copyright (c) 2020, GigaDevice Semiconductor Inc.
|
Copyright (c) 2022, GigaDevice Semiconductor Inc.
|
||||||
All rights reserved.
|
|
||||||
|
|
||||||
Redistribution and use in source and binary forms, with or without modification,
|
Redistribution and use in source and binary forms, with or without modification,
|
||||||
are permitted provided that the following conditions are met:
|
are permitted provided that the following conditions are met:
|
||||||
|
|
@ -341,8 +341,6 @@ typedef struct
|
||||||
#define TIMER_INT_FLAG_TRG TIMER_INTF_TRGIF /*!< trigger interrupt flag */
|
#define TIMER_INT_FLAG_TRG TIMER_INTF_TRGIF /*!< trigger interrupt flag */
|
||||||
#define TIMER_INT_FLAG_BRK TIMER_INTF_BRKIF
|
#define TIMER_INT_FLAG_BRK TIMER_INTF_BRKIF
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
/* TIMER DMA source enable */
|
/* TIMER DMA source enable */
|
||||||
#define TIMER_DMA_UPD ((uint16_t)TIMER_DMAINTEN_UPDEN) /*!< update DMA enable */
|
#define TIMER_DMA_UPD ((uint16_t)TIMER_DMAINTEN_UPDEN) /*!< update DMA enable */
|
||||||
#define TIMER_DMA_CH0D ((uint16_t)TIMER_DMAINTEN_CH0DEN) /*!< channel 0 DMA enable */
|
#define TIMER_DMA_CH0D ((uint16_t)TIMER_DMAINTEN_CH0DEN) /*!< channel 0 DMA enable */
|
||||||
|
|
@ -563,9 +561,9 @@ typedef struct
|
||||||
/* slave mode control */
|
/* slave mode control */
|
||||||
#define SMCFG_SMC(regval) (BITS(0, 2) & ((uint32_t)(regval) << 0U))
|
#define SMCFG_SMC(regval) (BITS(0, 2) & ((uint32_t)(regval) << 0U))
|
||||||
#define TIMER_SLAVE_MODE_DISABLE SMCFG_SMC(0) /*!< slave mode disable */
|
#define TIMER_SLAVE_MODE_DISABLE SMCFG_SMC(0) /*!< slave mode disable */
|
||||||
#define TIMER_ENCODER_MODE0 SMCFG_SMC(1) /*!< encoder mode 0 */
|
#define TIMER_QUAD_DECODER_MODE0 SMCFG_SMC(1) /*!< quadrature decoder mode 0 */
|
||||||
#define TIMER_ENCODER_MODE1 SMCFG_SMC(2) /*!< encoder mode 1 */
|
#define TIMER_QUAD_DECODER_MODE1 SMCFG_SMC(2) /*!< quadrature decoder mode 1 */
|
||||||
#define TIMER_ENCODER_MODE2 SMCFG_SMC(3) /*!< encoder mode 2 */
|
#define TIMER_QUAD_DECODER_MODE2 SMCFG_SMC(3) /*!< quadrature decoder mode 2 */
|
||||||
#define TIMER_SLAVE_MODE_RESTART SMCFG_SMC(4) /*!< restart mode */
|
#define TIMER_SLAVE_MODE_RESTART SMCFG_SMC(4) /*!< restart mode */
|
||||||
#define TIMER_SLAVE_MODE_PAUSE SMCFG_SMC(5) /*!< pause mode */
|
#define TIMER_SLAVE_MODE_PAUSE SMCFG_SMC(5) /*!< pause mode */
|
||||||
#define TIMER_SLAVE_MODE_EVENT SMCFG_SMC(6) /*!< event mode */
|
#define TIMER_SLAVE_MODE_EVENT SMCFG_SMC(6) /*!< event mode */
|
||||||
|
|
@ -660,20 +658,6 @@ void timer_single_pulse_mode_config(uint32_t timer_periph, uint32_t spmode);
|
||||||
/* configure TIMER update source */
|
/* configure TIMER update source */
|
||||||
void timer_update_source_config(uint32_t timer_periph, uint32_t update);
|
void timer_update_source_config(uint32_t timer_periph, uint32_t update);
|
||||||
|
|
||||||
/* TIMER interrupt and flag*/
|
|
||||||
/* enable the TIMER interrupt */
|
|
||||||
void timer_interrupt_enable(uint32_t timer_periph, uint32_t interrupt);
|
|
||||||
/* disable the TIMER interrupt */
|
|
||||||
void timer_interrupt_disable(uint32_t timer_periph, uint32_t interrupt);
|
|
||||||
/* get timer interrupt flag */
|
|
||||||
FlagStatus timer_interrupt_flag_get(uint32_t timer_periph, uint32_t interrupt);
|
|
||||||
/* clear TIMER interrupt flag */
|
|
||||||
void timer_interrupt_flag_clear(uint32_t timer_periph, uint32_t interrupt);
|
|
||||||
/* get TIMER flags */
|
|
||||||
FlagStatus timer_flag_get(uint32_t timer_periph, uint32_t flag);
|
|
||||||
/* clear TIMER flags */
|
|
||||||
void timer_flag_clear(uint32_t timer_periph, uint32_t flag);
|
|
||||||
|
|
||||||
/* timer DMA and event*/
|
/* timer DMA and event*/
|
||||||
/* enable the TIMER DMA */
|
/* enable the TIMER DMA */
|
||||||
void timer_dma_enable(uint32_t timer_periph, uint16_t dma);
|
void timer_dma_enable(uint32_t timer_periph, uint16_t dma);
|
||||||
|
|
@ -778,4 +762,18 @@ void timer_write_chxval_register_config(uint32_t timer_periph, uint16_t ccsel);
|
||||||
/* configure TIMER output value selection */
|
/* configure TIMER output value selection */
|
||||||
void timer_output_value_selection_config(uint32_t timer_periph, uint16_t outsel);
|
void timer_output_value_selection_config(uint32_t timer_periph, uint16_t outsel);
|
||||||
|
|
||||||
|
/* TIMER interrupt and flag*/
|
||||||
|
/* get TIMER flags */
|
||||||
|
FlagStatus timer_flag_get(uint32_t timer_periph, uint32_t flag);
|
||||||
|
/* clear TIMER flags */
|
||||||
|
void timer_flag_clear(uint32_t timer_periph, uint32_t flag);
|
||||||
|
/* enable the TIMER interrupt */
|
||||||
|
void timer_interrupt_enable(uint32_t timer_periph, uint32_t interrupt);
|
||||||
|
/* disable the TIMER interrupt */
|
||||||
|
void timer_interrupt_disable(uint32_t timer_periph, uint32_t interrupt);
|
||||||
|
/* get timer interrupt flag */
|
||||||
|
FlagStatus timer_interrupt_flag_get(uint32_t timer_periph, uint32_t interrupt);
|
||||||
|
/* clear TIMER interrupt flag */
|
||||||
|
void timer_interrupt_flag_clear(uint32_t timer_periph, uint32_t interrupt);
|
||||||
|
|
||||||
#endif /* GD32F4XX_TIMER_H */
|
#endif /* GD32F4XX_TIMER_H */
|
||||||
|
|
|
||||||
|
|
@ -5,10 +5,11 @@
|
||||||
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
||||||
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
||||||
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
||||||
|
\version 2022-03-09, V3.0.0, firmware for GD32F4xx
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/*
|
/*
|
||||||
Copyright (c) 2020, GigaDevice Semiconductor Inc.
|
Copyright (c) 2022, GigaDevice Semiconductor Inc.
|
||||||
|
|
||||||
Redistribution and use in source and binary forms, with or without modification,
|
Redistribution and use in source and binary forms, with or without modification,
|
||||||
are permitted provided that the following conditions are met:
|
are permitted provided that the following conditions are met:
|
||||||
|
|
@ -43,34 +44,34 @@ OF SUCH DAMAGE.
|
||||||
#define TLI TLI_BASE /*!< TLI base address */
|
#define TLI TLI_BASE /*!< TLI base address */
|
||||||
/* TLI layer definitions */
|
/* TLI layer definitions */
|
||||||
#define LAYER0 TLI_BASE /*!< TLI layer0 base address */
|
#define LAYER0 TLI_BASE /*!< TLI layer0 base address */
|
||||||
#define LAYER1 (TLI_BASE+0x80) /*!< TLI layer1 base address */
|
#define LAYER1 (TLI_BASE + 0x00000080U) /*!< TLI layer1 base address */
|
||||||
|
|
||||||
/* registers definitions */
|
/* registers definitions */
|
||||||
#define TLI_SPSZ REG32(TLI + 0x08U) /*!< TLI synchronous pulse size register */
|
#define TLI_SPSZ REG32(TLI + 0x00000008U) /*!< TLI synchronous pulse size register */
|
||||||
#define TLI_BPSZ REG32(TLI + 0x0CU) /*!< TLI back-porch size register */
|
#define TLI_BPSZ REG32(TLI + 0x0000000CU) /*!< TLI back-porch size register */
|
||||||
#define TLI_ASZ REG32(TLI + 0x10U) /*!< TLI active size register */
|
#define TLI_ASZ REG32(TLI + 0x00000010U) /*!< TLI active size register */
|
||||||
#define TLI_TSZ REG32(TLI + 0x14U) /*!< TLI total size register */
|
#define TLI_TSZ REG32(TLI + 0x00000014U) /*!< TLI total size register */
|
||||||
#define TLI_CTL REG32(TLI + 0x18U) /*!< TLI control register */
|
#define TLI_CTL REG32(TLI + 0x00000018U) /*!< TLI control register */
|
||||||
#define TLI_RL REG32(TLI + 0x24U) /*!< TLI reload Layer register */
|
#define TLI_RL REG32(TLI + 0x00000024U) /*!< TLI reload Layer register */
|
||||||
#define TLI_BGC REG32(TLI + 0x2CU) /*!< TLI background color register */
|
#define TLI_BGC REG32(TLI + 0x0000002CU) /*!< TLI background color register */
|
||||||
#define TLI_INTEN REG32(TLI + 0x34U) /*!< TLI interrupt enable register */
|
#define TLI_INTEN REG32(TLI + 0x00000034U) /*!< TLI interrupt enable register */
|
||||||
#define TLI_INTF REG32(TLI + 0x38U) /*!< TLI interrupt flag register */
|
#define TLI_INTF REG32(TLI + 0x00000038U) /*!< TLI interrupt flag register */
|
||||||
#define TLI_INTC REG32(TLI + 0x3CU) /*!< TLI interrupt flag clear register */
|
#define TLI_INTC REG32(TLI + 0x0000003CU) /*!< TLI interrupt flag clear register */
|
||||||
#define TLI_LM REG32(TLI + 0x40U) /*!< TLI line mark register */
|
#define TLI_LM REG32(TLI + 0x00000040U) /*!< TLI line mark register */
|
||||||
#define TLI_CPPOS REG32(TLI + 0x44U) /*!< TLI current pixel position register */
|
#define TLI_CPPOS REG32(TLI + 0x00000044U) /*!< TLI current pixel position register */
|
||||||
#define TLI_STAT REG32(TLI + 0x48U) /*!< TLI status register */
|
#define TLI_STAT REG32(TLI + 0x00000048U) /*!< TLI status register */
|
||||||
#define TLI_LxCTL(layerx) REG32((layerx) + 0x84U) /*!< TLI layer x control register */
|
#define TLI_LxCTL(layerx) REG32((layerx) + 0x00000084U) /*!< TLI layer x control register */
|
||||||
#define TLI_LxHPOS(layerx) REG32((layerx) + 0x88U) /*!< TLI layer x horizontal position parameters register */
|
#define TLI_LxHPOS(layerx) REG32((layerx) + 0x00000088U) /*!< TLI layer x horizontal position parameters register */
|
||||||
#define TLI_LxVPOS(layerx) REG32((layerx) + 0x8CU) /*!< TLI layer x vertical position parameters register */
|
#define TLI_LxVPOS(layerx) REG32((layerx) + 0x0000008CU) /*!< TLI layer x vertical position parameters register */
|
||||||
#define TLI_LxCKEY(layerx) REG32((layerx) + 0x90U) /*!< TLI layer x color key register */
|
#define TLI_LxCKEY(layerx) REG32((layerx) + 0x00000090U) /*!< TLI layer x color key register */
|
||||||
#define TLI_LxPPF(layerx) REG32((layerx) + 0x94U) /*!< TLI layer x packeted pixel format register */
|
#define TLI_LxPPF(layerx) REG32((layerx) + 0x00000094U) /*!< TLI layer x packeted pixel format register */
|
||||||
#define TLI_LxSA(layerx) REG32((layerx) + 0x98U) /*!< TLI layer x specified alpha register */
|
#define TLI_LxSA(layerx) REG32((layerx) + 0x00000098U) /*!< TLI layer x specified alpha register */
|
||||||
#define TLI_LxDC(layerx) REG32((layerx) + 0x9CU) /*!< TLI layer x default color register */
|
#define TLI_LxDC(layerx) REG32((layerx) + 0x0000009CU) /*!< TLI layer x default color register */
|
||||||
#define TLI_LxBLEND(layerx) REG32((layerx) + 0xA0U) /*!< TLI layer x blending register */
|
#define TLI_LxBLEND(layerx) REG32((layerx) + 0x000000A0U) /*!< TLI layer x blending register */
|
||||||
#define TLI_LxFBADDR(layerx) REG32((layerx) + 0xACU) /*!< TLI layer x frame base address register */
|
#define TLI_LxFBADDR(layerx) REG32((layerx) + 0x000000ACU) /*!< TLI layer x frame base address register */
|
||||||
#define TLI_LxFLLEN(layerx) REG32((layerx) + 0xB0U) /*!< TLI layer x frame line length register */
|
#define TLI_LxFLLEN(layerx) REG32((layerx) + 0x000000B0U) /*!< TLI layer x frame line length register */
|
||||||
#define TLI_LxFTLN(layerx) REG32((layerx) + 0xB4U) /*!< TLI layer x frame total line number register */
|
#define TLI_LxFTLN(layerx) REG32((layerx) + 0x000000B4U) /*!< TLI layer x frame total line number register */
|
||||||
#define TLI_LxLUT(layerx) REG32((layerx) + 0xC4U) /*!< TLI layer x look up table register */
|
#define TLI_LxLUT(layerx) REG32((layerx) + 0x000000C4U) /*!< TLI layer x look up table register */
|
||||||
|
|
||||||
/* bits definitions */
|
/* bits definitions */
|
||||||
/* TLI_SPSZ */
|
/* TLI_SPSZ */
|
||||||
|
|
@ -192,8 +193,7 @@ OF SUCH DAMAGE.
|
||||||
|
|
||||||
/* constants definitions */
|
/* constants definitions */
|
||||||
/* TLI parameter struct definitions */
|
/* TLI parameter struct definitions */
|
||||||
typedef struct
|
typedef struct {
|
||||||
{
|
|
||||||
uint16_t synpsz_vpsz; /*!< size of the vertical synchronous pulse */
|
uint16_t synpsz_vpsz; /*!< size of the vertical synchronous pulse */
|
||||||
uint16_t synpsz_hpsz; /*!< size of the horizontal synchronous pulse */
|
uint16_t synpsz_hpsz; /*!< size of the horizontal synchronous pulse */
|
||||||
uint16_t backpsz_vbpsz; /*!< size of the vertical back porch plus synchronous pulse */
|
uint16_t backpsz_vbpsz; /*!< size of the vertical back porch plus synchronous pulse */
|
||||||
|
|
@ -212,8 +212,7 @@ typedef struct
|
||||||
} tli_parameter_struct;
|
} tli_parameter_struct;
|
||||||
|
|
||||||
/* TLI layer parameter struct definitions */
|
/* TLI layer parameter struct definitions */
|
||||||
typedef struct
|
typedef struct {
|
||||||
{
|
|
||||||
uint16_t layer_window_rightpos; /*!< window right position */
|
uint16_t layer_window_rightpos; /*!< window right position */
|
||||||
uint16_t layer_window_leftpos; /*!< window left position */
|
uint16_t layer_window_leftpos; /*!< window left position */
|
||||||
uint16_t layer_window_bottompos; /*!< window bottom position */
|
uint16_t layer_window_bottompos; /*!< window bottom position */
|
||||||
|
|
@ -233,8 +232,7 @@ typedef struct
|
||||||
} tli_layer_parameter_struct;
|
} tli_layer_parameter_struct;
|
||||||
|
|
||||||
/* TLI layer LUT parameter struct definitions */
|
/* TLI layer LUT parameter struct definitions */
|
||||||
typedef struct
|
typedef struct {
|
||||||
{
|
|
||||||
uint32_t layer_table_addr; /*!< look up table write address */
|
uint32_t layer_table_addr; /*!< look up table write address */
|
||||||
uint8_t layer_lut_channel_red; /*!< red channel of a LUT entry */
|
uint8_t layer_lut_channel_red; /*!< red channel of a LUT entry */
|
||||||
uint8_t layer_lut_channel_green; /*!< green channel of a LUT entry */
|
uint8_t layer_lut_channel_green; /*!< green channel of a LUT entry */
|
||||||
|
|
@ -242,8 +240,7 @@ typedef struct
|
||||||
} tli_layer_lut_parameter_struct;
|
} tli_layer_lut_parameter_struct;
|
||||||
|
|
||||||
/* packeted pixel format */
|
/* packeted pixel format */
|
||||||
typedef enum
|
typedef enum {
|
||||||
{
|
|
||||||
LAYER_PPF_ARGB8888, /*!< layerx pixel format ARGB8888 */
|
LAYER_PPF_ARGB8888, /*!< layerx pixel format ARGB8888 */
|
||||||
LAYER_PPF_RGB888, /*!< layerx pixel format RGB888 */
|
LAYER_PPF_RGB888, /*!< layerx pixel format RGB888 */
|
||||||
LAYER_PPF_RGB565, /*!< layerx pixel format RGB565 */
|
LAYER_PPF_RGB565, /*!< layerx pixel format RGB565 */
|
||||||
|
|
|
||||||
|
|
@ -5,10 +5,11 @@
|
||||||
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
||||||
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
||||||
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
||||||
|
\version 2022-03-09, V3.0.0, firmware for GD32F4xx
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/*
|
/*
|
||||||
Copyright (c) 2020, GigaDevice Semiconductor Inc.
|
Copyright (c) 2022, GigaDevice Semiconductor Inc.
|
||||||
|
|
||||||
Redistribution and use in source and binary forms, with or without modification,
|
Redistribution and use in source and binary forms, with or without modification,
|
||||||
are permitted provided that the following conditions are met:
|
are permitted provided that the following conditions are met:
|
||||||
|
|
@ -43,14 +44,14 @@ OF SUCH DAMAGE.
|
||||||
#define TRNG TRNG_BASE
|
#define TRNG TRNG_BASE
|
||||||
|
|
||||||
/* registers definitions */
|
/* registers definitions */
|
||||||
#define TRNG_CTL REG32(TRNG + 0x00U) /*!< control register */
|
#define TRNG_CTL REG32(TRNG + 0x00000000U) /*!< control register */
|
||||||
#define TRNG_STAT REG32(TRNG + 0x04U) /*!< status register */
|
#define TRNG_STAT REG32(TRNG + 0x00000004U) /*!< status register */
|
||||||
#define TRNG_DATA REG32(TRNG + 0x08U) /*!< data register */
|
#define TRNG_DATA REG32(TRNG + 0x00000008U) /*!< data register */
|
||||||
|
|
||||||
/* bits definitions */
|
/* bits definitions */
|
||||||
/* TRNG_CTL */
|
/* TRNG_CTL */
|
||||||
#define TRNG_CTL_TRNGEN BIT(2) /*!< TRNG enable bit */
|
#define TRNG_CTL_TRNGEN BIT(2) /*!< TRNG enable bit */
|
||||||
#define TRNG_CTL_IE BIT(3) /*!< interrupt enable bit */
|
#define TRNG_CTL_TRNGIE BIT(3) /*!< interrupt enable bit */
|
||||||
|
|
||||||
/* TRNG_STAT */
|
/* TRNG_STAT */
|
||||||
#define TRNG_STAT_DRDY BIT(0) /*!< random data ready status bit */
|
#define TRNG_STAT_DRDY BIT(0) /*!< random data ready status bit */
|
||||||
|
|
@ -60,45 +61,43 @@ OF SUCH DAMAGE.
|
||||||
#define TRNG_STAT_SEIF BIT(6) /*!< seed error interrupt flag */
|
#define TRNG_STAT_SEIF BIT(6) /*!< seed error interrupt flag */
|
||||||
|
|
||||||
/* TRNG_DATA */
|
/* TRNG_DATA */
|
||||||
#define TRNG_DATA_TRNDATA BITS(0,31) /*!< 32-Bit Random data */
|
#define TRNG_DATA_TRNGDATA BITS(0,31) /*!< 32-Bit Random data */
|
||||||
|
|
||||||
/* constants definitions */
|
/* constants definitions */
|
||||||
/* trng status flag */
|
/* TRNG status flag */
|
||||||
typedef enum
|
typedef enum {
|
||||||
{
|
|
||||||
TRNG_FLAG_DRDY = TRNG_STAT_DRDY, /*!< random Data ready status */
|
TRNG_FLAG_DRDY = TRNG_STAT_DRDY, /*!< random Data ready status */
|
||||||
TRNG_FLAG_CECS = TRNG_STAT_CECS, /*!< clock error current status */
|
TRNG_FLAG_CECS = TRNG_STAT_CECS, /*!< clock error current status */
|
||||||
TRNG_FLAG_SECS = TRNG_STAT_SECS /*!< seed error current status */
|
TRNG_FLAG_SECS = TRNG_STAT_SECS /*!< seed error current status */
|
||||||
} trng_flag_enum;
|
} trng_flag_enum;
|
||||||
|
|
||||||
/* trng inerrupt flag */
|
/* TRNG inerrupt flag */
|
||||||
typedef enum
|
typedef enum {
|
||||||
{
|
|
||||||
TRNG_INT_FLAG_CEIF = TRNG_STAT_CEIF, /*!< clock error interrupt flag */
|
TRNG_INT_FLAG_CEIF = TRNG_STAT_CEIF, /*!< clock error interrupt flag */
|
||||||
TRNG_INT_FLAG_SEIF = TRNG_STAT_SEIF /*!< seed error interrupt flag */
|
TRNG_INT_FLAG_SEIF = TRNG_STAT_SEIF /*!< seed error interrupt flag */
|
||||||
} trng_int_flag_enum;
|
} trng_int_flag_enum;
|
||||||
|
|
||||||
/* function declarations */
|
/* function declarations */
|
||||||
/* initialization functions */
|
/* initialization functions */
|
||||||
/* deinitialize the TRNG */
|
/* reset TRNG */
|
||||||
void trng_deinit(void);
|
void trng_deinit(void);
|
||||||
/* enable the TRNG interface */
|
/* enable TRNG */
|
||||||
void trng_enable(void);
|
void trng_enable(void);
|
||||||
/* disable the TRNG interface */
|
/* disable TRNG */
|
||||||
void trng_disable(void);
|
void trng_disable(void);
|
||||||
/* get the true random data */
|
/* get the true random data */
|
||||||
uint32_t trng_get_true_random_data(void);
|
uint32_t trng_get_true_random_data(void);
|
||||||
|
|
||||||
/* flag & interrupt functions */
|
/* interrupt & flag functions */
|
||||||
/* trng interrupt enable */
|
/* enable TRNG interrupt */
|
||||||
void trng_interrupt_enable(void);
|
void trng_interrupt_enable(void);
|
||||||
/* trng interrupt disable */
|
/* disable TRNG interrupt */
|
||||||
void trng_interrupt_disable(void);
|
void trng_interrupt_disable(void);
|
||||||
/* get the trng status flags */
|
/* get TRNG flag status */
|
||||||
FlagStatus trng_flag_get(trng_flag_enum flag);
|
FlagStatus trng_flag_get(trng_flag_enum flag);
|
||||||
/* get the trng interrupt flags */
|
/* get TRNG interrupt flag status */
|
||||||
FlagStatus trng_interrupt_flag_get(trng_int_flag_enum int_flag);
|
FlagStatus trng_interrupt_flag_get(trng_int_flag_enum int_flag);
|
||||||
/* clear the trng interrupt flags */
|
/* clear TRNG interrupt flag status */
|
||||||
void trng_interrupt_flag_clear(trng_int_flag_enum int_flag);
|
void trng_interrupt_flag_clear(trng_int_flag_enum int_flag);
|
||||||
|
|
||||||
#endif /* GD32F4XX_TRNG_H */
|
#endif /* GD32F4XX_TRNG_H */
|
||||||
|
|
|
||||||
|
|
@ -5,10 +5,11 @@
|
||||||
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
||||||
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
||||||
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
||||||
|
\version 2022-03-09, V3.0.0, firmware for GD32F4xx
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/*
|
/*
|
||||||
Copyright (c) 2020, GigaDevice Semiconductor Inc.
|
Copyright (c) 2022, GigaDevice Semiconductor Inc.
|
||||||
|
|
||||||
Redistribution and use in source and binary forms, with or without modification,
|
Redistribution and use in source and binary forms, with or without modification,
|
||||||
are permitted provided that the following conditions are met:
|
are permitted provided that the following conditions are met:
|
||||||
|
|
@ -85,43 +86,43 @@ OF SUCH DAMAGE.
|
||||||
/* USARTx_CTL0 */
|
/* USARTx_CTL0 */
|
||||||
#define USART_CTL0_SBKCMD BIT(0) /*!< send break command */
|
#define USART_CTL0_SBKCMD BIT(0) /*!< send break command */
|
||||||
#define USART_CTL0_RWU BIT(1) /*!< receiver wakeup from mute mode */
|
#define USART_CTL0_RWU BIT(1) /*!< receiver wakeup from mute mode */
|
||||||
#define USART_CTL0_REN BIT(2) /*!< receiver enable */
|
#define USART_CTL0_REN BIT(2) /*!< enable receiver */
|
||||||
#define USART_CTL0_TEN BIT(3) /*!< transmitter enable */
|
#define USART_CTL0_TEN BIT(3) /*!< enable transmitter */
|
||||||
#define USART_CTL0_IDLEIE BIT(4) /*!< idle line detected interrupt enable */
|
#define USART_CTL0_IDLEIE BIT(4) /*!< enable idle line detected interrupt */
|
||||||
#define USART_CTL0_RBNEIE BIT(5) /*!< read data buffer not empty interrupt and overrun error interrupt enable */
|
#define USART_CTL0_RBNEIE BIT(5) /*!< enable read data buffer not empty interrupt and overrun error interrupt */
|
||||||
#define USART_CTL0_TCIE BIT(6) /*!< transmission complete interrupt enable */
|
#define USART_CTL0_TCIE BIT(6) /*!< enable transmission complete interrupt */
|
||||||
#define USART_CTL0_TBEIE BIT(7) /*!< transmitter buffer empty interrupt enable */
|
#define USART_CTL0_TBEIE BIT(7) /*!< enable transmitter buffer empty interrupt */
|
||||||
#define USART_CTL0_PERRIE BIT(8) /*!< parity error interrupt enable */
|
#define USART_CTL0_PERRIE BIT(8) /*!< enable parity error interrupt */
|
||||||
#define USART_CTL0_PM BIT(9) /*!< parity mode */
|
#define USART_CTL0_PM BIT(9) /*!< parity mode */
|
||||||
#define USART_CTL0_PCEN BIT(10) /*!< parity check function enable */
|
#define USART_CTL0_PCEN BIT(10) /*!< enable parity check function */
|
||||||
#define USART_CTL0_WM BIT(11) /*!< wakeup method in mute mode */
|
#define USART_CTL0_WM BIT(11) /*!< wakeup method in mute mode */
|
||||||
#define USART_CTL0_WL BIT(12) /*!< word length */
|
#define USART_CTL0_WL BIT(12) /*!< word length */
|
||||||
#define USART_CTL0_UEN BIT(13) /*!< USART enable */
|
#define USART_CTL0_UEN BIT(13) /*!< enable USART */
|
||||||
#define USART_CTL0_OVSMOD BIT(15) /*!< oversample mode */
|
#define USART_CTL0_OVSMOD BIT(15) /*!< oversample mode */
|
||||||
|
|
||||||
/* USARTx_CTL1 */
|
/* USARTx_CTL1 */
|
||||||
#define USART_CTL1_ADDR BITS(0,3) /*!< address of USART */
|
#define USART_CTL1_ADDR BITS(0,3) /*!< address of USART */
|
||||||
#define USART_CTL1_LBLEN BIT(5) /*!< LIN break frame length */
|
#define USART_CTL1_LBLEN BIT(5) /*!< LIN break frame length */
|
||||||
#define USART_CTL1_LBDIE BIT(6) /*!< LIN break detected interrupt eanble */
|
#define USART_CTL1_LBDIE BIT(6) /*!< enable LIN break detected interrupt */
|
||||||
#define USART_CTL1_CLEN BIT(8) /*!< CK length */
|
#define USART_CTL1_CLEN BIT(8) /*!< CK length */
|
||||||
#define USART_CTL1_CPH BIT(9) /*!< CK phase */
|
#define USART_CTL1_CPH BIT(9) /*!< CK phase */
|
||||||
#define USART_CTL1_CPL BIT(10) /*!< CK polarity */
|
#define USART_CTL1_CPL BIT(10) /*!< CK polarity */
|
||||||
#define USART_CTL1_CKEN BIT(11) /*!< CK pin enable */
|
#define USART_CTL1_CKEN BIT(11) /*!< enable CK pin */
|
||||||
#define USART_CTL1_STB BITS(12,13) /*!< STOP bits length */
|
#define USART_CTL1_STB BITS(12,13) /*!< STOP bits length */
|
||||||
#define USART_CTL1_LMEN BIT(14) /*!< LIN mode enable */
|
#define USART_CTL1_LMEN BIT(14) /*!< enable LIN mode */
|
||||||
|
|
||||||
/* USARTx_CTL2 */
|
/* USARTx_CTL2 */
|
||||||
#define USART_CTL2_ERRIE BIT(0) /*!< error interrupt enable */
|
#define USART_CTL2_ERRIE BIT(0) /*!< enable error interrupt */
|
||||||
#define USART_CTL2_IREN BIT(1) /*!< IrDA mode enable */
|
#define USART_CTL2_IREN BIT(1) /*!< enable IrDA mode */
|
||||||
#define USART_CTL2_IRLP BIT(2) /*!< IrDA low-power */
|
#define USART_CTL2_IRLP BIT(2) /*!< IrDA low-power */
|
||||||
#define USART_CTL2_HDEN BIT(3) /*!< half-duplex enable */
|
#define USART_CTL2_HDEN BIT(3) /*!< enable half-duplex */
|
||||||
#define USART_CTL2_NKEN BIT(4) /*!< NACK enable in smartcard mode */
|
#define USART_CTL2_NKEN BIT(4) /*!< NACK enable in smartcard mode */
|
||||||
#define USART_CTL2_SCEN BIT(5) /*!< smartcard mode enable */
|
#define USART_CTL2_SCEN BIT(5) /*!< enable smartcard mode */
|
||||||
#define USART_CTL2_DENR BIT(6) /*!< DMA request enable for reception */
|
#define USART_CTL2_DENR BIT(6) /*!< enable DMA request for reception */
|
||||||
#define USART_CTL2_DENT BIT(7) /*!< DMA request enable for transmission */
|
#define USART_CTL2_DENT BIT(7) /*!< enable DMA request for transmission */
|
||||||
#define USART_CTL2_RTSEN BIT(8) /*!< RTS enable */
|
#define USART_CTL2_RTSEN BIT(8) /*!< enable RTS */
|
||||||
#define USART_CTL2_CTSEN BIT(9) /*!< CTS enable */
|
#define USART_CTL2_CTSEN BIT(9) /*!< enable CTS */
|
||||||
#define USART_CTL2_CTSIE BIT(10) /*!< CTS interrupt enable */
|
#define USART_CTL2_CTSIE BIT(10) /*!< enable CTS interrupt */
|
||||||
#define USART_CTL2_OSB BIT(11) /*!< one sample bit method */
|
#define USART_CTL2_OSB BIT(11) /*!< one sample bit method */
|
||||||
|
|
||||||
/* USARTx_GP */
|
/* USARTx_GP */
|
||||||
|
|
@ -129,7 +130,7 @@ OF SUCH DAMAGE.
|
||||||
#define USART_GP_GUAT BITS(8,15) /*!< guard time value in smartcard mode */
|
#define USART_GP_GUAT BITS(8,15) /*!< guard time value in smartcard mode */
|
||||||
|
|
||||||
/* USARTx_CTL3 */
|
/* USARTx_CTL3 */
|
||||||
#define USART_CTL3_RTEN BIT(0) /*!< receiver timeout enable */
|
#define USART_CTL3_RTEN BIT(0) /*!< enable receiver timeout */
|
||||||
#define USART_CTL3_SCRTNUM BITS(1,3) /*!< smartcard auto-retry number */
|
#define USART_CTL3_SCRTNUM BITS(1,3) /*!< smartcard auto-retry number */
|
||||||
#define USART_CTL3_RTIE BIT(4) /*!< interrupt enable bit of receive timeout event */
|
#define USART_CTL3_RTIE BIT(4) /*!< interrupt enable bit of receive timeout event */
|
||||||
#define USART_CTL3_EBIE BIT(5) /*!< interrupt enable bit of end of block event */
|
#define USART_CTL3_EBIE BIT(5) /*!< interrupt enable bit of end of block event */
|
||||||
|
|
@ -173,8 +174,7 @@ OF SUCH DAMAGE.
|
||||||
#define USART_CHC_REG_OFFSET 0xC0U /*!< CHC register offset */
|
#define USART_CHC_REG_OFFSET 0xC0U /*!< CHC register offset */
|
||||||
|
|
||||||
/* USART flags */
|
/* USART flags */
|
||||||
typedef enum
|
typedef enum {
|
||||||
{
|
|
||||||
/* flags in STAT0 register */
|
/* flags in STAT0 register */
|
||||||
USART_FLAG_CTS = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 9U), /*!< CTS change flag */
|
USART_FLAG_CTS = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 9U), /*!< CTS change flag */
|
||||||
USART_FLAG_LBD = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 8U), /*!< LIN break detected flag */
|
USART_FLAG_LBD = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 8U), /*!< LIN break detected flag */
|
||||||
|
|
@ -195,8 +195,7 @@ typedef enum
|
||||||
} usart_flag_enum;
|
} usart_flag_enum;
|
||||||
|
|
||||||
/* USART interrupt flags */
|
/* USART interrupt flags */
|
||||||
typedef enum
|
typedef enum {
|
||||||
{
|
|
||||||
/* interrupt flags in CTL0 register */
|
/* interrupt flags in CTL0 register */
|
||||||
USART_INT_FLAG_PERR = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 8U, USART_STAT0_REG_OFFSET, 0U), /*!< parity error interrupt and flag */
|
USART_INT_FLAG_PERR = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 8U, USART_STAT0_REG_OFFSET, 0U), /*!< parity error interrupt and flag */
|
||||||
USART_INT_FLAG_TBE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 7U, USART_STAT0_REG_OFFSET, 7U), /*!< transmitter buffer empty interrupt and flag */
|
USART_INT_FLAG_TBE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 7U, USART_STAT0_REG_OFFSET, 7U), /*!< transmitter buffer empty interrupt and flag */
|
||||||
|
|
@ -217,8 +216,7 @@ typedef enum
|
||||||
} usart_interrupt_flag_enum;
|
} usart_interrupt_flag_enum;
|
||||||
|
|
||||||
/* USART interrupt flags */
|
/* USART interrupt flags */
|
||||||
typedef enum
|
typedef enum {
|
||||||
{
|
|
||||||
/* interrupt in CTL0 register */
|
/* interrupt in CTL0 register */
|
||||||
USART_INT_PERR = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 8U), /*!< parity error interrupt */
|
USART_INT_PERR = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 8U), /*!< parity error interrupt */
|
||||||
USART_INT_TBE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 7U), /*!< transmitter buffer empty interrupt */
|
USART_INT_TBE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 7U), /*!< transmitter buffer empty interrupt */
|
||||||
|
|
@ -235,9 +233,8 @@ typedef enum
|
||||||
USART_INT_RT = USART_REGIDX_BIT(USART_CTL3_REG_OFFSET, 4U), /*!< interrupt enable bit of receive timeout event */
|
USART_INT_RT = USART_REGIDX_BIT(USART_CTL3_REG_OFFSET, 4U), /*!< interrupt enable bit of receive timeout event */
|
||||||
} usart_interrupt_enum;
|
} usart_interrupt_enum;
|
||||||
|
|
||||||
/* USART invert configure */
|
/* configure USART invert */
|
||||||
typedef enum
|
typedef enum {
|
||||||
{
|
|
||||||
/* data bit level inversion */
|
/* data bit level inversion */
|
||||||
USART_DINV_ENABLE, /*!< data bit level inversion */
|
USART_DINV_ENABLE, /*!< data bit level inversion */
|
||||||
USART_DINV_DISABLE, /*!< data bit level not inversion */
|
USART_DINV_DISABLE, /*!< data bit level not inversion */
|
||||||
|
|
@ -249,12 +246,12 @@ typedef enum
|
||||||
USART_RXPIN_DISABLE, /*!< RX pin level not inversion */
|
USART_RXPIN_DISABLE, /*!< RX pin level not inversion */
|
||||||
} usart_invert_enum;
|
} usart_invert_enum;
|
||||||
|
|
||||||
/* USART receiver configure */
|
/* configure USART receiver */
|
||||||
#define CTL0_REN(regval) (BIT(2) & ((uint32_t)(regval) << 2))
|
#define CTL0_REN(regval) (BIT(2) & ((uint32_t)(regval) << 2))
|
||||||
#define USART_RECEIVE_ENABLE CTL0_REN(1) /*!< enable receiver */
|
#define USART_RECEIVE_ENABLE CTL0_REN(1) /*!< enable receiver */
|
||||||
#define USART_RECEIVE_DISABLE CTL0_REN(0) /*!< disable receiver */
|
#define USART_RECEIVE_DISABLE CTL0_REN(0) /*!< disable receiver */
|
||||||
|
|
||||||
/* USART transmitter configure */
|
/* configure USART transmitter */
|
||||||
#define CTL0_TEN(regval) (BIT(3) & ((uint32_t)(regval) << 3))
|
#define CTL0_TEN(regval) (BIT(3) & ((uint32_t)(regval) << 3))
|
||||||
#define USART_TRANSMIT_ENABLE CTL0_TEN(1) /*!< enable transmitter */
|
#define USART_TRANSMIT_ENABLE CTL0_TEN(1) /*!< enable transmitter */
|
||||||
#define USART_TRANSMIT_DISABLE CTL0_TEN(0) /*!< disable transmitter */
|
#define USART_TRANSMIT_DISABLE CTL0_TEN(0) /*!< disable transmitter */
|
||||||
|
|
@ -307,32 +304,32 @@ typedef enum
|
||||||
#define USART_CPL_LOW CTL1_CPL(0) /*!< steady low value on CK pin */
|
#define USART_CPL_LOW CTL1_CPL(0) /*!< steady low value on CK pin */
|
||||||
#define USART_CPL_HIGH CTL1_CPL(1) /*!< steady high value on CK pin */
|
#define USART_CPL_HIGH CTL1_CPL(1) /*!< steady high value on CK pin */
|
||||||
|
|
||||||
/* USART DMA request for receive configure */
|
/* configure USART DMA request for receive */
|
||||||
#define CLT2_DENR(regval) (BIT(6) & ((uint32_t)(regval) << 6))
|
#define CLT2_DENR(regval) (BIT(6) & ((uint32_t)(regval) << 6))
|
||||||
#define USART_DENR_ENABLE CLT2_DENR(1) /*!< DMA request enable for reception */
|
#define USART_RECEIVE_DMA_ENABLE CLT2_DENR(1) /*!< DMA request enable for reception */
|
||||||
#define USART_DENR_DISABLE CLT2_DENR(0) /*!< DMA request disable for reception */
|
#define USART_RECEIVE_DMA_DISABLE CLT2_DENR(0) /*!< DMA request disable for reception */
|
||||||
|
|
||||||
/* USART DMA request for transmission configure */
|
/* configure USART DMA request for transmission */
|
||||||
#define CLT2_DENT(regval) (BIT(7) & ((uint32_t)(regval) << 7))
|
#define CLT2_DENT(regval) (BIT(7) & ((uint32_t)(regval) << 7))
|
||||||
#define USART_DENT_ENABLE CLT2_DENT(1) /*!< DMA request enable for transmission */
|
#define USART_TRANSMIT_DMA_ENABLE CLT2_DENT(1) /*!< DMA request enable for transmission */
|
||||||
#define USART_DENT_DISABLE CLT2_DENT(0) /*!< DMA request disable for transmission */
|
#define USART_TRANSMIT_DMA_DISABLE CLT2_DENT(0) /*!< DMA request disable for transmission */
|
||||||
|
|
||||||
/* USART RTS configure */
|
/* configure USART RTS */
|
||||||
#define CLT2_RTSEN(regval) (BIT(8) & ((uint32_t)(regval) << 8))
|
#define CLT2_RTSEN(regval) (BIT(8) & ((uint32_t)(regval) << 8))
|
||||||
#define USART_RTS_ENABLE CLT2_RTSEN(1) /*!< RTS enable */
|
#define USART_RTS_ENABLE CLT2_RTSEN(1) /*!< enable RTS */
|
||||||
#define USART_RTS_DISABLE CLT2_RTSEN(0) /*!< RTS disable */
|
#define USART_RTS_DISABLE CLT2_RTSEN(0) /*!< disable RTS */
|
||||||
|
|
||||||
/* USART CTS configure */
|
/* configure USART CTS */
|
||||||
#define CLT2_CTSEN(regval) (BIT(9) & ((uint32_t)(regval) << 9))
|
#define CLT2_CTSEN(regval) (BIT(9) & ((uint32_t)(regval) << 9))
|
||||||
#define USART_CTS_ENABLE CLT2_CTSEN(1) /*!< CTS enable */
|
#define USART_CTS_ENABLE CLT2_CTSEN(1) /*!< enable CTS */
|
||||||
#define USART_CTS_DISABLE CLT2_CTSEN(0) /*!< CTS disable */
|
#define USART_CTS_DISABLE CLT2_CTSEN(0) /*!< disable CTS */
|
||||||
|
|
||||||
/* USART one sample bit method configure */
|
/* configure USART one sample bit method */
|
||||||
#define CTL2_OSB(regval) (BIT(11) & ((uint32_t)(regval) << 11))
|
#define CTL2_OSB(regval) (BIT(11) & ((uint32_t)(regval) << 11))
|
||||||
#define USART_OSB_1bit CTL2_OSB(1) /*!< 1 bit */
|
#define USART_OSB_1bit CTL2_OSB(1) /*!< 1 bit */
|
||||||
#define USART_OSB_3bit CTL2_OSB(0) /*!< 3 bits */
|
#define USART_OSB_3bit CTL2_OSB(0) /*!< 3 bits */
|
||||||
|
|
||||||
/* USART IrDA low-power enable */
|
/* enable USART IrDA low-power */
|
||||||
#define CTL2_IRLP(regval) (BIT(2) & ((uint32_t)(regval) << 2))
|
#define CTL2_IRLP(regval) (BIT(2) & ((uint32_t)(regval) << 2))
|
||||||
#define USART_IRLP_LOW CTL2_IRLP(1) /*!< low-power */
|
#define USART_IRLP_LOW CTL2_IRLP(1) /*!< low-power */
|
||||||
#define USART_IRLP_NORMAL CTL2_IRLP(0) /*!< normal */
|
#define USART_IRLP_NORMAL CTL2_IRLP(0) /*!< normal */
|
||||||
|
|
@ -394,7 +391,7 @@ void usart_receiver_timeout_disable(uint32_t usart_periph);
|
||||||
/* configure receiver timeout threshold */
|
/* configure receiver timeout threshold */
|
||||||
void usart_receiver_timeout_threshold_config(uint32_t usart_periph, uint32_t rtimeout);
|
void usart_receiver_timeout_threshold_config(uint32_t usart_periph, uint32_t rtimeout);
|
||||||
/* USART transmit data function */
|
/* USART transmit data function */
|
||||||
void usart_data_transmit(uint32_t usart_periph, uint32_t data);
|
void usart_data_transmit(uint32_t usart_periph, uint16_t data);
|
||||||
/* USART receive data function */
|
/* USART receive data function */
|
||||||
uint16_t usart_data_receive(uint32_t usart_periph);
|
uint16_t usart_data_receive(uint32_t usart_periph);
|
||||||
|
|
||||||
|
|
@ -434,7 +431,7 @@ void usart_synchronous_clock_config(uint32_t usart_periph, uint32_t clen, uint32
|
||||||
|
|
||||||
/* smartcard communication */
|
/* smartcard communication */
|
||||||
/* configure guard time value in smartcard mode */
|
/* configure guard time value in smartcard mode */
|
||||||
void usart_guard_time_config(uint32_t usart_periph, uint32_t guat);
|
void usart_guard_time_config(uint32_t usart_periph, uint8_t guat);
|
||||||
/* enable smartcard mode */
|
/* enable smartcard mode */
|
||||||
void usart_smartcard_mode_enable(uint32_t usart_periph);
|
void usart_smartcard_mode_enable(uint32_t usart_periph);
|
||||||
/* disable smartcard mode */
|
/* disable smartcard mode */
|
||||||
|
|
@ -444,9 +441,9 @@ void usart_smartcard_mode_nack_enable(uint32_t usart_periph);
|
||||||
/* disable NACK in smartcard mode */
|
/* disable NACK in smartcard mode */
|
||||||
void usart_smartcard_mode_nack_disable(uint32_t usart_periph);
|
void usart_smartcard_mode_nack_disable(uint32_t usart_periph);
|
||||||
/* configure smartcard auto-retry number */
|
/* configure smartcard auto-retry number */
|
||||||
void usart_smartcard_autoretry_config(uint32_t usart_periph, uint32_t scrtnum);
|
void usart_smartcard_autoretry_config(uint32_t usart_periph, uint8_t scrtnum);
|
||||||
/* configure block length */
|
/* configure block length */
|
||||||
void usart_block_length_config(uint32_t usart_periph, uint32_t bl);
|
void usart_block_length_config(uint32_t usart_periph, uint8_t bl);
|
||||||
|
|
||||||
/* IrDA communication */
|
/* IrDA communication */
|
||||||
/* enable IrDA mode */
|
/* enable IrDA mode */
|
||||||
|
|
|
||||||
|
|
@ -5,10 +5,11 @@
|
||||||
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
||||||
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
||||||
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
||||||
|
\version 2022-03-09, V3.0.0, firmware for GD32F4xx
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/*
|
/*
|
||||||
Copyright (c) 2020, GigaDevice Semiconductor Inc.
|
Copyright (c) 2022, GigaDevice Semiconductor Inc.
|
||||||
|
|
||||||
Redistribution and use in source and binary forms, with or without modification,
|
Redistribution and use in source and binary forms, with or without modification,
|
||||||
are permitted provided that the following conditions are met:
|
are permitted provided that the following conditions are met:
|
||||||
|
|
@ -40,7 +41,7 @@ OF SUCH DAMAGE.
|
||||||
#include "gd32f4xx.h"
|
#include "gd32f4xx.h"
|
||||||
|
|
||||||
/* WWDGT definitions */
|
/* WWDGT definitions */
|
||||||
#define WWDGT WWDGT_BASE
|
#define WWDGT WWDGT_BASE /*!< WWDGT base address */
|
||||||
|
|
||||||
/* registers definitions */
|
/* registers definitions */
|
||||||
#define WWDGT_CTL REG32((WWDGT) + 0x00U) /*!< WWDGT control register */
|
#define WWDGT_CTL REG32((WWDGT) + 0x00U) /*!< WWDGT control register */
|
||||||
|
|
@ -67,6 +68,11 @@ OF SUCH DAMAGE.
|
||||||
#define WWDGT_CFG_PSC_DIV4 CFG_PSC(2) /*!< the time base of WWDGT = (PCLK1/4096)/4 */
|
#define WWDGT_CFG_PSC_DIV4 CFG_PSC(2) /*!< the time base of WWDGT = (PCLK1/4096)/4 */
|
||||||
#define WWDGT_CFG_PSC_DIV8 CFG_PSC(3) /*!< the time base of WWDGT = (PCLK1/4096)/8 */
|
#define WWDGT_CFG_PSC_DIV8 CFG_PSC(3) /*!< the time base of WWDGT = (PCLK1/4096)/8 */
|
||||||
|
|
||||||
|
/* write value to WWDGT_CTL_CNT bit field */
|
||||||
|
#define CTL_CNT(regval) (BITS(0,6) & ((uint32_t)(regval) << 0))
|
||||||
|
/* write value to WWDGT_CFG_WIN bit field */
|
||||||
|
#define CFG_WIN(regval) (BITS(0,6) & ((uint32_t)(regval) << 0))
|
||||||
|
|
||||||
/* function declarations */
|
/* function declarations */
|
||||||
/* reset the window watchdog timer configuration */
|
/* reset the window watchdog timer configuration */
|
||||||
void wwdgt_deinit(void);
|
void wwdgt_deinit(void);
|
||||||
|
|
@ -78,11 +84,11 @@ void wwdgt_counter_update(uint16_t counter_value);
|
||||||
/* configure counter value, window value, and prescaler divider value */
|
/* configure counter value, window value, and prescaler divider value */
|
||||||
void wwdgt_config(uint16_t counter, uint16_t window, uint32_t prescaler);
|
void wwdgt_config(uint16_t counter, uint16_t window, uint32_t prescaler);
|
||||||
|
|
||||||
/* enable early wakeup interrupt of WWDGT */
|
|
||||||
void wwdgt_interrupt_enable(void);
|
|
||||||
/* check early wakeup interrupt state of WWDGT */
|
/* check early wakeup interrupt state of WWDGT */
|
||||||
FlagStatus wwdgt_flag_get(void);
|
FlagStatus wwdgt_flag_get(void);
|
||||||
/* clear early wakeup interrupt state of WWDGT */
|
/* clear early wakeup interrupt state of WWDGT */
|
||||||
void wwdgt_flag_clear(void);
|
void wwdgt_flag_clear(void);
|
||||||
|
/* enable early wakeup interrupt of WWDGT */
|
||||||
|
void wwdgt_interrupt_enable(void);
|
||||||
|
|
||||||
#endif /* GD32F4XX_WWDGT_H */
|
#endif /* GD32F4XX_WWDGT_H */
|
||||||
|
|
|
||||||
|
|
@ -5,10 +5,11 @@
|
||||||
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
||||||
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
||||||
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
||||||
|
\version 2022-03-09, V3.0.0, firmware for GD32F4xx
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/*
|
/*
|
||||||
Copyright (c) 2020, GigaDevice Semiconductor Inc.
|
Copyright (c) 2022, GigaDevice Semiconductor Inc.
|
||||||
|
|
||||||
Redistribution and use in source and binary forms, with or without modification,
|
Redistribution and use in source and binary forms, with or without modification,
|
||||||
are permitted provided that the following conditions are met:
|
are permitted provided that the following conditions are met:
|
||||||
|
|
@ -36,16 +37,16 @@ OF SUCH DAMAGE.
|
||||||
|
|
||||||
#include "gd32f4xx_adc.h"
|
#include "gd32f4xx_adc.h"
|
||||||
|
|
||||||
#define REGULAR_TRIGGER_MODE ((uint32_t)28U)
|
#define ROUTINE_TRIGGER_MODE ((uint32_t)28U)
|
||||||
#define INSERTED_TRIGGER_MODE ((uint32_t)20U)
|
#define INSERTED_TRIGGER_MODE ((uint32_t)20U)
|
||||||
/* discontinuous mode macro*/
|
/* discontinuous mode macro*/
|
||||||
#define ADC_CHANNEL_LENGTH_SUBTRACT_ONE ((uint8_t)1U)
|
#define ADC_CHANNEL_LENGTH_SUBTRACT_ONE ((uint8_t)1U)
|
||||||
|
|
||||||
/* ADC regular channel macro */
|
/* ADC routine channel macro */
|
||||||
#define ADC_REGULAR_CHANNEL_RANK_SIX ((uint8_t)6U)
|
#define ADC_ROUTINE_CHANNEL_RANK_SIX ((uint8_t)6U)
|
||||||
#define ADC_REGULAR_CHANNEL_RANK_TWELVE ((uint8_t)12U)
|
#define ADC_ROUTINE_CHANNEL_RANK_TWELVE ((uint8_t)12U)
|
||||||
#define ADC_REGULAR_CHANNEL_RANK_SIXTEEN ((uint8_t)16U)
|
#define ADC_ROUTINE_CHANNEL_RANK_SIXTEEN ((uint8_t)16U)
|
||||||
#define ADC_REGULAR_CHANNEL_RANK_LENGTH ((uint8_t)5U)
|
#define ADC_ROUTINE_CHANNEL_RANK_LENGTH ((uint8_t)5U)
|
||||||
|
|
||||||
/* ADC sampling time macro */
|
/* ADC sampling time macro */
|
||||||
#define ADC_CHANNEL_SAMPLE_TEN ((uint8_t)10U)
|
#define ADC_CHANNEL_SAMPLE_TEN ((uint8_t)10U)
|
||||||
|
|
@ -99,7 +100,7 @@ void adc_clock_config(uint32_t prescaler)
|
||||||
\param[in] function: the function to config
|
\param[in] function: the function to config
|
||||||
only one parameter can be selected which is shown as below:
|
only one parameter can be selected which is shown as below:
|
||||||
\arg ADC_SCAN_MODE: scan mode select
|
\arg ADC_SCAN_MODE: scan mode select
|
||||||
\arg ADC_INSERTED_CHANNEL_AUTO: inserted channel group convert automatically
|
\arg ADC_INSERTED_CHANNEL_AUTO: inserted sequence convert automatically
|
||||||
\arg ADC_CONTINUOUS_MODE: continuous mode select
|
\arg ADC_CONTINUOUS_MODE: continuous mode select
|
||||||
\param[in] newvalue: ENABLE or DISABLE
|
\param[in] newvalue: ENABLE or DISABLE
|
||||||
\param[out] none
|
\param[out] none
|
||||||
|
|
@ -113,7 +114,7 @@ void adc_special_function_config(uint32_t adc_periph , uint32_t function , Contr
|
||||||
ADC_CTL0(adc_periph) |= ADC_SCAN_MODE;
|
ADC_CTL0(adc_periph) |= ADC_SCAN_MODE;
|
||||||
}
|
}
|
||||||
if(0U != (function & ADC_INSERTED_CHANNEL_AUTO)) {
|
if(0U != (function & ADC_INSERTED_CHANNEL_AUTO)) {
|
||||||
/* enable inserted channel group convert automatically */
|
/* enable inserted sequence convert automatically */
|
||||||
ADC_CTL0(adc_periph) |= ADC_INSERTED_CHANNEL_AUTO;
|
ADC_CTL0(adc_periph) |= ADC_INSERTED_CHANNEL_AUTO;
|
||||||
}
|
}
|
||||||
if(0U != (function & ADC_CONTINUOUS_MODE)) {
|
if(0U != (function & ADC_CONTINUOUS_MODE)) {
|
||||||
|
|
@ -126,7 +127,7 @@ void adc_special_function_config(uint32_t adc_periph , uint32_t function , Contr
|
||||||
ADC_CTL0(adc_periph) &= ~ADC_SCAN_MODE;
|
ADC_CTL0(adc_periph) &= ~ADC_SCAN_MODE;
|
||||||
}
|
}
|
||||||
if(0U != (function & ADC_INSERTED_CHANNEL_AUTO)) {
|
if(0U != (function & ADC_INSERTED_CHANNEL_AUTO)) {
|
||||||
/* disable inserted channel group convert automatically */
|
/* disable inserted sequence convert automatically */
|
||||||
ADC_CTL0(adc_periph) &= ~ADC_INSERTED_CHANNEL_AUTO;
|
ADC_CTL0(adc_periph) &= ~ADC_INSERTED_CHANNEL_AUTO;
|
||||||
}
|
}
|
||||||
if(0U != (function & ADC_CONTINUOUS_MODE)) {
|
if(0U != (function & ADC_CONTINUOUS_MODE)) {
|
||||||
|
|
@ -344,7 +345,7 @@ void adc_dma_mode_disable(uint32_t adc_periph)
|
||||||
}
|
}
|
||||||
|
|
||||||
/*!
|
/*!
|
||||||
\brief when DMA=1, the DMA engine issues a request at end of each regular conversion
|
\brief when DMA=1, the DMA engine issues a request at end of each routine conversion
|
||||||
\param[in] adc_periph: ADCx,x=0,1,2
|
\param[in] adc_periph: ADCx,x=0,1,2
|
||||||
\param[out] none
|
\param[out] none
|
||||||
\retval none
|
\retval none
|
||||||
|
|
@ -368,58 +369,58 @@ void adc_dma_request_after_last_disable(uint32_t adc_periph)
|
||||||
/*!
|
/*!
|
||||||
\brief configure ADC discontinuous mode
|
\brief configure ADC discontinuous mode
|
||||||
\param[in] adc_periph: ADCx,x=0,1,2
|
\param[in] adc_periph: ADCx,x=0,1,2
|
||||||
\param[in] adc_channel_group: select the channel group
|
\param[in] adc_sequence: select the sequence
|
||||||
only one parameter can be selected which is shown as below:
|
only one parameter can be selected which is shown as below:
|
||||||
\arg ADC_REGULAR_CHANNEL: regular channel group
|
\arg ADC_ROUTINE_CHANNEL: routine sequence
|
||||||
\arg ADC_INSERTED_CHANNEL: inserted channel group
|
\arg ADC_INSERTED_CHANNEL: inserted sequence
|
||||||
\arg ADC_CHANNEL_DISCON_DISABLE: disable discontinuous mode of regular & inserted channel
|
\arg ADC_CHANNEL_DISCON_DISABLE: disable discontinuous mode of routine & inserted channel
|
||||||
\param[in] length: number of conversions in discontinuous mode,the number can be 1..8
|
\param[in] length: number of conversions in discontinuous mode,the number can be 1..8
|
||||||
for regular channel ,the number has no effect for inserted channel
|
for routine sequence ,the number has no effect for inserted sequence
|
||||||
\param[out] none
|
\param[out] none
|
||||||
\retval none
|
\retval none
|
||||||
*/
|
*/
|
||||||
void adc_discontinuous_mode_config(uint32_t adc_periph , uint8_t adc_channel_group , uint8_t length)
|
void adc_discontinuous_mode_config(uint32_t adc_periph, uint8_t adc_sequence, uint8_t length)
|
||||||
{
|
{
|
||||||
/* disable discontinuous mode of regular & inserted channel */
|
/* disable discontinuous mode of routine & inserted channel */
|
||||||
ADC_CTL0(adc_periph) &= ~((uint32_t)(ADC_CTL0_DISRC | ADC_CTL0_DISIC));
|
ADC_CTL0(adc_periph) &= ~((uint32_t)(ADC_CTL0_DISRC | ADC_CTL0_DISIC));
|
||||||
switch(adc_channel_group){
|
switch(adc_sequence) {
|
||||||
case ADC_REGULAR_CHANNEL:
|
case ADC_ROUTINE_CHANNEL:
|
||||||
/* config the number of conversions in discontinuous mode */
|
/* config the number of conversions in discontinuous mode */
|
||||||
ADC_CTL0(adc_periph) &= ~((uint32_t)ADC_CTL0_DISNUM);
|
ADC_CTL0(adc_periph) &= ~((uint32_t)ADC_CTL0_DISNUM);
|
||||||
if((length <= 8U) && (length >= 1U)) {
|
if((length <= 8U) && (length >= 1U)) {
|
||||||
ADC_CTL0(adc_periph) |= CTL0_DISNUM(((uint32_t)length - ADC_CHANNEL_LENGTH_SUBTRACT_ONE));
|
ADC_CTL0(adc_periph) |= CTL0_DISNUM(((uint32_t)length - ADC_CHANNEL_LENGTH_SUBTRACT_ONE));
|
||||||
}
|
}
|
||||||
/* enable regular channel group discontinuous mode */
|
/* enable routine sequence discontinuous mode */
|
||||||
ADC_CTL0(adc_periph) |= (uint32_t)ADC_CTL0_DISRC;
|
ADC_CTL0(adc_periph) |= (uint32_t)ADC_CTL0_DISRC;
|
||||||
break;
|
break;
|
||||||
case ADC_INSERTED_CHANNEL:
|
case ADC_INSERTED_CHANNEL:
|
||||||
/* enable inserted channel group discontinuous mode */
|
/* enable inserted sequence discontinuous mode */
|
||||||
ADC_CTL0(adc_periph) |= (uint32_t)ADC_CTL0_DISIC;
|
ADC_CTL0(adc_periph) |= (uint32_t)ADC_CTL0_DISIC;
|
||||||
break;
|
break;
|
||||||
case ADC_CHANNEL_DISCON_DISABLE:
|
case ADC_CHANNEL_DISCON_DISABLE:
|
||||||
/* disable discontinuous mode of regular & inserted channel */
|
/* disable discontinuous mode of routine & inserted channel */
|
||||||
default:
|
default:
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
/*!
|
/*!
|
||||||
\brief configure the length of regular channel group or inserted channel group
|
\brief configure the length of routine sequence or inserted sequence
|
||||||
\param[in] adc_periph: ADCx,x=0,1,2
|
\param[in] adc_periph: ADCx,x=0,1,2
|
||||||
\param[in] adc_channel_group: select the channel group
|
\param[in] adc_sequence: select the sequence
|
||||||
only one parameter can be selected which is shown as below:
|
only one parameter can be selected which is shown as below:
|
||||||
\arg ADC_REGULAR_CHANNEL: regular channel group
|
\arg ADC_ROUTINE_CHANNEL: routine sequence
|
||||||
\arg ADC_INSERTED_CHANNEL: inserted channel group
|
\arg ADC_INSERTED_CHANNEL: inserted sequence
|
||||||
\param[in] length: the length of the channel
|
\param[in] length: the length of the channel
|
||||||
regular channel 1-16
|
routine channel 1-16
|
||||||
inserted channel 1-4
|
inserted channel 1-4
|
||||||
\param[out] none
|
\param[out] none
|
||||||
\retval none
|
\retval none
|
||||||
*/
|
*/
|
||||||
void adc_channel_length_config(uint32_t adc_periph , uint8_t adc_channel_group , uint32_t length)
|
void adc_channel_length_config(uint32_t adc_periph, uint8_t adc_sequence, uint32_t length)
|
||||||
{
|
{
|
||||||
switch(adc_channel_group){
|
switch(adc_sequence) {
|
||||||
case ADC_REGULAR_CHANNEL:
|
case ADC_ROUTINE_CHANNEL:
|
||||||
if((length >= 1U) && (length <= 16U)) {
|
if((length >= 1U) && (length <= 16U)) {
|
||||||
ADC_RSQ0(adc_periph) &= ~((uint32_t)ADC_RSQ0_RL);
|
ADC_RSQ0(adc_periph) &= ~((uint32_t)ADC_RSQ0_RL);
|
||||||
ADC_RSQ0(adc_periph) |= RSQ0_RL((uint32_t)(length - ADC_CHANNEL_LENGTH_SUBTRACT_ONE));
|
ADC_RSQ0(adc_periph) |= RSQ0_RL((uint32_t)(length - ADC_CHANNEL_LENGTH_SUBTRACT_ONE));
|
||||||
|
|
@ -437,12 +438,12 @@ void adc_channel_length_config(uint32_t adc_periph , uint8_t adc_channel_group ,
|
||||||
}
|
}
|
||||||
|
|
||||||
/*!
|
/*!
|
||||||
\brief configure ADC regular channel
|
\brief configure ADC routine channel
|
||||||
\param[in] adc_periph: ADCx,x=0,1,2
|
\param[in] adc_periph: ADCx,x=0,1,2
|
||||||
\param[in] rank: the regular group sequencer rank,this parameter must be between 0 to 15
|
\param[in] rank: the routine sequence rank,this parameter must be between 0 to 15
|
||||||
\param[in] adc_channel: the selected ADC channel
|
\param[in] adc_channel: the selected ADC channel
|
||||||
only one parameter can be selected which is shown as below:
|
only one parameter can be selected which is shown as below:
|
||||||
\arg ADC_CHANNEL_x(x=0..18): ADC Channelx
|
\arg ADC_CHANNEL_x(x=0..18): ADC channelx
|
||||||
\param[in] sample_time: the sample time value
|
\param[in] sample_time: the sample time value
|
||||||
only one parameter can be selected which is shown as below:
|
only one parameter can be selected which is shown as below:
|
||||||
\arg ADC_SAMPLETIME_3: 3 cycles
|
\arg ADC_SAMPLETIME_3: 3 cycles
|
||||||
|
|
@ -456,45 +457,45 @@ void adc_channel_length_config(uint32_t adc_periph , uint8_t adc_channel_group ,
|
||||||
\param[out] none
|
\param[out] none
|
||||||
\retval none
|
\retval none
|
||||||
*/
|
*/
|
||||||
void adc_regular_channel_config(uint32_t adc_periph , uint8_t rank , uint8_t adc_channel , uint32_t sample_time)
|
void adc_routine_channel_config(uint32_t adc_periph, uint8_t rank, uint8_t adc_channel, uint32_t sample_time)
|
||||||
{
|
{
|
||||||
uint32_t rsq, sampt;
|
uint32_t rsq, sampt;
|
||||||
|
|
||||||
/* ADC regular sequence config */
|
/* ADC routine sequence config */
|
||||||
if(rank < ADC_REGULAR_CHANNEL_RANK_SIX){
|
if(rank < ADC_ROUTINE_CHANNEL_RANK_SIX) {
|
||||||
/* the regular group sequence rank is smaller than six */
|
/* the routine sequence rank is smaller than six */
|
||||||
rsq = ADC_RSQ2(adc_periph);
|
rsq = ADC_RSQ2(adc_periph);
|
||||||
rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (ADC_REGULAR_CHANNEL_RANK_LENGTH*rank)));
|
rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (ADC_ROUTINE_CHANNEL_RANK_LENGTH * rank)));
|
||||||
/* the channel number is written to these bits to select a channel as the nth conversion in the regular channel group */
|
/* the channel number is written to these bits to select a channel as the nth conversion in the routine sequence */
|
||||||
rsq |= ((uint32_t)adc_channel << (ADC_REGULAR_CHANNEL_RANK_LENGTH*rank));
|
rsq |= ((uint32_t)adc_channel << (ADC_ROUTINE_CHANNEL_RANK_LENGTH * rank));
|
||||||
ADC_RSQ2(adc_periph) = rsq;
|
ADC_RSQ2(adc_periph) = rsq;
|
||||||
}else if(rank < ADC_REGULAR_CHANNEL_RANK_TWELVE){
|
} else if(rank < ADC_ROUTINE_CHANNEL_RANK_TWELVE) {
|
||||||
/* the regular group sequence rank is smaller than twelve */
|
/* the routine sequence rank is smaller than twelve */
|
||||||
rsq = ADC_RSQ1(adc_periph);
|
rsq = ADC_RSQ1(adc_periph);
|
||||||
rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (ADC_REGULAR_CHANNEL_RANK_LENGTH*(rank-ADC_REGULAR_CHANNEL_RANK_SIX))));
|
rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (ADC_ROUTINE_CHANNEL_RANK_LENGTH * (rank - ADC_ROUTINE_CHANNEL_RANK_SIX))));
|
||||||
/* the channel number is written to these bits to select a channel as the nth conversion in the regular channel group */
|
/* the channel number is written to these bits to select a channel as the nth conversion in the routine sequence */
|
||||||
rsq |= ((uint32_t)adc_channel << (ADC_REGULAR_CHANNEL_RANK_LENGTH*(rank-ADC_REGULAR_CHANNEL_RANK_SIX)));
|
rsq |= ((uint32_t)adc_channel << (ADC_ROUTINE_CHANNEL_RANK_LENGTH * (rank - ADC_ROUTINE_CHANNEL_RANK_SIX)));
|
||||||
ADC_RSQ1(adc_periph) = rsq;
|
ADC_RSQ1(adc_periph) = rsq;
|
||||||
}else if(rank < ADC_REGULAR_CHANNEL_RANK_SIXTEEN){
|
} else if(rank < ADC_ROUTINE_CHANNEL_RANK_SIXTEEN) {
|
||||||
/* the regular group sequence rank is smaller than sixteen */
|
/* the routine sequence rank is smaller than sixteen */
|
||||||
rsq = ADC_RSQ0(adc_periph);
|
rsq = ADC_RSQ0(adc_periph);
|
||||||
rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (ADC_REGULAR_CHANNEL_RANK_LENGTH*(rank-ADC_REGULAR_CHANNEL_RANK_TWELVE))));
|
rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (ADC_ROUTINE_CHANNEL_RANK_LENGTH * (rank - ADC_ROUTINE_CHANNEL_RANK_TWELVE))));
|
||||||
/* the channel number is written to these bits to select a channel as the nth conversion in the regular channel group */
|
/* the channel number is written to these bits to select a channel as the nth conversion in the routine sequence */
|
||||||
rsq |= ((uint32_t)adc_channel << (ADC_REGULAR_CHANNEL_RANK_LENGTH*(rank-ADC_REGULAR_CHANNEL_RANK_TWELVE)));
|
rsq |= ((uint32_t)adc_channel << (ADC_ROUTINE_CHANNEL_RANK_LENGTH * (rank - ADC_ROUTINE_CHANNEL_RANK_TWELVE)));
|
||||||
ADC_RSQ0(adc_periph) = rsq;
|
ADC_RSQ0(adc_periph) = rsq;
|
||||||
} else {
|
} else {
|
||||||
}
|
}
|
||||||
|
|
||||||
/* ADC sampling time config */
|
/* ADC sampling time config */
|
||||||
if(adc_channel < ADC_CHANNEL_SAMPLE_TEN) {
|
if(adc_channel < ADC_CHANNEL_SAMPLE_TEN) {
|
||||||
/* the regular group sequence rank is smaller than ten */
|
/* the routine sequence rank is smaller than ten */
|
||||||
sampt = ADC_SAMPT1(adc_periph);
|
sampt = ADC_SAMPT1(adc_periph);
|
||||||
sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (ADC_CHANNEL_SAMPLE_LENGTH * adc_channel)));
|
sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (ADC_CHANNEL_SAMPLE_LENGTH * adc_channel)));
|
||||||
/* channel sample time set*/
|
/* channel sample time set*/
|
||||||
sampt |= (uint32_t)(sample_time << (ADC_CHANNEL_SAMPLE_LENGTH * adc_channel));
|
sampt |= (uint32_t)(sample_time << (ADC_CHANNEL_SAMPLE_LENGTH * adc_channel));
|
||||||
ADC_SAMPT1(adc_periph) = sampt;
|
ADC_SAMPT1(adc_periph) = sampt;
|
||||||
} else if(adc_channel <= ADC_CHANNEL_SAMPLE_EIGHTEEN) {
|
} else if(adc_channel <= ADC_CHANNEL_SAMPLE_EIGHTEEN) {
|
||||||
/* the regular group sequence rank is smaller than eighteen */
|
/* the routine sequence rank is smaller than eighteen */
|
||||||
sampt = ADC_SAMPT0(adc_periph);
|
sampt = ADC_SAMPT0(adc_periph);
|
||||||
sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (ADC_CHANNEL_SAMPLE_LENGTH * (adc_channel - ADC_CHANNEL_SAMPLE_TEN))));
|
sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (ADC_CHANNEL_SAMPLE_LENGTH * (adc_channel - ADC_CHANNEL_SAMPLE_TEN))));
|
||||||
/* channel sample time set*/
|
/* channel sample time set*/
|
||||||
|
|
@ -507,7 +508,7 @@ void adc_regular_channel_config(uint32_t adc_periph , uint8_t rank , uint8_t adc
|
||||||
/*!
|
/*!
|
||||||
\brief configure ADC inserted channel
|
\brief configure ADC inserted channel
|
||||||
\param[in] adc_periph: ADCx,x=0,1,2
|
\param[in] adc_periph: ADCx,x=0,1,2
|
||||||
\param[in] rank: the inserted group sequencer rank,this parameter must be between 0 to 3
|
\param[in] rank: the inserted sequence rank,this parameter must be between 0 to 3
|
||||||
\param[in] adc_channel: the selected ADC channel
|
\param[in] adc_channel: the selected ADC channel
|
||||||
only one parameter can be selected which is shown as below:
|
only one parameter can be selected which is shown as below:
|
||||||
\arg ADC_CHANNEL_x(x=0..18): ADC Channelx
|
\arg ADC_CHANNEL_x(x=0..18): ADC Channelx
|
||||||
|
|
@ -529,9 +530,9 @@ void adc_inserted_channel_config(uint32_t adc_periph , uint8_t rank , uint8_t ad
|
||||||
uint8_t inserted_length;
|
uint8_t inserted_length;
|
||||||
uint32_t isq, sampt;
|
uint32_t isq, sampt;
|
||||||
|
|
||||||
/* get inserted channel group length */
|
/* get inserted sequence length */
|
||||||
inserted_length = (uint8_t)GET_BITS(ADC_ISQ(adc_periph), 20U, 21U);
|
inserted_length = (uint8_t)GET_BITS(ADC_ISQ(adc_periph), 20U, 21U);
|
||||||
/* the channel number is written to these bits to select a channel as the nth conversion in the inserted channel group */
|
/* the channel number is written to these bits to select a channel as the nth conversion in the inserted sequence */
|
||||||
if(rank < 4U) {
|
if(rank < 4U) {
|
||||||
isq = ADC_ISQ(adc_periph);
|
isq = ADC_ISQ(adc_periph);
|
||||||
isq &= ~((uint32_t)(ADC_ISQ_ISQN << (ADC_INSERTED_CHANNEL_SHIFT_LENGTH - (inserted_length - rank) * ADC_INSERTED_CHANNEL_RANK_LENGTH)));
|
isq &= ~((uint32_t)(ADC_ISQ_ISQN << (ADC_INSERTED_CHANNEL_SHIFT_LENGTH - (inserted_length - rank) * ADC_INSERTED_CHANNEL_RANK_LENGTH)));
|
||||||
|
|
@ -541,14 +542,14 @@ void adc_inserted_channel_config(uint32_t adc_periph , uint8_t rank , uint8_t ad
|
||||||
|
|
||||||
/* ADC sampling time config */
|
/* ADC sampling time config */
|
||||||
if(adc_channel < ADC_CHANNEL_SAMPLE_TEN) {
|
if(adc_channel < ADC_CHANNEL_SAMPLE_TEN) {
|
||||||
/* the inserted group sequence rank is smaller than ten */
|
/* the inserted sequence rank is smaller than ten */
|
||||||
sampt = ADC_SAMPT1(adc_periph);
|
sampt = ADC_SAMPT1(adc_periph);
|
||||||
sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (ADC_CHANNEL_SAMPLE_LENGTH * adc_channel)));
|
sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (ADC_CHANNEL_SAMPLE_LENGTH * adc_channel)));
|
||||||
/* channel sample time set*/
|
/* channel sample time set*/
|
||||||
sampt |= (uint32_t) sample_time << (ADC_CHANNEL_SAMPLE_LENGTH * adc_channel);
|
sampt |= (uint32_t) sample_time << (ADC_CHANNEL_SAMPLE_LENGTH * adc_channel);
|
||||||
ADC_SAMPT1(adc_periph) = sampt;
|
ADC_SAMPT1(adc_periph) = sampt;
|
||||||
} else if(adc_channel <= ADC_CHANNEL_SAMPLE_EIGHTEEN) {
|
} else if(adc_channel <= ADC_CHANNEL_SAMPLE_EIGHTEEN) {
|
||||||
/* the inserted group sequence rank is smaller than eighteen */
|
/* the inserted sequence rank is smaller than eighteen */
|
||||||
sampt = ADC_SAMPT0(adc_periph);
|
sampt = ADC_SAMPT0(adc_periph);
|
||||||
sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (ADC_CHANNEL_SAMPLE_LENGTH * (adc_channel - ADC_CHANNEL_SAMPLE_TEN))));
|
sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (ADC_CHANNEL_SAMPLE_LENGTH * (adc_channel - ADC_CHANNEL_SAMPLE_TEN))));
|
||||||
/* channel sample time set*/
|
/* channel sample time set*/
|
||||||
|
|
@ -590,30 +591,30 @@ void adc_inserted_channel_offset_config(uint32_t adc_periph , uint8_t inserted_c
|
||||||
/*!
|
/*!
|
||||||
\brief configure ADC external trigger source
|
\brief configure ADC external trigger source
|
||||||
\param[in] adc_periph: ADCx,x=0,1,2
|
\param[in] adc_periph: ADCx,x=0,1,2
|
||||||
\param[in] adc_channel_group: select the channel group
|
\param[in] adc_sequence: select the sequence
|
||||||
only one parameter can be selected which is shown as below:
|
only one parameter can be selected which is shown as below:
|
||||||
\arg ADC_REGULAR_CHANNEL: regular channel group
|
\arg ADC_ROUTINE_CHANNEL: routine sequence
|
||||||
\arg ADC_INSERTED_CHANNEL: inserted channel group
|
\arg ADC_INSERTED_CHANNEL: inserted sequence
|
||||||
\param[in] external_trigger_source: regular or inserted group trigger source
|
\param[in] external_trigger_source: routine or inserted sequence trigger source
|
||||||
for regular channel:
|
for routine sequence:
|
||||||
only one parameter can be selected which is shown as below:
|
only one parameter can be selected which is shown as below:
|
||||||
\arg ADC_EXTTRIG_REGULAR_T0_CH0: external trigger timer 0 CC0 event select for regular channel
|
\arg ADC_EXTTRIG_ROUTINE_T0_CH0: external trigger timer 0 CC0 event select for routine sequence
|
||||||
\arg ADC_EXTTRIG_REGULAR_T0_CH1: external trigger timer 0 CC1 event select for regular channel
|
\arg ADC_EXTTRIG_ROUTINE_T0_CH1: external trigger timer 0 CC1 event select for routine sequence
|
||||||
\arg ADC_EXTTRIG_REGULAR_T0_CH2: external trigger timer 0 CC2 event select for regular channel
|
\arg ADC_EXTTRIG_ROUTINE_T0_CH2: external trigger timer 0 CC2 event select for routine sequence
|
||||||
\arg ADC_EXTTRIG_REGULAR_T1_CH1: external trigger timer 1 CC1 event select for regular channel
|
\arg ADC_EXTTRIG_ROUTINE_T1_CH1: external trigger timer 1 CC1 event select for routine sequence
|
||||||
\arg ADC_EXTTRIG_REGULAR_T1_CH2: external trigger timer 1 CC2 event select for regular channel
|
\arg ADC_EXTTRIG_ROUTINE_T1_CH2: external trigger timer 1 CC2 event select for routine sequence
|
||||||
\arg ADC_EXTTRIG_REGULAR_T1_CH3: external trigger timer 1 CC3 event select for regular channel
|
\arg ADC_EXTTRIG_ROUTINE_T1_CH3: external trigger timer 1 CC3 event select for routine sequence
|
||||||
\arg ADC_EXTTRIG_REGULAR_T1_TRGO: external trigger timer 1 TRGO event select for regular channel
|
\arg ADC_EXTTRIG_ROUTINE_T1_TRGO: external trigger timer 1 TRGO event select for routine sequence
|
||||||
\arg ADC_EXTTRIG_REGULAR_T2_CH0 : external trigger timer 2 CC0 event select for regular channel
|
\arg ADC_EXTTRIG_ROUTINE_T2_CH0 : external trigger timer 2 CC0 event select for routine sequence
|
||||||
\arg ADC_EXTTRIG_REGULAR_T2_TRGO : external trigger timer 2 TRGO event select for regular channel
|
\arg ADC_EXTTRIG_ROUTINE_T2_TRGO : external trigger timer 2 TRGO event select for routine sequence
|
||||||
\arg ADC_EXTTRIG_REGULAR_T3_CH3: external trigger timer 3 CC3 event select for regular channel
|
\arg ADC_EXTTRIG_ROUTINE_T3_CH3: external trigger timer 3 CC3 event select for routine sequence
|
||||||
\arg ADC_EXTTRIG_REGULAR_T4_CH0: external trigger timer 4 CC0 event select for regular channel
|
\arg ADC_EXTTRIG_ROUTINE_T4_CH0: external trigger timer 4 CC0 event select for routine sequence
|
||||||
\arg ADC_EXTTRIG_REGULAR_T4_CH1: external trigger timer 4 CC1 event select for regular channel
|
\arg ADC_EXTTRIG_ROUTINE_T4_CH1: external trigger timer 4 CC1 event select for routine sequence
|
||||||
\arg ADC_EXTTRIG_REGULAR_T4_CH2: external trigger timer 4 CC2 event select for regular channel
|
\arg ADC_EXTTRIG_ROUTINE_T4_CH2: external trigger timer 4 CC2 event select for routine sequence
|
||||||
\arg ADC_EXTTRIG_REGULAR_T7_CH0: external trigger timer 7 CC0 event select for regular channel
|
\arg ADC_EXTTRIG_ROUTINE_T7_CH0: external trigger timer 7 CC0 event select for routine sequence
|
||||||
\arg ADC_EXTTRIG_REGULAR_T7_TRGO: external trigger timer 7 TRGO event select for regular channel
|
\arg ADC_EXTTRIG_ROUTINE_T7_TRGO: external trigger timer 7 TRGO event select for routine sequence
|
||||||
\arg ADC_EXTTRIG_REGULAR_EXTI_11: external trigger extiline 11 select for regular channel
|
\arg ADC_EXTTRIG_ROUTINE_EXTI_11: external trigger extiline 11 select for routine sequence
|
||||||
for inserted channel:
|
for inserted sequence:
|
||||||
only one parameter can be selected which is shown as below:
|
only one parameter can be selected which is shown as below:
|
||||||
\arg ADC_EXTTRIG_INSERTED_T0_CH3: timer0 capture compare 3
|
\arg ADC_EXTTRIG_INSERTED_T0_CH3: timer0 capture compare 3
|
||||||
\arg ADC_EXTTRIG_INSERTED_T0_TRGO: timer0 TRGO event
|
\arg ADC_EXTTRIG_INSERTED_T0_TRGO: timer0 TRGO event
|
||||||
|
|
@ -634,16 +635,16 @@ void adc_inserted_channel_offset_config(uint32_t adc_periph , uint8_t inserted_c
|
||||||
\param[out] none
|
\param[out] none
|
||||||
\retval none
|
\retval none
|
||||||
*/
|
*/
|
||||||
void adc_external_trigger_source_config(uint32_t adc_periph , uint8_t adc_channel_group , uint32_t external_trigger_source)
|
void adc_external_trigger_source_config(uint32_t adc_periph, uint8_t adc_sequence, uint32_t external_trigger_source)
|
||||||
{
|
{
|
||||||
switch(adc_channel_group){
|
switch(adc_sequence) {
|
||||||
case ADC_REGULAR_CHANNEL:
|
case ADC_ROUTINE_CHANNEL:
|
||||||
/* configure ADC regular group external trigger source */
|
/* configure ADC routine sequence external trigger source */
|
||||||
ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_ETSRC);
|
ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_ETSRC);
|
||||||
ADC_CTL1(adc_periph) |= (uint32_t)external_trigger_source;
|
ADC_CTL1(adc_periph) |= (uint32_t)external_trigger_source;
|
||||||
break;
|
break;
|
||||||
case ADC_INSERTED_CHANNEL:
|
case ADC_INSERTED_CHANNEL:
|
||||||
/* configure ADC inserted group external trigger source */
|
/* configure ADC inserted sequence external trigger source */
|
||||||
ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_ETSIC);
|
ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_ETSIC);
|
||||||
ADC_CTL1(adc_periph) |= (uint32_t)external_trigger_source;
|
ADC_CTL1(adc_periph) |= (uint32_t)external_trigger_source;
|
||||||
break;
|
break;
|
||||||
|
|
@ -655,10 +656,10 @@ void adc_external_trigger_source_config(uint32_t adc_periph , uint8_t adc_channe
|
||||||
/*!
|
/*!
|
||||||
\brief enable ADC external trigger
|
\brief enable ADC external trigger
|
||||||
\param[in] adc_periph: ADCx,x=0,1,2
|
\param[in] adc_periph: ADCx,x=0,1,2
|
||||||
\param[in] adc_channel_group: select the channel group
|
\param[in] adc_sequence: select the sequence
|
||||||
only one parameter can be selected which is shown as below:
|
only one parameter can be selected which is shown as below:
|
||||||
\arg ADC_REGULAR_CHANNEL: regular channel group
|
\arg ADC_ROUTINE_CHANNEL: routine sequence
|
||||||
\arg ADC_INSERTED_CHANNEL: inserted channel group
|
\arg ADC_INSERTED_CHANNEL: inserted sequence
|
||||||
\param[in] trigger_mode: external trigger mode
|
\param[in] trigger_mode: external trigger mode
|
||||||
only one parameter can be selected which is shown as below:
|
only one parameter can be selected which is shown as below:
|
||||||
\arg EXTERNAL_TRIGGER_DISABLE: external trigger disable
|
\arg EXTERNAL_TRIGGER_DISABLE: external trigger disable
|
||||||
|
|
@ -668,16 +669,16 @@ void adc_external_trigger_source_config(uint32_t adc_periph , uint8_t adc_channe
|
||||||
\param[out] none
|
\param[out] none
|
||||||
\retval none
|
\retval none
|
||||||
*/
|
*/
|
||||||
void adc_external_trigger_config(uint32_t adc_periph , uint8_t adc_channel_group , uint32_t trigger_mode)
|
void adc_external_trigger_config(uint32_t adc_periph, uint8_t adc_sequence, uint32_t trigger_mode)
|
||||||
{
|
{
|
||||||
switch(adc_channel_group){
|
switch(adc_sequence) {
|
||||||
case ADC_REGULAR_CHANNEL:
|
case ADC_ROUTINE_CHANNEL:
|
||||||
/* configure ADC regular channel group external trigger mode */
|
/* configure ADC routine sequence external trigger mode */
|
||||||
ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_ETMRC);
|
ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_ETMRC);
|
||||||
ADC_CTL1(adc_periph) |= (uint32_t) (trigger_mode << REGULAR_TRIGGER_MODE);
|
ADC_CTL1(adc_periph) |= (uint32_t)(trigger_mode << ROUTINE_TRIGGER_MODE);
|
||||||
break;
|
break;
|
||||||
case ADC_INSERTED_CHANNEL:
|
case ADC_INSERTED_CHANNEL:
|
||||||
/* configure ADC inserted channel group external trigger mode */
|
/* configure ADC inserted sequence external trigger mode */
|
||||||
ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_ETMIC);
|
ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_ETMIC);
|
||||||
ADC_CTL1(adc_periph) |= (uint32_t)(trigger_mode << INSERTED_TRIGGER_MODE);
|
ADC_CTL1(adc_periph) |= (uint32_t)(trigger_mode << INSERTED_TRIGGER_MODE);
|
||||||
break;
|
break;
|
||||||
|
|
@ -689,22 +690,22 @@ void adc_external_trigger_config(uint32_t adc_periph , uint8_t adc_channel_group
|
||||||
/*!
|
/*!
|
||||||
\brief enable ADC software trigger
|
\brief enable ADC software trigger
|
||||||
\param[in] adc_periph: ADCx,x=0,1,2
|
\param[in] adc_periph: ADCx,x=0,1,2
|
||||||
\param[in] adc_channel_group: select the channel group
|
\param[in] adc_sequence: select the sequence
|
||||||
only one parameter can be selected which is shown as below:
|
only one parameter can be selected which is shown as below:
|
||||||
\arg ADC_REGULAR_CHANNEL: regular channel group
|
\arg ADC_ROUTINE_CHANNEL: routine sequence
|
||||||
\arg ADC_INSERTED_CHANNEL: inserted channel group
|
\arg ADC_INSERTED_CHANNEL: inserted sequence
|
||||||
\param[out] none
|
\param[out] none
|
||||||
\retval none
|
\retval none
|
||||||
*/
|
*/
|
||||||
void adc_software_trigger_enable(uint32_t adc_periph , uint8_t adc_channel_group)
|
void adc_software_trigger_enable(uint32_t adc_periph, uint8_t adc_sequence)
|
||||||
{
|
{
|
||||||
switch(adc_channel_group){
|
switch(adc_sequence) {
|
||||||
case ADC_REGULAR_CHANNEL:
|
case ADC_ROUTINE_CHANNEL:
|
||||||
/* enable ADC regular channel group software trigger */
|
/* enable ADC routine sequence software trigger */
|
||||||
ADC_CTL1(adc_periph) |= (uint32_t)ADC_CTL1_SWRCST;
|
ADC_CTL1(adc_periph) |= (uint32_t)ADC_CTL1_SWRCST;
|
||||||
break;
|
break;
|
||||||
case ADC_INSERTED_CHANNEL:
|
case ADC_INSERTED_CHANNEL:
|
||||||
/* enable ADC inserted channel group software trigger */
|
/* enable ADC inserted sequence software trigger */
|
||||||
ADC_CTL1(adc_periph) |= (uint32_t)ADC_CTL1_SWICST;
|
ADC_CTL1(adc_periph) |= (uint32_t)ADC_CTL1_SWICST;
|
||||||
break;
|
break;
|
||||||
default:
|
default:
|
||||||
|
|
@ -717,8 +718,8 @@ void adc_software_trigger_enable(uint32_t adc_periph , uint8_t adc_channel_group
|
||||||
\param[in] adc_periph: ADCx,x=0,1,2
|
\param[in] adc_periph: ADCx,x=0,1,2
|
||||||
\param[in] end_selection: end of conversion mode
|
\param[in] end_selection: end of conversion mode
|
||||||
only one parameter can be selected which is shown as below:
|
only one parameter can be selected which is shown as below:
|
||||||
\arg ADC_EOC_SET_SEQUENCE: only at the end of a sequence of regular conversions, the EOC bit is set.Overflow detection is disabled unless DMA=1.
|
\arg ADC_EOC_SET_SEQUENCE: only at the end of a sequence of routine conversions, the EOC bit is set.Overflow detection is disabled unless DMA=1.
|
||||||
\arg ADC_EOC_SET_CONVERSION: at the end of each regular conversion, the EOC bit is set.Overflow is detected automatically.
|
\arg ADC_EOC_SET_CONVERSION: at the end of each routine conversion, the EOC bit is set.Overflow is detected automatically.
|
||||||
\param[out] none
|
\param[out] none
|
||||||
\retval none
|
\retval none
|
||||||
*/
|
*/
|
||||||
|
|
@ -726,11 +727,11 @@ void adc_end_of_conversion_config(uint32_t adc_periph , uint8_t end_selection)
|
||||||
{
|
{
|
||||||
switch(end_selection) {
|
switch(end_selection) {
|
||||||
case ADC_EOC_SET_SEQUENCE:
|
case ADC_EOC_SET_SEQUENCE:
|
||||||
/* only at the end of a sequence of regular conversions, the EOC bit is set */
|
/* only at the end of a sequence of routine conversions, the EOC bit is set */
|
||||||
ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_EOCM);
|
ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_EOCM);
|
||||||
break;
|
break;
|
||||||
case ADC_EOC_SET_CONVERSION:
|
case ADC_EOC_SET_CONVERSION:
|
||||||
/* at the end of each regular conversion, the EOC bit is set.Overflow is detected automatically */
|
/* at the end of each routine conversion, the EOC bit is set.Overflow is detected automatically */
|
||||||
ADC_CTL1(adc_periph) |= (uint32_t)(ADC_CTL1_EOCM);
|
ADC_CTL1(adc_periph) |= (uint32_t)(ADC_CTL1_EOCM);
|
||||||
break;
|
break;
|
||||||
default:
|
default:
|
||||||
|
|
@ -739,26 +740,26 @@ void adc_end_of_conversion_config(uint32_t adc_periph , uint8_t end_selection)
|
||||||
}
|
}
|
||||||
|
|
||||||
/*!
|
/*!
|
||||||
\brief read ADC regular group data register
|
\brief read ADC routine data register
|
||||||
\param[in] adc_periph: ADCx,x=0,1,2
|
\param[in] adc_periph: ADCx,x=0,1,2
|
||||||
\param[in] none
|
\param[in] none
|
||||||
\param[out] none
|
\param[out] none
|
||||||
\retval the conversion value
|
\retval the conversion value
|
||||||
*/
|
*/
|
||||||
uint16_t adc_regular_data_read(uint32_t adc_periph)
|
uint16_t adc_routine_data_read(uint32_t adc_periph)
|
||||||
{
|
{
|
||||||
return (uint16_t)(ADC_RDATA(adc_periph));
|
return (uint16_t)(ADC_RDATA(adc_periph));
|
||||||
}
|
}
|
||||||
|
|
||||||
/*!
|
/*!
|
||||||
\brief read ADC inserted group data register
|
\brief read ADC inserted data register
|
||||||
\param[in] adc_periph: ADCx,x=0,1,2
|
\param[in] adc_periph: ADCx,x=0,1,2
|
||||||
\param[in] inserted_channel : insert channel select
|
\param[in] inserted_channel : insert channel select
|
||||||
only one parameter can be selected which is shown as below:
|
only one parameter can be selected which is shown as below:
|
||||||
\arg ADC_INSERTED_CHANNEL_0: inserted Channel0
|
\arg ADC_INSERTED_CHANNEL_0: inserted channel0
|
||||||
\arg ADC_INSERTED_CHANNEL_1: inserted channel1
|
\arg ADC_INSERTED_CHANNEL_1: inserted channel1
|
||||||
\arg ADC_INSERTED_CHANNEL_2: inserted Channel2
|
\arg ADC_INSERTED_CHANNEL_2: inserted channel2
|
||||||
\arg ADC_INSERTED_CHANNEL_3: inserted Channel3
|
\arg ADC_INSERTED_CHANNEL_3: inserted channel3
|
||||||
\param[out] none
|
\param[out] none
|
||||||
\retval the conversion value
|
\retval the conversion value
|
||||||
*/
|
*/
|
||||||
|
|
@ -820,31 +821,31 @@ void adc_watchdog_single_channel_enable(uint32_t adc_periph , uint8_t adc_channe
|
||||||
}
|
}
|
||||||
|
|
||||||
/*!
|
/*!
|
||||||
\brief configure ADC analog watchdog group channel
|
\brief configure ADC analog watchdog sequence channel
|
||||||
\param[in] adc_periph: ADCx,x=0,1,2
|
\param[in] adc_periph: ADCx,x=0,1,2
|
||||||
\param[in] adc_channel_group: the channel group use analog watchdog
|
\param[in] adc_sequence: the sequence use analog watchdog
|
||||||
only one parameter can be selected which is shown as below:
|
only one parameter can be selected which is shown as below:
|
||||||
\arg ADC_REGULAR_CHANNEL: regular channel group
|
\arg ADC_ROUTINE_CHANNEL: routine sequence
|
||||||
\arg ADC_INSERTED_CHANNEL: inserted channel group
|
\arg ADC_INSERTED_CHANNEL: inserted sequence
|
||||||
\arg ADC_REGULAR_INSERTED_CHANNEL: both regular and inserted group
|
\arg ADC_ROUTINE_INSERTED_CHANNEL: both routine and inserted sequence
|
||||||
\param[out] none
|
\param[out] none
|
||||||
\retval none
|
\retval none
|
||||||
*/
|
*/
|
||||||
void adc_watchdog_group_channel_enable(uint32_t adc_periph , uint8_t adc_channel_group)
|
void adc_watchdog_sequence_channel_enable(uint32_t adc_periph, uint8_t adc_sequence)
|
||||||
{
|
{
|
||||||
ADC_CTL0(adc_periph) &= ~((uint32_t)(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC));
|
ADC_CTL0(adc_periph) &= ~((uint32_t)(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC));
|
||||||
/* select the group */
|
/* select the sequence */
|
||||||
switch(adc_channel_group){
|
switch(adc_sequence) {
|
||||||
case ADC_REGULAR_CHANNEL:
|
case ADC_ROUTINE_CHANNEL:
|
||||||
/* regular channel analog watchdog enable */
|
/* routine channel analog watchdog enable */
|
||||||
ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_RWDEN;
|
ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_RWDEN;
|
||||||
break;
|
break;
|
||||||
case ADC_INSERTED_CHANNEL:
|
case ADC_INSERTED_CHANNEL:
|
||||||
/* inserted channel analog watchdog enable */
|
/* inserted channel analog watchdog enable */
|
||||||
ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_IWDEN;
|
ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_IWDEN;
|
||||||
break;
|
break;
|
||||||
case ADC_REGULAR_INSERTED_CHANNEL:
|
case ADC_ROUTINE_INSERTED_CHANNEL:
|
||||||
/* regular and inserted channel analog watchdog enable */
|
/* routine and inserted channel analog watchdog enable */
|
||||||
ADC_CTL0(adc_periph) |= (uint32_t)(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN);
|
ADC_CTL0(adc_periph) |= (uint32_t)(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN);
|
||||||
break;
|
break;
|
||||||
default:
|
default:
|
||||||
|
|
@ -855,28 +856,28 @@ void adc_watchdog_group_channel_enable(uint32_t adc_periph , uint8_t adc_channel
|
||||||
/*!
|
/*!
|
||||||
\brief disable ADC analog watchdog
|
\brief disable ADC analog watchdog
|
||||||
\param[in] adc_periph: ADCx,x=0,1,2
|
\param[in] adc_periph: ADCx,x=0,1,2
|
||||||
\param[in] adc_channel_group: the channel group use analog watchdog
|
\param[in] adc_sequence: the sequence use analog watchdog
|
||||||
only one parameter can be selected which is shown as below:
|
only one parameter can be selected which is shown as below:
|
||||||
\arg ADC_REGULAR_CHANNEL: regular channel group
|
\arg ADC_ROUTINE_CHANNEL: routine sequence
|
||||||
\arg ADC_INSERTED_CHANNEL: inserted channel group
|
\arg ADC_INSERTED_CHANNEL: inserted sequence
|
||||||
\arg ADC_REGULAR_INSERTED_CHANNEL: both regular and inserted group
|
\arg ADC_ROUTINE_INSERTED_CHANNEL: both routine and inserted sequence
|
||||||
\param[out] none
|
\param[out] none
|
||||||
\retval none
|
\retval none
|
||||||
*/
|
*/
|
||||||
void adc_watchdog_disable(uint32_t adc_periph , uint8_t adc_channel_group)
|
void adc_watchdog_disable(uint32_t adc_periph, uint8_t adc_sequence)
|
||||||
{
|
{
|
||||||
/* select the group */
|
/* select the sequence */
|
||||||
switch(adc_channel_group){
|
switch(adc_sequence) {
|
||||||
case ADC_REGULAR_CHANNEL:
|
case ADC_ROUTINE_CHANNEL:
|
||||||
/* disable ADC analog watchdog regular channel group */
|
/* disable ADC analog watchdog routine sequence */
|
||||||
ADC_CTL0(adc_periph) &= ~((uint32_t)ADC_CTL0_RWDEN);
|
ADC_CTL0(adc_periph) &= ~((uint32_t)ADC_CTL0_RWDEN);
|
||||||
break;
|
break;
|
||||||
case ADC_INSERTED_CHANNEL:
|
case ADC_INSERTED_CHANNEL:
|
||||||
/* disable ADC analog watchdog inserted channel group */
|
/* disable ADC analog watchdog inserted sequence */
|
||||||
ADC_CTL0(adc_periph) &= ~((uint32_t)ADC_CTL0_IWDEN);
|
ADC_CTL0(adc_periph) &= ~((uint32_t)ADC_CTL0_IWDEN);
|
||||||
break;
|
break;
|
||||||
case ADC_REGULAR_INSERTED_CHANNEL:
|
case ADC_ROUTINE_INSERTED_CHANNEL:
|
||||||
/* disable ADC analog watchdog regular and inserted channel group */
|
/* disable ADC analog watchdog routine and inserted sequence */
|
||||||
ADC_CTL0(adc_periph) &= ~((uint32_t)(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN));
|
ADC_CTL0(adc_periph) &= ~((uint32_t)(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN));
|
||||||
break;
|
break;
|
||||||
default:
|
default:
|
||||||
|
|
@ -906,11 +907,11 @@ void adc_watchdog_threshold_config(uint32_t adc_periph , uint16_t low_threshold
|
||||||
\param[in] adc_flag: the adc flag bits
|
\param[in] adc_flag: the adc flag bits
|
||||||
only one parameter can be selected which is shown as below:
|
only one parameter can be selected which is shown as below:
|
||||||
\arg ADC_FLAG_WDE: analog watchdog event flag
|
\arg ADC_FLAG_WDE: analog watchdog event flag
|
||||||
\arg ADC_FLAG_EOC: end of group conversion flag
|
\arg ADC_FLAG_EOC: end of sequence conversion flag
|
||||||
\arg ADC_FLAG_EOIC: end of inserted group conversion flag
|
\arg ADC_FLAG_EOIC: end of inserted sequence conversion flag
|
||||||
\arg ADC_FLAG_STIC: start flag of inserted channel group
|
\arg ADC_FLAG_STIC: start flag of inserted sequence
|
||||||
\arg ADC_FLAG_STRC: start flag of regular channel group
|
\arg ADC_FLAG_STRC: start flag of routine sequence
|
||||||
\arg ADC_FLAG_ROVF: regular data register overflow flag
|
\arg ADC_FLAG_ROVF: routine data register overflow flag
|
||||||
\param[out] none
|
\param[out] none
|
||||||
\retval FlagStatus: SET or RESET
|
\retval FlagStatus: SET or RESET
|
||||||
*/
|
*/
|
||||||
|
|
@ -930,11 +931,11 @@ FlagStatus adc_flag_get(uint32_t adc_periph , uint32_t adc_flag)
|
||||||
\param[in] adc_flag: the adc flag bits
|
\param[in] adc_flag: the adc flag bits
|
||||||
only one parameter can be selected which is shown as below:
|
only one parameter can be selected which is shown as below:
|
||||||
\arg ADC_FLAG_WDE: analog watchdog event flag
|
\arg ADC_FLAG_WDE: analog watchdog event flag
|
||||||
\arg ADC_FLAG_EOC: end of group conversion flag
|
\arg ADC_FLAG_EOC: end of sequence conversion flag
|
||||||
\arg ADC_FLAG_EOIC: end of inserted group conversion flag
|
\arg ADC_FLAG_EOIC: end of inserted sequence conversion flag
|
||||||
\arg ADC_FLAG_STIC: start flag of inserted channel group
|
\arg ADC_FLAG_STIC: start flag of inserted sequence
|
||||||
\arg ADC_FLAG_STRC: start flag of regular channel group
|
\arg ADC_FLAG_STRC: start flag of routine sequence
|
||||||
\arg ADC_FLAG_ROVF: regular data register overflow flag
|
\arg ADC_FLAG_ROVF: routine data register overflow flag
|
||||||
\param[out] none
|
\param[out] none
|
||||||
\retval none
|
\retval none
|
||||||
*/
|
*/
|
||||||
|
|
@ -950,7 +951,7 @@ void adc_flag_clear(uint32_t adc_periph , uint32_t adc_flag)
|
||||||
\param[out] none
|
\param[out] none
|
||||||
\retval FlagStatus: SET or RESET
|
\retval FlagStatus: SET or RESET
|
||||||
*/
|
*/
|
||||||
FlagStatus adc_regular_software_startconv_flag_get(uint32_t adc_periph)
|
FlagStatus adc_routine_software_startconv_flag_get(uint32_t adc_periph)
|
||||||
{
|
{
|
||||||
FlagStatus reval = RESET;
|
FlagStatus reval = RESET;
|
||||||
if((uint32_t)RESET != (ADC_STAT(adc_periph) & ADC_STAT_STRC)) {
|
if((uint32_t)RESET != (ADC_STAT(adc_periph) & ADC_STAT_STRC)) {
|
||||||
|
|
@ -981,9 +982,9 @@ FlagStatus adc_inserted_software_startconv_flag_get(uint32_t adc_periph)
|
||||||
\param[in] adc_interrupt: the adc interrupt bits
|
\param[in] adc_interrupt: the adc interrupt bits
|
||||||
only one parameter can be selected which is shown as below:
|
only one parameter can be selected which is shown as below:
|
||||||
\arg ADC_INT_FLAG_WDE: analog watchdog interrupt
|
\arg ADC_INT_FLAG_WDE: analog watchdog interrupt
|
||||||
\arg ADC_INT_FLAG_EOC: end of group conversion interrupt
|
\arg ADC_INT_FLAG_EOC: end of sequence conversion interrupt
|
||||||
\arg ADC_INT_FLAG_EOIC: end of inserted group conversion interrupt
|
\arg ADC_INT_FLAG_EOIC: end of inserted sequence conversion interrupt
|
||||||
\arg ADC_INT_FLAG_ROVF: regular data register overflow interrupt
|
\arg ADC_INT_FLAG_ROVF: routine data register overflow interrupt
|
||||||
\param[out] none
|
\param[out] none
|
||||||
\retval FlagStatus: SET or RESET
|
\retval FlagStatus: SET or RESET
|
||||||
*/
|
*/
|
||||||
|
|
@ -1001,21 +1002,21 @@ FlagStatus adc_interrupt_flag_get(uint32_t adc_periph , uint32_t adc_interrupt)
|
||||||
}
|
}
|
||||||
break;
|
break;
|
||||||
case ADC_INT_FLAG_EOC:
|
case ADC_INT_FLAG_EOC:
|
||||||
/* get the ADC end of group conversion interrupt bits */
|
/* get the ADC end of sequence conversion interrupt bits */
|
||||||
state = ADC_STAT(adc_periph) & ADC_STAT_EOC;
|
state = ADC_STAT(adc_periph) & ADC_STAT_EOC;
|
||||||
if((ADC_CTL0(adc_periph) & ADC_CTL0_EOCIE) && state) {
|
if((ADC_CTL0(adc_periph) & ADC_CTL0_EOCIE) && state) {
|
||||||
interrupt_flag = SET;
|
interrupt_flag = SET;
|
||||||
}
|
}
|
||||||
break;
|
break;
|
||||||
case ADC_INT_FLAG_EOIC:
|
case ADC_INT_FLAG_EOIC:
|
||||||
/* get the ADC end of inserted group conversion interrupt bits */
|
/* get the ADC end of inserted sequence conversion interrupt bits */
|
||||||
state = ADC_STAT(adc_periph) & ADC_STAT_EOIC;
|
state = ADC_STAT(adc_periph) & ADC_STAT_EOIC;
|
||||||
if((ADC_CTL0(adc_periph) & ADC_CTL0_EOICIE) && state) {
|
if((ADC_CTL0(adc_periph) & ADC_CTL0_EOICIE) && state) {
|
||||||
interrupt_flag = SET;
|
interrupt_flag = SET;
|
||||||
}
|
}
|
||||||
break;
|
break;
|
||||||
case ADC_INT_FLAG_ROVF:
|
case ADC_INT_FLAG_ROVF:
|
||||||
/* get the ADC regular data register overflow interrupt bits */
|
/* get the ADC routine data register overflow interrupt bits */
|
||||||
state = ADC_STAT(adc_periph) & ADC_STAT_ROVF;
|
state = ADC_STAT(adc_periph) & ADC_STAT_ROVF;
|
||||||
if((ADC_CTL0(adc_periph) & ADC_CTL0_ROVFIE) && state) {
|
if((ADC_CTL0(adc_periph) & ADC_CTL0_ROVFIE) && state) {
|
||||||
interrupt_flag = SET;
|
interrupt_flag = SET;
|
||||||
|
|
@ -1033,9 +1034,9 @@ FlagStatus adc_interrupt_flag_get(uint32_t adc_periph , uint32_t adc_interrupt)
|
||||||
\param[in] adc_interrupt: the adc status flag
|
\param[in] adc_interrupt: the adc status flag
|
||||||
only one parameter can be selected which is shown as below:
|
only one parameter can be selected which is shown as below:
|
||||||
\arg ADC_INT_FLAG_WDE: analog watchdog interrupt
|
\arg ADC_INT_FLAG_WDE: analog watchdog interrupt
|
||||||
\arg ADC_INT_FLAG_EOC: end of group conversion interrupt
|
\arg ADC_INT_FLAG_EOC: end of sequence conversion interrupt
|
||||||
\arg ADC_INT_FLAG_EOIC: end of inserted group conversion interrupt
|
\arg ADC_INT_FLAG_EOIC: end of inserted sequence conversion interrupt
|
||||||
\arg ADC_INT_FLAG_ROVF: regular data register overflow interrupt
|
\arg ADC_INT_FLAG_ROVF: routine data register overflow interrupt
|
||||||
\param[out] none
|
\param[out] none
|
||||||
\retval none
|
\retval none
|
||||||
*/
|
*/
|
||||||
|
|
@ -1050,9 +1051,9 @@ void adc_interrupt_flag_clear(uint32_t adc_periph , uint32_t adc_interrupt)
|
||||||
\param[in] adc_interrupt: the adc interrupt flag
|
\param[in] adc_interrupt: the adc interrupt flag
|
||||||
only one parameter can be selected which is shown as below:
|
only one parameter can be selected which is shown as below:
|
||||||
\arg ADC_INT_WDE: analog watchdog interrupt flag
|
\arg ADC_INT_WDE: analog watchdog interrupt flag
|
||||||
\arg ADC_INT_EOC: end of group conversion interrupt flag
|
\arg ADC_INT_EOC: end of sequence conversion interrupt flag
|
||||||
\arg ADC_INT_EOIC: end of inserted group conversion interrupt flag
|
\arg ADC_INT_EOIC: end of inserted sequence conversion interrupt flag
|
||||||
\arg ADC_INT_ROVF: regular data register overflow interrupt flag
|
\arg ADC_INT_ROVF: routine data register overflow interrupt flag
|
||||||
\param[out] none
|
\param[out] none
|
||||||
\retval none
|
\retval none
|
||||||
*/
|
*/
|
||||||
|
|
@ -1064,11 +1065,11 @@ void adc_interrupt_enable(uint32_t adc_periph , uint32_t adc_interrupt)
|
||||||
ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_WDEIE;
|
ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_WDEIE;
|
||||||
break;
|
break;
|
||||||
case ADC_INT_EOC:
|
case ADC_INT_EOC:
|
||||||
/* enable end of group conversion interrupt */
|
/* enable end of sequence conversion interrupt */
|
||||||
ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_EOCIE;
|
ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_EOCIE;
|
||||||
break;
|
break;
|
||||||
case ADC_INT_EOIC:
|
case ADC_INT_EOIC:
|
||||||
/* enable end of inserted group conversion interrupt */
|
/* enable end of inserted sequence conversion interrupt */
|
||||||
ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_EOICIE;
|
ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_EOICIE;
|
||||||
break;
|
break;
|
||||||
case ADC_INT_ROVF:
|
case ADC_INT_ROVF:
|
||||||
|
|
@ -1085,9 +1086,9 @@ void adc_interrupt_enable(uint32_t adc_periph , uint32_t adc_interrupt)
|
||||||
\param[in] adc_flag: the adc interrupt flag
|
\param[in] adc_flag: the adc interrupt flag
|
||||||
only one parameter can be selected which is shown as below:
|
only one parameter can be selected which is shown as below:
|
||||||
\arg ADC_INT_WDE: analog watchdog interrupt flag
|
\arg ADC_INT_WDE: analog watchdog interrupt flag
|
||||||
\arg ADC_INT_EOC: end of group conversion interrupt flag
|
\arg ADC_INT_EOC: end of sequence conversion interrupt flag
|
||||||
\arg ADC_INT_EOIC: end of inserted group conversion interrupt flag
|
\arg ADC_INT_EOIC: end of inserted sequence conversion interrupt flag
|
||||||
\arg ADC_INT_ROVF: regular data register overflow interrupt flag
|
\arg ADC_INT_ROVF: routine data register overflow interrupt flag
|
||||||
\param[out] none
|
\param[out] none
|
||||||
\retval none
|
\retval none
|
||||||
*/
|
*/
|
||||||
|
|
@ -1117,17 +1118,17 @@ void adc_interrupt_disable(uint32_t adc_periph , uint32_t adc_interrupt)
|
||||||
\param[in] sync_mode: ADC sync mode
|
\param[in] sync_mode: ADC sync mode
|
||||||
only one parameter can be selected which is shown as below:
|
only one parameter can be selected which is shown as below:
|
||||||
\arg ADC_SYNC_MODE_INDEPENDENT: all the ADCs work independently
|
\arg ADC_SYNC_MODE_INDEPENDENT: all the ADCs work independently
|
||||||
\arg ADC_DAUL_REGULAL_PARALLEL_INSERTED_PARALLEL: ADC0 and ADC1 work in combined regular parallel & inserted parallel mode
|
\arg ADC_DAUL_ROUTINE_PARALLEL_INSERTED_PARALLEL: ADC0 and ADC1 work in combined routine parallel & inserted parallel mode
|
||||||
\arg ADC_DAUL_REGULAL_PARALLEL_INSERTED_ROTATION: ADC0 and ADC1 work in combined regular parallel & trigger rotation mode
|
\arg ADC_DAUL_ROUTINE_PARALLEL_INSERTED_ROTATION: ADC0 and ADC1 work in combined routine parallel & trigger rotation mode
|
||||||
\arg ADC_DAUL_INSERTED_PARALLEL: ADC0 and ADC1 work in inserted parallel mode
|
\arg ADC_DAUL_INSERTED_PARALLEL: ADC0 and ADC1 work in inserted parallel mode
|
||||||
\arg ADC_DAUL_REGULAL_PARALLEL: ADC0 and ADC1 work in regular parallel mode
|
\arg ADC_DAUL_ROUTINE_PARALLEL: ADC0 and ADC1 work in routine parallel mode
|
||||||
\arg ADC_DAUL_REGULAL_FOLLOW_UP: ADC0 and ADC1 work in follow-up mode
|
\arg ADC_DAUL_ROUTINE_FOLLOW_UP: ADC0 and ADC1 work in follow-up mode
|
||||||
\arg ADC_DAUL_INSERTED_TRRIGGER_ROTATION: ADC0 and ADC1 work in trigger rotation mode
|
\arg ADC_DAUL_INSERTED_TRRIGGER_ROTATION: ADC0 and ADC1 work in trigger rotation mode
|
||||||
\arg ADC_ALL_REGULAL_PARALLEL_INSERTED_PARALLEL: all ADCs work in combined regular parallel & inserted parallel mode
|
\arg ADC_ALL_ROUTINE_PARALLEL_INSERTED_PARALLEL: all ADCs work in combined routine parallel & inserted parallel mode
|
||||||
\arg ADC_ALL_REGULAL_PARALLEL_INSERTED_ROTATION: all ADCs work in combined regular parallel & trigger rotation mode
|
\arg ADC_ALL_ROUTINE_PARALLEL_INSERTED_ROTATION: all ADCs work in combined routine parallel & trigger rotation mode
|
||||||
\arg ADC_ALL_INSERTED_PARALLEL: all ADCs work in inserted parallel mode
|
\arg ADC_ALL_INSERTED_PARALLEL: all ADCs work in inserted parallel mode
|
||||||
\arg ADC_ALL_REGULAL_PARALLEL: all ADCs work in regular parallel mode
|
\arg ADC_ALL_ROUTINE_PARALLEL: all ADCs work in routine parallel mode
|
||||||
\arg ADC_ALL_REGULAL_FOLLOW_UP: all ADCs work in follow-up mode
|
\arg ADC_ALL_ROUTINE_FOLLOW_UP: all ADCs work in follow-up mode
|
||||||
\arg ADC_ALL_INSERTED_TRRIGGER_ROTATION: all ADCs work in trigger rotation mode
|
\arg ADC_ALL_INSERTED_TRRIGGER_ROTATION: all ADCs work in trigger rotation mode
|
||||||
\param[out] none
|
\param[out] none
|
||||||
\retval none
|
\retval none
|
||||||
|
|
@ -1191,12 +1192,12 @@ void adc_sync_dma_request_after_last_disable(void)
|
||||||
}
|
}
|
||||||
|
|
||||||
/*!
|
/*!
|
||||||
\brief read ADC sync regular data register
|
\brief read ADC sync routine data register
|
||||||
\param[in] none
|
\param[in] none
|
||||||
\param[out] none
|
\param[out] none
|
||||||
\retval sync regular data
|
\retval sync routine data
|
||||||
*/
|
*/
|
||||||
uint32_t adc_sync_regular_data_read(void)
|
uint32_t adc_sync_routine_data_read(void)
|
||||||
{
|
{
|
||||||
return (uint32_t)ADC_SYNCDATA;
|
return (uint32_t)ADC_SYNCDATA;
|
||||||
}
|
}
|
||||||
|
|
|
||||||
|
|
@ -7,10 +7,12 @@
|
||||||
\version 2019-11-27, V2.0.1, firmware for GD32F4xx
|
\version 2019-11-27, V2.0.1, firmware for GD32F4xx
|
||||||
\version 2020-07-14, V2.0.2, firmware for GD32F4xx
|
\version 2020-07-14, V2.0.2, firmware for GD32F4xx
|
||||||
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
||||||
|
\version 2021-12-28, V2.1.1, firmware for GD32F4xx
|
||||||
|
\version 2022-03-09, V3.0.0, firmware for GD32F4xx
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/*
|
/*
|
||||||
Copyright (c) 2020, GigaDevice Semiconductor Inc.
|
Copyright (c) 2022, GigaDevice Semiconductor Inc.
|
||||||
|
|
||||||
Redistribution and use in source and binary forms, with or without modification,
|
Redistribution and use in source and binary forms, with or without modification,
|
||||||
are permitted provided that the following conditions are met:
|
are permitted provided that the following conditions are met:
|
||||||
|
|
@ -37,6 +39,7 @@ OF SUCH DAMAGE.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#include "gd32f4xx_can.h"
|
#include "gd32f4xx_can.h"
|
||||||
|
#include <stdlib.h>
|
||||||
|
|
||||||
#define CAN_ERROR_HANDLE(s) do{}while(1)
|
#define CAN_ERROR_HANDLE(s) do{}while(1)
|
||||||
|
|
||||||
|
|
@ -66,20 +69,23 @@ void can_deinit(uint32_t can_periph)
|
||||||
\arg CAN_FILTER_STRUCT: the CAN filter struct
|
\arg CAN_FILTER_STRUCT: the CAN filter struct
|
||||||
\arg CAN_TX_MESSAGE_STRUCT: the CAN TX message struct
|
\arg CAN_TX_MESSAGE_STRUCT: the CAN TX message struct
|
||||||
\arg CAN_RX_MESSAGE_STRUCT: the CAN RX message struct
|
\arg CAN_RX_MESSAGE_STRUCT: the CAN RX message struct
|
||||||
\param[in] p_struct: the pointer of the specific struct
|
\param[out] p_struct: the pointer of the specific struct
|
||||||
\param[out] none
|
|
||||||
\retval none
|
\retval none
|
||||||
*/
|
*/
|
||||||
void can_struct_para_init(can_struct_type_enum type, void *p_struct)
|
void can_struct_para_init(can_struct_type_enum type, void *p_struct)
|
||||||
{
|
{
|
||||||
uint8_t i;
|
uint8_t i;
|
||||||
|
|
||||||
|
if(NULL == p_struct) {
|
||||||
|
CAN_ERROR_HANDLE("struct parameter can not be NULL \r\n");
|
||||||
|
}
|
||||||
|
|
||||||
/* get type of the struct */
|
/* get type of the struct */
|
||||||
switch(type) {
|
switch(type) {
|
||||||
/* used for can_init() */
|
/* used for can_init() */
|
||||||
case CAN_INIT_STRUCT:
|
case CAN_INIT_STRUCT:
|
||||||
((can_parameter_struct *)p_struct)->auto_bus_off_recovery = DISABLE;
|
((can_parameter_struct *)p_struct)->auto_bus_off_recovery = DISABLE;
|
||||||
((can_parameter_struct*)p_struct)->no_auto_retrans = DISABLE;
|
((can_parameter_struct *)p_struct)->auto_retrans = DISABLE;
|
||||||
((can_parameter_struct *)p_struct)->auto_wake_up = DISABLE;
|
((can_parameter_struct *)p_struct)->auto_wake_up = DISABLE;
|
||||||
((can_parameter_struct *)p_struct)->prescaler = 0x03FFU;
|
((can_parameter_struct *)p_struct)->prescaler = 0x03FFU;
|
||||||
((can_parameter_struct *)p_struct)->rec_fifo_overwrite = DISABLE;
|
((can_parameter_struct *)p_struct)->rec_fifo_overwrite = DISABLE;
|
||||||
|
|
@ -149,7 +155,7 @@ void can_struct_para_init(can_struct_type_enum type, void* p_struct)
|
||||||
\arg time_triggered: ENABLE or DISABLE
|
\arg time_triggered: ENABLE or DISABLE
|
||||||
\arg auto_bus_off_recovery: ENABLE or DISABLE
|
\arg auto_bus_off_recovery: ENABLE or DISABLE
|
||||||
\arg auto_wake_up: ENABLE or DISABLE
|
\arg auto_wake_up: ENABLE or DISABLE
|
||||||
\arg no_auto_retrans: ENABLE or DISABLE
|
\arg auto_retrans: ENABLE or DISABLE
|
||||||
\arg rec_fifo_overwrite: ENABLE or DISABLE
|
\arg rec_fifo_overwrite: ENABLE or DISABLE
|
||||||
\arg trans_fifo_order: ENABLE or DISABLE
|
\arg trans_fifo_order: ENABLE or DISABLE
|
||||||
\arg prescaler: 0x0001 - 0x0400
|
\arg prescaler: 0x0001 - 0x0400
|
||||||
|
|
@ -179,13 +185,14 @@ ErrStatus can_init(uint32_t can_periph, can_parameter_struct* can_parameter_init
|
||||||
BT_BS1((uint32_t)can_parameter_init->time_segment_1) | \
|
BT_BS1((uint32_t)can_parameter_init->time_segment_1) | \
|
||||||
BT_BS2((uint32_t)can_parameter_init->time_segment_2) | \
|
BT_BS2((uint32_t)can_parameter_init->time_segment_2) | \
|
||||||
BT_BAUDPSC(((uint32_t)(can_parameter_init->prescaler) - 1U)));
|
BT_BAUDPSC(((uint32_t)(can_parameter_init->prescaler) - 1U)));
|
||||||
|
|
||||||
/* time trigger communication mode */
|
/* time trigger communication mode */
|
||||||
if(ENABLE == can_parameter_init->time_triggered) {
|
if(ENABLE == can_parameter_init->time_triggered) {
|
||||||
CAN_CTL(can_periph) |= CAN_CTL_TTC;
|
CAN_CTL(can_periph) |= CAN_CTL_TTC;
|
||||||
} else {
|
} else {
|
||||||
CAN_CTL(can_periph) &= ~CAN_CTL_TTC;
|
CAN_CTL(can_periph) &= ~CAN_CTL_TTC;
|
||||||
}
|
}
|
||||||
/* automatic bus-off managment */
|
/* automatic bus-off management */
|
||||||
if(ENABLE == can_parameter_init->auto_bus_off_recovery) {
|
if(ENABLE == can_parameter_init->auto_bus_off_recovery) {
|
||||||
CAN_CTL(can_periph) |= CAN_CTL_ABOR;
|
CAN_CTL(can_periph) |= CAN_CTL_ABOR;
|
||||||
} else {
|
} else {
|
||||||
|
|
@ -197,19 +204,19 @@ ErrStatus can_init(uint32_t can_periph, can_parameter_struct* can_parameter_init
|
||||||
} else {
|
} else {
|
||||||
CAN_CTL(can_periph) &= ~CAN_CTL_AWU;
|
CAN_CTL(can_periph) &= ~CAN_CTL_AWU;
|
||||||
}
|
}
|
||||||
/* automatic retransmission mode disable*/
|
/* automatic retransmission mode */
|
||||||
if(ENABLE == can_parameter_init->no_auto_retrans){
|
if(ENABLE == can_parameter_init->auto_retrans) {
|
||||||
CAN_CTL(can_periph) |= CAN_CTL_ARD;
|
|
||||||
}else{
|
|
||||||
CAN_CTL(can_periph) &= ~CAN_CTL_ARD;
|
CAN_CTL(can_periph) &= ~CAN_CTL_ARD;
|
||||||
}
|
|
||||||
/* receive fifo overwrite mode */
|
|
||||||
if(ENABLE == can_parameter_init->rec_fifo_overwrite){
|
|
||||||
CAN_CTL(can_periph) |= CAN_CTL_RFOD;
|
|
||||||
} else {
|
} else {
|
||||||
CAN_CTL(can_periph) &= ~CAN_CTL_RFOD;
|
CAN_CTL(can_periph) |= CAN_CTL_ARD;
|
||||||
}
|
}
|
||||||
/* transmit fifo order */
|
/* receive FIFO overwrite mode */
|
||||||
|
if(ENABLE == can_parameter_init->rec_fifo_overwrite) {
|
||||||
|
CAN_CTL(can_periph) &= ~CAN_CTL_RFOD;
|
||||||
|
} else {
|
||||||
|
CAN_CTL(can_periph) |= CAN_CTL_RFOD;
|
||||||
|
}
|
||||||
|
/* transmit FIFO order */
|
||||||
if(ENABLE == can_parameter_init->trans_fifo_order) {
|
if(ENABLE == can_parameter_init->trans_fifo_order) {
|
||||||
CAN_CTL(can_periph) |= CAN_CTL_TFO;
|
CAN_CTL(can_periph) |= CAN_CTL_TFO;
|
||||||
} else {
|
} else {
|
||||||
|
|
@ -223,7 +230,7 @@ ErrStatus can_init(uint32_t can_periph, can_parameter_struct* can_parameter_init
|
||||||
timeout--;
|
timeout--;
|
||||||
}
|
}
|
||||||
/* check exit initialize mode */
|
/* check exit initialize mode */
|
||||||
if(CAN_STAT_IWS == (CAN_STAT(can_periph) & CAN_STAT_IWS)){
|
if(0U != timeout) {
|
||||||
flag = SUCCESS;
|
flag = SUCCESS;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
@ -295,9 +302,7 @@ void can_filter_init(can_filter_parameter_struct* can_filter_parameter_init)
|
||||||
if(CAN_FIFO0 == (can_filter_parameter_init->filter_fifo_number)) {
|
if(CAN_FIFO0 == (can_filter_parameter_init->filter_fifo_number)) {
|
||||||
/* FIFO0 */
|
/* FIFO0 */
|
||||||
CAN_FAFIFO(CAN0) &= ~(uint32_t)val;
|
CAN_FAFIFO(CAN0) &= ~(uint32_t)val;
|
||||||
}
|
} else {
|
||||||
|
|
||||||
if(CAN_FIFO1 == can_filter_parameter_init->filter_fifo_number){
|
|
||||||
/* FIFO1 */
|
/* FIFO1 */
|
||||||
CAN_FAFIFO(CAN0) |= (uint32_t)val;
|
CAN_FAFIFO(CAN0) |= (uint32_t)val;
|
||||||
}
|
}
|
||||||
|
|
@ -313,8 +318,9 @@ void can_filter_init(can_filter_parameter_struct* can_filter_parameter_init)
|
||||||
}
|
}
|
||||||
|
|
||||||
/*!
|
/*!
|
||||||
\brief set CAN1 fliter start bank number
|
\brief set CAN1 filter start bank number
|
||||||
\param[in] can1_start_bank_number
|
\param[in] start_bank: CAN1 start bank number
|
||||||
|
only one parameter can be selected which is shown as below:
|
||||||
\arg (1..27)
|
\arg (1..27)
|
||||||
\param[out] none
|
\param[out] none
|
||||||
\retval none
|
\retval none
|
||||||
|
|
@ -326,7 +332,7 @@ void can1_filter_start_bank(uint8_t start_bank)
|
||||||
/* set CAN1 filter start number */
|
/* set CAN1 filter start number */
|
||||||
CAN_FCTL(CAN0) &= ~(uint32_t)CAN_FCTL_HBC1F;
|
CAN_FCTL(CAN0) &= ~(uint32_t)CAN_FCTL_HBC1F;
|
||||||
CAN_FCTL(CAN0) |= FCTL_HBC1F(start_bank);
|
CAN_FCTL(CAN0) |= FCTL_HBC1F(start_bank);
|
||||||
/* filter lock enaable */
|
/* filter lock enable */
|
||||||
CAN_FCTL(CAN0) &= ~CAN_FCTL_FLD;
|
CAN_FCTL(CAN0) &= ~CAN_FCTL_FLD;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
@ -339,7 +345,9 @@ void can1_filter_start_bank(uint8_t start_bank)
|
||||||
*/
|
*/
|
||||||
void can_debug_freeze_enable(uint32_t can_periph)
|
void can_debug_freeze_enable(uint32_t can_periph)
|
||||||
{
|
{
|
||||||
|
/* set DFZ bit */
|
||||||
CAN_CTL(can_periph) |= CAN_CTL_DFZ;
|
CAN_CTL(can_periph) |= CAN_CTL_DFZ;
|
||||||
|
|
||||||
if(CAN0 == can_periph) {
|
if(CAN0 == can_periph) {
|
||||||
dbg_periph_enable(DBG_CAN0_HOLD);
|
dbg_periph_enable(DBG_CAN0_HOLD);
|
||||||
}else{
|
}else{
|
||||||
|
|
@ -356,11 +364,13 @@ void can_debug_freeze_enable(uint32_t can_periph)
|
||||||
*/
|
*/
|
||||||
void can_debug_freeze_disable(uint32_t can_periph)
|
void can_debug_freeze_disable(uint32_t can_periph)
|
||||||
{
|
{
|
||||||
|
/* set DFZ bit */
|
||||||
CAN_CTL(can_periph) &= ~CAN_CTL_DFZ;
|
CAN_CTL(can_periph) &= ~CAN_CTL_DFZ;
|
||||||
|
|
||||||
if(CAN0 == can_periph){
|
if(CAN0 == can_periph){
|
||||||
dbg_periph_disable(DBG_CAN0_HOLD);
|
dbg_periph_disable(DBG_CAN0_HOLD);
|
||||||
}else{
|
}else{
|
||||||
dbg_periph_disable(DBG_CAN0_HOLD);
|
dbg_periph_disable(DBG_CAN1_HOLD);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
@ -375,7 +385,7 @@ void can_time_trigger_mode_enable(uint32_t can_periph)
|
||||||
{
|
{
|
||||||
uint8_t mailbox_number;
|
uint8_t mailbox_number;
|
||||||
|
|
||||||
/* enable the tcc mode */
|
/* enable the TTC mode */
|
||||||
CAN_CTL(can_periph) |= CAN_CTL_TTC;
|
CAN_CTL(can_periph) |= CAN_CTL_TTC;
|
||||||
/* enable time stamp */
|
/* enable time stamp */
|
||||||
for(mailbox_number = 0U; mailbox_number < 3U; mailbox_number++) {
|
for(mailbox_number = 0U; mailbox_number < 3U; mailbox_number++) {
|
||||||
|
|
@ -394,7 +404,7 @@ void can_time_trigger_mode_disable(uint32_t can_periph)
|
||||||
{
|
{
|
||||||
uint8_t mailbox_number;
|
uint8_t mailbox_number;
|
||||||
|
|
||||||
/* disable the TCC mode */
|
/* disable the TTC mode */
|
||||||
CAN_CTL(can_periph) &= ~CAN_CTL_TTC;
|
CAN_CTL(can_periph) &= ~CAN_CTL_TTC;
|
||||||
/* reset TSEN bits */
|
/* reset TSEN bits */
|
||||||
for(mailbox_number = 0U; mailbox_number < 3U; mailbox_number++) {
|
for(mailbox_number = 0U; mailbox_number < 3U; mailbox_number++) {
|
||||||
|
|
@ -447,8 +457,7 @@ uint8_t can_message_transmit(uint32_t can_periph, can_trasnmit_message_struct* t
|
||||||
transmit_message->tx_ft);
|
transmit_message->tx_ft);
|
||||||
}
|
}
|
||||||
/* set the data length */
|
/* set the data length */
|
||||||
transmit_message->tx_dlen &= (uint8_t)(CAN_TMP_DLENC);
|
CAN_TMP(can_periph, mailbox_number) &= ~CAN_TMP_DLENC;
|
||||||
CAN_TMP(can_periph, mailbox_number) &= ((uint32_t)~CAN_TMP_DLENC);
|
|
||||||
CAN_TMP(can_periph, mailbox_number) |= transmit_message->tx_dlen;
|
CAN_TMP(can_periph, mailbox_number) |= transmit_message->tx_dlen;
|
||||||
/* set the data */
|
/* set the data */
|
||||||
CAN_TMDATA0(can_periph, mailbox_number) = TMDATA0_DB3(transmit_message->tx_data[3]) | \
|
CAN_TMDATA0(can_periph, mailbox_number) = TMDATA0_DB3(transmit_message->tx_data[3]) | \
|
||||||
|
|
@ -504,17 +513,7 @@ can_transmit_state_enum can_transmit_states(uint32_t can_periph, uint8_t mailbox
|
||||||
case(CAN_STATE_PENDING):
|
case(CAN_STATE_PENDING):
|
||||||
state = CAN_TRANSMIT_PENDING;
|
state = CAN_TRANSMIT_PENDING;
|
||||||
break;
|
break;
|
||||||
/* transmit failed */
|
/* mailbox0 transmit succeeded */
|
||||||
case (CAN_TSTAT_MTF0 | CAN_TSTAT_TME0):
|
|
||||||
state = CAN_TRANSMIT_FAILED;
|
|
||||||
break;
|
|
||||||
case (CAN_TSTAT_MTF1 | CAN_TSTAT_TME1):
|
|
||||||
state = CAN_TRANSMIT_FAILED;
|
|
||||||
break;
|
|
||||||
case (CAN_TSTAT_MTF2 | CAN_TSTAT_TME2):
|
|
||||||
state = CAN_TRANSMIT_FAILED;
|
|
||||||
break;
|
|
||||||
/* transmit succeeded */
|
|
||||||
case(CAN_TSTAT_MTF0 | CAN_TSTAT_MTFNERR0 | CAN_TSTAT_TME0):
|
case(CAN_TSTAT_MTF0 | CAN_TSTAT_MTFNERR0 | CAN_TSTAT_TME0):
|
||||||
state = CAN_TRANSMIT_OK;
|
state = CAN_TRANSMIT_OK;
|
||||||
break;
|
break;
|
||||||
|
|
@ -595,7 +594,7 @@ void can_message_receive(uint32_t can_periph, uint8_t fifo_number, can_receive_m
|
||||||
receive_message->rx_ft = (uint8_t)(CAN_RFIFOMI_FT & CAN_RFIFOMI(can_periph, fifo_number));
|
receive_message->rx_ft = (uint8_t)(CAN_RFIFOMI_FT & CAN_RFIFOMI(can_periph, fifo_number));
|
||||||
/* filtering index */
|
/* filtering index */
|
||||||
receive_message->rx_fi = (uint8_t)(GET_RFIFOMP_FI(CAN_RFIFOMP(can_periph, fifo_number)));
|
receive_message->rx_fi = (uint8_t)(GET_RFIFOMP_FI(CAN_RFIFOMP(can_periph, fifo_number)));
|
||||||
/* get recevie data length */
|
/* get receive data length */
|
||||||
receive_message->rx_dlen = (uint8_t)(GET_RFIFOMP_DLENC(CAN_RFIFOMP(can_periph, fifo_number)));
|
receive_message->rx_dlen = (uint8_t)(GET_RFIFOMP_DLENC(CAN_RFIFOMP(can_periph, fifo_number)));
|
||||||
|
|
||||||
/* receive data */
|
/* receive data */
|
||||||
|
|
@ -617,7 +616,7 @@ void can_message_receive(uint32_t can_periph, uint8_t fifo_number, can_receive_m
|
||||||
}
|
}
|
||||||
|
|
||||||
/*!
|
/*!
|
||||||
\brief release FIFO0
|
\brief release FIFO
|
||||||
\param[in] can_periph
|
\param[in] can_periph
|
||||||
\arg CANx(x=0,1)
|
\arg CANx(x=0,1)
|
||||||
\param[in] fifo_number
|
\param[in] fifo_number
|
||||||
|
|
@ -811,62 +810,6 @@ uint8_t can_transmit_error_number_get(uint32_t can_periph)
|
||||||
return val;
|
return val;
|
||||||
}
|
}
|
||||||
|
|
||||||
/*!
|
|
||||||
\brief enable CAN interrupt
|
|
||||||
\param[in] can_periph
|
|
||||||
\arg CANx(x=0,1)
|
|
||||||
\param[in] interrupt
|
|
||||||
one or more parameters can be selected which are shown as below:
|
|
||||||
\arg CAN_INT_TME: transmit mailbox empty interrupt enable
|
|
||||||
\arg CAN_INT_RFNE0: receive FIFO0 not empty interrupt enable
|
|
||||||
\arg CAN_INT_RFF0: receive FIFO0 full interrupt enable
|
|
||||||
\arg CAN_INT_RFO0: receive FIFO0 overfull interrupt enable
|
|
||||||
\arg CAN_INT_RFNE1: receive FIFO1 not empty interrupt enable
|
|
||||||
\arg CAN_INT_RFF1: receive FIFO1 full interrupt enable
|
|
||||||
\arg CAN_INT_RFO1: receive FIFO1 overfull interrupt enable
|
|
||||||
\arg CAN_INT_WERR: warning error interrupt enable
|
|
||||||
\arg CAN_INT_PERR: passive error interrupt enable
|
|
||||||
\arg CAN_INT_BO: bus-off interrupt enable
|
|
||||||
\arg CAN_INT_ERRN: error number interrupt enable
|
|
||||||
\arg CAN_INT_ERR: error interrupt enable
|
|
||||||
\arg CAN_INT_WU: wakeup interrupt enable
|
|
||||||
\arg CAN_INT_SLPW: sleep working interrupt enable
|
|
||||||
\param[out] none
|
|
||||||
\retval none
|
|
||||||
*/
|
|
||||||
void can_interrupt_enable(uint32_t can_periph, uint32_t interrupt)
|
|
||||||
{
|
|
||||||
CAN_INTEN(can_periph) |= interrupt;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
\brief disable CAN interrupt
|
|
||||||
\param[in] can_periph
|
|
||||||
\arg CANx(x=0,1)
|
|
||||||
\param[in] interrupt
|
|
||||||
one or more parameters can be selected which are shown as below:
|
|
||||||
\arg CAN_INT_TME: transmit mailbox empty interrupt enable
|
|
||||||
\arg CAN_INT_RFNE0: receive FIFO0 not empty interrupt enable
|
|
||||||
\arg CAN_INT_RFF0: receive FIFO0 full interrupt enable
|
|
||||||
\arg CAN_INT_RFO0: receive FIFO0 overfull interrupt enable
|
|
||||||
\arg CAN_INT_RFNE1: receive FIFO1 not empty interrupt enable
|
|
||||||
\arg CAN_INT_RFF1: receive FIFO1 full interrupt enable
|
|
||||||
\arg CAN_INT_RFO1: receive FIFO1 overfull interrupt enable
|
|
||||||
\arg CAN_INT_WERR: warning error interrupt enable
|
|
||||||
\arg CAN_INT_PERR: passive error interrupt enable
|
|
||||||
\arg CAN_INT_BO: bus-off interrupt enable
|
|
||||||
\arg CAN_INT_ERRN: error number interrupt enable
|
|
||||||
\arg CAN_INT_ERR: error interrupt enable
|
|
||||||
\arg CAN_INT_WU: wakeup interrupt enable
|
|
||||||
\arg CAN_INT_SLPW: sleep working interrupt enable
|
|
||||||
\param[out] none
|
|
||||||
\retval none
|
|
||||||
*/
|
|
||||||
void can_interrupt_disable(uint32_t can_periph, uint32_t interrupt)
|
|
||||||
{
|
|
||||||
CAN_INTEN(can_periph) &= ~interrupt;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
/*!
|
||||||
\brief get CAN flag state
|
\brief get CAN flag state
|
||||||
\param[in] can_periph
|
\param[in] can_periph
|
||||||
|
|
@ -882,9 +825,9 @@ void can_interrupt_disable(uint32_t can_periph, uint32_t interrupt)
|
||||||
\arg CAN_FLAG_ERRIF: error flag
|
\arg CAN_FLAG_ERRIF: error flag
|
||||||
\arg CAN_FLAG_SLPWS: sleep working state
|
\arg CAN_FLAG_SLPWS: sleep working state
|
||||||
\arg CAN_FLAG_IWS: initial working state
|
\arg CAN_FLAG_IWS: initial working state
|
||||||
\arg CAN_FLAG_TMLS2: transmit mailbox 2 last sending in Tx FIFO
|
\arg CAN_FLAG_TMLS2: transmit mailbox 2 last sending in TX FIFO
|
||||||
\arg CAN_FLAG_TMLS1: transmit mailbox 1 last sending in Tx FIFO
|
\arg CAN_FLAG_TMLS1: transmit mailbox 1 last sending in TX FIFO
|
||||||
\arg CAN_FLAG_TMLS0: transmit mailbox 0 last sending in Tx FIFO
|
\arg CAN_FLAG_TMLS0: transmit mailbox 0 last sending in TX FIFO
|
||||||
\arg CAN_FLAG_TME2: transmit mailbox 2 empty
|
\arg CAN_FLAG_TME2: transmit mailbox 2 empty
|
||||||
\arg CAN_FLAG_TME1: transmit mailbox 1 empty
|
\arg CAN_FLAG_TME1: transmit mailbox 1 empty
|
||||||
\arg CAN_FLAG_TME0: transmit mailbox 0 empty
|
\arg CAN_FLAG_TME0: transmit mailbox 0 empty
|
||||||
|
|
@ -953,6 +896,62 @@ void can_flag_clear(uint32_t can_periph, can_flag_enum flag)
|
||||||
CAN_REG_VAL(can_periph, flag) = BIT(CAN_BIT_POS(flag));
|
CAN_REG_VAL(can_periph, flag) = BIT(CAN_BIT_POS(flag));
|
||||||
}
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief enable CAN interrupt
|
||||||
|
\param[in] can_periph
|
||||||
|
\arg CANx(x=0,1)
|
||||||
|
\param[in] interrupt
|
||||||
|
one or more parameters can be selected which are shown as below:
|
||||||
|
\arg CAN_INT_TME: transmit mailbox empty interrupt enable
|
||||||
|
\arg CAN_INT_RFNE0: receive FIFO0 not empty interrupt enable
|
||||||
|
\arg CAN_INT_RFF0: receive FIFO0 full interrupt enable
|
||||||
|
\arg CAN_INT_RFO0: receive FIFO0 overfull interrupt enable
|
||||||
|
\arg CAN_INT_RFNE1: receive FIFO1 not empty interrupt enable
|
||||||
|
\arg CAN_INT_RFF1: receive FIFO1 full interrupt enable
|
||||||
|
\arg CAN_INT_RFO1: receive FIFO1 overfull interrupt enable
|
||||||
|
\arg CAN_INT_WERR: warning error interrupt enable
|
||||||
|
\arg CAN_INT_PERR: passive error interrupt enable
|
||||||
|
\arg CAN_INT_BO: bus-off interrupt enable
|
||||||
|
\arg CAN_INT_ERRN: error number interrupt enable
|
||||||
|
\arg CAN_INT_ERR: error interrupt enable
|
||||||
|
\arg CAN_INT_WAKEUP: wakeup interrupt enable
|
||||||
|
\arg CAN_INT_SLPW: sleep working interrupt enable
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void can_interrupt_enable(uint32_t can_periph, uint32_t interrupt)
|
||||||
|
{
|
||||||
|
CAN_INTEN(can_periph) |= interrupt;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief disable CAN interrupt
|
||||||
|
\param[in] can_periph
|
||||||
|
\arg CANx(x=0,1)
|
||||||
|
\param[in] interrupt
|
||||||
|
one or more parameters can be selected which are shown as below:
|
||||||
|
\arg CAN_INT_TME: transmit mailbox empty interrupt enable
|
||||||
|
\arg CAN_INT_RFNE0: receive FIFO0 not empty interrupt enable
|
||||||
|
\arg CAN_INT_RFF0: receive FIFO0 full interrupt enable
|
||||||
|
\arg CAN_INT_RFO0: receive FIFO0 overfull interrupt enable
|
||||||
|
\arg CAN_INT_RFNE1: receive FIFO1 not empty interrupt enable
|
||||||
|
\arg CAN_INT_RFF1: receive FIFO1 full interrupt enable
|
||||||
|
\arg CAN_INT_RFO1: receive FIFO1 overfull interrupt enable
|
||||||
|
\arg CAN_INT_WERR: warning error interrupt enable
|
||||||
|
\arg CAN_INT_PERR: passive error interrupt enable
|
||||||
|
\arg CAN_INT_BO: bus-off interrupt enable
|
||||||
|
\arg CAN_INT_ERRN: error number interrupt enable
|
||||||
|
\arg CAN_INT_ERR: error interrupt enable
|
||||||
|
\arg CAN_INT_WAKEUP: wakeup interrupt enable
|
||||||
|
\arg CAN_INT_SLPW: sleep working interrupt enable
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void can_interrupt_disable(uint32_t can_periph, uint32_t interrupt)
|
||||||
|
{
|
||||||
|
CAN_INTEN(can_periph) &= ~interrupt;
|
||||||
|
}
|
||||||
|
|
||||||
/*!
|
/*!
|
||||||
\brief get CAN interrupt flag state
|
\brief get CAN interrupt flag state
|
||||||
\param[in] can_periph
|
\param[in] can_periph
|
||||||
|
|
@ -983,17 +982,17 @@ FlagStatus can_interrupt_flag_get(uint32_t can_periph, can_interrupt_flag_enum f
|
||||||
uint32_t ret1 = RESET;
|
uint32_t ret1 = RESET;
|
||||||
uint32_t ret2 = RESET;
|
uint32_t ret2 = RESET;
|
||||||
|
|
||||||
/* get the staus of interrupt flag */
|
/* get the status of interrupt flag */
|
||||||
if (flag == CAN_INT_FLAG_RFF0) {
|
if(flag == CAN_INT_FLAG_RFL0) {
|
||||||
ret1 = can_receive_message_length_get(can_periph, CAN_FIFO0);
|
ret1 = can_receive_message_length_get(can_periph, CAN_FIFO0);
|
||||||
} else if (flag == CAN_INT_FLAG_RFF1) {
|
} else if(flag == CAN_INT_FLAG_RFL1) {
|
||||||
ret1 = can_receive_message_length_get(can_periph, CAN_FIFO1);
|
ret1 = can_receive_message_length_get(can_periph, CAN_FIFO1);
|
||||||
} else if(flag == CAN_INT_FLAG_ERRN) {
|
} else if(flag == CAN_INT_FLAG_ERRN) {
|
||||||
ret1 = can_error_get(can_periph);
|
ret1 = can_error_get(can_periph);
|
||||||
} else {
|
} else {
|
||||||
ret1 = CAN_REG_VALS(can_periph, flag) & BIT(CAN_BIT_POS0(flag));
|
ret1 = CAN_REG_VALS(can_periph, flag) & BIT(CAN_BIT_POS0(flag));
|
||||||
}
|
}
|
||||||
/* get the staus of interrupt enale bit */
|
/* get the status of interrupt enable bit */
|
||||||
ret2 = CAN_INTEN(can_periph) & BIT(CAN_BIT_POS1(flag));
|
ret2 = CAN_INTEN(can_periph) & BIT(CAN_BIT_POS1(flag));
|
||||||
if(ret1 && ret2) {
|
if(ret1 && ret2) {
|
||||||
return SET;
|
return SET;
|
||||||
|
|
|
||||||
|
|
@ -5,10 +5,11 @@
|
||||||
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
||||||
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
||||||
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
||||||
|
\version 2022-03-09, V3.0.0, firmware for GD32F4xx
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/*
|
/*
|
||||||
Copyright (c) 2020, GigaDevice Semiconductor Inc.
|
Copyright (c) 2022, GigaDevice Semiconductor Inc.
|
||||||
|
|
||||||
Redistribution and use in source and binary forms, with or without modification,
|
Redistribution and use in source and binary forms, with or without modification,
|
||||||
are permitted provided that the following conditions are met:
|
are permitted provided that the following conditions are met:
|
||||||
|
|
@ -38,6 +39,7 @@ OF SUCH DAMAGE.
|
||||||
|
|
||||||
#define CRC_DATA_RESET_VALUE ((uint32_t)0xFFFFFFFFU)
|
#define CRC_DATA_RESET_VALUE ((uint32_t)0xFFFFFFFFU)
|
||||||
#define CRC_FDATA_RESET_VALUE ((uint32_t)0x00000000U)
|
#define CRC_FDATA_RESET_VALUE ((uint32_t)0x00000000U)
|
||||||
|
|
||||||
/*!
|
/*!
|
||||||
\brief deinit CRC calculation unit
|
\brief deinit CRC calculation unit
|
||||||
\param[in] none
|
\param[in] none
|
||||||
|
|
|
||||||
|
|
@ -5,10 +5,11 @@
|
||||||
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
||||||
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
||||||
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
||||||
|
\version 2022-03-09, V3.0.0, firmware for GD32F4xx
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/*
|
/*
|
||||||
Copyright (c) 2020, GigaDevice Semiconductor Inc.
|
Copyright (c) 2022, GigaDevice Semiconductor Inc.
|
||||||
|
|
||||||
Redistribution and use in source and binary forms, with or without modification,
|
Redistribution and use in source and binary forms, with or without modification,
|
||||||
are permitted provided that the following conditions are met:
|
are permitted provided that the following conditions are met:
|
||||||
|
|
@ -135,27 +136,12 @@ void ctc_refsource_polarity_config(uint32_t polarity)
|
||||||
CTC_CTL1 |= (uint32_t)polarity;
|
CTC_CTL1 |= (uint32_t)polarity;
|
||||||
}
|
}
|
||||||
|
|
||||||
/*!
|
|
||||||
\brief select USBFS or USBHS SOF signal
|
|
||||||
\param[in] usbsof:
|
|
||||||
\arg CTC_USBSOFSEL_USBHS: USBHS SOF signal is selected
|
|
||||||
\arg CTC_USBSOFSEL_USBFS: USBFS SOF signal is selected
|
|
||||||
\param[out] none
|
|
||||||
\retval none
|
|
||||||
*/
|
|
||||||
void ctc_usbsof_signal_select(uint32_t usbsof)
|
|
||||||
{
|
|
||||||
CTC_CTL1 &= (uint32_t)(~CTC_CTL1_USBSOFSEL);
|
|
||||||
CTC_CTL1 |= (uint32_t)usbsof;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
/*!
|
||||||
\brief select reference signal source
|
\brief select reference signal source
|
||||||
\param[in] refs:
|
\param[in] refs:
|
||||||
only one parameter can be selected which is shown as below:
|
only one parameter can be selected which is shown as below:
|
||||||
\arg CTC_REFSOURCE_GPIO: GPIO is selected
|
\arg CTC_REFSOURCE_GPIO: GPIO is selected
|
||||||
\arg CTC_REFSOURCE_LXTAL: LXTAL is selected
|
\arg CTC_REFSOURCE_LXTAL: LXTAL is selected
|
||||||
\arg CTC_REFSOURCE_USBSOF: USBSOF is selected
|
|
||||||
\param[out] none
|
\param[out] none
|
||||||
\retval none
|
\retval none
|
||||||
*/
|
*/
|
||||||
|
|
|
||||||
|
|
@ -5,10 +5,11 @@
|
||||||
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
||||||
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
||||||
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
||||||
|
\version 2022-03-09, V3.0.0, firmware for GD32F4xx
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/*
|
/*
|
||||||
Copyright (c) 2020, GigaDevice Semiconductor Inc.
|
Copyright (c) 2022, GigaDevice Semiconductor Inc.
|
||||||
|
|
||||||
Redistribution and use in source and binary forms, with or without modification,
|
Redistribution and use in source and binary forms, with or without modification,
|
||||||
are permitted provided that the following conditions are met:
|
are permitted provided that the following conditions are met:
|
||||||
|
|
@ -564,36 +565,6 @@ void dac_concurrent_interrupt_disable(void)
|
||||||
DAC_CTL &= (~ctl);
|
DAC_CTL &= (~ctl);
|
||||||
}
|
}
|
||||||
|
|
||||||
/*!
|
|
||||||
\brief enable DAC interrupt(DAC DMA underrun interrupt)
|
|
||||||
\param[in] dac_periph: DACx(x = 0,1)
|
|
||||||
\param[out] none
|
|
||||||
\retval none
|
|
||||||
*/
|
|
||||||
void dac_interrupt_enable(uint32_t dac_periph)
|
|
||||||
{
|
|
||||||
if(DAC0 == dac_periph){
|
|
||||||
DAC_CTL |= DAC_CTL_DDUDRIE0;
|
|
||||||
}else{
|
|
||||||
DAC_CTL |= DAC_CTL_DDUDRIE1;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
\brief disable DAC interrupt(DAC DMA underrun interrupt)
|
|
||||||
\param[in] dac_periph: DACx(x = 0,1)
|
|
||||||
\param[out] none
|
|
||||||
\retval none
|
|
||||||
*/
|
|
||||||
void dac_interrupt_disable(uint32_t dac_periph)
|
|
||||||
{
|
|
||||||
if(DAC0 == dac_periph){
|
|
||||||
DAC_CTL &= ~DAC_CTL_DDUDRIE0;
|
|
||||||
}else{
|
|
||||||
DAC_CTL &= ~DAC_CTL_DDUDRIE1;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
/*!
|
||||||
\brief get the specified DAC flag (DAC DMA underrun flag)
|
\brief get the specified DAC flag (DAC DMA underrun flag)
|
||||||
\param[in] dac_periph: DACx(x = 0,1)
|
\param[in] dac_periph: DACx(x = 0,1)
|
||||||
|
|
@ -632,6 +603,36 @@ void dac_flag_clear(uint32_t dac_periph)
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief enable DAC interrupt(DAC DMA underrun interrupt)
|
||||||
|
\param[in] dac_periph: DACx(x = 0,1)
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void dac_interrupt_enable(uint32_t dac_periph)
|
||||||
|
{
|
||||||
|
if(DAC0 == dac_periph) {
|
||||||
|
DAC_CTL |= DAC_CTL_DDUDRIE0;
|
||||||
|
} else {
|
||||||
|
DAC_CTL |= DAC_CTL_DDUDRIE1;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief disable DAC interrupt(DAC DMA underrun interrupt)
|
||||||
|
\param[in] dac_periph: DACx(x = 0,1)
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void dac_interrupt_disable(uint32_t dac_periph)
|
||||||
|
{
|
||||||
|
if(DAC0 == dac_periph) {
|
||||||
|
DAC_CTL &= ~DAC_CTL_DDUDRIE0;
|
||||||
|
} else {
|
||||||
|
DAC_CTL &= ~DAC_CTL_DDUDRIE1;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
/*!
|
/*!
|
||||||
\brief get the specified DAC interrupt flag (DAC DMA underrun interrupt flag)
|
\brief get the specified DAC interrupt flag (DAC DMA underrun interrupt flag)
|
||||||
\param[in] dac_periph: DACx(x = 0,1)
|
\param[in] dac_periph: DACx(x = 0,1)
|
||||||
|
|
|
||||||
|
|
@ -5,10 +5,11 @@
|
||||||
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
||||||
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
||||||
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
||||||
|
\version 2022-03-09, V3.0.0, firmware for GD32F4xx
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/*
|
/*
|
||||||
Copyright (c) 2020, GigaDevice Semiconductor Inc.
|
Copyright (c) 2022, GigaDevice Semiconductor Inc.
|
||||||
|
|
||||||
Redistribution and use in source and binary forms, with or without modification,
|
Redistribution and use in source and binary forms, with or without modification,
|
||||||
are permitted provided that the following conditions are met:
|
are permitted provided that the following conditions are met:
|
||||||
|
|
@ -117,7 +118,6 @@ void dbg_low_power_disable(uint32_t dbg_low_power)
|
||||||
\arg DBG_TIMER8_HOLD: hold TIMER8 counter when core is halted
|
\arg DBG_TIMER8_HOLD: hold TIMER8 counter when core is halted
|
||||||
\arg DBG_TIMER9_HOLD: hold TIMER9 counter when core is halted
|
\arg DBG_TIMER9_HOLD: hold TIMER9 counter when core is halted
|
||||||
\arg DBG_TIMER10_HOLD: hold TIMER10 counter when core is halted
|
\arg DBG_TIMER10_HOLD: hold TIMER10 counter when core is halted
|
||||||
\arg \param[out] none
|
|
||||||
\retval none
|
\retval none
|
||||||
*/
|
*/
|
||||||
void dbg_periph_enable(dbg_periph_enum dbg_periph)
|
void dbg_periph_enable(dbg_periph_enum dbg_periph)
|
||||||
|
|
@ -181,18 +181,3 @@ void dbg_trace_pin_disable(void)
|
||||||
DBG_CTL0 &= ~DBG_CTL0_TRACE_IOEN;
|
DBG_CTL0 &= ~DBG_CTL0_TRACE_IOEN;
|
||||||
}
|
}
|
||||||
|
|
||||||
/*!
|
|
||||||
\brief trace pin mode selection
|
|
||||||
\param[in] trace_mode:
|
|
||||||
\arg TRACE_MODE_ASYNC: trace pin used for async mode
|
|
||||||
\arg TRACE_MODE_SYNC_DATASIZE_1: trace pin used for sync mode and data size is 1
|
|
||||||
\arg TRACE_MODE_SYNC_DATASIZE_2: trace pin used for sync mode and data size is 2
|
|
||||||
\arg TRACE_MODE_SYNC_DATASIZE_4: trace pin used for sync mode and data size is 4
|
|
||||||
\param[out] none
|
|
||||||
\retval none
|
|
||||||
*/
|
|
||||||
void dbg_trace_pin_mode_set(uint32_t trace_mode)
|
|
||||||
{
|
|
||||||
DBG_CTL0 &= ~DBG_CTL0_TRACE_MODE;
|
|
||||||
DBG_CTL0 |= trace_mode;
|
|
||||||
}
|
|
||||||
|
|
|
||||||
|
|
@ -5,10 +5,11 @@
|
||||||
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
||||||
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
||||||
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
||||||
|
\version 2022-03-09, V3.0.0, firmware for GD32F4xx
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/*
|
/*
|
||||||
Copyright (c) 2020, GigaDevice Semiconductor Inc.
|
Copyright (c) 2022, GigaDevice Semiconductor Inc.
|
||||||
|
|
||||||
Redistribution and use in source and binary forms, with or without modification,
|
Redistribution and use in source and binary forms, with or without modification,
|
||||||
are permitted provided that the following conditions are met:
|
are permitted provided that the following conditions are met:
|
||||||
|
|
|
||||||
|
|
@ -1,14 +1,14 @@
|
||||||
/*!
|
/*!
|
||||||
\file gd32f4xx_dma.c
|
\file gd32f4xx_dma.c
|
||||||
\brief DMA driver
|
\brief DMA driver
|
||||||
|
|
||||||
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
||||||
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
||||||
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
||||||
|
\version 2022-03-09, V3.0.0, firmware for GD32F4xx
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/*
|
/*
|
||||||
Copyright (c) 2020, GigaDevice Semiconductor Inc.
|
Copyright (c) 2022, GigaDevice Semiconductor Inc.
|
||||||
|
|
||||||
Redistribution and use in source and binary forms, with or without modification,
|
Redistribution and use in source and binary forms, with or without modification,
|
||||||
are permitted provided that the following conditions are met:
|
are permitted provided that the following conditions are met:
|
||||||
|
|
@ -34,7 +34,6 @@ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSI
|
||||||
OF SUCH DAMAGE.
|
OF SUCH DAMAGE.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
|
|
||||||
#include "gd32f4xx_dma.h"
|
#include "gd32f4xx_dma.h"
|
||||||
|
|
||||||
/* DMA register bit offset */
|
/* DMA register bit offset */
|
||||||
|
|
@ -218,7 +217,8 @@ void dma_multi_data_mode_init(uint32_t dma_periph, dma_channel_enum channelx, dm
|
||||||
/* configure peripheral and memory transfer width,channel priotity,transfer mode,peripheral and memory burst transfer width */
|
/* configure peripheral and memory transfer width,channel priotity,transfer mode,peripheral and memory burst transfer width */
|
||||||
ctl = DMA_CHCTL(dma_periph, channelx);
|
ctl = DMA_CHCTL(dma_periph, channelx);
|
||||||
ctl &= ~(DMA_CHXCTL_PWIDTH | DMA_CHXCTL_MWIDTH | DMA_CHXCTL_PRIO | DMA_CHXCTL_TM | DMA_CHXCTL_PBURST | DMA_CHXCTL_MBURST);
|
ctl &= ~(DMA_CHXCTL_PWIDTH | DMA_CHXCTL_MWIDTH | DMA_CHXCTL_PRIO | DMA_CHXCTL_TM | DMA_CHXCTL_PBURST | DMA_CHXCTL_MBURST);
|
||||||
ctl |= (init_struct->periph_width | (init_struct->memory_width ) | init_struct->priority | init_struct->direction | init_struct->memory_burst_width | init_struct->periph_burst_width);
|
ctl |= (init_struct->periph_width | (init_struct->memory_width) | init_struct->priority | init_struct->direction | init_struct->memory_burst_width |
|
||||||
|
init_struct->periph_burst_width);
|
||||||
DMA_CHCTL(dma_periph, channelx) = ctl;
|
DMA_CHCTL(dma_periph, channelx) = ctl;
|
||||||
|
|
||||||
/* configure peripheral increasing mode */
|
/* configure peripheral increasing mode */
|
||||||
|
|
@ -747,6 +747,56 @@ void dma_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t fla
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief enable DMA interrupt
|
||||||
|
\param[in] dma_periph: DMAx(x=0,1)
|
||||||
|
\arg DMAx(x=0,1)
|
||||||
|
\param[in] channelx: specify which DMA channel
|
||||||
|
\arg DMA_CHx(x=0..7)
|
||||||
|
\param[in] source: specify which interrupt to enbale
|
||||||
|
only one parameters can be selected which are shown as below:
|
||||||
|
\arg DMA_CHXCTL_SDEIE: single data mode exception interrupt enable
|
||||||
|
\arg DMA_CHXCTL_TAEIE: tranfer access error interrupt enable
|
||||||
|
\arg DMA_CHXCTL_HTFIE: half transfer finish interrupt enable
|
||||||
|
\arg DMA_CHXCTL_FTFIE: full transfer finish interrupt enable
|
||||||
|
\arg DMA_CHXFCTL_FEEIE: FIFO exception interrupt enable
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void dma_interrupt_enable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source)
|
||||||
|
{
|
||||||
|
if(DMA_CHXFCTL_FEEIE != source) {
|
||||||
|
DMA_CHCTL(dma_periph, channelx) |= source;
|
||||||
|
} else {
|
||||||
|
DMA_CHFCTL(dma_periph, channelx) |= source;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief disable DMA interrupt
|
||||||
|
\param[in] dma_periph: DMAx(x=0,1)
|
||||||
|
\arg DMAx(x=0,1)
|
||||||
|
\param[in] channelx: specify which DMA channel
|
||||||
|
\arg DMA_CHx(x=0..7)
|
||||||
|
\param[in] source: specify which interrupt to disbale
|
||||||
|
only one parameters can be selected which are shown as below:
|
||||||
|
\arg DMA_CHXCTL_SDEIE: single data mode exception interrupt enable
|
||||||
|
\arg DMA_CHXCTL_TAEIE: tranfer access error interrupt enable
|
||||||
|
\arg DMA_CHXCTL_HTFIE: half transfer finish interrupt enable
|
||||||
|
\arg DMA_CHXCTL_FTFIE: full transfer finish interrupt enable
|
||||||
|
\arg DMA_CHXFCTL_FEEIE: FIFO exception interrupt enable
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void dma_interrupt_disable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source)
|
||||||
|
{
|
||||||
|
if(DMA_CHXFCTL_FEEIE != source) {
|
||||||
|
DMA_CHCTL(dma_periph, channelx) &= ~source;
|
||||||
|
} else {
|
||||||
|
DMA_CHFCTL(dma_periph, channelx) &= ~source;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
/*!
|
/*!
|
||||||
\brief get DMA interrupt flag is set or not
|
\brief get DMA interrupt flag is set or not
|
||||||
\param[in] dma_periph: DMAx(x=0,1)
|
\param[in] dma_periph: DMAx(x=0,1)
|
||||||
|
|
@ -852,54 +902,3 @@ void dma_interrupt_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, ui
|
||||||
DMA_INTC1(dma_periph) |= DMA_FLAG_ADD(interrupt, channelx);
|
DMA_INTC1(dma_periph) |= DMA_FLAG_ADD(interrupt, channelx);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
/*!
|
|
||||||
\brief enable DMA interrupt
|
|
||||||
\param[in] dma_periph: DMAx(x=0,1)
|
|
||||||
\arg DMAx(x=0,1)
|
|
||||||
\param[in] channelx: specify which DMA channel
|
|
||||||
\arg DMA_CHx(x=0..7)
|
|
||||||
\param[in] source: specify which interrupt to enbale
|
|
||||||
one or more parameters can be selected which are shown as below:
|
|
||||||
\arg DMA_CHXCTL_SDEIE: single data mode exception interrupt enable
|
|
||||||
\arg DMA_CHXCTL_TAEIE: tranfer access error interrupt enable
|
|
||||||
\arg DMA_CHXCTL_HTFIE: half transfer finish interrupt enable
|
|
||||||
\arg DMA_CHXCTL_FTFIE: full transfer finish interrupt enable
|
|
||||||
\arg DMA_CHXFCTL_FEEIE: FIFO exception interrupt enable
|
|
||||||
\param[out] none
|
|
||||||
\retval none
|
|
||||||
*/
|
|
||||||
void dma_interrupt_enable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source)
|
|
||||||
{
|
|
||||||
if(DMA_CHXFCTL_FEEIE != source){
|
|
||||||
DMA_CHCTL(dma_periph,channelx) |= source;
|
|
||||||
}else{
|
|
||||||
DMA_CHFCTL(dma_periph,channelx) |= source;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
\brief disable DMA interrupt
|
|
||||||
\param[in] dma_periph: DMAx(x=0,1)
|
|
||||||
\arg DMAx(x=0,1)
|
|
||||||
\param[in] channelx: specify which DMA channel
|
|
||||||
\arg DMA_CHx(x=0..7)
|
|
||||||
\param[in] source: specify which interrupt to disbale
|
|
||||||
one or more parameters can be selected which are shown as below:
|
|
||||||
\arg DMA_CHXCTL_SDEIE: single data mode exception interrupt enable
|
|
||||||
\arg DMA_CHXCTL_TAEIE: tranfer access error interrupt enable
|
|
||||||
\arg DMA_CHXCTL_HTFIE: half transfer finish interrupt enable
|
|
||||||
\arg DMA_CHXCTL_FTFIE: full transfer finish interrupt enable
|
|
||||||
\arg DMA_CHXFCTL_FEEIE: FIFO exception interrupt enable
|
|
||||||
\param[out] none
|
|
||||||
\retval none
|
|
||||||
*/
|
|
||||||
void dma_interrupt_disable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source)
|
|
||||||
{
|
|
||||||
if(DMA_CHXFCTL_FEEIE != source){
|
|
||||||
DMA_CHCTL(dma_periph,channelx) &= ~source;
|
|
||||||
}else{
|
|
||||||
DMA_CHFCTL(dma_periph,channelx) &= ~source;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -5,11 +5,11 @@
|
||||||
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
||||||
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
||||||
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
||||||
|
\version 2022-03-09, V3.0.0, firmware for GD32F4xx
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/*
|
/*
|
||||||
Copyright (c) 2020, GigaDevice Semiconductor Inc.
|
Copyright (c) 2022, GigaDevice Semiconductor Inc.
|
||||||
|
|
||||||
Redistribution and use in source and binary forms, with or without modification,
|
Redistribution and use in source and binary forms, with or without modification,
|
||||||
are permitted provided that the following conditions are met:
|
are permitted provided that the following conditions are met:
|
||||||
|
|
||||||
|
|
@ -85,7 +85,8 @@ static const uint16_t enet_reg_tab[] = {
|
||||||
0x0700, 0x0704, 0x0708, 0x070C, 0x0710, 0x0714, 0x0718, 0x071C, 0x0720, 0x0728, 0x072C,
|
0x0700, 0x0704, 0x0708, 0x070C, 0x0710, 0x0714, 0x0718, 0x071C, 0x0720, 0x0728, 0x072C,
|
||||||
|
|
||||||
0x1000, 0x1004, 0x1008, 0x100C, 0x1010, 0x1014, 0x1018, 0x101C, 0x1020, 0x1024, 0x1048,
|
0x1000, 0x1004, 0x1008, 0x100C, 0x1010, 0x1014, 0x1018, 0x101C, 0x1020, 0x1024, 0x1048,
|
||||||
0x104C, 0x1050, 0x1054};
|
0x104C, 0x1050, 0x1054
|
||||||
|
};
|
||||||
|
|
||||||
/* initialize ENET peripheral with generally concerned parameters, call it by enet_init() */
|
/* initialize ENET peripheral with generally concerned parameters, call it by enet_init() */
|
||||||
static void enet_default_init(void);
|
static void enet_default_init(void);
|
||||||
|
|
@ -183,7 +184,15 @@ void enet_deinit(void)
|
||||||
ENET_PAUSETIME_MINUS144/ENET_PAUSETIME_MINUS256 ;
|
ENET_PAUSETIME_MINUS144/ENET_PAUSETIME_MINUS256 ;
|
||||||
- ENET_MAC0_AND_UNIQUE_ADDRESS_PAUSEDETECT/ ENET_UNIQUE_PAUSEDETECT ;
|
- ENET_MAC0_AND_UNIQUE_ADDRESS_PAUSEDETECT/ ENET_UNIQUE_PAUSEDETECT ;
|
||||||
- ENET_RX_FLOWCONTROL_ENABLE/ ENET_RX_FLOWCONTROL_DISABLE ;
|
- ENET_RX_FLOWCONTROL_ENABLE/ ENET_RX_FLOWCONTROL_DISABLE ;
|
||||||
- ENET_TX_FLOWCONTROL_ENABLE/ ENET_TX_FLOWCONTROL_DISABLE .
|
- ENET_TX_FLOWCONTROL_ENABLE/ ENET_TX_FLOWCONTROL_DISABLE ;
|
||||||
|
- ENET_ACTIVE_THRESHOLD_256BYTES/ ENET_ACTIVE_THRESHOLD_512BYTES ;
|
||||||
|
- ENET_ACTIVE_THRESHOLD_768BYTES/ ENET_ACTIVE_THRESHOLD_1024BYTES ;
|
||||||
|
- ENET_ACTIVE_THRESHOLD_1280BYTES/ ENET_ACTIVE_THRESHOLD_1536BYTES ;
|
||||||
|
- ENET_ACTIVE_THRESHOLD_1792BYTES ;
|
||||||
|
- ENET_DEACTIVE_THRESHOLD_256BYTES/ ENET_DEACTIVE_THRESHOLD_512BYTES ;
|
||||||
|
- ENET_DEACTIVE_THRESHOLD_768BYTES/ ENET_DEACTIVE_THRESHOLD_1024BYTES ;
|
||||||
|
- ENET_DEACTIVE_THRESHOLD_1280BYTES/ ENET_DEACTIVE_THRESHOLD_1536BYTES ;
|
||||||
|
- ENET_DEACTIVE_THRESHOLD_1792BYTES .
|
||||||
HASHH_OPTION related parameters:
|
HASHH_OPTION related parameters:
|
||||||
- 0x0~0xFFFF FFFFU
|
- 0x0~0xFFFF FFFFU
|
||||||
HASHL_OPTION related parameters:
|
HASHL_OPTION related parameters:
|
||||||
|
|
@ -1544,7 +1553,7 @@ ErrStatus enet_phy_config(void)
|
||||||
reg |= ENET_MDC_HCLK_DIV42;
|
reg |= ENET_MDC_HCLK_DIV42;
|
||||||
} else if(ENET_RANGE(ahbclk, 100000000U, 150000000U)) {
|
} else if(ENET_RANGE(ahbclk, 100000000U, 150000000U)) {
|
||||||
reg |= ENET_MDC_HCLK_DIV62;
|
reg |= ENET_MDC_HCLK_DIV62;
|
||||||
}else if((ENET_RANGE(ahbclk, 150000000U, 200000000U))||(200000000U == ahbclk)){
|
} else if((ENET_RANGE(ahbclk, 150000000U, 240000000U)) || (240000000U == ahbclk)) {
|
||||||
reg |= ENET_MDC_HCLK_DIV102;
|
reg |= ENET_MDC_HCLK_DIV102;
|
||||||
} else {
|
} else {
|
||||||
return enet_state;
|
return enet_state;
|
||||||
|
|
@ -1604,8 +1613,7 @@ ErrStatus enet_phy_write_read(enet_phydirection_enum direction, uint16_t phy_add
|
||||||
do {
|
do {
|
||||||
phy_flag = (ENET_MAC_PHY_CTL & ENET_MAC_PHY_CTL_PB);
|
phy_flag = (ENET_MAC_PHY_CTL & ENET_MAC_PHY_CTL_PB);
|
||||||
timeout++;
|
timeout++;
|
||||||
}
|
} while((RESET != phy_flag) && (ENET_DELAY_TO != timeout));
|
||||||
while((RESET != phy_flag) && (ENET_DELAY_TO != timeout));
|
|
||||||
|
|
||||||
/* write/read operation complete */
|
/* write/read operation complete */
|
||||||
if(RESET == (ENET_MAC_PHY_CTL & ENET_MAC_PHY_CTL_PB)) {
|
if(RESET == (ENET_MAC_PHY_CTL & ENET_MAC_PHY_CTL_PB)) {
|
||||||
|
|
@ -1692,10 +1700,10 @@ void enet_forward_feature_enable(uint32_t feature)
|
||||||
\brief disable ENET forward feature
|
\brief disable ENET forward feature
|
||||||
\param[in] feature: the feature of ENET forward mode
|
\param[in] feature: the feature of ENET forward mode
|
||||||
one or more parameters can be selected which are shown as below
|
one or more parameters can be selected which are shown as below
|
||||||
\arg ENET_AUTO_PADCRC_DROP: the automatic zero-quanta generation function
|
\arg ENET_AUTO_PADCRC_DROP: the function of the MAC strips the Pad/FCS field on received frames
|
||||||
\arg ENET_TYPEFRAME_CRC_DROP: the flow control operation in the MAC
|
\arg ENET_TYPEFRAME_CRC_DROP: the function that FCS field(last 4 bytes) of frame will be dropped before forwarding
|
||||||
\arg ENET_FORWARD_ERRFRAMES: decoding function for the received pause frame and process it
|
\arg ENET_FORWARD_ERRFRAMES: the function that all frame received with error except runt error are forwarded to memory
|
||||||
\arg ENET_FORWARD_UNDERSZ_GOODFRAMES: back pressure operation in the MAC(only use in half-dulex mode)
|
\arg ENET_FORWARD_UNDERSZ_GOODFRAMES: the function that forwarding undersized good frames
|
||||||
\param[out] none
|
\param[out] none
|
||||||
\retval none
|
\retval none
|
||||||
*/
|
*/
|
||||||
|
|
@ -3462,8 +3470,6 @@ static void enet_default_init(void)
|
||||||
| ENET_RX_FLOWCONTROL_DISABLE | ENET_TX_FLOWCONTROL_DISABLE;
|
| ENET_RX_FLOWCONTROL_DISABLE | ENET_TX_FLOWCONTROL_DISABLE;
|
||||||
ENET_MAC_FCTL = reg_value;
|
ENET_MAC_FCTL = reg_value;
|
||||||
|
|
||||||
ENET_MAC_FCTH = ENET_DEACTIVE_THRESHOLD_512BYTES |ENET_ACTIVE_THRESHOLD_1536BYTES;
|
|
||||||
|
|
||||||
/* configure ENET_MAC_VLT register */
|
/* configure ENET_MAC_VLT register */
|
||||||
ENET_MAC_VLT = ENET_VLANTAGCOMPARISON_16BIT | MAC_VLT_VLTI(0);
|
ENET_MAC_VLT = ENET_VLANTAGCOMPARISON_16BIT | MAC_VLT_VLTI(0);
|
||||||
|
|
||||||
|
|
@ -3474,7 +3480,6 @@ static void enet_default_init(void)
|
||||||
reg_value |= ENET_TCPIP_CKSUMERROR_DROP | ENET_RX_MODE_STOREFORWARD \
|
reg_value |= ENET_TCPIP_CKSUMERROR_DROP | ENET_RX_MODE_STOREFORWARD \
|
||||||
| ENET_FLUSH_RXFRAME_ENABLE | ENET_TX_MODE_STOREFORWARD \
|
| ENET_FLUSH_RXFRAME_ENABLE | ENET_TX_MODE_STOREFORWARD \
|
||||||
| ENET_TX_THRESHOLD_64BYTES | ENET_RX_THRESHOLD_64BYTES \
|
| ENET_TX_THRESHOLD_64BYTES | ENET_RX_THRESHOLD_64BYTES \
|
||||||
|ENET_FORWARD_ERRFRAMES_DISABLE |ENET_FORWARD_UNDERSZ_GOODFRAMES_DISABLE \
|
|
||||||
| ENET_SECONDFRAME_OPT_DISABLE;
|
| ENET_SECONDFRAME_OPT_DISABLE;
|
||||||
ENET_DMA_CTL = reg_value;
|
ENET_DMA_CTL = reg_value;
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -5,10 +5,12 @@
|
||||||
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
||||||
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
||||||
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
||||||
|
\version 2022-03-09, V3.0.0, firmware for GD32F4xx
|
||||||
|
\version 2022-06-08, V3.0.1, firmware for GD32F4xx
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/*
|
/*
|
||||||
Copyright (c) 2020, GigaDevice Semiconductor Inc.
|
Copyright (c) 2022, GigaDevice Semiconductor Inc.
|
||||||
|
|
||||||
Redistribution and use in source and binary forms, with or without modification,
|
Redistribution and use in source and binary forms, with or without modification,
|
||||||
are permitted provided that the following conditions are met:
|
are permitted provided that the following conditions are met:
|
||||||
|
|
@ -112,9 +114,6 @@ OF SUCH DAMAGE.
|
||||||
|
|
||||||
#define SDARI_ARINTV_OFFSET ((uint32_t)1U)
|
#define SDARI_ARINTV_OFFSET ((uint32_t)1U)
|
||||||
|
|
||||||
#define SDRSCTL_SSCR_OFFSET ((uint32_t)1U)
|
|
||||||
#define SDRSCTL_SDSC_OFFSET ((uint32_t)4U)
|
|
||||||
|
|
||||||
#define SDSTAT_STA0_OFFSET ((uint32_t)1U)
|
#define SDSTAT_STA0_OFFSET ((uint32_t)1U)
|
||||||
#define SDSTAT_STA1_OFFSET ((uint32_t)3U)
|
#define SDSTAT_STA1_OFFSET ((uint32_t)3U)
|
||||||
|
|
||||||
|
|
@ -171,7 +170,7 @@ void exmc_norsram_struct_para_init(exmc_norsram_parameter_struct* exmc_norsram_i
|
||||||
exmc_norsram_init_struct->read_write_timing->syn_data_latency = EXMC_DATALAT_17_CLK;
|
exmc_norsram_init_struct->read_write_timing->syn_data_latency = EXMC_DATALAT_17_CLK;
|
||||||
exmc_norsram_init_struct->read_write_timing->asyn_access_mode = EXMC_ACCESS_MODE_A;
|
exmc_norsram_init_struct->read_write_timing->asyn_access_mode = EXMC_ACCESS_MODE_A;
|
||||||
|
|
||||||
/* write timing configure, when extended mode is used */
|
/* configure write timing, when extended mode is used */
|
||||||
exmc_norsram_init_struct->write_timing->asyn_address_setuptime = 0xFU;
|
exmc_norsram_init_struct->write_timing->asyn_address_setuptime = 0xFU;
|
||||||
exmc_norsram_init_struct->write_timing->asyn_address_holdtime = 0xFU;
|
exmc_norsram_init_struct->write_timing->asyn_address_holdtime = 0xFU;
|
||||||
exmc_norsram_init_struct->write_timing->asyn_data_setuptime = 0xFFU;
|
exmc_norsram_init_struct->write_timing->asyn_data_setuptime = 0xFFU;
|
||||||
|
|
@ -198,7 +197,7 @@ void exmc_norsram_struct_para_init(exmc_norsram_parameter_struct* exmc_norsram_i
|
||||||
read_write_timing: struct exmc_norsram_timing_parameter_struct set the time
|
read_write_timing: struct exmc_norsram_timing_parameter_struct set the time
|
||||||
asyn_access_mode: EXMC_ACCESS_MODE_A, EXMC_ACCESS_MODE_B, EXMC_ACCESS_MODE_C, EXMC_ACCESS_MODE_D
|
asyn_access_mode: EXMC_ACCESS_MODE_A, EXMC_ACCESS_MODE_B, EXMC_ACCESS_MODE_C, EXMC_ACCESS_MODE_D
|
||||||
syn_data_latency: EXMC_DATALAT_x_CLK, x=2..17
|
syn_data_latency: EXMC_DATALAT_x_CLK, x=2..17
|
||||||
syn_clk_division: EXMC_SYN_CLOCK_RATIO_x_CLK, x=2..16
|
syn_clk_division: EXMC_SYN_CLOCK_RATIO_DISABLE, EXMC_SYN_CLOCK_RATIO_x_CLK, x=2..16
|
||||||
bus_latency: 0x0U~0xFU
|
bus_latency: 0x0U~0xFU
|
||||||
asyn_data_setuptime: 0x01U~0xFFU
|
asyn_data_setuptime: 0x01U~0xFFU
|
||||||
asyn_address_holdtime: 0x1U~0xFU
|
asyn_address_holdtime: 0x1U~0xFU
|
||||||
|
|
@ -223,10 +222,11 @@ void exmc_norsram_init(exmc_norsram_parameter_struct* exmc_norsram_init_struct)
|
||||||
|
|
||||||
/* clear relative bits */
|
/* clear relative bits */
|
||||||
snctl &= ((uint32_t)~(EXMC_SNCTL_NREN | EXMC_SNCTL_NRTP | EXMC_SNCTL_NRW | EXMC_SNCTL_SBRSTEN |
|
snctl &= ((uint32_t)~(EXMC_SNCTL_NREN | EXMC_SNCTL_NRTP | EXMC_SNCTL_NRW | EXMC_SNCTL_SBRSTEN |
|
||||||
EXMC_SNCTL_NRWTPOL | EXMC_SNCTL_WRAPEN | EXMC_SNCTL_NRWTCFG | EXMC_SNCTL_WREN |
|
EXMC_SNCTL_NRWTPOL | EXMC_SNCTL_WRAPEN | EXMC_SNCTL_NRWTCFG | EXMC_SNCTL_WEN |
|
||||||
EXMC_SNCTL_NRWTEN | EXMC_SNCTL_EXMODEN | EXMC_SNCTL_ASYNCWAIT | EXMC_SNCTL_SYNCWR |
|
EXMC_SNCTL_NRWTEN | EXMC_SNCTL_EXMODEN | EXMC_SNCTL_ASYNCWTEN | EXMC_SNCTL_SYNCWR |
|
||||||
EXMC_SNCTL_NRMUX));
|
EXMC_SNCTL_NRMUX));
|
||||||
|
|
||||||
|
/* configure control bits */
|
||||||
snctl |= (uint32_t)(exmc_norsram_init_struct->address_data_mux << SNCTL_NRMUX_OFFSET) |
|
snctl |= (uint32_t)(exmc_norsram_init_struct->address_data_mux << SNCTL_NRMUX_OFFSET) |
|
||||||
exmc_norsram_init_struct->memory_type |
|
exmc_norsram_init_struct->memory_type |
|
||||||
exmc_norsram_init_struct->databus_width |
|
exmc_norsram_init_struct->databus_width |
|
||||||
|
|
@ -240,6 +240,7 @@ void exmc_norsram_init(exmc_norsram_parameter_struct* exmc_norsram_init_struct)
|
||||||
(exmc_norsram_init_struct->asyn_wait << SNCTL_ASYNCWAIT_OFFSET) |
|
(exmc_norsram_init_struct->asyn_wait << SNCTL_ASYNCWAIT_OFFSET) |
|
||||||
exmc_norsram_init_struct->write_mode;
|
exmc_norsram_init_struct->write_mode;
|
||||||
|
|
||||||
|
/* configure timing */
|
||||||
sntcfg = (uint32_t)exmc_norsram_init_struct->read_write_timing->asyn_address_setuptime |
|
sntcfg = (uint32_t)exmc_norsram_init_struct->read_write_timing->asyn_address_setuptime |
|
||||||
(exmc_norsram_init_struct->read_write_timing->asyn_address_holdtime << SNTCFG_AHLD_OFFSET) |
|
(exmc_norsram_init_struct->read_write_timing->asyn_address_holdtime << SNTCFG_AHLD_OFFSET) |
|
||||||
(exmc_norsram_init_struct->read_write_timing->asyn_data_setuptime << SNTCFG_DSET_OFFSET) |
|
(exmc_norsram_init_struct->read_write_timing->asyn_data_setuptime << SNTCFG_DSET_OFFSET) |
|
||||||
|
|
@ -248,12 +249,12 @@ void exmc_norsram_init(exmc_norsram_parameter_struct* exmc_norsram_init_struct)
|
||||||
exmc_norsram_init_struct->read_write_timing->syn_data_latency |
|
exmc_norsram_init_struct->read_write_timing->syn_data_latency |
|
||||||
exmc_norsram_init_struct->read_write_timing->asyn_access_mode;
|
exmc_norsram_init_struct->read_write_timing->asyn_access_mode;
|
||||||
|
|
||||||
/* nor flash access enable */
|
/* enable nor flash access */
|
||||||
if(EXMC_MEMORY_TYPE_NOR == exmc_norsram_init_struct->memory_type) {
|
if(EXMC_MEMORY_TYPE_NOR == exmc_norsram_init_struct->memory_type) {
|
||||||
snctl |= (uint32_t)EXMC_SNCTL_NREN;
|
snctl |= (uint32_t)EXMC_SNCTL_NREN;
|
||||||
}
|
}
|
||||||
|
|
||||||
/* extended mode configure */
|
/* configure extended mode */
|
||||||
if(ENABLE == exmc_norsram_init_struct->extended_mode) {
|
if(ENABLE == exmc_norsram_init_struct->extended_mode) {
|
||||||
snwtcfg = (uint32_t)exmc_norsram_init_struct->write_timing->asyn_address_setuptime |
|
snwtcfg = (uint32_t)exmc_norsram_init_struct->write_timing->asyn_address_setuptime |
|
||||||
(exmc_norsram_init_struct->write_timing->asyn_address_holdtime << SNTCFG_AHLD_OFFSET) |
|
(exmc_norsram_init_struct->write_timing->asyn_address_holdtime << SNTCFG_AHLD_OFFSET) |
|
||||||
|
|
@ -272,7 +273,7 @@ void exmc_norsram_init(exmc_norsram_parameter_struct* exmc_norsram_init_struct)
|
||||||
|
|
||||||
/*!
|
/*!
|
||||||
\brief enable EXMC NOR/PSRAM bank region
|
\brief enable EXMC NOR/PSRAM bank region
|
||||||
\param[in] exmc_norsram_region: specifie the region of NOR/PSRAM bank
|
\param[in] exmc_norsram_region: specify the region of NOR/PSRAM bank
|
||||||
only one parameter can be selected which is shown as below:
|
only one parameter can be selected which is shown as below:
|
||||||
\arg EXMC_BANK0_NORSRAM_REGIONx(x=0..3)
|
\arg EXMC_BANK0_NORSRAM_REGIONx(x=0..3)
|
||||||
\param[out] none
|
\param[out] none
|
||||||
|
|
@ -285,7 +286,7 @@ void exmc_norsram_enable(uint32_t exmc_norsram_region)
|
||||||
|
|
||||||
/*!
|
/*!
|
||||||
\brief disable EXMC NOR/PSRAM bank region
|
\brief disable EXMC NOR/PSRAM bank region
|
||||||
\param[in] exmc_norsram_region: specifie the region of NOR/PSRAM Bank
|
\param[in] exmc_norsram_region: specify the region of NOR/PSRAM Bank
|
||||||
only one parameter can be selected which is shown as below:
|
only one parameter can be selected which is shown as below:
|
||||||
\arg EXMC_BANK0_NORSRAM_REGIONx(x=0..3)
|
\arg EXMC_BANK0_NORSRAM_REGIONx(x=0..3)
|
||||||
\param[out] none
|
\param[out] none
|
||||||
|
|
@ -384,7 +385,7 @@ void exmc_nand_init(exmc_nand_parameter_struct* exmc_nand_init_struct)
|
||||||
((exmc_nand_init_struct->attribute_space_timing->holdtime << NPATCFG_ATTHLD_OFFSET) & EXMC_NPATCFG_ATTHLD) |
|
((exmc_nand_init_struct->attribute_space_timing->holdtime << NPATCFG_ATTHLD_OFFSET) & EXMC_NPATCFG_ATTHLD) |
|
||||||
((exmc_nand_init_struct->attribute_space_timing->databus_hiztime << NPATCFG_ATTHIZ_OFFSET) & EXMC_NPATCFG_ATTHIZ);
|
((exmc_nand_init_struct->attribute_space_timing->databus_hiztime << NPATCFG_ATTHIZ_OFFSET) & EXMC_NPATCFG_ATTHIZ);
|
||||||
|
|
||||||
/* EXMC_BANK1_NAND or EXMC_BANK2_NAND initialize */
|
/* initialize EXMC_BANK1_NAND or EXMC_BANK2_NAND */
|
||||||
EXMC_NPCTL(exmc_nand_init_struct->nand_bank) = npctl;
|
EXMC_NPCTL(exmc_nand_init_struct->nand_bank) = npctl;
|
||||||
EXMC_NPCTCFG(exmc_nand_init_struct->nand_bank) = npctcfg;
|
EXMC_NPCTCFG(exmc_nand_init_struct->nand_bank) = npctcfg;
|
||||||
EXMC_NPATCFG(exmc_nand_init_struct->nand_bank) = npatcfg;
|
EXMC_NPATCFG(exmc_nand_init_struct->nand_bank) = npatcfg;
|
||||||
|
|
@ -392,7 +393,7 @@ void exmc_nand_init(exmc_nand_parameter_struct* exmc_nand_init_struct)
|
||||||
|
|
||||||
/*!
|
/*!
|
||||||
\brief enable NAND bank
|
\brief enable NAND bank
|
||||||
\param[in] exmc_nand_bank: specifie the NAND bank
|
\param[in] exmc_nand_bank: specify the NAND bank
|
||||||
only one parameter can be selected which is shown as below:
|
only one parameter can be selected which is shown as below:
|
||||||
\arg EXMC_BANKx_NAND(x=1,2)
|
\arg EXMC_BANKx_NAND(x=1,2)
|
||||||
\param[out] none
|
\param[out] none
|
||||||
|
|
@ -405,7 +406,7 @@ void exmc_nand_enable(uint32_t exmc_nand_bank)
|
||||||
|
|
||||||
/*!
|
/*!
|
||||||
\brief disable NAND bank
|
\brief disable NAND bank
|
||||||
\param[in] exmc_nand_bank: specifie the NAND bank
|
\param[in] exmc_nand_bank: specify the NAND bank
|
||||||
only one parameter can be selected which is shown as below:
|
only one parameter can be selected which is shown as below:
|
||||||
\arg EXMC_BANKx_NAND(x=1,2)
|
\arg EXMC_BANKx_NAND(x=1,2)
|
||||||
\param[out] none
|
\param[out] none
|
||||||
|
|
@ -567,7 +568,7 @@ void exmc_sdram_struct_para_init(exmc_sdram_parameter_struct* exmc_sdram_init_st
|
||||||
exmc_sdram_init_struct->cas_latency = EXMC_CAS_LATENCY_1_SDCLK;
|
exmc_sdram_init_struct->cas_latency = EXMC_CAS_LATENCY_1_SDCLK;
|
||||||
exmc_sdram_init_struct->write_protection = ENABLE;
|
exmc_sdram_init_struct->write_protection = ENABLE;
|
||||||
exmc_sdram_init_struct->sdclock_config = EXMC_SDCLK_DISABLE;
|
exmc_sdram_init_struct->sdclock_config = EXMC_SDCLK_DISABLE;
|
||||||
exmc_sdram_init_struct->brust_read_switch = DISABLE;
|
exmc_sdram_init_struct->burst_read_switch = DISABLE;
|
||||||
exmc_sdram_init_struct->pipeline_read_delay = EXMC_PIPELINE_DELAY_0_HCLK;
|
exmc_sdram_init_struct->pipeline_read_delay = EXMC_PIPELINE_DELAY_0_HCLK;
|
||||||
|
|
||||||
exmc_sdram_init_struct->timing->load_mode_register_delay = 16U;
|
exmc_sdram_init_struct->timing->load_mode_register_delay = 16U;
|
||||||
|
|
@ -584,7 +585,7 @@ void exmc_sdram_struct_para_init(exmc_sdram_parameter_struct* exmc_sdram_init_st
|
||||||
\param[in] exmc_sdram_parameter_struct: configure the EXMC SDRAM parameter
|
\param[in] exmc_sdram_parameter_struct: configure the EXMC SDRAM parameter
|
||||||
sdram_device: EXMC_SDRAM_DEVICE0,EXMC_SDRAM_DEVICE1
|
sdram_device: EXMC_SDRAM_DEVICE0,EXMC_SDRAM_DEVICE1
|
||||||
pipeline_read_delay: EXMC_PIPELINE_DELAY_x_HCLK,x=0..2
|
pipeline_read_delay: EXMC_PIPELINE_DELAY_x_HCLK,x=0..2
|
||||||
brust_read_switch: ENABLE or DISABLE
|
burst_read_switch: ENABLE or DISABLE
|
||||||
sdclock_config: EXMC_SDCLK_DISABLE,EXMC_SDCLK_PERIODS_2_HCLK,EXMC_SDCLK_PERIODS_3_HCLK
|
sdclock_config: EXMC_SDCLK_DISABLE,EXMC_SDCLK_PERIODS_2_HCLK,EXMC_SDCLK_PERIODS_3_HCLK
|
||||||
write_protection: ENABLE or DISABLE
|
write_protection: ENABLE or DISABLE
|
||||||
cas_latency: EXMC_CAS_LATENCY_x_SDCLK,x=1..3
|
cas_latency: EXMC_CAS_LATENCY_x_SDCLK,x=1..3
|
||||||
|
|
@ -607,20 +608,20 @@ void exmc_sdram_init(exmc_sdram_parameter_struct* exmc_sdram_init_struct)
|
||||||
{
|
{
|
||||||
uint32_t sdctl0, sdctl1, sdtcfg0, sdtcfg1;
|
uint32_t sdctl0, sdctl1, sdtcfg0, sdtcfg1;
|
||||||
|
|
||||||
/* configuration EXMC_SDCTL0 or EXMC_SDCTL1 */
|
/* configure EXMC_SDCTL0 or EXMC_SDCTL1 */
|
||||||
if(EXMC_SDRAM_DEVICE0 == exmc_sdram_init_struct->sdram_device) {
|
if(EXMC_SDRAM_DEVICE0 == exmc_sdram_init_struct->sdram_device) {
|
||||||
/* configuration EXMC_SDCTL0 */
|
/* configure EXMC_SDCTL0 */
|
||||||
EXMC_SDCTL(EXMC_SDRAM_DEVICE0) = (uint32_t)exmc_sdram_init_struct->column_address_width |
|
EXMC_SDCTL(EXMC_SDRAM_DEVICE0) = (uint32_t)(exmc_sdram_init_struct->column_address_width |
|
||||||
exmc_sdram_init_struct->row_address_width |
|
exmc_sdram_init_struct->row_address_width |
|
||||||
exmc_sdram_init_struct->data_width |
|
exmc_sdram_init_struct->data_width |
|
||||||
exmc_sdram_init_struct->internal_bank_number |
|
exmc_sdram_init_struct->internal_bank_number |
|
||||||
exmc_sdram_init_struct->cas_latency |
|
exmc_sdram_init_struct->cas_latency |
|
||||||
(exmc_sdram_init_struct->write_protection << SDCTL_WPEN_OFFSET) |
|
(exmc_sdram_init_struct->write_protection << SDCTL_WPEN_OFFSET) |
|
||||||
exmc_sdram_init_struct->sdclock_config |
|
exmc_sdram_init_struct->sdclock_config |
|
||||||
(exmc_sdram_init_struct->brust_read_switch << SDCTL_BRSTRD_OFFSET)|
|
(exmc_sdram_init_struct->burst_read_switch << SDCTL_BRSTRD_OFFSET) |
|
||||||
exmc_sdram_init_struct->pipeline_read_delay;
|
exmc_sdram_init_struct->pipeline_read_delay);
|
||||||
|
|
||||||
/* configuration EXMC_SDTCFG0 */
|
/* configure EXMC_SDTCFG0 */
|
||||||
EXMC_SDTCFG(EXMC_SDRAM_DEVICE0) = (uint32_t)((exmc_sdram_init_struct->timing->load_mode_register_delay) - 1U) |
|
EXMC_SDTCFG(EXMC_SDRAM_DEVICE0) = (uint32_t)((exmc_sdram_init_struct->timing->load_mode_register_delay) - 1U) |
|
||||||
(((exmc_sdram_init_struct->timing->exit_selfrefresh_delay) - 1U) << SDTCFG_XSRD_OFFSET) |
|
(((exmc_sdram_init_struct->timing->exit_selfrefresh_delay) - 1U) << SDTCFG_XSRD_OFFSET) |
|
||||||
(((exmc_sdram_init_struct->timing->row_address_select_delay) - 1U) << SDTCFG_RASD_OFFSET) |
|
(((exmc_sdram_init_struct->timing->row_address_select_delay) - 1U) << SDTCFG_RASD_OFFSET) |
|
||||||
|
|
@ -629,42 +630,57 @@ void exmc_sdram_init(exmc_sdram_parameter_struct* exmc_sdram_init_struct)
|
||||||
(((exmc_sdram_init_struct->timing->row_precharge_delay) - 1U) << SDTCFG_RPD_OFFSET) |
|
(((exmc_sdram_init_struct->timing->row_precharge_delay) - 1U) << SDTCFG_RPD_OFFSET) |
|
||||||
(((exmc_sdram_init_struct->timing->row_to_column_delay) - 1U) << SDTCFG_RCD_OFFSET);
|
(((exmc_sdram_init_struct->timing->row_to_column_delay) - 1U) << SDTCFG_RCD_OFFSET);
|
||||||
} else {
|
} else {
|
||||||
/* configuration EXMC_SDCTL0 and EXMC_SDCTL1 */
|
/* configure EXMC_SDCTL0 and EXMC_SDCTL1 */
|
||||||
/* some bits in the EXMC_SDCTL1 register are reserved */
|
/* some bits in the EXMC_SDCTL1 register are reserved */
|
||||||
sdctl0 = EXMC_SDCTL(EXMC_SDRAM_DEVICE0) & (~(EXMC_SDCTL_PIPED | EXMC_SDCTL_BRSTRD | EXMC_SDCTL_SDCLK));
|
sdctl0 = EXMC_SDCTL(EXMC_SDRAM_DEVICE0) & (~(EXMC_SDCTL_PIPED | EXMC_SDCTL_BRSTRD | EXMC_SDCTL_SDCLK));
|
||||||
|
|
||||||
sdctl0 |= (uint32_t)exmc_sdram_init_struct->sdclock_config |
|
sdctl0 |= (uint32_t)(exmc_sdram_init_struct->sdclock_config |
|
||||||
exmc_sdram_init_struct->brust_read_switch |
|
(exmc_sdram_init_struct->burst_read_switch << SDCTL_BRSTRD_OFFSET) |
|
||||||
exmc_sdram_init_struct->pipeline_read_delay;
|
exmc_sdram_init_struct->pipeline_read_delay);
|
||||||
|
|
||||||
sdctl1 = (uint32_t)exmc_sdram_init_struct->column_address_width |
|
sdctl1 = (uint32_t)(exmc_sdram_init_struct->column_address_width |
|
||||||
exmc_sdram_init_struct->row_address_width |
|
exmc_sdram_init_struct->row_address_width |
|
||||||
exmc_sdram_init_struct->data_width |
|
exmc_sdram_init_struct->data_width |
|
||||||
exmc_sdram_init_struct->internal_bank_number |
|
exmc_sdram_init_struct->internal_bank_number |
|
||||||
exmc_sdram_init_struct->cas_latency |
|
exmc_sdram_init_struct->cas_latency |
|
||||||
exmc_sdram_init_struct->write_protection ;
|
(exmc_sdram_init_struct->write_protection << SDCTL_WPEN_OFFSET));
|
||||||
|
|
||||||
EXMC_SDCTL(EXMC_SDRAM_DEVICE0) = sdctl0;
|
EXMC_SDCTL(EXMC_SDRAM_DEVICE0) = sdctl0;
|
||||||
EXMC_SDCTL(EXMC_SDRAM_DEVICE1) = sdctl1;
|
EXMC_SDCTL(EXMC_SDRAM_DEVICE1) = sdctl1;
|
||||||
|
|
||||||
/* configuration EXMC_SDTCFG0 and EXMC_SDTCFG1 */
|
/* configure EXMC_SDTCFG0 and EXMC_SDTCFG1 */
|
||||||
/* some bits in the EXMC_SDTCFG1 register are reserved */
|
/* some bits in the EXMC_SDTCFG1 register are reserved */
|
||||||
sdtcfg0 = EXMC_SDTCFG(EXMC_SDRAM_DEVICE0) & (~(EXMC_SDTCFG_RPD | EXMC_SDTCFG_WRD | EXMC_SDTCFG_ARFD));
|
sdtcfg0 = EXMC_SDTCFG(EXMC_SDRAM_DEVICE0) & (~(EXMC_SDTCFG_RPD | EXMC_SDTCFG_WRD | EXMC_SDTCFG_ARFD));
|
||||||
|
|
||||||
sdtcfg0 |= (uint32_t)(((exmc_sdram_init_struct->timing->auto_refresh_delay)-1U) << SDTCFG_ARFD_OFFSET) |
|
sdtcfg0 |= (uint32_t)((((exmc_sdram_init_struct->timing->auto_refresh_delay) - 1U) << SDTCFG_ARFD_OFFSET) |
|
||||||
(((exmc_sdram_init_struct->timing->row_precharge_delay) - 1U) << SDTCFG_RPD_OFFSET) |
|
(((exmc_sdram_init_struct->timing->row_precharge_delay) - 1U) << SDTCFG_RPD_OFFSET) |
|
||||||
(((exmc_sdram_init_struct->timing->write_recovery_delay)-1U) << SDTCFG_WRD_OFFSET);
|
(((exmc_sdram_init_struct->timing->write_recovery_delay) - 1U) << SDTCFG_WRD_OFFSET));
|
||||||
|
|
||||||
sdtcfg1 = (uint32_t)((exmc_sdram_init_struct->timing->load_mode_register_delay)-1U) |
|
sdtcfg1 = (uint32_t)(((exmc_sdram_init_struct->timing->load_mode_register_delay) - 1U) |
|
||||||
(((exmc_sdram_init_struct->timing->exit_selfrefresh_delay) - 1U) << SDTCFG_XSRD_OFFSET) |
|
(((exmc_sdram_init_struct->timing->exit_selfrefresh_delay) - 1U) << SDTCFG_XSRD_OFFSET) |
|
||||||
(((exmc_sdram_init_struct->timing->row_address_select_delay) - 1U) << SDTCFG_RASD_OFFSET) |
|
(((exmc_sdram_init_struct->timing->row_address_select_delay) - 1U) << SDTCFG_RASD_OFFSET) |
|
||||||
(((exmc_sdram_init_struct->timing->row_to_column_delay)-1U) << SDTCFG_RCD_OFFSET);
|
(((exmc_sdram_init_struct->timing->row_to_column_delay) - 1U) << SDTCFG_RCD_OFFSET));
|
||||||
|
|
||||||
EXMC_SDTCFG(EXMC_SDRAM_DEVICE0) = sdtcfg0;
|
EXMC_SDTCFG(EXMC_SDRAM_DEVICE0) = sdtcfg0;
|
||||||
EXMC_SDTCFG(EXMC_SDRAM_DEVICE1) = sdtcfg1;
|
EXMC_SDTCFG(EXMC_SDRAM_DEVICE1) = sdtcfg1;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief initialize exmc_sdram_struct_command_para_init with the default values
|
||||||
|
\param[in] none
|
||||||
|
\param[out] the initialized struct exmc_sdram_struct_command_para_init pointer
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void exmc_sdram_struct_command_para_init(exmc_sdram_command_parameter_struct *exmc_sdram_command_init_struct)
|
||||||
|
{
|
||||||
|
/* configure the structure with default value */
|
||||||
|
exmc_sdram_command_init_struct->mode_register_content = 0U;
|
||||||
|
exmc_sdram_command_init_struct->auto_refresh_number = EXMC_SDRAM_AUTO_REFLESH_1_SDCLK;
|
||||||
|
exmc_sdram_command_init_struct->bank_select = EXMC_SDRAM_DEVICE0_SELECT;
|
||||||
|
exmc_sdram_command_init_struct->command = EXMC_SDRAM_NORMAL_OPERATION;
|
||||||
|
}
|
||||||
|
|
||||||
/*!
|
/*!
|
||||||
\brief deinitialize exmc SQPIPSRAM
|
\brief deinitialize exmc SQPIPSRAM
|
||||||
\param[in] none
|
\param[in] none
|
||||||
|
|
@ -717,7 +733,7 @@ void exmc_sqpipsram_init(exmc_sqpipsram_parameter_struct* exmc_sqpipsram_init_st
|
||||||
|
|
||||||
/*!
|
/*!
|
||||||
\brief configure consecutive clock
|
\brief configure consecutive clock
|
||||||
\param[in] clock_mode: specifie when the clock is generated
|
\param[in] clock_mode: specify when the clock is generated
|
||||||
only one parameter can be selected which is shown as below:
|
only one parameter can be selected which is shown as below:
|
||||||
\arg EXMC_CLOCK_SYN_MODE: the clock is generated only during synchronous access
|
\arg EXMC_CLOCK_SYN_MODE: the clock is generated only during synchronous access
|
||||||
\arg EXMC_CLOCK_UNCONDITIONALLY: the clock is generated unconditionally
|
\arg EXMC_CLOCK_UNCONDITIONALLY: the clock is generated unconditionally
|
||||||
|
|
@ -759,7 +775,7 @@ void exmc_norsram_page_size_config(uint32_t exmc_norsram_region, uint32_t page_s
|
||||||
|
|
||||||
/*!
|
/*!
|
||||||
\brief enable or disable the EXMC NAND ECC function
|
\brief enable or disable the EXMC NAND ECC function
|
||||||
\param[in] exmc_nand_bank: specifie the NAND bank
|
\param[in] exmc_nand_bank: specify the NAND bank
|
||||||
only one parameter can be selected which is shown as below:
|
only one parameter can be selected which is shown as below:
|
||||||
\arg EXMC_BANKx_NAND(x=1,2)
|
\arg EXMC_BANKx_NAND(x=1,2)
|
||||||
\param[in] newvalue: ENABLE or DISABLE
|
\param[in] newvalue: ENABLE or DISABLE
|
||||||
|
|
@ -779,7 +795,7 @@ void exmc_nand_ecc_config(uint32_t exmc_nand_bank, ControlStatus newvalue)
|
||||||
|
|
||||||
/*!
|
/*!
|
||||||
\brief get the EXMC ECC value
|
\brief get the EXMC ECC value
|
||||||
\param[in] exmc_nand_bank: specifie the NAND bank
|
\param[in] exmc_nand_bank: specify the NAND bank
|
||||||
only one parameter can be selected which is shown as below:
|
only one parameter can be selected which is shown as below:
|
||||||
\arg EXMC_BANKx_NAND(x=1,2)
|
\arg EXMC_BANKx_NAND(x=1,2)
|
||||||
\param[out] none
|
\param[out] none
|
||||||
|
|
@ -823,8 +839,7 @@ void exmc_sdram_readsample_config(uint32_t delay_cell, uint32_t extra_hclk)
|
||||||
/* reset the bits */
|
/* reset the bits */
|
||||||
sdrsctl = EXMC_SDRSCTL & (~(EXMC_SDRSCTL_SDSC | EXMC_SDRSCTL_SSCR));
|
sdrsctl = EXMC_SDRSCTL & (~(EXMC_SDRSCTL_SDSC | EXMC_SDRSCTL_SSCR));
|
||||||
/* set the bits */
|
/* set the bits */
|
||||||
sdrsctl |= (uint32_t)(delay_cell & EXMC_SDRSCTL_SDSC) |
|
sdrsctl |= (uint32_t)(delay_cell | extra_hclk);
|
||||||
((extra_hclk << SDRSCTL_SSCR_OFFSET) & EXMC_SDRSCTL_SSCR);
|
|
||||||
EXMC_SDRSCTL = sdrsctl;
|
EXMC_SDRSCTL = sdrsctl;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
@ -876,8 +891,8 @@ void exmc_sdram_autorefresh_number_set(uint32_t exmc_number)
|
||||||
}
|
}
|
||||||
|
|
||||||
/*!
|
/*!
|
||||||
\brief config the write protection function
|
\brief configure the write protection function
|
||||||
\param[in] exmc_sdram_device: specifie the SDRAM device
|
\param[in] exmc_sdram_device: specify the SDRAM device
|
||||||
only one parameter can be selected which is shown as below:
|
only one parameter can be selected which is shown as below:
|
||||||
\arg EXMC_SDRAM_DEVICEx(x=0,1)
|
\arg EXMC_SDRAM_DEVICEx(x=0,1)
|
||||||
\param[in] newvalue: ENABLE or DISABLE
|
\param[in] newvalue: ENABLE or DISABLE
|
||||||
|
|
@ -896,7 +911,7 @@ void exmc_sdram_write_protection_config(uint32_t exmc_sdram_device, ControlStatu
|
||||||
|
|
||||||
/*!
|
/*!
|
||||||
\brief get the status of SDRAM device0 or device1
|
\brief get the status of SDRAM device0 or device1
|
||||||
\param[in] exmc_sdram_device: specifie the SDRAM device
|
\param[in] exmc_sdram_device: specify the SDRAM device
|
||||||
only one parameter can be selected which is shown as below:
|
only one parameter can be selected which is shown as below:
|
||||||
\arg EXMC_SDRAM_DEVICEx(x=0,1)
|
\arg EXMC_SDRAM_DEVICEx(x=0,1)
|
||||||
\param[out] none
|
\param[out] none
|
||||||
|
|
@ -1036,14 +1051,14 @@ FlagStatus exmc_sqpipsram_send_command_state_get(uint32_t send_command_flag)
|
||||||
|
|
||||||
/*!
|
/*!
|
||||||
\brief enable EXMC interrupt
|
\brief enable EXMC interrupt
|
||||||
\param[in] exmc_bank: specifies the NAND bank,PC card bank or SDRAM device
|
\param[in] exmc_bank: specify the NAND bank,PC card bank or SDRAM device
|
||||||
only one parameter can be selected which is shown as below:
|
only one parameter can be selected which is shown as below:
|
||||||
\arg EXMC_BANK1_NAND: the NAND bank1
|
\arg EXMC_BANK1_NAND: the NAND bank1
|
||||||
\arg EXMC_BANK2_NAND: the NAND bank2
|
\arg EXMC_BANK2_NAND: the NAND bank2
|
||||||
\arg EXMC_BANK3_PCCARD: the PC card bank
|
\arg EXMC_BANK3_PCCARD: the PC card bank
|
||||||
\arg EXMC_SDRAM_DEVICE0: the SDRAM device0
|
\arg EXMC_SDRAM_DEVICE0: the SDRAM device0
|
||||||
\arg EXMC_SDRAM_DEVICE1: the SDRAM device1
|
\arg EXMC_SDRAM_DEVICE1: the SDRAM device1
|
||||||
\param[in] interrupt: specify get which interrupt flag
|
\param[in] interrupt: specify EXMC interrupt flag
|
||||||
only one parameter can be selected which is shown as below:
|
only one parameter can be selected which is shown as below:
|
||||||
\arg EXMC_NAND_PCCARD_INT_FLAG_RISE: rising edge interrupt and flag
|
\arg EXMC_NAND_PCCARD_INT_FLAG_RISE: rising edge interrupt and flag
|
||||||
\arg EXMC_NAND_PCCARD_INT_FLAG_LEVEL: high-level interrupt and flag
|
\arg EXMC_NAND_PCCARD_INT_FLAG_LEVEL: high-level interrupt and flag
|
||||||
|
|
@ -1065,14 +1080,14 @@ void exmc_interrupt_enable(uint32_t exmc_bank, uint32_t interrupt)
|
||||||
|
|
||||||
/*!
|
/*!
|
||||||
\brief disable EXMC interrupt
|
\brief disable EXMC interrupt
|
||||||
\param[in] exmc_bank: specifies the NAND bank , PC card bank or SDRAM device
|
\param[in] exmc_bank: specify the NAND bank , PC card bank or SDRAM device
|
||||||
only one parameter can be selected which is shown as below:
|
only one parameter can be selected which is shown as below:
|
||||||
\arg EXMC_BANK1_NAND: the NAND bank1
|
\arg EXMC_BANK1_NAND: the NAND bank1
|
||||||
\arg EXMC_BANK2_NAND: the NAND bank2
|
\arg EXMC_BANK2_NAND: the NAND bank2
|
||||||
\arg EXMC_BANK3_PCCARD: the PC card bank
|
\arg EXMC_BANK3_PCCARD: the PC card bank
|
||||||
\arg EXMC_SDRAM_DEVICE0: the SDRAM device0
|
\arg EXMC_SDRAM_DEVICE0: the SDRAM device0
|
||||||
\arg EXMC_SDRAM_DEVICE1: the SDRAM device1
|
\arg EXMC_SDRAM_DEVICE1: the SDRAM device1
|
||||||
\param[in] interrupt: specify get which interrupt flag
|
\param[in] interrupt: specify EXMC interrupt flag
|
||||||
only one parameter can be selected which is shown as below:
|
only one parameter can be selected which is shown as below:
|
||||||
\arg EXMC_NAND_PCCARD_INT_FLAG_RISE: rising edge interrupt and flag
|
\arg EXMC_NAND_PCCARD_INT_FLAG_RISE: rising edge interrupt and flag
|
||||||
\arg EXMC_NAND_PCCARD_INT_FLAG_LEVEL: high-level interrupt and flag
|
\arg EXMC_NAND_PCCARD_INT_FLAG_LEVEL: high-level interrupt and flag
|
||||||
|
|
@ -1094,7 +1109,7 @@ void exmc_interrupt_disable(uint32_t exmc_bank, uint32_t interrupt)
|
||||||
|
|
||||||
/*!
|
/*!
|
||||||
\brief get EXMC flag status
|
\brief get EXMC flag status
|
||||||
\param[in] exmc_bank: specifies the NAND bank , PC card bank or SDRAM device
|
\param[in] exmc_bank: specify the NAND bank , PC card bank or SDRAM device
|
||||||
only one parameter can be selected which is shown as below:
|
only one parameter can be selected which is shown as below:
|
||||||
\arg EXMC_BANK1_NAND: the NAND bank1
|
\arg EXMC_BANK1_NAND: the NAND bank1
|
||||||
\arg EXMC_BANK2_NAND: the NAND bank2
|
\arg EXMC_BANK2_NAND: the NAND bank2
|
||||||
|
|
@ -1135,7 +1150,7 @@ FlagStatus exmc_flag_get(uint32_t exmc_bank,uint32_t flag)
|
||||||
|
|
||||||
/*!
|
/*!
|
||||||
\brief clear EXMC flag status
|
\brief clear EXMC flag status
|
||||||
\param[in] exmc_bank: specifie the NAND bank , PCCARD bank or SDRAM device
|
\param[in] exmc_bank: specify the NAND bank , PCCARD bank or SDRAM device
|
||||||
only one parameter can be selected which is shown as below:
|
only one parameter can be selected which is shown as below:
|
||||||
\arg EXMC_BANK1_NAND: the NAND bank1
|
\arg EXMC_BANK1_NAND: the NAND bank1
|
||||||
\arg EXMC_BANK2_NAND: the NAND bank2
|
\arg EXMC_BANK2_NAND: the NAND bank2
|
||||||
|
|
@ -1166,7 +1181,7 @@ void exmc_flag_clear(uint32_t exmc_bank, uint32_t flag)
|
||||||
|
|
||||||
/*!
|
/*!
|
||||||
\brief get EXMC interrupt flag
|
\brief get EXMC interrupt flag
|
||||||
\param[in] exmc_bank: specifies the NAND bank , PC card bank or SDRAM device
|
\param[in] exmc_bank: specify the NAND bank , PC card bank or SDRAM device
|
||||||
only one parameter can be selected which is shown as below:
|
only one parameter can be selected which is shown as below:
|
||||||
\arg EXMC_BANK1_NAND: the NAND bank1
|
\arg EXMC_BANK1_NAND: the NAND bank1
|
||||||
\arg EXMC_BANK2_NAND: the NAND bank2
|
\arg EXMC_BANK2_NAND: the NAND bank2
|
||||||
|
|
@ -1209,7 +1224,7 @@ FlagStatus exmc_interrupt_flag_get(uint32_t exmc_bank, uint32_t interrupt)
|
||||||
|
|
||||||
/*!
|
/*!
|
||||||
\brief clear EXMC interrupt flag
|
\brief clear EXMC interrupt flag
|
||||||
\param[in] exmc_bank: specifies the NAND bank , PC card bank or SDRAM device
|
\param[in] exmc_bank: specify the NAND bank , PC card bank or SDRAM device
|
||||||
only one parameter can be selected which is shown as below:
|
only one parameter can be selected which is shown as below:
|
||||||
\arg EXMC_BANK1_NAND: the NAND bank1
|
\arg EXMC_BANK1_NAND: the NAND bank1
|
||||||
\arg EXMC_BANK2_NAND: the NAND bank2
|
\arg EXMC_BANK2_NAND: the NAND bank2
|
||||||
|
|
|
||||||
|
|
@ -1,14 +1,14 @@
|
||||||
/*!
|
/*!
|
||||||
\file gd32f4xx_exti.c
|
\file gd32f4xx_exti.c
|
||||||
\brief EXTI driver
|
\brief EXTI driver
|
||||||
|
|
||||||
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
||||||
\version 2018-12-12, V2.0.1, firmware for GD32F4xx
|
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
||||||
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
||||||
|
\version 2022-03-09, V3.0.0, firmware for GD32F4xx
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/*
|
/*
|
||||||
Copyright (c) 2020, GigaDevice Semiconductor Inc.
|
Copyright (c) 2022, GigaDevice Semiconductor Inc.
|
||||||
|
|
||||||
Redistribution and use in source and binary forms, with or without modification,
|
Redistribution and use in source and binary forms, with or without modification,
|
||||||
are permitted provided that the following conditions are met:
|
are permitted provided that the following conditions are met:
|
||||||
|
|
@ -36,6 +36,8 @@ OF SUCH DAMAGE.
|
||||||
|
|
||||||
#include "gd32f4xx_exti.h"
|
#include "gd32f4xx_exti.h"
|
||||||
|
|
||||||
|
#define EXTI_REG_RESET_VALUE ((uint32_t)0x00000000U)
|
||||||
|
|
||||||
/*!
|
/*!
|
||||||
\brief deinitialize the EXTI
|
\brief deinitialize the EXTI
|
||||||
\param[in] none
|
\param[in] none
|
||||||
|
|
@ -45,15 +47,15 @@ OF SUCH DAMAGE.
|
||||||
void exti_deinit(void)
|
void exti_deinit(void)
|
||||||
{
|
{
|
||||||
/* reset the value of all the EXTI registers */
|
/* reset the value of all the EXTI registers */
|
||||||
EXTI_INTEN = (uint32_t)0x00000000U;
|
EXTI_INTEN = EXTI_REG_RESET_VALUE;
|
||||||
EXTI_EVEN = (uint32_t)0x00000000U;
|
EXTI_EVEN = EXTI_REG_RESET_VALUE;
|
||||||
EXTI_RTEN = (uint32_t)0x00000000U;
|
EXTI_RTEN = EXTI_REG_RESET_VALUE;
|
||||||
EXTI_FTEN = (uint32_t)0x00000000U;
|
EXTI_FTEN = EXTI_REG_RESET_VALUE;
|
||||||
EXTI_SWIEV = (uint32_t)0x00000000U;
|
EXTI_SWIEV = EXTI_REG_RESET_VALUE;
|
||||||
}
|
}
|
||||||
|
|
||||||
/*!
|
/*!
|
||||||
\brief initialize the EXTI
|
\brief initialize the EXTI line x
|
||||||
\param[in] linex: EXTI line number, refer to exti_line_enum
|
\param[in] linex: EXTI line number, refer to exti_line_enum
|
||||||
only one parameter can be selected which is shown as below:
|
only one parameter can be selected which is shown as below:
|
||||||
\arg EXTI_x (x=0..22): EXTI line x
|
\arg EXTI_x (x=0..22): EXTI line x
|
||||||
|
|
@ -165,7 +167,7 @@ void exti_event_disable(exti_line_enum linex)
|
||||||
}
|
}
|
||||||
|
|
||||||
/*!
|
/*!
|
||||||
\brief enable EXTI software interrupt event
|
\brief enable the software interrupt event from EXTI line x
|
||||||
\param[in] linex: EXTI line number, refer to exti_line_enum
|
\param[in] linex: EXTI line number, refer to exti_line_enum
|
||||||
only one parameter can be selected which is shown as below:
|
only one parameter can be selected which is shown as below:
|
||||||
\arg EXTI_x (x=0..22): EXTI line x
|
\arg EXTI_x (x=0..22): EXTI line x
|
||||||
|
|
@ -178,7 +180,7 @@ void exti_software_interrupt_enable(exti_line_enum linex)
|
||||||
}
|
}
|
||||||
|
|
||||||
/*!
|
/*!
|
||||||
\brief disable EXTI software interrupt event
|
\brief disable the software interrupt event from EXTI line x
|
||||||
\param[in] linex: EXTI line number, refer to exti_line_enum
|
\param[in] linex: EXTI line number, refer to exti_line_enum
|
||||||
only one parameter can be selected which is shown as below:
|
only one parameter can be selected which is shown as below:
|
||||||
\arg EXTI_x (x=0..22): EXTI line x
|
\arg EXTI_x (x=0..22): EXTI line x
|
||||||
|
|
@ -191,7 +193,7 @@ void exti_software_interrupt_disable(exti_line_enum linex)
|
||||||
}
|
}
|
||||||
|
|
||||||
/*!
|
/*!
|
||||||
\brief get EXTI lines flag
|
\brief get EXTI line x interrupt pending flag
|
||||||
\param[in] linex: EXTI line number, refer to exti_line_enum
|
\param[in] linex: EXTI line number, refer to exti_line_enum
|
||||||
only one parameter can be selected which is shown as below:
|
only one parameter can be selected which is shown as below:
|
||||||
\arg EXTI_x (x=0..22): EXTI line x
|
\arg EXTI_x (x=0..22): EXTI line x
|
||||||
|
|
@ -208,7 +210,7 @@ FlagStatus exti_flag_get(exti_line_enum linex)
|
||||||
}
|
}
|
||||||
|
|
||||||
/*!
|
/*!
|
||||||
\brief clear EXTI lines pending flag
|
\brief clear EXTI line x interrupt pending flag
|
||||||
\param[in] linex: EXTI line number, refer to exti_line_enum
|
\param[in] linex: EXTI line number, refer to exti_line_enum
|
||||||
only one parameter can be selected which is shown as below:
|
only one parameter can be selected which is shown as below:
|
||||||
\arg EXTI_x (x=0..22): EXTI line x
|
\arg EXTI_x (x=0..22): EXTI line x
|
||||||
|
|
@ -221,7 +223,7 @@ void exti_flag_clear(exti_line_enum linex)
|
||||||
}
|
}
|
||||||
|
|
||||||
/*!
|
/*!
|
||||||
\brief get EXTI lines flag when the interrupt flag is set
|
\brief get EXTI line x interrupt pending flag
|
||||||
\param[in] linex: EXTI line number, refer to exti_line_enum
|
\param[in] linex: EXTI line number, refer to exti_line_enum
|
||||||
only one parameter can be selected which is shown as below:
|
only one parameter can be selected which is shown as below:
|
||||||
\arg EXTI_x (x=0..22): EXTI line x
|
\arg EXTI_x (x=0..22): EXTI line x
|
||||||
|
|
@ -230,12 +232,7 @@ void exti_flag_clear(exti_line_enum linex)
|
||||||
*/
|
*/
|
||||||
FlagStatus exti_interrupt_flag_get(exti_line_enum linex)
|
FlagStatus exti_interrupt_flag_get(exti_line_enum linex)
|
||||||
{
|
{
|
||||||
uint32_t flag_left, flag_right;
|
if(RESET != (EXTI_PD & (uint32_t)linex)) {
|
||||||
|
|
||||||
flag_left = EXTI_PD & (uint32_t)linex;
|
|
||||||
flag_right = EXTI_INTEN & (uint32_t)linex;
|
|
||||||
|
|
||||||
if((RESET != flag_left) && (RESET != flag_right)){
|
|
||||||
return SET;
|
return SET;
|
||||||
} else {
|
} else {
|
||||||
return RESET;
|
return RESET;
|
||||||
|
|
@ -243,7 +240,7 @@ FlagStatus exti_interrupt_flag_get(exti_line_enum linex)
|
||||||
}
|
}
|
||||||
|
|
||||||
/*!
|
/*!
|
||||||
\brief clear EXTI lines pending flag
|
\brief clear EXTI line x interrupt pending flag
|
||||||
\param[in] linex: EXTI line number, refer to exti_line_enum
|
\param[in] linex: EXTI line number, refer to exti_line_enum
|
||||||
only one parameter can be selected which is shown as below:
|
only one parameter can be selected which is shown as below:
|
||||||
\arg EXTI_x (x=0..22): EXTI line x
|
\arg EXTI_x (x=0..22): EXTI line x
|
||||||
|
|
@ -254,4 +251,3 @@ void exti_interrupt_flag_clear(exti_line_enum linex)
|
||||||
{
|
{
|
||||||
EXTI_PD = (uint32_t)linex;
|
EXTI_PD = (uint32_t)linex;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -5,10 +5,11 @@
|
||||||
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
||||||
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
||||||
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
||||||
|
\version 2022-03-09, V3.0.0, firmware for GD32F4xx
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/*
|
/*
|
||||||
Copyright (c) 2020, GigaDevice Semiconductor Inc.
|
Copyright (c) 2022, GigaDevice Semiconductor Inc.
|
||||||
|
|
||||||
Redistribution and use in source and binary forms, with or without modification,
|
Redistribution and use in source and binary forms, with or without modification,
|
||||||
are permitted provided that the following conditions are met:
|
are permitted provided that the following conditions are met:
|
||||||
|
|
@ -38,7 +39,7 @@ OF SUCH DAMAGE.
|
||||||
#include "gd32f4xx_fmc.h"
|
#include "gd32f4xx_fmc.h"
|
||||||
|
|
||||||
/*!
|
/*!
|
||||||
\brief set the wait state counter value
|
\brief set the FMC wait state counter
|
||||||
\param[in] wscnt: wait state counter value
|
\param[in] wscnt: wait state counter value
|
||||||
only one parameter can be selected which is shown as below:
|
only one parameter can be selected which is shown as below:
|
||||||
\arg WS_WSCNT_0: FMC 0 wait
|
\arg WS_WSCNT_0: FMC 0 wait
|
||||||
|
|
@ -97,8 +98,54 @@ void fmc_lock(void)
|
||||||
FMC_CTL |= FMC_CTL_LK;
|
FMC_CTL |= FMC_CTL_LK;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
#if defined (GD32F425) || defined (GD32F427) || defined (GD32F470)
|
||||||
|
|
||||||
/*!
|
/*!
|
||||||
\brief erase sector
|
\brief FMC erase page
|
||||||
|
\param[in] page_addr: the page address to be erased.
|
||||||
|
\param[out] none
|
||||||
|
\retval state of FMC
|
||||||
|
\arg FMC_READY: the operation has been completed
|
||||||
|
\arg FMC_BUSY: the operation is in progress
|
||||||
|
\arg FMC_RDDERR: read D-bus protection error
|
||||||
|
\arg FMC_PGSERR: program sequence error
|
||||||
|
\arg FMC_PGMERR: program size not match error
|
||||||
|
\arg FMC_WPERR: erase/program protection error
|
||||||
|
\arg FMC_OPERR: operation error
|
||||||
|
\arg FMC_TOERR: timeout error
|
||||||
|
*/
|
||||||
|
fmc_state_enum fmc_page_erase(uint32_t page_addr)
|
||||||
|
{
|
||||||
|
fmc_state_enum fmc_state = FMC_READY;
|
||||||
|
|
||||||
|
/* wait for the FMC ready */
|
||||||
|
fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
|
||||||
|
|
||||||
|
if(FMC_READY == fmc_state) {
|
||||||
|
/* unlock page erase operation */
|
||||||
|
FMC_PEKEY = UNLOCK_PE_KEY;
|
||||||
|
|
||||||
|
/* start page erase */
|
||||||
|
FMC_PECFG = FMC_PE_EN | page_addr;
|
||||||
|
FMC_CTL &= ~FMC_CTL_SN;
|
||||||
|
FMC_CTL |= FMC_CTL_SER;
|
||||||
|
FMC_CTL |= FMC_CTL_START;
|
||||||
|
|
||||||
|
/* wait for the FMC ready */
|
||||||
|
fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
|
||||||
|
|
||||||
|
FMC_PECFG &= ~FMC_PE_EN;
|
||||||
|
FMC_CTL &= ~FMC_CTL_SER;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* return the FMC state */
|
||||||
|
return fmc_state;
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief FMC erase sector
|
||||||
\param[in] fmc_sector: select the sector to erase
|
\param[in] fmc_sector: select the sector to erase
|
||||||
only one parameter can be selected which is shown as below:
|
only one parameter can be selected which is shown as below:
|
||||||
\arg CTL_SECTOR_NUMBER_0: sector 0
|
\arg CTL_SECTOR_NUMBER_0: sector 0
|
||||||
|
|
@ -138,13 +185,13 @@ void fmc_lock(void)
|
||||||
\arg FMC_PGMERR: program size not match error
|
\arg FMC_PGMERR: program size not match error
|
||||||
\arg FMC_WPERR: erase/program protection error
|
\arg FMC_WPERR: erase/program protection error
|
||||||
\arg FMC_OPERR: operation error
|
\arg FMC_OPERR: operation error
|
||||||
\arg FMC_PGERR: program error
|
\arg FMC_TOERR: timeout error
|
||||||
*/
|
*/
|
||||||
fmc_state_enum fmc_sector_erase(uint32_t fmc_sector)
|
fmc_state_enum fmc_sector_erase(uint32_t fmc_sector)
|
||||||
{
|
{
|
||||||
fmc_state_enum fmc_state = FMC_READY;
|
fmc_state_enum fmc_state = FMC_READY;
|
||||||
/* wait for the FMC ready */
|
/* wait for the FMC ready */
|
||||||
fmc_state = fmc_ready_wait();
|
fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
|
||||||
|
|
||||||
if(FMC_READY == fmc_state) {
|
if(FMC_READY == fmc_state) {
|
||||||
/* start sector erase */
|
/* start sector erase */
|
||||||
|
|
@ -153,7 +200,7 @@ fmc_state_enum fmc_sector_erase(uint32_t fmc_sector)
|
||||||
FMC_CTL |= FMC_CTL_START;
|
FMC_CTL |= FMC_CTL_START;
|
||||||
|
|
||||||
/* wait for the FMC ready */
|
/* wait for the FMC ready */
|
||||||
fmc_state = fmc_ready_wait();
|
fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
|
||||||
|
|
||||||
/* reset the SER bit */
|
/* reset the SER bit */
|
||||||
FMC_CTL &= (~FMC_CTL_SER);
|
FMC_CTL &= (~FMC_CTL_SER);
|
||||||
|
|
@ -165,7 +212,7 @@ fmc_state_enum fmc_sector_erase(uint32_t fmc_sector)
|
||||||
}
|
}
|
||||||
|
|
||||||
/*!
|
/*!
|
||||||
\brief erase whole chip
|
\brief FMC erase whole chip
|
||||||
\param[in] none
|
\param[in] none
|
||||||
\param[out] none
|
\param[out] none
|
||||||
\retval state of FMC
|
\retval state of FMC
|
||||||
|
|
@ -176,13 +223,13 @@ fmc_state_enum fmc_sector_erase(uint32_t fmc_sector)
|
||||||
\arg FMC_PGMERR: program size not match error
|
\arg FMC_PGMERR: program size not match error
|
||||||
\arg FMC_WPERR: erase/program protection error
|
\arg FMC_WPERR: erase/program protection error
|
||||||
\arg FMC_OPERR: operation error
|
\arg FMC_OPERR: operation error
|
||||||
\arg FMC_PGERR: program error
|
\arg FMC_TOERR: timeout error
|
||||||
*/
|
*/
|
||||||
fmc_state_enum fmc_mass_erase(void)
|
fmc_state_enum fmc_mass_erase(void)
|
||||||
{
|
{
|
||||||
fmc_state_enum fmc_state = FMC_READY;
|
fmc_state_enum fmc_state = FMC_READY;
|
||||||
/* wait for the FMC ready */
|
/* wait for the FMC ready */
|
||||||
fmc_state = fmc_ready_wait();
|
fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
|
||||||
|
|
||||||
if(FMC_READY == fmc_state) {
|
if(FMC_READY == fmc_state) {
|
||||||
/* start whole chip erase */
|
/* start whole chip erase */
|
||||||
|
|
@ -190,7 +237,7 @@ fmc_state_enum fmc_mass_erase(void)
|
||||||
FMC_CTL |= FMC_CTL_START;
|
FMC_CTL |= FMC_CTL_START;
|
||||||
|
|
||||||
/* wait for the FMC ready */
|
/* wait for the FMC ready */
|
||||||
fmc_state = fmc_ready_wait();
|
fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
|
||||||
|
|
||||||
/* reset the MER bits */
|
/* reset the MER bits */
|
||||||
FMC_CTL &= ~(FMC_CTL_MER0 | FMC_CTL_MER1);
|
FMC_CTL &= ~(FMC_CTL_MER0 | FMC_CTL_MER1);
|
||||||
|
|
@ -201,7 +248,7 @@ fmc_state_enum fmc_mass_erase(void)
|
||||||
}
|
}
|
||||||
|
|
||||||
/*!
|
/*!
|
||||||
\brief erase all FMC sectors in bank0
|
\brief FMC erase whole bank0
|
||||||
\param[in] none
|
\param[in] none
|
||||||
\param[out] none
|
\param[out] none
|
||||||
\retval state of FMC
|
\retval state of FMC
|
||||||
|
|
@ -212,13 +259,13 @@ fmc_state_enum fmc_mass_erase(void)
|
||||||
\arg FMC_PGMERR: program size not match error
|
\arg FMC_PGMERR: program size not match error
|
||||||
\arg FMC_WPERR: erase/program protection error
|
\arg FMC_WPERR: erase/program protection error
|
||||||
\arg FMC_OPERR: operation error
|
\arg FMC_OPERR: operation error
|
||||||
\arg FMC_PGERR: program error
|
\arg FMC_TOERR: timeout error
|
||||||
*/
|
*/
|
||||||
fmc_state_enum fmc_bank0_erase(void)
|
fmc_state_enum fmc_bank0_erase(void)
|
||||||
{
|
{
|
||||||
fmc_state_enum fmc_state = FMC_READY;
|
fmc_state_enum fmc_state = FMC_READY;
|
||||||
/* wait for the FMC ready */
|
/* wait for the FMC ready */
|
||||||
fmc_state = fmc_ready_wait();
|
fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
|
||||||
|
|
||||||
if(FMC_READY == fmc_state) {
|
if(FMC_READY == fmc_state) {
|
||||||
/* start FMC bank0 erase */
|
/* start FMC bank0 erase */
|
||||||
|
|
@ -226,7 +273,7 @@ fmc_state_enum fmc_bank0_erase(void)
|
||||||
FMC_CTL |= FMC_CTL_START;
|
FMC_CTL |= FMC_CTL_START;
|
||||||
|
|
||||||
/* wait for the FMC ready */
|
/* wait for the FMC ready */
|
||||||
fmc_state = fmc_ready_wait();
|
fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
|
||||||
|
|
||||||
/* reset the MER0 bit */
|
/* reset the MER0 bit */
|
||||||
FMC_CTL &= (~FMC_CTL_MER0);
|
FMC_CTL &= (~FMC_CTL_MER0);
|
||||||
|
|
@ -237,7 +284,7 @@ fmc_state_enum fmc_bank0_erase(void)
|
||||||
}
|
}
|
||||||
|
|
||||||
/*!
|
/*!
|
||||||
\brief erase all FMC sectors in bank1
|
\brief FMC erase whole bank1
|
||||||
\param[in] none
|
\param[in] none
|
||||||
\param[out] none
|
\param[out] none
|
||||||
\retval state of FMC
|
\retval state of FMC
|
||||||
|
|
@ -248,13 +295,13 @@ fmc_state_enum fmc_bank0_erase(void)
|
||||||
\arg FMC_PGMERR: program size not match error
|
\arg FMC_PGMERR: program size not match error
|
||||||
\arg FMC_WPERR: erase/program protection error
|
\arg FMC_WPERR: erase/program protection error
|
||||||
\arg FMC_OPERR: operation error
|
\arg FMC_OPERR: operation error
|
||||||
\arg FMC_PGERR: program error
|
\arg FMC_TOERR: timeout error
|
||||||
*/
|
*/
|
||||||
fmc_state_enum fmc_bank1_erase(void)
|
fmc_state_enum fmc_bank1_erase(void)
|
||||||
{
|
{
|
||||||
fmc_state_enum fmc_state = FMC_READY;
|
fmc_state_enum fmc_state = FMC_READY;
|
||||||
/* wait for the FMC ready */
|
/* wait for the FMC ready */
|
||||||
fmc_state = fmc_ready_wait();
|
fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
|
||||||
|
|
||||||
if(FMC_READY == fmc_state) {
|
if(FMC_READY == fmc_state) {
|
||||||
/* start FMC bank1 erase */
|
/* start FMC bank1 erase */
|
||||||
|
|
@ -262,7 +309,7 @@ fmc_state_enum fmc_bank1_erase(void)
|
||||||
FMC_CTL |= FMC_CTL_START;
|
FMC_CTL |= FMC_CTL_START;
|
||||||
|
|
||||||
/* wait for the FMC ready */
|
/* wait for the FMC ready */
|
||||||
fmc_state = fmc_ready_wait();
|
fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
|
||||||
|
|
||||||
/* reset the MER1 bit */
|
/* reset the MER1 bit */
|
||||||
FMC_CTL &= (~FMC_CTL_MER1);
|
FMC_CTL &= (~FMC_CTL_MER1);
|
||||||
|
|
@ -285,13 +332,13 @@ fmc_state_enum fmc_bank1_erase(void)
|
||||||
\arg FMC_PGMERR: program size not match error
|
\arg FMC_PGMERR: program size not match error
|
||||||
\arg FMC_WPERR: erase/program protection error
|
\arg FMC_WPERR: erase/program protection error
|
||||||
\arg FMC_OPERR: operation error
|
\arg FMC_OPERR: operation error
|
||||||
\arg FMC_PGERR: program error
|
\arg FMC_TOERR: timeout error
|
||||||
*/
|
*/
|
||||||
fmc_state_enum fmc_word_program(uint32_t address, uint32_t data)
|
fmc_state_enum fmc_word_program(uint32_t address, uint32_t data)
|
||||||
{
|
{
|
||||||
fmc_state_enum fmc_state = FMC_READY;
|
fmc_state_enum fmc_state = FMC_READY;
|
||||||
/* wait for the FMC ready */
|
/* wait for the FMC ready */
|
||||||
fmc_state = fmc_ready_wait();
|
fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
|
||||||
|
|
||||||
if(FMC_READY == fmc_state) {
|
if(FMC_READY == fmc_state) {
|
||||||
/* set the PG bit to start program */
|
/* set the PG bit to start program */
|
||||||
|
|
@ -302,7 +349,7 @@ fmc_state_enum fmc_word_program(uint32_t address, uint32_t data)
|
||||||
REG32(address) = data;
|
REG32(address) = data;
|
||||||
|
|
||||||
/* wait for the FMC ready */
|
/* wait for the FMC ready */
|
||||||
fmc_state = fmc_ready_wait();
|
fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
|
||||||
|
|
||||||
/* reset the PG bit */
|
/* reset the PG bit */
|
||||||
FMC_CTL &= ~FMC_CTL_PG;
|
FMC_CTL &= ~FMC_CTL_PG;
|
||||||
|
|
@ -325,13 +372,13 @@ fmc_state_enum fmc_word_program(uint32_t address, uint32_t data)
|
||||||
\arg FMC_PGMERR: program size not match error
|
\arg FMC_PGMERR: program size not match error
|
||||||
\arg FMC_WPERR: erase/program protection error
|
\arg FMC_WPERR: erase/program protection error
|
||||||
\arg FMC_OPERR: operation error
|
\arg FMC_OPERR: operation error
|
||||||
\arg FMC_PGERR: program error
|
\arg FMC_TOERR: timeout error
|
||||||
*/
|
*/
|
||||||
fmc_state_enum fmc_halfword_program(uint32_t address, uint16_t data)
|
fmc_state_enum fmc_halfword_program(uint32_t address, uint16_t data)
|
||||||
{
|
{
|
||||||
fmc_state_enum fmc_state = FMC_READY;
|
fmc_state_enum fmc_state = FMC_READY;
|
||||||
/* wait for the FMC ready */
|
/* wait for the FMC ready */
|
||||||
fmc_state = fmc_ready_wait();
|
fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
|
||||||
|
|
||||||
if(FMC_READY == fmc_state) {
|
if(FMC_READY == fmc_state) {
|
||||||
/* set the PG bit to start program */
|
/* set the PG bit to start program */
|
||||||
|
|
@ -342,7 +389,7 @@ fmc_state_enum fmc_halfword_program(uint32_t address, uint16_t data)
|
||||||
REG16(address) = data;
|
REG16(address) = data;
|
||||||
|
|
||||||
/* wait for the FMC ready */
|
/* wait for the FMC ready */
|
||||||
fmc_state = fmc_ready_wait();
|
fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
|
||||||
|
|
||||||
/* reset the PG bit */
|
/* reset the PG bit */
|
||||||
FMC_CTL &= ~FMC_CTL_PG;
|
FMC_CTL &= ~FMC_CTL_PG;
|
||||||
|
|
@ -365,13 +412,13 @@ fmc_state_enum fmc_halfword_program(uint32_t address, uint16_t data)
|
||||||
\arg FMC_PGMERR: program size not match error
|
\arg FMC_PGMERR: program size not match error
|
||||||
\arg FMC_WPERR: erase/program protection error
|
\arg FMC_WPERR: erase/program protection error
|
||||||
\arg FMC_OPERR: operation error
|
\arg FMC_OPERR: operation error
|
||||||
\arg FMC_PGERR: program error
|
\arg FMC_TOERR: timeout error
|
||||||
*/
|
*/
|
||||||
fmc_state_enum fmc_byte_program(uint32_t address, uint8_t data)
|
fmc_state_enum fmc_byte_program(uint32_t address, uint8_t data)
|
||||||
{
|
{
|
||||||
fmc_state_enum fmc_state = FMC_READY;
|
fmc_state_enum fmc_state = FMC_READY;
|
||||||
/* wait for the FMC ready */
|
/* wait for the FMC ready */
|
||||||
fmc_state = fmc_ready_wait();
|
fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
|
||||||
|
|
||||||
if(FMC_READY == fmc_state) {
|
if(FMC_READY == fmc_state) {
|
||||||
/* set the PG bit to start program */
|
/* set the PG bit to start program */
|
||||||
|
|
@ -382,7 +429,7 @@ fmc_state_enum fmc_byte_program(uint32_t address, uint8_t data)
|
||||||
REG8(address) = data;
|
REG8(address) = data;
|
||||||
|
|
||||||
/* wait for the FMC ready */
|
/* wait for the FMC ready */
|
||||||
fmc_state = fmc_ready_wait();
|
fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
|
||||||
|
|
||||||
/* reset the PG bit */
|
/* reset the PG bit */
|
||||||
FMC_CTL &= ~FMC_CTL_PG;
|
FMC_CTL &= ~FMC_CTL_PG;
|
||||||
|
|
@ -427,14 +474,8 @@ void ob_lock(void)
|
||||||
*/
|
*/
|
||||||
void ob_start(void)
|
void ob_start(void)
|
||||||
{
|
{
|
||||||
fmc_state_enum fmc_state = FMC_READY;
|
|
||||||
/* set the OB_START bit in OBCTL0 register */
|
/* set the OB_START bit in OBCTL0 register */
|
||||||
FMC_OBCTL0 |= FMC_OBCTL0_OB_START;
|
FMC_OBCTL0 |= FMC_OBCTL0_OB_START;
|
||||||
fmc_state = fmc_ready_wait();
|
|
||||||
if(FMC_READY != fmc_state){
|
|
||||||
while(1){
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
}
|
||||||
|
|
||||||
/*!
|
/*!
|
||||||
|
|
@ -448,12 +489,12 @@ void ob_erase(void)
|
||||||
uint32_t reg, reg1;
|
uint32_t reg, reg1;
|
||||||
fmc_state_enum fmc_state = FMC_READY;
|
fmc_state_enum fmc_state = FMC_READY;
|
||||||
/* wait for the FMC ready */
|
/* wait for the FMC ready */
|
||||||
fmc_state = fmc_ready_wait();
|
fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
|
||||||
|
|
||||||
if(FMC_READY == fmc_state){
|
|
||||||
reg = FMC_OBCTL0;
|
reg = FMC_OBCTL0;
|
||||||
reg1 = FMC_OBCTL1;
|
reg1 = FMC_OBCTL1;
|
||||||
|
|
||||||
|
if(FMC_READY == fmc_state) {
|
||||||
|
|
||||||
/* reset the OB_FWDGT, OB_DEEPSLEEP and OB_STDBY, set according to ob_fwdgt ,ob_deepsleep and ob_stdby */
|
/* reset the OB_FWDGT, OB_DEEPSLEEP and OB_STDBY, set according to ob_fwdgt ,ob_deepsleep and ob_stdby */
|
||||||
reg |= (FMC_OBCTL0_NWDG_HW | FMC_OBCTL0_NRST_DPSLP | FMC_OBCTL0_NRST_STDBY);
|
reg |= (FMC_OBCTL0_NWDG_HW | FMC_OBCTL0_NRST_DPSLP | FMC_OBCTL0_NRST_STDBY);
|
||||||
/* reset the BOR level */
|
/* reset the BOR level */
|
||||||
|
|
@ -483,25 +524,28 @@ void ob_erase(void)
|
||||||
\arg OB_WP_23_27: sector23~27
|
\arg OB_WP_23_27: sector23~27
|
||||||
\arg OB_WP_ALL: all sector
|
\arg OB_WP_ALL: all sector
|
||||||
\param[out] none
|
\param[out] none
|
||||||
\retval none
|
\retval SUCCESS or ERROR
|
||||||
*/
|
*/
|
||||||
void ob_write_protection_enable(uint32_t ob_wp)
|
ErrStatus ob_write_protection_enable(uint32_t ob_wp)
|
||||||
{
|
{
|
||||||
uint32_t reg0 = FMC_OBCTL0;
|
uint32_t reg0 = FMC_OBCTL0;
|
||||||
uint32_t reg1 = FMC_OBCTL1;
|
uint32_t reg1 = FMC_OBCTL1;
|
||||||
fmc_state_enum fmc_state = FMC_READY;
|
fmc_state_enum fmc_state = FMC_READY;
|
||||||
if(RESET != (FMC_OBCTL0 & FMC_OBCTL0_DRP)) {
|
if(RESET != (FMC_OBCTL0 & FMC_OBCTL0_DRP)) {
|
||||||
while(1){
|
return ERROR;
|
||||||
}
|
|
||||||
}
|
}
|
||||||
/* wait for the FMC ready */
|
/* wait for the FMC ready */
|
||||||
fmc_state = fmc_ready_wait();
|
fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
|
||||||
|
|
||||||
if(FMC_READY == fmc_state) {
|
if(FMC_READY == fmc_state) {
|
||||||
reg0 &= (~((uint32_t)ob_wp << 16));
|
reg0 &= (~((uint32_t)ob_wp << 16U));
|
||||||
reg1 &= (~(ob_wp & 0xFFFF0000U));
|
reg1 &= (~(ob_wp & 0xFFFF0000U));
|
||||||
FMC_OBCTL0 = reg0;
|
FMC_OBCTL0 = reg0;
|
||||||
FMC_OBCTL1 = reg1;
|
FMC_OBCTL1 = reg1;
|
||||||
|
|
||||||
|
return SUCCESS;
|
||||||
|
} else {
|
||||||
|
return ERROR;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
@ -513,25 +557,28 @@ void ob_write_protection_enable(uint32_t ob_wp)
|
||||||
\arg OB_WP_23_27: sector23~27
|
\arg OB_WP_23_27: sector23~27
|
||||||
\arg OB_WP_ALL: all sector
|
\arg OB_WP_ALL: all sector
|
||||||
\param[out] none
|
\param[out] none
|
||||||
\retval none
|
\retval SUCCESS or ERROR
|
||||||
*/
|
*/
|
||||||
void ob_write_protection_disable(uint32_t ob_wp)
|
ErrStatus ob_write_protection_disable(uint32_t ob_wp)
|
||||||
{
|
{
|
||||||
uint32_t reg0 = FMC_OBCTL0;
|
uint32_t reg0 = FMC_OBCTL0;
|
||||||
uint32_t reg1 = FMC_OBCTL1;
|
uint32_t reg1 = FMC_OBCTL1;
|
||||||
fmc_state_enum fmc_state = FMC_READY;
|
fmc_state_enum fmc_state = FMC_READY;
|
||||||
if(RESET != (FMC_OBCTL0 & FMC_OBCTL0_DRP)) {
|
if(RESET != (FMC_OBCTL0 & FMC_OBCTL0_DRP)) {
|
||||||
while(1){
|
return ERROR;
|
||||||
}
|
|
||||||
}
|
}
|
||||||
/* wait for the FMC ready */
|
/* wait for the FMC ready */
|
||||||
fmc_state = fmc_ready_wait();
|
fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
|
||||||
|
|
||||||
if(FMC_READY == fmc_state) {
|
if(FMC_READY == fmc_state) {
|
||||||
reg0 |= ((uint32_t)ob_wp << 16);
|
reg0 |= ((uint32_t)ob_wp << 16U);
|
||||||
reg1 |= (ob_wp & 0xFFFF0000U);
|
reg1 |= (ob_wp & 0xFFFF0000U);
|
||||||
FMC_OBCTL0 = reg0;
|
FMC_OBCTL0 = reg0;
|
||||||
FMC_OBCTL1 = reg1;
|
FMC_OBCTL1 = reg1;
|
||||||
|
|
||||||
|
return SUCCESS;
|
||||||
|
} else {
|
||||||
|
return ERROR;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
@ -553,50 +600,58 @@ void ob_drp_enable(uint32_t ob_drp)
|
||||||
uint32_t drp_state = FMC_OBCTL0 & FMC_OBCTL0_DRP;
|
uint32_t drp_state = FMC_OBCTL0 & FMC_OBCTL0_DRP;
|
||||||
uint32_t wp0_state = FMC_OBCTL0 & FMC_OBCTL0_WP0;
|
uint32_t wp0_state = FMC_OBCTL0 & FMC_OBCTL0_WP0;
|
||||||
uint32_t wp1_state = FMC_OBCTL1 & FMC_OBCTL1_WP1;
|
uint32_t wp1_state = FMC_OBCTL1 & FMC_OBCTL1_WP1;
|
||||||
/*disable write protection before enable D-bus read protection*/
|
|
||||||
if((RESET != drp_state) && ((FMC_OBCTL0_WP0 != wp0_state) && (FMC_OBCTL1_WP1 != wp1_state))){
|
|
||||||
while(1){
|
|
||||||
}
|
|
||||||
}
|
|
||||||
/* wait for the FMC ready */
|
/* wait for the FMC ready */
|
||||||
fmc_state = fmc_ready_wait();
|
fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
|
||||||
|
|
||||||
if(FMC_READY == fmc_state) {
|
if(FMC_READY == fmc_state) {
|
||||||
|
if(RESET == drp_state) {
|
||||||
reg0 &= ~FMC_OBCTL0_WP0;
|
reg0 &= ~FMC_OBCTL0_WP0;
|
||||||
reg1 &= ~FMC_OBCTL1_WP1;
|
reg1 &= ~FMC_OBCTL1_WP1;
|
||||||
reg0 |= ((uint32_t)ob_drp << 16);
|
}
|
||||||
|
reg0 |= ((uint32_t)ob_drp << 16U);
|
||||||
|
reg0 |= FMC_OBCTL0_DRP;
|
||||||
reg1 |= ((uint32_t)ob_drp & 0xFFFF0000U);
|
reg1 |= ((uint32_t)ob_drp & 0xFFFF0000U);
|
||||||
|
|
||||||
FMC_OBCTL0 = reg0;
|
FMC_OBCTL0 = reg0;
|
||||||
FMC_OBCTL1 = reg1;
|
FMC_OBCTL1 = reg1;
|
||||||
FMC_OBCTL0 |= FMC_OBCTL0_DRP;
|
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
/*!
|
/*!
|
||||||
\brief disable erase/program protection and D-bus read protection
|
\brief disable erase/program protection and D-bus read protection
|
||||||
\param[in] ob_drp: disable the WPx bits used as erase/program protection and D-bus read protection of each sector
|
\param[in] none
|
||||||
one or more parameters can be selected which are shown as below:
|
|
||||||
\arg OB_DRP_x(x=0..22): sector x(x = 0,1,2...22)
|
|
||||||
\arg OB_DRP_23_27: sector23~27
|
|
||||||
\arg OB_DRP_ALL: all sector
|
|
||||||
\param[out] none
|
\param[out] none
|
||||||
\retval none
|
\retval none
|
||||||
*/
|
*/
|
||||||
void ob_drp_disable(uint32_t ob_drp)
|
void ob_drp_disable(void)
|
||||||
{
|
{
|
||||||
uint32_t reg0 = FMC_OBCTL0;
|
uint32_t reg0 = FMC_OBCTL0;
|
||||||
uint32_t reg1 = FMC_OBCTL1;
|
uint32_t reg1 = FMC_OBCTL1;
|
||||||
fmc_state_enum fmc_state = FMC_READY;
|
fmc_state_enum fmc_state = FMC_READY;
|
||||||
/* wait for the FMC ready */
|
/* wait for the FMC ready */
|
||||||
fmc_state = fmc_ready_wait();
|
fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
|
||||||
|
|
||||||
if(FMC_READY == fmc_state) {
|
if(FMC_READY == fmc_state) {
|
||||||
|
if(((uint8_t)(reg0 >> 8U)) == (uint8_t)FMC_NSPC) {
|
||||||
|
/* security protection should be set as low level protection before disable D-BUS read protection */
|
||||||
|
reg0 &= ~FMC_OBCTL0_SPC;
|
||||||
|
reg0 |= ((uint32_t)FMC_LSPC << 8U);
|
||||||
|
FMC_OBCTL0 = reg0;
|
||||||
|
/* set the OB_START bit in OBCTL0 register */
|
||||||
|
FMC_OBCTL0 |= FMC_OBCTL0_OB_START;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* it is necessary to disable the security protection at the same time when D-BUS read protection is disabled */
|
||||||
|
reg0 &= ~FMC_OBCTL0_SPC;
|
||||||
|
reg0 |= ((uint32_t)FMC_NSPC << 8U);
|
||||||
reg0 |= FMC_OBCTL0_WP0;
|
reg0 |= FMC_OBCTL0_WP0;
|
||||||
reg0 &= (~FMC_OBCTL0_DRP);
|
reg0 &= (~FMC_OBCTL0_DRP);
|
||||||
FMC_OBCTL0 = reg0;
|
FMC_OBCTL0 = reg0;
|
||||||
|
|
||||||
reg1 |= FMC_OBCTL1_WP1;
|
reg1 |= FMC_OBCTL1_WP1;
|
||||||
FMC_OBCTL1 = reg1;
|
FMC_OBCTL1 = reg1;
|
||||||
|
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
@ -614,7 +669,7 @@ void ob_security_protection_config(uint8_t ob_spc)
|
||||||
{
|
{
|
||||||
fmc_state_enum fmc_state = FMC_READY;
|
fmc_state_enum fmc_state = FMC_READY;
|
||||||
/* wait for the FMC ready */
|
/* wait for the FMC ready */
|
||||||
fmc_state = fmc_ready_wait();
|
fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
|
||||||
|
|
||||||
if(FMC_READY == fmc_state) {
|
if(FMC_READY == fmc_state) {
|
||||||
uint32_t reg;
|
uint32_t reg;
|
||||||
|
|
@ -622,7 +677,7 @@ void ob_security_protection_config(uint8_t ob_spc)
|
||||||
reg = FMC_OBCTL0;
|
reg = FMC_OBCTL0;
|
||||||
/* reset the OBCTL0_SPC, set according to ob_spc */
|
/* reset the OBCTL0_SPC, set according to ob_spc */
|
||||||
reg &= ~FMC_OBCTL0_SPC;
|
reg &= ~FMC_OBCTL0_SPC;
|
||||||
reg |= ((uint32_t)ob_spc << 8);
|
reg |= ((uint32_t)ob_spc << 8U);
|
||||||
FMC_OBCTL0 = reg;
|
FMC_OBCTL0 = reg;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
@ -649,7 +704,7 @@ void ob_user_write(uint32_t ob_fwdgt, uint32_t ob_deepsleep, uint32_t ob_stdby)
|
||||||
fmc_state_enum fmc_state = FMC_READY;
|
fmc_state_enum fmc_state = FMC_READY;
|
||||||
|
|
||||||
/* wait for the FMC ready */
|
/* wait for the FMC ready */
|
||||||
fmc_state = fmc_ready_wait();
|
fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
|
||||||
|
|
||||||
if(FMC_READY == fmc_state) {
|
if(FMC_READY == fmc_state) {
|
||||||
uint32_t reg;
|
uint32_t reg;
|
||||||
|
|
@ -709,7 +764,7 @@ void ob_boot_mode_config(uint32_t boot_mode)
|
||||||
*/
|
*/
|
||||||
uint8_t ob_user_get(void)
|
uint8_t ob_user_get(void)
|
||||||
{
|
{
|
||||||
return (uint8_t)((uint8_t)(FMC_OBCTL0 >> 5) & (uint8_t)0x07);
|
return (uint8_t)((uint8_t)(FMC_OBCTL0 >> 5U) & 0x07U);
|
||||||
}
|
}
|
||||||
|
|
||||||
/*!
|
/*!
|
||||||
|
|
@ -721,7 +776,7 @@ uint8_t ob_user_get(void)
|
||||||
uint16_t ob_write_protection0_get(void)
|
uint16_t ob_write_protection0_get(void)
|
||||||
{
|
{
|
||||||
/* return the FMC write protection option byte value */
|
/* return the FMC write protection option byte value */
|
||||||
return (uint16_t)(((uint16_t)(FMC_OBCTL0 >> 16)) & (uint16_t)0x0FFF);
|
return (uint16_t)(((uint16_t)(FMC_OBCTL0 >> 16U)) & 0x0FFFU);
|
||||||
}
|
}
|
||||||
|
|
||||||
/*!
|
/*!
|
||||||
|
|
@ -733,11 +788,11 @@ uint16_t ob_write_protection0_get(void)
|
||||||
uint16_t ob_write_protection1_get(void)
|
uint16_t ob_write_protection1_get(void)
|
||||||
{
|
{
|
||||||
/* return the the FMC write protection option byte value */
|
/* return the the FMC write protection option byte value */
|
||||||
return (uint16_t)(((uint16_t)(FMC_OBCTL1 >> 16)) & (uint16_t)0x0FFF);
|
return (uint16_t)(((uint16_t)(FMC_OBCTL1 >> 16U)) & 0x0FFFU);
|
||||||
}
|
}
|
||||||
|
|
||||||
/*!
|
/*!
|
||||||
\brief get the FMC D-bus read protection protection
|
\brief get the FMC erase/program protection and D-bus read protection option bytes value
|
||||||
\param[in] none
|
\param[in] none
|
||||||
\param[out] none
|
\param[out] none
|
||||||
\retval the FMC erase/program protection and D-bus read protection option bytes value
|
\retval the FMC erase/program protection and D-bus read protection option bytes value
|
||||||
|
|
@ -745,11 +800,15 @@ uint16_t ob_write_protection1_get(void)
|
||||||
uint16_t ob_drp0_get(void)
|
uint16_t ob_drp0_get(void)
|
||||||
{
|
{
|
||||||
/* return the FMC erase/program protection and D-bus read protection option bytes value */
|
/* return the FMC erase/program protection and D-bus read protection option bytes value */
|
||||||
return (uint16_t)(((uint16_t)(FMC_OBCTL0 >> 16)) & (uint16_t)0x0FFF);
|
if(FMC_OBCTL0 & FMC_OBCTL0_DRP) {
|
||||||
|
return (uint16_t)(((uint16_t)(FMC_OBCTL0 >> 16U)) & 0x0FFFU);
|
||||||
|
} else {
|
||||||
|
return 0xF000U;
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
/*!
|
/*!
|
||||||
\brief get the FMC D-bus read protection protection
|
\brief get the FMC erase/program protection and D-bus read protection option bytes value
|
||||||
\param[in] none
|
\param[in] none
|
||||||
\param[out] none
|
\param[out] none
|
||||||
\retval the FMC erase/program protection and D-bus read protection option bytes value
|
\retval the FMC erase/program protection and D-bus read protection option bytes value
|
||||||
|
|
@ -757,11 +816,15 @@ uint16_t ob_drp0_get(void)
|
||||||
uint16_t ob_drp1_get(void)
|
uint16_t ob_drp1_get(void)
|
||||||
{
|
{
|
||||||
/* return the FMC erase/program protection and D-bus read protection option bytes value */
|
/* return the FMC erase/program protection and D-bus read protection option bytes value */
|
||||||
return (uint16_t)(((uint16_t)(FMC_OBCTL1 >> 16)) & (uint16_t)0x0FFF);
|
if(FMC_OBCTL0 & FMC_OBCTL0_DRP) {
|
||||||
|
return (uint16_t)(((uint16_t)(FMC_OBCTL1 >> 16U)) & 0x0FFFU);
|
||||||
|
} else {
|
||||||
|
return 0xF000U;
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
/*!
|
/*!
|
||||||
\brief get the FMC option byte security protection
|
\brief get option byte security protection code value
|
||||||
\param[in] none
|
\param[in] none
|
||||||
\param[out] none
|
\param[out] none
|
||||||
\retval FlagStatus: SET or RESET
|
\retval FlagStatus: SET or RESET
|
||||||
|
|
@ -770,7 +833,7 @@ FlagStatus ob_spc_get(void)
|
||||||
{
|
{
|
||||||
FlagStatus spc_state = RESET;
|
FlagStatus spc_state = RESET;
|
||||||
|
|
||||||
if (((uint8_t)(FMC_OBCTL0 >> 8)) != (uint8_t)FMC_NSPC){
|
if(((uint8_t)(FMC_OBCTL0 >> 8U)) != FMC_NSPC) {
|
||||||
spc_state = SET;
|
spc_state = SET;
|
||||||
} else {
|
} else {
|
||||||
spc_state = RESET;
|
spc_state = RESET;
|
||||||
|
|
@ -787,35 +850,7 @@ FlagStatus ob_spc_get(void)
|
||||||
uint8_t ob_user_bor_threshold_get(void)
|
uint8_t ob_user_bor_threshold_get(void)
|
||||||
{
|
{
|
||||||
/* return the FMC BOR threshold value */
|
/* return the FMC BOR threshold value */
|
||||||
return (uint8_t)((uint8_t)FMC_OBCTL0 & (uint8_t)0x0C);
|
return (uint8_t)((uint8_t)FMC_OBCTL0 & 0x0CU);
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
\brief enable FMC interrupt
|
|
||||||
\param[in] fmc_int: the FMC interrupt source
|
|
||||||
only one parameter can be selected which is shown as below:
|
|
||||||
\arg FMC_INT_END: enable FMC end of program interrupt
|
|
||||||
\arg FMC_INT_ERR: enable FMC error interrupt
|
|
||||||
\param[out] none
|
|
||||||
\retval none
|
|
||||||
*/
|
|
||||||
void fmc_interrupt_enable(uint32_t fmc_int)
|
|
||||||
{
|
|
||||||
FMC_CTL |= fmc_int;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
\brief disable FMC interrupt
|
|
||||||
\param[in] fmc_int: the FMC interrupt source
|
|
||||||
only one parameter can be selected which is shown as below:
|
|
||||||
\arg FMC_INT_END: disable FMC end of program interrupt
|
|
||||||
\arg FMC_INT_ERR: disable FMC error interrupt
|
|
||||||
\param[out] none
|
|
||||||
\retval none
|
|
||||||
*/
|
|
||||||
void fmc_interrupt_disable(uint32_t fmc_int)
|
|
||||||
{
|
|
||||||
FMC_CTL &= ~(uint32_t)fmc_int;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
/*!
|
/*!
|
||||||
|
|
@ -860,6 +895,87 @@ void fmc_flag_clear(uint32_t fmc_flag)
|
||||||
FMC_STAT = fmc_flag;
|
FMC_STAT = fmc_flag;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief enable FMC interrupt
|
||||||
|
\param[in] fmc_int: the FMC interrupt source
|
||||||
|
only one parameter can be selected which is shown as below:
|
||||||
|
\arg FMC_INT_END: enable FMC end of program interrupt
|
||||||
|
\arg FMC_INT_ERR: enable FMC error interrupt
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void fmc_interrupt_enable(uint32_t fmc_int)
|
||||||
|
{
|
||||||
|
FMC_CTL |= fmc_int;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief disable FMC interrupt
|
||||||
|
\param[in] fmc_int: the FMC interrupt source
|
||||||
|
only one parameter can be selected which is shown as below:
|
||||||
|
\arg FMC_INT_END: disable FMC end of program interrupt
|
||||||
|
\arg FMC_INT_ERR: disable FMC error interrupt
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void fmc_interrupt_disable(uint32_t fmc_int)
|
||||||
|
{
|
||||||
|
FMC_CTL &= ~(uint32_t)fmc_int;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief get FMC interrupt flag set or reset
|
||||||
|
\param[in] fmc_int_flag: FMC interrupt flag
|
||||||
|
only one parameter can be selected which is shown as below:
|
||||||
|
\arg FMC_INT_FLAG_RDDERR: FMC read D-bus protection error interrupt flag
|
||||||
|
\arg FMC_INT_FLAG_PGSERR: FMC program sequence error interrupt flag
|
||||||
|
\arg FMC_INT_FLAG_PGMERR: FMC program size not match error interrupt flag
|
||||||
|
\arg FMC_INT_FLAG_WPERR: FMC Erase/Program protection error interrupt flag
|
||||||
|
\arg FMC_INT_FLAG_OPERR: FMC operation error interrupt flag
|
||||||
|
\arg FMC_INT_FLAG_END: FMC end of operation interrupt flag
|
||||||
|
\param[out] none
|
||||||
|
\retval FlagStatus: SET or RESET
|
||||||
|
*/
|
||||||
|
FlagStatus fmc_interrupt_flag_get(uint32_t fmc_int_flag)
|
||||||
|
{
|
||||||
|
if(FMC_FLAG_END == fmc_int_flag) {
|
||||||
|
/* end of operation interrupt flag */
|
||||||
|
if(FMC_CTL & FMC_CTL_ENDIE) {
|
||||||
|
if(FMC_STAT & fmc_int_flag) {
|
||||||
|
return SET;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
} else {
|
||||||
|
/* error interrupt flags */
|
||||||
|
if(FMC_CTL & FMC_CTL_ERRIE) {
|
||||||
|
if(FMC_STAT & fmc_int_flag) {
|
||||||
|
return SET;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
return RESET;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief clear the FMC interrupt flag
|
||||||
|
\param[in] fmc_int_flag: FMC interrupt flag
|
||||||
|
only one parameter can be selected which is shown as below:
|
||||||
|
\arg FMC_INT_FLAG_RDDERR: FMC read D-bus protection error interrupt flag
|
||||||
|
\arg FMC_INT_FLAG_PGSERR: FMC program sequence error interrupt flag
|
||||||
|
\arg FMC_INT_FLAG_PGMERR: FMC program size not match error interrupt flag
|
||||||
|
\arg FMC_INT_FLAG_WPERR: FMC Erase/Program protection error interrupt flag
|
||||||
|
\arg FMC_INT_FLAG_OPERR: FMC operation error interrupt flag
|
||||||
|
\arg FMC_INT_FLAG_END: FMC end of operation interrupt flag
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void fmc_interrupt_flag_clear(uint32_t fmc_int_flag)
|
||||||
|
{
|
||||||
|
/* clear the interrupt flag */
|
||||||
|
FMC_STAT = fmc_int_flag;
|
||||||
|
}
|
||||||
|
|
||||||
/*!
|
/*!
|
||||||
\brief get the FMC state
|
\brief get the FMC state
|
||||||
\param[in] none
|
\param[in] none
|
||||||
|
|
@ -872,33 +988,28 @@ void fmc_flag_clear(uint32_t fmc_flag)
|
||||||
\arg FMC_PGMERR: program size not match error
|
\arg FMC_PGMERR: program size not match error
|
||||||
\arg FMC_WPERR: erase/program protection error
|
\arg FMC_WPERR: erase/program protection error
|
||||||
\arg FMC_OPERR: operation error
|
\arg FMC_OPERR: operation error
|
||||||
\arg FMC_PGERR: program error
|
|
||||||
*/
|
*/
|
||||||
fmc_state_enum fmc_state_get(void)
|
fmc_state_enum fmc_state_get(void)
|
||||||
{
|
{
|
||||||
fmc_state_enum fmc_state = FMC_READY;
|
fmc_state_enum fmc_state = FMC_READY;
|
||||||
|
uint32_t temp_val = FMC_STAT;
|
||||||
|
|
||||||
if((FMC_STAT & FMC_FLAG_BUSY) == FMC_FLAG_BUSY){
|
if(RESET != (temp_val & FMC_FLAG_BUSY)) {
|
||||||
fmc_state = FMC_BUSY;
|
fmc_state = FMC_BUSY;
|
||||||
}else{
|
} else if(RESET != (temp_val & FMC_FLAG_RDDERR)) {
|
||||||
if((FMC_STAT & FMC_FLAG_WPERR) != (uint32_t)0x00){
|
|
||||||
fmc_state = FMC_WPERR;
|
|
||||||
}else{
|
|
||||||
if((FMC_STAT & FMC_FLAG_RDDERR) != (uint32_t)0x00){
|
|
||||||
fmc_state = FMC_RDDERR;
|
fmc_state = FMC_RDDERR;
|
||||||
}else{
|
} else if(RESET != (temp_val & FMC_FLAG_PGSERR)) {
|
||||||
if((FMC_STAT & (uint32_t)0xEF) != (uint32_t)0x00){
|
fmc_state = FMC_PGSERR;
|
||||||
fmc_state = FMC_PGERR;
|
} else if(RESET != (temp_val & FMC_FLAG_PGMERR)) {
|
||||||
}else{
|
fmc_state = FMC_PGMERR;
|
||||||
if((FMC_STAT & FMC_FLAG_OPERR) != (uint32_t)0x00){
|
} else if(RESET != (temp_val & FMC_FLAG_WPERR)) {
|
||||||
|
fmc_state = FMC_WPERR;
|
||||||
|
} else if(RESET != (temp_val & FMC_FLAG_OPERR)) {
|
||||||
fmc_state = FMC_OPERR;
|
fmc_state = FMC_OPERR;
|
||||||
} else {
|
} else {
|
||||||
fmc_state = FMC_READY;
|
fmc_state = FMC_READY;
|
||||||
}
|
}
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
/* return the FMC state */
|
/* return the FMC state */
|
||||||
return fmc_state;
|
return fmc_state;
|
||||||
}
|
}
|
||||||
|
|
@ -915,9 +1026,9 @@ fmc_state_enum fmc_state_get(void)
|
||||||
\arg FMC_PGMERR: program size not match error
|
\arg FMC_PGMERR: program size not match error
|
||||||
\arg FMC_WPERR: erase/program protection error
|
\arg FMC_WPERR: erase/program protection error
|
||||||
\arg FMC_OPERR: operation error
|
\arg FMC_OPERR: operation error
|
||||||
\arg FMC_PGERR: program error
|
\arg FMC_TOERR: timeout error
|
||||||
*/
|
*/
|
||||||
fmc_state_enum fmc_ready_wait(void)
|
fmc_state_enum fmc_ready_wait(uint32_t timeout)
|
||||||
{
|
{
|
||||||
fmc_state_enum fmc_state = FMC_BUSY;
|
fmc_state_enum fmc_state = FMC_BUSY;
|
||||||
|
|
||||||
|
|
@ -925,7 +1036,12 @@ fmc_state_enum fmc_ready_wait(void)
|
||||||
do {
|
do {
|
||||||
/* get FMC state */
|
/* get FMC state */
|
||||||
fmc_state = fmc_state_get();
|
fmc_state = fmc_state_get();
|
||||||
}while(FMC_BUSY == fmc_state);
|
timeout--;
|
||||||
|
} while((FMC_BUSY == fmc_state) && (0U != timeout));
|
||||||
|
|
||||||
|
if(0U == timeout) {
|
||||||
|
fmc_state = FMC_TOERR;
|
||||||
|
}
|
||||||
|
|
||||||
/* return the FMC state */
|
/* return the FMC state */
|
||||||
return fmc_state;
|
return fmc_state;
|
||||||
|
|
|
||||||
|
|
@ -5,10 +5,11 @@
|
||||||
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
||||||
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
||||||
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
||||||
|
\version 2022-03-09, V3.0.0, firmware for GD32F4xx
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/*
|
/*
|
||||||
Copyright (c) 2020, GigaDevice Semiconductor Inc.
|
Copyright (c) 2022, GigaDevice Semiconductor Inc.
|
||||||
|
|
||||||
Redistribution and use in source and binary forms, with or without modification,
|
Redistribution and use in source and binary forms, with or without modification,
|
||||||
are permitted provided that the following conditions are met:
|
are permitted provided that the following conditions are met:
|
||||||
|
|
@ -36,11 +37,6 @@ OF SUCH DAMAGE.
|
||||||
|
|
||||||
#include "gd32f4xx_fwdgt.h"
|
#include "gd32f4xx_fwdgt.h"
|
||||||
|
|
||||||
/* write value to FWDGT_CTL_CMD bit field */
|
|
||||||
#define CTL_CMD(regval) (BITS(0,15) & ((uint32_t)(regval) << 0))
|
|
||||||
/* write value to FWDGT_RLD_RLD bit field */
|
|
||||||
#define RLD_RLD(regval) (BITS(0,11) & ((uint32_t)(regval) << 0))
|
|
||||||
|
|
||||||
/*!
|
/*!
|
||||||
\brief enable write access to FWDGT_PSC and FWDGT_RLD
|
\brief enable write access to FWDGT_PSC and FWDGT_RLD
|
||||||
\param[in] none
|
\param[in] none
|
||||||
|
|
@ -74,6 +70,71 @@ void fwdgt_enable(void)
|
||||||
FWDGT_CTL = FWDGT_KEY_ENABLE;
|
FWDGT_CTL = FWDGT_KEY_ENABLE;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief configure the free watchdog timer counter prescaler value
|
||||||
|
\param[in] prescaler_value: specify prescaler value
|
||||||
|
only one parameter can be selected which is shown as below:
|
||||||
|
\arg FWDGT_PSC_DIV4: FWDGT prescaler set to 4
|
||||||
|
\arg FWDGT_PSC_DIV8: FWDGT prescaler set to 8
|
||||||
|
\arg FWDGT_PSC_DIV16: FWDGT prescaler set to 16
|
||||||
|
\arg FWDGT_PSC_DIV32: FWDGT prescaler set to 32
|
||||||
|
\arg FWDGT_PSC_DIV64: FWDGT prescaler set to 64
|
||||||
|
\arg FWDGT_PSC_DIV128: FWDGT prescaler set to 128
|
||||||
|
\arg FWDGT_PSC_DIV256: FWDGT prescaler set to 256
|
||||||
|
\param[out] none
|
||||||
|
\retval ErrStatus: ERROR or SUCCESS
|
||||||
|
*/
|
||||||
|
ErrStatus fwdgt_prescaler_value_config(uint16_t prescaler_value)
|
||||||
|
{
|
||||||
|
uint32_t timeout = FWDGT_PSC_TIMEOUT;
|
||||||
|
uint32_t flag_status = RESET;
|
||||||
|
|
||||||
|
/* enable write access to FWDGT_PSC */
|
||||||
|
FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE;
|
||||||
|
|
||||||
|
/* wait until the PUD flag to be reset */
|
||||||
|
do{
|
||||||
|
flag_status = FWDGT_STAT & FWDGT_STAT_PUD;
|
||||||
|
}while((--timeout > 0U) && ((uint32_t)RESET != flag_status));
|
||||||
|
|
||||||
|
if ((uint32_t)RESET != flag_status){
|
||||||
|
return ERROR;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* configure FWDGT */
|
||||||
|
FWDGT_PSC = (uint32_t)prescaler_value;
|
||||||
|
|
||||||
|
return SUCCESS;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief configure the free watchdog timer counter reload value
|
||||||
|
\param[in] reload_value: specify reload value(0x0000 - 0x0FFF)
|
||||||
|
\param[out] none
|
||||||
|
\retval ErrStatus: ERROR or SUCCESS
|
||||||
|
*/
|
||||||
|
ErrStatus fwdgt_reload_value_config(uint16_t reload_value)
|
||||||
|
{
|
||||||
|
uint32_t timeout = FWDGT_RLD_TIMEOUT;
|
||||||
|
uint32_t flag_status = RESET;
|
||||||
|
|
||||||
|
/* enable write access to FWDGT_RLD */
|
||||||
|
FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE;
|
||||||
|
|
||||||
|
/* wait until the RUD flag to be reset */
|
||||||
|
do{
|
||||||
|
flag_status = FWDGT_STAT & FWDGT_STAT_RUD;
|
||||||
|
}while((--timeout > 0U) && ((uint32_t)RESET != flag_status));
|
||||||
|
|
||||||
|
if ((uint32_t)RESET != flag_status){
|
||||||
|
return ERROR;
|
||||||
|
}
|
||||||
|
|
||||||
|
FWDGT_RLD = RLD_RLD(reload_value);
|
||||||
|
|
||||||
|
return SUCCESS;
|
||||||
|
}
|
||||||
|
|
||||||
/*!
|
/*!
|
||||||
\brief reload the counter of FWDGT
|
\brief reload the counter of FWDGT
|
||||||
\param[in] none
|
\param[in] none
|
||||||
|
|
|
||||||
|
|
@ -5,10 +5,11 @@
|
||||||
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
||||||
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
||||||
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
||||||
|
\version 2022-03-09, V3.0.0, firmware for GD32F4xx
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/*
|
/*
|
||||||
Copyright (c) 2020, GigaDevice Semiconductor Inc.
|
Copyright (c) 2022, GigaDevice Semiconductor Inc.
|
||||||
|
|
||||||
Redistribution and use in source and binary forms, with or without modification,
|
Redistribution and use in source and binary forms, with or without modification,
|
||||||
are permitted provided that the following conditions are met:
|
are permitted provided that the following conditions are met:
|
||||||
|
|
@ -155,7 +156,7 @@ void gpio_mode_set(uint32_t gpio_periph, uint32_t mode, uint32_t pull_up_down, u
|
||||||
\arg GPIO_OSPEED_2MHZ: output max speed 2MHz
|
\arg GPIO_OSPEED_2MHZ: output max speed 2MHz
|
||||||
\arg GPIO_OSPEED_25MHZ: output max speed 25MHz
|
\arg GPIO_OSPEED_25MHZ: output max speed 25MHz
|
||||||
\arg GPIO_OSPEED_50MHZ: output max speed 50MHz
|
\arg GPIO_OSPEED_50MHZ: output max speed 50MHz
|
||||||
\arg GPIO_OSPEED_200MHZ: output max speed 200MHz
|
\arg GPIO_OSPEED_MAX: output max speed more than 50MHz
|
||||||
\param[in] pin: GPIO pin
|
\param[in] pin: GPIO pin
|
||||||
one or more parameters can be selected which are shown as below:
|
one or more parameters can be selected which are shown as below:
|
||||||
\arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL
|
\arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL
|
||||||
|
|
@ -310,7 +311,7 @@ FlagStatus gpio_output_bit_get(uint32_t gpio_periph, uint32_t pin)
|
||||||
}
|
}
|
||||||
|
|
||||||
/*!
|
/*!
|
||||||
\brief get GPIO all pins output status
|
\brief get GPIO port output status
|
||||||
\param[in] gpio_periph: GPIO port
|
\param[in] gpio_periph: GPIO port
|
||||||
only one parameter can be selected which is shown as below:
|
only one parameter can be selected which is shown as below:
|
||||||
\arg GPIOx(x = A,B,C,D,E,F,G,H,I)
|
\arg GPIOx(x = A,B,C,D,E,F,G,H,I)
|
||||||
|
|
@ -334,10 +335,10 @@ uint16_t gpio_output_port_get(uint32_t gpio_periph)
|
||||||
\arg GPIO_AF_3: TIMER7, TIMER8, TIMER9, TIMER10
|
\arg GPIO_AF_3: TIMER7, TIMER8, TIMER9, TIMER10
|
||||||
\arg GPIO_AF_4: I2C0, I2C1, I2C2
|
\arg GPIO_AF_4: I2C0, I2C1, I2C2
|
||||||
\arg GPIO_AF_5: SPI0, SPI1, SPI2, SPI3, SPI4, SPI5
|
\arg GPIO_AF_5: SPI0, SPI1, SPI2, SPI3, SPI4, SPI5
|
||||||
\arg GPIO_AF_6: SPI1, SPI2, SAI0
|
\arg GPIO_AF_6: SPI2, SPI3, SPI4
|
||||||
\arg GPIO_AF_7: USART0, USART1, USART2
|
\arg GPIO_AF_7: USART0, USART1, USART2, SPI1, SPI2
|
||||||
\arg GPIO_AF_8: UART3, UART4, USART5, UART6, UART7
|
\arg GPIO_AF_8: UART3, UART4, USART5, UART6, UART7
|
||||||
\arg GPIO_AF_9: CAN0, CAN1, TLI, TIMER11, TIMER12, TIMER13
|
\arg GPIO_AF_9: CAN0, CAN1, TLI, TIMER11, TIMER12, TIMER13, I2C1, I2C2, CTC
|
||||||
\arg GPIO_AF_10: USB_FS, USB_HS
|
\arg GPIO_AF_10: USB_FS, USB_HS
|
||||||
\arg GPIO_AF_11: ENET
|
\arg GPIO_AF_11: ENET
|
||||||
\arg GPIO_AF_12: EXMC, SDIO, USB_HS
|
\arg GPIO_AF_12: EXMC, SDIO, USB_HS
|
||||||
|
|
|
||||||
|
|
@ -6,10 +6,11 @@
|
||||||
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
||||||
\version 2019-04-16, V2.0.2, firmware for GD32F4xx
|
\version 2019-04-16, V2.0.2, firmware for GD32F4xx
|
||||||
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
||||||
|
\version 2022-03-09, V3.0.0, firmware for GD32F4xx
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/*
|
/*
|
||||||
Copyright (c) 2020, GigaDevice Semiconductor Inc.
|
Copyright (c) 2022, GigaDevice Semiconductor Inc.
|
||||||
|
|
||||||
Redistribution and use in source and binary forms, with or without modification,
|
Redistribution and use in source and binary forms, with or without modification,
|
||||||
are permitted provided that the following conditions are met:
|
are permitted provided that the following conditions are met:
|
||||||
|
|
@ -38,14 +39,14 @@ OF SUCH DAMAGE.
|
||||||
#include "gd32f4xx_i2c.h"
|
#include "gd32f4xx_i2c.h"
|
||||||
|
|
||||||
/* I2C register bit mask */
|
/* I2C register bit mask */
|
||||||
#define I2CCLK_MAX ((uint32_t)0x00000032U) /*!< i2cclk maximum value */
|
#define I2CCLK_MAX ((uint32_t)0x0000003CU) /*!< i2cclk maximum value */
|
||||||
#define I2CCLK_MIN ((uint32_t)0x00000002U) /*!< i2cclk minimum value */
|
#define I2CCLK_MIN ((uint32_t)0x00000002U) /*!< i2cclk minimum value */
|
||||||
#define I2C_FLAG_MASK ((uint32_t)0x0000FFFFU) /*!< i2c flag mask */
|
#define I2C_FLAG_MASK ((uint32_t)0x0000FFFFU) /*!< i2c flag mask */
|
||||||
#define I2C_ADDRESS_MASK ((uint32_t)0x000003FFU) /*!< i2c address mask */
|
#define I2C_ADDRESS_MASK ((uint32_t)0x000003FFU) /*!< i2c address mask */
|
||||||
#define I2C_ADDRESS2_MASK ((uint32_t)0x000000FEU) /*!< the second i2c address mask */
|
#define I2C_ADDRESS2_MASK ((uint32_t)0x000000FEU) /*!< the second i2c address mask */
|
||||||
|
|
||||||
/* I2C register bit offset */
|
/* I2C register bit offset */
|
||||||
#define STAT1_PECV_OFFSET ((uint32_t)8U) /* bit offset of PECV in I2C_STAT1 */
|
#define STAT1_PECV_OFFSET ((uint32_t)0x00000008U) /* bit offset of PECV in I2C_STAT1 */
|
||||||
|
|
||||||
/*!
|
/*!
|
||||||
\brief reset I2C
|
\brief reset I2C
|
||||||
|
|
@ -82,8 +83,8 @@ void i2c_deinit(uint32_t i2c_periph)
|
||||||
\param[in] clkspeed: I2C clock speed, supports standard mode (up to 100 kHz), fast mode (up to 400 kHz)
|
\param[in] clkspeed: I2C clock speed, supports standard mode (up to 100 kHz), fast mode (up to 400 kHz)
|
||||||
\param[in] dutycyc: duty cycle in fast mode
|
\param[in] dutycyc: duty cycle in fast mode
|
||||||
only one parameter can be selected which is shown as below:
|
only one parameter can be selected which is shown as below:
|
||||||
\arg I2C_DTCY_2: T_low/T_high=2
|
\arg I2C_DTCY_2: T_low/T_high = 2 in fast mode
|
||||||
\arg I2C_DTCY_16_9: T_low/T_high=16/9
|
\arg I2C_DTCY_16_9: T_low/T_high = 16/9 in fast mode
|
||||||
\param[out] none
|
\param[out] none
|
||||||
\retval none
|
\retval none
|
||||||
*/
|
*/
|
||||||
|
|
@ -109,6 +110,8 @@ void i2c_clock_config(uint32_t i2c_periph, uint32_t clkspeed, uint32_t dutycyc)
|
||||||
risetime = (uint32_t)((pclk1 / 1000000U) + 1U);
|
risetime = (uint32_t)((pclk1 / 1000000U) + 1U);
|
||||||
if(risetime >= I2CCLK_MAX) {
|
if(risetime >= I2CCLK_MAX) {
|
||||||
I2C_RT(i2c_periph) = I2CCLK_MAX;
|
I2C_RT(i2c_periph) = I2CCLK_MAX;
|
||||||
|
} else if(risetime <= I2CCLK_MIN) {
|
||||||
|
I2C_RT(i2c_periph) = I2CCLK_MIN;
|
||||||
} else {
|
} else {
|
||||||
I2C_RT(i2c_periph) = risetime;
|
I2C_RT(i2c_periph) = risetime;
|
||||||
}
|
}
|
||||||
|
|
@ -151,8 +154,8 @@ void i2c_clock_config(uint32_t i2c_periph, uint32_t clkspeed, uint32_t dutycyc)
|
||||||
\arg I2C_SMBUSMODE_ENABLE: SMBus mode
|
\arg I2C_SMBUSMODE_ENABLE: SMBus mode
|
||||||
\param[in] addformat: 7bits or 10bits
|
\param[in] addformat: 7bits or 10bits
|
||||||
only one parameter can be selected which is shown as below:
|
only one parameter can be selected which is shown as below:
|
||||||
\arg I2C_ADDFORMAT_7BITS: 7bits
|
\arg I2C_ADDFORMAT_7BITS: address format is 7 bits
|
||||||
\arg I2C_ADDFORMAT_10BITS: 10bits
|
\arg I2C_ADDFORMAT_10BITS: address format is 10 bits
|
||||||
\param[in] addr: I2C address
|
\param[in] addr: I2C address
|
||||||
\param[out] none
|
\param[out] none
|
||||||
\retval none
|
\retval none
|
||||||
|
|
@ -172,12 +175,12 @@ void i2c_mode_addr_config(uint32_t i2c_periph, uint32_t mode, uint32_t addformat
|
||||||
}
|
}
|
||||||
|
|
||||||
/*!
|
/*!
|
||||||
\brief SMBus type selection
|
\brief select SMBus type
|
||||||
\param[in] i2c_periph: I2Cx(x=0,1,2)
|
\param[in] i2c_periph: I2Cx(x=0,1,2)
|
||||||
\param[in] type:
|
\param[in] type:
|
||||||
only one parameter can be selected which is shown as below:
|
only one parameter can be selected which is shown as below:
|
||||||
\arg I2C_SMBUS_DEVICE: device
|
\arg I2C_SMBUS_DEVICE: SMBus mode device type
|
||||||
\arg I2C_SMBUS_HOST: host
|
\arg I2C_SMBUS_HOST: SMBus mode host type
|
||||||
\param[out] none
|
\param[out] none
|
||||||
\retval none
|
\retval none
|
||||||
*/
|
*/
|
||||||
|
|
@ -202,11 +205,12 @@ void i2c_smbus_type_config(uint32_t i2c_periph, uint32_t type)
|
||||||
*/
|
*/
|
||||||
void i2c_ack_config(uint32_t i2c_periph, uint32_t ack)
|
void i2c_ack_config(uint32_t i2c_periph, uint32_t ack)
|
||||||
{
|
{
|
||||||
if(I2C_ACK_ENABLE == ack){
|
uint32_t ctl = 0U;
|
||||||
I2C_CTL0(i2c_periph) |= I2C_CTL0_ACKEN;
|
|
||||||
}else{
|
ctl = I2C_CTL0(i2c_periph);
|
||||||
I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_ACKEN);
|
ctl &= ~(I2C_CTL0_ACKEN);
|
||||||
}
|
ctl |= ack;
|
||||||
|
I2C_CTL0(i2c_periph) = ctl;
|
||||||
}
|
}
|
||||||
|
|
||||||
/*!
|
/*!
|
||||||
|
|
@ -214,19 +218,19 @@ void i2c_ack_config(uint32_t i2c_periph, uint32_t ack)
|
||||||
\param[in] i2c_periph: I2Cx(x=0,1,2)
|
\param[in] i2c_periph: I2Cx(x=0,1,2)
|
||||||
\param[in] pos:
|
\param[in] pos:
|
||||||
only one parameter can be selected which is shown as below:
|
only one parameter can be selected which is shown as below:
|
||||||
\arg I2C_ACKPOS_CURRENT: whether to send ACK or not for the current
|
\arg I2C_ACKPOS_CURRENT: ACKEN bit decides whether or not to send ACK or not for the current byte
|
||||||
\arg I2C_ACKPOS_NEXT: whether to send ACK or not for the next byte
|
\arg I2C_ACKPOS_NEXT: ACKEN bit decides whether or not to send ACK for the next byte
|
||||||
\param[out] none
|
\param[out] none
|
||||||
\retval none
|
\retval none
|
||||||
*/
|
*/
|
||||||
void i2c_ackpos_config(uint32_t i2c_periph, uint32_t pos)
|
void i2c_ackpos_config(uint32_t i2c_periph, uint32_t pos)
|
||||||
{
|
{
|
||||||
|
uint32_t ctl = 0U;
|
||||||
/* configure I2C POAP position */
|
/* configure I2C POAP position */
|
||||||
if(I2C_ACKPOS_NEXT == pos){
|
ctl = I2C_CTL0(i2c_periph);
|
||||||
I2C_CTL0(i2c_periph) |= I2C_CTL0_POAP;
|
ctl &= ~(I2C_CTL0_POAP);
|
||||||
}else{
|
ctl |= pos;
|
||||||
I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_POAP);
|
I2C_CTL0(i2c_periph) = ctl;
|
||||||
}
|
|
||||||
}
|
}
|
||||||
|
|
||||||
/*!
|
/*!
|
||||||
|
|
@ -345,16 +349,16 @@ uint8_t i2c_data_receive(uint32_t i2c_periph)
|
||||||
}
|
}
|
||||||
|
|
||||||
/*!
|
/*!
|
||||||
\brief enable I2C DMA mode
|
\brief configure I2C DMA mode
|
||||||
\param[in] i2c_periph: I2Cx(x=0,1,2)
|
\param[in] i2c_periph: I2Cx(x=0,1,2)
|
||||||
\param[in] dmastate:
|
\param[in] dmastate:
|
||||||
only one parameter can be selected which is shown as below:
|
only one parameter can be selected which is shown as below:
|
||||||
\arg I2C_DMA_ON: DMA mode enable
|
\arg I2C_DMA_ON: enable DMA mode
|
||||||
\arg I2C_DMA_OFF: DMA mode disable
|
\arg I2C_DMA_OFF: disable DMA mode
|
||||||
\param[out] none
|
\param[out] none
|
||||||
\retval none
|
\retval none
|
||||||
*/
|
*/
|
||||||
void i2c_dma_enable(uint32_t i2c_periph, uint32_t dmastate)
|
void i2c_dma_config(uint32_t i2c_periph, uint32_t dmastate)
|
||||||
{
|
{
|
||||||
/* configure I2C DMA function */
|
/* configure I2C DMA function */
|
||||||
uint32_t ctl = 0U;
|
uint32_t ctl = 0U;
|
||||||
|
|
@ -391,14 +395,14 @@ void i2c_dma_last_transfer_config(uint32_t i2c_periph, uint32_t dmalast)
|
||||||
\param[in] i2c_periph: I2Cx(x=0,1,2)
|
\param[in] i2c_periph: I2Cx(x=0,1,2)
|
||||||
\param[in] stretchpara:
|
\param[in] stretchpara:
|
||||||
only one parameter can be selected which is shown as below:
|
only one parameter can be selected which is shown as below:
|
||||||
\arg I2C_SCLSTRETCH_ENABLE: SCL stretching is enabled
|
\arg I2C_SCLSTRETCH_ENABLE: enable SCL stretching
|
||||||
\arg I2C_SCLSTRETCH_DISABLE: SCL stretching is disabled
|
\arg I2C_SCLSTRETCH_DISABLE: disable SCL stretching
|
||||||
\param[out] none
|
\param[out] none
|
||||||
\retval none
|
\retval none
|
||||||
*/
|
*/
|
||||||
void i2c_stretch_scl_low_config(uint32_t i2c_periph, uint32_t stretchpara)
|
void i2c_stretch_scl_low_config(uint32_t i2c_periph, uint32_t stretchpara)
|
||||||
{
|
{
|
||||||
/* configure I2C SCL strerching enable or disable */
|
/* configure I2C SCL strerching */
|
||||||
uint32_t ctl = 0U;
|
uint32_t ctl = 0U;
|
||||||
|
|
||||||
ctl = I2C_CTL0(i2c_periph);
|
ctl = I2C_CTL0(i2c_periph);
|
||||||
|
|
@ -429,7 +433,7 @@ void i2c_slave_response_to_gcall_config(uint32_t i2c_periph, uint32_t gcallpara)
|
||||||
}
|
}
|
||||||
|
|
||||||
/*!
|
/*!
|
||||||
\brief software reset I2C
|
\brief configure software reset of I2C
|
||||||
\param[in] i2c_periph: I2Cx(x=0,1,2)
|
\param[in] i2c_periph: I2Cx(x=0,1,2)
|
||||||
\param[in] sreset:
|
\param[in] sreset:
|
||||||
only one parameter can be selected which is shown as below:
|
only one parameter can be selected which is shown as below:
|
||||||
|
|
@ -450,7 +454,7 @@ void i2c_software_reset_config(uint32_t i2c_periph, uint32_t sreset)
|
||||||
}
|
}
|
||||||
|
|
||||||
/*!
|
/*!
|
||||||
\brief I2C PEC calculation on or off
|
\brief configure I2C PEC calculation
|
||||||
\param[in] i2c_periph: I2Cx(x=0,1,2)
|
\param[in] i2c_periph: I2Cx(x=0,1,2)
|
||||||
\param[in] pecstate:
|
\param[in] pecstate:
|
||||||
only one parameter can be selected which is shown as below:
|
only one parameter can be selected which is shown as below:
|
||||||
|
|
@ -459,7 +463,7 @@ void i2c_software_reset_config(uint32_t i2c_periph, uint32_t sreset)
|
||||||
\param[out] none
|
\param[out] none
|
||||||
\retval none
|
\retval none
|
||||||
*/
|
*/
|
||||||
void i2c_pec_enable(uint32_t i2c_periph, uint32_t pecstate)
|
void i2c_pec_config(uint32_t i2c_periph, uint32_t pecstate)
|
||||||
{
|
{
|
||||||
/* on/off PEC calculation */
|
/* on/off PEC calculation */
|
||||||
uint32_t ctl = 0U;
|
uint32_t ctl = 0U;
|
||||||
|
|
@ -471,16 +475,16 @@ void i2c_pec_enable(uint32_t i2c_periph, uint32_t pecstate)
|
||||||
}
|
}
|
||||||
|
|
||||||
/*!
|
/*!
|
||||||
\brief I2C whether to transfer PEC value
|
\brief configure whether to transfer PEC value
|
||||||
\param[in] i2c_periph: I2Cx(x=0,1,2)
|
\param[in] i2c_periph: I2Cx(x=0,1,2)
|
||||||
\param[in] pecpara:
|
\param[in] pecpara:
|
||||||
only one parameter can be selected which is shown as below:
|
only one parameter can be selected which is shown as below:
|
||||||
\arg I2C_PECTRANS_ENABLE: transfer PEC
|
\arg I2C_PECTRANS_ENABLE: transfer PEC value
|
||||||
\arg I2C_PECTRANS_DISABLE: not transfer PEC
|
\arg I2C_PECTRANS_DISABLE: not transfer PEC value
|
||||||
\param[out] none
|
\param[out] none
|
||||||
\retval none
|
\retval none
|
||||||
*/
|
*/
|
||||||
void i2c_pec_transfer_enable(uint32_t i2c_periph, uint32_t pecpara)
|
void i2c_pec_transfer_config(uint32_t i2c_periph, uint32_t pecpara)
|
||||||
{
|
{
|
||||||
/* whether to transfer PEC */
|
/* whether to transfer PEC */
|
||||||
uint32_t ctl = 0U;
|
uint32_t ctl = 0U;
|
||||||
|
|
@ -503,7 +507,7 @@ uint8_t i2c_pec_value_get(uint32_t i2c_periph)
|
||||||
}
|
}
|
||||||
|
|
||||||
/*!
|
/*!
|
||||||
\brief I2C issue alert through SMBA pin
|
\brief configure I2C alert through SMBA pin
|
||||||
\param[in] i2c_periph: I2Cx(x=0,1,2)
|
\param[in] i2c_periph: I2Cx(x=0,1,2)
|
||||||
\param[in] smbuspara:
|
\param[in] smbuspara:
|
||||||
only one parameter can be selected which is shown as below:
|
only one parameter can be selected which is shown as below:
|
||||||
|
|
@ -512,9 +516,9 @@ uint8_t i2c_pec_value_get(uint32_t i2c_periph)
|
||||||
\param[out] none
|
\param[out] none
|
||||||
\retval none
|
\retval none
|
||||||
*/
|
*/
|
||||||
void i2c_smbus_issue_alert(uint32_t i2c_periph, uint32_t smbuspara)
|
void i2c_smbus_alert_config(uint32_t i2c_periph, uint32_t smbuspara)
|
||||||
{
|
{
|
||||||
/* issue alert through SMBA pin configure*/
|
/* configure smubus alert through SMBA pin */
|
||||||
uint32_t ctl = 0U;
|
uint32_t ctl = 0U;
|
||||||
|
|
||||||
ctl = I2C_CTL0(i2c_periph);
|
ctl = I2C_CTL0(i2c_periph);
|
||||||
|
|
@ -524,7 +528,7 @@ void i2c_smbus_issue_alert(uint32_t i2c_periph, uint32_t smbuspara)
|
||||||
}
|
}
|
||||||
|
|
||||||
/*!
|
/*!
|
||||||
\brief enable or disable I2C ARP protocol in SMBus switch
|
\brief configure I2C ARP protocol in SMBus
|
||||||
\param[in] i2c_periph: I2Cx(x=0,1,2)
|
\param[in] i2c_periph: I2Cx(x=0,1,2)
|
||||||
\param[in] arpstate:
|
\param[in] arpstate:
|
||||||
only one parameter can be selected which is shown as below:
|
only one parameter can be selected which is shown as below:
|
||||||
|
|
@ -533,7 +537,7 @@ void i2c_smbus_issue_alert(uint32_t i2c_periph, uint32_t smbuspara)
|
||||||
\param[out] none
|
\param[out] none
|
||||||
\retval none
|
\retval none
|
||||||
*/
|
*/
|
||||||
void i2c_smbus_arp_enable(uint32_t i2c_periph, uint32_t arpstate)
|
void i2c_smbus_arp_config(uint32_t i2c_periph, uint32_t arpstate)
|
||||||
{
|
{
|
||||||
/* enable or disable I2C ARP protocol*/
|
/* enable or disable I2C ARP protocol*/
|
||||||
uint32_t ctl = 0U;
|
uint32_t ctl = 0U;
|
||||||
|
|
@ -545,7 +549,7 @@ void i2c_smbus_arp_enable(uint32_t i2c_periph, uint32_t arpstate)
|
||||||
}
|
}
|
||||||
|
|
||||||
/*!
|
/*!
|
||||||
\brief analog noise filter disable
|
\brief disable analog noise filter
|
||||||
\param[in] i2c_periph: I2Cx(x=0,1,2)
|
\param[in] i2c_periph: I2Cx(x=0,1,2)
|
||||||
\param[out] none
|
\param[out] none
|
||||||
\retval none
|
\retval none
|
||||||
|
|
@ -556,7 +560,7 @@ void i2c_analog_noise_filter_disable(uint32_t i2c_periph)
|
||||||
}
|
}
|
||||||
|
|
||||||
/*!
|
/*!
|
||||||
\brief analog noise filter enable
|
\brief enable analog noise filter
|
||||||
\param[in] i2c_periph: I2Cx(x=0,1,2)
|
\param[in] i2c_periph: I2Cx(x=0,1,2)
|
||||||
\param[out] none
|
\param[out] none
|
||||||
\retval none
|
\retval none
|
||||||
|
|
@ -567,9 +571,26 @@ void i2c_analog_noise_filter_enable(uint32_t i2c_periph)
|
||||||
}
|
}
|
||||||
|
|
||||||
/*!
|
/*!
|
||||||
\brief digital noise filter configuration
|
\brief configure digital noise filter
|
||||||
\param[in] i2c_periph: I2Cx(x=0,1,2)
|
\param[in] i2c_periph: I2Cx(x=0,1,2)
|
||||||
\param[in] dfilterpara: refer to enum i2c_digital_filter_enum
|
\param[in] dfilterpara: refer to i2c_digital_filter_enum
|
||||||
|
only one parameter can be selected which is shown as below:
|
||||||
|
\arg I2C_DF_DISABLE: disable digital noise filter
|
||||||
|
\arg I2C_DF_1PCLK: enable digital noise filter and the maximum filtered spiker's length 1 PCLK1
|
||||||
|
\arg I2C_DF_2PCLK: enable digital noise filter and the maximum filtered spiker's length 2 PCLK1
|
||||||
|
\arg I2C_DF_3PCLK: enable digital noise filter and the maximum filtered spiker's length 3 PCLK1
|
||||||
|
\arg I2C_DF_4PCLK: enable digital noise filter and the maximum filtered spiker's length 4 PCLK1
|
||||||
|
\arg I2C_DF_5PCLK: enable digital noise filter and the maximum filtered spiker's length 5 PCLK1
|
||||||
|
\arg I2C_DF_6PCLK: enable digital noise filter and the maximum filtered spiker's length 6 PCLK1
|
||||||
|
\arg I2C_DF_7PCLK: enable digital noise filter and the maximum filtered spiker's length 7 PCLK1
|
||||||
|
\arg I2C_DF_8PCLK: enable digital noise filter and the maximum filtered spiker's length 8 PCLK1
|
||||||
|
\arg I2C_DF_9PCLK: enable digital noise filter and the maximum filtered spiker's length 9 PCLK1
|
||||||
|
\arg I2C_DF_10PCLK: enable digital noise filter and the maximum filtered spiker's length 10 PCLK1
|
||||||
|
\arg I2C_DF_11CLK: enable digital noise filter and the maximum filtered spiker's length 11 PCLK1
|
||||||
|
\arg I2C_DF_12CLK: enable digital noise filter and the maximum filtered spiker's length 12 PCLK1
|
||||||
|
\arg I2C_DF_13PCLK: enable digital noise filter and the maximum filtered spiker's length 13 PCLK1
|
||||||
|
\arg I2C_DF_14PCLK: enable digital noise filter and the maximum filtered spiker's length 14 PCLK1
|
||||||
|
\arg I2C_DF_15PCLK: enable digital noise filter and the maximum filtered spiker's length 15 PCLK1
|
||||||
\param[out] none
|
\param[out] none
|
||||||
\retval none
|
\retval none
|
||||||
*/
|
*/
|
||||||
|
|
@ -623,27 +644,27 @@ void i2c_sam_timeout_disable(uint32_t i2c_periph)
|
||||||
}
|
}
|
||||||
|
|
||||||
/*!
|
/*!
|
||||||
\brief check I2C flag is set or not
|
\brief get I2C flag status
|
||||||
\param[in] i2c_periph: I2Cx(x=0,1,2)
|
\param[in] i2c_periph: I2Cx(x=0,1,2)
|
||||||
\param[in] flag: I2C flags, refer to i2c_flag_enum
|
\param[in] flag: I2C flags, refer to i2c_flag_enum
|
||||||
only one parameter can be selected which is shown as below:
|
only one parameter can be selected which is shown as below:
|
||||||
\arg I2C_FLAG_SBSEND: start condition send out
|
\arg I2C_FLAG_SBSEND: start condition sent out in master mode
|
||||||
\arg I2C_FLAG_ADDSEND: address is sent in master mode or received and matches in slave mode
|
\arg I2C_FLAG_ADDSEND: address is sent in master mode or received and matches in slave mode
|
||||||
\arg I2C_FLAG_BTC: byte transmission finishes
|
\arg I2C_FLAG_BTC: byte transmission finishes
|
||||||
\arg I2C_FLAG_ADD10SEND: header of 10-bit address is sent in master mode
|
\arg I2C_FLAG_ADD10SEND: header of 10-bit address is sent in master mode
|
||||||
\arg I2C_FLAG_STPDET: stop condition detected in slave mode
|
\arg I2C_FLAG_STPDET: stop condition detected in slave mode
|
||||||
\arg I2C_FLAG_RBNE: I2C_DATA is not Empty during receiving
|
\arg I2C_FLAG_RBNE: I2C_DATA is not empty during receiving
|
||||||
\arg I2C_FLAG_TBE: I2C_DATA is empty during transmitting
|
\arg I2C_FLAG_TBE: I2C_DATA is empty during transmitting
|
||||||
\arg I2C_FLAG_BERR: a bus error occurs indication a unexpected start or stop condition on I2C bus
|
\arg I2C_FLAG_BERR: a bus error occurs indication a unexpected start or stop condition on I2C bus
|
||||||
\arg I2C_FLAG_LOSTARB: arbitration lost in master mode
|
\arg I2C_FLAG_LOSTARB: arbitration lost in master mode
|
||||||
\arg I2C_FLAG_AERR: acknowledge error
|
\arg I2C_FLAG_AERR: acknowledge error
|
||||||
\arg I2C_FLAG_OUERR: overrun or underrun situation occurs in slave mode
|
\arg I2C_FLAG_OUERR: over-run or under-run situation occurs in slave mode
|
||||||
\arg I2C_FLAG_PECERR: PEC error when receiving data
|
\arg I2C_FLAG_PECERR: PEC error when receiving data
|
||||||
\arg I2C_FLAG_SMBTO: timeout signal in SMBus mode
|
\arg I2C_FLAG_SMBTO: timeout signal in SMBus mode
|
||||||
\arg I2C_FLAG_SMBALT: SMBus alert status
|
\arg I2C_FLAG_SMBALT: SMBus alert status
|
||||||
\arg I2C_FLAG_MASTER: a flag indicating whether I2C block is in master or slave mode
|
\arg I2C_FLAG_MASTER: a flag indicating whether I2C block is in master or slave mode
|
||||||
\arg I2C_FLAG_I2CBSY: busy flag
|
\arg I2C_FLAG_I2CBSY: busy flag
|
||||||
\arg I2C_FLAG_TRS: whether the I2C is a transmitter or a receiver
|
\arg I2C_FLAG_TR: whether the I2C is a transmitter or a receiver
|
||||||
\arg I2C_FLAG_RXGC: general call address (00h) received
|
\arg I2C_FLAG_RXGC: general call address (00h) received
|
||||||
\arg I2C_FLAG_DEFSMB: default address of SMBus device
|
\arg I2C_FLAG_DEFSMB: default address of SMBus device
|
||||||
\arg I2C_FLAG_HSTSMB: SMBus host header detected in slave mode
|
\arg I2C_FLAG_HSTSMB: SMBus host header detected in slave mode
|
||||||
|
|
@ -665,18 +686,18 @@ FlagStatus i2c_flag_get(uint32_t i2c_periph, i2c_flag_enum flag)
|
||||||
}
|
}
|
||||||
|
|
||||||
/*!
|
/*!
|
||||||
\brief clear I2C flag
|
\brief clear I2C flag status
|
||||||
\param[in] i2c_periph: I2Cx(x=0,1,2)
|
\param[in] i2c_periph: I2Cx(x=0,1,2)
|
||||||
\param[in] flag: I2C flags, refer to i2c_flag_enum
|
\param[in] flag: I2C flags, refer to i2c_flag_enum
|
||||||
only one parameter can be selected which is shown as below:
|
only one parameter can be selected which is shown as below:
|
||||||
\arg I2C_FLAG_SMBALT: SMBus Alert status
|
\arg I2C_FLAG_SMBALT: SMBus alert status
|
||||||
\arg I2C_FLAG_SMBTO: timeout signal in SMBus mode
|
\arg I2C_FLAG_SMBTO: timeout signal in SMBus mode
|
||||||
\arg I2C_FLAG_PECERR: PEC error when receiving data
|
\arg I2C_FLAG_PECERR: PEC error when receiving data
|
||||||
\arg I2C_FLAG_OUERR: over-run or under-run situation occurs in slave mode
|
\arg I2C_FLAG_OUERR: over-run or under-run situation occurs in slave mode
|
||||||
\arg I2C_FLAG_AERR: acknowledge error
|
\arg I2C_FLAG_AERR: acknowledge error
|
||||||
\arg I2C_FLAG_LOSTARB: arbitration lost in master mode
|
\arg I2C_FLAG_LOSTARB: arbitration lost in master mode
|
||||||
\arg I2C_FLAG_BERR: a bus error
|
\arg I2C_FLAG_BERR: a bus error occurs indication a unexpected start or stop condition on I2C bus
|
||||||
\arg I2C_FLAG_ADDSEND: cleared by reading I2C_STAT0 and reading I2C_STAT1
|
\arg I2C_FLAG_ADDSEND: address is sent in master mode or received and matches in slave mode
|
||||||
\arg I2C_FLAG_TFF: txframe fall flag
|
\arg I2C_FLAG_TFF: txframe fall flag
|
||||||
\arg I2C_FLAG_TFR: txframe rise flag
|
\arg I2C_FLAG_TFR: txframe rise flag
|
||||||
\arg I2C_FLAG_RFF: rxframe fall flag
|
\arg I2C_FLAG_RFF: rxframe fall flag
|
||||||
|
|
@ -700,13 +721,13 @@ void i2c_flag_clear(uint32_t i2c_periph, i2c_flag_enum flag)
|
||||||
\param[in] i2c_periph: I2Cx(x=0,1,2)
|
\param[in] i2c_periph: I2Cx(x=0,1,2)
|
||||||
\param[in] interrupt: I2C interrupts, refer to i2c_interrupt_enum
|
\param[in] interrupt: I2C interrupts, refer to i2c_interrupt_enum
|
||||||
only one parameter can be selected which is shown as below:
|
only one parameter can be selected which is shown as below:
|
||||||
\arg I2C_INT_ERR: error interrupt enable
|
\arg I2C_INT_ERR: error interrupt
|
||||||
\arg I2C_INT_EV: event interrupt enable
|
\arg I2C_INT_EV: event interrupt
|
||||||
\arg I2C_INT_BUF: buffer interrupt enable
|
\arg I2C_INT_BUF: buffer interrupt
|
||||||
\arg I2C_INT_TFF: txframe fall interrupt enable
|
\arg I2C_INT_TFF: txframe fall interrupt
|
||||||
\arg I2C_INT_TFR: txframe rise interrupt enable
|
\arg I2C_INT_TFR: txframe rise interrupt
|
||||||
\arg I2C_INT_RFF: rxframe fall interrupt enable
|
\arg I2C_INT_RFF: rxframe fall interrupt
|
||||||
\arg I2C_INT_RFR: rxframe rise interrupt enable
|
\arg I2C_INT_RFR: rxframe rise interrupt
|
||||||
\param[out] none
|
\param[out] none
|
||||||
\retval none
|
\retval none
|
||||||
*/
|
*/
|
||||||
|
|
@ -718,15 +739,15 @@ void i2c_interrupt_enable(uint32_t i2c_periph, i2c_interrupt_enum interrupt)
|
||||||
/*!
|
/*!
|
||||||
\brief disable I2C interrupt
|
\brief disable I2C interrupt
|
||||||
\param[in] i2c_periph: I2Cx(x=0,1,2)
|
\param[in] i2c_periph: I2Cx(x=0,1,2)
|
||||||
\param[in] interrupt: I2C interrupts, refer to i2c_flag_enum
|
\param[in] interrupt: I2C interrupts, refer to i2c_interrupt_enum
|
||||||
only one parameter can be selected which is shown as below:
|
only one parameter can be selected which is shown as below:
|
||||||
\arg I2C_INT_ERR: error interrupt enable
|
\arg I2C_INT_ERR: error interrupt
|
||||||
\arg I2C_INT_EV: event interrupt enable
|
\arg I2C_INT_EV: event interrupt
|
||||||
\arg I2C_INT_BUF: buffer interrupt enable
|
\arg I2C_INT_BUF: buffer interrupt
|
||||||
\arg I2C_INT_TFF: txframe fall interrupt enable
|
\arg I2C_INT_TFF: txframe fall interrupt
|
||||||
\arg I2C_INT_TFR: txframe rise interrupt enable
|
\arg I2C_INT_TFR: txframe rise interrupt
|
||||||
\arg I2C_INT_RFF: rxframe fall interrupt enable
|
\arg I2C_INT_RFF: rxframe fall interrupt
|
||||||
\arg I2C_INT_RFR: rxframe rise interrupt enable
|
\arg I2C_INT_RFR: rxframe rise interrupt
|
||||||
\param[out] none
|
\param[out] none
|
||||||
\retval none
|
\retval none
|
||||||
*/
|
*/
|
||||||
|
|
@ -736,15 +757,15 @@ void i2c_interrupt_disable(uint32_t i2c_periph, i2c_interrupt_enum interrupt)
|
||||||
}
|
}
|
||||||
|
|
||||||
/*!
|
/*!
|
||||||
\brief check I2C interrupt flag
|
\brief get I2C interrupt flag status
|
||||||
\param[in] i2c_periph: I2Cx(x=0,1,2)
|
\param[in] i2c_periph: I2Cx(x=0,1,2)
|
||||||
\param[in] int_flag: I2C interrupt flags, refer to i2c_interrupt_flag_enum
|
\param[in] int_flag: I2C interrupt flags, refer to i2c_interrupt_flag_enum
|
||||||
only one parameter can be selected which is shown as below:
|
only one parameter can be selected which is shown as below:
|
||||||
\arg I2C_INT_FLAG_SBSEND: start condition sent out in master mode interrupt flag
|
\arg I2C_INT_FLAG_SBSEND: start condition sent out in master mode interrupt flag
|
||||||
\arg I2C_INT_FLAG_ADDSEND: address is sent in master mode or received and matches in slave mode interrupt flag
|
\arg I2C_INT_FLAG_ADDSEND: address is sent in master mode or received and matches in slave mode interrupt flag
|
||||||
\arg I2C_INT_FLAG_BTC: byte transmission finishes
|
\arg I2C_INT_FLAG_BTC: byte transmission finishes interrupt flag
|
||||||
\arg I2C_INT_FLAG_ADD10SEND: header of 10-bit address is sent in master mode interrupt flag
|
\arg I2C_INT_FLAG_ADD10SEND: header of 10-bit address is sent in master mode interrupt flag
|
||||||
\arg I2C_INT_FLAG_STPDET: etop condition detected in slave mode interrupt flag
|
\arg I2C_INT_FLAG_STPDET: stop condition detected in slave mode interrupt flag
|
||||||
\arg I2C_INT_FLAG_RBNE: I2C_DATA is not Empty during receiving interrupt flag
|
\arg I2C_INT_FLAG_RBNE: I2C_DATA is not Empty during receiving interrupt flag
|
||||||
\arg I2C_INT_FLAG_TBE: I2C_DATA is empty during transmitting interrupt flag
|
\arg I2C_INT_FLAG_TBE: I2C_DATA is empty during transmitting interrupt flag
|
||||||
\arg I2C_INT_FLAG_BERR: a bus error occurs indication a unexpected start or stop condition on I2C bus interrupt flag
|
\arg I2C_INT_FLAG_BERR: a bus error occurs indication a unexpected start or stop condition on I2C bus interrupt flag
|
||||||
|
|
@ -753,7 +774,7 @@ void i2c_interrupt_disable(uint32_t i2c_periph, i2c_interrupt_enum interrupt)
|
||||||
\arg I2C_INT_FLAG_OUERR: over-run or under-run situation occurs in slave mode interrupt flag
|
\arg I2C_INT_FLAG_OUERR: over-run or under-run situation occurs in slave mode interrupt flag
|
||||||
\arg I2C_INT_FLAG_PECERR: PEC error when receiving data interrupt flag
|
\arg I2C_INT_FLAG_PECERR: PEC error when receiving data interrupt flag
|
||||||
\arg I2C_INT_FLAG_SMBTO: timeout signal in SMBus mode interrupt flag
|
\arg I2C_INT_FLAG_SMBTO: timeout signal in SMBus mode interrupt flag
|
||||||
\arg I2C_INT_FLAG_SMBALT: SMBus Alert status interrupt flag
|
\arg I2C_INT_FLAG_SMBALT: SMBus alert status interrupt flag
|
||||||
\arg I2C_INT_FLAG_TFF: txframe fall interrupt flag
|
\arg I2C_INT_FLAG_TFF: txframe fall interrupt flag
|
||||||
\arg I2C_INT_FLAG_TFR: txframe rise interrupt flag
|
\arg I2C_INT_FLAG_TFR: txframe rise interrupt flag
|
||||||
\arg I2C_INT_FLAG_RFF: rxframe fall interrupt flag
|
\arg I2C_INT_FLAG_RFF: rxframe fall interrupt flag
|
||||||
|
|
@ -788,7 +809,7 @@ FlagStatus i2c_interrupt_flag_get(uint32_t i2c_periph, i2c_interrupt_flag_enum i
|
||||||
}
|
}
|
||||||
|
|
||||||
/*!
|
/*!
|
||||||
\brief clear I2C interrupt flag
|
\brief clear I2C interrupt flag status
|
||||||
\param[in] i2c_periph: I2Cx(x=0,1,2)
|
\param[in] i2c_periph: I2Cx(x=0,1,2)
|
||||||
\param[in] int_flag: I2C interrupt flags, refer to i2c_interrupt_flag_enum
|
\param[in] int_flag: I2C interrupt flags, refer to i2c_interrupt_flag_enum
|
||||||
only one parameter can be selected which is shown as below:
|
only one parameter can be selected which is shown as below:
|
||||||
|
|
@ -799,7 +820,7 @@ FlagStatus i2c_interrupt_flag_get(uint32_t i2c_periph, i2c_interrupt_flag_enum i
|
||||||
\arg I2C_INT_FLAG_OUERR: over-run or under-run situation occurs in slave mode interrupt flag
|
\arg I2C_INT_FLAG_OUERR: over-run or under-run situation occurs in slave mode interrupt flag
|
||||||
\arg I2C_INT_FLAG_PECERR: PEC error when receiving data interrupt flag
|
\arg I2C_INT_FLAG_PECERR: PEC error when receiving data interrupt flag
|
||||||
\arg I2C_INT_FLAG_SMBTO: timeout signal in SMBus mode interrupt flag
|
\arg I2C_INT_FLAG_SMBTO: timeout signal in SMBus mode interrupt flag
|
||||||
\arg I2C_INT_FLAG_SMBALT: SMBus Alert status interrupt flag
|
\arg I2C_INT_FLAG_SMBALT: SMBus alert status interrupt flag
|
||||||
\arg I2C_INT_FLAG_TFF: txframe fall interrupt flag
|
\arg I2C_INT_FLAG_TFF: txframe fall interrupt flag
|
||||||
\arg I2C_INT_FLAG_TFR: txframe rise interrupt flag
|
\arg I2C_INT_FLAG_TFR: txframe rise interrupt flag
|
||||||
\arg I2C_INT_FLAG_RFF: rxframe fall interrupt flag
|
\arg I2C_INT_FLAG_RFF: rxframe fall interrupt flag
|
||||||
|
|
|
||||||
|
|
@ -5,10 +5,11 @@
|
||||||
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
||||||
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
||||||
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
||||||
|
\version 2022-03-09, V3.0.0, firmware for GD32F4xx
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/*
|
/*
|
||||||
Copyright (c) 2020, GigaDevice Semiconductor Inc.
|
Copyright (c) 2022, GigaDevice Semiconductor Inc.
|
||||||
|
|
||||||
Redistribution and use in source and binary forms, with or without modification,
|
Redistribution and use in source and binary forms, with or without modification,
|
||||||
are permitted provided that the following conditions are met:
|
are permitted provided that the following conditions are met:
|
||||||
|
|
@ -139,6 +140,7 @@ void ipa_background_lut_loading_enable(void)
|
||||||
*/
|
*/
|
||||||
void ipa_pixel_format_convert_mode_set(uint32_t pfcm)
|
void ipa_pixel_format_convert_mode_set(uint32_t pfcm)
|
||||||
{
|
{
|
||||||
|
IPA_CTL &= ~(IPA_CTL_PFCM);
|
||||||
IPA_CTL |= pfcm;
|
IPA_CTL |= pfcm;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -5,10 +5,11 @@
|
||||||
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
||||||
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
||||||
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
||||||
|
\version 2022-03-09, V3.0.0, firmware for GD32F4xx
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/*
|
/*
|
||||||
Copyright (c) 2020, GigaDevice Semiconductor Inc.
|
Copyright (c) 2022, GigaDevice Semiconductor Inc.
|
||||||
|
|
||||||
Redistribution and use in source and binary forms, with or without modification,
|
Redistribution and use in source and binary forms, with or without modification,
|
||||||
are permitted provided that the following conditions are met:
|
are permitted provided that the following conditions are met:
|
||||||
|
|
@ -37,7 +38,7 @@ OF SUCH DAMAGE.
|
||||||
#include "gd32f4xx_iref.h"
|
#include "gd32f4xx_iref.h"
|
||||||
|
|
||||||
/*!
|
/*!
|
||||||
\brief deinit IREF
|
\brief deinitialize IREF
|
||||||
\param[in] none
|
\param[in] none
|
||||||
\param[out] none
|
\param[out] none
|
||||||
\retval none
|
\retval none
|
||||||
|
|
|
||||||
|
|
@ -1,14 +1,14 @@
|
||||||
/*!
|
/*!
|
||||||
\file gd32f4xx_misc.c
|
\file gd32f4xx_misc.c
|
||||||
\brief MISC driver
|
\brief MISC driver
|
||||||
|
|
||||||
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
||||||
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
||||||
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
||||||
|
\version 2022-03-09, V3.0.0, firmware for GD32F4xx
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/*
|
/*
|
||||||
Copyright (c) 2020, GigaDevice Semiconductor Inc.
|
Copyright (c) 2022, GigaDevice Semiconductor Inc.
|
||||||
|
|
||||||
Redistribution and use in source and binary forms, with or without modification,
|
Redistribution and use in source and binary forms, with or without modification,
|
||||||
are permitted provided that the following conditions are met:
|
are permitted provided that the following conditions are met:
|
||||||
|
|
@ -119,6 +119,7 @@ void nvic_irq_disable(uint8_t nvic_irq)
|
||||||
void nvic_vector_table_set(uint32_t nvic_vict_tab, uint32_t offset)
|
void nvic_vector_table_set(uint32_t nvic_vict_tab, uint32_t offset)
|
||||||
{
|
{
|
||||||
SCB->VTOR = nvic_vict_tab | (offset & NVIC_VECTTAB_OFFSET_MASK);
|
SCB->VTOR = nvic_vict_tab | (offset & NVIC_VECTTAB_OFFSET_MASK);
|
||||||
|
__DSB();
|
||||||
}
|
}
|
||||||
|
|
||||||
/*!
|
/*!
|
||||||
|
|
|
||||||
|
|
@ -5,10 +5,11 @@
|
||||||
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
||||||
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
||||||
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
||||||
|
\version 2022-03-09, V3.0.0, firmware for GD32F4xx
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/*
|
/*
|
||||||
Copyright (c) 2020, GigaDevice Semiconductor Inc.
|
Copyright (c) 2022, GigaDevice Semiconductor Inc.
|
||||||
|
|
||||||
Redistribution and use in source and binary forms, with or without modification,
|
Redistribution and use in source and binary forms, with or without modification,
|
||||||
are permitted provided that the following conditions are met:
|
are permitted provided that the following conditions are met:
|
||||||
|
|
@ -36,8 +37,9 @@ OF SUCH DAMAGE.
|
||||||
|
|
||||||
#include "gd32f4xx_pmu.h"
|
#include "gd32f4xx_pmu.h"
|
||||||
#include "core_cm4.h"
|
#include "core_cm4.h"
|
||||||
|
|
||||||
/*!
|
/*!
|
||||||
\brief reset PMU register
|
\brief reset PMU registers
|
||||||
\param[in] none
|
\param[in] none
|
||||||
\param[out] none
|
\param[out] none
|
||||||
\retval none
|
\retval none
|
||||||
|
|
@ -75,6 +77,18 @@ void pmu_lvd_select(uint32_t lvdt_n)
|
||||||
PMU_CTL |= PMU_CTL_LVDEN;
|
PMU_CTL |= PMU_CTL_LVDEN;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief disable PMU lvd
|
||||||
|
\param[in] none
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void pmu_lvd_disable(void)
|
||||||
|
{
|
||||||
|
/* disable LVD */
|
||||||
|
PMU_CTL &= ~PMU_CTL_LVDEN;
|
||||||
|
}
|
||||||
|
|
||||||
/*!
|
/*!
|
||||||
\brief select LDO output voltage
|
\brief select LDO output voltage
|
||||||
this bit set by software when the main PLL closed, before closing PLL, change the system clock to IRC16M or HXTAL
|
this bit set by software when the main PLL closed, before closing PLL, change the system clock to IRC16M or HXTAL
|
||||||
|
|
@ -91,38 +105,6 @@ void pmu_ldo_output_select(uint32_t ldo_output)
|
||||||
PMU_CTL |= ldo_output;
|
PMU_CTL |= ldo_output;
|
||||||
}
|
}
|
||||||
|
|
||||||
/*!
|
|
||||||
\brief enable low-driver mode in deep-sleep mode
|
|
||||||
\param[in] lowdr_mode:
|
|
||||||
\arg PMU_LOWDRIVER_ENABLE: enable low-driver mode in deep-sleep mode
|
|
||||||
\arg PMU_LOWDRIVER_DISABLE: disable low-driver mode in deep-sleep mode
|
|
||||||
\param[out] none
|
|
||||||
\retval none
|
|
||||||
*/
|
|
||||||
void pmu_low_driver_mode_enable(uint32_t lowdr_mode)
|
|
||||||
{
|
|
||||||
PMU_CTL &= ~PMU_CTL_LDEN;
|
|
||||||
PMU_CTL |= lowdr_mode;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
\brief switch high-driver mode
|
|
||||||
this bit set by software only when IRC16M or HXTAL used as system clock
|
|
||||||
\param[in] highdr_switch:
|
|
||||||
\arg PMU_HIGHDR_SWITCH_NONE: disable high-driver mode switch
|
|
||||||
\arg PMU_HIGHDR_SWITCH_EN: enable high-driver mode switch
|
|
||||||
\param[out] none
|
|
||||||
\retval none
|
|
||||||
*/
|
|
||||||
void pmu_highdriver_switch_select(uint32_t highdr_switch)
|
|
||||||
{
|
|
||||||
/* wait for HDRF flag set */
|
|
||||||
while(SET != pmu_flag_get(PMU_FLAG_HDRF)){
|
|
||||||
}
|
|
||||||
PMU_CTL &= ~PMU_CTL_HDS;
|
|
||||||
PMU_CTL |= highdr_switch;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
/*!
|
||||||
\brief enable high-driver mode
|
\brief enable high-driver mode
|
||||||
this bit set by software only when IRC16M or HXTAL used as system clock
|
this bit set by software only when IRC16M or HXTAL used as system clock
|
||||||
|
|
@ -147,47 +129,75 @@ void pmu_highdriver_mode_disable(void)
|
||||||
}
|
}
|
||||||
|
|
||||||
/*!
|
/*!
|
||||||
\brief disable PMU lvd
|
\brief switch high-driver mode
|
||||||
|
this bit set by software only when IRC16M or HXTAL used as system clock
|
||||||
|
\param[in] highdr_switch:
|
||||||
|
\arg PMU_HIGHDR_SWITCH_NONE: disable high-driver mode switch
|
||||||
|
\arg PMU_HIGHDR_SWITCH_EN: enable high-driver mode switch
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void pmu_highdriver_switch_select(uint32_t highdr_switch)
|
||||||
|
{
|
||||||
|
/* wait for HDRF flag set */
|
||||||
|
while(SET != pmu_flag_get(PMU_FLAG_HDRF)) {
|
||||||
|
}
|
||||||
|
PMU_CTL &= ~PMU_CTL_HDS;
|
||||||
|
PMU_CTL |= highdr_switch;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief enable low-driver mode in deep-sleep
|
||||||
\param[in] none
|
\param[in] none
|
||||||
\param[out] none
|
\param[out] none
|
||||||
\retval none
|
\retval none
|
||||||
*/
|
*/
|
||||||
void pmu_lvd_disable(void)
|
void pmu_lowdriver_mode_enable(void)
|
||||||
{
|
{
|
||||||
/* disable LVD */
|
PMU_CTL |= PMU_CTL_LDEN;
|
||||||
PMU_CTL &= ~PMU_CTL_LVDEN;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
/*!
|
/*!
|
||||||
\brief low-driver mode when use low power LDO
|
\brief disable low-driver mode in deep-sleep
|
||||||
|
\param[in] none
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void pmu_lowdriver_mode_disable(void)
|
||||||
|
{
|
||||||
|
PMU_CTL &= ~PMU_CTL_LDEN;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief in deep-sleep mode, driver mode when use low power LDO
|
||||||
\param[in] mode:
|
\param[in] mode:
|
||||||
\arg PMU_NORMALDR_LOWPWR: normal driver when use low power LDO
|
\arg PMU_NORMALDR_LOWPWR: normal driver when use low power LDO
|
||||||
\arg PMU_LOWDR_LOWPWR: low-driver mode enabled when LDEN is 11 and use low power LDO
|
\arg PMU_LOWDR_LOWPWR: low-driver mode enabled when LDEN is 11 and use low power LDO
|
||||||
\param[out] none
|
\param[out] none
|
||||||
\retval none
|
\retval none
|
||||||
*/
|
*/
|
||||||
void pmu_lowdriver_lowpower_config(uint32_t mode)
|
void pmu_lowpower_driver_config(uint32_t mode)
|
||||||
{
|
{
|
||||||
PMU_CTL &= ~PMU_CTL_LDLP;
|
PMU_CTL &= ~PMU_CTL_LDLP;
|
||||||
PMU_CTL |= mode;
|
PMU_CTL |= mode;
|
||||||
}
|
}
|
||||||
|
|
||||||
/*!
|
/*!
|
||||||
\brief low-driver mode when use normal power LDO
|
\brief in deep-sleep mode, driver mode when use normal power LDO
|
||||||
\param[in] mode:
|
\param[in] mode:
|
||||||
\arg PMU_NORMALDR_NORMALPWR: normal driver when use normal power LDO
|
\arg PMU_NORMALDR_NORMALPWR: normal driver when use normal power LDO
|
||||||
\arg PMU_LOWDR_NORMALPWR: low-driver mode enabled when LDEN is 11 and use normal power LDO
|
\arg PMU_LOWDR_NORMALPWR: low-driver mode enabled when LDEN is 11 and use normal power LDO
|
||||||
\param[out] none
|
\param[out] none
|
||||||
\retval none
|
\retval none
|
||||||
*/
|
*/
|
||||||
void pmu_lowdriver_normalpower_config(uint32_t mode)
|
void pmu_normalpower_driver_config(uint32_t mode)
|
||||||
{
|
{
|
||||||
PMU_CTL &= ~PMU_CTL_LDNP;
|
PMU_CTL &= ~PMU_CTL_LDNP;
|
||||||
PMU_CTL |= mode;
|
PMU_CTL |= mode;
|
||||||
}
|
}
|
||||||
|
|
||||||
/*!
|
/*!
|
||||||
\brief PMU work at sleep mode
|
\brief PMU work in sleep mode
|
||||||
\param[in] sleepmodecmd:
|
\param[in] sleepmodecmd:
|
||||||
\arg WFI_CMD: use WFI command
|
\arg WFI_CMD: use WFI command
|
||||||
\arg WFE_CMD: use WFE command
|
\arg WFE_CMD: use WFE command
|
||||||
|
|
@ -208,25 +218,37 @@ void pmu_to_sleepmode(uint8_t sleepmodecmd)
|
||||||
}
|
}
|
||||||
|
|
||||||
/*!
|
/*!
|
||||||
\brief PMU work at deepsleep mode
|
\brief PMU work in deep-sleep mode
|
||||||
\param[in] ldo
|
\param[in] ldo
|
||||||
\arg PMU_LDO_NORMAL: LDO normal work when pmu enter deepsleep mode
|
\arg PMU_LDO_NORMAL: LDO normal work when pmu enter deep-sleep mode
|
||||||
\arg PMU_LDO_LOWPOWER: LDO work at low power mode when pmu enter deepsleep mode
|
\arg PMU_LDO_LOWPOWER: LDO work at low power mode when pmu enter deep-sleep mode
|
||||||
|
\param[in] lowdrive:
|
||||||
|
only one parameter can be selected which is shown as below:
|
||||||
|
\arg PMU_LOWDRIVER_DISABLE: Low-driver mode disable in deep-sleep mode
|
||||||
|
\arg PMU_LOWDRIVER_ENABLE: Low-driver mode enable in deep-sleep mode
|
||||||
\param[in] deepsleepmodecmd:
|
\param[in] deepsleepmodecmd:
|
||||||
\arg WFI_CMD: use WFI command
|
\arg WFI_CMD: use WFI command
|
||||||
\arg WFE_CMD: use WFE command
|
\arg WFE_CMD: use WFE command
|
||||||
\param[out] none
|
\param[out] none
|
||||||
\retval none
|
\retval none
|
||||||
*/
|
*/
|
||||||
void pmu_to_deepsleepmode(uint32_t ldo,uint8_t deepsleepmodecmd)
|
void pmu_to_deepsleepmode(uint32_t ldo, uint32_t lowdrive, uint8_t deepsleepmodecmd)
|
||||||
{
|
{
|
||||||
static uint32_t reg_snap[4];
|
static uint32_t reg_snap[4];
|
||||||
/* clear stbmod and ldolp bits */
|
/* clear stbmod and ldolp bits */
|
||||||
PMU_CTL &= ~((uint32_t)(PMU_CTL_STBMOD | PMU_CTL_LDOLP));
|
PMU_CTL &= ~((uint32_t)(PMU_CTL_STBMOD | PMU_CTL_LDOLP | PMU_CTL_LDEN | PMU_CTL_LDNP | PMU_CTL_LDLP));
|
||||||
|
|
||||||
/* set ldolp bit according to pmu_ldo */
|
/* set ldolp bit according to pmu_ldo */
|
||||||
PMU_CTL |= ldo;
|
PMU_CTL |= ldo;
|
||||||
|
|
||||||
|
/* configure low drive mode in deep-sleep mode */
|
||||||
|
if(PMU_LOWDRIVER_ENABLE == lowdrive) {
|
||||||
|
if(PMU_LDO_NORMAL == ldo) {
|
||||||
|
PMU_CTL |= (uint32_t)(PMU_CTL_LDEN | PMU_CTL_LDNP);
|
||||||
|
} else {
|
||||||
|
PMU_CTL |= (uint32_t)(PMU_CTL_LDEN | PMU_CTL_LDLP);
|
||||||
|
}
|
||||||
|
}
|
||||||
/* set sleepdeep bit of Cortex-M4 system control register */
|
/* set sleepdeep bit of Cortex-M4 system control register */
|
||||||
SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
|
SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
|
||||||
|
|
||||||
|
|
@ -240,7 +262,7 @@ void pmu_to_deepsleepmode(uint32_t ldo,uint8_t deepsleepmodecmd)
|
||||||
REG32(0xE000E184U) = 0XBFFFF8FFU;
|
REG32(0xE000E184U) = 0XBFFFF8FFU;
|
||||||
REG32(0xE000E188U) = 0xFFFFEFFFU;
|
REG32(0xE000E188U) = 0xFFFFEFFFU;
|
||||||
|
|
||||||
/* select WFI or WFE command to enter deepsleep mode */
|
/* select WFI or WFE command to enter deep-sleep mode */
|
||||||
if(WFI_CMD == deepsleepmodecmd) {
|
if(WFI_CMD == deepsleepmodecmd) {
|
||||||
__WFI();
|
__WFI();
|
||||||
} else {
|
} else {
|
||||||
|
|
@ -259,30 +281,51 @@ void pmu_to_deepsleepmode(uint32_t ldo,uint8_t deepsleepmodecmd)
|
||||||
}
|
}
|
||||||
|
|
||||||
/*!
|
/*!
|
||||||
\brief pmu work at standby mode
|
\brief pmu work in standby mode
|
||||||
\param[in] standbymodecmd:
|
\param[in] none
|
||||||
\arg WFI_CMD: use WFI command
|
|
||||||
\arg WFE_CMD: use WFE command
|
|
||||||
\param[out] none
|
\param[out] none
|
||||||
\retval none
|
\retval none
|
||||||
*/
|
*/
|
||||||
void pmu_to_standbymode(uint8_t standbymodecmd)
|
void pmu_to_standbymode(void)
|
||||||
{
|
{
|
||||||
/* set sleepdeep bit of Cortex-M4 system control register */
|
|
||||||
SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
|
|
||||||
|
|
||||||
/* set stbmod bit */
|
/* set stbmod bit */
|
||||||
PMU_CTL |= PMU_CTL_STBMOD;
|
PMU_CTL |= PMU_CTL_STBMOD;
|
||||||
|
|
||||||
/* reset wakeup flag */
|
/* reset wakeup flag */
|
||||||
PMU_CTL |= PMU_CTL_WURST;
|
PMU_CTL |= PMU_CTL_WURST;
|
||||||
|
|
||||||
/* select WFI or WFE command to enter standby mode */
|
/* set sleepdeep bit of Cortex-M4 system control register */
|
||||||
if(WFI_CMD == standbymodecmd){
|
SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
|
||||||
|
|
||||||
|
REG32(0xE000E010U) &= 0x00010004U;
|
||||||
|
REG32(0xE000E180U) = 0XFFFFFFF7U;
|
||||||
|
REG32(0xE000E184U) = 0XFFFFFDFFU;
|
||||||
|
REG32(0xE000E188U) = 0xFFFFFFFFU;
|
||||||
|
|
||||||
|
/* select WFI command to enter standby mode */
|
||||||
__WFI();
|
__WFI();
|
||||||
}else{
|
|
||||||
__WFE();
|
|
||||||
}
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief enable PMU wakeup pin
|
||||||
|
\param[in] none
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void pmu_wakeup_pin_enable(void)
|
||||||
|
{
|
||||||
|
PMU_CS |= PMU_CS_WUPEN;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief disable PMU wakeup pin
|
||||||
|
\param[in] none
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void pmu_wakeup_pin_disable(void)
|
||||||
|
{
|
||||||
|
PMU_CS &= ~PMU_CS_WUPEN;
|
||||||
}
|
}
|
||||||
|
|
||||||
/*!
|
/*!
|
||||||
|
|
@ -300,16 +343,61 @@ void pmu_backup_ldo_config(uint32_t bkp_ldo)
|
||||||
}
|
}
|
||||||
|
|
||||||
/*!
|
/*!
|
||||||
\brief reset flag bit
|
\brief enable write access to the registers in backup domain
|
||||||
\param[in] flag_reset:
|
\param[in] none
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void pmu_backup_write_enable(void)
|
||||||
|
{
|
||||||
|
PMU_CTL |= PMU_CTL_BKPWEN;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief disable write access to the registers in backup domain
|
||||||
|
\param[in] none
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void pmu_backup_write_disable(void)
|
||||||
|
{
|
||||||
|
PMU_CTL &= ~PMU_CTL_BKPWEN;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief get flag state
|
||||||
|
\param[in] flag:
|
||||||
|
\arg PMU_FLAG_WAKEUP: wakeup flag
|
||||||
|
\arg PMU_FLAG_STANDBY: standby flag
|
||||||
|
\arg PMU_FLAG_LVD: lvd flag
|
||||||
|
\arg PMU_FLAG_BLDORF: backup SRAM LDO ready flag
|
||||||
|
\arg PMU_FLAG_LDOVSRF: LDO voltage select ready flag
|
||||||
|
\arg PMU_FLAG_HDRF: high-driver ready flag
|
||||||
|
\arg PMU_FLAG_HDSRF: high-driver switch ready flag
|
||||||
|
\arg PMU_FLAG_LDRF: low-driver mode ready flag
|
||||||
|
\param[out] none
|
||||||
|
\retval FlagStatus: SET or RESET
|
||||||
|
*/
|
||||||
|
FlagStatus pmu_flag_get(uint32_t flag)
|
||||||
|
{
|
||||||
|
if(PMU_CS & flag) {
|
||||||
|
return SET;
|
||||||
|
} else {
|
||||||
|
return RESET;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief clear flag bit
|
||||||
|
\param[in] flag:
|
||||||
\arg PMU_FLAG_RESET_WAKEUP: reset wakeup flag
|
\arg PMU_FLAG_RESET_WAKEUP: reset wakeup flag
|
||||||
\arg PMU_FLAG_RESET_STANDBY: reset standby flag
|
\arg PMU_FLAG_RESET_STANDBY: reset standby flag
|
||||||
\param[out] none
|
\param[out] none
|
||||||
\retval none
|
\retval none
|
||||||
*/
|
*/
|
||||||
void pmu_flag_reset(uint32_t flag_reset)
|
void pmu_flag_clear(uint32_t flag)
|
||||||
{
|
{
|
||||||
switch(flag_reset){
|
switch(flag) {
|
||||||
case PMU_FLAG_RESET_WAKEUP:
|
case PMU_FLAG_RESET_WAKEUP:
|
||||||
/* reset wakeup flag */
|
/* reset wakeup flag */
|
||||||
PMU_CTL |= PMU_CTL_WURST;
|
PMU_CTL |= PMU_CTL_WURST;
|
||||||
|
|
@ -322,70 +410,3 @@ void pmu_flag_reset(uint32_t flag_reset)
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
/*!
|
|
||||||
\brief get flag state
|
|
||||||
\param[in] pmu_flag:
|
|
||||||
\arg PMU_FLAG_WAKEUP: wakeup flag
|
|
||||||
\arg PMU_FLAG_STANDBY: standby flag
|
|
||||||
\arg PMU_FLAG_LVD: lvd flag
|
|
||||||
\arg PMU_FLAG_BLDORF: backup SRAM LDO ready flag
|
|
||||||
\arg PMU_FLAG_LDOVSRF: LDO voltage select ready flag
|
|
||||||
\arg PMU_FLAG_HDRF: high-driver ready flag
|
|
||||||
\arg PMU_FLAG_HDSRF: high-driver switch ready flag
|
|
||||||
\arg PMU_FLAG_LDRF: low-driver mode ready flag
|
|
||||||
\param[out] none
|
|
||||||
\retval FlagStatus: SET or RESET
|
|
||||||
*/
|
|
||||||
FlagStatus pmu_flag_get(uint32_t pmu_flag)
|
|
||||||
{
|
|
||||||
if(PMU_CS & pmu_flag){
|
|
||||||
return SET;
|
|
||||||
}else{
|
|
||||||
return RESET;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
\brief enable backup domain write
|
|
||||||
\param[in] none
|
|
||||||
\param[out] none
|
|
||||||
\retval none
|
|
||||||
*/
|
|
||||||
void pmu_backup_write_enable(void)
|
|
||||||
{
|
|
||||||
PMU_CTL |= PMU_CTL_BKPWEN;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
\brief disable backup domain write
|
|
||||||
\param[in] none
|
|
||||||
\param[out] none
|
|
||||||
\retval none
|
|
||||||
*/
|
|
||||||
void pmu_backup_write_disable(void)
|
|
||||||
{
|
|
||||||
PMU_CTL &= ~PMU_CTL_BKPWEN;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
\brief enable wakeup pin
|
|
||||||
\param[in] none
|
|
||||||
\param[out] none
|
|
||||||
\retval none
|
|
||||||
*/
|
|
||||||
void pmu_wakeup_pin_enable(void)
|
|
||||||
{
|
|
||||||
PMU_CS |= PMU_CS_WUPEN;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
\brief disable wakeup pin
|
|
||||||
\param[in] none
|
|
||||||
\param[out] none
|
|
||||||
\retval none
|
|
||||||
*/
|
|
||||||
void pmu_wakeup_pin_disable(void)
|
|
||||||
{
|
|
||||||
PMU_CS &= ~PMU_CS_WUPEN;
|
|
||||||
}
|
|
||||||
|
|
|
||||||
|
|
@ -5,10 +5,11 @@
|
||||||
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
||||||
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
||||||
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
||||||
|
\version 2022-03-09, V3.0.0, firmware for GD32F4xx
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/*
|
/*
|
||||||
Copyright (c) 2020, GigaDevice Semiconductor Inc.
|
Copyright (c) 2022, GigaDevice Semiconductor Inc.
|
||||||
|
|
||||||
Redistribution and use in source and binary forms, with or without modification,
|
Redistribution and use in source and binary forms, with or without modification,
|
||||||
are permitted provided that the following conditions are met:
|
are permitted provided that the following conditions are met:
|
||||||
|
|
@ -59,14 +60,16 @@ void rcu_deinit(void)
|
||||||
/* enable IRC16M */
|
/* enable IRC16M */
|
||||||
RCU_CTL |= RCU_CTL_IRC16MEN;
|
RCU_CTL |= RCU_CTL_IRC16MEN;
|
||||||
rcu_osci_stab_wait(RCU_IRC16M);
|
rcu_osci_stab_wait(RCU_IRC16M);
|
||||||
/* reset CFG0 register */
|
RCU_CFG0 &= ~RCU_CFG0_SCS;
|
||||||
RCU_CFG0 &= ~(RCU_CFG0_SCS | RCU_CFG0_AHBPSC | RCU_CFG0_APB1PSC | RCU_CFG0_APB2PSC |
|
|
||||||
RCU_CFG0_RTCDIV | RCU_CFG0_CKOUT0SEL | RCU_CFG0_I2SSEL | RCU_CFG0_CKOUT0DIV |
|
|
||||||
RCU_CFG0_CKOUT1DIV | RCU_CFG0_CKOUT1SEL);
|
|
||||||
/* reset CTL register */
|
/* reset CTL register */
|
||||||
RCU_CTL &= ~(RCU_CTL_HXTALEN | RCU_CTL_CKMEN | RCU_CTL_PLLEN | RCU_CTL_PLLI2SEN
|
RCU_CTL &= ~(RCU_CTL_HXTALEN | RCU_CTL_CKMEN | RCU_CTL_PLLEN | RCU_CTL_PLLI2SEN
|
||||||
| RCU_CTL_PLLSAIEN);
|
| RCU_CTL_PLLSAIEN);
|
||||||
RCU_CTL &= ~(RCU_CTL_HXTALBPS);
|
RCU_CTL &= ~(RCU_CTL_HXTALBPS);
|
||||||
|
/* reset CFG0 register */
|
||||||
|
RCU_CFG0 &= ~(RCU_CFG0_SCS | RCU_CFG0_AHBPSC | RCU_CFG0_APB1PSC | RCU_CFG0_APB2PSC |
|
||||||
|
RCU_CFG0_RTCDIV | RCU_CFG0_CKOUT0SEL | RCU_CFG0_I2SSEL | RCU_CFG0_CKOUT0DIV |
|
||||||
|
RCU_CFG0_CKOUT1DIV | RCU_CFG0_CKOUT1SEL);
|
||||||
/* reset PLL register */
|
/* reset PLL register */
|
||||||
RCU_PLL = 0x24003010U;
|
RCU_PLL = 0x24003010U;
|
||||||
/* reset PLLI2S register */
|
/* reset PLLI2S register */
|
||||||
|
|
@ -395,7 +398,7 @@ uint32_t rcu_system_clock_source_get(void)
|
||||||
\brief configure the AHB clock prescaler selection
|
\brief configure the AHB clock prescaler selection
|
||||||
\param[in] ck_ahb: AHB clock prescaler selection
|
\param[in] ck_ahb: AHB clock prescaler selection
|
||||||
only one parameter can be selected which is shown as below:
|
only one parameter can be selected which is shown as below:
|
||||||
\arg RCU_AHB_CKSYS_DIVx, x=1, 2, 4, 8, 16, 64, 128, 256, 512
|
\arg RCU_AHB_CKSYS_DIVx (x = 1, 2, 4, 8, 16, 64, 128, 256, 512): select CK_SYS / x as CK_AHB
|
||||||
\param[out] none
|
\param[out] none
|
||||||
\retval none
|
\retval none
|
||||||
*/
|
*/
|
||||||
|
|
@ -735,137 +738,6 @@ void rcu_tli_clock_div_config(uint32_t pllsai_r_div)
|
||||||
RCU_CFG1 = (reg | pllsai_r_div);
|
RCU_CFG1 = (reg | pllsai_r_div);
|
||||||
}
|
}
|
||||||
|
|
||||||
/*!
|
|
||||||
\brief get the clock stabilization and periphral reset flags
|
|
||||||
\param[in] flag: the clock stabilization and periphral reset flags, refer to rcu_flag_enum
|
|
||||||
only one parameter can be selected which is shown as below:
|
|
||||||
\arg RCU_FLAG_IRC16MSTB: IRC16M stabilization flag
|
|
||||||
\arg RCU_FLAG_HXTALSTB: HXTAL stabilization flag
|
|
||||||
\arg RCU_FLAG_PLLSTB: PLL stabilization flag
|
|
||||||
\arg RCU_FLAG_PLLI2SSTB: PLLI2S stabilization flag
|
|
||||||
\arg RCU_FLAG_PLLSAISTB: PLLSAI stabilization flag
|
|
||||||
\arg RCU_FLAG_LXTALSTB: LXTAL stabilization flag
|
|
||||||
\arg RCU_FLAG_IRC32KSTB: IRC32K stabilization flag
|
|
||||||
\arg RCU_FLAG_IRC48MSTB: IRC48M stabilization flag
|
|
||||||
\arg RCU_FLAG_BORRST: BOR reset flags
|
|
||||||
\arg RCU_FLAG_EPRST: external PIN reset flag
|
|
||||||
\arg RCU_FLAG_PORRST: Power reset flag
|
|
||||||
\arg RCU_FLAG_SWRST: software reset flag
|
|
||||||
\arg RCU_FLAG_FWDGTRST: free watchdog timer reset flag
|
|
||||||
\arg RCU_FLAG_WWDGTRST: window watchdog timer reset flag
|
|
||||||
\arg RCU_FLAG_LPRST: low-power reset flag
|
|
||||||
\param[out] none
|
|
||||||
\retval none
|
|
||||||
*/
|
|
||||||
FlagStatus rcu_flag_get(rcu_flag_enum flag)
|
|
||||||
{
|
|
||||||
/* get the rcu flag */
|
|
||||||
if(RESET != (RCU_REG_VAL(flag) & BIT(RCU_BIT_POS(flag)))){
|
|
||||||
return SET;
|
|
||||||
}else{
|
|
||||||
return RESET;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
\brief clear all the reset flag
|
|
||||||
\param[in] none
|
|
||||||
\param[out] none
|
|
||||||
\retval none
|
|
||||||
*/
|
|
||||||
void rcu_all_reset_flag_clear(void)
|
|
||||||
{
|
|
||||||
RCU_RSTSCK |= RCU_RSTSCK_RSTFC;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
\brief get the clock stabilization interrupt and ckm flags
|
|
||||||
\param[in] int_flag: interrupt and ckm flags, refer to rcu_int_flag_enum
|
|
||||||
only one parameter can be selected which is shown as below:
|
|
||||||
\arg RCU_INT_FLAG_IRC32KSTB: IRC32K stabilization interrupt flag
|
|
||||||
\arg RCU_INT_FLAG_LXTALSTB: LXTAL stabilization interrupt flag
|
|
||||||
\arg RCU_INT_FLAG_IRC16MSTB: IRC16M stabilization interrupt flag
|
|
||||||
\arg RCU_INT_FLAG_HXTALSTB: HXTAL stabilization interrupt flag
|
|
||||||
\arg RCU_INT_FLAG_PLLSTB: PLL stabilization interrupt flag
|
|
||||||
\arg RCU_INT_FLAG_PLLI2SSTB: PLLI2S stabilization interrupt flag
|
|
||||||
\arg RCU_INT_FLAG_PLLSAISTB: PLLSAI stabilization interrupt flag
|
|
||||||
\arg RCU_INT_FLAG_CKM: HXTAL clock stuck interrupt flag
|
|
||||||
\arg RCU_INT_FLAG_IRC48MSTB: IRC48M stabilization interrupt flag
|
|
||||||
\param[out] none
|
|
||||||
\retval FlagStatus: SET or RESET
|
|
||||||
*/
|
|
||||||
FlagStatus rcu_interrupt_flag_get(rcu_int_flag_enum int_flag)
|
|
||||||
{
|
|
||||||
/* get the rcu interrupt flag */
|
|
||||||
if(RESET != (RCU_REG_VAL(int_flag) & BIT(RCU_BIT_POS(int_flag)))){
|
|
||||||
return SET;
|
|
||||||
}else{
|
|
||||||
return RESET;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
\brief clear the interrupt flags
|
|
||||||
\param[in] int_flag: clock stabilization and stuck interrupt flags clear, refer to rcu_int_flag_clear_enum
|
|
||||||
only one parameter can be selected which is shown as below:
|
|
||||||
\arg RCU_INT_FLAG_IRC32KSTB_CLR: IRC32K stabilization interrupt flag clear
|
|
||||||
\arg RCU_INT_FLAG_LXTALSTB_CLR: LXTAL stabilization interrupt flag clear
|
|
||||||
\arg RCU_INT_FLAG_IRC16MSTB_CLR: IRC16M stabilization interrupt flag clear
|
|
||||||
\arg RCU_INT_FLAG_HXTALSTB_CLR: HXTAL stabilization interrupt flag clear
|
|
||||||
\arg RCU_INT_FLAG_PLLSTB_CLR: PLL stabilization interrupt flag clear
|
|
||||||
\arg RCU_INT_FLAG_PLLI2SSTB_CLR: PLLI2S stabilization interrupt flag clear
|
|
||||||
\arg RCU_INT_FLAG_PLLSAISTB_CLR: PLLSAI stabilization interrupt flag clear
|
|
||||||
\arg RCU_INT_FLAG_CKM_CLR: clock stuck interrupt flag clear
|
|
||||||
\arg RCU_INT_FLAG_IRC48MSTB_CLR: IRC48M stabilization interrupt flag clear
|
|
||||||
\param[out] none
|
|
||||||
\retval none
|
|
||||||
*/
|
|
||||||
void rcu_interrupt_flag_clear(rcu_int_flag_clear_enum int_flag)
|
|
||||||
{
|
|
||||||
RCU_REG_VAL(int_flag) |= BIT(RCU_BIT_POS(int_flag));
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
\brief enable the stabilization interrupt
|
|
||||||
\param[in] interrupt: clock stabilization interrupt, refer to rcu_int_enum
|
|
||||||
Only one parameter can be selected which is shown as below:
|
|
||||||
\arg RCU_INT_IRC32KSTB: IRC32K stabilization interrupt enable
|
|
||||||
\arg RCU_INT_LXTALSTB: LXTAL stabilization interrupt enable
|
|
||||||
\arg RCU_INT_IRC16MSTB: IRC16M stabilization interrupt enable
|
|
||||||
\arg RCU_INT_HXTALSTB: HXTAL stabilization interrupt enable
|
|
||||||
\arg RCU_INT_PLLSTB: PLL stabilization interrupt enable
|
|
||||||
\arg RCU_INT_PLLI2SSTB: PLLI2S stabilization interrupt enable
|
|
||||||
\arg RCU_INT_PLLSAISTB: PLLSAI stabilization interrupt enable
|
|
||||||
\arg RCU_INT_IRC48MSTB: IRC48M stabilization interrupt enable
|
|
||||||
\param[out] none
|
|
||||||
\retval none
|
|
||||||
*/
|
|
||||||
void rcu_interrupt_enable(rcu_int_enum interrupt)
|
|
||||||
{
|
|
||||||
RCU_REG_VAL(interrupt) |= BIT(RCU_BIT_POS(interrupt));
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
/*!
|
|
||||||
\brief disable the stabilization interrupt
|
|
||||||
\param[in] interrupt: clock stabilization interrupt, refer to rcu_int_enum
|
|
||||||
only one parameter can be selected which is shown as below:
|
|
||||||
\arg RCU_INT_IRC32KSTB: IRC32K stabilization interrupt disable
|
|
||||||
\arg RCU_INT_LXTALSTB: LXTAL stabilization interrupt disable
|
|
||||||
\arg RCU_INT_IRC16MSTB: IRC16M stabilization interrupt disable
|
|
||||||
\arg RCU_INT_HXTALSTB: HXTAL stabilization interrupt disable
|
|
||||||
\arg RCU_INT_PLLSTB: PLL stabilization interrupt disable
|
|
||||||
\arg RCU_INT_PLLI2SSTB: PLLI2S stabilization interrupt disable
|
|
||||||
\arg RCU_INT_PLLSAISTB: PLLSAI stabilization interrupt disable
|
|
||||||
\arg RCU_INT_IRC48MSTB: IRC48M stabilization interrupt disable
|
|
||||||
\param[out] none
|
|
||||||
\retval none
|
|
||||||
*/
|
|
||||||
void rcu_interrupt_disable(rcu_int_enum interrupt)
|
|
||||||
{
|
|
||||||
RCU_REG_VAL(interrupt) &= ~BIT(RCU_BIT_POS(interrupt));
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
/*!
|
||||||
\brief configure the LXTAL drive capability
|
\brief configure the LXTAL drive capability
|
||||||
\param[in] lxtal_dricap: drive capability of LXTAL
|
\param[in] lxtal_dricap: drive capability of LXTAL
|
||||||
|
|
@ -1129,29 +1001,6 @@ void rcu_osci_bypass_mode_disable(rcu_osci_type_enum osci)
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
/*!
|
|
||||||
\brief enable the HXTAL clock monitor
|
|
||||||
\param[in] none
|
|
||||||
\param[out] none
|
|
||||||
\retval none
|
|
||||||
*/
|
|
||||||
|
|
||||||
void rcu_hxtal_clock_monitor_enable(void)
|
|
||||||
{
|
|
||||||
RCU_CTL |= RCU_CTL_CKMEN;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
\brief disable the HXTAL clock monitor
|
|
||||||
\param[in] none
|
|
||||||
\param[out] none
|
|
||||||
\retval none
|
|
||||||
*/
|
|
||||||
void rcu_hxtal_clock_monitor_disable(void)
|
|
||||||
{
|
|
||||||
RCU_CTL &= ~RCU_CTL_CKMEN;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
/*!
|
||||||
\brief set the IRC16M adjust value
|
\brief set the IRC16M adjust value
|
||||||
\param[in] irc16m_adjval: IRC16M adjust value, must be between 0 and 0x1F
|
\param[in] irc16m_adjval: IRC16M adjust value, must be between 0 and 0x1F
|
||||||
|
|
@ -1169,34 +1018,6 @@ void rcu_irc16m_adjust_value_set(uint32_t irc16m_adjval)
|
||||||
RCU_CTL = (reg | ((irc16m_adjval & RCU_IRC16M_ADJUST_MASK) << RCU_IRC16M_ADJUST_OFFSET));
|
RCU_CTL = (reg | ((irc16m_adjval & RCU_IRC16M_ADJUST_MASK) << RCU_IRC16M_ADJUST_OFFSET));
|
||||||
}
|
}
|
||||||
|
|
||||||
/*!
|
|
||||||
\brief unlock the voltage key
|
|
||||||
\param[in] none
|
|
||||||
\param[out] none
|
|
||||||
\retval none
|
|
||||||
*/
|
|
||||||
void rcu_voltage_key_unlock(void)
|
|
||||||
{
|
|
||||||
RCU_VKEY = RCU_VKEY_UNLOCK;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
\brief deep-sleep mode voltage select
|
|
||||||
\param[in] dsvol: deep sleep mode voltage
|
|
||||||
only one parameter can be selected which is shown as below:
|
|
||||||
\arg RCU_DEEPSLEEP_V_1_2: the core voltage is 1.2V
|
|
||||||
\arg RCU_DEEPSLEEP_V_1_1: the core voltage is 1.1V
|
|
||||||
\arg RCU_DEEPSLEEP_V_1_0: the core voltage is 1.0V
|
|
||||||
\arg RCU_DEEPSLEEP_V_0_9: the core voltage is 0.9V
|
|
||||||
\param[out] none
|
|
||||||
\retval none
|
|
||||||
*/
|
|
||||||
void rcu_deepsleep_voltage_set(uint32_t dsvol)
|
|
||||||
{
|
|
||||||
dsvol &= RCU_DSV_DSLPVS;
|
|
||||||
RCU_DSV = dsvol;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
/*!
|
||||||
\brief configure the spread spectrum modulation for the main PLL clock
|
\brief configure the spread spectrum modulation for the main PLL clock
|
||||||
\param[in] spread_spectrum_type: PLL spread spectrum modulation type select
|
\param[in] spread_spectrum_type: PLL spread spectrum modulation type select
|
||||||
|
|
@ -1241,6 +1062,57 @@ void rcu_spread_spectrum_disable(void)
|
||||||
RCU_PLLSSCTL &= ~RCU_PLLSSCTL_SSCGON;
|
RCU_PLLSSCTL &= ~RCU_PLLSSCTL_SSCGON;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief enable the HXTAL clock monitor
|
||||||
|
\param[in] none
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
|
||||||
|
void rcu_hxtal_clock_monitor_enable(void)
|
||||||
|
{
|
||||||
|
RCU_CTL |= RCU_CTL_CKMEN;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief disable the HXTAL clock monitor
|
||||||
|
\param[in] none
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void rcu_hxtal_clock_monitor_disable(void)
|
||||||
|
{
|
||||||
|
RCU_CTL &= ~RCU_CTL_CKMEN;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief unlock the voltage key
|
||||||
|
\param[in] none
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void rcu_voltage_key_unlock(void)
|
||||||
|
{
|
||||||
|
RCU_VKEY = RCU_VKEY_UNLOCK;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief deep-sleep mode voltage select
|
||||||
|
\param[in] dsvol: deep sleep mode voltage
|
||||||
|
only one parameter can be selected which is shown as below:
|
||||||
|
\arg RCU_DEEPSLEEP_V_0: the core voltage is default value
|
||||||
|
\arg RCU_DEEPSLEEP_V_1: the core voltage is (default value-0.1)V(customers are not recommended to use it)
|
||||||
|
\arg RCU_DEEPSLEEP_V_2: the core voltage is (default value-0.2)V(customers are not recommended to use it)
|
||||||
|
\arg RCU_DEEPSLEEP_V_3: the core voltage is (default value-0.3)V(customers are not recommended to use it)
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void rcu_deepsleep_voltage_set(uint32_t dsvol)
|
||||||
|
{
|
||||||
|
dsvol &= RCU_DSV_DSLPVS;
|
||||||
|
RCU_DSV = dsvol;
|
||||||
|
}
|
||||||
|
|
||||||
/*!
|
/*!
|
||||||
\brief get the system clock, bus and peripheral clock frequency
|
\brief get the system clock, bus and peripheral clock frequency
|
||||||
\param[in] clock: the clock frequency which to get
|
\param[in] clock: the clock frequency which to get
|
||||||
|
|
@ -1327,3 +1199,134 @@ uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock)
|
||||||
}
|
}
|
||||||
return ck_freq;
|
return ck_freq;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief get the clock stabilization and periphral reset flags
|
||||||
|
\param[in] flag: the clock stabilization and periphral reset flags, refer to rcu_flag_enum
|
||||||
|
only one parameter can be selected which is shown as below:
|
||||||
|
\arg RCU_FLAG_IRC16MSTB: IRC16M stabilization flag
|
||||||
|
\arg RCU_FLAG_HXTALSTB: HXTAL stabilization flag
|
||||||
|
\arg RCU_FLAG_PLLSTB: PLL stabilization flag
|
||||||
|
\arg RCU_FLAG_PLLI2SSTB: PLLI2S stabilization flag
|
||||||
|
\arg RCU_FLAG_PLLSAISTB: PLLSAI stabilization flag
|
||||||
|
\arg RCU_FLAG_LXTALSTB: LXTAL stabilization flag
|
||||||
|
\arg RCU_FLAG_IRC32KSTB: IRC32K stabilization flag
|
||||||
|
\arg RCU_FLAG_IRC48MSTB: IRC48M stabilization flag
|
||||||
|
\arg RCU_FLAG_BORRST: BOR reset flags
|
||||||
|
\arg RCU_FLAG_EPRST: external PIN reset flag
|
||||||
|
\arg RCU_FLAG_PORRST: Power reset flag
|
||||||
|
\arg RCU_FLAG_SWRST: software reset flag
|
||||||
|
\arg RCU_FLAG_FWDGTRST: free watchdog timer reset flag
|
||||||
|
\arg RCU_FLAG_WWDGTRST: window watchdog timer reset flag
|
||||||
|
\arg RCU_FLAG_LPRST: low-power reset flag
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
FlagStatus rcu_flag_get(rcu_flag_enum flag)
|
||||||
|
{
|
||||||
|
/* get the rcu flag */
|
||||||
|
if(RESET != (RCU_REG_VAL(flag) & BIT(RCU_BIT_POS(flag)))) {
|
||||||
|
return SET;
|
||||||
|
} else {
|
||||||
|
return RESET;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief clear all the reset flag
|
||||||
|
\param[in] none
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void rcu_all_reset_flag_clear(void)
|
||||||
|
{
|
||||||
|
RCU_RSTSCK |= RCU_RSTSCK_RSTFC;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief get the clock stabilization interrupt and ckm flags
|
||||||
|
\param[in] int_flag: interrupt and ckm flags, refer to rcu_int_flag_enum
|
||||||
|
only one parameter can be selected which is shown as below:
|
||||||
|
\arg RCU_INT_FLAG_IRC32KSTB: IRC32K stabilization interrupt flag
|
||||||
|
\arg RCU_INT_FLAG_LXTALSTB: LXTAL stabilization interrupt flag
|
||||||
|
\arg RCU_INT_FLAG_IRC16MSTB: IRC16M stabilization interrupt flag
|
||||||
|
\arg RCU_INT_FLAG_HXTALSTB: HXTAL stabilization interrupt flag
|
||||||
|
\arg RCU_INT_FLAG_PLLSTB: PLL stabilization interrupt flag
|
||||||
|
\arg RCU_INT_FLAG_PLLI2SSTB: PLLI2S stabilization interrupt flag
|
||||||
|
\arg RCU_INT_FLAG_PLLSAISTB: PLLSAI stabilization interrupt flag
|
||||||
|
\arg RCU_INT_FLAG_CKM: HXTAL clock stuck interrupt flag
|
||||||
|
\arg RCU_INT_FLAG_IRC48MSTB: IRC48M stabilization interrupt flag
|
||||||
|
\param[out] none
|
||||||
|
\retval FlagStatus: SET or RESET
|
||||||
|
*/
|
||||||
|
FlagStatus rcu_interrupt_flag_get(rcu_int_flag_enum int_flag)
|
||||||
|
{
|
||||||
|
/* get the rcu interrupt flag */
|
||||||
|
if(RESET != (RCU_REG_VAL(int_flag) & BIT(RCU_BIT_POS(int_flag)))) {
|
||||||
|
return SET;
|
||||||
|
} else {
|
||||||
|
return RESET;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief clear the interrupt flags
|
||||||
|
\param[in] int_flag: clock stabilization and stuck interrupt flags clear, refer to rcu_int_flag_clear_enum
|
||||||
|
only one parameter can be selected which is shown as below:
|
||||||
|
\arg RCU_INT_FLAG_IRC32KSTB_CLR: IRC32K stabilization interrupt flag clear
|
||||||
|
\arg RCU_INT_FLAG_LXTALSTB_CLR: LXTAL stabilization interrupt flag clear
|
||||||
|
\arg RCU_INT_FLAG_IRC16MSTB_CLR: IRC16M stabilization interrupt flag clear
|
||||||
|
\arg RCU_INT_FLAG_HXTALSTB_CLR: HXTAL stabilization interrupt flag clear
|
||||||
|
\arg RCU_INT_FLAG_PLLSTB_CLR: PLL stabilization interrupt flag clear
|
||||||
|
\arg RCU_INT_FLAG_PLLI2SSTB_CLR: PLLI2S stabilization interrupt flag clear
|
||||||
|
\arg RCU_INT_FLAG_PLLSAISTB_CLR: PLLSAI stabilization interrupt flag clear
|
||||||
|
\arg RCU_INT_FLAG_CKM_CLR: clock stuck interrupt flag clear
|
||||||
|
\arg RCU_INT_FLAG_IRC48MSTB_CLR: IRC48M stabilization interrupt flag clear
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void rcu_interrupt_flag_clear(rcu_int_flag_clear_enum int_flag)
|
||||||
|
{
|
||||||
|
RCU_REG_VAL(int_flag) |= BIT(RCU_BIT_POS(int_flag));
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief enable the stabilization interrupt
|
||||||
|
\param[in] interrupt: clock stabilization interrupt, refer to rcu_int_enum
|
||||||
|
Only one parameter can be selected which is shown as below:
|
||||||
|
\arg RCU_INT_IRC32KSTB: IRC32K stabilization interrupt enable
|
||||||
|
\arg RCU_INT_LXTALSTB: LXTAL stabilization interrupt enable
|
||||||
|
\arg RCU_INT_IRC16MSTB: IRC16M stabilization interrupt enable
|
||||||
|
\arg RCU_INT_HXTALSTB: HXTAL stabilization interrupt enable
|
||||||
|
\arg RCU_INT_PLLSTB: PLL stabilization interrupt enable
|
||||||
|
\arg RCU_INT_PLLI2SSTB: PLLI2S stabilization interrupt enable
|
||||||
|
\arg RCU_INT_PLLSAISTB: PLLSAI stabilization interrupt enable
|
||||||
|
\arg RCU_INT_IRC48MSTB: IRC48M stabilization interrupt enable
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void rcu_interrupt_enable(rcu_int_enum interrupt)
|
||||||
|
{
|
||||||
|
RCU_REG_VAL(interrupt) |= BIT(RCU_BIT_POS(interrupt));
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief disable the stabilization interrupt
|
||||||
|
\param[in] interrupt: clock stabilization interrupt, refer to rcu_int_enum
|
||||||
|
only one parameter can be selected which is shown as below:
|
||||||
|
\arg RCU_INT_IRC32KSTB: IRC32K stabilization interrupt disable
|
||||||
|
\arg RCU_INT_LXTALSTB: LXTAL stabilization interrupt disable
|
||||||
|
\arg RCU_INT_IRC16MSTB: IRC16M stabilization interrupt disable
|
||||||
|
\arg RCU_INT_HXTALSTB: HXTAL stabilization interrupt disable
|
||||||
|
\arg RCU_INT_PLLSTB: PLL stabilization interrupt disable
|
||||||
|
\arg RCU_INT_PLLI2SSTB: PLLI2S stabilization interrupt disable
|
||||||
|
\arg RCU_INT_PLLSAISTB: PLLSAI stabilization interrupt disable
|
||||||
|
\arg RCU_INT_IRC48MSTB: IRC48M stabilization interrupt disable
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void rcu_interrupt_disable(rcu_int_enum interrupt)
|
||||||
|
{
|
||||||
|
RCU_REG_VAL(interrupt) &= ~BIT(RCU_BIT_POS(interrupt));
|
||||||
|
}
|
||||||
|
|
|
||||||
|
|
@ -5,10 +5,11 @@
|
||||||
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
||||||
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
||||||
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
||||||
|
\version 2022-03-09, V3.0.0, firmware for GD32F4xx
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/*
|
/*
|
||||||
Copyright (c) 2020, GigaDevice Semiconductor Inc.
|
Copyright (c) 2022, GigaDevice Semiconductor Inc.
|
||||||
|
|
||||||
Redistribution and use in source and binary forms, with or without modification,
|
Redistribution and use in source and binary forms, with or without modification,
|
||||||
are permitted provided that the following conditions are met:
|
are permitted provided that the following conditions are met:
|
||||||
|
|
@ -45,7 +46,6 @@ OF SUCH DAMAGE.
|
||||||
#define RTC_SHIFTCTL_TIMEOUT ((uint32_t)0x00001000U) /*!< shift function operation pending flag timeout */
|
#define RTC_SHIFTCTL_TIMEOUT ((uint32_t)0x00001000U) /*!< shift function operation pending flag timeout */
|
||||||
#define RTC_ALRMXWF_TIMEOUT ((uint32_t)0x00008000U) /*!< alarm configuration can be write flag timeout */
|
#define RTC_ALRMXWF_TIMEOUT ((uint32_t)0x00008000U) /*!< alarm configuration can be write flag timeout */
|
||||||
|
|
||||||
|
|
||||||
/*!
|
/*!
|
||||||
\brief reset most of the RTC registers
|
\brief reset most of the RTC registers
|
||||||
\param[in] none
|
\param[in] none
|
||||||
|
|
@ -295,7 +295,7 @@ void rtc_current_time_get(rtc_parameter_struct* rtc_initpara_struct)
|
||||||
rtc_initpara_struct->second = (uint8_t)GET_TIME_SC(temp_tr);
|
rtc_initpara_struct->second = (uint8_t)GET_TIME_SC(temp_tr);
|
||||||
rtc_initpara_struct->factor_asyn = (uint16_t)GET_PSC_FACTOR_A(temp_pscr);
|
rtc_initpara_struct->factor_asyn = (uint16_t)GET_PSC_FACTOR_A(temp_pscr);
|
||||||
rtc_initpara_struct->factor_syn = (uint16_t)GET_PSC_FACTOR_S(temp_pscr);
|
rtc_initpara_struct->factor_syn = (uint16_t)GET_PSC_FACTOR_S(temp_pscr);
|
||||||
rtc_initpara_struct->am_pm = (uint32_t)(temp_pscr & RTC_TIME_PM);
|
rtc_initpara_struct->am_pm = (uint32_t)(temp_tr & RTC_TIME_PM);
|
||||||
rtc_initpara_struct->display_format = (uint32_t)(temp_ctlr & RTC_CTL_CS);
|
rtc_initpara_struct->display_format = (uint32_t)(temp_ctlr & RTC_CTL_CS);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
@ -780,8 +780,8 @@ void rtc_interrupt_disable(uint32_t interrupt)
|
||||||
\arg RTC_FLAG_TP0: RTC tamper 0 detected flag
|
\arg RTC_FLAG_TP0: RTC tamper 0 detected flag
|
||||||
\arg RTC_FLAG_TSOVR: time-stamp overflow flag
|
\arg RTC_FLAG_TSOVR: time-stamp overflow flag
|
||||||
\arg RTC_FLAG_TS: time-stamp flag
|
\arg RTC_FLAG_TS: time-stamp flag
|
||||||
\arg RTC_FLAG_ALARM0: alarm0 occurs flag
|
\arg RTC_FLAG_ALRM0: alarm0 occurs flag
|
||||||
\arg RTC_FLAG_ALARM1: alarm1 occurs flag
|
\arg RTC_FLAG_ALRM1: alarm1 occurs flag
|
||||||
\arg RTC_FLAG_WT: wakeup timer occurs flag
|
\arg RTC_FLAG_WT: wakeup timer occurs flag
|
||||||
\arg RTC_FLAG_INIT: initialization state flag
|
\arg RTC_FLAG_INIT: initialization state flag
|
||||||
\arg RTC_FLAG_RSYN: register synchronization flag
|
\arg RTC_FLAG_RSYN: register synchronization flag
|
||||||
|
|
@ -876,7 +876,6 @@ void rtc_calibration_output_config(uint32_t source)
|
||||||
RTC_WPK = RTC_LOCK_KEY;
|
RTC_WPK = RTC_LOCK_KEY;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
/*!
|
/*!
|
||||||
\brief adjust the daylight saving time by adding or substracting one hour from the current time
|
\brief adjust the daylight saving time by adding or substracting one hour from the current time
|
||||||
\param[in] operation: hour adjustment operation
|
\param[in] operation: hour adjustment operation
|
||||||
|
|
|
||||||
|
|
@ -5,10 +5,11 @@
|
||||||
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
||||||
\version 2018-12-12, V2.0.1, firmware for GD32F4xx
|
\version 2018-12-12, V2.0.1, firmware for GD32F4xx
|
||||||
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
||||||
|
\version 2022-03-09, V3.0.0, firmware for GD32F4xx
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/*
|
/*
|
||||||
Copyright (c) 2020, GigaDevice Semiconductor Inc.
|
Copyright (c) 2022, GigaDevice Semiconductor Inc.
|
||||||
|
|
||||||
Redistribution and use in source and binary forms, with or without modification,
|
Redistribution and use in source and binary forms, with or without modification,
|
||||||
are permitted provided that the following conditions are met:
|
are permitted provided that the following conditions are met:
|
||||||
|
|
|
||||||
|
|
@ -5,10 +5,11 @@
|
||||||
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
||||||
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
||||||
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
||||||
|
\version 2022-03-09, V3.0.0, firmware for GD32F4xx
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/*
|
/*
|
||||||
Copyright (c) 2020, GigaDevice Semiconductor Inc.
|
Copyright (c) 2022, GigaDevice Semiconductor Inc.
|
||||||
|
|
||||||
Redistribution and use in source and binary forms, with or without modification,
|
Redistribution and use in source and binary forms, with or without modification,
|
||||||
are permitted provided that the following conditions are met:
|
are permitted provided that the following conditions are met:
|
||||||
|
|
@ -280,13 +281,11 @@ void i2s_psc_config(uint32_t spi_periph, uint32_t i2s_audiosample, uint32_t i2s_
|
||||||
/* get the RCU_PLLI2S_PLLI2SR value */
|
/* get the RCU_PLLI2S_PLLI2SR value */
|
||||||
plli2sr = (uint32_t)((RCU_PLLI2S & RCU_PLLI2S_PLLI2SR) >> 28);
|
plli2sr = (uint32_t)((RCU_PLLI2S & RCU_PLLI2S_PLLI2SR) >> 28);
|
||||||
|
|
||||||
if((RCU_PLL & RCU_PLL_PLLSEL) == RCU_PLLSRC_HXTAL)
|
if((RCU_PLL & RCU_PLL_PLLSEL) == RCU_PLLSRC_HXTAL) {
|
||||||
{
|
|
||||||
/* get the I2S source clock value */
|
/* get the I2S source clock value */
|
||||||
i2sclock = (uint32_t)(((HXTAL_VALUE / plli2sm) * plli2sn) / plli2sr);
|
i2sclock = (uint32_t)(((HXTAL_VALUE / plli2sm) * plli2sn) / plli2sr);
|
||||||
}
|
} else {
|
||||||
else
|
/* get the I2S source clock value */
|
||||||
{ /* get the I2S source clock value */
|
|
||||||
i2sclock = (uint32_t)(((IRC16M_VALUE / plli2sm) * plli2sn) / plli2sr);
|
i2sclock = (uint32_t)(((IRC16M_VALUE / plli2sm) * plli2sn) / plli2sr);
|
||||||
}
|
}
|
||||||
#endif /* I2S_EXTERNAL_CLOCK_IN */
|
#endif /* I2S_EXTERNAL_CLOCK_IN */
|
||||||
|
|
@ -487,107 +486,6 @@ void spi_bidirectional_transfer_config(uint32_t spi_periph, uint32_t transfer_di
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
/*!
|
|
||||||
\brief set SPI CRC polynomial
|
|
||||||
\param[in] spi_periph: SPIx(x=0,1,2,3,4,5)
|
|
||||||
\param[in] crc_poly: CRC polynomial value
|
|
||||||
\param[out] none
|
|
||||||
\retval none
|
|
||||||
*/
|
|
||||||
void spi_crc_polynomial_set(uint32_t spi_periph,uint16_t crc_poly)
|
|
||||||
{
|
|
||||||
/* enable SPI CRC */
|
|
||||||
SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_CRCEN;
|
|
||||||
|
|
||||||
/* set SPI CRC polynomial */
|
|
||||||
SPI_CRCPOLY(spi_periph) = (uint32_t)crc_poly;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
\brief get SPI CRC polynomial
|
|
||||||
\param[in] spi_periph: SPIx(x=0,1,2,3,4,5)
|
|
||||||
\param[out] none
|
|
||||||
\retval 16-bit CRC polynomial
|
|
||||||
*/
|
|
||||||
uint16_t spi_crc_polynomial_get(uint32_t spi_periph)
|
|
||||||
{
|
|
||||||
return ((uint16_t)SPI_CRCPOLY(spi_periph));
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
\brief turn on CRC function
|
|
||||||
\param[in] spi_periph: SPIx(x=0,1,2,3,4,5)
|
|
||||||
\param[out] none
|
|
||||||
\retval none
|
|
||||||
*/
|
|
||||||
void spi_crc_on(uint32_t spi_periph)
|
|
||||||
{
|
|
||||||
SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_CRCEN;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
\brief turn off CRC function
|
|
||||||
\param[in] spi_periph: SPIx(x=0,1,2,3,4,5)
|
|
||||||
\param[out] none
|
|
||||||
\retval none
|
|
||||||
*/
|
|
||||||
void spi_crc_off(uint32_t spi_periph)
|
|
||||||
{
|
|
||||||
SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_CRCEN);
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
\brief SPI next data is CRC value
|
|
||||||
\param[in] spi_periph: SPIx(x=0,1,2,3,4,5)
|
|
||||||
\param[out] none
|
|
||||||
\retval none
|
|
||||||
*/
|
|
||||||
void spi_crc_next(uint32_t spi_periph)
|
|
||||||
{
|
|
||||||
SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_CRCNT;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
\brief get SPI CRC send value or receive value
|
|
||||||
\param[in] spi_periph: SPIx(x=0,1,2,3,4,5)
|
|
||||||
\param[in] spi_crc: SPI crc value
|
|
||||||
only one parameter can be selected which is shown as below:
|
|
||||||
\arg SPI_CRC_TX: get transmit crc value
|
|
||||||
\arg SPI_CRC_RX: get receive crc value
|
|
||||||
\param[out] none
|
|
||||||
\retval 16-bit CRC value
|
|
||||||
*/
|
|
||||||
uint16_t spi_crc_get(uint32_t spi_periph,uint8_t spi_crc)
|
|
||||||
{
|
|
||||||
if(SPI_CRC_TX == spi_crc){
|
|
||||||
return ((uint16_t)(SPI_TCRC(spi_periph)));
|
|
||||||
}else{
|
|
||||||
return ((uint16_t)(SPI_RCRC(spi_periph)));
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
\brief enable SPI TI mode
|
|
||||||
\param[in] spi_periph: SPIx(x=0,1,2,3,4,5)
|
|
||||||
\param[out] none
|
|
||||||
\retval none
|
|
||||||
*/
|
|
||||||
void spi_ti_mode_enable(uint32_t spi_periph)
|
|
||||||
{
|
|
||||||
SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_TMOD;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
\brief disable SPI TI mode
|
|
||||||
\param[in] spi_periph: SPIx(x=0,1,2,3,4,5)
|
|
||||||
\param[out] none
|
|
||||||
\retval none
|
|
||||||
*/
|
|
||||||
void spi_ti_mode_disable(uint32_t spi_periph)
|
|
||||||
{
|
|
||||||
SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_TMOD);
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
/*!
|
||||||
\brief configure i2s full duplex mode
|
\brief configure i2s full duplex mode
|
||||||
\param[in] i2s_add_periph: I2Sx_ADD(x=1,2)
|
\param[in] i2s_add_periph: I2Sx_ADD(x=1,2)
|
||||||
|
|
@ -643,13 +541,136 @@ void i2s_full_duplex_mode_config(uint32_t i2s_add_periph, uint32_t i2s_mode, uin
|
||||||
I2S_ADD_I2SCTL(i2s_add_periph) = (uint32_t)reg;
|
I2S_ADD_I2SCTL(i2s_add_periph) = (uint32_t)reg;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief clear SPI/I2S format error flag status
|
||||||
|
\param[in] spi_periph: SPIx(x=0,1,2,3,4,5)
|
||||||
|
\param[in] flag: SPI/I2S frame format error flag
|
||||||
|
\arg SPI_FLAG_FERR: only for SPI work in TI mode
|
||||||
|
\arg I2S_FLAG_FERR: for I2S
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void spi_i2s_format_error_clear(uint32_t spi_periph, uint32_t flag)
|
||||||
|
{
|
||||||
|
SPI_STAT(spi_periph) = (uint32_t)(~flag);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief set SPI CRC polynomial
|
||||||
|
\param[in] spi_periph: SPIx(x=0,1,2,3,4,5)
|
||||||
|
\param[in] crc_poly: CRC polynomial value
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void spi_crc_polynomial_set(uint32_t spi_periph, uint16_t crc_poly)
|
||||||
|
{
|
||||||
|
/* set SPI CRC polynomial */
|
||||||
|
SPI_CRCPOLY(spi_periph) = (uint32_t)crc_poly;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief get SPI CRC polynomial
|
||||||
|
\param[in] spi_periph: SPIx(x=0,1,2,3,4,5)
|
||||||
|
\param[out] none
|
||||||
|
\retval 16-bit CRC polynomial
|
||||||
|
*/
|
||||||
|
uint16_t spi_crc_polynomial_get(uint32_t spi_periph)
|
||||||
|
{
|
||||||
|
return ((uint16_t)SPI_CRCPOLY(spi_periph));
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief turn on SPI CRC function
|
||||||
|
\param[in] spi_periph: SPIx(x=0,1,2,3,4,5)
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void spi_crc_on(uint32_t spi_periph)
|
||||||
|
{
|
||||||
|
SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_CRCEN;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief turn off SPI CRC function
|
||||||
|
\param[in] spi_periph: SPIx(x=0,1,2,3,4,5)
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void spi_crc_off(uint32_t spi_periph)
|
||||||
|
{
|
||||||
|
SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_CRCEN);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief SPI next data is CRC value
|
||||||
|
\param[in] spi_periph: SPIx(x=0,1,2,3,4,5)
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void spi_crc_next(uint32_t spi_periph)
|
||||||
|
{
|
||||||
|
SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_CRCNT;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief get SPI CRC send value or receive value
|
||||||
|
\param[in] spi_periph: SPIx(x=0,1,2,3,4,5)
|
||||||
|
\param[in] spi_crc: SPI crc value
|
||||||
|
only one parameter can be selected which is shown as below:
|
||||||
|
\arg SPI_CRC_TX: get transmit crc value
|
||||||
|
\arg SPI_CRC_RX: get receive crc value
|
||||||
|
\param[out] none
|
||||||
|
\retval 16-bit CRC value
|
||||||
|
*/
|
||||||
|
uint16_t spi_crc_get(uint32_t spi_periph, uint8_t spi_crc)
|
||||||
|
{
|
||||||
|
if(SPI_CRC_TX == spi_crc) {
|
||||||
|
return ((uint16_t)(SPI_TCRC(spi_periph)));
|
||||||
|
} else {
|
||||||
|
return ((uint16_t)(SPI_RCRC(spi_periph)));
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief clear SPI CRC error flag status
|
||||||
|
\param[in] spi_periph: SPIx(x=0,1,2,3,4,5)
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void spi_crc_error_clear(uint32_t spi_periph)
|
||||||
|
{
|
||||||
|
SPI_STAT(spi_periph) = (uint32_t)(~SPI_FLAG_CRCERR);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief enable SPI TI mode
|
||||||
|
\param[in] spi_periph: SPIx(x=0,1,2,3,4,5)
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void spi_ti_mode_enable(uint32_t spi_periph)
|
||||||
|
{
|
||||||
|
SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_TMOD;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief disable SPI TI mode
|
||||||
|
\param[in] spi_periph: SPIx(x=0,1,2,3,4,5)
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void spi_ti_mode_disable(uint32_t spi_periph)
|
||||||
|
{
|
||||||
|
SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_TMOD);
|
||||||
|
}
|
||||||
|
|
||||||
/*!
|
/*!
|
||||||
\brief enable quad wire SPI
|
\brief enable quad wire SPI
|
||||||
\param[in] spi_periph: SPIx(only x=5)
|
\param[in] spi_periph: SPIx(only x=5)
|
||||||
\param[out] none
|
\param[out] none
|
||||||
\retval none
|
\retval none
|
||||||
*/
|
*/
|
||||||
void qspi_enable(uint32_t spi_periph)
|
void spi_quad_enable(uint32_t spi_periph)
|
||||||
{
|
{
|
||||||
SPI_QCTL(spi_periph) |= (uint32_t)SPI_QCTL_QMOD;
|
SPI_QCTL(spi_periph) |= (uint32_t)SPI_QCTL_QMOD;
|
||||||
}
|
}
|
||||||
|
|
@ -660,7 +681,7 @@ void qspi_enable(uint32_t spi_periph)
|
||||||
\param[out] none
|
\param[out] none
|
||||||
\retval none
|
\retval none
|
||||||
*/
|
*/
|
||||||
void qspi_disable(uint32_t spi_periph)
|
void spi_quad_disable(uint32_t spi_periph)
|
||||||
{
|
{
|
||||||
SPI_QCTL(spi_periph) &= (uint32_t)(~SPI_QCTL_QMOD);
|
SPI_QCTL(spi_periph) &= (uint32_t)(~SPI_QCTL_QMOD);
|
||||||
}
|
}
|
||||||
|
|
@ -671,7 +692,7 @@ void qspi_disable(uint32_t spi_periph)
|
||||||
\param[out] none
|
\param[out] none
|
||||||
\retval none
|
\retval none
|
||||||
*/
|
*/
|
||||||
void qspi_write_enable(uint32_t spi_periph)
|
void spi_quad_write_enable(uint32_t spi_periph)
|
||||||
{
|
{
|
||||||
SPI_QCTL(spi_periph) &= (uint32_t)(~SPI_QCTL_QRD);
|
SPI_QCTL(spi_periph) &= (uint32_t)(~SPI_QCTL_QRD);
|
||||||
}
|
}
|
||||||
|
|
@ -682,7 +703,7 @@ void qspi_write_enable(uint32_t spi_periph)
|
||||||
\param[out] none
|
\param[out] none
|
||||||
\retval none
|
\retval none
|
||||||
*/
|
*/
|
||||||
void qspi_read_enable(uint32_t spi_periph)
|
void spi_quad_read_enable(uint32_t spi_periph)
|
||||||
{
|
{
|
||||||
SPI_QCTL(spi_periph) |= (uint32_t)SPI_QCTL_QRD;
|
SPI_QCTL(spi_periph) |= (uint32_t)SPI_QCTL_QRD;
|
||||||
}
|
}
|
||||||
|
|
@ -693,7 +714,7 @@ void qspi_read_enable(uint32_t spi_periph)
|
||||||
\param[out] none
|
\param[out] none
|
||||||
\retval none
|
\retval none
|
||||||
*/
|
*/
|
||||||
void qspi_io23_output_enable(uint32_t spi_periph)
|
void spi_quad_io23_output_enable(uint32_t spi_periph)
|
||||||
{
|
{
|
||||||
SPI_QCTL(spi_periph) |= (uint32_t)SPI_QCTL_IO23_DRV;
|
SPI_QCTL(spi_periph) |= (uint32_t)SPI_QCTL_IO23_DRV;
|
||||||
}
|
}
|
||||||
|
|
@ -704,11 +725,42 @@ void qspi_io23_output_enable(uint32_t spi_periph)
|
||||||
\param[out] none
|
\param[out] none
|
||||||
\retval none
|
\retval none
|
||||||
*/
|
*/
|
||||||
void qspi_io23_output_disable(uint32_t spi_periph)
|
void spi_quad_io23_output_disable(uint32_t spi_periph)
|
||||||
{
|
{
|
||||||
SPI_QCTL(spi_periph) &= (uint32_t)(~SPI_QCTL_IO23_DRV);
|
SPI_QCTL(spi_periph) &= (uint32_t)(~SPI_QCTL_IO23_DRV);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief get SPI and I2S flag status
|
||||||
|
\param[in] spi_periph: SPIx(x=0,1,2,3,4,5)
|
||||||
|
\param[in] spi_i2s_flag: SPI/I2S flag status
|
||||||
|
only one parameter can be selected which are shown as below:
|
||||||
|
\arg SPI_FLAG_TBE: transmit buffer empty flag
|
||||||
|
\arg SPI_FLAG_RBNE: receive buffer not empty flag
|
||||||
|
\arg SPI_FLAG_TRANS: transmit on-going flag
|
||||||
|
\arg SPI_FLAG_RXORERR: receive overrun error flag
|
||||||
|
\arg SPI_FLAG_CONFERR: mode config error flag
|
||||||
|
\arg SPI_FLAG_CRCERR: CRC error flag
|
||||||
|
\arg SPI_FLAG_FERR: format error flag
|
||||||
|
\arg I2S_FLAG_TBE: transmit buffer empty flag
|
||||||
|
\arg I2S_FLAG_RBNE: receive buffer not empty flag
|
||||||
|
\arg I2S_FLAG_TRANS: transmit on-going flag
|
||||||
|
\arg I2S_FLAG_RXORERR: overrun error flag
|
||||||
|
\arg I2S_FLAG_TXURERR: underrun error flag
|
||||||
|
\arg I2S_FLAG_CH: channel side flag
|
||||||
|
\arg I2S_FLAG_FERR: format error flag
|
||||||
|
\param[out] none
|
||||||
|
\retval FlagStatus: SET or RESET
|
||||||
|
*/
|
||||||
|
FlagStatus spi_i2s_flag_get(uint32_t spi_periph, uint32_t flag)
|
||||||
|
{
|
||||||
|
if(SPI_STAT(spi_periph) & flag) {
|
||||||
|
return SET;
|
||||||
|
} else {
|
||||||
|
return RESET;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
/*!
|
/*!
|
||||||
\brief enable SPI and I2S interrupt
|
\brief enable SPI and I2S interrupt
|
||||||
\param[in] spi_periph: SPIx(x=0,1,2,3,4,5)
|
\param[in] spi_periph: SPIx(x=0,1,2,3,4,5)
|
||||||
|
|
@ -721,9 +773,9 @@ void qspi_io23_output_enable(uint32_t spi_periph)
|
||||||
\param[out] none
|
\param[out] none
|
||||||
\retval none
|
\retval none
|
||||||
*/
|
*/
|
||||||
void spi_i2s_interrupt_enable(uint32_t spi_periph, uint8_t spi_i2s_int)
|
void spi_i2s_interrupt_enable(uint32_t spi_periph, uint8_t interrupt)
|
||||||
{
|
{
|
||||||
switch(spi_i2s_int){
|
switch(interrupt) {
|
||||||
/* SPI/I2S transmit buffer empty interrupt */
|
/* SPI/I2S transmit buffer empty interrupt */
|
||||||
case SPI_I2S_INT_TBE:
|
case SPI_I2S_INT_TBE:
|
||||||
SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_TBEIE;
|
SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_TBEIE;
|
||||||
|
|
@ -753,9 +805,9 @@ void spi_i2s_interrupt_enable(uint32_t spi_periph, uint8_t spi_i2s_int)
|
||||||
\param[out] none
|
\param[out] none
|
||||||
\retval none
|
\retval none
|
||||||
*/
|
*/
|
||||||
void spi_i2s_interrupt_disable(uint32_t spi_periph, uint8_t spi_i2s_int)
|
void spi_i2s_interrupt_disable(uint32_t spi_periph, uint8_t interrupt)
|
||||||
{
|
{
|
||||||
switch(spi_i2s_int){
|
switch(interrupt) {
|
||||||
/* SPI/I2S transmit buffer empty interrupt */
|
/* SPI/I2S transmit buffer empty interrupt */
|
||||||
case SPI_I2S_INT_TBE :
|
case SPI_I2S_INT_TBE :
|
||||||
SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_TBEIE);
|
SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_TBEIE);
|
||||||
|
|
@ -777,6 +829,7 @@ void spi_i2s_interrupt_disable(uint32_t spi_periph, uint8_t spi_i2s_int)
|
||||||
\brief get SPI and I2S interrupt flag status
|
\brief get SPI and I2S interrupt flag status
|
||||||
\param[in] spi_periph: SPIx(x=0,1,2,3,4,5)
|
\param[in] spi_periph: SPIx(x=0,1,2,3,4,5)
|
||||||
\param[in] spi_i2s_int: SPI/I2S interrupt flag status
|
\param[in] spi_i2s_int: SPI/I2S interrupt flag status
|
||||||
|
only one parameter can be selected which are shown as below:
|
||||||
\arg SPI_I2S_INT_FLAG_TBE: transmit buffer empty interrupt flag
|
\arg SPI_I2S_INT_FLAG_TBE: transmit buffer empty interrupt flag
|
||||||
\arg SPI_I2S_INT_FLAG_RBNE: receive buffer not empty interrupt flag
|
\arg SPI_I2S_INT_FLAG_RBNE: receive buffer not empty interrupt flag
|
||||||
\arg SPI_I2S_INT_FLAG_RXORERR: overrun interrupt flag
|
\arg SPI_I2S_INT_FLAG_RXORERR: overrun interrupt flag
|
||||||
|
|
@ -787,12 +840,12 @@ void spi_i2s_interrupt_disable(uint32_t spi_periph, uint8_t spi_i2s_int)
|
||||||
\param[out] none
|
\param[out] none
|
||||||
\retval FlagStatus: SET or RESET
|
\retval FlagStatus: SET or RESET
|
||||||
*/
|
*/
|
||||||
FlagStatus spi_i2s_interrupt_flag_get(uint32_t spi_periph, uint8_t spi_i2s_int)
|
FlagStatus spi_i2s_interrupt_flag_get(uint32_t spi_periph, uint8_t interrupt)
|
||||||
{
|
{
|
||||||
uint32_t reg1 = SPI_STAT(spi_periph);
|
uint32_t reg1 = SPI_STAT(spi_periph);
|
||||||
uint32_t reg2 = SPI_CTL1(spi_periph);
|
uint32_t reg2 = SPI_CTL1(spi_periph);
|
||||||
|
|
||||||
switch(spi_i2s_int){
|
switch(interrupt) {
|
||||||
/* SPI/I2S transmit buffer empty interrupt */
|
/* SPI/I2S transmit buffer empty interrupt */
|
||||||
case SPI_I2S_INT_FLAG_TBE :
|
case SPI_I2S_INT_FLAG_TBE :
|
||||||
reg1 = reg1 & SPI_STAT_TBE;
|
reg1 = reg1 & SPI_STAT_TBE;
|
||||||
|
|
@ -838,45 +891,3 @@ FlagStatus spi_i2s_interrupt_flag_get(uint32_t spi_periph, uint8_t spi_i2s_int)
|
||||||
return RESET;
|
return RESET;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
/*!
|
|
||||||
\brief get SPI and I2S flag status
|
|
||||||
\param[in] spi_periph: SPIx(x=0,1,2,3,4,5)
|
|
||||||
\param[in] spi_i2s_flag: SPI/I2S flag status
|
|
||||||
\arg SPI_FLAG_TBE: transmit buffer empty flag
|
|
||||||
\arg SPI_FLAG_RBNE: receive buffer not empty flag
|
|
||||||
\arg SPI_FLAG_TRANS: transmit on-going flag
|
|
||||||
\arg SPI_FLAG_RXORERR: receive overrun error flag
|
|
||||||
\arg SPI_FLAG_CONFERR: mode config error flag
|
|
||||||
\arg SPI_FLAG_CRCERR: CRC error flag
|
|
||||||
\arg SPI_FLAG_FERR: format error flag
|
|
||||||
\arg I2S_FLAG_TBE: transmit buffer empty flag
|
|
||||||
\arg I2S_FLAG_RBNE: receive buffer not empty flag
|
|
||||||
\arg I2S_FLAG_TRANS: transmit on-going flag
|
|
||||||
\arg I2S_FLAG_RXORERR: overrun error flag
|
|
||||||
\arg I2S_FLAG_TXURERR: underrun error flag
|
|
||||||
\arg I2S_FLAG_CH: channel side flag
|
|
||||||
\arg I2S_FLAG_FERR: format error flag
|
|
||||||
\param[out] none
|
|
||||||
\retval FlagStatus: SET or RESET
|
|
||||||
*/
|
|
||||||
FlagStatus spi_i2s_flag_get(uint32_t spi_periph, uint32_t spi_i2s_flag)
|
|
||||||
{
|
|
||||||
if(SPI_STAT(spi_periph) & spi_i2s_flag){
|
|
||||||
return SET;
|
|
||||||
}else{
|
|
||||||
return RESET;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
\brief clear SPI CRC error flag status
|
|
||||||
\param[in] spi_periph: SPIx(x=0,1,2,3,4,5)
|
|
||||||
\param[out] none
|
|
||||||
\retval none
|
|
||||||
*/
|
|
||||||
void spi_crc_error_clear(uint32_t spi_periph)
|
|
||||||
{
|
|
||||||
SPI_STAT(spi_periph) &= (uint32_t)(~SPI_FLAG_CRCERR);
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -5,10 +5,11 @@
|
||||||
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
||||||
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
||||||
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
||||||
|
\version 2022-03-09, V3.0.0, firmware for GD32F4xx
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/*
|
/*
|
||||||
Copyright (c) 2020, GigaDevice Semiconductor Inc.
|
Copyright (c) 2022, GigaDevice Semiconductor Inc.
|
||||||
|
|
||||||
Redistribution and use in source and binary forms, with or without modification,
|
Redistribution and use in source and binary forms, with or without modification,
|
||||||
are permitted provided that the following conditions are met:
|
are permitted provided that the following conditions are met:
|
||||||
|
|
|
||||||
|
|
@ -5,10 +5,11 @@
|
||||||
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
||||||
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
||||||
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
||||||
|
\version 2022-03-09, V3.0.0, firmware for GD32F4xx
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/*
|
/*
|
||||||
Copyright (c) 2020, GigaDevice Semiconductor Inc.
|
Copyright (c) 2022, GigaDevice Semiconductor Inc.
|
||||||
|
|
||||||
Redistribution and use in source and binary forms, with or without modification,
|
Redistribution and use in source and binary forms, with or without modification,
|
||||||
are permitted provided that the following conditions are met:
|
are permitted provided that the following conditions are met:
|
||||||
|
|
@ -412,150 +413,6 @@ void timer_update_source_config(uint32_t timer_periph, uint32_t update)
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
/*!
|
|
||||||
\brief enable the TIMER interrupt
|
|
||||||
\param[in] timer_periph: please refer to the following parameters
|
|
||||||
\param[in] interrupt: timer interrupt enable source
|
|
||||||
only one parameter can be selected which is shown as below:
|
|
||||||
\arg TIMER_INT_UP: update interrupt enable, TIMERx(x=0..13)
|
|
||||||
\arg TIMER_INT_CH0: channel 0 interrupt enable, TIMERx(x=0..4,7..13)
|
|
||||||
\arg TIMER_INT_CH1: channel 1 interrupt enable, TIMERx(x=0..4,7,8,11)
|
|
||||||
\arg TIMER_INT_CH2: channel 2 interrupt enable, TIMERx(x=0..4,7)
|
|
||||||
\arg TIMER_INT_CH3: channel 3 interrupt enable , TIMERx(x=0..4,7)
|
|
||||||
\arg TIMER_INT_CMT: commutation interrupt enable, TIMERx(x=0,7)
|
|
||||||
\arg TIMER_INT_TRG: trigger interrupt enable, TIMERx(x=0..4,7,8,11)
|
|
||||||
\arg TIMER_INT_BRK: break interrupt enable, TIMERx(x=0,7)
|
|
||||||
\param[out] none
|
|
||||||
\retval none
|
|
||||||
*/
|
|
||||||
void timer_interrupt_enable(uint32_t timer_periph, uint32_t interrupt)
|
|
||||||
{
|
|
||||||
TIMER_DMAINTEN(timer_periph) |= (uint32_t) interrupt;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
\brief disable the TIMER interrupt
|
|
||||||
\param[in] timer_periph: please refer to the following parameters
|
|
||||||
\param[in] interrupt: timer interrupt source enable
|
|
||||||
only one parameter can be selected which is shown as below:
|
|
||||||
\arg TIMER_INT_UP: update interrupt enable, TIMERx(x=0..13)
|
|
||||||
\arg TIMER_INT_CH0: channel 0 interrupt enable, TIMERx(x=0..4,7..13)
|
|
||||||
\arg TIMER_INT_CH1: channel 1 interrupt enable, TIMERx(x=0..4,7,8,11)
|
|
||||||
\arg TIMER_INT_CH2: channel 2 interrupt enable, TIMERx(x=0..4,7)
|
|
||||||
\arg TIMER_INT_CH3: channel 3 interrupt enable , TIMERx(x=0..4,7)
|
|
||||||
\arg TIMER_INT_CMT: commutation interrupt enable, TIMERx(x=0,7)
|
|
||||||
\arg TIMER_INT_TRG: trigger interrupt enable, TIMERx(x=0..4,7,8,11)
|
|
||||||
\arg TIMER_INT_BRK: break interrupt enable, TIMERx(x=0,7)
|
|
||||||
\param[out] none
|
|
||||||
\retval none
|
|
||||||
*/
|
|
||||||
void timer_interrupt_disable(uint32_t timer_periph, uint32_t interrupt)
|
|
||||||
{
|
|
||||||
TIMER_DMAINTEN(timer_periph) &= (~(uint32_t)interrupt);
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
\brief get timer interrupt flag
|
|
||||||
\param[in] timer_periph: please refer to the following parameters
|
|
||||||
\param[in] interrupt: the timer interrupt bits
|
|
||||||
only one parameter can be selected which is shown as below:
|
|
||||||
\arg TIMER_INT_FLAG_UP: update interrupt flag,TIMERx(x=0..13)
|
|
||||||
\arg TIMER_INT_FLAG_CH0: channel 0 interrupt flag,TIMERx(x=0..4,7..13)
|
|
||||||
\arg TIMER_INT_FLAG_CH1: channel 1 interrupt flag,TIMERx(x=0..4,7,8,11)
|
|
||||||
\arg TIMER_INT_FLAG_CH2: channel 2 interrupt flag,TIMERx(x=0..4,7)
|
|
||||||
\arg TIMER_INT_FLAG_CH3: channel 3 interrupt flag,TIMERx(x=0..4,7)
|
|
||||||
\arg TIMER_INT_FLAG_CMT: channel commutation interrupt flag,TIMERx(x=0,7)
|
|
||||||
\arg TIMER_INT_FLAG_TRG: trigger interrupt flag,TIMERx(x=0,7,8,11)
|
|
||||||
\arg TIMER_INT_FLAG_BRK: break interrupt flag,TIMERx(x=0,7)
|
|
||||||
\param[out] none
|
|
||||||
\retval FlagStatus: SET or RESET
|
|
||||||
*/
|
|
||||||
FlagStatus timer_interrupt_flag_get(uint32_t timer_periph, uint32_t interrupt)
|
|
||||||
{
|
|
||||||
uint32_t val;
|
|
||||||
val = (TIMER_DMAINTEN(timer_periph) & interrupt);
|
|
||||||
if((RESET != (TIMER_INTF(timer_periph) & interrupt) ) && (RESET != val)){
|
|
||||||
return SET;
|
|
||||||
}else{
|
|
||||||
return RESET;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
\brief clear TIMER interrupt flag
|
|
||||||
\param[in] timer_periph: please refer to the following parameters
|
|
||||||
\param[in] interrupt: the timer interrupt bits
|
|
||||||
only one parameter can be selected which is shown as below:
|
|
||||||
\arg TIMER_INT_FLAG_UP: update interrupt flag,TIMERx(x=0..13)
|
|
||||||
\arg TIMER_INT_FLAG_CH0: channel 0 interrupt flag,TIMERx(x=0..4,7..13)
|
|
||||||
\arg TIMER_INT_FLAG_CH1: channel 1 interrupt flag,TIMERx(x=0..4,7,8,11)
|
|
||||||
\arg TIMER_INT_FLAG_CH2: channel 2 interrupt flag,TIMERx(x=0..4,7)
|
|
||||||
\arg TIMER_INT_FLAG_CH3: channel 3 interrupt flag,TIMERx(x=0..4,7)
|
|
||||||
\arg TIMER_INT_FLAG_CMT: channel commutation interrupt flag,TIMERx(x=0,7)
|
|
||||||
\arg TIMER_INT_FLAG_TRG: trigger interrupt flag,TIMERx(x=0,7,8,11)
|
|
||||||
\arg TIMER_INT_FLAG_BRK: break interrupt flag,TIMERx(x=0,7)
|
|
||||||
\param[out] none
|
|
||||||
\retval none
|
|
||||||
*/
|
|
||||||
void timer_interrupt_flag_clear(uint32_t timer_periph, uint32_t interrupt)
|
|
||||||
{
|
|
||||||
TIMER_INTF(timer_periph) = (~(uint32_t)interrupt);
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
\brief get TIMER flags
|
|
||||||
\param[in] timer_periph: please refer to the following parameters
|
|
||||||
\param[in] flag: the timer interrupt flags
|
|
||||||
only one parameter can be selected which is shown as below:
|
|
||||||
\arg TIMER_FLAG_UP: update flag,TIMERx(x=0..13)
|
|
||||||
\arg TIMER_FLAG_CH0: channel 0 flag,TIMERx(x=0..4,7..13)
|
|
||||||
\arg TIMER_FLAG_CH1: channel 1 flag,TIMERx(x=0..4,7,8,11)
|
|
||||||
\arg TIMER_FLAG_CH2: channel 2 flag,TIMERx(x=0..4,7)
|
|
||||||
\arg TIMER_FLAG_CH3: channel 3 flag,TIMERx(x=0..4,7)
|
|
||||||
\arg TIMER_FLAG_CMT: channel control update flag,TIMERx(x=0,7)
|
|
||||||
\arg TIMER_FLAG_TRG: trigger flag,TIMERx(x=0,7,8,11)
|
|
||||||
\arg TIMER_FLAG_BRK: break flag,TIMERx(x=0,7)
|
|
||||||
\arg TIMER_FLAG_CH0OF: channel 0 overcapture flag,TIMERx(x=0..4,7..11)
|
|
||||||
\arg TIMER_FLAG_CH1OF: channel 1 overcapture flag,TIMERx(x=0..4,7,8,11)
|
|
||||||
\arg TIMER_FLAG_CH2OF: channel 2 overcapture flag,TIMERx(x=0..4,7)
|
|
||||||
\arg TIMER_FLAG_CH3OF: channel 3 overcapture flag,TIMERx(x=0..4,7)
|
|
||||||
\param[out] none
|
|
||||||
\retval FlagStatus: SET or RESET
|
|
||||||
*/
|
|
||||||
FlagStatus timer_flag_get(uint32_t timer_periph, uint32_t flag)
|
|
||||||
{
|
|
||||||
if(RESET != (TIMER_INTF(timer_periph) & flag)){
|
|
||||||
return SET;
|
|
||||||
}else{
|
|
||||||
return RESET;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
\brief clear TIMER flags
|
|
||||||
\param[in] timer_periph: please refer to the following parameters
|
|
||||||
\param[in] flag: the timer interrupt flags
|
|
||||||
only one parameter can be selected which is shown as below:
|
|
||||||
\arg TIMER_FLAG_UP: update flag,TIMERx(x=0..13)
|
|
||||||
\arg TIMER_FLAG_CH0: channel 0 flag,TIMERx(x=0..4,7..13)
|
|
||||||
\arg TIMER_FLAG_CH1: channel 1 flag,TIMERx(x=0..4,7,8,11)
|
|
||||||
\arg TIMER_FLAG_CH2: channel 2 flag,TIMERx(x=0..4,7)
|
|
||||||
\arg TIMER_FLAG_CH3: channel 3 flag,TIMERx(x=0..4,7)
|
|
||||||
\arg TIMER_FLAG_CMT: channel control update flag,TIMERx(x=0,7)
|
|
||||||
\arg TIMER_FLAG_TRG: trigger flag,TIMERx(x=0,7,8,11)
|
|
||||||
\arg TIMER_FLAG_BRK: break flag,TIMERx(x=0,7)
|
|
||||||
\arg TIMER_FLAG_CH0OF: channel 0 overcapture flag,TIMERx(x=0..4,7..11)
|
|
||||||
\arg TIMER_FLAG_CH1OF: channel 1 overcapture flag,TIMERx(x=0..4,7,8,11)
|
|
||||||
\arg TIMER_FLAG_CH2OF: channel 2 overcapture flag,TIMERx(x=0..4,7)
|
|
||||||
\arg TIMER_FLAG_CH3OF: channel 3 overcapture flag,TIMERx(x=0..4,7)
|
|
||||||
\param[out] none
|
|
||||||
\retval none
|
|
||||||
*/
|
|
||||||
void timer_flag_clear(uint32_t timer_periph, uint32_t flag)
|
|
||||||
{
|
|
||||||
TIMER_INTF(timer_periph) = (~(uint32_t)flag);
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
/*!
|
||||||
\brief enable the TIMER DMA
|
\brief enable the TIMER DMA
|
||||||
\param[in] timer_periph: please refer to the following parameters
|
\param[in] timer_periph: please refer to the following parameters
|
||||||
|
|
@ -676,7 +533,7 @@ void timer_event_software_generate(uint32_t timer_periph, uint16_t event)
|
||||||
}
|
}
|
||||||
|
|
||||||
/*!
|
/*!
|
||||||
\brief initialize TIMER break parameter struct with a default value
|
\brief initialize TIMER break parameter struct
|
||||||
\param[in] breakpara: TIMER break parameter struct
|
\param[in] breakpara: TIMER break parameter struct
|
||||||
\param[out] none
|
\param[out] none
|
||||||
\retval none
|
\retval none
|
||||||
|
|
@ -1355,7 +1212,7 @@ void timer_channel_complementary_output_state_config(uint32_t timer_periph, uint
|
||||||
}
|
}
|
||||||
|
|
||||||
/*!
|
/*!
|
||||||
\brief initialize TIMER channel input parameter struct with a default value
|
\brief initialize TIMER channel input parameter struct
|
||||||
\param[in] icpara: TIMER channel intput parameter struct
|
\param[in] icpara: TIMER channel intput parameter struct
|
||||||
\param[out] none
|
\param[out] none
|
||||||
\retval none
|
\retval none
|
||||||
|
|
@ -1742,9 +1599,9 @@ void timer_master_output_trigger_source_select(uint32_t timer_periph, uint32_t o
|
||||||
\param[in] slavemode:
|
\param[in] slavemode:
|
||||||
only one parameter can be selected which is shown as below:
|
only one parameter can be selected which is shown as below:
|
||||||
\arg TIMER_SLAVE_MODE_DISABLE: slave mode disable(TIMERx(x=0..4,7,8,11))
|
\arg TIMER_SLAVE_MODE_DISABLE: slave mode disable(TIMERx(x=0..4,7,8,11))
|
||||||
\arg TIMER_ENCODER_MODE0: encoder mode 0(TIMERx(x=0..4,7))
|
\arg TIMER_QUAD_DECODER_MODE0: quadrature decoder mode 0(TIMERx(x=0..4,7))
|
||||||
\arg TIMER_ENCODER_MODE1: encoder mode 1(TIMERx(x=0..4,7))
|
\arg TIMER_QUAD_DECODER_MODE1: quadrature decoder mode 1(TIMERx(x=0..4,7))
|
||||||
\arg TIMER_ENCODER_MODE2: encoder mode 2(TIMERx(x=0..4,7))
|
\arg TIMER_QUAD_DECODER_MODE2: quadrature decoder mode 2(TIMERx(x=0..4,7))
|
||||||
\arg TIMER_SLAVE_MODE_RESTART: restart mode(TIMERx(x=0..4,7,8,11))
|
\arg TIMER_SLAVE_MODE_RESTART: restart mode(TIMERx(x=0..4,7,8,11))
|
||||||
\arg TIMER_SLAVE_MODE_PAUSE: pause mode(TIMERx(x=0..4,7,8,11))
|
\arg TIMER_SLAVE_MODE_PAUSE: pause mode(TIMERx(x=0..4,7,8,11))
|
||||||
\arg TIMER_SLAVE_MODE_EVENT: event mode(TIMERx(x=0..4,7,8,11))
|
\arg TIMER_SLAVE_MODE_EVENT: event mode(TIMERx(x=0..4,7,8,11))
|
||||||
|
|
@ -1808,12 +1665,12 @@ void timer_external_trigger_config(uint32_t timer_periph, uint32_t extprescaler,
|
||||||
|
|
||||||
/*!
|
/*!
|
||||||
\brief configure TIMER quadrature decoder mode
|
\brief configure TIMER quadrature decoder mode
|
||||||
\param[in] timer_periph: TIMERx(x=0..4,7,8,11)
|
\param[in] timer_periph: TIMERx(x=0..4,7)
|
||||||
\param[in] decomode:
|
\param[in] decomode:
|
||||||
only one parameter can be selected which is shown as below:
|
only one parameter can be selected which is shown as below:
|
||||||
\arg TIMER_ENCODER_MODE0: counter counts on CI0FE0 edge depending on CI1FE1 level
|
\arg TIMER_QUAD_DECODER_MODE0: counter counts on CI0FE0 edge depending on CI1FE1 level
|
||||||
\arg TIMER_ENCODER_MODE1: counter counts on CI1FE1 edge depending on CI0FE0 level
|
\arg TIMER_QUAD_DECODER_MODE1: counter counts on CI1FE1 edge depending on CI0FE0 level
|
||||||
\arg TIMER_ENCODER_MODE2: counter counts on both CI0FE0 and CI1FE1 edges depending on the level of the other input
|
\arg TIMER_QUAD_DECODER_MODE2: counter counts on both CI0FE0 and CI1FE1 edges depending on the level of the other input
|
||||||
\param[in] ic0polarity:
|
\param[in] ic0polarity:
|
||||||
only one parameter can be selected which is shown as below:
|
only one parameter can be selected which is shown as below:
|
||||||
\arg TIMER_IC_POLARITY_RISING: capture rising edge
|
\arg TIMER_IC_POLARITY_RISING: capture rising edge
|
||||||
|
|
@ -2061,3 +1918,147 @@ void timer_output_value_selection_config(uint32_t timer_periph, uint16_t outsel)
|
||||||
/* illegal parameters */
|
/* illegal parameters */
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief get TIMER flags
|
||||||
|
\param[in] timer_periph: please refer to the following parameters
|
||||||
|
\param[in] flag: the timer interrupt flags
|
||||||
|
only one parameter can be selected which is shown as below:
|
||||||
|
\arg TIMER_FLAG_UP: update flag,TIMERx(x=0..13)
|
||||||
|
\arg TIMER_FLAG_CH0: channel 0 flag,TIMERx(x=0..4,7..13)
|
||||||
|
\arg TIMER_FLAG_CH1: channel 1 flag,TIMERx(x=0..4,7,8,11)
|
||||||
|
\arg TIMER_FLAG_CH2: channel 2 flag,TIMERx(x=0..4,7)
|
||||||
|
\arg TIMER_FLAG_CH3: channel 3 flag,TIMERx(x=0..4,7)
|
||||||
|
\arg TIMER_FLAG_CMT: channel control update flag,TIMERx(x=0,7)
|
||||||
|
\arg TIMER_FLAG_TRG: trigger flag,TIMERx(x=0,7,8,11)
|
||||||
|
\arg TIMER_FLAG_BRK: break flag,TIMERx(x=0,7)
|
||||||
|
\arg TIMER_FLAG_CH0O: channel 0 overcapture flag,TIMERx(x=0..4,7..11)
|
||||||
|
\arg TIMER_FLAG_CH1O: channel 1 overcapture flag,TIMERx(x=0..4,7,8,11)
|
||||||
|
\arg TIMER_FLAG_CH2O: channel 2 overcapture flag,TIMERx(x=0..4,7)
|
||||||
|
\arg TIMER_FLAG_CH3O: channel 3 overcapture flag,TIMERx(x=0..4,7)
|
||||||
|
\param[out] none
|
||||||
|
\retval FlagStatus: SET or RESET
|
||||||
|
*/
|
||||||
|
FlagStatus timer_flag_get(uint32_t timer_periph, uint32_t flag)
|
||||||
|
{
|
||||||
|
if(RESET != (TIMER_INTF(timer_periph) & flag)) {
|
||||||
|
return SET;
|
||||||
|
} else {
|
||||||
|
return RESET;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief clear TIMER flags
|
||||||
|
\param[in] timer_periph: please refer to the following parameters
|
||||||
|
\param[in] flag: the timer interrupt flags
|
||||||
|
only one parameter can be selected which is shown as below:
|
||||||
|
\arg TIMER_FLAG_UP: update flag,TIMERx(x=0..13)
|
||||||
|
\arg TIMER_FLAG_CH0: channel 0 flag,TIMERx(x=0..4,7..13)
|
||||||
|
\arg TIMER_FLAG_CH1: channel 1 flag,TIMERx(x=0..4,7,8,11)
|
||||||
|
\arg TIMER_FLAG_CH2: channel 2 flag,TIMERx(x=0..4,7)
|
||||||
|
\arg TIMER_FLAG_CH3: channel 3 flag,TIMERx(x=0..4,7)
|
||||||
|
\arg TIMER_FLAG_CMT: channel control update flag,TIMERx(x=0,7)
|
||||||
|
\arg TIMER_FLAG_TRG: trigger flag,TIMERx(x=0,7,8,11)
|
||||||
|
\arg TIMER_FLAG_BRK: break flag,TIMERx(x=0,7)
|
||||||
|
\arg TIMER_FLAG_CH0O: channel 0 overcapture flag,TIMERx(x=0..4,7..11)
|
||||||
|
\arg TIMER_FLAG_CH1O: channel 1 overcapture flag,TIMERx(x=0..4,7,8,11)
|
||||||
|
\arg TIMER_FLAG_CH2O: channel 2 overcapture flag,TIMERx(x=0..4,7)
|
||||||
|
\arg TIMER_FLAG_CH3O: channel 3 overcapture flag,TIMERx(x=0..4,7)
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void timer_flag_clear(uint32_t timer_periph, uint32_t flag)
|
||||||
|
{
|
||||||
|
TIMER_INTF(timer_periph) = (~(uint32_t)flag);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief enable the TIMER interrupt
|
||||||
|
\param[in] timer_periph: please refer to the following parameters
|
||||||
|
\param[in] interrupt: timer interrupt enable source
|
||||||
|
only one parameter can be selected which is shown as below:
|
||||||
|
\arg TIMER_INT_UP: update interrupt enable, TIMERx(x=0..13)
|
||||||
|
\arg TIMER_INT_CH0: channel 0 interrupt enable, TIMERx(x=0..4,7..13)
|
||||||
|
\arg TIMER_INT_CH1: channel 1 interrupt enable, TIMERx(x=0..4,7,8,11)
|
||||||
|
\arg TIMER_INT_CH2: channel 2 interrupt enable, TIMERx(x=0..4,7)
|
||||||
|
\arg TIMER_INT_CH3: channel 3 interrupt enable , TIMERx(x=0..4,7)
|
||||||
|
\arg TIMER_INT_CMT: commutation interrupt enable, TIMERx(x=0,7)
|
||||||
|
\arg TIMER_INT_TRG: trigger interrupt enable, TIMERx(x=0..4,7,8,11)
|
||||||
|
\arg TIMER_INT_BRK: break interrupt enable, TIMERx(x=0,7)
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void timer_interrupt_enable(uint32_t timer_periph, uint32_t interrupt)
|
||||||
|
{
|
||||||
|
TIMER_DMAINTEN(timer_periph) |= (uint32_t) interrupt;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief disable the TIMER interrupt
|
||||||
|
\param[in] timer_periph: please refer to the following parameters
|
||||||
|
\param[in] interrupt: timer interrupt source enable
|
||||||
|
only one parameter can be selected which is shown as below:
|
||||||
|
\arg TIMER_INT_UP: update interrupt enable, TIMERx(x=0..13)
|
||||||
|
\arg TIMER_INT_CH0: channel 0 interrupt enable, TIMERx(x=0..4,7..13)
|
||||||
|
\arg TIMER_INT_CH1: channel 1 interrupt enable, TIMERx(x=0..4,7,8,11)
|
||||||
|
\arg TIMER_INT_CH2: channel 2 interrupt enable, TIMERx(x=0..4,7)
|
||||||
|
\arg TIMER_INT_CH3: channel 3 interrupt enable , TIMERx(x=0..4,7)
|
||||||
|
\arg TIMER_INT_CMT: commutation interrupt enable, TIMERx(x=0,7)
|
||||||
|
\arg TIMER_INT_TRG: trigger interrupt enable, TIMERx(x=0..4,7,8,11)
|
||||||
|
\arg TIMER_INT_BRK: break interrupt enable, TIMERx(x=0,7)
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void timer_interrupt_disable(uint32_t timer_periph, uint32_t interrupt)
|
||||||
|
{
|
||||||
|
TIMER_DMAINTEN(timer_periph) &= (~(uint32_t)interrupt);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief get timer interrupt flag
|
||||||
|
\param[in] timer_periph: please refer to the following parameters
|
||||||
|
\param[in] interrupt: the timer interrupt bits
|
||||||
|
only one parameter can be selected which is shown as below:
|
||||||
|
\arg TIMER_INT_FLAG_UP: update interrupt flag,TIMERx(x=0..13)
|
||||||
|
\arg TIMER_INT_FLAG_CH0: channel 0 interrupt flag,TIMERx(x=0..4,7..13)
|
||||||
|
\arg TIMER_INT_FLAG_CH1: channel 1 interrupt flag,TIMERx(x=0..4,7,8,11)
|
||||||
|
\arg TIMER_INT_FLAG_CH2: channel 2 interrupt flag,TIMERx(x=0..4,7)
|
||||||
|
\arg TIMER_INT_FLAG_CH3: channel 3 interrupt flag,TIMERx(x=0..4,7)
|
||||||
|
\arg TIMER_INT_FLAG_CMT: channel commutation interrupt flag,TIMERx(x=0,7)
|
||||||
|
\arg TIMER_INT_FLAG_TRG: trigger interrupt flag,TIMERx(x=0,7,8,11)
|
||||||
|
\arg TIMER_INT_FLAG_BRK: break interrupt flag,TIMERx(x=0,7)
|
||||||
|
\param[out] none
|
||||||
|
\retval FlagStatus: SET or RESET
|
||||||
|
*/
|
||||||
|
FlagStatus timer_interrupt_flag_get(uint32_t timer_periph, uint32_t interrupt)
|
||||||
|
{
|
||||||
|
uint32_t val;
|
||||||
|
val = (TIMER_DMAINTEN(timer_periph) & interrupt);
|
||||||
|
if((RESET != (TIMER_INTF(timer_periph) & interrupt)) && (RESET != val)) {
|
||||||
|
return SET;
|
||||||
|
} else {
|
||||||
|
return RESET;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief clear TIMER interrupt flag
|
||||||
|
\param[in] timer_periph: please refer to the following parameters
|
||||||
|
\param[in] interrupt: the timer interrupt bits
|
||||||
|
only one parameter can be selected which is shown as below:
|
||||||
|
\arg TIMER_INT_FLAG_UP: update interrupt flag,TIMERx(x=0..13)
|
||||||
|
\arg TIMER_INT_FLAG_CH0: channel 0 interrupt flag,TIMERx(x=0..4,7..13)
|
||||||
|
\arg TIMER_INT_FLAG_CH1: channel 1 interrupt flag,TIMERx(x=0..4,7,8,11)
|
||||||
|
\arg TIMER_INT_FLAG_CH2: channel 2 interrupt flag,TIMERx(x=0..4,7)
|
||||||
|
\arg TIMER_INT_FLAG_CH3: channel 3 interrupt flag,TIMERx(x=0..4,7)
|
||||||
|
\arg TIMER_INT_FLAG_CMT: channel commutation interrupt flag,TIMERx(x=0,7)
|
||||||
|
\arg TIMER_INT_FLAG_TRG: trigger interrupt flag,TIMERx(x=0,7,8,11)
|
||||||
|
\arg TIMER_INT_FLAG_BRK: break interrupt flag,TIMERx(x=0,7)
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void timer_interrupt_flag_clear(uint32_t timer_periph, uint32_t interrupt)
|
||||||
|
{
|
||||||
|
TIMER_INTF(timer_periph) = (~(uint32_t)interrupt);
|
||||||
|
}
|
||||||
|
|
|
||||||
|
|
@ -5,10 +5,11 @@
|
||||||
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
||||||
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
||||||
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
||||||
|
\version 2022-03-09, V3.0.0, firmware for GD32F4xx
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/*
|
/*
|
||||||
Copyright (c) 2020, GigaDevice Semiconductor Inc.
|
Copyright (c) 2022, GigaDevice Semiconductor Inc.
|
||||||
|
|
||||||
Redistribution and use in source and binary forms, with or without modification,
|
Redistribution and use in source and binary forms, with or without modification,
|
||||||
are permitted provided that the following conditions are met:
|
are permitted provided that the following conditions are met:
|
||||||
|
|
@ -385,7 +386,6 @@ void tli_lut_struct_para_init(tli_layer_lut_parameter_struct *lut_struct)
|
||||||
*/
|
*/
|
||||||
void tli_lut_init(uint32_t layerx, tli_layer_lut_parameter_struct *lut_struct)
|
void tli_lut_init(uint32_t layerx, tli_layer_lut_parameter_struct *lut_struct)
|
||||||
{
|
{
|
||||||
TLI_LxLUT(layerx) &= ~(TLI_LxLUT_TB|TLI_LxLUT_TG|TLI_LxLUT_TR|TLI_LxLUT_TADD);
|
|
||||||
TLI_LxLUT(layerx) = (uint32_t)(((uint32_t)lut_struct->layer_lut_channel_blue) | ((uint32_t)lut_struct->layer_lut_channel_green << 8U)
|
TLI_LxLUT(layerx) = (uint32_t)(((uint32_t)lut_struct->layer_lut_channel_blue) | ((uint32_t)lut_struct->layer_lut_channel_green << 8U)
|
||||||
| ((uint32_t)lut_struct->layer_lut_channel_red << 16U
|
| ((uint32_t)lut_struct->layer_lut_channel_red << 16U
|
||||||
| ((uint32_t)lut_struct->layer_table_addr << 24U)));
|
| ((uint32_t)lut_struct->layer_table_addr << 24U)));
|
||||||
|
|
|
||||||
|
|
@ -5,10 +5,11 @@
|
||||||
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
||||||
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
||||||
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
||||||
|
\version 2022-03-09, V3.0.0, firmware for GD32F4xx
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/*
|
/*
|
||||||
Copyright (c) 2020, GigaDevice Semiconductor Inc.
|
Copyright (c) 2022, GigaDevice Semiconductor Inc.
|
||||||
|
|
||||||
Redistribution and use in source and binary forms, with or without modification,
|
Redistribution and use in source and binary forms, with or without modification,
|
||||||
are permitted provided that the following conditions are met:
|
are permitted provided that the following conditions are met:
|
||||||
|
|
@ -37,7 +38,7 @@ OF SUCH DAMAGE.
|
||||||
#include "gd32f4xx_trng.h"
|
#include "gd32f4xx_trng.h"
|
||||||
|
|
||||||
/*!
|
/*!
|
||||||
\brief deinitialize the TRNG
|
\brief reset TRNG
|
||||||
\param[in] none
|
\param[in] none
|
||||||
\param[out] none
|
\param[out] none
|
||||||
\retval none
|
\retval none
|
||||||
|
|
@ -49,7 +50,7 @@ void trng_deinit(void)
|
||||||
}
|
}
|
||||||
|
|
||||||
/*!
|
/*!
|
||||||
\brief enable the TRNG interface
|
\brief enable TRNG
|
||||||
\param[in] none
|
\param[in] none
|
||||||
\param[out] none
|
\param[out] none
|
||||||
\retval none
|
\retval none
|
||||||
|
|
@ -60,7 +61,7 @@ void trng_enable(void)
|
||||||
}
|
}
|
||||||
|
|
||||||
/*!
|
/*!
|
||||||
\brief disable the TRNG interface
|
\brief disable TRNG
|
||||||
\param[in] none
|
\param[in] none
|
||||||
\param[out] none
|
\param[out] none
|
||||||
\retval none
|
\retval none
|
||||||
|
|
@ -74,7 +75,7 @@ void trng_disable(void)
|
||||||
\brief get the true random data
|
\brief get the true random data
|
||||||
\param[in] none
|
\param[in] none
|
||||||
\param[out] none
|
\param[out] none
|
||||||
\retval the generated random data
|
\retval uint32_t: 0x0-0xFFFFFFFF
|
||||||
*/
|
*/
|
||||||
uint32_t trng_get_true_random_data(void)
|
uint32_t trng_get_true_random_data(void)
|
||||||
{
|
{
|
||||||
|
|
@ -82,34 +83,34 @@ uint32_t trng_get_true_random_data(void)
|
||||||
}
|
}
|
||||||
|
|
||||||
/*!
|
/*!
|
||||||
\brief enable the TRNG interrupt
|
\brief enable TRNG interrupt
|
||||||
\param[in] none
|
\param[in] none
|
||||||
\param[out] none
|
\param[out] none
|
||||||
\retval none
|
\retval none
|
||||||
*/
|
*/
|
||||||
void trng_interrupt_enable(void)
|
void trng_interrupt_enable(void)
|
||||||
{
|
{
|
||||||
TRNG_CTL |= TRNG_CTL_IE;
|
TRNG_CTL |= TRNG_CTL_TRNGIE;
|
||||||
}
|
}
|
||||||
|
|
||||||
/*!
|
/*!
|
||||||
\brief disable the TRNG interrupt
|
\brief disable TRNG interrupt
|
||||||
\param[in] none
|
\param[in] none
|
||||||
\param[out] none
|
\param[out] none
|
||||||
\retval none
|
\retval none
|
||||||
*/
|
*/
|
||||||
void trng_interrupt_disable(void)
|
void trng_interrupt_disable(void)
|
||||||
{
|
{
|
||||||
TRNG_CTL &= ~TRNG_CTL_IE;
|
TRNG_CTL &= ~TRNG_CTL_TRNGIE;
|
||||||
}
|
}
|
||||||
|
|
||||||
/*!
|
/*!
|
||||||
\brief get the trng status flags
|
\brief get TRNG flag status
|
||||||
\param[in] flag: trng status flag, refer to trng_flag_enum
|
\param[in] flag: TRNG flag
|
||||||
only one parameter can be selected which is shown as below:
|
only one parameter can be selected which is shown as below:
|
||||||
\arg TRNG_FLAG_DRDY: Random Data ready status
|
\arg TRNG_FLAG_DRDY: random Data ready status
|
||||||
\arg TRNG_FLAG_CECS: Clock error current status
|
\arg TRNG_FLAG_CECS: clock error current status
|
||||||
\arg TRNG_FLAG_SECS: Seed error current status
|
\arg TRNG_FLAG_SECS: seed error current status
|
||||||
\param[out] none
|
\param[out] none
|
||||||
\retval FlagStatus: SET or RESET
|
\retval FlagStatus: SET or RESET
|
||||||
*/
|
*/
|
||||||
|
|
@ -123,11 +124,11 @@ FlagStatus trng_flag_get(trng_flag_enum flag)
|
||||||
}
|
}
|
||||||
|
|
||||||
/*!
|
/*!
|
||||||
\brief get the trng interrupt flags
|
\brief get TRNG interrupt flag status
|
||||||
\param[in] int_flag: trng interrupt flag, refer to trng_int_flag_enum
|
\param[in] int_flag: TRNG interrupt flag
|
||||||
only one parameter can be selected which is shown as below:
|
only one parameter can be selected which is shown as below:
|
||||||
\arg TRNG_INT_FLAG_CEIF: clock error interrupt flag
|
\arg TRNG_INT_FLAG_CEIF: clock error interrupt flag
|
||||||
\arg TRNG_INT_FLAG_SEIF: Seed error interrupt flag
|
\arg TRNG_INT_FLAG_SEIF: seed error interrupt flag
|
||||||
\param[out] none
|
\param[out] none
|
||||||
\retval FlagStatus: SET or RESET
|
\retval FlagStatus: SET or RESET
|
||||||
*/
|
*/
|
||||||
|
|
@ -141,11 +142,11 @@ FlagStatus trng_interrupt_flag_get(trng_int_flag_enum int_flag)
|
||||||
}
|
}
|
||||||
|
|
||||||
/*!
|
/*!
|
||||||
\brief clear the trng interrupt flags
|
\brief clear TRNG interrupt flag status
|
||||||
\param[in] int_flag: trng interrupt flag, refer to trng_int_flag_enum
|
\param[in] int_flag: TRNG interrupt flag
|
||||||
only one parameter can be selected which is shown as below:
|
only one parameter can be selected which is shown as below:
|
||||||
\arg TRNG_INT_FLAG_CEIF: clock error interrupt flag
|
\arg TRNG_INT_FLAG_CEIF: clock error interrupt flag
|
||||||
\arg TRNG_INT_FLAG_SEIF: Seed error interrupt flag
|
\arg TRNG_INT_FLAG_SEIF: seed error interrupt flag
|
||||||
\param[out] none
|
\param[out] none
|
||||||
\retval none
|
\retval none
|
||||||
*/
|
*/
|
||||||
|
|
|
||||||
|
|
@ -5,10 +5,11 @@
|
||||||
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
||||||
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
||||||
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
||||||
|
\version 2022-03-09, V3.0.0, firmware for GD32F4xx
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/*
|
/*
|
||||||
Copyright (c) 2020, GigaDevice Semiconductor Inc.
|
Copyright (c) 2022, GigaDevice Semiconductor Inc.
|
||||||
|
|
||||||
Redistribution and use in source and binary forms, with or without modification,
|
Redistribution and use in source and binary forms, with or without modification,
|
||||||
are permitted provided that the following conditions are met:
|
are permitted provided that the following conditions are met:
|
||||||
|
|
@ -34,7 +35,6 @@ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSI
|
||||||
OF SUCH DAMAGE.
|
OF SUCH DAMAGE.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
|
|
||||||
#include "gd32f4xx_usart.h"
|
#include "gd32f4xx_usart.h"
|
||||||
|
|
||||||
/* USART register bit offset */
|
/* USART register bit offset */
|
||||||
|
|
@ -399,9 +399,9 @@ void usart_receiver_timeout_threshold_config(uint32_t usart_periph, uint32_t rti
|
||||||
\param[out] none
|
\param[out] none
|
||||||
\retval none
|
\retval none
|
||||||
*/
|
*/
|
||||||
void usart_data_transmit(uint32_t usart_periph, uint32_t data)
|
void usart_data_transmit(uint32_t usart_periph, uint16_t data)
|
||||||
{
|
{
|
||||||
USART_DATA(usart_periph) = ((uint16_t)USART_DATA_DATA & data);
|
USART_DATA(usart_periph) = USART_DATA_DATA & (uint32_t)data;
|
||||||
}
|
}
|
||||||
|
|
||||||
/*!
|
/*!
|
||||||
|
|
@ -425,7 +425,7 @@ uint16_t usart_data_receive(uint32_t usart_periph)
|
||||||
void usart_address_config(uint32_t usart_periph, uint8_t addr)
|
void usart_address_config(uint32_t usart_periph, uint8_t addr)
|
||||||
{
|
{
|
||||||
USART_CTL1(usart_periph) &= ~(USART_CTL1_ADDR);
|
USART_CTL1(usart_periph) &= ~(USART_CTL1_ADDR);
|
||||||
USART_CTL1(usart_periph) |= (USART_CTL1_ADDR & addr);
|
USART_CTL1(usart_periph) |= (USART_CTL1_ADDR & (uint32_t)addr);
|
||||||
}
|
}
|
||||||
|
|
||||||
/*!
|
/*!
|
||||||
|
|
@ -579,15 +579,8 @@ void usart_synchronous_clock_disable(uint32_t usart_periph)
|
||||||
*/
|
*/
|
||||||
void usart_synchronous_clock_config(uint32_t usart_periph, uint32_t clen, uint32_t cph, uint32_t cpl)
|
void usart_synchronous_clock_config(uint32_t usart_periph, uint32_t clen, uint32_t cph, uint32_t cpl)
|
||||||
{
|
{
|
||||||
uint32_t ctl = 0U;
|
USART_CTL1(usart_periph) &= ~(USART_CTL1_CLEN | USART_CTL1_CPH | USART_CTL1_CPL);
|
||||||
|
USART_CTL1(usart_periph) = (USART_CTL1_CLEN & clen) | (USART_CTL1_CPH & cph) | (USART_CTL1_CPL & cpl);
|
||||||
/* read USART_CTL1 register */
|
|
||||||
ctl = USART_CTL1(usart_periph);
|
|
||||||
ctl &= ~(USART_CTL1_CLEN | USART_CTL1_CPH | USART_CTL1_CPL);
|
|
||||||
/* set CK length, CK phase, CK polarity */
|
|
||||||
ctl |= (USART_CTL1_CLEN & clen) | (USART_CTL1_CPH & cph) | (USART_CTL1_CPL & cpl);
|
|
||||||
|
|
||||||
USART_CTL1(usart_periph) = ctl;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
/*!
|
/*!
|
||||||
|
|
@ -597,10 +590,10 @@ void usart_synchronous_clock_config(uint32_t usart_periph, uint32_t clen, uint32
|
||||||
\param[out] none
|
\param[out] none
|
||||||
\retval none
|
\retval none
|
||||||
*/
|
*/
|
||||||
void usart_guard_time_config(uint32_t usart_periph,uint32_t guat)
|
void usart_guard_time_config(uint32_t usart_periph, uint8_t guat)
|
||||||
{
|
{
|
||||||
USART_GP(usart_periph) &= ~(USART_GP_GUAT);
|
USART_GP(usart_periph) &= ~(USART_GP_GUAT);
|
||||||
USART_GP(usart_periph) |= (USART_GP_GUAT & ((guat)<<GP_GUAT_OFFSET));
|
USART_GP(usart_periph) |= (USART_GP_GUAT & ((uint32_t)guat << GP_GUAT_OFFSET));
|
||||||
}
|
}
|
||||||
|
|
||||||
/*!
|
/*!
|
||||||
|
|
@ -654,10 +647,10 @@ void usart_smartcard_mode_nack_disable(uint32_t usart_periph)
|
||||||
\param[out] none
|
\param[out] none
|
||||||
\retval none
|
\retval none
|
||||||
*/
|
*/
|
||||||
void usart_smartcard_autoretry_config(uint32_t usart_periph, uint32_t scrtnum)
|
void usart_smartcard_autoretry_config(uint32_t usart_periph, uint8_t scrtnum)
|
||||||
{
|
{
|
||||||
USART_CTL3(usart_periph) &= ~(USART_CTL3_SCRTNUM);
|
USART_CTL3(usart_periph) &= ~(USART_CTL3_SCRTNUM);
|
||||||
USART_CTL3(usart_periph) |= (USART_CTL3_SCRTNUM & ((scrtnum)<<CTL3_SCRTNUM_OFFSET));
|
USART_CTL3(usart_periph) |= (USART_CTL3_SCRTNUM & ((uint32_t)scrtnum << CTL3_SCRTNUM_OFFSET));
|
||||||
}
|
}
|
||||||
|
|
||||||
/*!
|
/*!
|
||||||
|
|
@ -667,10 +660,10 @@ void usart_smartcard_autoretry_config(uint32_t usart_periph, uint32_t scrtnum)
|
||||||
\param[out] none
|
\param[out] none
|
||||||
\retval none
|
\retval none
|
||||||
*/
|
*/
|
||||||
void usart_block_length_config(uint32_t usart_periph, uint32_t bl)
|
void usart_block_length_config(uint32_t usart_periph, uint8_t bl)
|
||||||
{
|
{
|
||||||
USART_RT(usart_periph) &= ~(USART_RT_BL);
|
USART_RT(usart_periph) &= ~(USART_RT_BL);
|
||||||
USART_RT(usart_periph) |= (USART_RT_BL & ((bl)<<RT_BL_OFFSET));
|
USART_RT(usart_periph) |= (USART_RT_BL & ((uint32_t)bl << RT_BL_OFFSET));
|
||||||
}
|
}
|
||||||
|
|
||||||
/*!
|
/*!
|
||||||
|
|
@ -705,7 +698,7 @@ void usart_irda_mode_disable(uint32_t usart_periph)
|
||||||
void usart_prescaler_config(uint32_t usart_periph, uint8_t psc)
|
void usart_prescaler_config(uint32_t usart_periph, uint8_t psc)
|
||||||
{
|
{
|
||||||
USART_GP(usart_periph) &= ~(USART_GP_PSC);
|
USART_GP(usart_periph) &= ~(USART_GP_PSC);
|
||||||
USART_GP(usart_periph) |= psc;
|
USART_GP(usart_periph) |= (uint32_t)psc;
|
||||||
}
|
}
|
||||||
|
|
||||||
/*!
|
/*!
|
||||||
|
|
@ -736,15 +729,9 @@ void usart_irda_lowpower_config(uint32_t usart_periph, uint32_t irlp)
|
||||||
*/
|
*/
|
||||||
void usart_hardware_flow_rts_config(uint32_t usart_periph, uint32_t rtsconfig)
|
void usart_hardware_flow_rts_config(uint32_t usart_periph, uint32_t rtsconfig)
|
||||||
{
|
{
|
||||||
uint32_t ctl = 0U;
|
USART_CTL2(usart_periph) &= ~(USART_CTL2_RTSEN);
|
||||||
|
USART_CTL2(usart_periph) |= (USART_CTL2_RTSEN & rtsconfig);
|
||||||
ctl = USART_CTL2(usart_periph);
|
|
||||||
ctl &= ~USART_CTL2_RTSEN;
|
|
||||||
ctl |= rtsconfig;
|
|
||||||
/* configure RTS */
|
|
||||||
USART_CTL2(usart_periph) = ctl;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
/*!
|
/*!
|
||||||
\brief configure hardware flow control CTS
|
\brief configure hardware flow control CTS
|
||||||
\param[in] usart_periph: USARTx(x=0,1,2,5)
|
\param[in] usart_periph: USARTx(x=0,1,2,5)
|
||||||
|
|
@ -757,13 +744,8 @@ void usart_hardware_flow_rts_config(uint32_t usart_periph, uint32_t rtsconfig)
|
||||||
*/
|
*/
|
||||||
void usart_hardware_flow_cts_config(uint32_t usart_periph, uint32_t ctsconfig)
|
void usart_hardware_flow_cts_config(uint32_t usart_periph, uint32_t ctsconfig)
|
||||||
{
|
{
|
||||||
uint32_t ctl = 0U;
|
USART_CTL2(usart_periph) &= ~(USART_CTL2_CTSEN);
|
||||||
|
USART_CTL2(usart_periph) |= (USART_CTL2_CTSEN & ctsconfig);
|
||||||
ctl = USART_CTL2(usart_periph);
|
|
||||||
ctl &= ~USART_CTL2_CTSEN;
|
|
||||||
ctl |= ctsconfig;
|
|
||||||
/* configure CTS */
|
|
||||||
USART_CTL2(usart_periph) = ctl;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
/*!
|
/*!
|
||||||
|
|
@ -819,20 +801,15 @@ void usart_hardware_flow_coherence_config(uint32_t usart_periph, uint32_t hcm)
|
||||||
\param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7)
|
\param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7)
|
||||||
\param[in] dmacmd: enable or disable DMA for reception
|
\param[in] dmacmd: enable or disable DMA for reception
|
||||||
only one parameter can be selected which is shown as below:
|
only one parameter can be selected which is shown as below:
|
||||||
\arg USART_DENR_ENABLE: DMA enable for reception
|
\arg USART_RECEIVE_DMA_ENABLE: DMA enable for reception
|
||||||
\arg USART_DENR_DISABLE: DMA disable for reception
|
\arg USART_RECEIVE_DMA_DISABLE: DMA disable for reception
|
||||||
\param[out] none
|
\param[out] none
|
||||||
\retval none
|
\retval none
|
||||||
*/
|
*/
|
||||||
void usart_dma_receive_config(uint32_t usart_periph, uint32_t dmacmd)
|
void usart_dma_receive_config(uint32_t usart_periph, uint32_t dmacmd)
|
||||||
{
|
{
|
||||||
uint32_t ctl = 0U;
|
USART_CTL2(usart_periph) &= ~(USART_CTL2_DENR);
|
||||||
|
USART_CTL2(usart_periph) |= (USART_CTL2_DENR & dmacmd);
|
||||||
ctl = USART_CTL2(usart_periph);
|
|
||||||
ctl &= ~USART_CTL2_DENR;
|
|
||||||
ctl |= dmacmd;
|
|
||||||
/* configure DMA reception */
|
|
||||||
USART_CTL2(usart_periph) = ctl;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
/*!
|
/*!
|
||||||
|
|
@ -840,20 +817,15 @@ void usart_dma_receive_config(uint32_t usart_periph, uint32_t dmacmd)
|
||||||
\param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7)
|
\param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7)
|
||||||
\param[in] dmacmd: enable or disable DMA for transmission
|
\param[in] dmacmd: enable or disable DMA for transmission
|
||||||
only one parameter can be selected which is shown as below:
|
only one parameter can be selected which is shown as below:
|
||||||
\arg USART_DENT_ENABLE: DMA enable for transmission
|
\arg USART_TRANSMIT_DMA_ENABLE: DMA enable for transmission
|
||||||
\arg USART_DENT_DISABLE: DMA disable for transmission
|
\arg USART_TRANSMIT_DMA_DISABLE: DMA disable for transmission
|
||||||
\param[out] none
|
\param[out] none
|
||||||
\retval none
|
\retval none
|
||||||
*/
|
*/
|
||||||
void usart_dma_transmit_config(uint32_t usart_periph, uint32_t dmacmd)
|
void usart_dma_transmit_config(uint32_t usart_periph, uint32_t dmacmd)
|
||||||
{
|
{
|
||||||
uint32_t ctl = 0U;
|
USART_CTL2(usart_periph) &= ~(USART_CTL2_DENT);
|
||||||
|
USART_CTL2(usart_periph) |= (USART_CTL2_DENT & dmacmd);
|
||||||
ctl = USART_CTL2(usart_periph);
|
|
||||||
ctl &= ~USART_CTL2_DENT;
|
|
||||||
ctl |= dmacmd;
|
|
||||||
/* configure DMA transmission */
|
|
||||||
USART_CTL2(usart_periph) = ctl;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
/*!
|
/*!
|
||||||
|
|
|
||||||
|
|
@ -5,10 +5,11 @@
|
||||||
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
\version 2016-08-15, V1.0.0, firmware for GD32F4xx
|
||||||
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
\version 2018-12-12, V2.0.0, firmware for GD32F4xx
|
||||||
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
\version 2020-09-30, V2.1.0, firmware for GD32F4xx
|
||||||
|
\version 2022-03-09, V3.0.0, firmware for GD32F4xx
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/*
|
/*
|
||||||
Copyright (c) 2020, GigaDevice Semiconductor Inc.
|
Copyright (c) 2022, GigaDevice Semiconductor Inc.
|
||||||
|
|
||||||
Redistribution and use in source and binary forms, with or without modification,
|
Redistribution and use in source and binary forms, with or without modification,
|
||||||
are permitted provided that the following conditions are met:
|
are permitted provided that the following conditions are met:
|
||||||
|
|
@ -36,11 +37,6 @@ OF SUCH DAMAGE.
|
||||||
|
|
||||||
#include "gd32f4xx_wwdgt.h"
|
#include "gd32f4xx_wwdgt.h"
|
||||||
|
|
||||||
/* write value to WWDGT_CTL_CNT bit field */
|
|
||||||
#define CTL_CNT(regval) (BITS(0,6) & ((uint32_t)(regval) << 0))
|
|
||||||
/* write value to WWDGT_CFG_WIN bit field */
|
|
||||||
#define CFG_WIN(regval) (BITS(0,6) & ((uint32_t)(regval) << 0))
|
|
||||||
|
|
||||||
/*!
|
/*!
|
||||||
\brief reset the window watchdog timer configuration
|
\brief reset the window watchdog timer configuration
|
||||||
\param[in] none
|
\param[in] none
|
||||||
|
|
@ -72,12 +68,7 @@ void wwdgt_enable(void)
|
||||||
*/
|
*/
|
||||||
void wwdgt_counter_update(uint16_t counter_value)
|
void wwdgt_counter_update(uint16_t counter_value)
|
||||||
{
|
{
|
||||||
uint32_t reg = 0U;
|
WWDGT_CTL = (uint32_t)(CTL_CNT(counter_value));
|
||||||
|
|
||||||
reg = (WWDGT_CTL & (~WWDGT_CTL_CNT));
|
|
||||||
reg |= CTL_CNT(counter_value);
|
|
||||||
|
|
||||||
WWDGT_CTL = reg;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
/*!
|
/*!
|
||||||
|
|
@ -95,30 +86,9 @@ void wwdgt_counter_update(uint16_t counter_value)
|
||||||
*/
|
*/
|
||||||
void wwdgt_config(uint16_t counter, uint16_t window, uint32_t prescaler)
|
void wwdgt_config(uint16_t counter, uint16_t window, uint32_t prescaler)
|
||||||
{
|
{
|
||||||
uint32_t reg_cfg = 0U, reg_ctl = 0U;
|
|
||||||
|
|
||||||
/* clear WIN and PSC bits, clear CNT bit */
|
|
||||||
reg_cfg = (WWDGT_CFG &(~(WWDGT_CFG_WIN|WWDGT_CFG_PSC)));
|
|
||||||
reg_ctl = (WWDGT_CTL &(~WWDGT_CTL_CNT));
|
|
||||||
|
|
||||||
/* configure WIN and PSC bits, configure CNT bit */
|
/* configure WIN and PSC bits, configure CNT bit */
|
||||||
reg_cfg |= CFG_WIN(window);
|
WWDGT_CTL = (uint32_t)(CTL_CNT(counter));
|
||||||
reg_cfg |= prescaler;
|
WWDGT_CFG = (uint32_t)(CFG_WIN(window) | prescaler);
|
||||||
reg_ctl |= CTL_CNT(counter);
|
|
||||||
|
|
||||||
WWDGT_CTL = reg_ctl;
|
|
||||||
WWDGT_CFG = reg_cfg;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
\brief enable early wakeup interrupt of WWDGT
|
|
||||||
\param[in] none
|
|
||||||
\param[out] none
|
|
||||||
\retval none
|
|
||||||
*/
|
|
||||||
void wwdgt_interrupt_enable(void)
|
|
||||||
{
|
|
||||||
WWDGT_CFG |= WWDGT_CFG_EWIE;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
/*!
|
/*!
|
||||||
|
|
@ -144,5 +114,16 @@ FlagStatus wwdgt_flag_get(void)
|
||||||
*/
|
*/
|
||||||
void wwdgt_flag_clear(void)
|
void wwdgt_flag_clear(void)
|
||||||
{
|
{
|
||||||
WWDGT_STAT &= (~WWDGT_STAT_EWIF);
|
WWDGT_STAT = (uint32_t)(RESET);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief enable early wakeup interrupt of WWDGT
|
||||||
|
\param[in] none
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void wwdgt_interrupt_enable(void)
|
||||||
|
{
|
||||||
|
WWDGT_CFG |= WWDGT_CFG_EWIE;
|
||||||
}
|
}
|
||||||
|
|
|
||||||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue