RT-Thread
/
rt-thread
mirror of https://github.com/RT-Thread/rt-thread
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Add NuMaker-HMI-MA35D1 and RTP porting.

This commit is contained in:
Wayne Lin 2022-10-03 15:07:07 +08:00 committed by Bernard Xiong
parent ece0c6eef8
commit 2825189542
334 changed files with 168700 additions and 343 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

24
bsp/nuvoton/README.md
View File

@ -1,14 +1,16 @@
# Nuvoton BSP Description
Current supported BSP shown in below table:
| **BSP Folder** | **Board Name** |
| ------------------------- | -------------------------- |
| [numaker-iot-m487](numaker-iot-m487) | Nuvoton NuMaker-IoT-M487 |
| [numaker-pfm-m487](numaker-pfm-m487) | Nuvoton NuMaker-PFM-M487 |
| [nk-980iot](nk-980iot) | Nuvoton NK-980IOT |
| [numaker-m2354](numaker-m2354) | Nuvoton NuMaker-M2354 |
| [nk-rtu980](nk-rtu980) | Nuvoton NK-RTU980 |
| [nk-n9h30](nk-n9h30) | Nuvoton NK-N9H30 |
| [numaker-m032ki](numaker-m032ki) | Nuvoton NuMaker-M032KI |
| [numaker-m467hj](numaker-m467hj) | Nuvoton NuMaker-M467HJ |
| [numaker-iot-m467](numaker-iot-m467) | Nuvoton NuMaker-IoT-M467 |
| **Board Name** | **CPU Architecture** | **BSP Folder** |
| ------------------------- | ------------------------- | -------------------------- |
| NuMaker-IoT-M487 | CORTEX-M4 | [numaker-iot-m487](numaker-iot-m487) |
| NuMaker-PFM-M487 | CORTEX-M4 | [numaker-pfm-m487](numaker-pfm-m487) |
| NK-980IOT | ARM926EJS | [nk-980iot](nk-980iot) |
| NuMaker-M2354 | CORTEX-M23 | [numaker-m2354](numaker-m2354) |
| NK-RTU980 | ARM926EJS | [nk-rtu980](nk-rtu980) |
| NK-N9H30 | CORTEX-M4 | [nk-n9h30](nk-n9h30) |
| NuMaker-M032KI | CORTEX-M0 | [numaker-m032ki](numaker-m032ki) |
| NuMaker-M467HJ | CORTEX-M4 | [numaker-m467hj](numaker-m467hj) |
| NuMaker-IoT-M467 | CORTEX-M4 | [numaker-iot-m467](numaker-iot-m467) |
| NuMaker-HMI-MA35D1 | CORTEX-A35, CORTEX-M4 | [numaker-hmi-ma35d1](numaker-hmi-ma35d1), [ma35-rtp](ma35-rtp) |

1
bsp/nuvoton/docs/LVGL_Notes.md
View File

@ -12,6 +12,7 @@ Current supported LVGL running environment on Nuvoton's boards shown in below ta
| numaker-m032ki | Widgets | Nu-TFT v1.3 | config_lvgl |
| numaker-m467hj | Widgets | NuMaker-TFT-LCD43 v1.0 | config_lvgl |
| numaker-iot-m467 | Widgets | Nu-TFT v1.3 | config_lvgl |
| numaker-hmi-ma35d1 | Widgets | No | .config |
## Download related packages

4
bsp/nuvoton/libraries/m031/rtt_port/drv_uart.c
View File

@ -516,7 +516,7 @@ static rt_err_t nu_pdma_uart_rx_config(struct rt_serial_device *serial, uint8_t
nu_pdma_uart_rx_cb,
(void *)serial,
NU_PDMA_EVENT_TRANSFER_DONE | NU_PDMA_EVENT_TIMEOUT);
if ( result != RT_EOK )
if (result != RT_EOK)
{
goto exit_nu_pdma_uart_rx_config;
}
@ -527,7 +527,7 @@ static rt_err_t nu_pdma_uart_rx_config(struct rt_serial_device *serial, uint8_t
(uint32_t)pu8Buf,
i32TriggerLen,
1000); //Idle-timeout, 1ms
if ( result != RT_EOK )
if (result != RT_EOK)
{
goto exit_nu_pdma_uart_rx_config;
}

115
bsp/nuvoton/libraries/m2354/rtt_port/drv_usbhost.c
View File

@ -21,6 +21,13 @@
#include "usb.h"
#include "usbh_lib.h"
#define LOG_TAG "drv.usbhost"
#define DBG_ENABLE
#define DBG_SECTION_NAME LOG_TAG
#define DBG_LEVEL LOG_LVL_DBG
#define DBG_COLOR
#include <rtdbg.h>
#if !defined(NU_USBHOST_HUB_POLLING_INTERVAL)
#define NU_USBHOST_HUB_POLLING_INTERVAL (100)
#endif
@ -60,6 +67,7 @@ typedef struct nu_port_dev
UDEV_T *pUDev;
EP_INFO_T *apsEPInfo[NU_MAX_USBH_PIPE];
struct urequest asSetupReq[NU_MAX_USBH_PIPE];
uint32_t u32SentLength[NU_MAX_USBH_PIPE];
struct rt_completion utr_completion;
int port_num;
rt_bool_t bEnumDone;
@ -426,22 +434,30 @@ static int nu_int_xfer(
int timeouts)
{
int ret;
int retry = 3;
while (retry > 0)
while (1)
{
ret = usbh_int_xfer(psUTR);
if (ret == 0)
if (ret < 0)
return ret;
if (rt_completion_wait(&(psPortDev->utr_completion), timeouts) != 0)
{
RT_DEBUG_LOG(RT_DEBUG_USB, ("Request %08x Timeout in %d ms!!\n", psUTR, timeouts));
usbh_quit_utr(psUTR);
rt_completion_init(&(psPortDev->utr_completion));
rt_thread_mdelay(1);
}
else
{
RT_DEBUG_LOG(RT_DEBUG_USB, ("Transferring done %08x\n", psUTR));
usbh_quit_utr(psUTR);
break;
RT_DEBUG_LOG(RT_DEBUG_USB, ("nu_int_xfer ERROR: failed to submit interrupt request\n"));
rt_thread_delay((pipe->ep.bInterval * RT_TICK_PER_SECOND / 1000) > 0 ? (pipe->ep.bInterval * RT_TICK_PER_SECOND / 1000) : 1);
retry --;
}
}
if (ret < 0)
return ret;
return 0;
}
@ -453,30 +469,6 @@ static void xfer_done_cb(UTR_T *psUTR)
rt_completion_done(&(psPortDev->utr_completion));
}
static void int_xfer_done_cb(UTR_T *psUTR)
{
upipe_t pipe = (upipe_t)psUTR->context;
if (psUTR->status != 0)
{
RT_DEBUG_LOG(RT_DEBUG_USB, ("Interrupt xfer failed %d\n", psUTR->status));
goto exit_int_xfer_done_cb;
}
if (pipe->callback != RT_NULL)
{
struct uhost_msg msg;
msg.type = USB_MSG_CALLBACK;
msg.content.cb.function = pipe->callback;
msg.content.cb.context = pipe;
rt_usbh_event_signal(&s_sUSBHDev.uhcd, &msg);
}
exit_int_xfer_done_cb:
free_utr(psUTR);
}
static int nu_pipe_xfer(upipe_t pipe, rt_uint8_t token, void *buffer, int nbytes, int timeouts)
{
S_NU_RH_PORT_CTRL *psPortCtrl;
@ -510,6 +502,7 @@ static int nu_pipe_xfer(upipe_t pipe, rt_uint8_t token, void *buffer, int nbytes
{
struct urequest *psSetup = (struct urequest *)buffer_nonch;
RT_ASSERT(buffer_nonch != RT_NULL);
psPortCtrl->asHubPortDev->u32SentLength[pipe->pipe_index] = 0;
/* Read data from USB device. */
if (psSetup->request_type & USB_REQ_TYPE_DIR_IN)
@ -531,10 +524,31 @@ static int nu_pipe_xfer(upipe_t pipe, rt_uint8_t token, void *buffer, int nbytes
//token == USBH_PID_DATA
if (buffer_nonch && ((pipe->ep.bEndpointAddress & USB_DIR_MASK) == USB_DIR_IN))
{
struct urequest *psSetup = &psPortCtrl->asHubPortDev->asSetupReq[pipe->pipe_index];
/* Read data from USB device. */
//Trigger USBHostLib Ctril_Xfer
ret = nu_ctrl_xfer(psPortDev, &psPortCtrl->asHubPortDev->asSetupReq[pipe->pipe_index], buffer_nonch, timeouts);
if (ret != nbytes)
/*
* Workaround: HCD driver can readback all bytes of setup.wLength, but not support single packet transferring.
*/
if (psPortCtrl->asHubPortDev->u32SentLength[pipe->pipe_index] == 0)
{
ret = nu_ctrl_xfer(psPortDev, psSetup, buffer_nonch, timeouts);
psPortCtrl->asHubPortDev->u32SentLength[pipe->pipe_index] = ret;
}
else
{
if (psPortCtrl->asHubPortDev->u32SentLength[pipe->pipe_index] < nbytes)
{
ret = 0;
}
else
{
psPortCtrl->asHubPortDev->u32SentLength[pipe->pipe_index] -= nbytes;
ret = nbytes;
}
}
if (ret <= 0)
goto exit_nu_pipe_xfer;
}
else
@ -579,9 +593,6 @@ static int nu_pipe_xfer(upipe_t pipe, rt_uint8_t token, void *buffer, int nbytes
}
else if (pipe->ep.bmAttributes == USB_EP_ATTR_INT)
{
psUTR->func = int_xfer_done_cb;
psUTR->context = pipe;
if (nu_int_xfer(pipe, psPortDev, psUTR, timeouts) < 0)
{
RT_DEBUG_LOG(RT_DEBUG_USB, ("nu_pipe_xfer ERROR: int transfer failed\n"));
@ -591,7 +602,7 @@ static int nu_pipe_xfer(upipe_t pipe, rt_uint8_t token, void *buffer, int nbytes
{
i32XferLen = nbytes;
}
goto exit2_nu_pipe_xfer;
goto exit_nu_pipe_xfer;
}
else if (pipe->ep.bmAttributes == USB_EP_ATTR_ISOC)
{
@ -630,20 +641,17 @@ failreport_nu_pipe_xfer:
i32XferLen = psUTR->xfer_len;
exit_nu_pipe_xfer:
//Call callback
if (pipe->callback != RT_NULL)
{
pipe->callback(pipe);
}
exit_nu_pipe_xfer:
if (psUTR)
free_utr(psUTR);
exit2_nu_pipe_xfer:
NU_USBHOST_UNLOCK();
return i32XferLen;
@ -851,12 +859,19 @@ int nu_usbh_register(void)
psUHCD->num_ports = NU_MAX_USBH_PORT;
#if !defined(BSP_USING_OTG)
SYS_UnlockReg();
{
uint32_t u32RegLockBackup;
/* Set OTG as USB Host role */
SYS->USBPHY = SYS_USBPHY_OTGPHYEN_Msk | SYS_USBPHY_SBO_Msk | (0x1 << SYS_USBPHY_USBROLE_Pos);
u32RegLockBackup = SYS_IsRegLocked();
if (u32RegLockBackup)
SYS_UnlockReg();
SYS_LockReg();
/* Set OTG as USB Host role */
SYS->USBPHY = SYS_USBPHY_OTGPHYEN_Msk | SYS_USBPHY_SBO_Msk | (0x1 << SYS_USBPHY_USBROLE_Pos);
if (u32RegLockBackup)
SYS_LockReg();
}
#endif
@ -875,6 +890,6 @@ int nu_usbh_register(void)
return 0;
}
INIT_DEVICE_EXPORT(nu_usbh_register);
INIT_APP_EXPORT(nu_usbh_register);
#endif

22
bsp/nuvoton/libraries/m460/rtt_port/drv_ccap.c
View File

@ -208,6 +208,22 @@ static rt_err_t ccap_pipe_configure(nu_ccap_t psNuCcap, ccap_view_info_t psViewI
{
uint32_t u32Offset = 0;
uint32_t u32WM, u32WN, u32HM, u32HN;
uint32_t u32Div = 0;
if (psCcapConf->sPipeInfo_Planar.u32PixFmt == CCAP_PAR_PLNFMT_YUV422)
{
/* U/V farm size equals Y/2 farm size */
u32Div = 2;
}
else if (psCcapConf->sPipeInfo_Planar.u32PixFmt == CCAP_PAR_PLNFMT_YUV420)
{
/* U/V farm size equals Y/4 farm size */
u32Div = 4;
}
else
{
goto fail_ccap_pipe_configure;
}
/* Set System Memory Planar Y Base Address Register */
CCAP_SetPlanarYBuf(psNuCcap->base, (uint32_t)psCcapConf->sPipeInfo_Planar.pu8FarmAddr + u32Offset);
@ -217,7 +233,7 @@ static rt_err_t ccap_pipe_configure(nu_ccap_t psNuCcap, ccap_view_info_t psViewI
/* Set System Memory Planar U Base Address Register */
CCAP_SetPlanarUBuf(psNuCcap->base, (uint32_t)psCcapConf->sPipeInfo_Planar.pu8FarmAddr + u32Offset);
u32Offset += ((psCcapConf->sPipeInfo_Planar.u32Height * psCcapConf->sPipeInfo_Planar.u32Width) / 2);
u32Offset += ((psCcapConf->sPipeInfo_Planar.u32Height * psCcapConf->sPipeInfo_Planar.u32Width) / u32Div);
/* Set System Memory Planar V Base Address Register */
CCAP_SetPlanarVBuf(psNuCcap->base, (uint32_t)psCcapConf->sPipeInfo_Planar.pu8FarmAddr + u32Offset);
@ -258,6 +274,10 @@ static rt_err_t ccap_pipe_configure(nu_ccap_t psNuCcap, ccap_view_info_t psViewI
u32PipeEnabling);
return RT_EOK;
fail_ccap_pipe_configure:
return -RT_ERROR;
}
static rt_err_t ccap_open(rt_device_t dev, rt_uint16_t oflag)

133
bsp/nuvoton/libraries/m460/rtt_port/drv_usbhost.c
View File

@ -23,6 +23,13 @@
#include "usb.h"
#include "usbh_lib.h"
#define LOG_TAG "drv.usbhost"
#define DBG_ENABLE
#define DBG_SECTION_NAME LOG_TAG
#define DBG_LEVEL LOG_LVL_DBG
#define DBG_COLOR
#include <rtdbg.h>
#if !defined(NU_USBHOST_HUB_POLLING_INTERVAL)
#define NU_USBHOST_HUB_POLLING_INTERVAL (100)
#endif
@ -62,6 +69,7 @@ typedef struct nu_port_dev
UDEV_T *pUDev;
EP_INFO_T *apsEPInfo[NU_MAX_USBH_PIPE];
struct urequest asSetupReq[NU_MAX_USBH_PIPE];
uint32_t u32SentLength[NU_MAX_USBH_PIPE];
struct rt_completion utr_completion;
int port_num;
rt_bool_t bEnumDone;
@ -445,22 +453,30 @@ static int nu_int_xfer(
int timeouts)
{
int ret;
int retry = 3;
while (retry > 0)
while (1)
{
ret = usbh_int_xfer(psUTR);
if (ret == 0)
if (ret < 0)
return ret;
if (rt_completion_wait(&(psPortDev->utr_completion), timeouts) != 0)
{
RT_DEBUG_LOG(RT_DEBUG_USB, ("Request %08x Timeout in %d ms!!\n", psUTR, timeouts));
usbh_quit_utr(psUTR);
rt_completion_init(&(psPortDev->utr_completion));
rt_thread_mdelay(1);
}
else
{
RT_DEBUG_LOG(RT_DEBUG_USB, ("Transferring done %08x\n", psUTR));
usbh_quit_utr(psUTR);
break;
RT_DEBUG_LOG(RT_DEBUG_USB, ("nu_int_xfer ERROR: failed to submit interrupt request\n"));
rt_thread_delay((pipe->ep.bInterval * RT_TICK_PER_SECOND / 1000) > 0 ? (pipe->ep.bInterval * RT_TICK_PER_SECOND / 1000) : 1);
retry --;
}
}
if (ret < 0)
return ret;
return 0;
}
@ -472,30 +488,6 @@ static void xfer_done_cb(UTR_T *psUTR)
rt_completion_done(&(psPortDev->utr_completion));
}
static void int_xfer_done_cb(UTR_T *psUTR)
{
upipe_t pipe = (upipe_t)psUTR->context;
if (psUTR->status != 0)
{
RT_DEBUG_LOG(RT_DEBUG_USB, ("Interrupt xfer failed %d\n", psUTR->status));
goto exit_int_xfer_done_cb;
}
if (pipe->callback != RT_NULL)
{
struct uhost_msg msg;
msg.type = USB_MSG_CALLBACK;
msg.content.cb.function = pipe->callback;
msg.content.cb.context = pipe;
rt_usbh_event_signal(&s_sUSBHDev.uhcd, &msg);
}
exit_int_xfer_done_cb:
free_utr(psUTR);
}
static int nu_pipe_xfer(upipe_t pipe, rt_uint8_t token, void *buffer, int nbytes, int timeouts)
{
S_NU_RH_PORT_CTRL *psPortCtrl;
@ -529,6 +521,7 @@ static int nu_pipe_xfer(upipe_t pipe, rt_uint8_t token, void *buffer, int nbytes
{
struct urequest *psSetup = (struct urequest *)buffer_nonch;
RT_ASSERT(buffer_nonch != RT_NULL);
psPortCtrl->asHubPortDev->u32SentLength[pipe->pipe_index] = 0;
/* Read data from USB device. */
if (psSetup->request_type & USB_REQ_TYPE_DIR_IN)
@ -550,10 +543,31 @@ static int nu_pipe_xfer(upipe_t pipe, rt_uint8_t token, void *buffer, int nbytes
//token == USBH_PID_DATA
if (buffer_nonch && ((pipe->ep.bEndpointAddress & USB_DIR_MASK) == USB_DIR_IN))
{
struct urequest *psSetup = &psPortCtrl->asHubPortDev->asSetupReq[pipe->pipe_index];
/* Read data from USB device. */
//Trigger USBHostLib Ctril_Xfer
ret = nu_ctrl_xfer(psPortDev, &psPortCtrl->asHubPortDev->asSetupReq[pipe->pipe_index], buffer_nonch, timeouts);
if (ret != nbytes)
/*
* Workaround: HCD driver can readback all bytes of setup.wLength, but not support single packet transferring.
*/
if (psPortCtrl->asHubPortDev->u32SentLength[pipe->pipe_index] == 0)
{
ret = nu_ctrl_xfer(psPortDev, psSetup, buffer_nonch, timeouts);
psPortCtrl->asHubPortDev->u32SentLength[pipe->pipe_index] = ret;
}
else
{
if (psPortCtrl->asHubPortDev->u32SentLength[pipe->pipe_index] < nbytes)
{
ret = 0;
}
else
{
psPortCtrl->asHubPortDev->u32SentLength[pipe->pipe_index] -= nbytes;
ret = nbytes;
}
}
if (ret <= 0)
goto exit_nu_pipe_xfer;
}
else
@ -598,9 +612,6 @@ static int nu_pipe_xfer(upipe_t pipe, rt_uint8_t token, void *buffer, int nbytes
}
else if (pipe->ep.bmAttributes == USB_EP_ATTR_INT)
{
psUTR->func = int_xfer_done_cb;
psUTR->context = pipe;
if (nu_int_xfer(pipe, psPortDev, psUTR, timeouts) < 0)
{
RT_DEBUG_LOG(RT_DEBUG_USB, ("nu_pipe_xfer ERROR: int transfer failed\n"));
@ -610,7 +621,7 @@ static int nu_pipe_xfer(upipe_t pipe, rt_uint8_t token, void *buffer, int nbytes
{
i32XferLen = nbytes;
}
goto exit2_nu_pipe_xfer;
goto exit_nu_pipe_xfer;
}
else if (pipe->ep.bmAttributes == USB_EP_ATTR_ISOC)
{
@ -649,20 +660,17 @@ failreport_nu_pipe_xfer:
i32XferLen = psUTR->xfer_len;
exit_nu_pipe_xfer:
//Call callback
if (pipe->callback != RT_NULL)
{
pipe->callback(pipe);
}
exit_nu_pipe_xfer:
if (psUTR)
free_utr(psUTR);
exit2_nu_pipe_xfer:
NU_USBHOST_UNLOCK();
return i32XferLen;
@ -859,7 +867,6 @@ int nu_usbh_register(void)
{
rt_err_t res;
uhcd_t psUHCD;
uint32_t u32RegLockBackup;
psUHCD = (uhcd_t)&s_sUSBHDev.uhcd;
@ -869,28 +876,32 @@ int nu_usbh_register(void)
psUHCD->ops = &nu_uhcd_ops;
psUHCD->num_ports = NU_MAX_USBH_PORT;
#if !defined(BSP_USING_HSOTG)
u32RegLockBackup = SYS_IsRegLocked();
SYS_UnlockReg();
{
uint32_t u32RegLockBackup;
u32RegLockBackup = SYS_IsRegLocked();
if (u32RegLockBackup)
SYS_UnlockReg();
#if defined(BSP_USING_HSUSBH)
/* Set USB Host role */
SYS->USBPHY = (SYS->USBPHY & ~SYS_USBPHY_HSUSBROLE_Msk) | (0x1u << SYS_USBPHY_HSUSBROLE_Pos);
SYS->USBPHY |= SYS_USBPHY_HSUSBEN_Msk | SYS_USBPHY_SBO_Msk;
rt_thread_delay(20);
SYS->USBPHY |= SYS_USBPHY_HSUSBACT_Msk;
/* Set USB Host role */
SYS->USBPHY = (SYS->USBPHY & ~SYS_USBPHY_HSUSBROLE_Msk) | (0x1u << SYS_USBPHY_HSUSBROLE_Pos);
SYS->USBPHY |= SYS_USBPHY_HSUSBEN_Msk | SYS_USBPHY_SBO_Msk;
rt_thread_delay(20);
SYS->USBPHY |= SYS_USBPHY_HSUSBACT_Msk;
#endif
#if defined(BSP_USING_USBH)
/* Set USB Host role */
SYS->USBPHY = (SYS->USBPHY & ~SYS_USBPHY_USBROLE_Msk) | (0x1u << SYS_USBPHY_USBROLE_Pos);
SYS->USBPHY |= SYS_USBPHY_USBEN_Msk | SYS_USBPHY_SBO_Msk ;
/* Set USB Host role */
SYS->USBPHY = (SYS->USBPHY & ~SYS_USBPHY_USBROLE_Msk) | (0x1u << SYS_USBPHY_USBROLE_Pos);
SYS->USBPHY |= SYS_USBPHY_USBEN_Msk | SYS_USBPHY_SBO_Msk ;
#endif
if (u32RegLockBackup)
SYS_LockReg();
if (u32RegLockBackup)
SYS_LockReg();
}
#endif
@ -909,6 +920,6 @@ int nu_usbh_register(void)
return 0;
}
INIT_DEVICE_EXPORT(nu_usbh_register);
INIT_APP_EXPORT(nu_usbh_register);
#endif

130
bsp/nuvoton/libraries/m480/rtt_port/drv_usbhost.c
View File

@ -23,6 +23,13 @@
#include "usb.h"
#include "usbh_lib.h"
#define LOG_TAG "drv.usbhost"
#define DBG_ENABLE
#define DBG_SECTION_NAME LOG_TAG
#define DBG_LEVEL LOG_LVL_DBG
#define DBG_COLOR
#include <rtdbg.h>
#if !defined(NU_USBHOST_HUB_POLLING_INTERVAL)
#define NU_USBHOST_HUB_POLLING_INTERVAL (100)
#endif
@ -62,6 +69,7 @@ typedef struct nu_port_dev
UDEV_T *pUDev;
EP_INFO_T *apsEPInfo[NU_MAX_USBH_PIPE];
struct urequest asSetupReq[NU_MAX_USBH_PIPE];
uint32_t u32SentLength[NU_MAX_USBH_PIPE];
struct rt_completion utr_completion;
int port_num;
rt_bool_t bEnumDone;
@ -416,7 +424,6 @@ static int nu_bulk_xfer(
rt_kprintf("psUTR->bIsTransferDone: %08x\n", psUTR->bIsTransferDone);
rt_kprintf("psUTR->status: %08x\n", psUTR->status);
rt_kprintf("psUTR->td_cnt: %08x\n", psUTR->td_cnt);
return -1;
}
return 0;
@ -429,22 +436,30 @@ static int nu_int_xfer(
int timeouts)
{
int ret;
int retry = 3;
while (retry > 0)
while (1)
{
ret = usbh_int_xfer(psUTR);
if (ret == 0)
if (ret < 0)
return ret;
if (rt_completion_wait(&(psPortDev->utr_completion), timeouts) != 0)
{
RT_DEBUG_LOG(RT_DEBUG_USB, ("Request %08x Timeout in %d ms!!\n", psUTR, timeouts));
usbh_quit_utr(psUTR);
rt_completion_init(&(psPortDev->utr_completion));
rt_thread_mdelay(1);
}
else
{
RT_DEBUG_LOG(RT_DEBUG_USB, ("Transferring done %08x\n", psUTR));
usbh_quit_utr(psUTR);
break;
RT_DEBUG_LOG(RT_DEBUG_USB, ("nu_int_xfer ERROR: failed to submit interrupt request\n"));
rt_thread_delay((pipe->ep.bInterval * RT_TICK_PER_SECOND / 1000) > 0 ? (pipe->ep.bInterval * RT_TICK_PER_SECOND / 1000) : 1);
retry --;
}
}
if (ret < 0)
return ret;
return 0;
}
@ -456,30 +471,6 @@ static void xfer_done_cb(UTR_T *psUTR)
rt_completion_done(&(psPortDev->utr_completion));
}
static void int_xfer_done_cb(UTR_T *psUTR)
{
upipe_t pipe = (upipe_t)psUTR->context;
if (psUTR->status != 0)
{
RT_DEBUG_LOG(RT_DEBUG_USB, ("Interrupt xfer failed %d\n", psUTR->status));
goto exit_int_xfer_done_cb;
}
if (pipe->callback != RT_NULL)
{
struct uhost_msg msg;
msg.type = USB_MSG_CALLBACK;
msg.content.cb.function = pipe->callback;
msg.content.cb.context = pipe;
rt_usbh_event_signal(&s_sUSBHDev.uhcd, &msg);
}
exit_int_xfer_done_cb:
free_utr(psUTR);
}
static int nu_pipe_xfer(upipe_t pipe, rt_uint8_t token, void *buffer, int nbytes, int timeouts)
{
S_NU_RH_PORT_CTRL *psPortCtrl;
@ -513,6 +504,7 @@ static int nu_pipe_xfer(upipe_t pipe, rt_uint8_t token, void *buffer, int nbytes
{
struct urequest *psSetup = (struct urequest *)buffer_nonch;
RT_ASSERT(buffer_nonch != RT_NULL);
psPortCtrl->asHubPortDev->u32SentLength[pipe->pipe_index] = 0;
/* Read data from USB device. */
if (psSetup->request_type & USB_REQ_TYPE_DIR_IN)
@ -534,10 +526,31 @@ static int nu_pipe_xfer(upipe_t pipe, rt_uint8_t token, void *buffer, int nbytes
//token == USBH_PID_DATA
if (buffer_nonch && ((pipe->ep.bEndpointAddress & USB_DIR_MASK) == USB_DIR_IN))
{
struct urequest *psSetup = &psPortCtrl->asHubPortDev->asSetupReq[pipe->pipe_index];
/* Read data from USB device. */
//Trigger USBHostLib Ctril_Xfer
ret = nu_ctrl_xfer(psPortDev, &psPortCtrl->asHubPortDev->asSetupReq[pipe->pipe_index], buffer_nonch, timeouts);
if (ret != nbytes)
/*
* Workaround: HCD driver can readback all bytes of setup.wLength, but not support single packet transferring.
*/
if (psPortCtrl->asHubPortDev->u32SentLength[pipe->pipe_index] == 0)
{
ret = nu_ctrl_xfer(psPortDev, psSetup, buffer_nonch, timeouts);
psPortCtrl->asHubPortDev->u32SentLength[pipe->pipe_index] = ret;
}
else
{
if (psPortCtrl->asHubPortDev->u32SentLength[pipe->pipe_index] < nbytes)
{
ret = 0;
}
else
{
psPortCtrl->asHubPortDev->u32SentLength[pipe->pipe_index] -= nbytes;
ret = nbytes;
}
}
if (ret <= 0)
goto exit_nu_pipe_xfer;
}
else
@ -582,9 +595,6 @@ static int nu_pipe_xfer(upipe_t pipe, rt_uint8_t token, void *buffer, int nbytes
}
else if (pipe->ep.bmAttributes == USB_EP_ATTR_INT)
{
psUTR->func = int_xfer_done_cb;
psUTR->context = pipe;
if (nu_int_xfer(pipe, psPortDev, psUTR, timeouts) < 0)
{
RT_DEBUG_LOG(RT_DEBUG_USB, ("nu_pipe_xfer ERROR: int transfer failed\n"));
@ -594,7 +604,7 @@ static int nu_pipe_xfer(upipe_t pipe, rt_uint8_t token, void *buffer, int nbytes
{
i32XferLen = nbytes;
}
goto exit2_nu_pipe_xfer;
goto exit_nu_pipe_xfer;
}
else if (pipe->ep.bmAttributes == USB_EP_ATTR_ISOC)
{
@ -633,20 +643,17 @@ failreport_nu_pipe_xfer:
i32XferLen = psUTR->xfer_len;
exit_nu_pipe_xfer:
//Call callback
if (pipe->callback != RT_NULL)
{
pipe->callback(pipe);
}
exit_nu_pipe_xfer:
if (psUTR)
free_utr(psUTR);
exit2_nu_pipe_xfer:
NU_USBHOST_UNLOCK();
return i32XferLen;
@ -852,25 +859,32 @@ int nu_usbh_register(void)
psUHCD->ops = &nu_uhcd_ops;
psUHCD->num_ports = NU_MAX_USBH_PORT;
#if !defined(BSP_USING_HSOTG)
SYS_UnlockReg();
{
uint32_t u32RegLockBackup;
u32RegLockBackup = SYS_IsRegLocked();
if (u32RegLockBackup)
SYS_UnlockReg();
#if defined(BSP_USING_HSUSBH)
/* Set USB Host role */
SYS->USBPHY = (SYS->USBPHY & ~SYS_USBPHY_HSUSBROLE_Msk) | (0x1u << SYS_USBPHY_HSUSBROLE_Pos);
SYS->USBPHY |= SYS_USBPHY_HSUSBEN_Msk | SYS_USBPHY_SBO_Msk;
rt_thread_delay(20);
SYS->USBPHY |= SYS_USBPHY_HSUSBACT_Msk;
/* Set USB Host role */
SYS->USBPHY = (SYS->USBPHY & ~SYS_USBPHY_HSUSBROLE_Msk) | (0x1u << SYS_USBPHY_HSUSBROLE_Pos);
SYS->USBPHY |= SYS_USBPHY_HSUSBEN_Msk | SYS_USBPHY_SBO_Msk;
rt_thread_delay(20);
SYS->USBPHY |= SYS_USBPHY_HSUSBACT_Msk;
#endif
#if defined(BSP_USING_USBH)
/* Set USB Host role */
SYS->USBPHY = (SYS->USBPHY & ~SYS_USBPHY_USBROLE_Msk) | (0x1u << SYS_USBPHY_USBROLE_Pos);
SYS->USBPHY |= SYS_USBPHY_USBEN_Msk | SYS_USBPHY_SBO_Msk ;
/* Set USB Host role */
SYS->USBPHY = (SYS->USBPHY & ~SYS_USBPHY_USBROLE_Msk) | (0x1u << SYS_USBPHY_USBROLE_Pos);
SYS->USBPHY |= SYS_USBPHY_USBEN_Msk | SYS_USBPHY_SBO_Msk ;
#endif
SYS_LockReg();
if (u32RegLockBackup)
SYS_LockReg();
}
#endif
@ -889,6 +903,6 @@ int nu_usbh_register(void)
return 0;
}
INIT_DEVICE_EXPORT(nu_usbh_register);
INIT_APP_EXPORT(nu_usbh_register);
#endif

136
bsp/nuvoton/libraries/ma35/CMSIS/Include/arm_common_tables.h Normal file
View File

@ -0,0 +1,136 @@
/* ----------------------------------------------------------------------
* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
*
* $Date: 19. October 2015
* $Revision: V.1.4.5 a
*
* Project: CMSIS DSP Library
* Title: arm_common_tables.h
*
* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions
*
* Target Processor: Cortex-M4/Cortex-M3
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* - Neither the name of ARM LIMITED nor the names of its contributors
* may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* -------------------------------------------------------------------- */
#ifndef _ARM_COMMON_TABLES_H
#define _ARM_COMMON_TABLES_H
#include "arm_math.h"
extern const uint16_t armBitRevTable[1024];
extern const q15_t armRecipTableQ15[64];
extern const q31_t armRecipTableQ31[64];
/* extern const q31_t realCoefAQ31[1024]; */
/* extern const q31_t realCoefBQ31[1024]; */
extern const float32_t twiddleCoef_16[32];
extern const float32_t twiddleCoef_32[64];
extern const float32_t twiddleCoef_64[128];
extern const float32_t twiddleCoef_128[256];
extern const float32_t twiddleCoef_256[512];
extern const float32_t twiddleCoef_512[1024];
extern const float32_t twiddleCoef_1024[2048];
extern const float32_t twiddleCoef_2048[4096];
extern const float32_t twiddleCoef_4096[8192];
#define twiddleCoef twiddleCoef_4096
extern const q31_t twiddleCoef_16_q31[24];
extern const q31_t twiddleCoef_32_q31[48];
extern const q31_t twiddleCoef_64_q31[96];
extern const q31_t twiddleCoef_128_q31[192];
extern const q31_t twiddleCoef_256_q31[384];
extern const q31_t twiddleCoef_512_q31[768];
extern const q31_t twiddleCoef_1024_q31[1536];
extern const q31_t twiddleCoef_2048_q31[3072];
extern const q31_t twiddleCoef_4096_q31[6144];
extern const q15_t twiddleCoef_16_q15[24];
extern const q15_t twiddleCoef_32_q15[48];
extern const q15_t twiddleCoef_64_q15[96];
extern const q15_t twiddleCoef_128_q15[192];
extern const q15_t twiddleCoef_256_q15[384];
extern const q15_t twiddleCoef_512_q15[768];
extern const q15_t twiddleCoef_1024_q15[1536];
extern const q15_t twiddleCoef_2048_q15[3072];
extern const q15_t twiddleCoef_4096_q15[6144];
extern const float32_t twiddleCoef_rfft_32[32];
extern const float32_t twiddleCoef_rfft_64[64];
extern const float32_t twiddleCoef_rfft_128[128];
extern const float32_t twiddleCoef_rfft_256[256];
extern const float32_t twiddleCoef_rfft_512[512];
extern const float32_t twiddleCoef_rfft_1024[1024];
extern const float32_t twiddleCoef_rfft_2048[2048];
extern const float32_t twiddleCoef_rfft_4096[4096];
/* floating-point bit reversal tables */
#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20 )
#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48 )
#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56 )
#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 )
#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 )
#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 )
#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800)
#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808)
#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032)
extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH];
/* fixed-point bit reversal tables */
#define ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH ((uint16_t)12 )
#define ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH ((uint16_t)24 )
#define ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH ((uint16_t)56 )
#define ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH ((uint16_t)112 )
#define ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH ((uint16_t)240 )
#define ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH ((uint16_t)480 )
#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992 )
#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984)
#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032)
extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH];
/* Tables for Fast Math Sine and Cosine */
extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1];
extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1];
extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1];
#endif /* ARM_COMMON_TABLES_H */

79
bsp/nuvoton/libraries/ma35/CMSIS/Include/arm_const_structs.h Normal file
View File

@ -0,0 +1,79 @@
/* ----------------------------------------------------------------------
* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
*
* $Date: 19. March 2015
* $Revision: V.1.4.5
*
* Project: CMSIS DSP Library
* Title: arm_const_structs.h
*
* Description: This file has constant structs that are initialized for
* user convenience. For example, some can be given as
* arguments to the arm_cfft_f32() function.
*
* Target Processor: Cortex-M4/Cortex-M3
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* - Neither the name of ARM LIMITED nor the names of its contributors
* may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* -------------------------------------------------------------------- */
#ifndef _ARM_CONST_STRUCTS_H
#define _ARM_CONST_STRUCTS_H
#include "arm_math.h"
#include "arm_common_tables.h"
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096;
#endif

7154
bsp/nuvoton/libraries/ma35/CMSIS/Include/arm_math.h Normal file
View File

File diff suppressed because it is too large Load Diff

734
bsp/nuvoton/libraries/ma35/CMSIS/Include/cmsis_armcc.h Normal file
View File

@ -0,0 +1,734 @@
/**************************************************************************//**
* @file cmsis_armcc.h
* @brief CMSIS Cortex-M Core Function/Instruction Header File
* @version V4.30
* @date 20. October 2015
******************************************************************************/
/* Copyright (c) 2009 - 2015 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#ifndef __CMSIS_ARMCC_H
#define __CMSIS_ARMCC_H
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
#error "Please use ARM Compiler Toolchain V4.0.677 or later!"
#endif
/* ########################### Core Function Access ########################### */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
@{
*/
/* intrinsic void __enable_irq(); */
/* intrinsic void __disable_irq(); */
/**
\brief Get Control Register
\details Returns the content of the Control Register.
\return Control Register value
*/
__STATIC_INLINE uint32_t __get_CONTROL(void)
{
register uint32_t __regControl __ASM("control");
return (__regControl);
}
/**
\brief Set Control Register
\details Writes the given value to the Control Register.
\param [in] control Control Register value to set
*/
__STATIC_INLINE void __set_CONTROL(uint32_t control)
{
register uint32_t __regControl __ASM("control");
__regControl = control;
}
/**
\brief Get IPSR Register
\details Returns the content of the IPSR Register.
\return IPSR Register value
*/
__STATIC_INLINE uint32_t __get_IPSR(void)
{
register uint32_t __regIPSR __ASM("ipsr");
return (__regIPSR);
}
/**
\brief Get APSR Register
\details Returns the content of the APSR Register.
\return APSR Register value
*/
__STATIC_INLINE uint32_t __get_APSR(void)
{
register uint32_t __regAPSR __ASM("apsr");
return (__regAPSR);
}
/**
\brief Get xPSR Register
\details Returns the content of the xPSR Register.
\return xPSR Register value
*/
__STATIC_INLINE uint32_t __get_xPSR(void)
{
register uint32_t __regXPSR __ASM("xpsr");
return (__regXPSR);
}
/**
\brief Get Process Stack Pointer
\details Returns the current value of the Process Stack Pointer (PSP).
\return PSP Register value
*/
__STATIC_INLINE uint32_t __get_PSP(void)
{
register uint32_t __regProcessStackPointer __ASM("psp");
return (__regProcessStackPointer);
}
/**
\brief Set Process Stack Pointer
\details Assigns the given value to the Process Stack Pointer (PSP).
\param [in] topOfProcStack Process Stack Pointer value to set
*/
__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
{
register uint32_t __regProcessStackPointer __ASM("psp");
__regProcessStackPointer = topOfProcStack;
}
/**
\brief Get Main Stack Pointer
\details Returns the current value of the Main Stack Pointer (MSP).
\return MSP Register value
*/
__STATIC_INLINE uint32_t __get_MSP(void)
{
register uint32_t __regMainStackPointer __ASM("msp");
return (__regMainStackPointer);
}
/**
\brief Set Main Stack Pointer
\details Assigns the given value to the Main Stack Pointer (MSP).
\param [in] topOfMainStack Main Stack Pointer value to set
*/
__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
{
register uint32_t __regMainStackPointer __ASM("msp");
__regMainStackPointer = topOfMainStack;
}
/**
\brief Get Priority Mask
\details Returns the current state of the priority mask bit from the Priority Mask Register.
\return Priority Mask value
*/
__STATIC_INLINE uint32_t __get_PRIMASK(void)
{
register uint32_t __regPriMask __ASM("primask");
return (__regPriMask);
}
/**
\brief Set Priority Mask
\details Assigns the given value to the Priority Mask Register.
\param [in] priMask Priority Mask
*/
__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
{
register uint32_t __regPriMask __ASM("primask");
__regPriMask = (priMask);
}
#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
/**
\brief Enable FIQ
\details Enables FIQ interrupts by clearing the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __enable_fault_irq __enable_fiq
/**
\brief Disable FIQ
\details Disables FIQ interrupts by setting the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __disable_fault_irq __disable_fiq
/**
\brief Get Base Priority
\details Returns the current value of the Base Priority register.
\return Base Priority register value
*/
__STATIC_INLINE uint32_t __get_BASEPRI(void)
{
register uint32_t __regBasePri __ASM("basepri");
return (__regBasePri);
}
/**
\brief Set Base Priority
\details Assigns the given value to the Base Priority register.
\param [in] basePri Base Priority value to set
*/
__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
{
register uint32_t __regBasePri __ASM("basepri");
__regBasePri = (basePri & 0xFFU);
}
/**
\brief Set Base Priority with condition
\details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
or the new value increases the BASEPRI priority level.
\param [in] basePri Base Priority value to set
*/
__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
{
register uint32_t __regBasePriMax __ASM("basepri_max");
__regBasePriMax = (basePri & 0xFFU);
}
/**
\brief Get Fault Mask
\details Returns the current value of the Fault Mask register.
\return Fault Mask register value
*/
__STATIC_INLINE uint32_t __get_FAULTMASK(void)
{
register uint32_t __regFaultMask __ASM("faultmask");
return (__regFaultMask);
}
/**
\brief Set Fault Mask
\details Assigns the given value to the Fault Mask register.
\param [in] faultMask Fault Mask value to set
*/
__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
{
register uint32_t __regFaultMask __ASM("faultmask");
__regFaultMask = (faultMask & (uint32_t)1);
}
#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */
#if (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U)
/**
\brief Get FPSCR
\details Returns the current value of the Floating Point Status/Control register.
\return Floating Point Status/Control register value
*/
__STATIC_INLINE uint32_t __get_FPSCR(void)
{
#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
register uint32_t __regfpscr __ASM("fpscr");
return (__regfpscr);
#else
return (0U);
#endif
}
/**
\brief Set FPSCR
\details Assigns the given value to the Floating Point Status/Control register.
\param [in] fpscr Floating Point Status/Control value to set
*/
__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
{
#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
register uint32_t __regfpscr __ASM("fpscr");
__regfpscr = (fpscr);
#endif
}
#endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */
/*@} end of CMSIS_Core_RegAccFunctions */
/* ########################## Core Instruction Access ######################### */
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
Access to dedicated instructions
@{
*/
/**
\brief No Operation
\details No Operation does nothing. This instruction can be used for code alignment purposes.
*/
#define __NOP __nop
/**
\brief Wait For Interrupt
\details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
*/
#define __WFI __wfi
/**
\brief Wait For Event
\details Wait For Event is a hint instruction that permits the processor to enter
a low-power state until one of a number of events occurs.
*/
#define __WFE __wfe
/**
\brief Send Event
\details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
*/
#define __SEV __sev
/**
\brief Instruction Synchronization Barrier
\details Instruction Synchronization Barrier flushes the pipeline in the processor,
so that all instructions following the ISB are fetched from cache or memory,
after the instruction has been completed.
*/
#define __ISB() do {\
__schedule_barrier();\
__isb(0xF);\
__schedule_barrier();\
} while (0U)
/**
\brief Data Synchronization Barrier
\details Acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
#define __DSB() do {\
__schedule_barrier();\
__dsb(0xF);\
__schedule_barrier();\
} while (0U)
/**
\brief Data Memory Barrier
\details Ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
#define __DMB() do {\
__schedule_barrier();\
__dmb(0xF);\
__schedule_barrier();\
} while (0U)
/**
\brief Reverse byte order (32 bit)
\details Reverses the byte order in integer value.
\param [in] value Value to reverse
\return Reversed value
*/
#define __REV __rev
/**
\brief Reverse byte order (16 bit)
\details Reverses the byte order in two unsigned short values.
\param [in] value Value to reverse
\return Reversed value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
{
rev16 r0, r0
bx lr
}
#endif
/**
\brief Reverse byte order in signed short value
\details Reverses the byte order in a signed short value with sign extension to integer.
\param [in] value Value to reverse
\return Reversed value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
{
revsh r0, r0
bx lr
}
#endif
/**
\brief Rotate Right in unsigned value (32 bit)
\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
\param [in] value Value to rotate
\param [in] value Number of Bits to rotate
\return Rotated value
*/
#define __ROR __ror
/**
\brief Breakpoint
\details Causes the processor to enter Debug state.
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
\param [in] value is ignored by the processor.
If required, a debugger can use it to store additional information about the breakpoint.
*/
#define __BKPT(value) __breakpoint(value)
/**
\brief Reverse bit order of value
\details Reverses the bit order of the given value.
\param [in] value Value to reverse
\return Reversed value
*/
#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
#define __RBIT __rbit
#else
__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
{
uint32_t result;
int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */
result = value; /* r will be reversed bits of v; first get LSB of v */
for (value >>= 1U; value; value >>= 1U)
{
result <<= 1U;
result |= value & 1U;
s--;
}
result <<= s; /* shift when v's highest bits are zero */
return (result);
}
#endif
/**
\brief Count leading zeros
\details Counts the number of leading zeros of a data value.
\param [in] value Value to count the leading zeros
\return number of leading zeros in value
*/
#define __CLZ __clz
#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
/**
\brief LDR Exclusive (8 bit)
\details Executes a exclusive LDR instruction for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
#else
#define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop")
#endif
/**
\brief LDR Exclusive (16 bit)
\details Executes a exclusive LDR instruction for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
#else
#define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop")
#endif
/**
\brief LDR Exclusive (32 bit)
\details Executes a exclusive LDR instruction for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
#else
#define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop")
#endif
/**
\brief STR Exclusive (8 bit)
\details Executes a exclusive STR instruction for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __STREXB(value, ptr) __strex(value, ptr)
#else
#define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
#endif
/**
\brief STR Exclusive (16 bit)
\details Executes a exclusive STR instruction for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __STREXH(value, ptr) __strex(value, ptr)
#else
#define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
#endif
/**
\brief STR Exclusive (32 bit)
\details Executes a exclusive STR instruction for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __STREXW(value, ptr) __strex(value, ptr)
#else
#define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
#endif
/**
\brief Remove the exclusive lock
\details Removes the exclusive lock which is created by LDREX.
*/
#define __CLREX __clrex
/**
\brief Signed Saturate
\details Saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
#define __SSAT __ssat
/**
\brief Unsigned Saturate
\details Saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
#define __USAT __usat
/**
\brief Rotate Right with Extend (32 bit)
\details Moves each bit of a bitstring right by one bit.
The carry input is shifted in at the left end of the bitstring.
\param [in] value Value to rotate
\return Rotated value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
{
rrx r0, r0
bx lr
}
#endif
/**
\brief LDRT Unprivileged (8 bit)
\details Executes a Unprivileged LDRT instruction for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
/**
\brief LDRT Unprivileged (16 bit)
\details Executes a Unprivileged LDRT instruction for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
/**
\brief LDRT Unprivileged (32 bit)
\details Executes a Unprivileged LDRT instruction for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
/**
\brief STRT Unprivileged (8 bit)
\details Executes a Unprivileged STRT instruction for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
#define __STRBT(value, ptr) __strt(value, ptr)
/**
\brief STRT Unprivileged (16 bit)
\details Executes a Unprivileged STRT instruction for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
#define __STRHT(value, ptr) __strt(value, ptr)
/**
\brief STRT Unprivileged (32 bit)
\details Executes a Unprivileged STRT instruction for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
#define __STRT(value, ptr) __strt(value, ptr)
#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
/* ################### Compiler specific Intrinsics ########################### */
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
Access to dedicated SIMD instructions
@{
*/
#if (__CORTEX_M >= 0x04U) /* only for Cortex-M4 and above */
#define __SADD8 __sadd8
#define __QADD8 __qadd8
#define __SHADD8 __shadd8
#define __UADD8 __uadd8
#define __UQADD8 __uqadd8
#define __UHADD8 __uhadd8
#define __SSUB8 __ssub8
#define __QSUB8 __qsub8
#define __SHSUB8 __shsub8
#define __USUB8 __usub8
#define __UQSUB8 __uqsub8
#define __UHSUB8 __uhsub8
#define __SADD16 __sadd16
#define __QADD16 __qadd16
#define __SHADD16 __shadd16
#define __UADD16 __uadd16
#define __UQADD16 __uqadd16
#define __UHADD16 __uhadd16
#define __SSUB16 __ssub16
#define __QSUB16 __qsub16
#define __SHSUB16 __shsub16
#define __USUB16 __usub16
#define __UQSUB16 __uqsub16
#define __UHSUB16 __uhsub16
#define __SASX __sasx
#define __QASX __qasx
#define __SHASX __shasx
#define __UASX __uasx
#define __UQASX __uqasx
#define __UHASX __uhasx
#define __SSAX __ssax
#define __QSAX __qsax
#define __SHSAX __shsax
#define __USAX __usax
#define __UQSAX __uqsax
#define __UHSAX __uhsax
#define __USAD8 __usad8
#define __USADA8 __usada8
#define __SSAT16 __ssat16
#define __USAT16 __usat16
#define __UXTB16 __uxtb16
#define __UXTAB16 __uxtab16
#define __SXTB16 __sxtb16
#define __SXTAB16 __sxtab16
#define __SMUAD __smuad
#define __SMUADX __smuadx
#define __SMLAD __smlad
#define __SMLADX __smladx
#define __SMLALD __smlald
#define __SMLALDX __smlaldx
#define __SMUSD __smusd
#define __SMUSDX __smusdx
#define __SMLSD __smlsd
#define __SMLSDX __smlsdx
#define __SMLSLD __smlsld
#define __SMLSLDX __smlsldx
#define __SEL __sel
#define __QADD __qadd
#define __QSUB __qsub
#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
((int64_t)(ARG3) << 32U) ) >> 32U))
#endif /* (__CORTEX_M >= 0x04) */
/*@} end of group CMSIS_SIMD_intrinsics */
#endif /* __CMSIS_ARMCC_H */

1804
bsp/nuvoton/libraries/ma35/CMSIS/Include/cmsis_armcc_V6.h Normal file
View File

File diff suppressed because it is too large Load Diff

1377
bsp/nuvoton/libraries/ma35/CMSIS/Include/cmsis_gcc.h Normal file
View File

File diff suppressed because it is too large Load Diff

798
bsp/nuvoton/libraries/ma35/CMSIS/Include/core_cm0.h Normal file
View File

@ -0,0 +1,798 @@
/**************************************************************************//**
* @file core_cm0.h
* @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
* @version V4.30
* @date 20. October 2015
******************************************************************************/
/* Copyright (c) 2009 - 2015 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CORE_CM0_H_GENERIC
#define __CORE_CM0_H_GENERIC
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
CMSIS violates the following MISRA-C:2004 rules:
\li Required Rule 8.5, object/function definition in header file.<br>
Function definitions in header files are used to allow 'inlining'.
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Unions are used for effective representation of core registers.
\li Advisory Rule 19.7, Function-like macro defined.<br>
Function-like macros are used to allow more efficient code.
*/
/*******************************************************************************
* CMSIS definitions
******************************************************************************/
/**
\ingroup Cortex_M0
@{
*/
/* CMSIS CM0 definitions */
#define __CM0_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */
#define __CM0_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */
#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \
__CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
#define __CORTEX_M (0x00U) /*!< Cortex-M Core */
#if defined ( __CC_ARM )
#define __ASM __asm /*!< asm keyword for ARM Compiler */
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
#define __STATIC_INLINE static __inline
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#define __ASM __asm /*!< asm keyword for ARM Compiler */
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
#define __STATIC_INLINE static __inline
#elif defined ( __GNUC__ )
#define __ASM __asm /*!< asm keyword for GNU Compiler */
#define __INLINE inline /*!< inline keyword for GNU Compiler */
#define __STATIC_INLINE static inline
#elif defined ( __ICCARM__ )
#define __ASM __asm /*!< asm keyword for IAR Compiler */
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
#define __STATIC_INLINE static inline
#elif defined ( __TMS470__ )
#define __ASM __asm /*!< asm keyword for TI CCS Compiler */
#define __STATIC_INLINE static inline
#elif defined ( __TASKING__ )
#define __ASM __asm /*!< asm keyword for TASKING Compiler */
#define __INLINE inline /*!< inline keyword for TASKING Compiler */
#define __STATIC_INLINE static inline
#elif defined ( __CSMC__ )
#define __packed
#define __ASM _asm /*!< asm keyword for COSMIC Compiler */
#define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */
#define __STATIC_INLINE static inline
#else
#error Unknown compiler
#endif
/** __FPU_USED indicates whether an FPU is used or not.
This core does not support an FPU at all
*/
#define __FPU_USED 0U
#if defined ( __CC_ARM )
#if defined __TARGET_FPU_VFP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#if defined __ARM_PCS_VFP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __GNUC__ )
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __ICCARM__ )
#if defined __ARMVFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TMS470__ )
#if defined __TI_VFP_SUPPORT__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TASKING__ )
#if defined __FPU_VFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __CSMC__ )
#if ( __CSMC__ & 0x400U)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#endif
#include "core_cmInstr.h" /* Core Instruction Access */
#include "core_cmFunc.h" /* Core Function Access */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM0_H_GENERIC */
#ifndef __CMSIS_GENERIC
#ifndef __CORE_CM0_H_DEPENDANT
#define __CORE_CM0_H_DEPENDANT
#ifdef __cplusplus
extern "C" {
#endif
/* check device defines and use defaults */
#if defined __CHECK_DEVICE_DEFINES
#ifndef __CM0_REV
#define __CM0_REV 0x0000U
#warning "__CM0_REV not defined in device header file; using default!"
#endif
#ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 2U
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
#endif
#ifndef __Vendor_SysTickConfig
#define __Vendor_SysTickConfig 0U
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
#endif
#endif
/* IO definitions (access restrictions to peripheral registers) */
/**
\defgroup CMSIS_glob_defs CMSIS Global Defines
<strong>IO Type Qualifiers</strong> are used
\li to specify the access to peripheral variables.
\li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
/*@} end of group Cortex_M0 */
/*******************************************************************************
* Register Abstraction
Core Register contain:
- Core Register
- Core NVIC Register
- Core SCB Register
- Core SysTick Register
******************************************************************************/
/**
\defgroup CMSIS_core_register Defines and Type Definitions
\brief Type definitions and defines for Cortex-M processor based devices.
*/
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CORE Status and Control Registers
\brief Core Register type definitions.
@{
*/
/**
\brief Union type to access the Application Program Status Register (APSR).
*/
typedef union
{
struct
{
uint32_t _reserved0: 28; /*!< bit: 0..27 Reserved */
uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */
uint32_t C: 1; /*!< bit: 29 Carry condition code flag */
uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */
uint32_t N: 1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} APSR_Type;
/* APSR Register Definitions */
#define APSR_N_Pos 31U /*!< APSR: N Position */
#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
#define APSR_Z_Pos 30U /*!< APSR: Z Position */
#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
#define APSR_C_Pos 29U /*!< APSR: C Position */
#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
#define APSR_V_Pos 28U /*!< APSR: V Position */
#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
/**
\brief Union type to access the Interrupt Program Status Register (IPSR).
*/
typedef union
{
struct
{
uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0: 23; /*!< bit: 9..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} IPSR_Type;
/* IPSR Register Definitions */
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
/**
\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
*/
typedef union
{
struct
{
uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0: 15; /*!< bit: 9..23 Reserved */
uint32_t T: 1; /*!< bit: 24 Thumb bit (read 0) */
uint32_t _reserved1: 3; /*!< bit: 25..27 Reserved */
uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */
uint32_t C: 1; /*!< bit: 29 Carry condition code flag */
uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */
uint32_t N: 1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} xPSR_Type;
/* xPSR Register Definitions */
#define xPSR_N_Pos 31U /*!< xPSR: N Position */
#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
#define xPSR_C_Pos 29U /*!< xPSR: C Position */
#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
#define xPSR_V_Pos 28U /*!< xPSR: V Position */
#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
#define xPSR_T_Pos 24U /*!< xPSR: T Position */
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
/**
\brief Union type to access the Control Registers (CONTROL).
*/
typedef union
{
struct
{
uint32_t _reserved0: 1; /*!< bit: 0 Reserved */
uint32_t SPSEL: 1; /*!< bit: 1 Stack to be used */
uint32_t _reserved1: 30; /*!< bit: 2..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} CONTROL_Type;
/* CONTROL Register Definitions */
#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
/*@} end of group CMSIS_CORE */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
\brief Type definitions for the NVIC Registers
@{
*/
/**
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
*/
typedef struct
{
__IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
uint32_t RESERVED0[31U];
__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
uint32_t RSERVED1[31U];
__IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
uint32_t RESERVED2[31U];
__IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
uint32_t RESERVED3[31U];
uint32_t RESERVED4[64U];
__IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
} NVIC_Type;
/*@} end of group CMSIS_NVIC */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SCB System Control Block (SCB)
\brief Type definitions for the System Control Block Registers
@{
*/
/**
\brief Structure type to access the System Control Block (SCB).
*/
typedef struct
{
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
uint32_t RESERVED0;
__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
__IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
__IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
uint32_t RESERVED1;
__IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
} SCB_Type;
/* SCB CPUID Register Definitions */
#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
/* SCB Interrupt Control State Register Definitions */
#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
/* SCB Application Interrupt and Reset Control Register Definitions */
#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
/* SCB System Control Register Definitions */
#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
/* SCB Configuration Control Register Definitions */
#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
/* SCB System Handler Control and State Register Definitions */
#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
/*@} end of group CMSIS_SCB */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
\brief Type definitions for the System Timer Registers.
@{
*/
/**
\brief Structure type to access the System Timer (SysTick).
*/
typedef struct
{
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
} SysTick_Type;
/* SysTick Control / Status Register Definitions */
#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
/* SysTick Reload Register Definitions */
#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
/* SysTick Current Register Definitions */
#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
/* SysTick Calibration Register Definitions */
#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
/*@} end of group CMSIS_SysTick */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
\brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
Therefore they are not covered by the Cortex-M0 header file.
@{
*/
/*@} end of group CMSIS_CoreDebug */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_bitfield Core register bit field macros
\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
@{
*/
/**
\brief Mask and shift a bit field value for use in a register bit range.
\param[in] field Name of the register bit field.
\param[in] value Value of the bit field.
\return Masked and shifted value.
*/
#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)
/**
\brief Mask and shift a register value to extract a bit filed value.
\param[in] field Name of the register bit field.
\param[in] value Value of register.
\return Masked and shifted bit field value.
*/
#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)
/*@} end of group CMSIS_core_bitfield */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_base Core Definitions
\brief Definitions for base addresses, unions, and structures.
@{
*/
/* Memory mapping of Cortex-M0 Hardware */
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
/*@} */
/*******************************************************************************
* Hardware Abstraction Layer
Core Function Interface contains:
- Core NVIC Functions
- Core SysTick Functions
- Core Register Access Functions
******************************************************************************/
/**
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
*/
/* ########################## NVIC functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
\brief Functions that manage interrupts and exceptions via the NVIC.
@{
*/
/* Interrupt Priorities are WORD accessible only under ARMv6M */
/* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
/**
\brief Enable External Interrupt
\details Enables a device-specific interrupt in the NVIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
{
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
/**
\brief Disable External Interrupt
\details Disables a device-specific interrupt in the NVIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
{
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
/**
\brief Get Pending Interrupt
\details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.
\param [in] IRQn Interrupt number.
\return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending.
*/
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
return ((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
/**
\brief Set Pending Interrupt
\details Sets the pending bit of an external interrupt.
\param [in] IRQn Interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
/**
\brief Clear Pending Interrupt
\details Clears the pending bit of an external interrupt.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
/**
\brief Set Interrupt Priority
\details Sets the priority of an interrupt.
\note The priority cannot be set for every core interrupt.
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
*/
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
if ((int32_t)(IRQn) < 0)
{
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
else
{
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
}
/**
\brief Get Interrupt Priority
\details Reads the priority of an interrupt.
The interrupt number can be positive to specify an external (device specific) interrupt,
or negative to specify an internal (core) interrupt.
\param [in] IRQn Interrupt number.
\return Interrupt Priority.
Value is aligned automatically to the implemented priority bits of the microcontroller.
*/
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) < 0)
{
return ((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn)) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
else
{
return ((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn)) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
}
/**
\brief System Reset
\details Initiates a system reset request to reset the MCU.
*/
__STATIC_INLINE void NVIC_SystemReset(void)
{
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
SCB_AIRCR_SYSRESETREQ_Msk);
__DSB(); /* Ensure completion of memory access */
for (;;) /* wait until reset */
{
__NOP();
}
}
/*@} end of CMSIS_Core_NVICFunctions */
/* ################################## SysTick function ############################################ */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
\brief Functions that configure the System.
@{
*/
#if (__Vendor_SysTickConfig == 0U)
/**
\brief System Tick Configuration
\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
Counter is in free running mode to generate periodic interrupts.
\param [in] ticks Number of ticks between two interrupts.
\return 0 Function succeeded.
\return 1 Function failed.
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
{
return (1UL); /* Reload value impossible */
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
NVIC_SetPriority(SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
}
#endif
/*@} end of CMSIS_Core_SysTickFunctions */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM0_H_DEPENDANT */
#endif /* __CMSIS_GENERIC */

914
bsp/nuvoton/libraries/ma35/CMSIS/Include/core_cm0plus.h Normal file
View File

@ -0,0 +1,914 @@
/**************************************************************************//**
* @file core_cm0plus.h
* @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
* @version V4.30
* @date 20. October 2015
******************************************************************************/
/* Copyright (c) 2009 - 2015 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CORE_CM0PLUS_H_GENERIC
#define __CORE_CM0PLUS_H_GENERIC
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
CMSIS violates the following MISRA-C:2004 rules:
\li Required Rule 8.5, object/function definition in header file.<br>
Function definitions in header files are used to allow 'inlining'.
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Unions are used for effective representation of core registers.
\li Advisory Rule 19.7, Function-like macro defined.<br>
Function-like macros are used to allow more efficient code.
*/
/*******************************************************************************
* CMSIS definitions
******************************************************************************/
/**
\ingroup Cortex-M0+
@{
*/
/* CMSIS CM0+ definitions */
#define __CM0PLUS_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */
#define __CM0PLUS_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */
#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \
__CM0PLUS_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
#define __CORTEX_M (0x00U) /*!< Cortex-M Core */
#if defined ( __CC_ARM )
#define __ASM __asm /*!< asm keyword for ARM Compiler */
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
#define __STATIC_INLINE static __inline
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#define __ASM __asm /*!< asm keyword for ARM Compiler */
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
#define __STATIC_INLINE static __inline
#elif defined ( __GNUC__ )
#define __ASM __asm /*!< asm keyword for GNU Compiler */
#define __INLINE inline /*!< inline keyword for GNU Compiler */
#define __STATIC_INLINE static inline
#elif defined ( __ICCARM__ )
#define __ASM __asm /*!< asm keyword for IAR Compiler */
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
#define __STATIC_INLINE static inline
#elif defined ( __TMS470__ )
#define __ASM __asm /*!< asm keyword for TI CCS Compiler */
#define __STATIC_INLINE static inline
#elif defined ( __TASKING__ )
#define __ASM __asm /*!< asm keyword for TASKING Compiler */
#define __INLINE inline /*!< inline keyword for TASKING Compiler */
#define __STATIC_INLINE static inline
#elif defined ( __CSMC__ )
#define __packed
#define __ASM _asm /*!< asm keyword for COSMIC Compiler */
#define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */
#define __STATIC_INLINE static inline
#else
#error Unknown compiler
#endif
/** __FPU_USED indicates whether an FPU is used or not.
This core does not support an FPU at all
*/
#define __FPU_USED 0U
#if defined ( __CC_ARM )
#if defined __TARGET_FPU_VFP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#if defined __ARM_PCS_VFP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __GNUC__ )
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __ICCARM__ )
#if defined __ARMVFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TMS470__ )
#if defined __TI_VFP_SUPPORT__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TASKING__ )
#if defined __FPU_VFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __CSMC__ )
#if ( __CSMC__ & 0x400U)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#endif
#include "core_cmInstr.h" /* Core Instruction Access */
#include "core_cmFunc.h" /* Core Function Access */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM0PLUS_H_GENERIC */
#ifndef __CMSIS_GENERIC
#ifndef __CORE_CM0PLUS_H_DEPENDANT
#define __CORE_CM0PLUS_H_DEPENDANT
#ifdef __cplusplus
extern "C" {
#endif
/* check device defines and use defaults */
#if defined __CHECK_DEVICE_DEFINES
#ifndef __CM0PLUS_REV
#define __CM0PLUS_REV 0x0000U
#warning "__CM0PLUS_REV not defined in device header file; using default!"
#endif
#ifndef __MPU_PRESENT
#define __MPU_PRESENT 0U
#warning "__MPU_PRESENT not defined in device header file; using default!"
#endif
#ifndef __VTOR_PRESENT
#define __VTOR_PRESENT 0U
#warning "__VTOR_PRESENT not defined in device header file; using default!"
#endif
#ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 2U
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
#endif
#ifndef __Vendor_SysTickConfig
#define __Vendor_SysTickConfig 0U
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
#endif
#endif
/* IO definitions (access restrictions to peripheral registers) */
/**
\defgroup CMSIS_glob_defs CMSIS Global Defines
<strong>IO Type Qualifiers</strong> are used
\li to specify the access to peripheral variables.
\li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
/*@} end of group Cortex-M0+ */
/*******************************************************************************
* Register Abstraction
Core Register contain:
- Core Register
- Core NVIC Register
- Core SCB Register
- Core SysTick Register
- Core MPU Register
******************************************************************************/
/**
\defgroup CMSIS_core_register Defines and Type Definitions
\brief Type definitions and defines for Cortex-M processor based devices.
*/
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CORE Status and Control Registers
\brief Core Register type definitions.
@{
*/
/**
\brief Union type to access the Application Program Status Register (APSR).
*/
typedef union
{
struct
{
uint32_t _reserved0: 28; /*!< bit: 0..27 Reserved */
uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */
uint32_t C: 1; /*!< bit: 29 Carry condition code flag */
uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */
uint32_t N: 1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} APSR_Type;
/* APSR Register Definitions */
#define APSR_N_Pos 31U /*!< APSR: N Position */
#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
#define APSR_Z_Pos 30U /*!< APSR: Z Position */
#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
#define APSR_C_Pos 29U /*!< APSR: C Position */
#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
#define APSR_V_Pos 28U /*!< APSR: V Position */
#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
/**
\brief Union type to access the Interrupt Program Status Register (IPSR).
*/
typedef union
{
struct
{
uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0: 23; /*!< bit: 9..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} IPSR_Type;
/* IPSR Register Definitions */
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
/**
\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
*/
typedef union
{
struct
{
uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0: 15; /*!< bit: 9..23 Reserved */
uint32_t T: 1; /*!< bit: 24 Thumb bit (read 0) */
uint32_t _reserved1: 3; /*!< bit: 25..27 Reserved */
uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */
uint32_t C: 1; /*!< bit: 29 Carry condition code flag */
uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */
uint32_t N: 1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} xPSR_Type;
/* xPSR Register Definitions */
#define xPSR_N_Pos 31U /*!< xPSR: N Position */
#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
#define xPSR_C_Pos 29U /*!< xPSR: C Position */
#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
#define xPSR_V_Pos 28U /*!< xPSR: V Position */
#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
#define xPSR_T_Pos 24U /*!< xPSR: T Position */
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
/**
\brief Union type to access the Control Registers (CONTROL).
*/
typedef union
{
struct
{
uint32_t nPRIV: 1; /*!< bit: 0 Execution privilege in Thread mode */
uint32_t SPSEL: 1; /*!< bit: 1 Stack to be used */
uint32_t _reserved1: 30; /*!< bit: 2..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} CONTROL_Type;
/* CONTROL Register Definitions */
#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
/*@} end of group CMSIS_CORE */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
\brief Type definitions for the NVIC Registers
@{
*/
/**
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
*/
typedef struct
{
__IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
uint32_t RESERVED0[31U];
__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
uint32_t RSERVED1[31U];
__IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
uint32_t RESERVED2[31U];
__IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
uint32_t RESERVED3[31U];
uint32_t RESERVED4[64U];
__IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
} NVIC_Type;
/*@} end of group CMSIS_NVIC */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SCB System Control Block (SCB)
\brief Type definitions for the System Control Block Registers
@{
*/
/**
\brief Structure type to access the System Control Block (SCB).
*/
typedef struct
{
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
#if (__VTOR_PRESENT == 1U)
__IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
#else
uint32_t RESERVED0;
#endif
__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
__IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
__IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
uint32_t RESERVED1;
__IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
} SCB_Type;
/* SCB CPUID Register Definitions */
#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
/* SCB Interrupt Control State Register Definitions */
#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
#if (__VTOR_PRESENT == 1U)
/* SCB Interrupt Control State Register Definitions */
#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */
#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
#endif
/* SCB Application Interrupt and Reset Control Register Definitions */
#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
/* SCB System Control Register Definitions */
#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
/* SCB Configuration Control Register Definitions */
#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
/* SCB System Handler Control and State Register Definitions */
#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
/*@} end of group CMSIS_SCB */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
\brief Type definitions for the System Timer Registers.
@{
*/
/**
\brief Structure type to access the System Timer (SysTick).
*/
typedef struct
{
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
} SysTick_Type;
/* SysTick Control / Status Register Definitions */
#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
/* SysTick Reload Register Definitions */
#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
/* SysTick Current Register Definitions */
#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
/* SysTick Calibration Register Definitions */
#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
/*@} end of group CMSIS_SysTick */
#if (__MPU_PRESENT == 1U)
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_MPU Memory Protection Unit (MPU)
\brief Type definitions for the Memory Protection Unit (MPU)
@{
*/
/**
\brief Structure type to access the Memory Protection Unit (MPU).
*/
typedef struct
{
__IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
__IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
__IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
__IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
__IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
} MPU_Type;
/* MPU Type Register Definitions */
#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
/* MPU Control Register Definitions */
#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
/* MPU Region Number Register Definitions */
#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
/* MPU Region Base Address Register Definitions */
#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */
#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
/* MPU Region Attribute and Size Register Definitions */
#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
/*@} end of group CMSIS_MPU */
#endif
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
\brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
Therefore they are not covered by the Cortex-M0+ header file.
@{
*/
/*@} end of group CMSIS_CoreDebug */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_bitfield Core register bit field macros
\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
@{
*/
/**
\brief Mask and shift a bit field value for use in a register bit range.
\param[in] field Name of the register bit field.
\param[in] value Value of the bit field.
\return Masked and shifted value.
*/
#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)
/**
\brief Mask and shift a register value to extract a bit filed value.
\param[in] field Name of the register bit field.
\param[in] value Value of register.
\return Masked and shifted bit field value.
*/
#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)
/*@} end of group CMSIS_core_bitfield */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_base Core Definitions
\brief Definitions for base addresses, unions, and structures.
@{
*/
/* Memory mapping of Cortex-M0+ Hardware */
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
#if (__MPU_PRESENT == 1U)
#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
#endif
/*@} */
/*******************************************************************************
* Hardware Abstraction Layer
Core Function Interface contains:
- Core NVIC Functions
- Core SysTick Functions
- Core Register Access Functions
******************************************************************************/
/**
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
*/
/* ########################## NVIC functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
\brief Functions that manage interrupts and exceptions via the NVIC.
@{
*/
/* Interrupt Priorities are WORD accessible only under ARMv6M */
/* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
/**
\brief Enable External Interrupt
\details Enables a device-specific interrupt in the NVIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
{
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
/**
\brief Disable External Interrupt
\details Disables a device-specific interrupt in the NVIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
{
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
/**
\brief Get Pending Interrupt
\details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.
\param [in] IRQn Interrupt number.
\return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending.
*/
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
return ((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
/**
\brief Set Pending Interrupt
\details Sets the pending bit of an external interrupt.
\param [in] IRQn Interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
/**
\brief Clear Pending Interrupt
\details Clears the pending bit of an external interrupt.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
/**
\brief Set Interrupt Priority
\details Sets the priority of an interrupt.
\note The priority cannot be set for every core interrupt.
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
*/
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
if ((int32_t)(IRQn) < 0)
{
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
else
{
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
}
/**
\brief Get Interrupt Priority
\details Reads the priority of an interrupt.
The interrupt number can be positive to specify an external (device specific) interrupt,
or negative to specify an internal (core) interrupt.
\param [in] IRQn Interrupt number.
\return Interrupt Priority.
Value is aligned automatically to the implemented priority bits of the microcontroller.
*/
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) < 0)
{
return ((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn)) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
else
{
return ((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn)) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
}
/**
\brief System Reset
\details Initiates a system reset request to reset the MCU.
*/
__STATIC_INLINE void NVIC_SystemReset(void)
{
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
SCB_AIRCR_SYSRESETREQ_Msk);
__DSB(); /* Ensure completion of memory access */
for (;;) /* wait until reset */
{
__NOP();
}
}
/*@} end of CMSIS_Core_NVICFunctions */
/* ################################## SysTick function ############################################ */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
\brief Functions that configure the System.
@{
*/
#if (__Vendor_SysTickConfig == 0U)
/**
\brief System Tick Configuration
\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
Counter is in free running mode to generate periodic interrupts.
\param [in] ticks Number of ticks between two interrupts.
\return 0 Function succeeded.
\return 1 Function failed.
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
{
return (1UL); /* Reload value impossible */
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
NVIC_SetPriority(SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
}
#endif
/*@} end of CMSIS_Core_SysTickFunctions */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM0PLUS_H_DEPENDANT */
#endif /* __CMSIS_GENERIC */

1763
bsp/nuvoton/libraries/ma35/CMSIS/Include/core_cm3.h Normal file
View File

File diff suppressed because it is too large Load Diff

1937
bsp/nuvoton/libraries/ma35/CMSIS/Include/core_cm4.h Normal file
View File

File diff suppressed because it is too large Load Diff

2535
bsp/nuvoton/libraries/ma35/CMSIS/Include/core_cm7.h Normal file
View File

File diff suppressed because it is too large Load Diff

87
bsp/nuvoton/libraries/ma35/CMSIS/Include/core_cmFunc.h Normal file
View File

@ -0,0 +1,87 @@
/**************************************************************************//**
* @file core_cmFunc.h
* @brief CMSIS Cortex-M Core Function Access Header File
* @version V4.30
* @date 20. October 2015
******************************************************************************/
/* Copyright (c) 2009 - 2015 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CORE_CMFUNC_H
#define __CORE_CMFUNC_H
/* ########################### Core Function Access ########################### */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
@{
*/
/*------------------ RealView Compiler -----------------*/
#if defined ( __CC_ARM )
#include "cmsis_armcc.h"
/*------------------ ARM Compiler V6 -------------------*/
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#include "cmsis_armcc_V6.h"
/*------------------ GNU Compiler ----------------------*/
#elif defined ( __GNUC__ )
#include "cmsis_gcc.h"
/*------------------ ICC Compiler ----------------------*/
#elif defined ( __ICCARM__ )
#include <cmsis_iar.h>
/*------------------ TI CCS Compiler -------------------*/
#elif defined ( __TMS470__ )
#include <cmsis_ccs.h>
/*------------------ TASKING Compiler ------------------*/
#elif defined ( __TASKING__ )
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
/*------------------ COSMIC Compiler -------------------*/
#elif defined ( __CSMC__ )
#include <cmsis_csm.h>
#endif
/*@} end of CMSIS_Core_RegAccFunctions */
#endif /* __CORE_CMFUNC_H */

87
bsp/nuvoton/libraries/ma35/CMSIS/Include/core_cmInstr.h Normal file
View File

@ -0,0 +1,87 @@
/**************************************************************************//**
* @file core_cmInstr.h
* @brief CMSIS Cortex-M Core Instruction Access Header File
* @version V4.30
* @date 20. October 2015
******************************************************************************/
/* Copyright (c) 2009 - 2015 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CORE_CMINSTR_H
#define __CORE_CMINSTR_H
/* ########################## Core Instruction Access ######################### */
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
Access to dedicated instructions
@{
*/
/*------------------ RealView Compiler -----------------*/
#if defined ( __CC_ARM )
#include "cmsis_armcc.h"
/*------------------ ARM Compiler V6 -------------------*/
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#include "cmsis_armcc_V6.h"
/*------------------ GNU Compiler ----------------------*/
#elif defined ( __GNUC__ )
#include "cmsis_gcc.h"
/*------------------ ICC Compiler ----------------------*/
#elif defined ( __ICCARM__ )
#include <cmsis_iar.h>
/*------------------ TI CCS Compiler -------------------*/
#elif defined ( __TMS470__ )
#include <cmsis_ccs.h>
/*------------------ TASKING Compiler ------------------*/
#elif defined ( __TASKING__ )
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
/*------------------ COSMIC Compiler -------------------*/
#elif defined ( __CSMC__ )
#include <cmsis_csm.h>
#endif
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
#endif /* __CORE_CMINSTR_H */

96
bsp/nuvoton/libraries/ma35/CMSIS/Include/core_cmSimd.h Normal file
View File

@ -0,0 +1,96 @@
/**************************************************************************//**
* @file core_cmSimd.h
* @brief CMSIS Cortex-M SIMD Header File
* @version V4.30
* @date 20. October 2015
******************************************************************************/
/* Copyright (c) 2009 - 2015 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CORE_CMSIMD_H
#define __CORE_CMSIMD_H
#ifdef __cplusplus
extern "C" {
#endif
/* ################### Compiler specific Intrinsics ########################### */
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
Access to dedicated SIMD instructions
@{
*/
/*------------------ RealView Compiler -----------------*/
#if defined ( __CC_ARM )
#include "cmsis_armcc.h"
/*------------------ ARM Compiler V6 -------------------*/
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#include "cmsis_armcc_V6.h"
/*------------------ GNU Compiler ----------------------*/
#elif defined ( __GNUC__ )
#include "cmsis_gcc.h"
/*------------------ ICC Compiler ----------------------*/
#elif defined ( __ICCARM__ )
#include <cmsis_iar.h>
/*------------------ TI CCS Compiler -------------------*/
#elif defined ( __TMS470__ )
#include <cmsis_ccs.h>
/*------------------ TASKING Compiler ------------------*/
#elif defined ( __TASKING__ )
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
/*------------------ COSMIC Compiler -------------------*/
#elif defined ( __CSMC__ )
#include <cmsis_csm.h>
#endif
/*@} end of group CMSIS_SIMD_intrinsics */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CMSIMD_H */

926
bsp/nuvoton/libraries/ma35/CMSIS/Include/core_sc000.h Normal file
View File

@ -0,0 +1,926 @@
/**************************************************************************//**
* @file core_sc000.h
* @brief CMSIS SC000 Core Peripheral Access Layer Header File
* @version V4.30
* @date 20. October 2015
******************************************************************************/
/* Copyright (c) 2009 - 2015 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CORE_SC000_H_GENERIC
#define __CORE_SC000_H_GENERIC
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
CMSIS violates the following MISRA-C:2004 rules:
\li Required Rule 8.5, object/function definition in header file.<br>
Function definitions in header files are used to allow 'inlining'.
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Unions are used for effective representation of core registers.
\li Advisory Rule 19.7, Function-like macro defined.<br>
Function-like macros are used to allow more efficient code.
*/
/*******************************************************************************
* CMSIS definitions
******************************************************************************/
/**
\ingroup SC000
@{
*/
/* CMSIS SC000 definitions */
#define __SC000_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */
#define __SC000_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */
#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \
__SC000_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
#define __CORTEX_SC (000U) /*!< Cortex secure core */
#if defined ( __CC_ARM )
#define __ASM __asm /*!< asm keyword for ARM Compiler */
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
#define __STATIC_INLINE static __inline
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#define __ASM __asm /*!< asm keyword for ARM Compiler */
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
#define __STATIC_INLINE static __inline
#elif defined ( __GNUC__ )
#define __ASM __asm /*!< asm keyword for GNU Compiler */
#define __INLINE inline /*!< inline keyword for GNU Compiler */
#define __STATIC_INLINE static inline
#elif defined ( __ICCARM__ )
#define __ASM __asm /*!< asm keyword for IAR Compiler */
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
#define __STATIC_INLINE static inline
#elif defined ( __TMS470__ )
#define __ASM __asm /*!< asm keyword for TI CCS Compiler */
#define __STATIC_INLINE static inline
#elif defined ( __TASKING__ )
#define __ASM __asm /*!< asm keyword for TASKING Compiler */
#define __INLINE inline /*!< inline keyword for TASKING Compiler */
#define __STATIC_INLINE static inline
#elif defined ( __CSMC__ )
#define __packed
#define __ASM _asm /*!< asm keyword for COSMIC Compiler */
#define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */
#define __STATIC_INLINE static inline
#else
#error Unknown compiler
#endif
/** __FPU_USED indicates whether an FPU is used or not.
This core does not support an FPU at all
*/
#define __FPU_USED 0U
#if defined ( __CC_ARM )
#if defined __TARGET_FPU_VFP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#if defined __ARM_PCS_VFP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __GNUC__ )
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __ICCARM__ )
#if defined __ARMVFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TMS470__ )
#if defined __TI_VFP_SUPPORT__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TASKING__ )
#if defined __FPU_VFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __CSMC__ )
#if ( __CSMC__ & 0x400U)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#endif
#include "core_cmInstr.h" /* Core Instruction Access */
#include "core_cmFunc.h" /* Core Function Access */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_SC000_H_GENERIC */
#ifndef __CMSIS_GENERIC
#ifndef __CORE_SC000_H_DEPENDANT
#define __CORE_SC000_H_DEPENDANT
#ifdef __cplusplus
extern "C" {
#endif
/* check device defines and use defaults */
#if defined __CHECK_DEVICE_DEFINES
#ifndef __SC000_REV
#define __SC000_REV 0x0000U
#warning "__SC000_REV not defined in device header file; using default!"
#endif
#ifndef __MPU_PRESENT
#define __MPU_PRESENT 0U
#warning "__MPU_PRESENT not defined in device header file; using default!"
#endif
#ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 2U
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
#endif
#ifndef __Vendor_SysTickConfig
#define __Vendor_SysTickConfig 0U
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
#endif
#endif
/* IO definitions (access restrictions to peripheral registers) */
/**
\defgroup CMSIS_glob_defs CMSIS Global Defines
<strong>IO Type Qualifiers</strong> are used
\li to specify the access to peripheral variables.
\li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
/*@} end of group SC000 */
/*******************************************************************************
* Register Abstraction
Core Register contain:
- Core Register
- Core NVIC Register
- Core SCB Register
- Core SysTick Register
- Core MPU Register
******************************************************************************/
/**
\defgroup CMSIS_core_register Defines and Type Definitions
\brief Type definitions and defines for Cortex-M processor based devices.
*/
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CORE Status and Control Registers
\brief Core Register type definitions.
@{
*/
/**
\brief Union type to access the Application Program Status Register (APSR).
*/
typedef union
{
struct
{
uint32_t _reserved0: 28; /*!< bit: 0..27 Reserved */
uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */
uint32_t C: 1; /*!< bit: 29 Carry condition code flag */
uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */
uint32_t N: 1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} APSR_Type;
/* APSR Register Definitions */
#define APSR_N_Pos 31U /*!< APSR: N Position */
#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
#define APSR_Z_Pos 30U /*!< APSR: Z Position */
#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
#define APSR_C_Pos 29U /*!< APSR: C Position */
#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
#define APSR_V_Pos 28U /*!< APSR: V Position */
#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
/**
\brief Union type to access the Interrupt Program Status Register (IPSR).
*/
typedef union
{
struct
{
uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0: 23; /*!< bit: 9..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} IPSR_Type;
/* IPSR Register Definitions */
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
/**
\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
*/
typedef union
{
struct
{
uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0: 15; /*!< bit: 9..23 Reserved */
uint32_t T: 1; /*!< bit: 24 Thumb bit (read 0) */
uint32_t _reserved1: 3; /*!< bit: 25..27 Reserved */
uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */
uint32_t C: 1; /*!< bit: 29 Carry condition code flag */
uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */
uint32_t N: 1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} xPSR_Type;
/* xPSR Register Definitions */
#define xPSR_N_Pos 31U /*!< xPSR: N Position */
#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
#define xPSR_C_Pos 29U /*!< xPSR: C Position */
#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
#define xPSR_V_Pos 28U /*!< xPSR: V Position */
#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
#define xPSR_T_Pos 24U /*!< xPSR: T Position */
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
/**
\brief Union type to access the Control Registers (CONTROL).
*/
typedef union
{
struct
{
uint32_t _reserved0: 1; /*!< bit: 0 Reserved */
uint32_t SPSEL: 1; /*!< bit: 1 Stack to be used */
uint32_t _reserved1: 30; /*!< bit: 2..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} CONTROL_Type;
/* CONTROL Register Definitions */
#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
/*@} end of group CMSIS_CORE */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
\brief Type definitions for the NVIC Registers
@{
*/
/**
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
*/
typedef struct
{
__IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
uint32_t RESERVED0[31U];
__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
uint32_t RSERVED1[31U];
__IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
uint32_t RESERVED2[31U];
__IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
uint32_t RESERVED3[31U];
uint32_t RESERVED4[64U];
__IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
} NVIC_Type;
/*@} end of group CMSIS_NVIC */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SCB System Control Block (SCB)
\brief Type definitions for the System Control Block Registers
@{
*/
/**
\brief Structure type to access the System Control Block (SCB).
*/
typedef struct
{
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
__IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
__IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
__IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
uint32_t RESERVED0[1U];
__IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
uint32_t RESERVED1[154U];
__IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */
} SCB_Type;
/* SCB CPUID Register Definitions */
#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
/* SCB Interrupt Control State Register Definitions */
#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
/* SCB Interrupt Control State Register Definitions */
#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
/* SCB Application Interrupt and Reset Control Register Definitions */
#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
/* SCB System Control Register Definitions */
#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
/* SCB Configuration Control Register Definitions */
#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
/* SCB System Handler Control and State Register Definitions */
#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
/*@} end of group CMSIS_SCB */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
\brief Type definitions for the System Control and ID Register not in the SCB
@{
*/
/**
\brief Structure type to access the System Control and ID Register not in the SCB.
*/
typedef struct
{
uint32_t RESERVED0[2U];
__IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
} SCnSCB_Type;
/* Auxiliary Control Register Definitions */
#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
/*@} end of group CMSIS_SCnotSCB */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
\brief Type definitions for the System Timer Registers.
@{
*/
/**
\brief Structure type to access the System Timer (SysTick).
*/
typedef struct
{
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
} SysTick_Type;
/* SysTick Control / Status Register Definitions */
#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
/* SysTick Reload Register Definitions */
#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
/* SysTick Current Register Definitions */
#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
/* SysTick Calibration Register Definitions */
#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
/*@} end of group CMSIS_SysTick */
#if (__MPU_PRESENT == 1U)
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_MPU Memory Protection Unit (MPU)
\brief Type definitions for the Memory Protection Unit (MPU)
@{
*/
/**
\brief Structure type to access the Memory Protection Unit (MPU).
*/
typedef struct
{
__IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
__IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
__IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
__IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
__IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
} MPU_Type;
/* MPU Type Register Definitions */
#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
/* MPU Control Register Definitions */
#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
/* MPU Region Number Register Definitions */
#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
/* MPU Region Base Address Register Definitions */
#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */
#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
/* MPU Region Attribute and Size Register Definitions */
#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
/*@} end of group CMSIS_MPU */
#endif
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
\brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
Therefore they are not covered by the SC000 header file.
@{
*/
/*@} end of group CMSIS_CoreDebug */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_bitfield Core register bit field macros
\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
@{
*/
/**
\brief Mask and shift a bit field value for use in a register bit range.
\param[in] field Name of the register bit field.
\param[in] value Value of the bit field.
\return Masked and shifted value.
*/
#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)
/**
\brief Mask and shift a register value to extract a bit filed value.
\param[in] field Name of the register bit field.
\param[in] value Value of register.
\return Masked and shifted bit field value.
*/
#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)
/*@} end of group CMSIS_core_bitfield */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_base Core Definitions
\brief Definitions for base addresses, unions, and structures.
@{
*/
/* Memory mapping of SC000 Hardware */
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
#if (__MPU_PRESENT == 1U)
#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
#endif
/*@} */
/*******************************************************************************
* Hardware Abstraction Layer
Core Function Interface contains:
- Core NVIC Functions
- Core SysTick Functions
- Core Register Access Functions
******************************************************************************/
/**
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
*/
/* ########################## NVIC functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
\brief Functions that manage interrupts and exceptions via the NVIC.
@{
*/
/* Interrupt Priorities are WORD accessible only under ARMv6M */
/* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
/**
\brief Enable External Interrupt
\details Enables a device-specific interrupt in the NVIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
{
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
/**
\brief Disable External Interrupt
\details Disables a device-specific interrupt in the NVIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
{
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
/**
\brief Get Pending Interrupt
\details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.
\param [in] IRQn Interrupt number.
\return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending.
*/
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
return ((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
/**
\brief Set Pending Interrupt
\details Sets the pending bit of an external interrupt.
\param [in] IRQn Interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
/**
\brief Clear Pending Interrupt
\details Clears the pending bit of an external interrupt.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
/**
\brief Set Interrupt Priority
\details Sets the priority of an interrupt.
\note The priority cannot be set for every core interrupt.
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
*/
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
if ((int32_t)(IRQn) < 0)
{
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
else
{
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
}
/**
\brief Get Interrupt Priority
\details Reads the priority of an interrupt.
The interrupt number can be positive to specify an external (device specific) interrupt,
or negative to specify an internal (core) interrupt.
\param [in] IRQn Interrupt number.
\return Interrupt Priority.
Value is aligned automatically to the implemented priority bits of the microcontroller.
*/
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) < 0)
{
return ((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn)) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
else
{
return ((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn)) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
}
/**
\brief System Reset
\details Initiates a system reset request to reset the MCU.
*/
__STATIC_INLINE void NVIC_SystemReset(void)
{
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
SCB_AIRCR_SYSRESETREQ_Msk);
__DSB(); /* Ensure completion of memory access */
for (;;) /* wait until reset */
{
__NOP();
}
}
/*@} end of CMSIS_Core_NVICFunctions */
/* ################################## SysTick function ############################################ */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
\brief Functions that configure the System.
@{
*/
#if (__Vendor_SysTickConfig == 0U)
/**
\brief System Tick Configuration
\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
Counter is in free running mode to generate periodic interrupts.
\param [in] ticks Number of ticks between two interrupts.
\return 0 Function succeeded.
\return 1 Function failed.
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
{
return (1UL); /* Reload value impossible */
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
NVIC_SetPriority(SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
}
#endif
/*@} end of CMSIS_Core_SysTickFunctions */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_SC000_H_DEPENDANT */
#endif /* __CMSIS_GENERIC */

1745
bsp/nuvoton/libraries/ma35/CMSIS/Include/core_sc300.h Normal file
View File

File diff suppressed because it is too large Load Diff

14
bsp/nuvoton/libraries/ma35/CMSIS/SConscript Normal file
View File

@ -0,0 +1,14 @@
import rtconfig
Import('RTT_ROOT')
from building import *
# get current directory
group = []
if GetDepend('USE_MA35D1_SUBM'):
cwd = GetCurrentDir()
src = []
path = [cwd + '/Include',]
group = DefineGroup('CMSIS', src, depend = [''], CPPPATH = path)
Return('group')

15
bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/NuMicro.h Normal file
View File

@ -0,0 +1,15 @@
/**************************************************************************//**
* @file NuMicro.h
* @brief NuMicro peripheral access layer header file.
*
* SPDX-License-Identifier: Apache-2.0
* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __NUMICRO_H__
#define __NUMICRO_H__
#include "ma35d1.h"
#endif /* __NUMICRO_H__ */

378
bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/adc_reg.h Normal file
View File

@ -0,0 +1,378 @@
/**************************************************************************//**
* @file adc.h
* @brief ADC driver header file
*
* SPDX-License-Identifier: Apache-2.0
* @copyright (C) 2020~2021 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __ADC_REG_H__
#define __ADC_REG_H__
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
/**
@addtogroup REGISTER Control Register
@{
*/
/**
@addtogroup ADC Analog to Digital Converter(ADC)
Memory Mapped Structure for ADC Controller
@{ */
typedef struct
{
/**
* @var ADC_T::CTL
* Offset: 0x00 ADC Control
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |ADEN |ADC Power Control
* | | |0 = Power down ADC.
* | | |1 = Power on ADC.
* |[8] |MST |Menu Start Conversion
* | | |0 = Functional menu not started.
* | | |1 = Start all enable bit in ADC_CONF register.
* | | |Note: This bit is set by software and cleared by hardware when all the tasks listed in ADC_CONF are done.
* |[9] |PEDEEN |Pen Down Event Enable Bit
* | | |0 = Pen down event interrupt Disabled.
* | | |1 = Pen down event interrupt Enabled.
* |[11] |WKTEN |Touch Wake Up Enable Bit
* | | |0 = Touch wake-up Disabled.
* | | |1 = Touch wake-up Enabled.
* |[16] |WMSWCH |Wire Mode Switch for 5-wire/4-wire Configuration
* | | |0 = 4-wire mode.
* | | |1 = 5-wire mode.
* @var ADC_T::CONF
* Offset: 0x04 ADC Configure
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |TEN |Touch Detection Enable Bit
* | | |0 = Touch detection function Disabled.
* | | |1 = Touch detection function Enabled.
* |[1] |ZEN |Press Measure Enable Bit
* | | |1 = Press measure function Disabled.
* | | |1 = Press measure function Enabled.
* |[2] |NACEN |Normal A/D Conversion Enable Bit
* | | |ADC normal conversion function enable
* | | |0 = Normal A/D Conversion Disabled.
* | | |1 = Normal A/D Conversion Enabled.
* |[7:6] |REFSEL |ADC Reference Select
* | | |ADC reference voltage select when ADC operate in normal conversion.
* | | |00 = AGND33 vs VREF input.
* | | |01 = YM vs YP.
* | | |10 = XM vs XP.
* | | |11 = AGND33 vs AVDD33.
* |[14:12] |CHSEL |Channel Selection
* | | |ADC input channel selection.
* | | |000 = VREF.
* | | |001 = A1.
* | | |010 = A2.
* | | |011 = VSENSE.
* | | |100 = YM.
* | | |101 = YP.
* | | |110 = XM.
* | | |111 = XP.
* |[20] |TMAVDIS |Display T Mean Average Disable Bit
* | | |Touch mean average for X and Y function disable bit.
* | | |0 = Touch mean average for X and Y function Enabled.
* | | |1 = Touch mean average for X and Y function Disabled.
* |[21] |ZMAVDIS |Display Z Mean Average Disable Bit
* | | |Pressure mean average for Z1 and Z2 function disable bit.
* | | |0 = Pressure mean average for Z1 and Z2 function Enabled.
* | | |1 = Pressure mean average for Z1 and Z2 function Disabled.
* |[22] |SPEED |Speed Mode Selection
* | | |0 = All ADC channels set to high speed mode.
* | | |1 = All ADC channels set to low speed mode.
* @var ADC_T::IER
* Offset: 0x08 ADC Interrupt Enable Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |MIEN |Menu Interrupt Enable Bit
* | | |Function menu complete interrupt enable.
* | | |0 = Menu interrupt Disabled.
* | | |1 = Menu interrupt Enabled.
* |[2] |PEDEIEN |Pen Down Event Interrupt Enable Bit
* | | |0 = Pen down event detection interrupt Disabled.
* | | |1 = Pen down event detection interrupt Enabled.
* |[3] |WKTIEN |Wake Up Touch Interrupt Enable Bit
* | | |0 = Wake up touch detection interrupt Disabled.
* | | |1 = Wake up touch detection interrupt Enabled.
* |[6] |PEUEIEN |Pen Up Event Interrupt Enable Bit
* | | |0 = Pen up event detection interrupt Disabled.
* | | |1 = Pen up event detection interrupt Enabled.
* @var ADC_T::ISR
* Offset: 0x0C ADC Interrupt Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |MF |Menu Complete Flag
* | | |Function menu complete status indicator.
* | | |Note: Set by hardware and write 1 to clear this bit.
* |[2] |PEDEF |Pen Down Event Flag
* | | |Pen down event status indicator.
* | | |Note: Set by hardware and write 1 to clear this bit.
* |[4] |PEUEF |Pen Up Event Flag
* | | |Pen up event status indicator.
* | | |Note: Set by hardware and write 1 to clear this bit.
* |[8] |TF |Touch Conversion Finish
* | | |Functional menu touch detection conversion finish.
* | | |Note: Set by hardware and write 1 to clear this bit.
* |[9] |ZF |Press Conversion Finish
* | | |Functional menu press measure conversion finish.
* | | |Note: Set by hardware and write 1 to clear this bit.
* |[10] |NACF |Normal AD Conversion Finish
* | | |Functional menu normal AD conversion finish.
* | | |Note: Set by hardware and write 1 to clear this bit.
* |[17] |INTTC |Interrupt Signal for Touch Screen Touching Detection
* | | |This signal is directly from analog macro without de-bouncing and can be used to determine the pen down touch event together with PEDEF (ADC_ISR[2]) flag.
* @var ADC_T::WKISR
* Offset: 0x10 ADC Wake-up interrupt Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[1] |WPEDEF |Wake Up Pen Down Event Flag
* | | |Pen down event wake up status indicator.
* @var ADC_T::XYDATA
* Offset: 0x20 ADC Touch X,Y Position Data
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[11:0] |XDATA |ADC X Data
* | | |When TEN (ADC_CONF[0]) is set, the touch x-position will be stored in this register.
* | | |Note: If the TMAVDIS (ADC_CONF[20]) = 0, both x and y position are the results of the mean average of x and y in ADC_XYSORT0 ~ ADC_XYSORT3.
* |[27:16] |YDATA |ADC Y Data
* | | |When TEN (ADC_CONF[0]) is set, the touch y-position will be stored in this register.
* | | |Note: If the TMAVDIS (ADC_CONF[20]) = 0, both x and y position are the results of the mean average of x and y in ADC_XYSORT0 ~ ADC_XYSORT3.
* @var ADC_T::ZDATA
* Offset: 0x24 ADC Touch Z Pressure Data
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[11:0] |Z1DATA |ADC Z1 Data
* | | |When ZEN (ADC_CONF[1]) is set; the touch pressure measure Z1 will be stored in this register.
* | | |Note: If the ZMAVDIS (ADC_CONF[21]) = 0, both Z1 and Z2 data is the results of the mean average of Z1 and Z2 in ADC_ZSORT0 ~ ADC_ZSORT3.
* |[27:16] |Z2DATA |ADC Z2 Data
* | | |When ZEN (ADC_CONF[1]) is set; the touch pressure measure Z2 will be stored in this register.
* | | |Note: If the ZMAVDIS (ADC_CONF[21]) = 0, both Z1 and Z2 data is the results of the mean average of Z1 and Z2 in ADC_ZSORT0 ~ ADC_ZSORT3.
* @var ADC_T::DATA
* Offset: 0x28 ADC Normal Conversion Data
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[11:0] |ADCDATA |ADC Data
* | | |When NACEN (ADC_CONF[2]) is enabled, the AD converting result with corresponding channel is stored in this register.
* @var ADC_T::XYSORT0
* Offset: 0x1F4 ADC Touch XY Position Mean Value Sort 0
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[11:0] |XSORT0 |X Position Sort Data 0
* | | |X position mean average sort data 0.
* |[27:16] |YSORT0 |Y Position Sort Data 0
* | | |Y position mean average sort data 0.
* @var ADC_T::XYSORT1
* Offset: 0x1F8 ADC Touch XY Position Mean Value Sort 1
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[11:0] |XSORT1 |X Position Sort Data 1
* | | |X position mean average sort data 1.
* |[27:16] |YSORT1 |Y Position Sort Data 1
* | | |Y position mean average sort data 1.
* @var ADC_T::XYSORT2
* Offset: 0x1FC ADC Touch XY Position Mean Value Sort 2
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[11:0] |XSORT2 |X Position Sort Data 2
* | | |X position mean average sort data 2.
* |[27:16] |YSORT2 |Y Position Sort Data 2
* | | |Y position mean average sort data 2.
* @var ADC_T::XYSORT3
* Offset: 0x200 ADC Touch XY Position Mean Value Sort 3
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[11:0] |XSORT3 |X Position Sort Data 3
* | | |X position mean average sort data 3.
* |[27:16] |YSORT3 |Y Position Sort Data 3
* | | |Y position mean average sort data 3.
* @var ADC_T::ZSORT0
* Offset: 0x204 ADC Touch Z Pressure Mean Value Sort 0
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[11:0] |Z1SORT0 |Z1 Position Sort Data 0
* | | |Z1 position Mean average sort data 0.
* |[27:16] |Z2SORT0 |Z2 Position Sort Data 0
* | | |Z2 position Mean average sort data 0.
* @var ADC_T::ZSORT1
* Offset: 0x208 ADC Touch Z Pressure Mean Value Sort 1
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[11:0] |Z1SORT1 |Z1 Position Sort Data 1
* | | |Z1 position Mean average sort data 1.
* |[27:16] |Z2SORT1 |Z2 Position Sort Data 1
* | | |Z2 position Mean average sort data 1.
* @var ADC_T::ZSORT2
* Offset: 0x20C ADC Touch Z Pressure Mean Value Sort 2
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[11:0] |Z1SORT2 |Z1 Position Sort Data 2
* | | |Z1 position Mean average sort data 2.
* |[27:16] |Z2SORT2 |Z2 Position Sort Data 2
* | | |Z2 position Mean average sort data 2.
* @var ADC_T::ZSORT3
* Offset: 0x210 ADC Touch Z Pressure Mean Value Sort 3
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[11:0] |Z1SORT3 |Z1 Position Sort Data 3
* | | |Z1 position Mean average sort data 3.
* |[27:16] |Z2SORT3 |Z2 Position Sort Data 3
* | | |Z2 position Mean average sort data 3.
*/
__IO uint32_t CTL; /*!< [0x0000] ADC Control */
__IO uint32_t CONF; /*!< [0x0004] ADC Configure */
__IO uint32_t IER; /*!< [0x0008] ADC Interrupt Enable Register */
__IO uint32_t ISR; /*!< [0x000c] ADC Interrupt Status Register */
__I uint32_t WKISR; /*!< [0x0010] ADC Wake-up interrupt Status Register */
__I uint32_t RESERVE0[3];
__I uint32_t XYDATA; /*!< [0x0020] ADC Touch X,Y Position Data */
__I uint32_t ZDATA; /*!< [0x0024] ADC Touch Z Pressure Data */
__I uint32_t DATA; /*!< [0x0028] ADC Normal Conversion Data */
__I uint32_t RESERVE1[114];
__I uint32_t XYSORT[4]; /*!< [0x01f4~0x0200] ADC Touch XY Position Mean Value Sort Register */
__I uint32_t ZSORT0[4]; /*!< [0x0204~0x0210] ADC Touch Z Pressure Mean Value Sort Register */
} ADC_T;
/**
@addtogroup ADC_CONST ADC Bit Field Definition
Constant Definitions for ADC Controller
@{ */
#define ADC_CTL_ADEN_Pos (0) /*!< ADC_T::CTL: ADEN Position */
#define ADC_CTL_ADEN_Msk (0x1ul << ADC_CTL_ADEN_Pos) /*!< ADC_T::CTL: ADEN Mask */
#define ADC_CTL_MST_Pos (8) /*!< ADC_T::CTL: MST Position */
#define ADC_CTL_MST_Msk (0x1ul << ADC_CTL_MST_Pos) /*!< ADC_T::CTL: MST Mask */
#define ADC_CTL_PEDEEN_Pos (9) /*!< ADC_T::CTL: PEDEEN Position */
#define ADC_CTL_PEDEEN_Msk (0x1ul << ADC_CTL_PEDEEN_Pos) /*!< ADC_T::CTL: PEDEEN Mask */
#define ADC_CTL_WKTEN_Pos (11) /*!< ADC_T::CTL: WKTEN Position */
#define ADC_CTL_WKTEN_Msk (0x1ul << ADC_CTL_WKTEN_Pos) /*!< ADC_T::CTL: WKTEN Mask */
#define ADC_CTL_WMSWCH_Pos (16) /*!< ADC_T::CTL: WMSWCH Position */
#define ADC_CTL_WMSWCH_Msk (0x1ul << ADC_CTL_WMSWCH_Pos) /*!< ADC_T::CTL: WMSWCH Mask */
#define ADC_CONF_TEN_Pos (0) /*!< ADC_T::CONF: TEN Position */
#define ADC_CONF_TEN_Msk (0x1ul << ADC_CONF_TEN_Pos) /*!< ADC_T::CONF: TEN Mask */
#define ADC_CONF_ZEN_Pos (1) /*!< ADC_T::CONF: ZEN Position */
#define ADC_CONF_ZEN_Msk (0x1ul << ADC_CONF_ZEN_Pos) /*!< ADC_T::CONF: ZEN Mask */
#define ADC_CONF_NACEN_Pos (2) /*!< ADC_T::CONF: NACEN Position */
#define ADC_CONF_NACEN_Msk (0x1ul << ADC_CONF_NACEN_Pos) /*!< ADC_T::CONF: NACEN Mask */
#define ADC_CONF_REFSEL_Pos (6) /*!< ADC_T::CONF: REFSEL Position */
#define ADC_CONF_REFSEL_Msk (0x3ul << ADC_CONF_REFSEL_Pos) /*!< ADC_T::CONF: REFSEL Mask */
#define ADC_CONF_CHSEL_Pos (12) /*!< ADC_T::CONF: CHSEL Position */
#define ADC_CONF_CHSEL_Msk (0x7ul << ADC_CONF_CHSEL_Pos) /*!< ADC_T::CONF: CHSEL Mask */
#define ADC_CONF_TMAVDIS_Pos (20) /*!< ADC_T::CONF: TMAVDIS Position */
#define ADC_CONF_TMAVDIS_Msk (0x1ul << ADC_CONF_TMAVDIS_Pos) /*!< ADC_T::CONF: TMAVDIS Mask */
#define ADC_CONF_ZMAVDIS_Pos (21) /*!< ADC_T::CONF: ZMAVDIS Position */
#define ADC_CONF_ZMAVDIS_Msk (0x1ul << ADC_CONF_ZMAVDIS_Pos) /*!< ADC_T::CONF: ZMAVDIS Mask */
#define ADC_CONF_SPEED_Pos (22) /*!< ADC_T::CONF: SPEED Position */
#define ADC_CONF_SPEED_Msk (0x1ul << ADC_CONF_SPEED_Pos) /*!< ADC_T::CONF: SPEED Mask */
#define ADC_IER_MIEN_Pos (0) /*!< ADC_T::IER: MIEN Position */
#define ADC_IER_MIEN_Msk (0x1ul << ADC_IER_MIEN_Pos) /*!< ADC_T::IER: MIEN Mask */
#define ADC_IER_PEDEIEN_Pos (2) /*!< ADC_T::IER: PEDEIEN Position */
#define ADC_IER_PEDEIEN_Msk (0x1ul << ADC_IER_PEDEIEN_Pos) /*!< ADC_T::IER: PEDEIEN Mask */
#define ADC_IER_WKTIEN_Pos (3) /*!< ADC_T::IER: WKTIEN Position */
#define ADC_IER_WKTIEN_Msk (0x1ul << ADC_IER_WKTIEN_Pos) /*!< ADC_T::IER: WKTIEN Mask */
#define ADC_IER_PEUEIEN_Pos (6) /*!< ADC_T::IER: PEUEIEN Position */
#define ADC_IER_PEUEIEN_Msk (0x1ul << ADC_IER_PEUEIEN_Pos) /*!< ADC_T::IER: PEUEIEN Mask */
#define ADC_ISR_MF_Pos (0) /*!< ADC_T::ISR: MF Position */
#define ADC_ISR_MF_Msk (0x1ul << ADC_ISR_MF_Pos) /*!< ADC_T::ISR: MF Mask */
#define ADC_ISR_PEDEF_Pos (2) /*!< ADC_T::ISR: PEDEF Position */
#define ADC_ISR_PEDEF_Msk (0x1ul << ADC_ISR_PEDEF_Pos) /*!< ADC_T::ISR: PEDEF Mask */
#define ADC_ISR_PEUEF_Pos (4) /*!< ADC_T::ISR: PEUEF Position */
#define ADC_ISR_PEUEF_Msk (0x1ul << ADC_ISR_PEUEF_Pos) /*!< ADC_T::ISR: PEUEF Mask */
#define ADC_ISR_TF_Pos (8) /*!< ADC_T::ISR: TF Position */
#define ADC_ISR_TF_Msk (0x1ul << ADC_ISR_TF_Pos) /*!< ADC_T::ISR: TF Mask */
#define ADC_ISR_ZF_Pos (9) /*!< ADC_T::ISR: ZF Position */
#define ADC_ISR_ZF_Msk (0x1ul << ADC_ISR_ZF_Pos) /*!< ADC_T::ISR: ZF Mask */
#define ADC_ISR_NACF_Pos (10) /*!< ADC_T::ISR: NACF Position */
#define ADC_ISR_NACF_Msk (0x1ul << ADC_ISR_NACF_Pos) /*!< ADC_T::ISR: NACF Mask */
#define ADC_ISR_INTTC_Pos (17) /*!< ADC_T::ISR: INTTC Position */
#define ADC_ISR_INTTC_Msk (0x1ul << ADC_ISR_INTTC_Pos) /*!< ADC_T::ISR: INTTC Mask */
#define ADC_WKISR_WPEDEF_Pos (1) /*!< ADC_T::WKISR: WPEDEF Position */
#define ADC_WKISR_WPEDEF_Msk (0x1ul << ADC_WKISR_WPEDEF_Pos) /*!< ADC_T::WKISR: WPEDEF Mask */
#define ADC_XYDATA_XDATA_Pos (0) /*!< ADC_T::XYDATA: XDATA Position */
#define ADC_XYDATA_XDATA_Msk (0xffful << ADC_XYDATA_XDATA_Pos) /*!< ADC_T::XYDATA: XDATA Mask */
#define ADC_XYDATA_YDATA_Pos (16) /*!< ADC_T::XYDATA: YDATA Position */
#define ADC_XYDATA_YDATA_Msk (0xffful << ADC_XYDATA_YDATA_Pos) /*!< ADC_T::XYDATA: YDATA Mask */
#define ADC_ZDATA_Z1DATA_Pos (0) /*!< ADC_T::ZDATA: Z1DATA Position */
#define ADC_ZDATA_Z1DATA_Msk (0xffful << ADC_ZDATA_Z1DATA_Pos) /*!< ADC_T::ZDATA: Z1DATA Mask */
#define ADC_ZDATA_Z2DATA_Pos (16) /*!< ADC_T::ZDATA: Z2DATA Position */
#define ADC_ZDATA_Z2DATA_Msk (0xffful << ADC_ZDATA_Z2DATA_Pos) /*!< ADC_T::ZDATA: Z2DATA Mask */
#define ADC_DATA_ADCDATA_Pos (0) /*!< ADC_T::DATA: ADCDATA Position */
#define ADC_DATA_ADCDATA_Msk (0xffful << ADC_DATA_ADCDATA_Pos) /*!< ADC_T::DATA: ADCDATA Mask */
#define ADC_XYSORT_XSORT_Pos (0) /*!< ADC_T::XYSORT: XSORT Position */
#define ADC_XYSORT_XSORT_Msk (0xffful << ADC_XYSORT_XSORT_Pos) /*!< ADC_T::XYSORT: XSORT Mask */
#define ADC_XYSORT_YSORT_Pos (16) /*!< ADC_T::XYSORT: YSORT Position */
#define ADC_XYSORT_YSORT_Msk (0xffful << ADC_XYSORT_YSORT_Pos) /*!< ADC_T::XYSORT: YSORT Mask */
#define ADC_ZSORT_Z1SORT_Pos (0) /*!< ADC_T::ZSORT: Z1SORT Position */
#define ADC_ZSORT_Z1SORT_Msk (0xffful << ADC_ZSORT_Z1SORT_Pos) /*!< ADC_T::ZSORT: Z1SORT Mask */
#define ADC_ZSORT_Z2SORT_Pos (16) /*!< ADC_T::ZSORT: Z2SORT Position */
#define ADC_ZSORT_Z2SORT_Msk (0xffful << ADC_ZSORT_Z2SORT_Pos) /*!< ADC_T::ZSORT: Z2SORT Mask */
/**@}*/ /* ADC_CONST */
/**@}*/ /* end of ADC register group */
/**@}*/ /* end of REGISTER group */
#if defined ( __CC_ARM )
#pragma no_anon_unions
#endif
#endif //__ADC_REG_H__

1709
bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/canfd_reg.h Normal file
View File

File diff suppressed because it is too large Load Diff

453
bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/ccap_reg.h Normal file
View File

@ -0,0 +1,453 @@
/**************************************************************************//**
* @file ccap_reg.h
* @version V3.00
* @brief CCAP register definition header file
*
* @copyright SPDX-License-Identifier: Apache-2.0
* @copyright (C) 2021 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __CCAP_REG_H__
#define __CCAP_REG_H__
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
/**
@addtogroup REGISTER Control Register
@{
*/
/**
@addtogroup CCAP Camera Capture Interface Controller (CCAP)
Memory Mapped Structure for CCAP Controller
@{ */
typedef struct
{
/**
* @var CCAP_T::CTL
* Offset: 0x00 Camera Capture Interface Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |CCAPEN |Camera Capture Interface Enable Bit
* | | |0 = Camera Capture Interface Disabled.
* | | |1 = Camera Capture Interface Enabled.
* |[6] |PKTEN |Packet Output Enable Bit
* | | |0 = Packet output Disabled.
* | | |1 = Packet output Enabled.
* |[7] |MONO |Monochrome CMOS Sensor Select
* | | |0 = Color CMOS Sensor.
* | | |1 = Monochrome CMOS Sensor. The U/V components are ignored when the MONO is enabled.
* |[16] |SHUTTER |Camera Capture Interface Automatically Disable the Capture Interface After a Frame Had Been Captured
* | | |0 = Shutter Disabled.
* | | |1 = Shutter Enabled.
* |[17] |MY4_SWAP |Monochrome CMOS Sensor 4-bit Data Nibble Swap
* | | |0 = The 4-bit data input sequence: 1st Pixel is for 1st Nibble (1st pixel at MSB).
* | | |1 = The 4-bit data input sequence: 1st Pixel is for 2nd Nibble (1st pixel at LSB).
* |[18] |MY8_MY4 |Monochrome CMOS Sensor Data I/O Interface
* | | |0 = Monochrome CMOS sensor is by the 4-bit data I/O interface.
* | | |1 = Monochrome CMOS sensor is by the 8-bit data I/O interface.
* |[19] |Luma_Y_One|Color/Monochrome CMOS Sensor Luminance 8-bit Y to 1-bit Y Conversion
* | | |0 = Color/Monochrome CMOS sensor Luma-Y-One bit Disabled.
* | | |1 = Color/Monochrome CMOS sensor Luma-Y-One bit Enabled.
* | | |Note: Color CMOS sensor U/V components are ignored when the Luma_Y_One is enabled.
* |[20] |UPDATE |Update Register at New Frame
* | | |0 = Update register at new frame Disabled.
* | | |1 = Update register at new frame Enabled (Auto clear to 0 when register updated).
* |[24] |VPRST |Capture Interface Reset
* | | |0 = Capture interface reset Disabled.
* | | |1 = Capture interface reset Enabled.
* @var CCAP_T::PAR
* Offset: 0x04 Camera Capture Interface Parameter Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |INFMT |Sensor Input Data Format
* | | |0 = YCbCr422.
* | | |1 = RGB565.
* |[1] |SENTYPE |Sensor Input Type
* | | |0 = CCIR601.
* | | |1 = CCIR656, VSync & Hsync embedded in the data signal.
* |[3:2] |INDATORD |Sensor Input Data Order
* | | |If INFMT (CCAP_PAR[0]) = 0 (YCbCr):
* | | |00 = Sensor input data (Byte 0 1 2 3) is Y0 U0 Y1 V0.
* | | |01 = Sensor input data (Byte 0 1 2 3) is Y0 V0 Y1 U0.
* | | |10 = Sensor input data (Byte 0 1 2 3) is U0 Y0 V0 Y1.
* | | |11 = Sensor input data (Byte 0 1 2 3) is V0 Y0 U0 Y1.
* | | |If INFMT (CCAP_PAR[0]) = 1 (RGB565):
* | | |00 = Sensor input data (Byte 0) is {R[4:0],G[5:3]}. Sensor input data (Byte 1) is {G[2:0], B[4:0]}.
* | | |01 = Sensor input data (Byte 0) is {B[4:0],G[5:3]}. Sensor input data (Byte 1) is {G[2:0], R[4:0]}.
* | | |10 = Sensor input data (Byte 0) is {G[2:0],B[4:0]}. Sensor input data (Byte 1) is {R[4:0], G[5:3]}.
* | | |11 = Sensor input data (Byte 0) is {G[2:0],R[4:0]}. Sensor input data (Byte 1) is {B[4:0], G[5:3]}.
* |[5:4] |OUTFMT |Image Data Format Output to System Memory
* | | |00 = YCbCr422.
* | | |01 = Only output Y. (Select this format when CCAP_CTL "Luma_Y_One" or "MONO" enabled).
* | | |10 = RGB555.
* | | |11 = RGB565.
* |[6] |RANGE |Scale Input YUV CCIR601 Color Range to Full Range
* | | |0 = Default.
* | | |1 = Scale to full range.
* |[8] |PCLKP |Sensor Pixel Clock Polarity
* | | |0 = Input video data and signals are latched by falling edge of Pixel Clock.
* | | |1 = Input video data and signals are latched by rising edge of Pixel Clock.
* |[9] |HSP |Sensor Hsync Polarity
* | | |0 = Sync Low.
* | | |1 = Sync High.
* |[10] |VSP |Sensor Vsync Polarity
* | | |0 = Sync Low.
* | | |1 = Sync High.
* |[18] |FBB |Field by Blank
* | | |Field by Blank (only in ccir-656 mode) means blanking pixel data(0x80108010) have to transfer to system memory or not.
* | | |0 = Field by blank Disabled. (blank pixel data will transfer to system memory).
* | | |1 = Field by blank Enabled. (only active data will transfer to system memory).
* @var CCAP_T::INT
* Offset: 0x08 Camera Capture Interface Interrupt Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |VINTF |Video Frame End Interrupt
* | | |0 = Did not receive a frame completely.
* | | |1 = Received a frame completely.
* | | |Note: This bit is cleared by writing 1 to it.
* |[1] |MEINTF |Bus Master Transfer Error Interrupt
* | | |0 = Transfer Error did not occur.
* | | |1 = Transfer Error occurred.
* | | |Note: This bit is cleared by writing 1 to it.
* |[3] |ADDRMINTF |Memory Address Match Interrupt
* | | |0 = Memory Address Match Interrupt did not occur.
* | | |1 = Memory Address Match Interrupt occurred.
* | | |Note: This bit is cleared by writing 1 to it.
* |[16] |VIEN |Video Frame End Interrupt Enable Bit
* | | |0 = Video frame end interrupt Disabled.
* | | |1 = Video frame end interrupt Enabled.
* |[17] |MEIEN |Bus Master Transfer Error Interrupt Enable Bit
* | | |0 = Bus Master Transfer error interrupt Disabled.
* | | |1 = Bus Master Transfer error interrupt Enabled.
* |[19] |ADDRMIEN |Memory Address Match Interrupt Enable Bit
* | | |0 = Memory address match interrupt Disabled.
* | | |1 = Memory address match interrupt Enabled.
* @var CCAP_T::CWSP
* Offset: 0x20 Cropping Window Starting Address Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[11:0] |CWSADDRH |Cropping Window Horizontal Starting Address
* | | |Specify the value of the cropping window horizontal start address.
* |[26:16] |CWSADDRV |Cropping Window Vertical Starting Address
* | | |Specify the value of the cropping window vertical start address.
* @var CCAP_T::CWS
* Offset: 0x24 Cropping Window Size Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[11:0] |CWW |Cropping Window Width
* | | |Specify the size of the cropping window width.
* |[26:16] |CWH |Cropping Window Height
* | | |Specify the size of the cropping window height.
* @var CCAP_T::PKTSL
* Offset: 0x28 Packet Scaling Vertical/Horizontal Factor Register (LSB)
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |PKTSHML |Packet Scaling Horizontal Factor M
* | | |Specifies the lower 8-bit of denominator part (M) of the horizontal scaling factor.
* | | |The lower 8-bit will be cascaded with higher 8-bit (PKDSHMH) to form a 16-bit denominator (M) of vertical factor.
* | | |The output image width will be equal to the image width * N/M.
* | | |Note: The value of N must be equal to or less than M.
* |[15:8] |PKTSHNL |Packet Scaling Horizontal Factor N
* | | |Specify the lower 8-bit of numerator part (N) of the horizontal scaling factor.
* | | |The lower 8-bit will be cascaded with higher 8-bit (PKDSHNH) to form a 16-bit numerator of horizontal factor.
* |[23:16] |PKTSVML |Packet Scaling Vertical Factor M
* | | |Specify the lower 8-bit of denominator part (M) of the vertical scaling factor.
* | | |The lower 8-bit will be cascaded with higher 8-bit (PKDSVMH) to form a 16-bit denominator (M) of vertical factor.
* | | |The output image width will be equal to the image height * N/M.
* | | |Note: The value of N must be equal to or less than M.
* |[31:24] |PKTSVNL |Packet Scaling Vertical Factor N
* | | |Specify the lower 8-bit of numerator part (N) of the vertical scaling factor.
* | | |The lower 8-bit will be cascaded with higher 8-bit (PKDSVNH) to form a 16-bit numerator of vertical factor.
* @var CCAP_T::FRCTL
* Offset: 0x30 Scaling Frame Rate Factor Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[5:0] |FRM |Scaling Frame Rate Factor M
* | | |Specify the denominator part (M) of the frame rate scaling factor.
* | | |The output image frame rate will be equal to input image frame rate * (N/M).
* | | |Note: The value of N must be equal to or less than M.
* |[13:8] |FRN |Scaling Frame Rate Factor N
* | | |Specify the numerator part (N) of the frame rate scaling factor.
* @var CCAP_T::STRIDE
* Offset: 0x34 Frame Output Pixel Stride Width Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[13:0] |PKTSTRIDE |Packet Frame Output Pixel Stride Width
* | | |The output pixel stride size of packet pipe.
* | | |It is a 32-pixel aligned stride width for the Luma-Y-One bit format or a 4-pixel aligned stride with for the Luma-Y-Eight bit format when color or monochrome CMOS sensors used.
* | | |This means that every new captured line is by word alignment address when color or monochrome CMOS sensors used.
* @var CCAP_T::FIFOTH
* Offset: 0x3C FIFO Threshold Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[28:24] |PKTFTH |Packet FIFO Threshold
* | | |Specify the 5-bit value of the packet FIFO threshold.
* |[31] |OVF |FIFO Overflow Flag
* | | |Indicate the FIFO overflow flag.
* @var CCAP_T::CMPADDR
* Offset: 0x40 Compare Memory Base Address Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |CMPADDR |Compare Memory Base Address
* | | |It is a word alignment address, that is, the address is aligned by ignoring the 2 LSB bits [1:0].
* @var CCAP_T::LUMA_Y1_THD
* Offset: 0x44 Luminance Y8 to Y1 Threshold Value Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :-----------: | :---- |
* |[7:0] |LUMA_Y1_THRESH |Luminance Y8 to Y1 Threshold Value
* | | |Specify the 8-bit threshold value for the luminance Y bit-8 to the luminance Y 1-bit conversion.
* @var CCAP_T::PKTSM
* Offset: 0x48 Packet Scaling Vertical/Horizontal Factor Register (MSB)
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |PKTSHMH |Packet Scaling Horizontal Factor M
* | | |Specify the higher 8-bit of denominator part (M) of the horizontal scaling factor.
* | | |Please refer to the register CCAP_PKTSL for the detailed operation.
* |[15:8] |PKTSHNH |Packet Scaling Horizontal Factor N
* | | |Specify the higher 8-bit of numerator part (N) of the horizontal scaling factor.
* | | |Please refer to the register CCAP_PKTSL for the detailed operation.
* |[23:16] |PKTSVMH |Packet Scaling Vertical Factor M
* | | |Specify the higher 8-bit of denominator part (M) of the vertical scaling factor.
* | | |Please refer to the register CCAP_PKTSL to check the cooperation between these two registers.
* |[31:24] |PKTSVNH |Packet Scaling Vertical Factor N
* | | |Specify the higher 8-bit of numerator part (N) of the vertical scaling factor.
* | | |Please refer to the register CCAP_PKTSL to check the cooperation between these two registers.
* @var CCAP_T::CURADDRP
* Offset: 0x50 Current Packet System Memory Address Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |CURADDR |Current Packet Output Memory Address
* | | |Specify the 32-bit value of the current packet output memory address.
* @var CCAP_T::PKTBA0
* Offset: 0x60 System Memory Packet Base Address 0 Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |BASEADDR |System Memory Packet Base Address 0
* | | |It is a word alignment address, that is, the address is aligned by ignoring the 2 LSB bits [1:0].
*/
__IO uint32_t CTL; /*!< [0x0000] Camera Capture Interface Control Register */
__IO uint32_t PAR; /*!< [0x0004] Camera Capture Interface Parameter Register */
__IO uint32_t INT; /*!< [0x0008] Camera Capture Interface Interrupt Register */
__I uint32_t RESERVE0[5];
__IO uint32_t CWSP; /*!< [0x0020] Cropping Window Starting Address Register */
__IO uint32_t CWS; /*!< [0x0024] Cropping Window Size Register */
__IO uint32_t PKTSL; /*!< [0x0028] Packet Scaling Vertical/Horizontal Factor Register (LSB) */
__IO uint32_t PLNSL; /*!< [0x002C] Planar Scaling Vertical/Horizontal Factor Register (LSB) */
__IO uint32_t FRCTL; /*!< [0x0030] Scaling Frame Rate Factor Register */
__IO uint32_t STRIDE; /*!< [0x0034] Frame Output Pixel Stride Width Register */
__I uint32_t RESERVE1[1];
__IO uint32_t FIFOTH; /*!< [0x003C] FIFO Threshold Register */
__IO uint32_t CMPADDR; /*!< [0x0040] Compare Memory Base Address Register */
__IO uint32_t LUMA_Y1_THD; /*!< [0x0044] Luminance Y8 to Y1 Threshold Value Register */
__IO uint32_t PKTSM; /*!< [0x0048] Packet Scaling Vertical/Horizontal Factor Register (MSB) */
__IO uint32_t PLNSM; /*!< [0x004C] Planar Scaling Vertical/Horizontal Factor Register (MSB) */
__I uint32_t CURADDRP; /*!< [0x0050] Current Packet System Memory Address Register */
__I uint32_t CURADDRY; /*!< [0x0054] Current Planar Y System Memory Address Register */
__I uint32_t CURADDRU; /*!< [0x0058] Current Planar U System Memory Address Register */
__I uint32_t CURADDRV; /*!< [0x005C] Current Planar V System Memory Address Register */
__IO uint32_t PKTBA0; /*!< [0x0060] System Memory Packet Base Address 0 Register */
__I uint32_t RESERVE4[7];
__IO uint32_t YBA; /*!< [0x0080] System Memory Planar Y Base Address Register */
__IO uint32_t UBA; /*!< [0x0084] System Memory Planar U Base Address Register */
__IO uint32_t VBA; /*!< [0x0088] System Memory Planar V Base Address Register */
} CCAP_T;
/**
@addtogroup CCAP_CONST CCAP Bit Field Definition
Constant Definitions for CCAP Controller
@{ */
#define CCAP_CTL_CCAPEN_Pos (0) /*!< CCAP_T::CTL: CCAPEN Position */
#define CCAP_CTL_CCAPEN_Msk (0x1ul << CCAP_CTL_CCAPEN_Pos) /*!< CCAP_T::CTL: CCAPEN Mask */
#define CCAP_CTL_PLNEN_Pos (5) /*!< CCAP_T::CTL: PLNEN Position */
#define CCAP_CTL_PLNEN_Msk (0x1ul << CCAP_CTL_PLNEN_Pos) /*!< CCAP_T::CTL: PLNEN Mask */
#define CCAP_CTL_PKTEN_Pos (6) /*!< CCAP_T::CTL: PKTEN Position */
#define CCAP_CTL_PKTEN_Msk (0x1ul << CCAP_CTL_PKTEN_Pos) /*!< CCAP_T::CTL: PKTEN Mask */
#define CCAP_CTL_MONO_Pos (7) /*!< CCAP_T::CTL: MONO Position */
#define CCAP_CTL_MONO_Msk (0x1ul << CCAP_CTL_MONO_Pos) /*!< CCAP_T::CTL: MONO Mask */
#define CCAP_CTL_SHUTTER_Pos (16) /*!< CCAP_T::CTL: SHUTTER Position */
#define CCAP_CTL_SHUTTER_Msk (0x1ul << CCAP_CTL_SHUTTER_Pos) /*!< CCAP_T::CTL: SHUTTER Mask */
#define CCAP_CTL_MY4_SWAP_Pos (17) /*!< CCAP_T::CTL: MY4_SWAP Position */
#define CCAP_CTL_MY4_SWAP_Msk (0x1ul << CCAP_CTL_MY4_SWAP_Pos) /*!< CCAP_T::CTL: MY4_SWAP Mask */
#define CCAP_CTL_MY8_MY4_Pos (18) /*!< CCAP_T::CTL: MY8_MY4 Position */
#define CCAP_CTL_MY8_MY4_Msk (0x1ul << CCAP_CTL_MY8_MY4_Pos) /*!< CCAP_T::CTL: MY8_MY4 Mask */
#define CCAP_CTL_Luma_Y_One_Pos (19) /*!< CCAP_T::CTL: Luma_Y_One Position */
#define CCAP_CTL_Luma_Y_One_Msk (0x1ul << CCAP_CTL_Luma_Y_One_Pos) /*!< CCAP_T::CTL: Luma_Y_One Mask */
#define CCAP_CTL_UPDATE_Pos (20) /*!< CCAP_T::CTL: UPDATE Position */
#define CCAP_CTL_UPDATE_Msk (0x1ul << CCAP_CTL_UPDATE_Pos) /*!< CCAP_T::CTL: UPDATE Mask */
#define CCAP_CTL_VPRST_Pos (24) /*!< CCAP_T::CTL: VPRST Position */
#define CCAP_CTL_VPRST_Msk (0x1ul << CCAP_CTL_VPRST_Pos) /*!< CCAP_T::CTL: VPRST Mask */
#define CCAP_PAR_INFMT_Pos (0) /*!< CCAP_T::PAR: INFMT Position */
#define CCAP_PAR_INFMT_Msk (0x1ul << CCAP_PAR_INFMT_Pos) /*!< CCAP_T::PAR: INFMT Mask */
#define CCAP_PAR_SENTYPE_Pos (1) /*!< CCAP_T::PAR: SENTYPE Position */
#define CCAP_PAR_SENTYPE_Msk (0x1ul << CCAP_PAR_SENTYPE_Pos) /*!< CCAP_T::PAR: SENTYPE Mask */
#define CCAP_PAR_INDATORD_Pos (2) /*!< CCAP_T::PAR: INDATORD Position */
#define CCAP_PAR_INDATORD_Msk (0x3ul << CCAP_PAR_INDATORD_Pos) /*!< CCAP_T::PAR: INDATORD Mask */
#define CCAP_PAR_PLNFMT_Pos (7) /*!< CCAP_T::PAR: OUTFMT Position */
#define CCAP_PAR_PLNFMT_Msk (0x1ul << CCAP_PAR_OUTFMT_Pos) /*!< CCAP_T::PAR: OUTFMT Mask */
#define CCAP_PAR_OUTFMT_Pos (4) /*!< CCAP_T::PAR: OUTFMT Position */
#define CCAP_PAR_OUTFMT_Msk (0x3ul << CCAP_PAR_OUTFMT_Pos) /*!< CCAP_T::PAR: OUTFMT Mask */
#define CCAP_PAR_RANGE_Pos (6) /*!< CCAP_T::PAR: RANGE Position */
#define CCAP_PAR_RANGE_Msk (0x1ul << CCAP_PAR_RANGE_Pos) /*!< CCAP_T::PAR: RANGE Mask */
#define CCAP_PAR_PCLKP_Pos (8) /*!< CCAP_T::PAR: PCLKP Position */
#define CCAP_PAR_PCLKP_Msk (0x1ul << CCAP_PAR_PCLKP_Pos) /*!< CCAP_T::PAR: PCLKP Mask */
#define CCAP_PAR_HSP_Pos (9) /*!< CCAP_T::PAR: HSP Position */
#define CCAP_PAR_HSP_Msk (0x1ul << CCAP_PAR_HSP_Pos) /*!< CCAP_T::PAR: HSP Mask */
#define CCAP_PAR_VSP_Pos (10) /*!< CCAP_T::PAR: VSP Position */
#define CCAP_PAR_VSP_Msk (0x1ul << CCAP_PAR_VSP_Pos) /*!< CCAP_T::PAR: VSP Mask */
#define CCAP_PAR_FBB_Pos (18) /*!< CCAP_T::PAR: FBB Position */
#define CCAP_PAR_FBB_Msk (0x1ul << CCAP_PAR_FBB_Pos) /*!< CCAP_T::PAR: FBB Mask */
#define CCAP_INT_VINTF_Pos (0) /*!< CCAP_T::INT: VINTF Position */
#define CCAP_INT_VINTF_Msk (0x1ul << CCAP_INT_VINTF_Pos) /*!< CCAP_T::INT: VINTF Mask */
#define CCAP_INT_MEINTF_Pos (1) /*!< CCAP_T::INT: MEINTF Position */
#define CCAP_INT_MEINTF_Msk (0x1ul << CCAP_INT_MEINTF_Pos) /*!< CCAP_T::INT: MEINTF Mask */
#define CCAP_INT_ADDRMINTF_Pos (3) /*!< CCAP_T::INT: ADDRMINTF Position */
#define CCAP_INT_ADDRMINTF_Msk (0x1ul << CCAP_INT_ADDRMINTF_Pos) /*!< CCAP_T::INT: ADDRMINTF Mask */
#define CCAP_INT_VIEN_Pos (16) /*!< CCAP_T::INT: VIEN Position */
#define CCAP_INT_VIEN_Msk (0x1ul << CCAP_INT_VIEN_Pos) /*!< CCAP_T::INT: VIEN Mask */
#define CCAP_INT_MEIEN_Pos (17) /*!< CCAP_T::INT: MEIEN Position */
#define CCAP_INT_MEIEN_Msk (0x1ul << CCAP_INT_MEIEN_Pos) /*!< CCAP_T::INT: MEIEN Mask */
#define CCAP_INT_ADDRMIEN_Pos (19) /*!< CCAP_T::INT: ADDRMIEN Position */
#define CCAP_INT_ADDRMIEN_Msk (0x1ul << CCAP_INT_ADDRMIEN_Pos) /*!< CCAP_T::INT: ADDRMIEN Mask */
#define CCAP_CWSP_CWSADDRH_Pos (0) /*!< CCAP_T::CWSP: CWSADDRH Position */
#define CCAP_CWSP_CWSADDRH_Msk (0xffful << CCAP_CWSP_CWSADDRH_Pos) /*!< CCAP_T::CWSP: CWSADDRH Mask */
#define CCAP_CWSP_CWSADDRV_Pos (16) /*!< CCAP_T::CWSP: CWSADDRV Position */
#define CCAP_CWSP_CWSADDRV_Msk (0x7fful << CCAP_CWSP_CWSADDRV_Pos) /*!< CCAP_T::CWSP: CWSADDRV Mask */
#define CCAP_CWS_CWW_Pos (0) /*!< CCAP_T::CWS: CWW Position */
#define CCAP_CWS_CWW_Msk (0xffful << CCAP_CWS_CWW_Pos) /*!< CCAP_T::CWS: CWW Mask */
#define CCAP_CWS_CWH_Pos (16) /*!< CCAP_T::CWS: CIWH Position */
#define CCAP_CWS_CWH_Msk (0x7fful << CCAP_CWS_CWH_Pos) /*!< CCAP_T::CWS: CIWH Mask */
#define CCAP_PKTSL_PKTSHML_Pos (0) /*!< CCAP_T::PKTSL: PKTSHML Position */
#define CCAP_PKTSL_PKTSHML_Msk (0xfful << CCAP_PKTSL_PKTSHML_Pos) /*!< CCAP_T::PKTSL: PKTSHML Mask */
#define CCAP_PKTSL_PKTSHNL_Pos (8) /*!< CCAP_T::PKTSL: PKTSHNL Position */
#define CCAP_PKTSL_PKTSHNL_Msk (0xfful << CCAP_PKTSL_PKTSHNL_Pos) /*!< CCAP_T::PKTSL: PKTSHNL Mask */
#define CCAP_PKTSL_PKTSVML_Pos (16) /*!< CCAP_T::PKTSL: PKTSVML Position */
#define CCAP_PKTSL_PKTSVML_Msk (0xfful << CCAP_PKTSL_PKTSVML_Pos) /*!< CCAP_T::PKTSL: PKTSVML Mask */
#define CCAP_PKTSL_PKTSVNL_Pos (24) /*!< CCAP_T::PKTSL: PKTSVNL Position */
#define CCAP_PKTSL_PKTSVNL_Msk (0xfful << CCAP_PKTSL_PKTSVNL_Pos) /*!< CCAP_T::PKTSL: PKTSVNL Mask */
#define CCAP_PLNSL_PLNSHML_Pos (0) /*!< CCAP_T::PLNSL: PLNSHML Position */
#define CCAP_PLNSL_PLNSHML_Msk (0xfful << CCAP_PLNSL_PLNSHML_Pos) /*!< CCAP_T::PLNSL: PLNSHML Mask */
#define CCAP_PLNSL_PLNSHNL_Pos (8) /*!< CCAP_T::PLNSL: PLNSHNL Position */
#define CCAP_PLNSL_PLNSHNL_Msk (0xfful << CCAP_PLNSL_PLNSHNL_Pos) /*!< CCAP_T::PLNSL: PLNSHNL Mask */
#define CCAP_PLNSL_PLNSVML_Pos (16) /*!< CCAP_T::PLNSL: PLNSVML Position */
#define CCAP_PLNSL_PLNSVML_Msk (0xfful << CCAP_PLNSL_PLNSVML_Pos) /*!< CCAP_T::PLNSL: PLNSVML Mask */
#define CCAP_PLNSL_PLNSVNL_Pos (24) /*!< CCAP_T::PLNSL: PLNSVNL Position */
#define CCAP_PLNSL_PLNSVNL_Msk (0xfful << CCAP_PLNSL_PLNSVNL_Pos) /*!< CCAP_T::PLNSL: PLNSVNL Mask */
#define CCAP_FRCTL_FRM_Pos (0) /*!< CCAP_T::FRCTL: FRM Position */
#define CCAP_FRCTL_FRM_Msk (0x3ful << CCAP_FRCTL_FRM_Pos) /*!< CCAP_T::FRCTL: FRM Mask */
#define CCAP_FRCTL_FRN_Pos (8) /*!< CCAP_T::FRCTL: FRN Position */
#define CCAP_FRCTL_FRN_Msk (0x3ful << CCAP_FRCTL_FRN_Pos) /*!< CCAP_T::FRCTL: FRN Mask */
#define CCAP_STRIDE_PKTSTRIDE_Pos (0) /*!< CCAP_T::STRIDE: PKTSTRIDE Position */
#define CCAP_STRIDE_PKTSTRIDE_Msk (0x3ffful << CCAP_STRIDE_PKTSTRIDE_Pos) /*!< CCAP_T::STRIDE: PKTSTRIDE Mask */
#define CCAP_STRIDE_PLNSTRIDE_Pos (16) /*!< CCAP_T::STRIDE: PLNSTRIDE Position */
#define CCAP_STRIDE_PLNSTRIDE_Msk (0x3ffful << CCAP_STRIDE_PLNSTRIDE_Pos) /*!< CCAP_T::STRIDE: PLNSTRIDE Mask */
#define CCAP_FIFOTH_PKTFTH_Pos (24) /*!< CCAP_T::FIFOTH: PKTFTH Position */
#define CCAP_FIFOTH_PKTFTH_Msk (0x1ful << CCAP_FIFOTH_PKTFTH_Pos) /*!< CCAP_T::FIFOTH: PKTFTH Mask */
#define CCAP_FIFOTH_OVF_Pos (31) /*!< CCAP_T::FIFOTH: OVF Position */
#define CCAP_FIFOTH_OVF_Msk (0x1ul << CCAP_FIFOTH_OVF_Pos) /*!< CCAP_T::FIFOTH: OVF Mask */
#define CCAP_CMPADDR_CMPADDR_Pos (0) /*!< CCAP_T::CMPADDR: CMPADDR Position */
#define CCAP_CMPADDR_CMPADDR_Msk (0xfffffffful << CCAP_CMPADDR_CMPADDR_Pos) /*!< CCAP_T::CMPADDR: CMPADDR Mask */
#define CCAP_PKTSM_PKTSHMH_Pos (0) /*!< CCAP_T::PKTSM: PKTSHMH Position */
#define CCAP_PKTSM_PKTSHMH_Msk (0xfful << CCAP_PKTSM_PKTSHMH_Pos) /*!< CCAP_T::PKTSM: PKTSHMH Mask */
#define CCAP_PKTSM_PKTSHNH_Pos (8) /*!< CCAP_T::PKTSM: PKTSHNH Position */
#define CCAP_PKTSM_PKTSHNH_Msk (0xfful << CCAP_PKTSM_PKTSHNH_Pos) /*!< CCAP_T::PKTSM: PKTSHNH Mask */
#define CCAP_PKTSM_PKTSVMH_Pos (16) /*!< CCAP_T::PKTSM: PKTSVMH Position */
#define CCAP_PKTSM_PKTSVMH_Msk (0xfful << CCAP_PKTSM_PKTSVMH_Pos) /*!< CCAP_T::PKTSM: PKTSVMH Mask */
#define CCAP_PKTSM_PKTSVNH_Pos (24) /*!< CCAP_T::PKTSM: PKTSVNH Position */
#define CCAP_PKTSM_PKTSVNH_Msk (0xfful << CCAP_PKTSM_PKTSVNH_Pos) /*!< CCAP_T::PKTSM: PKTSVNH Mask */
#define CCAP_PLNSM_PLNSHMH_Pos (0) /*!< CCAP_T::PLNSM: PLNSHMH Position */
#define CCAP_PLNSM_PLNSHMH_Msk (0xfful << CCAP_PLNSM_PLNSHMH_Pos) /*!< CCAP_T::PLNSM: PLNSHMH Mask */
#define CCAP_PLNSM_PLNSHNH_Pos (8) /*!< CCAP_T::PLNSM: PLNSHNH Position */
#define CCAP_PLNSM_PLNSHNH_Msk (0xfful << CCAP_PLNSM_PLNSHNH_Pos) /*!< CCAP_T::PLNSM: PLNSHNH Mask */
#define CCAP_PLNSM_PLNSVMH_Pos (16) /*!< CCAP_T::PLNSM: PLNSVMH Position */
#define CCAP_PLNSM_PLNSVMH_Msk (0xfful << CCAP_PLNSM_PLNSVMH_Pos) /*!< CCAP_T::PLNSM: PLNSVMH Mask */
#define CCAP_PLNSM_PLNSVNH_Pos (24) /*!< CCAP_T::PLNSM: PLNSVNH Position */
#define CCAP_PLNSM_PLNSVNH_Msk (0xfful << CCAP_PLNSM_PLNSVNH_Pos) /*!< CCAP_T::PLNSM: PLNSVNH Mask */
#define CCAP_CURADDRP_CURADDR_Pos (0) /*!< CCAP_T::CURADDRP: CURADDR Position */
#define CCAP_CURADDRP_CURADDR_Msk (0xfffffffful << CCAP_CURADDRP_CURADDR_Pos) /*!< CCAP_T::CURADDRP: CURADDR Mask */
#define CCAP_PKTBA0_BASEADDR_Pos (0) /*!< CCAP_T::PKTBA0: BASEADDR Position */
#define CCAP_PKTBA0_BASEADDR_Msk (0xfffffffful << CCAP_PKTBA0_BASEADDR_Pos) /*!< CCAP_T::PKTBA0: BASEADDR Mask */
/**@}*/ /* CCAP_CONST */
/**@}*/ /* end of CCAP register group */
/**@}*/ /* end of REGISTER group */
#if defined ( __CC_ARM )
#pragma no_anon_unions
#endif
#endif /* __CCAP_REG_H__ */

2596
bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/clk_reg.h Normal file
View File

File diff suppressed because it is too large Load Diff

7135
bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/crypto_reg.h Normal file
View File

File diff suppressed because it is too large Load Diff

9569
bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/ddr32phy_reg.h Normal file
View File

File diff suppressed because it is too large Load Diff

1432
bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/disp_reg.h Normal file
View File

File diff suppressed because it is too large Load Diff

315
bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/dpm_reg.h Normal file
View File

@ -0,0 +1,315 @@
/**************************************************************************//**
* @file dpm_reg.h
* @brief DPM register definition header file
*
* SPDX-License-Identifier: Apache-2.0
* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __DPM_REG_H__
#define __DPM_REG_H__
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
/**
@addtogroup REGISTER Control Register
@{
*/
/*---------------------- Debug Protection Mechanism -------------------------*/
/**
@addtogroup DPM Debug Protection Mechanism(DPM)
Memory Mapped Structure for DPM Controller
@{ */
typedef struct
{
/**
* @var DPM_T::A35SDS
* Offset: 0x10 DPM A35 Secure Debug State Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |REGDEN |Debug State Register Enable Bit
* | | |0 = Set the debug state to CLOSE state when current state is OPEN state.
* | | |1 = Set the debug state to OPEN state when current state is CLOSE state.
* | | |Note: if SINFAEN.SSPCC is set to high. This bit becomes read-only by Non-Secure software
* |[1] |ODIS |Debug State OTP Disable Bit (Read Only)
* | | |Indicate the Disable bit stored in OTP.
* |[2] |OLOCK |Debug State OTP Lock Bit (Read Only)
* | | |Indicate the Lock bit stored in OTP.
* |[31:24] |VCODE |Write Verify Code and Read Verify Code
* | | |Read operation:
* | | |0xA5 = The read access for DPM_CTL is correct.
* | | |Others = The read access for DPM_CTL is incorrect.
* | | |Write operation:
* | | |0x5A = The write verify code, which is needed to do a valid write to DPM_CA35SDS.
* | | |Others = Invalid write verify code.
* @var DPM_T::A35SNDS
* Offset: 0x14 DPM A35 Secure Non-invasive Debug State Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |REGDEN |Debug State Register Enable Bit
* | | |0 = Set the debug state to CLOSE state when current state is OPEN state.
* | | |1 = Set the debug state to OPEN state when current state is CLOSE state.
* | | |Note: if SINFAEN.SSPCC is set to high. This bit becomes read-only by Non-Secure software
* |[1] |ODIS |Debug State OTP Disable Bit (Read Only)
* | | |Indicate the Disable bit stored in OTP.
* |[2] |OLOCK |Debug State OTP Lock Bit (Read Only)
* | | |Indicate the Lock bit stored in OTP.
* |[31:24] |VCODE |Write Verify Code and Read Verify Code
* | | |Read operation:
* | | |0xA5 = The read access for DPM_CTL is correct.
* | | |Others = The read access for DPM_CTL is incorrect.
* | | |Write operation:
* | | |0x5A = The write verify code, which is needed to do a valid write to DPM_CA35SDS.
* | | |Others = Invalid write verify code.
* @var DPM_T::A35NSDS
* Offset: 0x18 DPM A35 Non-secure Debug State Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |REGDEN |Debug State Register Enable Bit
* | | |0 = Set the debug state to CLOSE state when current state is OPEN state.
* | | |1 = Set the debug state to OPEN state when current state is CLOSE state.
* | | |Note: if SINFAEN.SSPCC is set to high. This bit becomes read-only by Non-Secure software
* |[1] |ODIS |Debug State OTP Disable Bit (Read Only)
* | | |Indicate the Disable bit stored in OTP.
* |[2] |OLOCK |Debug State OTP Lock Bit (Read Only)
* | | |Indicate the Lock bit stored in OTP.
* |[31:24] |VCODE |Write Verify Code and Read Verify Code
* | | |Read operation:
* | | |0xA5 = The read access for DPM_CTL is correct.
* | | |Others = The read access for DPM_CTL is incorrect.
* | | |Write operation:
* | | |0x5A = The write verify code, which is needed to do a valid write to DPM_CA35SDS.
* | | |Others = Invalid write verify code.
* @var DPM_T::A35NSNDS
* Offset: 0x1C DPM A35 Non-secure Non-invasive Debug State Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |REGDEN |Debug State Register Enable Bit
* | | |0 = Set the debug state to CLOSE state when current state is OPEN state.
* | | |1 = Set the debug state to OPEN state when current state is CLOSE state.
* | | |Note: if SINFAEN.SSPCC is set to high. This bit becomes read-only by Non-Secure software
* |[1] |ODIS |Debug State OTP Disable Bit (Read Only)
* | | |Indicate the Disable bit stored in OTP.
* |[2] |OLOCK |Debug State OTP Lock Bit (Read Only)
* | | |Indicate the Lock bit stored in OTP.
* |[31:24] |VCODE |Write Verify Code and Read Verify Code
* | | |Read operation:
* | | |0xA5 = The read access for DPM_CTL is correct.
* | | |Others = The read access for DPM_CTL is incorrect.
* | | |Write operation:
* | | |0x5A = The write verify code, which is needed to do a valid write to DPM_CA35SDS.
* | | |Others = Invalid write verify code.
* @var DPM_T::M4DS
* Offset: 0x20 DPM M4 Debug State Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |REGDEN |Debug State Register Enable Bit
* | | |0 = Set the debug state to CLOSE state when current state is OPEN state.
* | | |1 = Set the debug state to OPEN state when current state is CLOSE state.
* | | |Note: if SINFAEN.SSPCC is set to high. This bit becomes read-only by Non-Secure software
* |[1] |ODIS |Debug State OTP Disable Bit (Read Only)
* | | |Indicate the Disable bit stored in OTP.
* |[2] |OLOCK |Debug State OTP Lock Bit (Read Only)
* | | |Indicate the Lock bit stored in OTP.
* |[31:24] |VCODE |Write Verify Code and Read Verify Code
* | | |Read operation:
* | | |0xA5 = The read access for DPM_CTL is correct.
* | | |Others = The read access for DPM_CTL is incorrect.
* | | |Write operation:
* | | |0x5A = The write verify code, which is needed to do a valid write to DPM_CA35SDS.
* | | |Others = Invalid write verify code.
* @var DPM_T::M4NDS
* Offset: 0x24 DPM M4 Non-invasive Debug State Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |REGDEN |Debug State Register Enable Bit
* | | |0 = Set the debug state to CLOSE state when current state is OPEN state.
* | | |1 = Set the debug state to OPEN state when current state is CLOSE state.
* | | |Note: if SINFAEN.SSPCC is set to high. This bit becomes read-only by Non-Secure software
* |[1] |ODIS |Debug State OTP Disable Bit (Read Only)
* | | |Indicate the Disable bit stored in OTP.
* |[2] |OLOCK |Debug State OTP Lock Bit (Read Only)
* | | |Indicate the Lock bit stored in OTP.
* |[31:24] |VCODE |Write Verify Code and Read Verify Code
* | | |Read operation:
* | | |0xA5 = The read access for DPM_CTL is correct.
* | | |Others = The read access for DPM_CTL is incorrect.
* | | |Write operation:
* | | |0x5A = The write verify code, which is needed to do a valid write to DPM_CA35SDS.
* | | |Others = Invalid write verify code.
* @var DPM_T::EXTDS
* Offset: 0x30 DPM External Debug State Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |REGDEN |Debug State Register Enable Bit
* | | |0 = Set the debug state to CLOSE state when current state is OPEN state.
* | | |1 = Set the debug state to OPEN state when current state is CLOSE state.
* | | |Note: if SINFAEN.SSPCC is set to high. This bit becomes read-only by Non-Secure software
* |[1] |ODIS |Debug State OTP Disable Bit (Read Only)
* | | |Indicate the Disable bit stored in OTP.
* |[2] |OLOCK |Debug State OTP Lock Bit (Read Only)
* | | |Indicate the Lock bit stored in OTP.
* |[31:24] |VCODE |Write Verify Code and Read Verify Code
* | | |Read operation:
* | | |0xA5 = The read access for DPM_CTL is correct.
* | | |Others = The read access for DPM_CTL is incorrect.
* | | |Write operation:
* | | |0x5A = The write verify code, which is needed to do a valid write to DPM_CA35SDS.
* | | |Others = Invalid write verify code.
* @var DPM_T::EXTTDS
* Offset: 0x34 DPM External Tracing Debug State Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |REGDEN |Debug State Register Enable Bit
* | | |0 = Set the debug state to CLOSE state when current state is OPEN state.
* | | |1 = Set the debug state to OPEN state when current state is CLOSE state.
* | | |Note: if SINFAEN.SSPCC is set to high. This bit becomes read-only by Non-Secure software
* |[1] |ODIS |Debug State OTP Disable Bit (Read Only)
* | | |Indicate the Disable bit stored in OTP.
* |[2] |OLOCK |Debug State OTP Lock Bit (Read Only)
* | | |Indicate the Lock bit stored in OTP.
* |[31:24] |VCODE |Write Verify Code and Read Verify Code
* | | |Read operation:
* | | |0xA5 = The read access for DPM_CTL is correct.
* | | |Others = The read access for DPM_CTL is incorrect.
* | | |Write operation:
* | | |0x5A = The write verify code, which is needed to do a valid write to DPM_CA35SDS.
* | | |Others = Invalid write verify code.
*/
__I uint32_t RESERVE0[4];
__IO uint32_t A35SDS; /*!< [0x0010] DPM A35 Secure Debug State Register */
__IO uint32_t A35SNDS; /*!< [0x0014] DPM A35 Secure Non-invasive Debug State Register */
__IO uint32_t A35NSDS; /*!< [0x0018] DPM A35 Non-secure Debug State Register */
__IO uint32_t A35NSNDS; /*!< [0x001c] DPM A35 Non-secure Non-invasive Debug State Register */
__IO uint32_t M4DS; /*!< [0x0020] DPM M4 Debug State Register */
__IO uint32_t M4NDS; /*!< [0x0024] DPM M4 Non-invasive Debug State Register */
__I uint32_t RESERVE1[2];
__IO uint32_t EXTDS; /*!< [0x0030] DPM External Debug State Register */
__IO uint32_t EXTTDS; /*!< [0x0034] DPM External Tracing Debug State Register */
} DPM_T;
/**
@addtogroup DPM_CONST DPM Bit Field Definition
Constant Definitions for DPM Controller
@{ */
#define DPM_A35SDS_REGDEN_Pos (0) /*!< DPM_T::A35SDS: REGDEN Position */
#define DPM_A35SDS_REGDEN_Msk (0x1ul << DPM_A35SDS_REGDEN_Pos) /*!< DPM_T::A35SDS: REGDEN Mask */
#define DPM_A35SDS_ODIS_Pos (1) /*!< DPM_T::A35SDS: ODIS Position */
#define DPM_A35SDS_ODIS_Msk (0x1ul << DPM_A35SDS_ODIS_Pos) /*!< DPM_T::A35SDS: ODIS Mask */
#define DPM_A35SDS_OLOCK_Pos (2) /*!< DPM_T::A35SDS: OLOCK Position */
#define DPM_A35SDS_OLOCK_Msk (0x1ul << DPM_A35SDS_OLOCK_Pos) /*!< DPM_T::A35SDS: OLOCK Mask */
#define DPM_A35SDS_VCODE_Pos (24) /*!< DPM_T::A35SDS: VCODE Position */
#define DPM_A35SDS_VCODE_Msk (0xfful << DPM_A35SDS_VCODE_Pos) /*!< DPM_T::A35SDS: VCODE Mask */
#define DPM_A35SNDS_REGDEN_Pos (0) /*!< DPM_T::A35SNDS: REGDEN Position */
#define DPM_A35SNDS_REGDEN_Msk (0x1ul << DPM_A35SNDS_REGDEN_Pos) /*!< DPM_T::A35SNDS: REGDEN Mask */
#define DPM_A35SNDS_ODIS_Pos (1) /*!< DPM_T::A35SNDS: ODIS Position */
#define DPM_A35SNDS_ODIS_Msk (0x1ul << DPM_A35SNDS_ODIS_Pos) /*!< DPM_T::A35SNDS: ODIS Mask */
#define DPM_A35SNDS_OLOCK_Pos (2) /*!< DPM_T::A35SNDS: OLOCK Position */
#define DPM_A35SNDS_OLOCK_Msk (0x1ul << DPM_A35SNDS_OLOCK_Pos) /*!< DPM_T::A35SNDS: OLOCK Mask */
#define DPM_A35SNDS_VCODE_Pos (24) /*!< DPM_T::A35SNDS: VCODE Position */
#define DPM_A35SNDS_VCODE_Msk (0xfful << DPM_A35SNDS_VCODE_Pos) /*!< DPM_T::A35SNDS: VCODE Mask */
#define DPM_A35NSDS_REGDEN_Pos (0) /*!< DPM_T::A35NSDS: REGDEN Position */
#define DPM_A35NSDS_REGDEN_Msk (0x1ul << DPM_A35NSDS_REGDEN_Pos) /*!< DPM_T::A35NSDS: REGDEN Mask */
#define DPM_A35NSDS_ODIS_Pos (1) /*!< DPM_T::A35NSDS: ODIS Position */
#define DPM_A35NSDS_ODIS_Msk (0x1ul << DPM_A35NSDS_ODIS_Pos) /*!< DPM_T::A35NSDS: ODIS Mask */
#define DPM_A35NSDS_OLOCK_Pos (2) /*!< DPM_T::A35NSDS: OLOCK Position */
#define DPM_A35NSDS_OLOCK_Msk (0x1ul << DPM_A35NSDS_OLOCK_Pos) /*!< DPM_T::A35NSDS: OLOCK Mask */
#define DPM_A35NSDS_VCODE_Pos (24) /*!< DPM_T::A35NSDS: VCODE Position */
#define DPM_A35NSDS_VCODE_Msk (0xfful << DPM_A35NSDS_VCODE_Pos) /*!< DPM_T::A35NSDS: VCODE Mask */
#define DPM_A35NSNDS_REGDEN_Pos (0) /*!< DPM_T::A35NSNDS: REGDEN Position */
#define DPM_A35NSNDS_REGDEN_Msk (0x1ul << DPM_A35NSNDS_REGDEN_Pos) /*!< DPM_T::A35NSNDS: REGDEN Mask */
#define DPM_A35NSNDS_ODIS_Pos (1) /*!< DPM_T::A35NSNDS: ODIS Position */
#define DPM_A35NSNDS_ODIS_Msk (0x1ul << DPM_A35NSNDS_ODIS_Pos) /*!< DPM_T::A35NSNDS: ODIS Mask */
#define DPM_A35NSNDS_OLOCK_Pos (2) /*!< DPM_T::A35NSNDS: OLOCK Position */
#define DPM_A35NSNDS_OLOCK_Msk (0x1ul << DPM_A35NSNDS_OLOCK_Pos) /*!< DPM_T::A35NSNDS: OLOCK Mask */
#define DPM_A35NSNDS_VCODE_Pos (24) /*!< DPM_T::A35NSNDS: VCODE Position */
#define DPM_A35NSNDS_VCODE_Msk (0xfful << DPM_A35NSNDS_VCODE_Pos) /*!< DPM_T::A35NSNDS: VCODE Mask */
#define DPM_M4DS_REGDEN_Pos (0) /*!< DPM_T::M4DS: REGDEN Position */
#define DPM_M4DS_REGDEN_Msk (0x1ul << DPM_M4DS_REGDEN_Pos) /*!< DPM_T::M4DS: REGDEN Mask */
#define DPM_M4DS_ODIS_Pos (1) /*!< DPM_T::M4DS: ODIS Position */
#define DPM_M4DS_ODIS_Msk (0x1ul << DPM_M4DS_ODIS_Pos) /*!< DPM_T::M4DS: ODIS Mask */
#define DPM_M4DS_OLOCK_Pos (2) /*!< DPM_T::M4DS: OLOCK Position */
#define DPM_M4DS_OLOCK_Msk (0x1ul << DPM_M4DS_OLOCK_Pos) /*!< DPM_T::M4DS: OLOCK Mask */
#define DPM_M4DS_VCODE_Pos (24) /*!< DPM_T::M4DS: VCODE Position */
#define DPM_M4DS_VCODE_Msk (0xfful << DPM_M4DS_VCODE_Pos) /*!< DPM_T::M4DS: VCODE Mask */
#define DPM_M4NDS_REGDEN_Pos (0) /*!< DPM_T::M4NDS: REGDEN Position */
#define DPM_M4NDS_REGDEN_Msk (0x1ul << DPM_M4NDS_REGDEN_Pos) /*!< DPM_T::M4NDS: REGDEN Mask */
#define DPM_M4NDS_ODIS_Pos (1) /*!< DPM_T::M4NDS: ODIS Position */
#define DPM_M4NDS_ODIS_Msk (0x1ul << DPM_M4NDS_ODIS_Pos) /*!< DPM_T::M4NDS: ODIS Mask */
#define DPM_M4NDS_OLOCK_Pos (2) /*!< DPM_T::M4NDS: OLOCK Position */
#define DPM_M4NDS_OLOCK_Msk (0x1ul << DPM_M4NDS_OLOCK_Pos) /*!< DPM_T::M4NDS: OLOCK Mask */
#define DPM_M4NDS_VCODE_Pos (24) /*!< DPM_T::M4NDS: VCODE Position */
#define DPM_M4NDS_VCODE_Msk (0xfful << DPM_M4NDS_VCODE_Pos) /*!< DPM_T::M4NDS: VCODE Mask */
#define DPM_EXTDS_REGDEN_Pos (0) /*!< DPM_T::EXTDS: REGDEN Position */
#define DPM_EXTDS_REGDEN_Msk (0x1ul << DPM_EXTDS_REGDEN_Pos) /*!< DPM_T::EXTDS: REGDEN Mask */
#define DPM_EXTDS_ODIS_Pos (1) /*!< DPM_T::EXTDS: ODIS Position */
#define DPM_EXTDS_ODIS_Msk (0x1ul << DPM_EXTDS_ODIS_Pos) /*!< DPM_T::EXTDS: ODIS Mask */
#define DPM_EXTDS_OLOCK_Pos (2) /*!< DPM_T::EXTDS: OLOCK Position */
#define DPM_EXTDS_OLOCK_Msk (0x1ul << DPM_EXTDS_OLOCK_Pos) /*!< DPM_T::EXTDS: OLOCK Mask */
#define DPM_EXTDS_VCODE_Pos (24) /*!< DPM_T::EXTDS: VCODE Position */
#define DPM_EXTDS_VCODE_Msk (0xfful << DPM_EXTDS_VCODE_Pos) /*!< DPM_T::EXTDS: VCODE Mask */
#define DPM_EXTTDS_REGDEN_Pos (0) /*!< DPM_T::EXTTDS: REGDEN Position */
#define DPM_EXTTDS_REGDEN_Msk (0x1ul << DPM_EXTTDS_REGDEN_Pos) /*!< DPM_T::EXTTDS: REGDEN Mask */
#define DPM_EXTTDS_ODIS_Pos (1) /*!< DPM_T::EXTTDS: ODIS Position */
#define DPM_EXTTDS_ODIS_Msk (0x1ul << DPM_EXTTDS_ODIS_Pos) /*!< DPM_T::EXTTDS: ODIS Mask */
#define DPM_EXTTDS_OLOCK_Pos (2) /*!< DPM_T::EXTTDS: OLOCK Position */
#define DPM_EXTTDS_OLOCK_Msk (0x1ul << DPM_EXTTDS_OLOCK_Pos) /*!< DPM_T::EXTTDS: OLOCK Mask */
#define DPM_EXTTDS_VCODE_Pos (24) /*!< DPM_T::EXTTDS: VCODE Position */
#define DPM_EXTTDS_VCODE_Msk (0xfful << DPM_EXTTDS_VCODE_Pos) /*!< DPM_T::EXTTDS: VCODE Mask */
/**@}*/ /* DPM_CONST */
/**@}*/ /* end of DPM register group */
/**@}*/ /* end of REGISTER group */
#if defined ( __CC_ARM )
#pragma no_anon_unions
#endif
#endif /* __DPM_REG_H__ */

2278
bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/eadc_reg.h Normal file
View File

File diff suppressed because it is too large Load Diff

428
bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/ebi_reg.h Normal file
View File

@ -0,0 +1,428 @@
/**************************************************************************//**
* @file ebi_reg.h
* @brief EBI register definition header file
*
* SPDX-License-Identifier: Apache-2.0
* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __EBI_REG_H__
#define __EBI_REG_H__
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
/**
@addtogroup REGISTER Control Register
@{
*/
/**
@addtogroup EBI External Bus Interface Controller(EBI)
Memory Mapped Structure for EBI Controller
@{ */
typedef struct
{
/**
* @var EBI_T::CTL0
* Offset: 0x00 External Bus Interface Bank0 Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |EN |EBI Enable Bit
* | | |This bit is the functional enable bit for EBI.
* | | |0 = EBI function Disabled.
* | | |1 = EBI function Enabled.
* |[1] |DW16 |EBI Data Width 16-bit Select
* | | |This bit defines if the EBI data width is 8-bit or 16-bit.
* | | |0 = EBI data width is 8-bit.
* | | |1 = EBI data width is 16-bit.
* |[2] |CSPOLINV |Chip Select Pin Polar Inverse
* | | |This bit defines the active level of EBI chip select pin (EBI_nCS).
* | | |0 = Chip select pin (EBI_nCS) is active low.
* | | |1 = Chip select pin (EBI_nCS) is active high.
* |[3] |ADSEPEN |EBI Address/Data Bus Separate Mode Enable Bit
* | | |0 = Address/Data Bus Separate Mode Disabled.
* | | |1 = Address/Data Bus Separate Mode Enabled.
* |[4] |CACCESS |Continuous Data Access Mode
* | | |When continuous access mode enabled, the tASU, tALE and tLHD cycles are bypass for continuous data transfer request.
* | | |0 = Continuous data access mode Disabled.
* | | |1 = Continuous data access mode Enabled.
* |[10:8] |MCLKDIV |External Output Clock Divider
* | | |The frequency of EBI output clock (MCLK) is controlled by MCLKDIV as follow:
* | | |000 = HCLK/1.
* | | |001 = HCLK/2.
* | | |010 = HCLK/4.
* | | |011 = HCLK/8.
* | | |100 = HCLK/16.
* | | |101 = HCLK/32.
* | | |110 = HCLK/64.
* | | |111 = HCLK/128.
* |[18:16] |TALE |Extend Time of ALE
* | | |The EBI_ALE high pulse period (tALE) to latch the address can be controlled by TALE.
* | | |tALE = (TALE+1)*EBI_MCLK.
* | | |Note: This field only available in EBI_CTL0 register.
* |[24] |WBUFEN |EBI Write Buffer Enable Bit
* | | |0 = EBI write buffer Disabled.
* | | |1 = EBI write buffer Enabled.
* | | |Note: This bit only available in EBI_CTL0 register.
* @var EBI_T::TCTL0
* Offset: 0x04 External Bus Interface Bank0 Timing Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:3] |TACC |EBI Data Access Time
* | | |TACC defines data access time (tACC).
* | | |tACC = (TACC +1) * EBI_MCLK.
* |[10:8] |TAHD |EBI Data Access Hold Time
* | | |TAHD defines data access hold time (tAHD).
* | | |tAHD = (TAHD +1) * EBI_MCLK.
* |[15:12] |W2X |Idle Cycle After Write
* | | |This field defines the number of W2X idle cycle.
* | | |W2X idle cycle = (W2X * EBI_MCLK).
* | | |When write action is finished, W2X idle cycle is inserted and EBI_nCS return to idle state.
* |[22] |RAHDOFF |Access Hold Time Disable Control When Read
* | | |0 = Data Access Hold Time (tAHD) during EBI reading Enabled.
* | | |1 = Data Access Hold Time (tAHD) during EBI reading Disabled.
* |[23] |WAHDOFF |Access Hold Time Disable Control When Write
* | | |0 = Data Access Hold Time (tAHD) during EBI writing Enabled.
* | | |1 = Data Access Hold Time (tAHD) during EBI writing Disabled.
* |[27:24] |R2R |Idle Cycle Between Read-to-read
* | | |This field defines the number of R2R idle cycle.
* | | |R2R idle cycle = (R2R * EBI_MCLK).
* | | |When read action is finished and the next action is going to read, R2R idle cycle is inserted and EBI_nCS return to idle state.
* @var EBI_T::CTL1
* Offset: 0x10 External Bus Interface Bank1 Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |EN |EBI Enable Bit
* | | |This bit is the functional enable bit for EBI.
* | | |0 = EBI function Disabled.
* | | |1 = EBI function Enabled.
* |[1] |DW16 |EBI Data Width 16-bit Select
* | | |This bit defines if the EBI data width is 8-bit or 16-bit.
* | | |0 = EBI data width is 8-bit.
* | | |1 = EBI data width is 16-bit.
* |[2] |CSPOLINV |Chip Select Pin Polar Inverse
* | | |This bit defines the active level of EBI chip select pin (EBI_nCS).
* | | |0 = Chip select pin (EBI_nCS) is active low.
* | | |1 = Chip select pin (EBI_nCS) is active high.
* |[3] |ADSEPEN |EBI Address/Data Bus Separate Mode Enable Bit
* | | |0 = Address/Data Bus Separate Mode Disabled.
* | | |1 = Address/Data Bus Separate Mode Enabled.
* |[4] |CACCESS |Continuous Data Access Mode
* | | |When continuous access mode enabled, the tASU, tALE and tLHD cycles are bypass for continuous data transfer request.
* | | |0 = Continuous data access mode Disabled.
* | | |1 = Continuous data access mode Enabled.
* |[10:8] |MCLKDIV |External Output Clock Divider
* | | |The frequency of EBI output clock (MCLK) is controlled by MCLKDIV as follow:
* | | |000 = HCLK/1.
* | | |001 = HCLK/2.
* | | |010 = HCLK/4.
* | | |011 = HCLK/8.
* | | |100 = HCLK/16.
* | | |101 = HCLK/32.
* | | |110 = HCLK/64.
* | | |111 = HCLK/128.
* |[18:16] |TALE |Extend Time of ALE
* | | |The EBI_ALE high pulse period (tALE) to latch the address can be controlled by TALE.
* | | |tALE = (TALE+1)*EBI_MCLK.
* | | |Note: This field only available in EBI_CTL0 register.
* |[24] |WBUFEN |EBI Write Buffer Enable Bit
* | | |0 = EBI write buffer Disabled.
* | | |1 = EBI write buffer Enabled.
* | | |Note: This bit only available in EBI_CTL0 register.
* @var EBI_T::TCTL1
* Offset: 0x14 External Bus Interface Bank1 Timing Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:3] |TACC |EBI Data Access Time
* | | |TACC defines data access time (tACC).
* | | |tACC = (TACC +1) * EBI_MCLK.
* |[10:8] |TAHD |EBI Data Access Hold Time
* | | |TAHD defines data access hold time (tAHD).
* | | |tAHD = (TAHD +1) * EBI_MCLK.
* |[15:12] |W2X |Idle Cycle After Write
* | | |This field defines the number of W2X idle cycle.
* | | |W2X idle cycle = (W2X * EBI_MCLK).
* | | |When write action is finished, W2X idle cycle is inserted and EBI_nCS return to idle state.
* |[22] |RAHDOFF |Access Hold Time Disable Control When Read
* | | |0 = Data Access Hold Time (tAHD) during EBI reading Enabled.
* | | |1 = Data Access Hold Time (tAHD) during EBI reading Disabled.
* |[23] |WAHDOFF |Access Hold Time Disable Control When Write
* | | |0 = Data Access Hold Time (tAHD) during EBI writing Enabled.
* | | |1 = Data Access Hold Time (tAHD) during EBI writing Disabled.
* |[27:24] |R2R |Idle Cycle Between Read-to-read
* | | |This field defines the number of R2R idle cycle.
* | | |R2R idle cycle = (R2R * EBI_MCLK).
* | | |When read action is finished and the next action is going to read, R2R idle cycle is inserted and EBI_nCS return to idle state.
* @var EBI_T::CTL2
* Offset: 0x20 External Bus Interface Bank2 Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |EN |EBI Enable Bit
* | | |This bit is the functional enable bit for EBI.
* | | |0 = EBI function Disabled.
* | | |1 = EBI function Enabled.
* |[1] |DW16 |EBI Data Width 16-bit Select
* | | |This bit defines if the EBI data width is 8-bit or 16-bit.
* | | |0 = EBI data width is 8-bit.
* | | |1 = EBI data width is 16-bit.
* |[2] |CSPOLINV |Chip Select Pin Polar Inverse
* | | |This bit defines the active level of EBI chip select pin (EBI_nCS).
* | | |0 = Chip select pin (EBI_nCS) is active low.
* | | |1 = Chip select pin (EBI_nCS) is active high.
* |[3] |ADSEPEN |EBI Address/Data Bus Separate Mode Enable Bit
* | | |0 = Address/Data Bus Separate Mode Disabled.
* | | |1 = Address/Data Bus Separate Mode Enabled.
* |[4] |CACCESS |Continuous Data Access Mode
* | | |When continuous access mode enabled, the tASU, tALE and tLHD cycles are bypass for continuous data transfer request.
* | | |0 = Continuous data access mode Disabled.
* | | |1 = Continuous data access mode Enabled.
* |[10:8] |MCLKDIV |External Output Clock Divider
* | | |The frequency of EBI output clock (MCLK) is controlled by MCLKDIV as follow:
* | | |000 = HCLK/1.
* | | |001 = HCLK/2.
* | | |010 = HCLK/4.
* | | |011 = HCLK/8.
* | | |100 = HCLK/16.
* | | |101 = HCLK/32.
* | | |110 = HCLK/64.
* | | |111 = HCLK/128.
* |[18:16] |TALE |Extend Time of ALE
* | | |The EBI_ALE high pulse period (tALE) to latch the address can be controlled by TALE.
* | | |tALE = (TALE+1)*EBI_MCLK.
* | | |Note: This field only available in EBI_CTL0 register.
* |[24] |WBUFEN |EBI Write Buffer Enable Bit
* | | |0 = EBI write buffer Disabled.
* | | |1 = EBI write buffer Enabled.
* | | |Note: This bit only available in EBI_CTL0 register.
* @var EBI_T::TCTL2
* Offset: 0x24 External Bus Interface Bank2 Timing Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:3] |TACC |EBI Data Access Time
* | | |TACC defines data access time (tACC).
* | | |tACC = (TACC +1) * EBI_MCLK.
* |[10:8] |TAHD |EBI Data Access Hold Time
* | | |TAHD defines data access hold time (tAHD).
* | | |tAHD = (TAHD +1) * EBI_MCLK.
* |[15:12] |W2X |Idle Cycle After Write
* | | |This field defines the number of W2X idle cycle.
* | | |W2X idle cycle = (W2X * EBI_MCLK).
* | | |When write action is finished, W2X idle cycle is inserted and EBI_nCS return to idle state.
* |[22] |RAHDOFF |Access Hold Time Disable Control When Read
* | | |0 = Data Access Hold Time (tAHD) during EBI reading Enabled.
* | | |1 = Data Access Hold Time (tAHD) during EBI reading Disabled.
* |[23] |WAHDOFF |Access Hold Time Disable Control When Write
* | | |0 = Data Access Hold Time (tAHD) during EBI writing Enabled.
* | | |1 = Data Access Hold Time (tAHD) during EBI writing Disabled.
* |[27:24] |R2R |Idle Cycle Between Read-to-read
* | | |This field defines the number of R2R idle cycle.
* | | |R2R idle cycle = (R2R * EBI_MCLK).
* | | |When read action is finished and the next action is going to read, R2R idle cycle is inserted and EBI_nCS return to idle state.
*/
__IO uint32_t CTL0; /*!< [0x0000] External Bus Interface Bank0 Control Register */
__IO uint32_t TCTL0; /*!< [0x0004] External Bus Interface Bank0 Timing Control Register */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE0[2];
/// @endcond //HIDDEN_SYMBOLS
__IO uint32_t CTL1; /*!< [0x0010] External Bus Interface Bank1 Control Register */
__IO uint32_t TCTL1; /*!< [0x0014] External Bus Interface Bank1 Timing Control Register */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE1[2];
/// @endcond //HIDDEN_SYMBOLS
__IO uint32_t CTL2; /*!< [0x0020] External Bus Interface Bank2 Control Register */
__IO uint32_t TCTL2; /*!< [0x0024] External Bus Interface Bank2 Timing Control Register */
} EBI_T;
/**
@addtogroup EBI_CONST EBI Bit Field Definition
Constant Definitions for EBI Controller
@{ */
#define EBI_CTL_EN_Pos (0) /*!< EBI_T::CTL: EN Position */
#define EBI_CTL_EN_Msk (0x1ul << EBI_CTL_EN_Pos) /*!< EBI_T::CTL: EN Mask */
#define EBI_CTL_DW16_Pos (1) /*!< EBI_T::CTL: DW16 Position */
#define EBI_CTL_DW16_Msk (0x1ul << EBI_CTL_DW16_Pos) /*!< EBI_T::CTL: DW16 Mask */
#define EBI_CTL_CSPOLINV_Pos (2) /*!< EBI_T::CTL: CSPOLINV Position */
#define EBI_CTL_CSPOLINV_Msk (0x1ul << EBI_CTL_CSPOLINV_Pos) /*!< EBI_T::CTL: CSPOLINV Mask */
#define EBI_CTL_ADSEPEN_Pos (3) /*!< EBI_T::CTL: ADSEPEN Position */
#define EBI_CTL_ADSEPEN_Msk (0x1ul << EBI_CTL_ADSEPEN_Pos) /*!< EBI_T::CTL: ADSEPEN Mask */
#define EBI_CTL_CACCESS_Pos (4) /*!< EBI_T::CTL: CACCESS Position */
#define EBI_CTL_CACCESS_Msk (0x1ul << EBI_CTL_CACCESS_Pos) /*!< EBI_T::CTL: CACCESS Mask */
#define EBI_CTL_MCLKDIV_Pos (8) /*!< EBI_T::CTL: MCLKDIV Position */
#define EBI_CTL_MCLKDIV_Msk (0x7ul << EBI_CTL_MCLKDIV_Pos) /*!< EBI_T::CTL: MCLKDIV Mask */
#define EBI_CTL_TALE_Pos (16) /*!< EBI_T::CTL: TALE Position */
#define EBI_CTL_TALE_Msk (0x7ul << EBI_CTL_TALE_Pos) /*!< EBI_T::CTL: TALE Mask */
#define EBI_CTL_WBUFEN_Pos (24) /*!< EBI_T::CTL: WBUFEN Position */
#define EBI_CTL_WBUFEN_Msk (0x1ul << EBI_CTL_WBUFEN_Pos) /*!< EBI_T::CTL: WBUFEN Mask */
#define EBI_TCTL_TACC_Pos (3) /*!< EBI_T::TCTL: TACC Position */
#define EBI_TCTL_TACC_Msk (0x1ful << EBI_TCTL_TACC_Pos) /*!< EBI_T::TCTL: TACC Mask */
#define EBI_TCTL_TAHD_Pos (8) /*!< EBI_T::TCTL: TAHD Position */
#define EBI_TCTL_TAHD_Msk (0x7ul << EBI_TCTL_TAHD_Pos) /*!< EBI_T::TCTL: TAHD Mask */
#define EBI_TCTL_W2X_Pos (12) /*!< EBI_T::TCTL: W2X Position */
#define EBI_TCTL_W2X_Msk (0xful << EBI_TCTL_W2X_Pos) /*!< EBI_T::TCTL: W2X Mask */
#define EBI_TCTL_RAHDOFF_Pos (22) /*!< EBI_T::TCTL: RAHDOFF Position */
#define EBI_TCTL_RAHDOFF_Msk (0x1ul << EBI_TCTL_RAHDOFF_Pos) /*!< EBI_T::TCTL: RAHDOFF Mask */
#define EBI_TCTL_WAHDOFF_Pos (23) /*!< EBI_T::TCTL: WAHDOFF Position */
#define EBI_TCTL_WAHDOFF_Msk (0x1ul << EBI_TCTL_WAHDOFF_Pos) /*!< EBI_T::TCTL: WAHDOFF Mask */
#define EBI_TCTL_R2R_Pos (24) /*!< EBI_T::TCTL: R2R Position */
#define EBI_TCTL_R2R_Msk (0xful << EBI_TCTL_R2R_Pos) /*!< EBI_T::TCTL: R2R Mask */
#define EBI_CTL0_EN_Pos (0) /*!< EBI_T::CTL0: EN Position */
#define EBI_CTL0_EN_Msk (0x1ul << EBI_CTL0_EN_Pos) /*!< EBI_T::CTL0: EN Mask */
#define EBI_CTL0_DW16_Pos (1) /*!< EBI_T::CTL0: DW16 Position */
#define EBI_CTL0_DW16_Msk (0x1ul << EBI_CTL0_DW16_Pos) /*!< EBI_T::CTL0: DW16 Mask */
#define EBI_CTL0_CSPOLINV_Pos (2) /*!< EBI_T::CTL0: CSPOLINV Position */
#define EBI_CTL0_CSPOLINV_Msk (0x1ul << EBI_CTL0_CSPOLINV_Pos) /*!< EBI_T::CTL0: CSPOLINV Mask */
#define EBI_CTL0_ADSEPEN_Pos (3) /*!< EBI_T::CTL0: ADSEPEN Position */
#define EBI_CTL0_ADSEPEN_Msk (0x1ul << EBI_CTL0_ADSEPEN_Pos) /*!< EBI_T::CTL0: ADSEPEN Mask */
#define EBI_CTL0_CACCESS_Pos (4) /*!< EBI_T::CTL0: CACCESS Position */
#define EBI_CTL0_CACCESS_Msk (0x1ul << EBI_CTL0_CACCESS_Pos) /*!< EBI_T::CTL0: CACCESS Mask */
#define EBI_CTL0_MCLKDIV_Pos (8) /*!< EBI_T::CTL0: MCLKDIV Position */
#define EBI_CTL0_MCLKDIV_Msk (0x7ul << EBI_CTL0_MCLKDIV_Pos) /*!< EBI_T::CTL0: MCLKDIV Mask */
#define EBI_CTL0_TALE_Pos (16) /*!< EBI_T::CTL0: TALE Position */
#define EBI_CTL0_TALE_Msk (0x7ul << EBI_CTL0_TALE_Pos) /*!< EBI_T::CTL0: TALE Mask */
#define EBI_CTL0_WBUFEN_Pos (24) /*!< EBI_T::CTL0: WBUFEN Position */
#define EBI_CTL0_WBUFEN_Msk (0x1ul << EBI_CTL0_WBUFEN_Pos) /*!< EBI_T::CTL0: WBUFEN Mask */
#define EBI_TCTL0_TACC_Pos (3) /*!< EBI_T::TCTL0: TACC Position */
#define EBI_TCTL0_TACC_Msk (0x1ful << EBI_TCTL0_TACC_Pos) /*!< EBI_T::TCTL0: TACC Mask */
#define EBI_TCTL0_TAHD_Pos (8) /*!< EBI_T::TCTL0: TAHD Position */
#define EBI_TCTL0_TAHD_Msk (0x7ul << EBI_TCTL0_TAHD_Pos) /*!< EBI_T::TCTL0: TAHD Mask */
#define EBI_TCTL0_W2X_Pos (12) /*!< EBI_T::TCTL0: W2X Position */
#define EBI_TCTL0_W2X_Msk (0xful << EBI_TCTL0_W2X_Pos) /*!< EBI_T::TCTL0: W2X Mask */
#define EBI_TCTL0_RAHDOFF_Pos (22) /*!< EBI_T::TCTL0: RAHDOFF Position */
#define EBI_TCTL0_RAHDOFF_Msk (0x1ul << EBI_TCTL0_RAHDOFF_Pos) /*!< EBI_T::TCTL0: RAHDOFF Mask */
#define EBI_TCTL0_WAHDOFF_Pos (23) /*!< EBI_T::TCTL0: WAHDOFF Position */
#define EBI_TCTL0_WAHDOFF_Msk (0x1ul << EBI_TCTL0_WAHDOFF_Pos) /*!< EBI_T::TCTL0: WAHDOFF Mask */
#define EBI_TCTL0_R2R_Pos (24) /*!< EBI_T::TCTL0: R2R Position */
#define EBI_TCTL0_R2R_Msk (0xful << EBI_TCTL0_R2R_Pos) /*!< EBI_T::TCTL0: R2R Mask */
#define EBI_CTL1_EN_Pos (0) /*!< EBI_T::CTL1: EN Position */
#define EBI_CTL1_EN_Msk (0x1ul << EBI_CTL1_EN_Pos) /*!< EBI_T::CTL1: EN Mask */
#define EBI_CTL1_DW16_Pos (1) /*!< EBI_T::CTL1: DW16 Position */
#define EBI_CTL1_DW16_Msk (0x1ul << EBI_CTL1_DW16_Pos) /*!< EBI_T::CTL1: DW16 Mask */
#define EBI_CTL1_CSPOLINV_Pos (2) /*!< EBI_T::CTL1: CSPOLINV Position */
#define EBI_CTL1_CSPOLINV_Msk (0x1ul << EBI_CTL1_CSPOLINV_Pos) /*!< EBI_T::CTL1: CSPOLINV Mask */
#define EBI_CTL1_ADSEPEN_Pos (3) /*!< EBI_T::CTL1: ADSEPEN Position */
#define EBI_CTL1_ADSEPEN_Msk (0x1ul << EBI_CTL1_ADSEPEN_Pos) /*!< EBI_T::CTL1: ADSEPEN Mask */
#define EBI_CTL1_CACCESS_Pos (4) /*!< EBI_T::CTL1: CACCESS Position */
#define EBI_CTL1_CACCESS_Msk (0x1ul << EBI_CTL1_CACCESS_Pos) /*!< EBI_T::CTL1: CACCESS Mask */
#define EBI_CTL1_MCLKDIV_Pos (8) /*!< EBI_T::CTL1: MCLKDIV Position */
#define EBI_CTL1_MCLKDIV_Msk (0x7ul << EBI_CTL1_MCLKDIV_Pos) /*!< EBI_T::CTL1: MCLKDIV Mask */
#define EBI_CTL1_TALE_Pos (16) /*!< EBI_T::CTL1: TALE Position */
#define EBI_CTL1_TALE_Msk (0x7ul << EBI_CTL1_TALE_Pos) /*!< EBI_T::CTL1: TALE Mask */
#define EBI_CTL1_WBUFEN_Pos (24) /*!< EBI_T::CTL1: WBUFEN Position */
#define EBI_CTL1_WBUFEN_Msk (0x1ul << EBI_CTL1_WBUFEN_Pos) /*!< EBI_T::CTL1: WBUFEN Mask */
#define EBI_TCTL1_TACC_Pos (3) /*!< EBI_T::TCTL1: TACC Position */
#define EBI_TCTL1_TACC_Msk (0x1ful << EBI_TCTL1_TACC_Pos) /*!< EBI_T::TCTL1: TACC Mask */
#define EBI_TCTL1_TAHD_Pos (8) /*!< EBI_T::TCTL1: TAHD Position */
#define EBI_TCTL1_TAHD_Msk (0x7ul << EBI_TCTL1_TAHD_Pos) /*!< EBI_T::TCTL1: TAHD Mask */
#define EBI_TCTL1_W2X_Pos (12) /*!< EBI_T::TCTL1: W2X Position */
#define EBI_TCTL1_W2X_Msk (0xful << EBI_TCTL1_W2X_Pos) /*!< EBI_T::TCTL1: W2X Mask */
#define EBI_TCTL1_RAHDOFF_Pos (22) /*!< EBI_T::TCTL1: RAHDOFF Position */
#define EBI_TCTL1_RAHDOFF_Msk (0x1ul << EBI_TCTL1_RAHDOFF_Pos) /*!< EBI_T::TCTL1: RAHDOFF Mask */
#define EBI_TCTL1_WAHDOFF_Pos (23) /*!< EBI_T::TCTL1: WAHDOFF Position */
#define EBI_TCTL1_WAHDOFF_Msk (0x1ul << EBI_TCTL1_WAHDOFF_Pos) /*!< EBI_T::TCTL1: WAHDOFF Mask */
#define EBI_TCTL1_R2R_Pos (24) /*!< EBI_T::TCTL1: R2R Position */
#define EBI_TCTL1_R2R_Msk (0xful << EBI_TCTL1_R2R_Pos) /*!< EBI_T::TCTL1: R2R Mask */
#define EBI_CTL2_EN_Pos (0) /*!< EBI_T::CTL2: EN Position */
#define EBI_CTL2_EN_Msk (0x1ul << EBI_CTL2_EN_Pos) /*!< EBI_T::CTL2: EN Mask */
#define EBI_CTL2_DW16_Pos (1) /*!< EBI_T::CTL2: DW16 Position */
#define EBI_CTL2_DW16_Msk (0x1ul << EBI_CTL2_DW16_Pos) /*!< EBI_T::CTL2: DW16 Mask */
#define EBI_CTL2_CSPOLINV_Pos (2) /*!< EBI_T::CTL2: CSPOLINV Position */
#define EBI_CTL2_CSPOLINV_Msk (0x1ul << EBI_CTL2_CSPOLINV_Pos) /*!< EBI_T::CTL2: CSPOLINV Mask */
#define EBI_CTL2_ADSEPEN_Pos (3) /*!< EBI_T::CTL2: ADSEPEN Position */
#define EBI_CTL2_ADSEPEN_Msk (0x1ul << EBI_CTL2_ADSEPEN_Pos) /*!< EBI_T::CTL2: ADSEPEN Mask */
#define EBI_CTL2_CACCESS_Pos (4) /*!< EBI_T::CTL2: CACCESS Position */
#define EBI_CTL2_CACCESS_Msk (0x1ul << EBI_CTL2_CACCESS_Pos) /*!< EBI_T::CTL2: CACCESS Mask */
#define EBI_CTL2_MCLKDIV_Pos (8) /*!< EBI_T::CTL2: MCLKDIV Position */
#define EBI_CTL2_MCLKDIV_Msk (0x7ul << EBI_CTL2_MCLKDIV_Pos) /*!< EBI_T::CTL2: MCLKDIV Mask */
#define EBI_CTL2_TALE_Pos (16) /*!< EBI_T::CTL2: TALE Position */
#define EBI_CTL2_TALE_Msk (0x7ul << EBI_CTL2_TALE_Pos) /*!< EBI_T::CTL2: TALE Mask */
#define EBI_CTL2_WBUFEN_Pos (24) /*!< EBI_T::CTL2: WBUFEN Position */
#define EBI_CTL2_WBUFEN_Msk (0x1ul << EBI_CTL2_WBUFEN_Pos) /*!< EBI_T::CTL2: WBUFEN Mask */
#define EBI_TCTL2_TACC_Pos (3) /*!< EBI_T::TCTL2: TACC Position */
#define EBI_TCTL2_TACC_Msk (0x1ful << EBI_TCTL2_TACC_Pos) /*!< EBI_T::TCTL2: TACC Mask */
#define EBI_TCTL2_TAHD_Pos (8) /*!< EBI_T::TCTL2: TAHD Position */
#define EBI_TCTL2_TAHD_Msk (0x7ul << EBI_TCTL2_TAHD_Pos) /*!< EBI_T::TCTL2: TAHD Mask */
#define EBI_TCTL2_W2X_Pos (12) /*!< EBI_T::TCTL2: W2X Position */
#define EBI_TCTL2_W2X_Msk (0xful << EBI_TCTL2_W2X_Pos) /*!< EBI_T::TCTL2: W2X Mask */
#define EBI_TCTL2_RAHDOFF_Pos (22) /*!< EBI_T::TCTL2: RAHDOFF Position */
#define EBI_TCTL2_RAHDOFF_Msk (0x1ul << EBI_TCTL2_RAHDOFF_Pos) /*!< EBI_T::TCTL2: RAHDOFF Mask */
#define EBI_TCTL2_WAHDOFF_Pos (23) /*!< EBI_T::TCTL2: WAHDOFF Position */
#define EBI_TCTL2_WAHDOFF_Msk (0x1ul << EBI_TCTL2_WAHDOFF_Pos) /*!< EBI_T::TCTL2: WAHDOFF Mask */
#define EBI_TCTL2_R2R_Pos (24) /*!< EBI_T::TCTL2: R2R Position */
#define EBI_TCTL2_R2R_Msk (0xful << EBI_TCTL2_R2R_Pos) /*!< EBI_T::TCTL2: R2R Mask */
/**@}*/ /* EBI_CONST */
/**@}*/ /* end of EBI register group */
/**@}*/ /* end of REGISTER group */
#if defined ( __CC_ARM )
#pragma no_anon_unions
#endif
#endif /* __EBI_REG_H__ */

389
bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/ecap_reg.h Normal file
View File

@ -0,0 +1,389 @@
/**************************************************************************//**
* @file ecap_reg.h
* @brief ECAP register definition header file
*
* SPDX-License-Identifier: Apache-2.0
* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __ECAP_REG_H__
#define __ECAP_REG_H__
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
/**
@addtogroup REGISTER Control Register
@{
*/
/**
@addtogroup ECAP Enhanced Input Capture Timer(ECAP)
Memory Mapped Structure for ECAP Controller
@{ */
typedef struct
{
/**
* @var ECAP_T::CNT
* Offset: 0x00 Input Capture Counter (24-bit up counter)
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[23:0] |CNT |Input Capture Timer/Counter
* | | |The input Capture Timer/Counter is a 24-bit up-counting counter
* | | |The clock source for the counter is from the clock divider
* @var ECAP_T::HLD0
* Offset: 0x04 Input Capture Hold Register 0
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[23:0] |HOLD |Input Capture Counter Hold Register
* | | |When an active input capture channel detects a valid edge signal change, the ECAPCNT value is latched into the corresponding holding register
* | | |Each input channel has its own holding register named by ECAP_HLDx where x is from 0 to 2 to indicate inputs from IC0 to IC2, respectively.
* @var ECAP_T::HLD1
* Offset: 0x08 Input Capture Hold Register 1
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[23:0] |HOLD |Input Capture Counter Hold Register
* | | |When an active input capture channel detects a valid edge signal change, the ECAPCNT value is latched into the corresponding holding register
* | | |Each input channel has its own holding register named by ECAP_HLDx where x is from 0 to 2 to indicate inputs from IC0 to IC2, respectively.
* @var ECAP_T::HLD2
* Offset: 0x0C Input Capture Hold Register 2
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[23:0] |HOLD |Input Capture Counter Hold Register
* | | |When an active input capture channel detects a valid edge signal change, the ECAPCNT value is latched into the corresponding holding register
* | | |Each input channel has its own holding register named by ECAP_HLDx where x is from 0 to 2 to indicate inputs from IC0 to IC2, respectively.
* @var ECAP_T::CNTCMP
* Offset: 0x10 Input Capture Compare Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[23:0] |CNTCMP |Input Capture Counter Compare Register
* | | |If the compare function is enabled (CMPEN = 1), this register (ECAP_CNTCMP) is used to compare with the capture counter (ECAP_CNT).
* | | |If the reload control is enabled (RLDEN[n] = 1, n=0~3), an overflow event or capture events will trigger the hardware to load the value of this register (ECAP_CNTCMP) into ECAP_CNT.
* @var ECAP_T::CTL0
* Offset: 0x14 Input Capture Control Register 0
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[2:0] |NFCLKSEL |Noise Filter Clock Pre-divide Selection
* | | |To determine the sampling frequency of the Noise Filter clock
* | | |000 = CAP_CLK.
* | | |001 = CAP_CLK/2.
* | | |010 = CAP_CLK/4.
* | | |011 = CAP_CLK/16.
* | | |100 = CAP_CLK/32.
* | | |101 = CAP_CLK/64.
* |[3] |CAPNFDIS |Input Capture Noise Filter Disable Control
* | | |0 = Noise filter of Input Capture Enabled.
* | | |1 = Noise filter of Input Capture Disabled (Bypass).
* |[4] |IC0EN |Port Pin IC0 Input to Input Capture Unit Enable Control
* | | |0 = IC0 input to Input Capture Unit Disabled.
* | | |1 = IC0 input to Input Capture Unit Enabled.
* |[5] |IC1EN |Port Pin IC1 Input to Input Capture Unit Enable Control
* | | |0 = IC1 input to Input Capture Unit Disabled.
* | | |1 = IC1 input to Input Capture Unit Enabled.
* |[6] |IC2EN |Port Pin IC2 Input to Input Capture Unit Enable Control
* | | |0 = IC2 input to Input Capture Unit Disabled.
* | | |1 = IC2 input to Input Capture Unit Enabled.
* |[9:8] |CAPSEL0 |CAP0 Input Source Selection
* | | |00 = CAP0 input is from port pin ICAP0.
* | | |01 = Reserved.
* | | |10 = CAP0 input is from signal CHA of QEI controller unit n.
* | | |11 = Reserved.
* | | |Note: Input capture unit n matches QEIn, where n = 0~1.
* |[11:10] |CAPSEL1 |CAP1 Input Source Selection
* | | |00 = CAP1 input is from port pin ICAP1.
* | | |01 = Reserved.
* | | |10 = CAP1 input is from signal CHB of QEI controller unit n.
* | | |11 = Reserved.
* | | |Note: Input capture unit n matches QEIn, where n = 0~1.
* |[13:12] |CAPSEL2 |CAP2 Input Source Selection
* | | |00 = CAP2 input is from port pin ICAP2.
* | | |01 = Reserved.
* | | |10 = CAP2 input is from signal CHX of QEI controller unit n.
* | | |11 = Reserved.
* | | |Note: Input capture unit n matches QEIn, where n = 0~1.
* |[16] |CAPIEN0 |Input Capture Channel 0 Interrupt Enable Control
* | | |0 = The flag CAPTF0 can trigger Input Capture interrupt Disabled.
* | | |1 = The flag CAPTF0 can trigger Input Capture interrupt Enabled.
* |[17] |CAPIEN1 |Input Capture Channel 1 Interrupt Enable Control
* | | |0 = The flag CAPTF1 can trigger Input Capture interrupt Disabled.
* | | |1 = The flag CAPTF1 can trigger Input Capture interrupt Enabled.
* |[18] |CAPIEN2 |Input Capture Channel 2 Interrupt Enable Control
* | | |0 = The flag CAPTF2 can trigger Input Capture interrupt Disabled.
* | | |1 = The flag CAPTF2 can trigger Input Capture interrupt Enabled.
* |[20] |OVIEN |CAPOVF Trigger Input Capture Interrupt Enable Control
* | | |0 = The flag CAPOVF can trigger Input Capture interrupt Disabled.
* | | |1 = The flag CAPOVF can trigger Input Capture interrupt Enabled.
* |[21] |CMPIEN |CAPCMPF Trigger Input Capture Interrupt Enable Control
* | | |0 = The flag CAPCMPF can trigger Input Capture interrupt Disabled.
* | | |1 = The flag CAPCMPF can trigger Input Capture interrupt Enabled.
* |[24] |CNTEN |Input Capture Counter Start Counting Control
* | | |Setting this bit to 1, the capture counter (ECAP_CNT) starts up-counting synchronously with the clock from the .
* | | |0 = ECAP_CNT stop counting.
* | | |1 = ECAP_CNT starts up-counting.
* |[25] |CMPCLREN |Input Capture Counter Cleared by Compare-match Control
* | | |If this bit is set to 1, the capture counter (ECAP_CNT) will be cleared to 0 when the compare-match event (CAPCMPF = 1) occurs.
* | | |0 = Compare-match event (CAPCMPF) can clear capture counter (ECAP_CNT) Disabled.
* | | |1 = Compare-match event (CAPCMPF) can clear capture counter (ECAP_CNT) Enabled.
* |[28] |CMPEN |Compare Function Enable Control
* | | |The compare function in input capture timer/counter is to compare the dynamic counting ECAP_CNT with the compare register ECAP_CNTCMP, if ECAP_CNT value reaches ECAP_CNTCMP, the flag CAPCMPF will be set.
* | | |0 = The compare function Disabled.
* | | |1 = The compare function Enabled.
* |[29] |CAPEN |Input Capture Timer/Counter Enable Control
* | | |0 = Input Capture function Disabled.
* | | |1 = Input Capture function Enabled.
* @var ECAP_T::CTL1
* Offset: 0x18 Input Capture Control Register 1
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[1:0] |EDGESEL0 |Channel 0 Captured Edge Selection
* | | |Input capture0 can detect falling edge change only, rising edge change only or both edge change
* | | |00 = Detect rising edge only.
* | | |01 = Detect falling edge only.
* | | |1x = Detect both rising and falling edge.
* |[3:2] |EDGESEL1 |Channel 1 Captured Edge Selection
* | | |Input capture1 can detect falling edge change only, rising edge change only or both edge change
* | | |00 = Detect rising edge only.
* | | |01 = Detect falling edge only.
* | | |1x = Detect both rising and falling edge.
* |[5:4] |EDGESEL2 |Channel 2 Captured Edge Selection
* | | |Input capture2 can detect falling edge change only, rising edge change only or both edge changes
* | | |00 = Detect rising edge only.
* | | |01 = Detect falling edge only.
* | | |1x = Detect both rising and falling edge.
* |[8] |CAP0RLDEN |Capture Counter Reload Function Triggered by Event CAPTE0 Enable Bit
* | | |0 = The reload triggered by Event CAPTE0 Disabled.
* | | |1 = The reload triggered by Event CAPTE0 Enabled.
* |[9] |CAP1RLDEN |Capture Counter Reload Function Triggered by Event CAPTE1 Enable Bit
* | | |0 = The reload triggered by Event CAPTE1 Disabled.
* | | |1 = The reload triggered by Event CAPTE1 Enabled.
* |[10] |CAP2RLDEN |Capture Counter Reload Function Triggered by Event CAPTE2 Enable Bit
* | | |0 = The reload triggered by Event CAPTE2 Disabled.
* | | |1 = The reload triggered by Event CAPTE2 Enabled.
* |[11] |OVRLDEN |Capture Counter Reload Function Triggered by Overflow Enable Bit
* | | |0 = The reload triggered by CAPOV Disabled.
* | | |1 = The reload triggered by CAPOV Enabled.
* |[14:12] |CLKSEL |Capture Timer Clock Divide Selection
* | | |The capture timer clock has a pre-divider with eight divided options controlled by CLKSEL[2:0].
* | | |000 = CAP_CLK/1.
* | | |001 = CAP_CLK/4.
* | | |010 = CAP_CLK/16.
* | | |011 = CAP_CLK/32.
* | | |100 = CAP_CLK/64.
* | | |101 = CAP_CLK/96.
* | | |110 = CAP_CLK/112.
* | | |111 = CAP_CLK/128.
* |[17:16] |CNTSRCSEL |Capture Timer/Counter Clock Source Selection
* | | |Select the capture timer/counter clock source.
* | | |00 = CAP_CLK (default).
* | | |01 = CAP0.
* | | |10 = CAP1.
* | | |11 = CAP2.
* |[20] |CAP0CLREN |Capture Counter Cleared by Capture Event0 Control
* | | |0 = Event CAPTE0 can clear capture counter (ECAP_CNT) Disabled.
* | | |1 = Event CAPTE0 can clear capture counter (ECAP_CNT) Enabled.
* |[21] |CAP1CLREN |Capture Counter Cleared by Capture Event1 Control
* | | |0 = Event CAPTE1 can clear capture counter (ECAP_CNT) Disabled.
* | | |1 = Event CAPTE1 can clear capture counter (ECAP_CNT) Enabled.
* |[22] |CAP2CLREN |Capture Counter Cleared by Capture Event2 Control
* | | |0 = Event CAPTE2 can clear capture counter (ECAP_CNT) Disabled.
* | | |1 = Event CAPTE2 can clear capture counter (ECAP_CNT) Enabled.
* @var ECAP_T::STATUS
* Offset: 0x1C Input Capture Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |CAPTF0 |Input Capture Channel 0 Triggered Flag
* | | |When the input capture channel 0 detects a valid edge change at CAP0 input, it will set flag CAPTF0 to high.
* | | |0 = No valid edge change has been detected at CAP0 input since last clear.
* | | |1 = At least a valid edge change has been detected at CAP0 input since last clear.
* | | |Note: This bit is only cleared by writing 1 to it.
* |[1] |CAPTF1 |Input Capture Channel 1 Triggered Flag
* | | |When the input capture channel 1 detects a valid edge change at CAP1 input, it will set flag CAPTF1 to high.
* | | |0 = No valid edge change has been detected at CAP1 input since last clear.
* | | |1 = At least a valid edge change has been detected at CAP1 input since last clear.
* | | |Note: This bit is only cleared by writing 1 to it.
* |[2] |CAPTF2 |Input Capture Channel 2 Triggered Flag
* | | |When the input capture channel 2 detects a valid edge change at CAP2 input, it will set flag CAPTF2 to high.
* | | |0 = No valid edge change has been detected at CAP2 input since last clear.
* | | |1 = At least a valid edge change has been detected at CAP2 input since last clear.
* | | |Note: This bit is only cleared by writing 1 to it.
* |[4] |CAPCMPF |Input Capture Compare-match Flag
* | | |If the input capture compare function is enabled, the flag is set by hardware when capture counter (ECAP_CNT) up counts and reaches the ECAP_CNTCMP value.
* | | |0 = ECAP_CNT has not matched ECAP_CNTCMP value since last clear.
* | | |1 = ECAP_CNT has matched ECAP_CNTCMP value at least once since last clear.
* | | |Note: This bit is only cleared by writing 1 to it.
* |[5] |CAPOVF |Input Capture Counter Overflow Flag
* | | |Flag is set by hardware when counter (ECAP_CNT) overflows from 0x00FF_FFFF to zero.
* | | |0 = No overflow event has occurred since last clear.
* | | |1 = Overflow event(s) has/have occurred since last clear.
* | | |Note: This bit is only cleared by writing 1 to it.
* |[6] |CAP0 |Value of Input Channel 0, CAP0 (Read Only)
* | | |Reflecting the value of input channel 0, CAP0
* | | |(The bit is read only and write is ignored)
* |[7] |CAP1 |Value of Input Channel 1, CAP1 (Read Only)
* | | |Reflecting the value of input channel 1, CAP1
* | | |(The bit is read only and write is ignored)
* |[8] |CAP2 |Value of Input Channel 2, CAP2 (Read Only)
* | | |Reflecting the value of input channel 2, CAP2.
* | | |(The bit is read only and write is ignored)
*/
__IO uint32_t CNT; /*!< [0x0000] Input Capture Counter */
__IO uint32_t HLD0; /*!< [0x0004] Input Capture Hold Register 0 */
__IO uint32_t HLD1; /*!< [0x0008] Input Capture Hold Register 1 */
__IO uint32_t HLD2; /*!< [0x000c] Input Capture Hold Register 2 */
__IO uint32_t CNTCMP; /*!< [0x0010] Input Capture Compare Register */
__IO uint32_t CTL0; /*!< [0x0014] Input Capture Control Register 0 */
__IO uint32_t CTL1; /*!< [0x0018] Input Capture Control Register 1 */
__IO uint32_t STATUS; /*!< [0x001c] Input Capture Status Register */
} ECAP_T;
/**
@addtogroup ECAP_CONST ECAP Bit Field Definition
Constant Definitions for ECAP Controller
@{ */
#define ECAP_CNT_CNT_Pos (0) /*!< ECAP_T::CNT: CNT Position */
#define ECAP_CNT_CNT_Msk (0xfffffful << ECAP_CNT_CNT_Pos) /*!< ECAP_T::CNT: CNT Mask */
#define ECAP_HLD0_HOLD_Pos (0) /*!< ECAP_T::HLD0: HOLD Position */
#define ECAP_HLD0_HOLD_Msk (0xfffffful << ECAP_HLD0_HOLD_Pos) /*!< ECAP_T::HLD0: HOLD Mask */
#define ECAP_HLD1_HOLD_Pos (0) /*!< ECAP_T::HLD1: HOLD Position */
#define ECAP_HLD1_HOLD_Msk (0xfffffful << ECAP_HLD1_HOLD_Pos) /*!< ECAP_T::HLD1: HOLD Mask */
#define ECAP_HLD2_HOLD_Pos (0) /*!< ECAP_T::HLD2: HOLD Position */
#define ECAP_HLD2_HOLD_Msk (0xfffffful << ECAP_HLD2_HOLD_Pos) /*!< ECAP_T::HLD2: HOLD Mask */
#define ECAP_CNTCMP_CNTCMP_Pos (0) /*!< ECAP_T::CNTCMP: CNTCMP Position */
#define ECAP_CNTCMP_CNTCMP_Msk (0xfffffful << ECAP_CNTCMP_CNTCMP_Pos) /*!< ECAP_T::CNTCMP: CNTCMP Mask */
#define ECAP_CTL0_NFCLKSEL_Pos (0) /*!< ECAP_T::CTL0: NFCLKSEL Position */
#define ECAP_CTL0_NFCLKSEL_Msk (0x7ul << ECAP_CTL0_NFCLKSEL_Pos) /*!< ECAP_T::CTL0: NFCLKSEL Mask */
#define ECAP_CTL0_CAPNFDIS_Pos (3) /*!< ECAP_T::CTL0: CAPNFDIS Position */
#define ECAP_CTL0_CAPNFDIS_Msk (0x1ul << ECAP_CTL0_CAPNFDIS_Pos) /*!< ECAP_T::CTL0: CAPNFDIS Mask */
#define ECAP_CTL0_IC0EN_Pos (4) /*!< ECAP_T::CTL0: IC0EN Position */
#define ECAP_CTL0_IC0EN_Msk (0x1ul << ECAP_CTL0_IC0EN_Pos) /*!< ECAP_T::CTL0: IC0EN Mask */
#define ECAP_CTL0_IC1EN_Pos (5) /*!< ECAP_T::CTL0: IC1EN Position */
#define ECAP_CTL0_IC1EN_Msk (0x1ul << ECAP_CTL0_IC1EN_Pos) /*!< ECAP_T::CTL0: IC1EN Mask */
#define ECAP_CTL0_IC2EN_Pos (6) /*!< ECAP_T::CTL0: IC2EN Position */
#define ECAP_CTL0_IC2EN_Msk (0x1ul << ECAP_CTL0_IC2EN_Pos) /*!< ECAP_T::CTL0: IC2EN Mask */
#define ECAP_CTL0_CAPSEL0_Pos (8) /*!< ECAP_T::CTL0: CAPSEL0 Position */
#define ECAP_CTL0_CAPSEL0_Msk (0x3ul << ECAP_CTL0_CAPSEL0_Pos) /*!< ECAP_T::CTL0: CAPSEL0 Mask */
#define ECAP_CTL0_CAPSEL1_Pos (10) /*!< ECAP_T::CTL0: CAPSEL1 Position */
#define ECAP_CTL0_CAPSEL1_Msk (0x3ul << ECAP_CTL0_CAPSEL1_Pos) /*!< ECAP_T::CTL0: CAPSEL1 Mask */
#define ECAP_CTL0_CAPSEL2_Pos (12) /*!< ECAP_T::CTL0: CAPSEL2 Position */
#define ECAP_CTL0_CAPSEL2_Msk (0x3ul << ECAP_CTL0_CAPSEL2_Pos) /*!< ECAP_T::CTL0: CAPSEL2 Mask */
#define ECAP_CTL0_CAPIEN0_Pos (16) /*!< ECAP_T::CTL0: CAPIEN0 Position */
#define ECAP_CTL0_CAPIEN0_Msk (0x1ul << ECAP_CTL0_CAPIEN0_Pos) /*!< ECAP_T::CTL0: CAPIEN0 Mask */
#define ECAP_CTL0_CAPIEN1_Pos (17) /*!< ECAP_T::CTL0: CAPIEN1 Position */
#define ECAP_CTL0_CAPIEN1_Msk (0x1ul << ECAP_CTL0_CAPIEN1_Pos) /*!< ECAP_T::CTL0: CAPIEN1 Mask */
#define ECAP_CTL0_CAPIEN2_Pos (18) /*!< ECAP_T::CTL0: CAPIEN2 Position */
#define ECAP_CTL0_CAPIEN2_Msk (0x1ul << ECAP_CTL0_CAPIEN2_Pos) /*!< ECAP_T::CTL0: CAPIEN2 Mask */
#define ECAP_CTL0_OVIEN_Pos (20) /*!< ECAP_T::CTL0: OVIEN Position */
#define ECAP_CTL0_OVIEN_Msk (0x1ul << ECAP_CTL0_OVIEN_Pos) /*!< ECAP_T::CTL0: OVIEN Mask */
#define ECAP_CTL0_CMPIEN_Pos (21) /*!< ECAP_T::CTL0: CMPIEN Position */
#define ECAP_CTL0_CMPIEN_Msk (0x1ul << ECAP_CTL0_CMPIEN_Pos) /*!< ECAP_T::CTL0: CMPIEN Mask */
#define ECAP_CTL0_CNTEN_Pos (24) /*!< ECAP_T::CTL0: CNTEN Position */
#define ECAP_CTL0_CNTEN_Msk (0x1ul << ECAP_CTL0_CNTEN_Pos) /*!< ECAP_T::CTL0: CNTEN Mask */
#define ECAP_CTL0_CMPCLREN_Pos (25) /*!< ECAP_T::CTL0: CMPCLREN Position */
#define ECAP_CTL0_CMPCLREN_Msk (0x1ul << ECAP_CTL0_CMPCLREN_Pos) /*!< ECAP_T::CTL0: CMPCLREN Mask */
#define ECAP_CTL0_CMPEN_Pos (28) /*!< ECAP_T::CTL0: CMPEN Position */
#define ECAP_CTL0_CMPEN_Msk (0x1ul << ECAP_CTL0_CMPEN_Pos) /*!< ECAP_T::CTL0: CMPEN Mask */
#define ECAP_CTL0_CAPEN_Pos (29) /*!< ECAP_T::CTL0: CAPEN Position */
#define ECAP_CTL0_CAPEN_Msk (0x1ul << ECAP_CTL0_CAPEN_Pos) /*!< ECAP_T::CTL0: CAPEN Mask */
#define ECAP_CTL1_EDGESEL0_Pos (0) /*!< ECAP_T::CTL1: EDGESEL0 Position */
#define ECAP_CTL1_EDGESEL0_Msk (0x3ul << ECAP_CTL1_EDGESEL0_Pos) /*!< ECAP_T::CTL1: EDGESEL0 Mask */
#define ECAP_CTL1_EDGESEL1_Pos (2) /*!< ECAP_T::CTL1: EDGESEL1 Position */
#define ECAP_CTL1_EDGESEL1_Msk (0x3ul << ECAP_CTL1_EDGESEL1_Pos) /*!< ECAP_T::CTL1: EDGESEL1 Mask */
#define ECAP_CTL1_EDGESEL2_Pos (4) /*!< ECAP_T::CTL1: EDGESEL2 Position */
#define ECAP_CTL1_EDGESEL2_Msk (0x3ul << ECAP_CTL1_EDGESEL2_Pos) /*!< ECAP_T::CTL1: EDGESEL2 Mask */
#define ECAP_CTL1_CAP0RLDEN_Pos (8) /*!< ECAP_T::CTL1: CAP0RLDEN Position */
#define ECAP_CTL1_CAP0RLDEN_Msk (0x1ul << ECAP_CTL1_CAP0RLDEN_Pos) /*!< ECAP_T::CTL1: CAP0RLDEN Mask */
#define ECAP_CTL1_CAP1RLDEN_Pos (9) /*!< ECAP_T::CTL1: CAP1RLDEN Position */
#define ECAP_CTL1_CAP1RLDEN_Msk (0x1ul << ECAP_CTL1_CAP1RLDEN_Pos) /*!< ECAP_T::CTL1: CAP1RLDEN Mask */
#define ECAP_CTL1_CAP2RLDEN_Pos (10) /*!< ECAP_T::CTL1: CAP2RLDEN Position */
#define ECAP_CTL1_CAP2RLDEN_Msk (0x1ul << ECAP_CTL1_CAP2RLDEN_Pos) /*!< ECAP_T::CTL1: CAP2RLDEN Mask */
#define ECAP_CTL1_OVRLDEN_Pos (11) /*!< ECAP_T::CTL1: OVRLDEN Position */
#define ECAP_CTL1_OVRLDEN_Msk (0x1ul << ECAP_CTL1_OVRLDEN_Pos) /*!< ECAP_T::CTL1: OVRLDEN Mask */
#define ECAP_CTL1_CLKSEL_Pos (12) /*!< ECAP_T::CTL1: CLKSEL Position */
#define ECAP_CTL1_CLKSEL_Msk (0x7ul << ECAP_CTL1_CLKSEL_Pos) /*!< ECAP_T::CTL1: CLKSEL Mask */
#define ECAP_CTL1_CNTSRCSEL_Pos (16) /*!< ECAP_T::CTL1: CNTSRCSEL Position */
#define ECAP_CTL1_CNTSRCSEL_Msk (0x3ul << ECAP_CTL1_CNTSRCSEL_Pos) /*!< ECAP_T::CTL1: CNTSRCSEL Mask */
#define ECAP_CTL1_CAP0CLREN_Pos (20) /*!< ECAP_T::CTL1: CAP0CLREN Position */
#define ECAP_CTL1_CAP0CLREN_Msk (0x1ul << ECAP_CTL1_CAP0CLREN_Pos) /*!< ECAP_T::CTL1: CAP0CLREN Mask */
#define ECAP_CTL1_CAP1CLREN_Pos (21) /*!< ECAP_T::CTL1: CAP1CLREN Position */
#define ECAP_CTL1_CAP1CLREN_Msk (0x1ul << ECAP_CTL1_CAP1CLREN_Pos) /*!< ECAP_T::CTL1: CAP1CLREN Mask */
#define ECAP_CTL1_CAP2CLREN_Pos (22) /*!< ECAP_T::CTL1: CAP2CLREN Position */
#define ECAP_CTL1_CAP2CLREN_Msk (0x1ul << ECAP_CTL1_CAP2CLREN_Pos) /*!< ECAP_T::CTL1: CAP2CLREN Mask */
#define ECAP_STATUS_CAPTF0_Pos (0) /*!< ECAP_T::STATUS: CAPTF0 Position */
#define ECAP_STATUS_CAPTF0_Msk (0x1ul << ECAP_STATUS_CAPTF0_Pos) /*!< ECAP_T::STATUS: CAPTF0 Mask */
#define ECAP_STATUS_CAPTF1_Pos (1) /*!< ECAP_T::STATUS: CAPTF1 Position */
#define ECAP_STATUS_CAPTF1_Msk (0x1ul << ECAP_STATUS_CAPTF1_Pos) /*!< ECAP_T::STATUS: CAPTF1 Mask */
#define ECAP_STATUS_CAPTF2_Pos (2) /*!< ECAP_T::STATUS: CAPTF2 Position */
#define ECAP_STATUS_CAPTF2_Msk (0x1ul << ECAP_STATUS_CAPTF2_Pos) /*!< ECAP_T::STATUS: CAPTF2 Mask */
#define ECAP_STATUS_CAPCMPF_Pos (4) /*!< ECAP_T::STATUS: CAPCMPF Position */
#define ECAP_STATUS_CAPCMPF_Msk (0x1ul << ECAP_STATUS_CAPCMPF_Pos) /*!< ECAP_T::STATUS: CAPCMPF Mask */
#define ECAP_STATUS_CAPOVF_Pos (5) /*!< ECAP_T::STATUS: CAPOVF Position */
#define ECAP_STATUS_CAPOVF_Msk (0x1ul << ECAP_STATUS_CAPOVF_Pos) /*!< ECAP_T::STATUS: CAPOVF Mask */
#define ECAP_STATUS_CAP0_Pos (8) /*!< ECAP_T::STATUS: CAP0 Position */
#define ECAP_STATUS_CAP0_Msk (0x1ul << ECAP_STATUS_CAP0_Pos) /*!< ECAP_T::STATUS: CAP0 Mask */
#define ECAP_STATUS_CAP1_Pos (9) /*!< ECAP_T::STATUS: CAP1 Position */
#define ECAP_STATUS_CAP1_Msk (0x1ul << ECAP_STATUS_CAP1_Pos) /*!< ECAP_T::STATUS: CAP1 Mask */
#define ECAP_STATUS_CAP2_Pos (10) /*!< ECAP_T::STATUS: CAP2 Position */
#define ECAP_STATUS_CAP2_Msk (0x1ul << ECAP_STATUS_CAP2_Pos) /*!< ECAP_T::STATUS: CAP2 Mask */
/**@}*/ /* ECAP_CONST */
/**@}*/ /* end of ECAP register group */
/**@}*/ /* end of REGISTER group */
#if defined ( __CC_ARM )
#pragma no_anon_unions
#endif
#endif /* __ECAP_REG_H__ */

4978
bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/epwm_reg.h Normal file
View File

File diff suppressed because it is too large Load Diff

382
bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/gfx_reg.h Normal file
View File

@ -0,0 +1,382 @@
/**************************************************************************//**
* @file gfx_reg.h
* @brief GFX register definition header file
*
* SPDX-License-Identifier: Apache-2.0
* @copyright (C) 2021 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __GFX_REG_H__
#define __GFX_REG_H__
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
/**
@addtogroup REGISTER Control Register
@{
*/
/**
@addtogroup GFX 2D Graphic Engine (GFX)
Memory Mapped Structure for GFX Controller
@{ */
typedef struct
{
/**
* @var GFX_T::AQHiClockControl
* Offset: 0x00 Clock control register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |CLK3D_DIS |Disable 3D clock
* | | |Software core clock disable signal for core (clk1x) clock.
* | | |When set to 1, the clock is frozen.
* |[1] |CLK2D_DIS |Disable 2D clock
* | | |Software clock disable signal.
* | | |For this core both bits CLK3D_DIS and CLK2D_DIS should be controlled by software.
* | | |The AXI interface clock is the only block not stalled at that point.
* |[8:2] |FSCALE_VAL|Core clock frequency scale value
* | | |If this value is set to 1, the core clock will be 1/64 of clk1x, otherwise clock is fully frequency
* |[9] |FSCALE_CMD_LOAD|Core clock frequency scale value
* | | |When writing a 1 to this bit, it updates the frequency scale factor with the value FSCALE_VAL.
* | | |The bit must be set back to 0 after that.
* | | |If this bit is set and FSCALE_VAL=0 (an invalid combination), the HREADYOUT output signal will get stuck to 0.
* |[10] |DISABLE_RAM_CLOCK_GATING|Disables clock gating for rams.
* |[12] |SOFT_RESET|Soft resets the GFX.
* |[17] |IDLE2_D |2D pipe is idle.
* |[19] |ISOLATE_GPU|Isolate GPU bit
* | | |Used for power on/off sequence.
* @var GFX_T::AQHiIdle
* Offset: 0x04 Idle status register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |IDLE_FE |FE is idle.
* |[1] |IDLE_DE |DE is idle.
* |[2] |IDLE_PE |PE is idle.
* |[31] |AXI_LP |AXI is in low power mode.
* @var GFX_T::AQAxiConfig
* Offset: 0x08 AXI configuration register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[11:8] |AWCACHE |Set AWCACHE[3:0] value
* |[15:12] |ARCACHE |Set ARCACHE[3:0] value
* |[17:16] |AXDOMAIN_SHARED|Configure AxDOMAIN value for shareable request.
* |[19:18] |AXDOMAIN_NON_SHARED|Configure AxDOMAIN value for non-shareable request.
* |[23:20] |AXCACHE_OVERRIDE_SHARED|Configure AxCACHE value for shareable request.
* @var GFX_T::AQAxiStatus
* Offset: 0x0C AXI status register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[3:0] |WR_ERR_ID |Write error ID
* |[7:4] |RD_ERR_ID |Read error ID
* |[8] |DET_WR_ERR|1 = Detect write error
* |[9] |DET_RD_ERR|1 = Detect read error
* @var GFX_T::AQIntrAcknowledge
* Offset: 0x10 Interrupt acknowledge register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |INTR_VEC |Interrupt Vector
* | | |Each bit represents a corresponding event being triggered.
* | | |Reading from this register clears the outstanding interrupt.
* | | |For each interrupt event, 0=Clear, 1=Interrupt Active.
* | | |INTR_VEC[31] is AXI_BUS_ERROR, 0 = No Error.
* @var GFX_T::AQIntrEnbl
* Offset: 0x14 Interrupt enable register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |INTR_ENBL_VEC|Interrupt enable
* | | |Each bit enables a corresponding event.
* @var GFX_T::GCChipRev
* Offset: 0x24 Revision register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |REV |Revision
* @var GFX_T::GCChipDate
* Offset: 0x28 Release date register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |DATE |Date (YYYY/MM/DD)
* @var GFX_T::gcTotalCycles
* Offset: 0x78 Total cycles register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |CYCLES |Total cycles
* | | |This register is a free running counter.
* | | |It can be reset by writing 0 to it.
* @var GFX_T::gcregHIChipPatchRev
* Offset: 0x98 Patch revision level register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |PATCH_REV |Patch revision level for the chip.
* @var GFX_T::gcProductId
* Offset: 0xA8 Product ID register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[3:0] |GRADE_LEVEL|Grade Level
* | | |0 = None-no extra letter on the product name;.
* | | |2 = L-Lite.
* | | |3 = UL-Ultra Lite.
* |[23:4] |NUM |Product Number
* | | |520 for this core.
* |[27:24] |TYPE |Core Type
* | | |0 = GC (2D or 3D Graphics Cores).
* @var GFX_T::gcModulePowerControls
* Offset: 0x100 Control register for module level power
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |ENABLE_MODULE_CLOCK_GATING|Enables module level clock gating.
* |[1] |DISABLE_STALL_MODULE_CLOCK_GATING|Disables module level clock gating for stall condition.
* |[2] |DISABLE_STARVE_MODULE_CLOCK_GATING|Disables module level clock gating for starve/idle condition.
* @var GFX_T::gcregMMUControl
* Offset: 0x18C MMU Control register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |ENABLE |Enable the MMU
* | | |For security reasons, once the MMU is enabled it cannot be disabled anymore.
* | | |1 = enable.
* @var GFX_T::AQMemoryDebug
* Offset: 0x414 Memory debug register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |MAX_OUTSTANDING_READS|Limits the total number of outstanding read requests.
* @var GFX_T::AQRegisterTImingControl
* Offset: 0x42C SRAM timing control register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |FOR_RF1P |For 1 port RAM
* |[15:8] |FOR_RF2P |For 2 port RAM
* |[17:16] |FAST_RTC |RTC for fast RAMs
* |[19:18] |FAST_WTC |WTC for fast RAMs
* |[20] |POWER_DOW |Power down
* |[21] |DEEP_SLEEP|Deep sleep
* |[22] |LIGHT_SLEEP|Light sleep
* @var GFX_T::AQCmdBufferAddr
* Offset: 0x654 Command buffer base address register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |ADDRESS |Base address for the command buffer
* | | |The address must be 64-bit alignment and it is always physical.
* | | |To check the value of the current fetch address use AQFEDebugCurCmdAdr register.
* | | |Since this is a write only register is has no reset value.
* @var GFX_T::AQCmdBufferCtrl
* Offset: 0x658 Command buffer control register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |PREFETCH |Prefetch (write only)
* | | |Number of 64-bit words to fetch from the command buffer.
* |[16] |ENABLE |Enable
* | | |Enable the command parser.
* @var GFX_T::AQFEDebugCurCmdAdr
* Offset: 0x664 Command decoder address register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:4] |CUR_CMD_ADR|This is the command decoder address
* | | |The address is always physical so the MSB should always be 0.
* | | |Note that with the current MMU all 32 bits are valid.
* | | |It has no reset value.
*/
__IO uint32_t AQHiClockControl; /*!< [0x0000] Clock control register */
__I uint32_t AQHiIdle; /*!< [0x0004] Idle status register */
__IO uint32_t AQAxiConfig; /*!< [0x0008] AXI configuration register */
__I uint32_t AQAxiStatus; /*!< [0x000c] AXI status register */
__I uint32_t AQIntrAcknowledge; /*!< [0x0010] Interrupt acknowledge register */
__IO uint32_t AQIntrEnbl; /*!< [0x0014] Interrupt enable register */
__I uint32_t RESERVE0[3];
__I uint32_t GCChipRev; /*!< [0x0024] Revision register */
__I uint32_t GCChipDate; /*!< [0x0028] Release date register */
__I uint32_t RESERVE1[19];
__IO uint32_t gcTotalCycles; /*!< [0x0078] Total cycles register */
__I uint32_t RESERVE2[7];
__I uint32_t gcregHIChipPatchRev; /*!< [0x0098] Patch revision level register */
__I uint32_t RESERVE3[3];
__I uint32_t gcProductId; /*!< [0x00a8] Product ID register */
__I uint32_t RESERVE4[21];
__IO uint32_t gcModulePowerControls; /*!< [0x0100] Control register for module level power */
__I uint32_t RESERVE5[34];
__O uint32_t gcregMMUControl; /*!< [0x018c] MMU Control register */
__I uint32_t RESERVE6[161];
__IO uint32_t AQMemoryDebug; /*!< [0x0414] Memory debug register */
__I uint32_t RESERVE7[5];
__IO uint32_t AQRegisterTImingControl; /*!< [0x042c] SRAM timing control register */
__I uint32_t RESERVE8[137];
__O uint32_t AQCmdBufferAddr; /*!< [0x0654] Command buffer base address register */
__IO uint32_t AQCmdBufferCtrl; /*!< [0x0658] Command buffer control register */
__I uint32_t RESERVE9[2];
__I uint32_t AQFEDebugCurCmdAdr; /*!< [0x0664] Command decoder address register */
} GFX_T;
/**
@addtogroup GFX_CONST GFX Bit Field Definition
Constant Definitions for GFX Controller
@{ */
#define GFX_AQHiClockControl_CLK3D_DIS_Pos (0) /*!< GFX_T::AQHiClockControl: CLK3D_DIS Position*/
#define GFX_AQHiClockControl_CLK3D_DIS_Msk (0x1ul << GFX_AQHiClockControl_CLK3D_DIS_Pos) /*!< GFX_T::AQHiClockControl: CLK3D_DIS Mask*/
#define GFX_AQHiClockControl_CLK2D_DIS_Pos (1) /*!< GFX_T::AQHiClockControl: CLK2D_DIS Position*/
#define GFX_AQHiClockControl_CLK2D_DIS_Msk (0x1ul << GFX_AQHiClockControl_CLK2D_DIS_Pos) /*!< GFX_T::AQHiClockControl: CLK2D_DIS Mask*/
#define GFX_AQHiClockControl_FSCALE_VAL_Pos (2) /*!< GFX_T::AQHiClockControl: FSCALE_VAL Position*/
#define GFX_AQHiClockControl_FSCALE_VAL_Msk (0x7ful << GFX_AQHiClockControl_FSCALE_VAL_Pos) /*!< GFX_T::AQHiClockControl: FSCALE_VAL Mask*/
#define GFX_AQHiClockControl_FSCALE_CMD_LOAD_Pos (9) /*!< GFX_T::AQHiClockControl: FSCALE_CMD_LOAD Position*/
#define GFX_AQHiClockControl_FSCALE_CMD_LOAD_Msk (0x1ul << GFX_AQHiClockControl_FSCALE_CMD_LOAD_Pos) /*!< GFX_T::AQHiClockControl: FSCALE_CMD_LOAD Mask*/
#define GFX_AQHiClockControl_DISABLE_RAM_CLOCK_GATING_Pos (10) /*!< GFX_T::AQHiClockControl: DISABLE_RAM_CLOCK_GATING Position*/
#define GFX_AQHiClockControl_DISABLE_RAM_CLOCK_GATING_Msk (0x1ul << GFX_AQHiClockControl_DISABLE_RAM_CLOCK_GATING_Pos) /*!< GFX_T::AQHiClockControl: DISABLE_RAM_CLOCK_GATING Mask*/
#define GFX_AQHiClockControl_SOFT_RESET_Pos (12) /*!< GFX_T::AQHiClockControl: SOFT_RESET Position*/
#define GFX_AQHiClockControl_SOFT_RESET_Msk (0x1ul << GFX_AQHiClockControl_SOFT_RESET_Pos) /*!< GFX_T::AQHiClockControl: SOFT_RESET Mask*/
#define GFX_AQHiClockControl_IDLE2_D_Pos (17) /*!< GFX_T::AQHiClockControl: IDLE2_D Position*/
#define GFX_AQHiClockControl_IDLE2_D_Msk (0x1ul << GFX_AQHiClockControl_IDLE2_D_Pos) /*!< GFX_T::AQHiClockControl: IDLE2_D Mask */
#define GFX_AQHiClockControl_ISOLATE_GPU_Pos (19) /*!< GFX_T::AQHiClockControl: ISOLATE_GPU Position*/
#define GFX_AQHiClockControl_ISOLATE_GPU_Msk (0x1ul << GFX_AQHiClockControl_ISOLATE_GPU_Pos) /*!< GFX_T::AQHiClockControl: ISOLATE_GPU Mask*/
#define GFX_AQHiIdle_IDLE_FE_Pos (0) /*!< GFX_T::AQHiIdle: IDLE_FE Position */
#define GFX_AQHiIdle_IDLE_FE_Msk (0x1ul << GFX_AQHiIdle_IDLE_FE_Pos) /*!< GFX_T::AQHiIdle: IDLE_FE Mask */
#define GFX_AQHiIdle_IDLE_DE_Pos (1) /*!< GFX_T::AQHiIdle: IDLE_DE Position */
#define GFX_AQHiIdle_IDLE_DE_Msk (0x1ul << GFX_AQHiIdle_IDLE_DE_Pos) /*!< GFX_T::AQHiIdle: IDLE_DE Mask */
#define GFX_AQHiIdle_IDLE_PE_Pos (2) /*!< GFX_T::AQHiIdle: IDLE_PE Position */
#define GFX_AQHiIdle_IDLE_PE_Msk (0x1ul << GFX_AQHiIdle_IDLE_PE_Pos) /*!< GFX_T::AQHiIdle: IDLE_PE Mask */
#define GFX_AQHiIdle_AXI_LP_Pos (31) /*!< GFX_T::AQHiIdle: AXI_LP Position */
#define GFX_AQHiIdle_AXI_LP_Msk (0x1ul << GFX_AQHiIdle_AXI_LP_Pos) /*!< GFX_T::AQHiIdle: AXI_LP Mask */
#define GFX_AQAxiConfig_AWCACHE_Pos (8) /*!< GFX_T::AQAxiConfig: AWCACHE Position */
#define GFX_AQAxiConfig_AWCACHE_Msk (0xful << GFX_AQAxiConfig_AWCACHE_Pos) /*!< GFX_T::AQAxiConfig: AWCACHE Mask */
#define GFX_AQAxiConfig_ARCACHE_Pos (12) /*!< GFX_T::AQAxiConfig: ARCACHE Position */
#define GFX_AQAxiConfig_ARCACHE_Msk (0xful << GFX_AQAxiConfig_ARCACHE_Pos) /*!< GFX_T::AQAxiConfig: ARCACHE Mask */
#define GFX_AQAxiConfig_AXDOMAIN_SHARED_Pos (16) /*!< GFX_T::AQAxiConfig: AXDOMAIN_SHARED Position*/
#define GFX_AQAxiConfig_AXDOMAIN_SHARED_Msk (0x3ul << GFX_AQAxiConfig_AXDOMAIN_SHARED_Pos) /*!< GFX_T::AQAxiConfig: AXDOMAIN_SHARED Mask*/
#define GFX_AQAxiConfig_AXDOMAIN_NON_SHARED_Pos (18) /*!< GFX_T::AQAxiConfig: AXDOMAIN_NON_SHARED Position*/
#define GFX_AQAxiConfig_AXDOMAIN_NON_SHARED_Msk (0x3ul << GFX_AQAxiConfig_AXDOMAIN_NON_SHARED_Pos) /*!< GFX_T::AQAxiConfig: AXDOMAIN_NON_SHARED Mask*/
#define GFX_AQAxiConfig_AXCACHE_OVERRIDE_SHARED_Pos (20) /*!< GFX_T::AQAxiConfig: AXCACHE_OVERRIDE_SHARED Position*/
#define GFX_AQAxiConfig_AXCACHE_OVERRIDE_SHARED_Msk (0xful << GFX_AQAxiConfig_AXCACHE_OVERRIDE_SHARED_Pos) /*!< GFX_T::AQAxiConfig: AXCACHE_OVERRIDE_SHARED Mask*/
#define GFX_AQAxiStatus_WR_ERR_ID_Pos (0) /*!< GFX_T::AQAxiStatus: WR_ERR_ID Position */
#define GFX_AQAxiStatus_WR_ERR_ID_Msk (0xful << GFX_AQAxiStatus_WR_ERR_ID_Pos) /*!< GFX_T::AQAxiStatus: WR_ERR_ID Mask */
#define GFX_AQAxiStatus_RD_ERR_ID_Pos (4) /*!< GFX_T::AQAxiStatus: RD_ERR_ID Position */
#define GFX_AQAxiStatus_RD_ERR_ID_Msk (0xful << GFX_AQAxiStatus_RD_ERR_ID_Pos) /*!< GFX_T::AQAxiStatus: RD_ERR_ID Mask */
#define GFX_AQAxiStatus_DET_WR_ERR_Pos (8) /*!< GFX_T::AQAxiStatus: DET_WR_ERR Position*/
#define GFX_AQAxiStatus_DET_WR_ERR_Msk (0x1ul << GFX_AQAxiStatus_DET_WR_ERR_Pos) /*!< GFX_T::AQAxiStatus: DET_WR_ERR Mask */
#define GFX_AQAxiStatus_DET_RD_ERR_Pos (9) /*!< GFX_T::AQAxiStatus: DET_RD_ERR Position*/
#define GFX_AQAxiStatus_DET_RD_ERR_Msk (0x1ul << GFX_AQAxiStatus_DET_RD_ERR_Pos) /*!< GFX_T::AQAxiStatus: DET_RD_ERR Mask */
#define GFX_AQIntrAcknowledge_INTR_VEC_Pos (0) /*!< GFX_T::AQIntrAcknowledge: INTR_VEC Position*/
#define GFX_AQIntrAcknowledge_INTR_VEC_Msk (0xfffffffful << GFX_AQIntrAcknowledge_INTR_VEC_Pos) /*!< GFX_T::AQIntrAcknowledge: INTR_VEC Mask*/
#define GFX_AQIntrEnbl_INTR_ENBL_VEC_Pos (0) /*!< GFX_T::AQIntrEnbl: INTR_ENBL_VEC Position*/
#define GFX_AQIntrEnbl_INTR_ENBL_VEC_Msk (0xfffffffful << GFX_AQIntrEnbl_INTR_ENBL_VEC_Pos) /*!< GFX_T::AQIntrEnbl: INTR_ENBL_VEC Mask */
#define GFX_GCChipRev_REV_Pos (0) /*!< GFX_T::GCChipRev: REV Position */
#define GFX_GCChipRev_REV_Msk (0xfffffffful << GFX_GCChipRev_REV_Pos) /*!< GFX_T::GCChipRev: REV Mask */
#define GFX_GCChipDate_DATE_Pos (0) /*!< GFX_T::GCChipDate: DATE Position */
#define GFX_GCChipDate_DATE_Msk (0xfffffffful << GFX_GCChipDate_DATE_Pos) /*!< GFX_T::GCChipDate: DATE Mask */
#define GFX_gcTotalCycles_CYCLES_Pos (0) /*!< GFX_T::gcTotalCycles: CYCLES Position */
#define GFX_gcTotalCycles_CYCLES_Msk (0xfffffffful << GFX_gcTotalCycles_CYCLES_Pos) /*!< GFX_T::gcTotalCycles: CYCLES Mask */
#define GFX_gcregHIChipPatchRev_PATCH_REV_Pos (0) /*!< GFX_T::gcregHIChipPatchRev: PATCH_REV Position*/
#define GFX_gcregHIChipPatchRev_PATCH_REV_Msk (0xfful << GFX_gcregHIChipPatchRev_PATCH_REV_Pos) /*!< GFX_T::gcregHIChipPatchRev: PATCH_REV Mask*/
#define GFX_gcProductId_GRADE_LEVEL_Pos (0) /*!< GFX_T::gcProductId: GRADE_LEVEL Position*/
#define GFX_gcProductId_GRADE_LEVEL_Msk (0xful << GFX_gcProductId_GRADE_LEVEL_Pos) /*!< GFX_T::gcProductId: GRADE_LEVEL Mask */
#define GFX_gcProductId_NUM_Pos (4) /*!< GFX_T::gcProductId: NUM Position */
#define GFX_gcProductId_NUM_Msk (0xffffful << GFX_gcProductId_NUM_Pos) /*!< GFX_T::gcProductId: NUM Mask */
#define GFX_gcProductId_TYPE_Pos (24) /*!< GFX_T::gcProductId: TYPE Position */
#define GFX_gcProductId_TYPE_Msk (0xful << GFX_gcProductId_TYPE_Pos) /*!< GFX_T::gcProductId: TYPE Mask */
#define GFX_gcModulePowerControls_ENABLE_MODULE_CLOCK_GATING_Pos (0) /*!< GFX_T::gcModulePowerControls: ENABLE_MODULE_CLOCK_GATING Position*/
#define GFX_gcModulePowerControls_ENABLE_MODULE_CLOCK_GATING_Msk (0x1ul << GFX_gcModulePowerControls_ENABLE_MODULE_CLOCK_GATING_Pos) /*!< GFX_T::gcModulePowerControls: ENABLE_MODULE_CLOCK_GATING Mask*/
#define GFX_gcModulePowerControls_DISABLE_STALL_MODULE_CLOCK_GATING_Pos (1) /*!< GFX_T::gcModulePowerControls: DISABLE_STALL_MODULE_CLOCK_GATING Position*/
#define GFX_gcModulePowerControls_DISABLE_STALL_MODULE_CLOCK_GATING_Msk (0x1ul << GFX_gcModulePowerControls_DISABLE_STALL_MODULE_CLOCK_GATING_Pos) /*!< GFX_T::gcModulePowerControls: DISABLE_STALL_MODULE_CLOCK_GATING Mask*/
#define GFX_gcModulePowerControls_DISABLE_STARVE_MODULE_CLOCK_GATING_Pos (2) /*!< GFX_T::gcModulePowerControls: DISABLE_STARVE_MODULE_CLOCK_GATING Position*/
#define GFX_gcModulePowerControls_DISABLE_STARVE_MODULE_CLOCK_GATING_Msk (0x1ul << GFX_gcModulePowerControls_DISABLE_STARVE_MODULE_CLOCK_GATING_Pos) /*!< GFX_T::gcModulePowerControls: DISABLE_STARVE_MODULE_CLOCK_GATING Mask*/
#define GFX_gcregMMUControl_ENABLE_Pos (0) /*!< GFX_T::gcregMMUControl: ENABLE Position*/
#define GFX_gcregMMUControl_ENABLE_Msk (0x1ul << GFX_gcregMMUControl_ENABLE_Pos) /*!< GFX_T::gcregMMUControl: ENABLE Mask */
#define GFX_AQMemoryDebug_MAX_OUTSTANDING_READS_Pos (0) /*!< GFX_T::AQMemoryDebug: MAX_OUTSTANDING_READS Position*/
#define GFX_AQMemoryDebug_MAX_OUTSTANDING_READS_Msk (0xfful << GFX_AQMemoryDebug_MAX_OUTSTANDING_READS_Pos) /*!< GFX_T::AQMemoryDebug: MAX_OUTSTANDING_READS Mask*/
#define GFX_AQRegisterTImingControl_FOR_RF1P_Pos (0) /*!< GFX_T::AQRegisterTImingControl: FOR_RF1P Position*/
#define GFX_AQRegisterTImingControl_FOR_RF1P_Msk (0xfful << GFX_AQRegisterTImingControl_FOR_RF1P_Pos) /*!< GFX_T::AQRegisterTImingControl: FOR_RF1P Mask*/
#define GFX_AQRegisterTImingControl_FOR_RF2P_Pos (8) /*!< GFX_T::AQRegisterTImingControl: FOR_RF2P Position*/
#define GFX_AQRegisterTImingControl_FOR_RF2P_Msk (0xfful << GFX_AQRegisterTImingControl_FOR_RF2P_Pos) /*!< GFX_T::AQRegisterTImingControl: FOR_RF2P Mask*/
#define GFX_AQRegisterTImingControl_FAST_RTC_Pos (16) /*!< GFX_T::AQRegisterTImingControl: FAST_RTC Position*/
#define GFX_AQRegisterTImingControl_FAST_RTC_Msk (0x3ul << GFX_AQRegisterTImingControl_FAST_RTC_Pos) /*!< GFX_T::AQRegisterTImingControl: FAST_RTC Mask*/
#define GFX_AQRegisterTImingControl_FAST_WTC_Pos (18) /*!< GFX_T::AQRegisterTImingControl: FAST_WTC Position*/
#define GFX_AQRegisterTImingControl_FAST_WTC_Msk (0x3ul << GFX_AQRegisterTImingControl_FAST_WTC_Pos) /*!< GFX_T::AQRegisterTImingControl: FAST_WTC Mask*/
#define GFX_AQRegisterTImingControl_POWER_DOW_Pos (20) /*!< GFX_T::AQRegisterTImingControl: POWER_DOW Position*/
#define GFX_AQRegisterTImingControl_POWER_DOW_Msk (0x1ul << GFX_AQRegisterTImingControl_POWER_DOW_Pos) /*!< GFX_T::AQRegisterTImingControl: POWER_DOW Mask*/
#define GFX_AQRegisterTImingControl_DEEP_SLEEP_Pos (21) /*!< GFX_T::AQRegisterTImingControl: DEEP_SLEEP Position*/
#define GFX_AQRegisterTImingControl_DEEP_SLEEP_Msk (0x1ul << GFX_AQRegisterTImingControl_DEEP_SLEEP_Pos) /*!< GFX_T::AQRegisterTImingControl: DEEP_SLEEP Mask*/
#define GFX_AQRegisterTImingControl_LIGHT_SLEEP_Pos (22) /*!< GFX_T::AQRegisterTImingControl: LIGHT_SLEEP Position*/
#define GFX_AQRegisterTImingControl_LIGHT_SLEEP_Msk (0x1ul << GFX_AQRegisterTImingControl_LIGHT_SLEEP_Pos) /*!< GFX_T::AQRegisterTImingControl: LIGHT_SLEEP Mask*/
#define GFX_AQCmdBufferAddr_ADDRESS_Pos (0) /*!< GFX_T::AQCmdBufferAddr: ADDRESS Position*/
#define GFX_AQCmdBufferAddr_ADDRESS_Msk (0xfffffffful << GFX_AQCmdBufferAddr_ADDRESS_Pos) /*!< GFX_T::AQCmdBufferAddr: ADDRESS Mask */
#define GFX_AQCmdBufferCtrl_PREFETCH_Pos (0) /*!< GFX_T::AQCmdBufferCtrl: PREFETCH Position*/
#define GFX_AQCmdBufferCtrl_PREFETCH_Msk (0xfffful << GFX_AQCmdBufferCtrl_PREFETCH_Pos) /*!< GFX_T::AQCmdBufferCtrl: PREFETCH Mask */
#define GFX_AQCmdBufferCtrl_ENABLE_Pos (16) /*!< GFX_T::AQCmdBufferCtrl: ENABLE Position*/
#define GFX_AQCmdBufferCtrl_ENABLE_Msk (0x1ul << GFX_AQCmdBufferCtrl_ENABLE_Pos) /*!< GFX_T::AQCmdBufferCtrl: ENABLE Mask */
#define GFX_AQFEDebugCurCmdAdr_CUR_CMD_ADR_Pos (4) /*!< GFX_T::AQFEDebugCurCmdAdr: CUR_CMD_ADR Position*/
#define GFX_AQFEDebugCurCmdAdr_CUR_CMD_ADR_Msk (0xffffffful << GFX_AQFEDebugCurCmdAdr_CUR_CMD_ADR_Pos) /*!< GFX_T::AQFEDebugCurCmdAdr: CUR_CMD_ADR Mask*/
/**@}*/ /* GFX_CONST */
/**@}*/ /* end of GFX register group */
/**@}*/ /* end of REGISTER group */
#if defined ( __CC_ARM )
#pragma no_anon_unions
#endif
#endif /* __GFX_REG_H__ */

2606
bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/gmac_reg.h Normal file
View File

File diff suppressed because it is too large Load Diff

1221
bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/gpio_reg.h Normal file
View File

File diff suppressed because it is too large Load Diff

3108
bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/hsusbd_reg.h Normal file
View File

File diff suppressed because it is too large Load Diff

597
bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/hsusbh_reg.h Normal file
View File

@ -0,0 +1,597 @@
/**************************************************************************//**
* @file hsusbh_reg.h
* @brief HSUSBH register definition header file
*
* SPDX-License-Identifier: Apache-2.0
* @copyright (C) 2021 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __HSUSBH_REG_H__
#define __HSUSBH_REG_H__
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
/**
@addtogroup REGISTER Control Register
@{
*/
/**
@addtogroup HSUSBH High Speed USB Host Controller
Memory Mapped Structure for HSUSBH Controller
@{ */
typedef struct
{
/**
* @var HSUSBH_T::EHCVNR
* Offset: 0x00 EHCI Version Number Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |CRLEN |Capability Registers Length
* | | |This register is used as an offset to add to register base to find the beginning of the Operational Register Space defined in EHCI specification.
* |[31:16] |VERSION |Host Controller Interface Version Number
* | | |This is a two-byte register containing a BCD encoding of the EHCI revision number supported by this host controller
* | | |The most significant byte of this register represents a major revision and the least significant byte is the minor revision.
* @var HSUSBH_T::EHCSPR
* Offset: 0x04 EHCI Structural Parameters Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[3:0] |N_PORTS |Number of Physical Downstream Ports
* | | |This field specifies the number of physical downstream ports implemented on this host controller
* | | |The value of this field determines how many port registers are addressable in the Operational Register Space (see Table 2-8 of EHCI spec.)
* | | |Valid values are in the range of 1H to FH.
* | | |A zero in this field is undefined.
* |[4] |PPC |Port Power Control
* | | |This field indicates whether the host controller implementation includes port power control
* | | |A one in this bit indicates the ports have port power switches
* | | |A zero in this bit indicates the port do not have port power stitches
* | | |The value of this field affects the functionality of the Port Power field in each port status and control register.
* |[11:8] |N_PCC |Number of Ports Per Companion Controller
* | | |This field indicates the number of ports supported per companion host controller
* | | |It is used to indicate the port routing configuration to system software.
* | | |For example, if N_PORTS has a value of 6 and N_CC has a value of 2 then N_PCC could have a value of 3
* | | |The convention is that the first N_PCC ports are assumed to be routed to companion controller 1, the next N_PCC ports to companion controller 2, etc
* | | |In the previous example, the N_PCC could have been 4, where the first 4 are routed to companion controller 1 and the last two are routed to companion controller 2.
* | | |The number in this field must be consistent with N_PORTS and N_CC.
* |[15:12] |N_CC |Number of Companion Controller
* | | |This field indicates the number of companion controllers associated with this USB 2.0 host controller.
* | | |A zero in this field indicates there are no companion host controllers
* | | |Port-ownership hand-off is not supported
* | | |Only high-speed devices are supported on the host controller root ports.
* | | |A value larger than zero in this field indicates there are companion USB 1.1 host controller(s)
* | | |Port-ownership hand-offs are supported
* | | |High, Full- and Low-speed devices are supported on the host controller root ports.
* @var HSUSBH_T::EHCCPR
* Offset: 0x08 EHCI Capability Parameters Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |AC64 |64-bit Addressing Capability
* | | |0 = Data structure using 32-bit address memory pointers.
* | | |1 = Data structure using 64-bit address memory pointers.
* |[1] |PFLF |Programmable Frame List Flag
* | | |0 = System software must use a frame list length of 1024 elements with this EHCI host controller.
* | | |1 = System software can specify and use a smaller frame list and configure the host controller via the USB Command Register.
* |[2] |ASPC |Asynchronous Schedule Park Capability
* | | |0 = This EHCI host controller doesn't support park feature of high-speed queue heads in the Asynchronous Schedule.
* | | |1 = This EHCI host controller support park feature of high-speed queue heads in the Asynchronous Schedule.
* |[7:4] |IST |Isochronous Scheduling Threshold
* | | |This field indicates, relative to the current position of the executing host controller, where software can reliably update the isochronous schedule.
* | | |When bit [7] is zero, the value of the least significant 3 bits indicates the number of micro-frames a host controller can hold a set of isochronous data structures (one or more) before flushing the state.
* | | |When bit [7] is a one, then host software assumes the host controller may cache an isochronous data structure for an entire frame.
* |[15:8] |EECP |EHCI Extended Capabilities Pointer
* | | |0 = No extended capabilities are implemented.
* | | |1 = Extended capabilities are implemented.
* @var HSUSBH_T::UCMDR
* Offset: 0x10 USB Command Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |RUN |Run/Stop (read/write)
* | | |When set to a 1, the Host Controller proceeds with execution of the schedule
* | | |The Host Controller continues execution as long as this bit is set to a 1
* | | |When this bit is set to 0, the Host Controller completes the current and any actively pipelined transactions on the USB and then halts
* | | |The Host Controller must halt within 16 micro-frames after software clears the Run bit
* | | |The HC Halted bit in the status register indicates when the Host Controller has finished its pending pipelined transactions and has entered the stopped state
* | | |Software must not write a one to this field unless the host controller is in the Halted state (i.e
* | | |HCHalted in the USBSTS register is a one)
* | | |Doing so will yield undefined results.
* | | |0 = Stop.
* | | |1 = Run.
* |[1] |HCRST |Host Controller Reset (read/write)
* | | |This control bit is used by software to reset the host controller
* | | |The effects of this on Root Hub registers are similar to a Chip Hardware Reset.
* | | |When software writes a one to this bit, the Host Controller resets its internal pipelines, timers, counters, state machines, etc
* | | |to their initial value
* | | |Any transaction currently in progress on USB is immediately terminated
* | | |A USB reset is not driven on downstream ports.
* | | |All operational registers, including port registers and port state machines are set to their initial values
* | | |Port ownership reverts to the companion host controller(s), with the side effects
* | | |Software must reinitialize the host controller in order to return the host controller to an operational state.
* | | |This bit is set to zero by the Host Controller when the reset process is complete
* | | |Software cannot terminate the reset process early by writing a zero to this register.
* | | |Software should not set this bit to a one when the HCHalted bit in the USBSTS register is a zero
* | | |Attempting to reset an actively running host controller will result in undefined behavior.
* |[3:2] |FLSZ |Frame List Size (read only)
* | | |This field is R/W only if Programmable Frame List Flag in the HCCPARAMS registers is set to a one
* | | |This field specifies the size of the frame list
* | | |The size the frame list controls which bits in the Frame Index Register should be used for the Frame List Current index
* | | |Values mean:
* | | |00 = 1024 elements (4096 bytes) Default value.
* | | |01 = 512 elements (2048 bytes).
* | | |10 = 256 elements (1024 bytes) - for resource-constrained environment.
* | | |11 = Reserved.
* |[4] |PSEN |Periodic Schedule Enable (read/write)
* | | |This bit controls whether the host controller skips processing the Periodic Schedule. Values mean:
* | | |0 = Do not process the Periodic Schedule.
* | | |1 = Use the PERIODICLISTBASE register to access the Periodic Schedule.
* |[5] |ASEN |Asynchronous Schedule Enable (read/write)
* | | |This bit controls whether the host controller skips processing the Asynchronous Schedule. Values mean:
* | | |0 = Do not process the Asynchronous Schedule.
* | | |1 = Use the ASYNCLISTADDR register to access the Asynchronous Schedule.
* |[6] |IAAD |Interrupt on Asynchronous Advance Doorbell (read/write)
* | | |This bit is used as a doorbell by software to tell the host controller to issue an interrupt the next time it advances asynchronous schedule
* | | |Software must write a 1 to this bit to ring the doorbell.
* | | |When the host controller has evicted all appropriate cached schedule state, it sets the Interrupt on Asynchronous Advance status bit in the USBSTS register
* | | |If the Interrupt on Asynchronous Advance Enable bit in the USBINTR register is a one then the host controller will assert an interrupt at the next interrupt threshold.
* | | |The host controller sets this bit to a zero after it has set the Interrupt on Asynchronous Advance status bit in the USBSTS register to a one.
* | | |Software should not write a one to this bit when the asynchronous schedule is disabled
* | | |Doing so will yield undefined results.
* |[23:16] |ITC |Interrupt Threshold Control (read/write)
* | | |This field is used by system software to select the maximum rate at which the host controller will issue interrupts
* | | |The only valid values are defined below
* | | |If software writes an invalid value to this register, the results are undefined
* | | |Value Maximum Interrupt Interval
* | | |0x00 = Reserved.
* | | |0x01 = 1 micro-frame.
* | | |0x02 = 2 micro-frames.
* | | |0x04 = 4 micro-frames.
* | | |0x08 = 8 micro-frames (default, equates to 1 ms).
* | | |0x10 = 16 micro-frames (2 ms).
* | | |0x20 = 32 micro-frames (4 ms).
* | | |0x40 = 64 micro-frames (8 ms).
* | | |Any other value in this register yields undefined results.
* | | |Software modifications to this bit while HCHalted bit is equal to zero results in undefined behavior.
* @var HSUSBH_T::USTSR
* Offset: 0x14 USB Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |USBINT |USB Interrupt (write 1 to clear)
* | | |The Host Controller sets this bit to 1 on the completion of a USB transaction, which results in the retirement of a Transfer Descriptor that had its IOC bit set.
* | | |The Host Controller also sets this bit to 1 when a short packet is detected (actual number of bytes received was less than the expected number of bytes).
* |[1] |UERRINT |USB Error Interrupt (write 1 to clear)
* | | |The Host Controller sets this bit to 1 when completion of a USB transaction results in an error condition (e.g., error counter underflow)
* | | |If the TD on which the error interrupt occurred also had its IOC bit set, both this bit and USBINT bit are set.
* |[2] |PCD |Port Change Detect (write 1 to clear)
* | | |The Host Controller sets this bit to a one when any port for which the Port Owner bit is set to zero has a change bit transition from a zero to a one or a Force Port Resume bit transition from a zero to a one as a result of a J-K transition detected on a suspended port
* | | |This bit will also be set as a result of the Connect Status Change being set to a one after system software has relinquished ownership of a connected port by writing a one to a port's Port Owner bit.
* | | |This bit is allowed to be maintained in the Auxiliary power well
* | | |Alternatively, it is also acceptable that on a D3 to D0 transition of the EHCI HC device, this bit is loaded with the OR of all of the PORTSC change bits (including: Force port resume, overcurrent change, enable/disable change and connect status change).
* |[3] |FLR |Frame List Rollover (write 1 to clear)
* | | |The Host Controller sets this bit to a one when the Frame List Index rolls over from its maximum value to zero
* | | |The exact value at which the rollover occurs depends on the frame list size
* | | |For example, if the frame list size (as programmed in the Frame List Size field of the USBCMD register) is 1024, the Frame Index Register rolls over every time FRINDEX[13] toggles
* | | |Similarly, if the size is 512, the Host Controller sets this bit to a one every time FRINDEX[12] toggles.
* |[4] |HSERR |Host System Error (write 1 to clear)
* | | |The Host Controller sets this bit to 1 when a serious error occurs during a host system access involving the Host Controller module.
* |[5] |IAA |Interrupt on Asynchronous Advance (write 1 to clear)
* | | |System software can force the host controller to issue an interrupt the next time the host controller advances the asynchronous schedule by writing a one to the Interrupt on Asynchronous Advance Doorbell bit in the USBCMD register
* | | |This status bit indicates the assertion of that interrupt source.
* |[12] |HCHalted |HCHalted (Read Only)
* | | |This bit is a zero whenever the Run/Stop bit is a one
* | | |The Host Controller sets this bit to one after it has stopped executing as a result of the Run/Stop bit being set to 0, either by software or by the Host Controller hardware (e.g
* | | |internal error).
* |[13] |RECLA |Reclamation (Read Only)
* | | |This is a read-only status bit, which is used to detect an empty asynchronous schedule.
* |[14] |PSS |Periodic Schedule Status (Read Only)
* | | |The bit reports the current real status of the Periodic Schedule
* | | |If this bit is a zero then the status of the Periodic Schedule is disabled
* | | |If this bit is a one then the status of the Periodic Schedule is enabled
* | | |The Host Controller is not required to immediately disable or enable the Periodic Schedule when software transitions the Periodic Schedule Enable bit in the USBCMD register
* | | |When this bit and the Periodic Schedule Enable bit are the same value, the Periodic Schedule is either enabled (1) or disabled (0).
* |[15] |ASS |Asynchronous Schedule Status (Read Only)
* | | |The bit reports the current real status of the Asynchronous Schedule
* | | |If this bit is a zero then the status of them Asynchronous Schedule is disabled
* | | |If this bit is a one then the status of the Asynchronous Schedule is enabled
* | | |The Host Controller is not required to immediately disable or enable the Asynchronous Schedule when software transitions the Asynchronous Schedule Enable bit in the USBCMD register
* | | |When this bit and the Asynchronous Schedule Enable bit are the same value, the Asynchronous Schedule is either enabled (1) or disabled (0).
* @var HSUSBH_T::UIENR
* Offset: 0x18 USB Interrupt Enable Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |USBIEN |USB Interrupt Enable or Disable Bit
* | | |When this bit is a one, and the USBINT bit in the USBSTS register is a one, the host controller will issue an interrupt at the next interrupt threshold
* | | |The interrupt is acknowledged by software clearing the USBINT bit.
* | | |0 = USB interrupt Disabled.
* | | |1 = USB interrupt Enabled.
* |[1] |UERRIEN |USB Error Interrupt Enable or Disable Bit
* | | |When this bit is a one, and the USBERRINT bit in the USBSTS register is a one, the host controller will issue an interrupt at the next interrupt threshold
* | | |The interrupt is acknowledged by software clearing the USBERRINT bit.
* | | |0 = USB Error interrupt Disabled.
* | | |1 = USB Error interrupt Enabled.
* |[2] |PCIEN |Port Change Interrupt Enable or Disable Bit
* | | |When this bit is a one, and the Port Change Detect bit in the USBSTS register is a one, the host controller will issue an interrupt
* | | |The interrupt is acknowledged by software clearing the Port Change Detect bit.
* | | |0 = Port Change interrupt Disabled.
* | | |1 = Port Change interrupt Enabled.
* |[3] |FLREN |Frame List Rollover Enable or Disable Bit
* | | |When this bit is a one, and the Frame List Rollover bit in the USBSTS register is a one, the host controller will issue an interrupt
* | | |The interrupt is acknowledged by software clearing the Frame List Rollover bit.
* | | |0 = Frame List Rollover interrupt Disabled.
* | | |1 = Frame List Rollover interrupt Enabled.
* |[4] |HSERREN |Host System Error Enable or Disable Bit
* | | |When this bit is a one, and the Host System Error Status bit in the USBSTS register is a one, the host controller will issue an interrupt
* | | |The interrupt is acknowledged by software clearing the Host System Error bit.
* | | |0 = Host System Error interrupt Disabled.
* | | |1 = Host System Error interrupt Enabled.
* |[5] |IAAEN |Interrupt on Asynchronous Advance Enable or Disable Bit
* | | |When this bit is a one, and the Interrupt on Asynchronous Advance bit in the USBSTS register is a one, the host controller will issue an interrupt at the next interrupt threshold
* | | |The interrupt is acknowledged by software clearing the Interrupt on Asynchronous Advance bit.
* | | |0 = Interrupt on Asynchronous Advance Disabled.
* | | |1 = Interrupt on Asynchronous Advance Enabled.
* @var HSUSBH_T::UFINDR
* Offset: 0x1C USB Frame Index Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[13:0] |FI |Frame Index
* | | |The value in this register increment at the end of each time frame (e.g
* | | |micro-frame)
* | | |Bits [N:3] are used for the Frame List current index
* | | |This means that each location of the frame list is accessed 8 times (frames or micro-frames) before moving to the next index
* | | |The following illustrates values of N based on the value of the Frame List Size field in the USBCMD register.
* | | |FLSZ (UCMDR[3:2] Number Elements N
* | | |0x0 1024 12
* | | |0x1 512 11
* | | |0x2 256 10
* | | |0x3 Reserved
* @var HSUSBH_T::UPFLBAR
* Offset: 0x24 USB Periodic Frame List Base Address Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:12] |BADDR |Base Address
* | | |These bits correspond to memory address signals [31:12], respectively.
* @var HSUSBH_T::UCALAR
* Offset: 0x28 USB Current Asynchronous List Address Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:5] |LPL |Link Pointer Low
* | | |These bits correspond to memory address signals [31:5], respectively
* | | |This field may only reference a Queue Head (QH).
* @var HSUSBH_T::UCFGR
* Offset: 0x50 USB Configure Flag Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |CF |Configure Flag
* | | |Host software sets this bit as the last action in its process of configuring the Host Controller
* | | |This bit controls the default port-routing control logic
* | | |Bit values and side-effects are listed below.
* | | |0 = Port routing control logic default-routes each port to an implementation dependent classic host controller.
* | | |1 = Port routing control logic default-routes all ports to this host controller.
* @var HSUSBH_T::UPSCR
* Offset: 0x54 USB Port Status and Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |CCS |Current Connect Status (Read Only)
* | | |This value reflects the current state of the port, and may not correspond directly to the event that caused the Connect Status Change bit (Bit 1) to be set.
* | | |This field is zero if Port Power is zero.
* | | |0 = No device is present.
* | | |1 = Device is present on port.
* |[1] |CSC |Connect Status Change (read/write)
* | | |Indicates a change has occurred in the port's Current Connect Status
* | | |The host controller sets this bit for all changes to the port device connect status, even if system software has not cleared an existing connect status change
* | | |For example, the insertion status changes twice before system software has cleared the changed condition, hub hardware will be "setting" an already-set bit (i.e., the bit will remain set).Software sets this bit to 0 by writing a 1 to it.
* | | |This field is zero if Port Power is zero.
* | | |0 = No change.
* | | |1 = Change in Current Connect Status.
* |[2] |PE |Port Enabled/Disabled (read/write)
* | | |Ports can only be enabled by the host controller as a part of the reset and enable
* | | |Software cannot enable a port by writing a one to this field
* | | |The host controller will only set this bit to a one when the reset sequence determines that the attached device is a high-speed device.
* | | |Ports can be disabled by either a fault condition (disconnect event or other fault condition) or by host software
* | | |Note that the bit status does not change until the port state actually changes
* | | |There may be a delay in disabling or enabling a port due to other host controller and bus events.
* | | |When the port is disabled, downstream propagation of data is blocked on this port, except for reset.
* | | |This field is zero if Port Power is zero.
* | | |0 = Port Disabled.
* | | |1 = Port Enabled.
* |[3] |PEC |Port Enable/Disable Change (write 1 to clear)
* | | |For the root hub, this bit gets set to a one only when a port is disabled due to the appropriate conditions existing at the EOF2 point (See Chapter 11 of the USB Specification for the definition of a Port Error)
* | | |Software clears this bit by writing a 1 to it.
* | | |This field is zero if Port Power is zero.
* | | |0 = No change.
* | | |1 = Port enabled/disabled status has changed.
* |[4] |OCA |Overcurrent Active (Read Only)
* | | |This bit will automatically transition from a one to a zero when the overcurrent condition is removed.
* | | |0 = This port does not have an overcurrent condition.
* | | |1 = This port currently has an overcurrent condition.
* |[5] |OCC |Overcurrent Change (write 1 to clear)
* | | |1 = This bit gets set to a one when there is a change to Overcurrent Active
* | | |Software clears this bit by writing a one to this bit position.
* | | |0 = Default.
* |[6] |FPR |Force Port Resume (read/write)
* | | |This functionality defined for manipulating this bit depends on the value of the Suspend bit
* | | |For example, if the port is not suspended (Suspend and Enabled bits are a one) and software transitions this bit to a one, then the effects on the bus are undefined.
* | | |Software sets this bit to a 1 to drive resume signaling
* | | |The Host Controller sets this bit to a 1 if a J-to-K transition is detected while the port is in the Suspend state
* | | |When this bit transitions to a one because a J-to-K transition is detected, the Port Change Detect bit in the USBSTS register is also set to a one
* | | |If software sets this bit to a one, the host controller must not set the Port Change Detect bit.
* | | |Note that when the EHCI controller owns the port, the resume sequence follows the defined sequence documented in the USB Specification Revision 2.0
* | | |The resume signaling (Full-speed 'K') is driven on the port as long as this bit remains a one
* | | |Software must appropriately time the Resume and set this bit to a zero when the appropriate amount of time has elapsed
* | | |Writing a zero (from one) causes the port to return to high-speed mode (forcing the bus below the port into a high-speed idle)
* | | |This bit will remain a one until the port has switched to the high-speed idle
* | | |The host controller must complete this transition within 2 milliseconds of software setting this bit to a zero.
* | | |This field is zero if Port Power is zero.
* | | |0 = No resume (K-state) detected/driven on port.
* | | |1 = Resume detected/driven on port.
* |[7] |SUSPEND |Suspend (read/write)
* | | |Port Enabled Bit and Suspend bit of this register define the port states as follows:
* | | |00 = Port Disable.
* | | |01 = Port Disable.
* | | |10 = Port Enable.
* | | |11 = Port Suspend.
* | | |When in suspend state, downstream propagation of data is blocked on this port, except for port reset
* | | |The blocking occurs at the end of the current transaction, if a transaction was in progress when this bit was written to 1
* | | |In the suspend state, the port is sensitive to resume detection
* | | |Note that the bit status does not change until the port is suspended and that there may be a delay in suspending a port if there is a transaction currently in progress on the USB.
* | | |A write of zero to this bit is ignored by the host controller
* | | |The host controller will unconditionally set this bit to a zero when:
* | | |Software sets the Force Port Resume bit to a zero (from a one).
* | | |Software sets the Port Reset bit to a one (from a zero).
* | | |If host software sets this bit to a one when the port is not enabled (i.e
* | | |Port enabled bit is a zero) the results are undefined.
* | | |This field is zero if Port Power is zero.
* | | |0 = Port not in suspend state.
* | | |1 = Port in suspend state.
* |[8] |PRST |Port Reset (read/write)
* | | |When software writes a one to this bit (from a zero), the bus reset sequence as defined in the USB Specification Revision 2.0 is started
* | | |Software writes a zero to this bit to terminate the bus reset sequence
* | | |Software must keep this bit at a one long enough to ensure the reset sequence, as specified in the USB Specification Revision 2.0, completes
* | | |Note: when software writes this bit to a one, it must also write a zero to the Port Enable bit.
* | | |Note that when software writes a zero to this bit there may be a delay before the bit status changes to a zero
* | | |The bit status will not read as a zero until after the reset has completed
* | | |If the port is in high-speed mode after reset is complete, the host controller will automatically enable this port (e.g
* | | |set the Port Enable bit to a one)
* | | |A host controller must terminate the reset and stabilize the state of the port within 2 milliseconds of software transitioning this bit from a one to a zero
* | | |For example: if the port detects that the attached device is high-speed during reset, then the host controller must have the port in the enabled state within 2ms of software writing this bit to a zero.
* | | |The HCHalted bit in the USBSTS register should be a zero before software attempts to use this bit
* | | |The host controller may hold Port Reset asserted to a one when the HCHalted bit is a one.
* | | |This field is zero if Port Power is zero.
* | | |0 = Port is not in Reset.
* | | |1 = Port is in Reset.
* |[11:10] |LSTS |Line Status (Read Only)
* | | |These bits reflect the current logical levels of the D+ (bit 11) and D- (bit 10) signal lines
* | | |These bits are used for detection of low-speed USB devices prior to the port reset and enable sequence
* | | |This field is valid only when the port enable bit is zero and the current connect status bit is set to a one.
* | | |The encoding of the bits are:
* | | |Bits[11:10] USB State Interpretation
* | | |00 = SE0 Not Low-speed device, perform EHCI reset.
* | | |01 = K-state Low-speed device, release ownership of port.
* | | |10 = J-state Not Low-speed device, perform EHCI reset.
* | | |11 = Undefined Not Low-speed device, perform EHCI reset.
* | | |This value of this field is undefined if Port Power is zero.
* |[12] |PP |Port Power
* | | |Host controller has port power control switches
* | | |This bit represents the Current setting of the switch (0 = off, 1 = on)
* | | |When power is not available on a port (i.e
* | | |PP equals a 0), the port is nonfunctional and will not report attaches, detaches, etc.
* | | |When an overcurrent condition is detected on a powered port and PPC is a one, the PP bit in each affected port may be transitioned by the host controller from a 1 to 0 (removing power from the port).
* |[13] |PO |Port Owner (read/write)
* | | |This bit unconditionally goes to a 0b when the Configured bit in the CONFIGFLAG register makes a 0 to 1 transition
* | | |This bit unconditionally goes to 1 whenever the Configured bit is zero.
* | | |System software uses this field to release ownership of the port to a selected host controller (in the event that the attached device is not a high-speed device)
* | | |Software writes a one to this bit when the attached device is not a high-speed device
* | | |A one in this bit means that a companion host controller owns and controls the port.
* |[19:16] |PTC |Port Test Control (read/write)
* | | |When this field is zero, the port is NOT operating in a test mode
* | | |A non-zero value indicates that it is operating in test mode and the specific test mode is indicated by the specific value
* | | |The encoding of the test mode bits are (0x6 ~ 0xF are reserved):
* | | |Bits Test Mode
* | | |0x0 = Test mode not enabled.
* | | |0x1 = Test J_STATE.
* | | |0x2 = Test K_STATE.
* | | |0x3 = Test SE0_NAK.
* | | |0x4 = Test Packet.
* | | |0x5 = Test FORCE_ENABLE.
*/
__I uint32_t EHCVNR; /*!< [0x0000] EHCI Version Number Register */
__I uint32_t EHCSPR; /*!< [0x0004] EHCI Structural Parameters Register */
__I uint32_t EHCCPR; /*!< [0x0008] EHCI Capability Parameters Register */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE0[1];
/// @endcond //HIDDEN_SYMBOLS
__IO uint32_t UCMDR; /*!< [0x0010] USB Command Register */
__IO uint32_t USTSR; /*!< [0x0014] USB Status Register */
__IO uint32_t UIENR; /*!< [0x0018] USB Interrupt Enable Register */
__IO uint32_t UFINDR; /*!< [0x001c] USB Frame Index Register */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE1[1];
/// @endcond //HIDDEN_SYMBOLS
__IO uint32_t UPFLBAR; /*!< [0x0024] USB Periodic Frame List Base Address Register */
__IO uint32_t UCALAR; /*!< [0x0028] USB Current Asynchronous List Address Register */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE2[9];
/// @endcond //HIDDEN_SYMBOLS
__IO uint32_t UCFGR; /*!< [0x0050] USB Configure Flag Register */
__IO uint32_t UPSCR[1]; /*!< [0x0054] USB Port Status and Control Register */
} HSUSBH_T;
/**
@addtogroup HSUSBH_CONST HSUSBH Bit Field Definition
Constant Definitions for HSUSBH Controller
@{ */
#define HSUSBH_EHCVNR_CRLEN_Pos (0) /*!< HSUSBH_T::EHCVNR: CRLEN Position */
#define HSUSBH_EHCVNR_CRLEN_Msk (0xfful << HSUSBH_EHCVNR_CRLEN_Pos) /*!< HSUSBH_T::EHCVNR: CRLEN Mask */
#define HSUSBH_EHCVNR_VERSION_Pos (16) /*!< HSUSBH_T::EHCVNR: VERSION Position */
#define HSUSBH_EHCVNR_VERSION_Msk (0xfffful << HSUSBH_EHCVNR_VERSION_Pos) /*!< HSUSBH_T::EHCVNR: VERSION Mask */
#define HSUSBH_EHCSPR_N_PORTS_Pos (0) /*!< HSUSBH_T::EHCSPR: N_PORTS Position */
#define HSUSBH_EHCSPR_N_PORTS_Msk (0xful << HSUSBH_EHCSPR_N_PORTS_Pos) /*!< HSUSBH_T::EHCSPR: N_PORTS Mask */
#define HSUSBH_EHCSPR_PPC_Pos (4) /*!< HSUSBH_T::EHCSPR: PPC Position */
#define HSUSBH_EHCSPR_PPC_Msk (0x1ul << HSUSBH_EHCSPR_PPC_Pos) /*!< HSUSBH_T::EHCSPR: PPC Mask */
#define HSUSBH_EHCSPR_N_PCC_Pos (8) /*!< HSUSBH_T::EHCSPR: N_PCC Position */
#define HSUSBH_EHCSPR_N_PCC_Msk (0xful << HSUSBH_EHCSPR_N_PCC_Pos) /*!< HSUSBH_T::EHCSPR: N_PCC Mask */
#define HSUSBH_EHCSPR_N_CC_Pos (12) /*!< HSUSBH_T::EHCSPR: N_CC Position */
#define HSUSBH_EHCSPR_N_CC_Msk (0xful << HSUSBH_EHCSPR_N_CC_Pos) /*!< HSUSBH_T::EHCSPR: N_CC Mask */
#define HSUSBH_EHCCPR_AC64_Pos (0) /*!< HSUSBH_T::EHCCPR: AC64 Position */
#define HSUSBH_EHCCPR_AC64_Msk (0x1ul << HSUSBH_EHCCPR_AC64_Pos) /*!< HSUSBH_T::EHCCPR: AC64 Mask */
#define HSUSBH_EHCCPR_PFLF_Pos (1) /*!< HSUSBH_T::EHCCPR: PFLF Position */
#define HSUSBH_EHCCPR_PFLF_Msk (0x1ul << HSUSBH_EHCCPR_PFLF_Pos) /*!< HSUSBH_T::EHCCPR: PFLF Mask */
#define HSUSBH_EHCCPR_ASPC_Pos (2) /*!< HSUSBH_T::EHCCPR: ASPC Position */
#define HSUSBH_EHCCPR_ASPC_Msk (0x1ul << HSUSBH_EHCCPR_ASPC_Pos) /*!< HSUSBH_T::EHCCPR: ASPC Mask */
#define HSUSBH_EHCCPR_IST_Pos (4) /*!< HSUSBH_T::EHCCPR: IST Position */
#define HSUSBH_EHCCPR_IST_Msk (0xful << HSUSBH_EHCCPR_IST_Pos) /*!< HSUSBH_T::EHCCPR: IST Mask */
#define HSUSBH_EHCCPR_EECP_Pos (8) /*!< HSUSBH_T::EHCCPR: EECP Position */
#define HSUSBH_EHCCPR_EECP_Msk (0xfful << HSUSBH_EHCCPR_EECP_Pos) /*!< HSUSBH_T::EHCCPR: EECP Mask */
#define HSUSBH_UCMDR_RUN_Pos (0) /*!< HSUSBH_T::UCMDR: RUN Position */
#define HSUSBH_UCMDR_RUN_Msk (0x1ul << HSUSBH_UCMDR_RUN_Pos) /*!< HSUSBH_T::UCMDR: RUN Mask */
#define HSUSBH_UCMDR_HCRST_Pos (1) /*!< HSUSBH_T::UCMDR: HCRST Position */
#define HSUSBH_UCMDR_HCRST_Msk (0x1ul << HSUSBH_UCMDR_HCRST_Pos) /*!< HSUSBH_T::UCMDR: HCRST Mask */
#define HSUSBH_UCMDR_FLSZ_Pos (2) /*!< HSUSBH_T::UCMDR: FLSZ Position */
#define HSUSBH_UCMDR_FLSZ_Msk (0x3ul << HSUSBH_UCMDR_FLSZ_Pos) /*!< HSUSBH_T::UCMDR: FLSZ Mask */
#define HSUSBH_UCMDR_PSEN_Pos (4) /*!< HSUSBH_T::UCMDR: PSEN Position */
#define HSUSBH_UCMDR_PSEN_Msk (0x1ul << HSUSBH_UCMDR_PSEN_Pos) /*!< HSUSBH_T::UCMDR: PSEN Mask */
#define HSUSBH_UCMDR_ASEN_Pos (5) /*!< HSUSBH_T::UCMDR: ASEN Position */
#define HSUSBH_UCMDR_ASEN_Msk (0x1ul << HSUSBH_UCMDR_ASEN_Pos) /*!< HSUSBH_T::UCMDR: ASEN Mask */
#define HSUSBH_UCMDR_IAAD_Pos (6) /*!< HSUSBH_T::UCMDR: IAAD Position */
#define HSUSBH_UCMDR_IAAD_Msk (0x1ul << HSUSBH_UCMDR_IAAD_Pos) /*!< HSUSBH_T::UCMDR: IAAD Mask */
#define HSUSBH_UCMDR_ITC_Pos (16) /*!< HSUSBH_T::UCMDR: ITC Position */
#define HSUSBH_UCMDR_ITC_Msk (0xfful << HSUSBH_UCMDR_ITC_Pos) /*!< HSUSBH_T::UCMDR: ITC Mask */
#define HSUSBH_USTSR_USBINT_Pos (0) /*!< HSUSBH_T::USTSR: USBINT Position */
#define HSUSBH_USTSR_USBINT_Msk (0x1ul << HSUSBH_USTSR_USBINT_Pos) /*!< HSUSBH_T::USTSR: USBINT Mask */
#define HSUSBH_USTSR_UERRINT_Pos (1) /*!< HSUSBH_T::USTSR: UERRINT Position */
#define HSUSBH_USTSR_UERRINT_Msk (0x1ul << HSUSBH_USTSR_UERRINT_Pos) /*!< HSUSBH_T::USTSR: UERRINT Mask */
#define HSUSBH_USTSR_PCD_Pos (2) /*!< HSUSBH_T::USTSR: PCD Position */
#define HSUSBH_USTSR_PCD_Msk (0x1ul << HSUSBH_USTSR_PCD_Pos) /*!< HSUSBH_T::USTSR: PCD Mask */
#define HSUSBH_USTSR_FLR_Pos (3) /*!< HSUSBH_T::USTSR: FLR Position */
#define HSUSBH_USTSR_FLR_Msk (0x1ul << HSUSBH_USTSR_FLR_Pos) /*!< HSUSBH_T::USTSR: FLR Mask */
#define HSUSBH_USTSR_HSERR_Pos (4) /*!< HSUSBH_T::USTSR: HSERR Position */
#define HSUSBH_USTSR_HSERR_Msk (0x1ul << HSUSBH_USTSR_HSERR_Pos) /*!< HSUSBH_T::USTSR: HSERR Mask */
#define HSUSBH_USTSR_IAA_Pos (5) /*!< HSUSBH_T::USTSR: IAA Position */
#define HSUSBH_USTSR_IAA_Msk (0x1ul << HSUSBH_USTSR_IAA_Pos) /*!< HSUSBH_T::USTSR: IAA Mask */
#define HSUSBH_USTSR_HCHalted_Pos (12) /*!< HSUSBH_T::USTSR: HCHalted Position */
#define HSUSBH_USTSR_HCHalted_Msk (0x1ul << HSUSBH_USTSR_HCHalted_Pos) /*!< HSUSBH_T::USTSR: HCHalted Mask */
#define HSUSBH_USTSR_RECLA_Pos (13) /*!< HSUSBH_T::USTSR: RECLA Position */
#define HSUSBH_USTSR_RECLA_Msk (0x1ul << HSUSBH_USTSR_RECLA_Pos) /*!< HSUSBH_T::USTSR: RECLA Mask */
#define HSUSBH_USTSR_PSS_Pos (14) /*!< HSUSBH_T::USTSR: PSS Position */
#define HSUSBH_USTSR_PSS_Msk (0x1ul << HSUSBH_USTSR_PSS_Pos) /*!< HSUSBH_T::USTSR: PSS Mask */
#define HSUSBH_USTSR_ASS_Pos (15) /*!< HSUSBH_T::USTSR: ASS Position */
#define HSUSBH_USTSR_ASS_Msk (0x1ul << HSUSBH_USTSR_ASS_Pos) /*!< HSUSBH_T::USTSR: ASS Mask */
#define HSUSBH_UIENR_USBIEN_Pos (0) /*!< HSUSBH_T::UIENR: USBIEN Position */
#define HSUSBH_UIENR_USBIEN_Msk (0x1ul << HSUSBH_UIENR_USBIEN_Pos) /*!< HSUSBH_T::UIENR: USBIEN Mask */
#define HSUSBH_UIENR_UERRIEN_Pos (1) /*!< HSUSBH_T::UIENR: UERRIEN Position */
#define HSUSBH_UIENR_UERRIEN_Msk (0x1ul << HSUSBH_UIENR_UERRIEN_Pos) /*!< HSUSBH_T::UIENR: UERRIEN Mask */
#define HSUSBH_UIENR_PCIEN_Pos (2) /*!< HSUSBH_T::UIENR: PCIEN Position */
#define HSUSBH_UIENR_PCIEN_Msk (0x1ul << HSUSBH_UIENR_PCIEN_Pos) /*!< HSUSBH_T::UIENR: PCIEN Mask */
#define HSUSBH_UIENR_FLREN_Pos (3) /*!< HSUSBH_T::UIENR: FLREN Position */
#define HSUSBH_UIENR_FLREN_Msk (0x1ul << HSUSBH_UIENR_FLREN_Pos) /*!< HSUSBH_T::UIENR: FLREN Mask */
#define HSUSBH_UIENR_HSERREN_Pos (4) /*!< HSUSBH_T::UIENR: HSERREN Position */
#define HSUSBH_UIENR_HSERREN_Msk (0x1ul << HSUSBH_UIENR_HSERREN_Pos) /*!< HSUSBH_T::UIENR: HSERREN Mask */
#define HSUSBH_UIENR_IAAEN_Pos (5) /*!< HSUSBH_T::UIENR: IAAEN Position */
#define HSUSBH_UIENR_IAAEN_Msk (0x1ul << HSUSBH_UIENR_IAAEN_Pos) /*!< HSUSBH_T::UIENR: IAAEN Mask */
#define HSUSBH_UFINDR_FI_Pos (0) /*!< HSUSBH_T::UFINDR: FI Position */
#define HSUSBH_UFINDR_FI_Msk (0x3ffful << HSUSBH_UFINDR_FI_Pos) /*!< HSUSBH_T::UFINDR: FI Mask */
#define HSUSBH_UPFLBAR_BADDR_Pos (12) /*!< HSUSBH_T::UPFLBAR: BADDR Position */
#define HSUSBH_UPFLBAR_BADDR_Msk (0xffffful << HSUSBH_UPFLBAR_BADDR_Pos) /*!< HSUSBH_T::UPFLBAR: BADDR Mask */
#define HSUSBH_UCALAR_LPL_Pos (5) /*!< HSUSBH_T::UCALAR: LPL Position */
#define HSUSBH_UCALAR_LPL_Msk (0x7fffffful << HSUSBH_UCALAR_LPL_Pos) /*!< HSUSBH_T::UCALAR: LPL Mask */
#define HSUSBH_UCFGR_CF_Pos (0) /*!< HSUSBH_T::UCFGR: CF Position */
#define HSUSBH_UCFGR_CF_Msk (0x1ul << HSUSBH_UCFGR_CF_Pos) /*!< HSUSBH_T::UCFGR: CF Mask */
#define HSUSBH_UPSCR_CCS_Pos (0) /*!< HSUSBH_T::UPSCR: CCS Position */
#define HSUSBH_UPSCR_CCS_Msk (0x1ul << HSUSBH_UPSCR_CCS_Pos) /*!< HSUSBH_T::UPSCR: CCS Mask */
#define HSUSBH_UPSCR_CSC_Pos (1) /*!< HSUSBH_T::UPSCR: CSC Position */
#define HSUSBH_UPSCR_CSC_Msk (0x1ul << HSUSBH_UPSCR_CSC_Pos) /*!< HSUSBH_T::UPSCR: CSC Mask */
#define HSUSBH_UPSCR_PE_Pos (2) /*!< HSUSBH_T::UPSCR: PE Position */
#define HSUSBH_UPSCR_PE_Msk (0x1ul << HSUSBH_UPSCR_PE_Pos) /*!< HSUSBH_T::UPSCR: PE Mask */
#define HSUSBH_UPSCR_PEC_Pos (3) /*!< HSUSBH_T::UPSCR: PEC Position */
#define HSUSBH_UPSCR_PEC_Msk (0x1ul << HSUSBH_UPSCR_PEC_Pos) /*!< HSUSBH_T::UPSCR: PEC Mask */
#define HSUSBH_UPSCR_OCA_Pos (4) /*!< HSUSBH_T::UPSCR: OCA Position */
#define HSUSBH_UPSCR_OCA_Msk (0x1ul << HSUSBH_UPSCR_OCA_Pos) /*!< HSUSBH_T::UPSCR: OCA Mask */
#define HSUSBH_UPSCR_OCC_Pos (5) /*!< HSUSBH_T::UPSCR: OCC Position */
#define HSUSBH_UPSCR_OCC_Msk (0x1ul << HSUSBH_UPSCR_OCC_Pos) /*!< HSUSBH_T::UPSCR: OCC Mask */
#define HSUSBH_UPSCR_FPR_Pos (6) /*!< HSUSBH_T::UPSCR: FPR Position */
#define HSUSBH_UPSCR_FPR_Msk (0x1ul << HSUSBH_UPSCR_FPR_Pos) /*!< HSUSBH_T::UPSCR: FPR Mask */
#define HSUSBH_UPSCR_SUSPEND_Pos (7) /*!< HSUSBH_T::UPSCR: SUSPEND Position */
#define HSUSBH_UPSCR_SUSPEND_Msk (0x1ul << HSUSBH_UPSCR_SUSPEND_Pos) /*!< HSUSBH_T::UPSCR: SUSPEND Mask */
#define HSUSBH_UPSCR_PRST_Pos (8) /*!< HSUSBH_T::UPSCR: PRST Position */
#define HSUSBH_UPSCR_PRST_Msk (0x1ul << HSUSBH_UPSCR_PRST_Pos) /*!< HSUSBH_T::UPSCR: PRST Mask */
#define HSUSBH_UPSCR_LSTS_Pos (10) /*!< HSUSBH_T::UPSCR: LSTS Position */
#define HSUSBH_UPSCR_LSTS_Msk (0x3ul << HSUSBH_UPSCR_LSTS_Pos) /*!< HSUSBH_T::UPSCR: LSTS Mask */
#define HSUSBH_UPSCR_PP_Pos (12) /*!< HSUSBH_T::UPSCR: PP Position */
#define HSUSBH_UPSCR_PP_Msk (0x1ul << HSUSBH_UPSCR_PP_Pos) /*!< HSUSBH_T::UPSCR: PP Mask */
#define HSUSBH_UPSCR_PO_Pos (13) /*!< HSUSBH_T::UPSCR: PO Position */
#define HSUSBH_UPSCR_PO_Msk (0x1ul << HSUSBH_UPSCR_PO_Pos) /*!< HSUSBH_T::UPSCR: PO Mask */
#define HSUSBH_UPSCR_PTC_Pos (16) /*!< HSUSBH_T::UPSCR: PTC Position */
#define HSUSBH_UPSCR_PTC_Msk (0xful << HSUSBH_UPSCR_PTC_Pos) /*!< HSUSBH_T::UPSCR: PTC Mask */
/**@}*/ /* HSUSBH_CONST */
/**@}*/ /* end of HSUSBH register group */
/**@}*/ /* end of REGISTER group */
#if defined ( __CC_ARM )
#pragma no_anon_unions
#endif
#endif /* __HSUSBH_REG_H__ */

452
bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/hwsem_reg.h Normal file
View File

@ -0,0 +1,452 @@
/**************************************************************************//**
* @file hwsem_reg.h
* @brief HWSEM register definition header file
*
* SPDX-License-Identifier: Apache-2.0
* @copyright (C) 2020~2021 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __HWSEM_REG_H__
#define __HWSEM_REG_H__
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
/**
@addtogroup REGISTER Control Register
@{
*/
/**
@addtogroup HWSEM Hardware Semaphore (HWSEM)
Memory Mapped Structure for HWSEM Controller
@{ */
typedef struct
{
/**
* @var HWSEM_T::CTL
* Offset: 0x00 HWSEM Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |SEM0RST |Reset Semaphore 0
* | | |Set this bit to reset semaphore 0
* | | |After reset, SEM_SEM0 will reset to 0
* | | |This bit automatically clears to 0 after reset complete.
* |[1] |SEM1RST |Reset Semaphore 1
* | | |Set this bit to reset semaphore 1
* | | |After reset, SEM_SEM1 will reset to 0
* | | |This bit automatically clears to 0 after reset complete.
* |[2] |SEM2RST |Reset Semaphore 2
* | | |Set this bit to reset semaphore 2
* | | |After reset, SEM_SEM2 will reset to 0
* | | |This bit automatically clears to 0 after reset complete.
* |[3] |SEM3RST |Reset Semaphore 3
* | | |Set this bit to reset semaphore 3
* | | |After reset, SEM_SEM3 will reset to 0
* | | |This bit automatically clears to 0 after reset complete.
* |[4] |SEM4RST |Reset Semaphore 4
* | | |Set this bit to reset semaphore 4
* | | |After reset, SEM_SEM4 will reset to 0
* | | |This bit automatically clears to 0 after reset complete.
* |[5] |SEM5RST |Reset Semaphore 5
* | | |Set this bit to reset semaphore 5
* | | |After reset, SEM_SEM5 will reset to 0
* | | |This bit automatically clears to 0 after reset complete.
* |[6] |SEM6RST |Reset Semaphore 6
* | | |Set this bit to reset semaphore 6
* | | |After reset, SEM_SEM6 will reset to 0
* | | |This bit automatically clears to 0 after reset complete.
* |[7] |SEM7RST |Reset Semaphore 7
* | | |Set this bit to reset semaphore 7
* | | |After reset, SEM_SEM7 will reset to 0
* | | |This bit automatically clears to 0 after reset complete.
* @var HWSEM_T::INTENA35
* Offset: 0x04 HWSEM Interrupt Enable Register (A35 Can Read/Write ,M4 Can Only Read)
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |SEM0IEN |Semaphore 0 Unlock Interrupt Enable Bit
* | | |0 = Semaphore 0 unlock interrupt Disabled
* | | |1 = Semaphore 0 unlock interrupt Enabled.
* |[1] |SEM1IEN |Semaphore 1 Unlock Interrupt Enable Bit
* | | |0 = Semaphore 1 unlock interrupt Disabled
* | | |1 = Semaphore 1 unlock interrupt Enabled.
* |[2] |SEM2IEN |Semaphore 2 Unlock Interrupt Enable Bit
* | | |0 = Semaphore 2 unlock interrupt Disabled
* | | |1 = Semaphore 2 unlock interrupt Enabled.
* |[3] |SEM3IEN |Semaphore 3 Unlock Interrupt Enable Bit
* | | |0 = Semaphore 3 unlock interrupt Disabled
* | | |1 = Semaphore 3 unlock interrupt Enabled.
* |[4] |SEM4IEN |Semaphore 4 Unlock Interrupt Enable Bit
* | | |0 = Semaphore 4 unlock interrupt Disabled
* | | |1 = Semaphore 4 unlock interrupt Enabled.
* |[5] |SEM5IEN |Semaphore 5 Unlock Interrupt Enable Bit
* | | |0 = Semaphore 5 unlock interrupt Disabled
* | | |1 = Semaphore 5 unlock interrupt Enabled.
* |[6] |SEM6IEN |Semaphore 6 Unlock Interrupt Enable Bit
* | | |0 = Semaphore 6 unlock interrupt Disabled
* | | |1 = Semaphore 6 unlock interrupt Enabled.
* |[7] |SEM7IEN |Semaphore 7 Unlock Interrupt Enable Bit
* | | |0 = Semaphore 7 unlock interrupt Disabled
* | | |1 = Semaphore 7 unlock interrupt Enabled.
* @var HWSEM_T::INTENM4
* Offset: 0x08 HWSEM Interrupt Enable Register (M4 Can Read/Write , A35 Can Only Read)
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |SEM0IEN |Semaphore 0 Unlock Interrupt Enable Bit
* | | |0 = Semaphore 0 unlock interrupt Disabled.
* | | |1 = Semaphore 0 unlock interrupt Enabled.
* |[1] |SEM1IEN |Semaphore 1 Unlock Interrupt Enable Bit
* | | |0 = Semaphore 1 unlock interrupt Disabled.
* | | |1 = Semaphore 1 unlock interrupt Enabled.
* |[2] |SEM2IEN |Semaphore 2 Unlock Interrupt Enable Bit
* | | |0 = Semaphore 2 unlock interrupt Disabled.
* | | |1 = Semaphore 2 unlock interrupt Enabled.
* |[3] |SEM3IEN |Semaphore 3 Unlock Interrupt Enable Bit
* | | |0 = Semaphore 3 unlock interrupt Disabled.
* | | |1 = Semaphore 3 unlock interrupt Enabled.
* |[4] |SEM4IEN |Semaphore 4 Unlock Interrupt Enable Bit
* | | |0 = Semaphore 4 unlock interrupt Disabled.
* | | |1 = Semaphore 4 unlock interrupt Enabled.
* |[5] |SEM5IEN |Semaphore 5 Unlock Interrupt Enable Bit
* | | |0 = Semaphore 5 unlock interrupt Disabled.
* | | |1 = Semaphore 5 unlock interrupt Enabled.
* |[6] |SEM6IEN |Semaphore 6 Unlock Interrupt Enable Bit
* | | |0 = Semaphore 6 unlock interrupt Disabled.
* | | |1 = Semaphore 6 unlock interrupt Enabled.
* |[7] |SEM7IEN |Semaphore 7 Unlock Interrupt Enable Bit
* | | |0 = Semaphore 7 unlock interrupt Disabled.
* | | |1 = Semaphore 7 unlock interrupt Enabled.
* @var HWSEM_T::INTSTSA35
* Offset: 0x0C HWSEM Interrupt Status Register (A35 Can Read/Write ,M4 Can Only Read) (Write 1 to Clear)
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |SEM0IF |Semaphore 0 Unlock Interrupt Flag
* | | |0 = No semaphore 0 unlock interrupt generated.
* | | |1 = Semaphore 0 unlock interrupt generated.
* | | |Note: Write 1 to clear this bit to 0.
* |[1] |SEM1IF |Semaphore 1 Unlock Interrupt Flag
* | | |0 = No semaphore 1 unlock interrupt generated.
* | | |1 = Semaphore 1 unlock interrupt generated.
* | | |Note: Write 1 to clear this bit to 0.
* |[2] |SEM2IF |Semaphore 2 Unlock Interrupt Flag
* | | |0 = No semaphore 2 unlock interrupt generated.
* | | |1 = Semaphore 2 unlock interrupt generated.
* | | |Note: Write 1 to clear this bit to 0.
* |[3] |SEM3IF |Semaphore 3 Unlock Interrupt Flag
* | | |0 = No semaphore 3 unlock interrupt generated.
* | | |1 = Semaphore 3 unlock interrupt generated.
* | | |Note: Write 1 to clear this bit to 0.
* |[4] |SEM4IF |Semaphore 4 Unlock Interrupt Flag
* | | |0 = No semaphore 4 unlock interrupt generated.
* | | |1 = Semaphore 4 unlock interrupt generated.
* | | |Note: Write 1 to clear this bit to 0.
* |[5] |SEM5IF |Semaphore 5 Unlock Interrupt Flag
* | | |0 = No semaphore 5 unlock interrupt generated.
* | | |1 = Semaphore 5 unlock interrupt generated.
* | | |Note: Write 1 to clear this bit to 0.
* |[6] |SEM6IF |Semaphore 6 Unlock Interrupt Flag
* | | |0 = No semaphore 6 unlock interrupt generated.
* | | |1 = Semaphore 6 unlock interrupt generated.
* | | |Note: Write 1 to clear this bit to 0.
* |[7] |SEM7IF |Semaphore 7 Unlock Interrupt Flag
* | | |0 = No semaphore 7 unlock interrupt generated.
* | | |1 = Semaphore 7 unlock interrupt generated.
* | | |Note: Write 1 to clear this bit to 0.
* @var HWSEM_T::INTSTSM4
* Offset: 0x10 HWSEM Interrupt Status Register (M4 Can Read/Write , A35 Can Only Read) (Write 1 to Clear)
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |SEM0IF |Semaphore 0 Unlock Interrupt Flag
* | | |0 = No semaphore 0 unlock interrupt generated.
* | | |1 = Semaphore 0 unlock interrupt generated.
* | | |Note: Write 1 to clear this bit to 0.
* |[1] |SEM1IF |Semaphore 1 Unlock Interrupt Flag
* | | |0 = No semaphore 1 unlock interrupt generated.
* | | |1 = Semaphore 1 unlock interrupt generated.
* | | |Note: Write 1 to clear this bit to 0.
* |[2] |SEM2IF |Semaphore 2 Unlock Interrupt Flag
* | | |0 = No semaphore 2 unlock interrupt generated.
* | | |1 = Semaphore 2 unlock interrupt generated.
* | | |Note: Write 1 to clear this bit to 0.
* |[3] |SEM3IF |Semaphore 3 Unlock Interrupt Flag
* | | |0 = No semaphore 3 unlock interrupt generated.
* | | |1 = Semaphore 3 unlock interrupt generated.
* | | |Note: Write 1 to clear this bit to 0.
* |[4] |SEM4IF |Semaphore 4 Unlock Interrupt Flag
* | | |0 = No semaphore 4 unlock interrupt generated.
* | | |1 = Semaphore 4 unlock interrupt generated.
* | | |Note: Write 1 to clear this bit to 0.
* |[5] |SEM5IF |Semaphore 5 Unlock Interrupt Flag
* | | |0 = No semaphore 5 unlock interrupt generated.
* | | |1 = Semaphore 5 unlock interrupt generated.
* | | |Note: Write 1 to clear this bit to 0.
* |[6] |SEM6IF |Semaphore 6 Unlock Interrupt Flag
* | | |0 = No semaphore 6 unlock interrupt generated.
* | | |1 = Semaphore 6 unlock interrupt generated.
* | | |Note: Write 1 to clear this bit to 0.
* |[7] |SEM7IF |Semaphore 7 Unlock Interrupt Flag
* | | |0 = No semaphore 7 unlock interrupt generated.
* | | |1 = Semaphore 7 unlock interrupt generated.
* | | |Note: Write 1 to clear this bit to 0.
* @var HWSEM_T::SEM0
* Offset: 0x20 HWSEM Semaphore 0 Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[3:0] |ID |Processor ID (Read Only)
* | | |This field holds the ID of Processor which lock this semaphore.
* | | |0000 = Semaphore is unlocked.
* | | |0001 = This semaphore is locked by Cortex-A.
* | | |0010 = This semaphore is locked by Cortex-M.
* | | |Others = Reserved.
* |[15:8] |KEY |Key for Lock/Unlock Semaphore
* | | |This field holds the key to lock/unlock this semaphore.
* @var HWSEM_T::SEM1
* Offset: 0x24 HWSEM Semaphore 1 Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[3:0] |ID |Processor ID (Read Only)
* | | |This field holds the ID of Processor which lock this semaphore.
* | | |0000 = Semaphore is unlocked.
* | | |0001 = This semaphore is locked by Cortex-A.
* | | |0010 = This semaphore is locked by Cortex-M.
* | | |Others = Reserved.
* |[15:8] |KEY |Key for Lock/Unlock Semaphore
* | | |This field holds the key to lock/unlock this semaphore.
* @var HWSEM_T::SEM2
* Offset: 0x28 HWSEM Semaphore 2 Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[3:0] |ID |Processor ID (Read Only)
* | | |This field holds the ID of Processor which lock this semaphore.
* | | |0000 = Semaphore is unlocked.
* | | |0001 = This semaphore is locked by Cortex-A.
* | | |0010 = This semaphore is locked by Cortex-M.
* | | |Others = Reserved.
* |[15:8] |KEY |Key for Lock/Unlock Semaphore
* | | |This field holds the key to lock/unlock this semaphore.
* @var HWSEM_T::SEM3
* Offset: 0x2C HWSEM Semaphore 3 Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[3:0] |ID |Processor ID (Read Only)
* | | |This field holds the ID of Processor which lock this semaphore.
* | | |0000 = Semaphore is unlocked.
* | | |0001 = This semaphore is locked by Cortex-A.
* | | |0010 = This semaphore is locked by Cortex-M.
* | | |Others = Reserved.
* |[15:8] |KEY |Key for Lock/Unlock Semaphore
* | | |This field holds the key to lock/unlock this semaphore.
* @var HWSEM_T::SEM4
* Offset: 0x30 HWSEM Semaphore 4 Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[3:0] |ID |Processor ID (Read Only)
* | | |This field holds the ID of Processor which lock this semaphore.
* | | |0000 = Semaphore is unlocked.
* | | |0001 = This semaphore is locked by Cortex-A.
* | | |0010 = This semaphore is locked by Cortex-M.
* | | |Others = Reserved.
* |[15:8] |KEY |Key for Lock/Unlock Semaphore
* | | |This field holds the key to lock/unlock this semaphore.
* @var HWSEM_T::SEM5
* Offset: 0x34 HWSEM Semaphore 5 Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[3:0] |ID |Processor ID (Read Only)
* | | |This field holds the ID of Processor which lock this semaphore.
* | | |0000 = Semaphore is unlocked.
* | | |0001 = This semaphore is locked by Cortex-A.
* | | |0010 = This semaphore is locked by Cortex-M.
* | | |Others = Reserved.
* |[15:8] |KEY |Key for Lock/Unlock Semaphore
* | | |This field holds the key to lock/unlock this semaphore.
* @var HWSEM_T::SEM6
* Offset: 0x38 HWSEM Semaphore 6 Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[3:0] |ID |Processor ID (Read Only)
* | | |This field holds the ID of Processor which lock this semaphore.
* | | |0000 = Semaphore is unlocked.
* | | |0001 = This semaphore is locked by Cortex-A.
* | | |0010 = This semaphore is locked by Cortex-M.
* | | |Others = Reserved.
* |[15:8] |KEY |Key for Lock/Unlock Semaphore
* | | |This field holds the key to lock/unlock this semaphore.
* @var HWSEM_T::SEM7
* Offset: 0x3C HWSEM Semaphore 7 Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[3:0] |ID |Processor ID (Read Only)
* | | |This field holds the ID of Processor which lock this semaphore.
* | | |0000 = Semaphore is unlocked.
* | | |0001 = This semaphore is locked by Cortex-A.
* | | |0010 = This semaphore is locked by Cortex-M.
* | | |Others = Reserved.
* |[15:8] |KEY |Key for Lock/Unlock Semaphore
* | | |This field holds the key to lock/unlock this semaphore.
*/
__IO uint32_t CTL; /*!< [0x0000] HWSEM Control Register */
__IO uint32_t INTENA35; /*!< [0x0004] HWSEM Interrupt Enable Register */
__IO uint32_t INTENM4; /*!< [0x0008] HWSEM Interrupt Enable Register */
__IO uint32_t INTSTSA35; /*!< [0x000c] HWSEM Interrupt Status Register */
__IO uint32_t INTSTSM4; /*!< [0x0010] HWSEM Interrupt Status Register */
__I uint32_t RESERVE0[3];
__IO uint32_t SEM[8]; /*!< [0x0020~0x003C] HWSEM Semaphore 0~8 Register */
} HWSEM_T;
/**
@addtogroup HWSEM_CONST HWSEM Bit Field Definition
Constant Definitions for HWSEM Controller
@{ */
#define HWSEM_CTL_SEM0RST_Pos (0) /*!< HWSEM_T::CTL: SEM0RST Position */
#define HWSEM_CTL_SEM0RST_Msk (0x1ul << HWSEM_CTL_SEM0RST_Pos) /*!< HWSEM_T::CTL: SEM0RST Mask */
#define HWSEM_CTL_SEM1RST_Pos (1) /*!< HWSEM_T::CTL: SEM1RST Position */
#define HWSEM_CTL_SEM1RST_Msk (0x1ul << HWSEM_CTL_SEM1RST_Pos) /*!< HWSEM_T::CTL: SEM1RST Mask */
#define HWSEM_CTL_SEM2RST_Pos (2) /*!< HWSEM_T::CTL: SEM2RST Position */
#define HWSEM_CTL_SEM2RST_Msk (0x1ul << HWSEM_CTL_SEM2RST_Pos) /*!< HWSEM_T::CTL: SEM2RST Mask */
#define HWSEM_CTL_SEM3RST_Pos (3) /*!< HWSEM_T::CTL: SEM3RST Position */
#define HWSEM_CTL_SEM3RST_Msk (0x1ul << HWSEM_CTL_SEM3RST_Pos) /*!< HWSEM_T::CTL: SEM3RST Mask */
#define HWSEM_CTL_SEM4RST_Pos (4) /*!< HWSEM_T::CTL: SEM4RST Position */
#define HWSEM_CTL_SEM4RST_Msk (0x1ul << HWSEM_CTL_SEM4RST_Pos) /*!< HWSEM_T::CTL: SEM4RST Mask */
#define HWSEM_CTL_SEM5RST_Pos (5) /*!< HWSEM_T::CTL: SEM5RST Position */
#define HWSEM_CTL_SEM5RST_Msk (0x1ul << HWSEM_CTL_SEM5RST_Pos) /*!< HWSEM_T::CTL: SEM5RST Mask */
#define HWSEM_CTL_SEM6RST_Pos (6) /*!< HWSEM_T::CTL: SEM6RST Position */
#define HWSEM_CTL_SEM6RST_Msk (0x1ul << HWSEM_CTL_SEM6RST_Pos) /*!< HWSEM_T::CTL: SEM6RST Mask */
#define HWSEM_CTL_SEM7RST_Pos (7) /*!< HWSEM_T::CTL: SEM7RST Position */
#define HWSEM_CTL_SEM7RST_Msk (0x1ul << HWSEM_CTL_SEM7RST_Pos) /*!< HWSEM_T::CTL: SEM7RST Mask */
#define HWSEM_INTENA35_SEM0IEN_Pos (0) /*!< HWSEM_T::INTENA35: SEM0IEN Position */
#define HWSEM_INTENA35_SEM0IEN_Msk (0x1ul << HWSEM_INTENA35_SEM0IEN_Pos) /*!< HWSEM_T::INTENA35: SEM0IEN Mask */
#define HWSEM_INTENA35_SEM1IEN_Pos (1) /*!< HWSEM_T::INTENA35: SEM1IEN Position */
#define HWSEM_INTENA35_SEM1IEN_Msk (0x1ul << HWSEM_INTENA35_SEM1IEN_Pos) /*!< HWSEM_T::INTENA35: SEM1IEN Mask */
#define HWSEM_INTENA35_SEM2IEN_Pos (2) /*!< HWSEM_T::INTENA35: SEM2IEN Position */
#define HWSEM_INTENA35_SEM2IEN_Msk (0x1ul << HWSEM_INTENA35_SEM2IEN_Pos) /*!< HWSEM_T::INTENA35: SEM2IEN Mask */
#define HWSEM_INTENA35_SEM3IEN_Pos (3) /*!< HWSEM_T::INTENA35: SEM3IEN Position */
#define HWSEM_INTENA35_SEM3IEN_Msk (0x1ul << HWSEM_INTENA35_SEM3IEN_Pos) /*!< HWSEM_T::INTENA35: SEM3IEN Mask */
#define HWSEM_INTENA35_SEM4IEN_Pos (4) /*!< HWSEM_T::INTENA35: SEM4IEN Position */
#define HWSEM_INTENA35_SEM4IEN_Msk (0x1ul << HWSEM_INTENA35_SEM4IEN_Pos) /*!< HWSEM_T::INTENA35: SEM4IEN Mask */
#define HWSEM_INTENA35_SEM5IEN_Pos (5) /*!< HWSEM_T::INTENA35: SEM5IEN Position */
#define HWSEM_INTENA35_SEM5IEN_Msk (0x1ul << HWSEM_INTENA35_SEM5IEN_Pos) /*!< HWSEM_T::INTENA35: SEM5IEN Mask */
#define HWSEM_INTENA35_SEM6IEN_Pos (6) /*!< HWSEM_T::INTENA35: SEM6IEN Position */
#define HWSEM_INTENA35_SEM6IEN_Msk (0x1ul << HWSEM_INTENA35_SEM6IEN_Pos) /*!< HWSEM_T::INTENA35: SEM6IEN Mask */
#define HWSEM_INTENA35_SEM7IEN_Pos (7) /*!< HWSEM_T::INTENA35: SEM7IEN Position */
#define HWSEM_INTENA35_SEM7IEN_Msk (0x1ul << HWSEM_INTENA35_SEM7IEN_Pos) /*!< HWSEM_T::INTENA35: SEM7IEN Mask */
#define HWSEM_INTENM4_SEM0IEN_Pos (0) /*!< HWSEM_T::INTENM4: SEM0IEN Position */
#define HWSEM_INTENM4_SEM0IEN_Msk (0x1ul << HWSEM_INTENM4_SEM0IEN_Pos) /*!< HWSEM_T::INTENM4: SEM0IEN Mask */
#define HWSEM_INTENM4_SEM1IEN_Pos (1) /*!< HWSEM_T::INTENM4: SEM1IEN Position */
#define HWSEM_INTENM4_SEM1IEN_Msk (0x1ul << HWSEM_INTENM4_SEM1IEN_Pos) /*!< HWSEM_T::INTENM4: SEM1IEN Mask */
#define HWSEM_INTENM4_SEM2IEN_Pos (2) /*!< HWSEM_T::INTENM4: SEM2IEN Position */
#define HWSEM_INTENM4_SEM2IEN_Msk (0x1ul << HWSEM_INTENM4_SEM2IEN_Pos) /*!< HWSEM_T::INTENM4: SEM2IEN Mask */
#define HWSEM_INTENM4_SEM3IEN_Pos (3) /*!< HWSEM_T::INTENM4: SEM3IEN Position */
#define HWSEM_INTENM4_SEM3IEN_Msk (0x1ul << HWSEM_INTENM4_SEM3IEN_Pos) /*!< HWSEM_T::INTENM4: SEM3IEN Mask */
#define HWSEM_INTENM4_SEM4IEN_Pos (4) /*!< HWSEM_T::INTENM4: SEM4IEN Position */
#define HWSEM_INTENM4_SEM4IEN_Msk (0x1ul << HWSEM_INTENM4_SEM4IEN_Pos) /*!< HWSEM_T::INTENM4: SEM4IEN Mask */
#define HWSEM_INTENM4_SEM5IEN_Pos (5) /*!< HWSEM_T::INTENM4: SEM5IEN Position */
#define HWSEM_INTENM4_SEM5IEN_Msk (0x1ul << HWSEM_INTENM4_SEM5IEN_Pos) /*!< HWSEM_T::INTENM4: SEM5IEN Mask */
#define HWSEM_INTENM4_SEM6IEN_Pos (6) /*!< HWSEM_T::INTENM4: SEM6IEN Position */
#define HWSEM_INTENM4_SEM6IEN_Msk (0x1ul << HWSEM_INTENM4_SEM6IEN_Pos) /*!< HWSEM_T::INTENM4: SEM6IEN Mask */
#define HWSEM_INTENM4_SEM7IEN_Pos (7) /*!< HWSEM_T::INTENM4: SEM7IEN Position */
#define HWSEM_INTENM4_SEM7IEN_Msk (0x1ul << HWSEM_INTENM4_SEM7IEN_Pos) /*!< HWSEM_T::INTENM4: SEM7IEN Mask */
#define HWSEM_INTSTSA35_SEM0IF_Pos (0) /*!< HWSEM_T::INTSTSA35: SEM0IF Position */
#define HWSEM_INTSTSA35_SEM0IF_Msk (0x1ul << HWSEM_INTSTSA35_SEM0IF_Pos) /*!< HWSEM_T::INTSTSA35: SEM0IF Mask */
#define HWSEM_INTSTSA35_SEM1IF_Pos (1) /*!< HWSEM_T::INTSTSA35: SEM1IF Position */
#define HWSEM_INTSTSA35_SEM1IF_Msk (0x1ul << HWSEM_INTSTSA35_SEM1IF_Pos) /*!< HWSEM_T::INTSTSA35: SEM1IF Mask */
#define HWSEM_INTSTSA35_SEM2IF_Pos (2) /*!< HWSEM_T::INTSTSA35: SEM2IF Position */
#define HWSEM_INTSTSA35_SEM2IF_Msk (0x1ul << HWSEM_INTSTSA35_SEM2IF_Pos) /*!< HWSEM_T::INTSTSA35: SEM2IF Mask */
#define HWSEM_INTSTSA35_SEM3IF_Pos (3) /*!< HWSEM_T::INTSTSA35: SEM3IF Position */
#define HWSEM_INTSTSA35_SEM3IF_Msk (0x1ul << HWSEM_INTSTSA35_SEM3IF_Pos) /*!< HWSEM_T::INTSTSA35: SEM3IF Mask */
#define HWSEM_INTSTSA35_SEM4IF_Pos (4) /*!< HWSEM_T::INTSTSA35: SEM4IF Position */
#define HWSEM_INTSTSA35_SEM4IF_Msk (0x1ul << HWSEM_INTSTSA35_SEM4IF_Pos) /*!< HWSEM_T::INTSTSA35: SEM4IF Mask */
#define HWSEM_INTSTSA35_SEM5IF_Pos (5) /*!< HWSEM_T::INTSTSA35: SEM5IF Position */
#define HWSEM_INTSTSA35_SEM5IF_Msk (0x1ul << HWSEM_INTSTSA35_SEM5IF_Pos) /*!< HWSEM_T::INTSTSA35: SEM5IF Mask */
#define HWSEM_INTSTSA35_SEM6IF_Pos (6) /*!< HWSEM_T::INTSTSA35: SEM6IF Position */
#define HWSEM_INTSTSA35_SEM6IF_Msk (0x1ul << HWSEM_INTSTSA35_SEM6IF_Pos) /*!< HWSEM_T::INTSTSA35: SEM6IF Mask */
#define HWSEM_INTSTSA35_SEM7IF_Pos (7) /*!< HWSEM_T::INTSTSA35: SEM7IF Position */
#define HWSEM_INTSTSA35_SEM7IF_Msk (0x1ul << HWSEM_INTSTSA35_SEM7IF_Pos) /*!< HWSEM_T::INTSTSA35: SEM7IF Mask */
#define HWSEM_INTSTSM4_SEM0IF_Pos (0) /*!< HWSEM_T::INTSTSM4: SEM0IF Position */
#define HWSEM_INTSTSM4_SEM0IF_Msk (0x1ul << HWSEM_INTSTSM4_SEM0IF_Pos) /*!< HWSEM_T::INTSTSM4: SEM0IF Mask */
#define HWSEM_INTSTSM4_SEM1IF_Pos (1) /*!< HWSEM_T::INTSTSM4: SEM1IF Position */
#define HWSEM_INTSTSM4_SEM1IF_Msk (0x1ul << HWSEM_INTSTSM4_SEM1IF_Pos) /*!< HWSEM_T::INTSTSM4: SEM1IF Mask */
#define HWSEM_INTSTSM4_SEM2IF_Pos (2) /*!< HWSEM_T::INTSTSM4: SEM2IF Position */
#define HWSEM_INTSTSM4_SEM2IF_Msk (0x1ul << HWSEM_INTSTSM4_SEM2IF_Pos) /*!< HWSEM_T::INTSTSM4: SEM2IF Mask */
#define HWSEM_INTSTSM4_SEM3IF_Pos (3) /*!< HWSEM_T::INTSTSM4: SEM3IF Position */
#define HWSEM_INTSTSM4_SEM3IF_Msk (0x1ul << HWSEM_INTSTSM4_SEM3IF_Pos) /*!< HWSEM_T::INTSTSM4: SEM3IF Mask */
#define HWSEM_INTSTSM4_SEM4IF_Pos (4) /*!< HWSEM_T::INTSTSM4: SEM4IF Position */
#define HWSEM_INTSTSM4_SEM4IF_Msk (0x1ul << HWSEM_INTSTSM4_SEM4IF_Pos) /*!< HWSEM_T::INTSTSM4: SEM4IF Mask */
#define HWSEM_INTSTSM4_SEM5IF_Pos (5) /*!< HWSEM_T::INTSTSM4: SEM5IF Position */
#define HWSEM_INTSTSM4_SEM5IF_Msk (0x1ul << HWSEM_INTSTSM4_SEM5IF_Pos) /*!< HWSEM_T::INTSTSM4: SEM5IF Mask */
#define HWSEM_INTSTSM4_SEM6IF_Pos (6) /*!< HWSEM_T::INTSTSM4: SEM6IF Position */
#define HWSEM_INTSTSM4_SEM6IF_Msk (0x1ul << HWSEM_INTSTSM4_SEM6IF_Pos) /*!< HWSEM_T::INTSTSM4: SEM6IF Mask */
#define HWSEM_INTSTSM4_SEM7IF_Pos (7) /*!< HWSEM_T::INTSTSM4: SEM7IF Position */
#define HWSEM_INTSTSM4_SEM7IF_Msk (0x1ul << HWSEM_INTSTSM4_SEM7IF_Pos) /*!< HWSEM_T::INTSTSM4: SEM7IF Mask */
#define HWSEM_SEM_ID_Pos (0)
#define HWSEM_SEM_ID_Msk (0xful << HWSEM_SEM_ID_Pos)
#define HWSEM_SEM_KEY_Pos (8) /*!< HWSEM_T::SEM: ID Position */
#define HWSEM_SEM_KEY_Msk (0xfful << HWSEM_SEM_KEY_Pos) /*!< HWSEM_T::SEM: ID Mask */
/**@}*/ /* HWSEM_CONST */
/**@}*/ /* end of HWSEM register group */
/**@}*/ /* end of REGISTER group */
#if defined ( __CC_ARM )
#pragma no_anon_unions
#endif
#endif /* __HWSEM_REG_H__ */

453
bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/i2c_reg.h Normal file
View File

@ -0,0 +1,453 @@
/**************************************************************************//**
* @file i2c_reg.h
* @brief I2C register definition header file
*
* SPDX-License-Identifier: Apache-2.0
* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __I2C_REG_H__
#define __I2C_REG_H__
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
/**
@addtogroup REGISTER Control Register
@{
*/
/*---------------------- Inter-IC Bus Controller -------------------------*/
/**
@addtogroup I2C Inter-IC Bus Controller(I2C)
Memory Mapped Structure for I2C Controller
@{ */
typedef struct
{
/**
* @var I2C_T::CTL0
* Offset: 0x00 I2C Control Register 0
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[2] |AA |Assert Acknowledge Control
* | | |When AA =1 prior to address or data is received, an acknowledged (low level to SDA) will be returned during the acknowledge clock pulse on the SCL line when (1) A slave is acknowledging the address sent from master, (2) The receiver devices are acknowledging the data sent by transmitter
* | | |When AA=0 prior to address or data received, a Not acknowledged (high level to SDA) will be returned during the acknowledge clock pulse on the SCL line
* |[3] |SI |I2C Interrupt Flag
* | | |When a new I2C state is present in the I2C_STATUS0 register, the SI flag is set by hardware
* | | |If bit INTEN (I2C_CTL0 [7]) is set, the I2C interrupt is requested
* | | |SI must be cleared by software
* | | |Clear SI by writing 1 to this bit.
* | | |For ACKMEN is set in slave read mode, the SI flag is set in 8th clock period for user to confirm the acknowledge bit and 9th clock period for user to read the data in the data buffer.
* |[4] |STO |I2C STOP Control
* | | |In Master mode, setting STO to transmit a STOP condition to bus then I2C controller will check the bus condition if a STOP condition is detected
* | | |This bit will be cleared by hardware automatically.
* |[5] |STA |I2C START Control
* | | |Setting STA to logic 1 to enter Master mode, the I2C hardware sends a START or Repeat START condition to bus when the bus is free.
* |[6] |I2CEN |I2C Controller Enable Bit
* | | |Set to enable I2C serial function controller
* | | |When I2CEN=1 the I2C serial function enable
* | | |The multi-function pin function must set to SDA, and SCL of I2C function first.
* | | |0 = I2C controller Disabled.
* | | |1 = I2C controller Enabled.
* |[7] |INTEN |Enable Interrupt
* | | |0 = I2C interrupt Disabled.
* | | |1 = I2C interrupt Enabled.
* @var I2C_T::ADDR0
* Offset: 0x04 I2C Slave Address Register0
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |GC |General Call Function
* | | |0 = General Call Function Disabled.
* | | |1 = General Call Function Enabled.
* |[10:1] |ADDR |I2C Address
* | | |The content of this register is irrelevant when I2C is in Master mode
* | | |In the slave mode, the seven most significant bits must be loaded with the chipu2019s own address
* | | |The I2C hardware will react if either of the address is matched.
* | | |Note: When software set 10'h000, the address cannot be used.
* @var I2C_T::DAT
* Offset: 0x08 I2C Data Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |DAT |I2C Data
* | | |Bit [7:0] is located with the 8-bit transferred/received data of I2C serial port.
* @var I2C_T::STATUS0
* Offset: 0x0C I2C Status Register 0
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |STATUS |I2C Status
* | | |The three least significant bits are always 0
* | | |The five most significant bits contain the status code
* | | |There are 28 possible status codes
* | | |When the content of I2C_STATUS0 is F8H, no serial interrupt is requested
* | | |Others I2C_STATUS0 values correspond to defined I2C states
* | | |When each of these states is entered, a status interrupt is requested (SI = 1)
* | | |A valid status code is present in I2C_STATUS0 one cycle after SI is set by hardware and is still present one cycle after SI has been reset by software
* | | |In addition, states 00H stands for a Bus Error
* | | |A Bus Error occurs when a START or STOP condition is present at an illegal position in the formation frame
* | | |Example of illegal position are during the serial transfer of an address byte, a data byte or an acknowledge bit.
* @var I2C_T::CLKDIV
* Offset: 0x10 I2C Clock Divided Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[9:0] |DIVIDER |I2C Clock Divided
* | | |Indicates the I2C clock rate: Data Baud Rate of I2C = (system clock) / (4x (I2C_CLKDIV+1)).
* | | |Note: The minimum value of I2C_CLKDIV is 4.
* |[15:12] |NFCNT |Noise Filter Count
* | | |The bits control the input filter width.
* | | |0 = Filter width 3*PCLK
* | | |1 = Filter width 4*PCLK
* | | |N = Filter width (3+N)*PCKL
* | | |Note: Filter width Min :3*PCLK, Max : 18*PCLK
* @var I2C_T::TOCTL
* Offset: 0x14 I2C Time-out Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |TOIF |Time-out Flag
* | | |This bit is set by hardware when I2C time-out happened and it can interrupt CPU if I2C interrupt enable bit (INTEN) is set to 1.
* | | |Note: Software can write 1 to clear this bit.
* |[1] |TOCDIV4 |Time-out Counter Input Clock Divided by 4
* | | |When enabled, the time-out period is extended 4 times.
* | | |0 = Time-out period is extend 4 times Disabled.
* | | |1 = Time-out period is extend 4 times Enabled.
* |[2] |TOCEN |Time-out Counter Enable Bit
* | | |When enabled, the 14-bit time-out counter will start counting when SI is cleared
* | | |Setting flag SI to '1' will reset counter and re-start up counting after SI is cleared.
* | | |0 = Time-out counter Disabled.
* | | |1 = Time-out counter Enabled.
* @var I2C_T::ADDR1
* Offset: 0x18 I2C Slave Address Register1
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |GC |General Call Function
* | | |0 = General Call Function Disabled.
* | | |1 = General Call Function Enabled.
* |[10:1] |ADDR |I2C Address
* | | |The content of this register is irrelevant when I2C is in Master mode
* | | |In the slave mode, the seven most significant bits must be loaded with the chip's own address
* | | |The I2C hardware will react if either of the address is matched.
* | | |Note: When software set 10'h000, the address cannot be used.
* @var I2C_T::ADDR2
* Offset: 0x1C I2C Slave Address Register2
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |GC |General Call Function
* | | |0 = General Call Function Disabled.
* | | |1 = General Call Function Enabled.
* |[10:1] |ADDR |I2C Address
* | | |The content of this register is irrelevant when I2C is in Master mode
* | | |In the slave mode, the seven most significant bits must be loaded with the chip's own address
* | | |The I2C hardware will react if either of the address is matched.
* | | |Note: When software set 10'h000, the address cannot be used.
* @var I2C_T::ADDR3
* Offset: 0x20 I2C Slave Address Register3
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |GC |General Call Function
* | | |0 = General Call Function Disabled.
* | | |1 = General Call Function Enabled.
* |[10:1] |ADDR |I2C Address
* | | |The content of this register is irrelevant when I2C is in Master mode
* | | |In the slave mode, the seven most significant bits must be loaded with the chip's own address
* | | |The I2C hardware will react if either of the address is matched.
* | | |Note: When software set 10'h000, the address cannot be used.
* @var I2C_T::ADDRMSK0
* Offset: 0x24 I2C Slave Address Mask Register0
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[10:1] |ADDRMSK |I2C Address Mask
* | | |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.).
* | | |1 = Mask Enabled (the received corresponding address bit is don't care.).
* | | |I2C bus controllers support multiple address recognition with four address mask register
* | | |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care
* | | |If the bit is set to 0, that means the received corresponding register bit should be exact the same as address register.
* | | |Note: The wake-up function cannot use address mask.
* @var I2C_T::ADDRMSK1
* Offset: 0x28 I2C Slave Address Mask Register1
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[10:1] |ADDRMSK |I2C Address Mask
* | | |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.).
* | | |1 = Mask Enabled (the received corresponding address bit is don't care.).
* | | |I2C bus controllers support multiple address recognition with four address mask register
* | | |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care
* | | |If the bit is set to 0, that means the received corresponding register bit should be exact the same as address register.
* | | |Note: The wake-up function cannot use address mask.
* @var I2C_T::ADDRMSK2
* Offset: 0x2C I2C Slave Address Mask Register2
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[10:1] |ADDRMSK |I2C Address Mask
* | | |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.).
* | | |1 = Mask Enabled (the received corresponding address bit is don't care.).
* | | |I2C bus controllers support multiple address recognition with four address mask register
* | | |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care
* | | |If the bit is set to 0, that means the received corresponding register bit should be exact the same as address register.
* | | |Note: The wake-up function cannot use address mask.
* @var I2C_T::ADDRMSK3
* Offset: 0x30 I2C Slave Address Mask Register3
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[10:1] |ADDRMSK |I2C Address Mask
* | | |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.).
* | | |1 = Mask Enabled (the received corresponding address bit is don't care.).
* | | |I2C bus controllers support multiple address recognition with four address mask register
* | | |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care
* | | |If the bit is set to 0, that means the received corresponding register bit should be exact the same as address register.
* | | |Note: The wake-up function cannot use address mask.
* @var I2C_T::WKCTL
* Offset: 0x3C I2C Wake-up Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |WKEN |I2C Wake-up Enable Bit
* | | |0 = I2C wake-up function Disabled.
* | | |1= I2C wake-up function Enabled.
* |[7] |NHDBUSEN |I2C No Hold BUS Enable Bit
* | | |0 = I2C hold bus after wake-up.
* | | |1= I2C don't hold bus after wake-up.
* | | |Note: The I2C controller could respond when WKIF event is not clear, it may cause error data transmitted or received
* | | |If data transmitted or received when WKIF event is not clear, user must reset I2C controller and execute the original operation again.
* @var I2C_T::WKSTS
* Offset: 0x40 I2C Wake-up Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |WKIF |I2C Wake-up Flag
* | | |When chip is woken up from Power-down mode by I2C, this bit is set to 1
* | | |Software can write 1 to clear this bit.
* |[1] |WKAKDONE |Wakeup Address Frame Acknowledge Bit Done
* | | |0 = The ACK bit cycle of address match frame isn't done.
* | | |1 = The ACK bit cycle of address match frame is done in power down.
* | | |Note: This bit can't release WKIF. Software can write 1 to clear this bit.
* |[2] |WRSTSWK |Read/Write Status Bit in Address Wakeup Frame
* | | |0 = Write command be record on the address match wakeup frame.
* | | |1 = Read command be record on the address match wakeup frame.
* | | |Note: This bit will be cleared when software can write 1 to WKAKDONE bit.
* @var I2C_T::CTL1
* Offset: 0x44 I2C Control Register 1
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |TXPDMAEN |PDMA Transmit Channel Available
* | | |0 = Transmit PDMA function Disabled.
* | | |1 = Transmit PDMA function Enabled.
* |[1] |RXPDMAEN |PDMA Receive Channel Available
* | | |0 = Receive PDMA function Disabled.
* | | |1 = Receive PDMA function Enabled.
* |[2] |PDMARST |PDMA Reset
* | | |0 = No effect.
* | | |1 = Reset the I2C request to PDMA.
* |[8] |PDMASTR |PDMA Stretch Bit
* | | |0 = I2C send STOP automatically after PDMA transfer done. (only master TX)
* | | |1 = I2C SCL bus is stretched by hardware after PDMA transfer done if the SI is not cleared
* | | |(only master TX)
* |[9] |ADDR10EN |Address 10-bit Function Enable Bit
* | | |0 = Address match 10-bit function Disabled.
* | | |1 = Address match 10-bit function Enabled.
* @var I2C_T::STATUS1
* Offset: 0x48 I2C Status Register 1
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |ADMAT0 |I2C Address 0 Match Status
* | | |When address 0 is matched, hardware will inform which address used
* | | |This bit will set to 1, and software can write 1 to clear this bit.
* |[1] |ADMAT1 |I2C Address 1 Match Status
* | | |When address 1 is matched, hardware will inform which address used
* | | |This bit will set to 1, and software can write 1 to clear this bit.
* |[2] |ADMAT2 |I2C Address 2 Match Status
* | | |When address 2 is matched, hardware will inform which address used
* | | |This bit will set to 1, and software can write 1 to clear this bit.
* |[3] |ADMAT3 |I2C Address 3 Match Status
* | | |When address 3 is matched, hardware will inform which address used
* | | |This bit will set to 1, and software can write 1 to clear this bit.
* |[16] |RXPDMAERR |RX PDMA ERROR Status
* | | |When RX PDMA is busy and received fail data
* | | |This bit will set to 1, and software can write 1 to clear this bit.
* | | |0 = PDMA receive data correct.
* | | |1 = PDMA receive data failed.
* | | |Note: This bit is vaild when RXPDMAEN (I2C_CTL1[1]) is enabled.
* @var I2C_T::TMCTL
* Offset: 0x4C I2C Timing Configure Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[24:16] |HTCTL |Hold Time Configure Control
* | | |This field is used to generate the delay timing between SCL falling edge and SDA rising edge in transmission mode.
* | | |The delay hold time is numbers of peripheral clock = HTCTL x PCLK.
*/
__IO uint32_t CTL0; /*!< [0x0000] I2C Control Register 0 */
__IO uint32_t ADDR0; /*!< [0x0004] I2C Slave Address Register0 */
__IO uint32_t DAT; /*!< [0x0008] I2C Data Register */
__I uint32_t STATUS0; /*!< [0x000c] I2C Status Register 0 */
__IO uint32_t CLKDIV; /*!< [0x0010] I2C Clock Divided Register */
__IO uint32_t TOCTL; /*!< [0x0014] I2C Time-out Control Register */
__IO uint32_t ADDR1; /*!< [0x0018] I2C Slave Address Register1 */
__IO uint32_t ADDR2; /*!< [0x001c] I2C Slave Address Register2 */
__IO uint32_t ADDR3; /*!< [0x0020] I2C Slave Address Register3 */
__IO uint32_t ADDRMSK0; /*!< [0x0024] I2C Slave Address Mask Register0 */
__IO uint32_t ADDRMSK1; /*!< [0x0028] I2C Slave Address Mask Register1 */
__IO uint32_t ADDRMSK2; /*!< [0x002c] I2C Slave Address Mask Register2 */
__IO uint32_t ADDRMSK3; /*!< [0x0030] I2C Slave Address Mask Register3 */
__I uint32_t RESERVE0[2];
__IO uint32_t WKCTL; /*!< [0x003c] I2C Wake-up Control Register */
__IO uint32_t WKSTS; /*!< [0x0040] I2C Wake-up Status Register */
__IO uint32_t CTL1; /*!< [0x0044] I2C Control Register 1 */
__IO uint32_t STATUS1; /*!< [0x0048] I2C Status Register 1 */
__IO uint32_t TMCTL; /*!< [0x004c] I2C Timing Configure Control Register */
} I2C_T;
/**
@addtogroup I2C_CONST I2C Bit Field Definition
Constant Definitions for I2C Controller
@{ */
#define I2C_CTL0_AA_Pos (2) /*!< I2C_T::CTL0: AA Position */
#define I2C_CTL0_AA_Msk (0x1ul << I2C_CTL0_AA_Pos) /*!< I2C_T::CTL0: AA Mask */
#define I2C_CTL0_SI_Pos (3) /*!< I2C_T::CTL0: SI Position */
#define I2C_CTL0_SI_Msk (0x1ul << I2C_CTL0_SI_Pos) /*!< I2C_T::CTL0: SI Mask */
#define I2C_CTL0_STO_Pos (4) /*!< I2C_T::CTL0: STO Position */
#define I2C_CTL0_STO_Msk (0x1ul << I2C_CTL0_STO_Pos) /*!< I2C_T::CTL0: STO Mask */
#define I2C_CTL0_STA_Pos (5) /*!< I2C_T::CTL0: STA Position */
#define I2C_CTL0_STA_Msk (0x1ul << I2C_CTL0_STA_Pos) /*!< I2C_T::CTL0: STA Mask */
#define I2C_CTL0_I2CEN_Pos (6) /*!< I2C_T::CTL0: I2CEN Position */
#define I2C_CTL0_I2CEN_Msk (0x1ul << I2C_CTL0_I2CEN_Pos) /*!< I2C_T::CTL0: I2CEN Mask */
#define I2C_CTL0_INTEN_Pos (7) /*!< I2C_T::CTL0: INTEN Position */
#define I2C_CTL0_INTEN_Msk (0x1ul << I2C_CTL0_INTEN_Pos) /*!< I2C_T::CTL0: INTEN Mask */
#define I2C_ADDR0_GC_Pos (0) /*!< I2C_T::ADDR0: GC Position */
#define I2C_ADDR0_GC_Msk (0x1ul << I2C_ADDR0_GC_Pos) /*!< I2C_T::ADDR0: GC Mask */
#define I2C_ADDR0_ADDR_Pos (1) /*!< I2C_T::ADDR0: ADDR Position */
#define I2C_ADDR0_ADDR_Msk (0x3fful << I2C_ADDR0_ADDR_Pos) /*!< I2C_T::ADDR0: ADDR Mask */
#define I2C_DAT_DAT_Pos (0) /*!< I2C_T::DAT: DAT Position */
#define I2C_DAT_DAT_Msk (0xfful << I2C_DAT_DAT_Pos) /*!< I2C_T::DAT: DAT Mask */
#define I2C_STATUS0_STATUS_Pos (0) /*!< I2C_T::STATUS0: STATUS Position */
#define I2C_STATUS0_STATUS_Msk (0xfful << I2C_STATUS0_STATUS_Pos) /*!< I2C_T::STATUS0: STATUS Mask */
#define I2C_CLKDIV_DIVIDER_Pos (0) /*!< I2C_T::CLKDIV: DIVIDER Position */
#define I2C_CLKDIV_DIVIDER_Msk (0x3fful << I2C_CLKDIV_DIVIDER_Pos) /*!< I2C_T::CLKDIV: DIVIDER Mask */
#define I2C_CLKDIV_NFCNT_Pos (12) /*!< I2C_T::CLKDIV: NFCNT Position */
#define I2C_CLKDIV_NFCNT_Msk (0xful << I2C_CLKDIV_NFCNT_Pos) /*!< I2C_T::CLKDIV: NFCNT Mask */
#define I2C_TOCTL_TOIF_Pos (0) /*!< I2C_T::TOCTL: TOIF Position */
#define I2C_TOCTL_TOIF_Msk (0x1ul << I2C_TOCTL_TOIF_Pos) /*!< I2C_T::TOCTL: TOIF Mask */
#define I2C_TOCTL_TOCDIV4_Pos (1) /*!< I2C_T::TOCTL: TOCDIV4 Position */
#define I2C_TOCTL_TOCDIV4_Msk (0x1ul << I2C_TOCTL_TOCDIV4_Pos) /*!< I2C_T::TOCTL: TOCDIV4 Mask */
#define I2C_TOCTL_TOCEN_Pos (2) /*!< I2C_T::TOCTL: TOCEN Position */
#define I2C_TOCTL_TOCEN_Msk (0x1ul << I2C_TOCTL_TOCEN_Pos) /*!< I2C_T::TOCTL: TOCEN Mask */
#define I2C_ADDR1_GC_Pos (0) /*!< I2C_T::ADDR1: GC Position */
#define I2C_ADDR1_GC_Msk (0x1ul << I2C_ADDR1_GC_Pos) /*!< I2C_T::ADDR1: GC Mask */
#define I2C_ADDR1_ADDR_Pos (1) /*!< I2C_T::ADDR1: ADDR Position */
#define I2C_ADDR1_ADDR_Msk (0x3fful << I2C_ADDR1_ADDR_Pos) /*!< I2C_T::ADDR1: ADDR Mask */
#define I2C_ADDR2_GC_Pos (0) /*!< I2C_T::ADDR2: GC Position */
#define I2C_ADDR2_GC_Msk (0x1ul << I2C_ADDR2_GC_Pos) /*!< I2C_T::ADDR2: GC Mask */
#define I2C_ADDR2_ADDR_Pos (1) /*!< I2C_T::ADDR2: ADDR Position */
#define I2C_ADDR2_ADDR_Msk (0x3fful << I2C_ADDR2_ADDR_Pos) /*!< I2C_T::ADDR2: ADDR Mask */
#define I2C_ADDR3_GC_Pos (0) /*!< I2C_T::ADDR3: GC Position */
#define I2C_ADDR3_GC_Msk (0x1ul << I2C_ADDR3_GC_Pos) /*!< I2C_T::ADDR3: GC Mask */
#define I2C_ADDR3_ADDR_Pos (1) /*!< I2C_T::ADDR3: ADDR Position */
#define I2C_ADDR3_ADDR_Msk (0x3fful << I2C_ADDR3_ADDR_Pos) /*!< I2C_T::ADDR3: ADDR Mask */
#define I2C_ADDRMSK0_ADDRMSK_Pos (1) /*!< I2C_T::ADDRMSK0: ADDRMSK Position */
#define I2C_ADDRMSK0_ADDRMSK_Msk (0x3fful << I2C_ADDRMSK0_ADDRMSK_Pos) /*!< I2C_T::ADDRMSK0: ADDRMSK Mask */
#define I2C_ADDRMSK1_ADDRMSK_Pos (1) /*!< I2C_T::ADDRMSK1: ADDRMSK Position */
#define I2C_ADDRMSK1_ADDRMSK_Msk (0x3fful << I2C_ADDRMSK1_ADDRMSK_Pos) /*!< I2C_T::ADDRMSK1: ADDRMSK Mask */
#define I2C_ADDRMSK2_ADDRMSK_Pos (1) /*!< I2C_T::ADDRMSK2: ADDRMSK Position */
#define I2C_ADDRMSK2_ADDRMSK_Msk (0x3fful << I2C_ADDRMSK2_ADDRMSK_Pos) /*!< I2C_T::ADDRMSK2: ADDRMSK Mask */
#define I2C_ADDRMSK3_ADDRMSK_Pos (1) /*!< I2C_T::ADDRMSK3: ADDRMSK Position */
#define I2C_ADDRMSK3_ADDRMSK_Msk (0x3fful << I2C_ADDRMSK3_ADDRMSK_Pos) /*!< I2C_T::ADDRMSK3: ADDRMSK Mask */
#define I2C_WKCTL_WKEN_Pos (0) /*!< I2C_T::WKCTL: WKEN Position */
#define I2C_WKCTL_WKEN_Msk (0x1ul << I2C_WKCTL_WKEN_Pos) /*!< I2C_T::WKCTL: WKEN Mask */
#define I2C_WKCTL_NHDBUSEN_Pos (7) /*!< I2C_T::WKCTL: NHDBUSEN Position */
#define I2C_WKCTL_NHDBUSEN_Msk (0x1ul << I2C_WKCTL_NHDBUSEN_Pos) /*!< I2C_T::WKCTL: NHDBUSEN Mask */
#define I2C_WKSTS_WKIF_Pos (0) /*!< I2C_T::WKSTS: WKIF Position */
#define I2C_WKSTS_WKIF_Msk (0x1ul << I2C_WKSTS_WKIF_Pos) /*!< I2C_T::WKSTS: WKIF Mask */
#define I2C_WKSTS_WKAKDONE_Pos (1) /*!< I2C_T::WKSTS: WKAKDONE Position */
#define I2C_WKSTS_WKAKDONE_Msk (0x1ul << I2C_WKSTS_WKAKDONE_Pos) /*!< I2C_T::WKSTS: WKAKDONE Mask */
#define I2C_WKSTS_WRSTSWK_Pos (2) /*!< I2C_T::WKSTS: WRSTSWK Position */
#define I2C_WKSTS_WRSTSWK_Msk (0x1ul << I2C_WKSTS_WRSTSWK_Pos) /*!< I2C_T::WKSTS: WRSTSWK Mask */
#define I2C_CTL1_TXPDMAEN_Pos (0) /*!< I2C_T::CTL1: TXPDMAEN Position */
#define I2C_CTL1_TXPDMAEN_Msk (0x1ul << I2C_CTL1_TXPDMAEN_Pos) /*!< I2C_T::CTL1: TXPDMAEN Mask */
#define I2C_CTL1_RXPDMAEN_Pos (1) /*!< I2C_T::CTL1: RXPDMAEN Position */
#define I2C_CTL1_RXPDMAEN_Msk (0x1ul << I2C_CTL1_RXPDMAEN_Pos) /*!< I2C_T::CTL1: RXPDMAEN Mask */
#define I2C_CTL1_PDMARST_Pos (2) /*!< I2C_T::CTL1: PDMARST Position */
#define I2C_CTL1_PDMARST_Msk (0x1ul << I2C_CTL1_PDMARST_Pos) /*!< I2C_T::CTL1: PDMARST Mask */
#define I2C_CTL1_PDMASTR_Pos (8) /*!< I2C_T::CTL1: PDMASTR Position */
#define I2C_CTL1_PDMASTR_Msk (0x1ul << I2C_CTL1_PDMASTR_Pos) /*!< I2C_T::CTL1: PDMASTR Mask */
#define I2C_CTL1_ADDR10EN_Pos (9) /*!< I2C_T::CTL1: ADDR10EN Position */
#define I2C_CTL1_ADDR10EN_Msk (0x1ul << I2C_CTL1_ADDR10EN_Pos) /*!< I2C_T::CTL1: ADDR10EN Mask */
#define I2C_STATUS1_ADMAT0_Pos (0) /*!< I2C_T::STATUS1: ADMAT0 Position */
#define I2C_STATUS1_ADMAT0_Msk (0x1ul << I2C_STATUS1_ADMAT0_Pos) /*!< I2C_T::STATUS1: ADMAT0 Mask */
#define I2C_STATUS1_ADMAT1_Pos (1) /*!< I2C_T::STATUS1: ADMAT1 Position */
#define I2C_STATUS1_ADMAT1_Msk (0x1ul << I2C_STATUS1_ADMAT1_Pos) /*!< I2C_T::STATUS1: ADMAT1 Mask */
#define I2C_STATUS1_ADMAT2_Pos (2) /*!< I2C_T::STATUS1: ADMAT2 Position */
#define I2C_STATUS1_ADMAT2_Msk (0x1ul << I2C_STATUS1_ADMAT2_Pos) /*!< I2C_T::STATUS1: ADMAT2 Mask */
#define I2C_STATUS1_ADMAT3_Pos (3) /*!< I2C_T::STATUS1: ADMAT3 Position */
#define I2C_STATUS1_ADMAT3_Msk (0x1ul << I2C_STATUS1_ADMAT3_Pos) /*!< I2C_T::STATUS1: ADMAT3 Mask */
#define I2C_STATUS1_RXPDMAERR_Pos (16) /*!< I2C_T::STATUS1: RXPDMAERR Position */
#define I2C_STATUS1_RXPDMAERR_Msk (0x1ul << I2C_STATUS1_RXPDMAERR_Pos) /*!< I2C_T::STATUS1: RXPDMAERR Mask */
#define I2C_TMCTL_HTCTL_Pos (16) /*!< I2C_T::TMCTL: HTCTL Position */
#define I2C_TMCTL_HTCTL_Msk (0x1fful << I2C_TMCTL_HTCTL_Pos) /*!< I2C_T::TMCTL: HTCTL Mask */
/**@}*/ /* I2C_CONST */
/**@}*/ /* end of I2C register group */
/**@}*/ /* end of REGISTER group */
#if defined ( __CC_ARM )
#pragma no_anon_unions
#endif
#endif /* __I2C_REG_H__ */

704
bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/i2s_reg.h Normal file
View File

@ -0,0 +1,704 @@
/**************************************************************************//**
* @file i2s_reg.h
* @brief I2S register definition header file
*
* SPDX-License-Identifier: Apache-2.0
* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __I2S_REG_H__
#define __I2S_REG_H__
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
/**
@addtogroup REGISTER Control Register
@{
*/
/**
@addtogroup I2S I2S Interface Controller(I2S)
Memory Mapped Structure for I2S Controller
@{ */
typedef struct
{
/**
* @var I2S_T::CTL0
* Offset: 0x00 I2S Control Register 0
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |I2SEN |I2S Controller Enable Bit
* | | |0 = I2S controller Disabled.
* | | |1 = I2S controller Enabled.
* |[1] |TXEN |Transmit Enable Bit
* | | |0 = Data transmission Disabled.
* | | |1 = Data transmission Enabled.
* |[2] |RXEN |Receive Enable Bit
* | | |0 = Data receiving Disabled.
* | | |1 = Data receiving Enabled.
* |[3] |MUTE |Transmit Mute Enable Bit
* | | |0 = Transmit data is shifted from buffer.
* | | |1 = Send zero on transmit channel.
* |[5:4] |DATWIDTH |Data Width
* | | |This bit field is used to define the bit-width of data word in each audio channel
* | | |00 = The bit-width of data word is 8-bit.
* | | |01 = The bit-width of data word is 16-bit.
* | | |10 = The bit-width of data word is 24-bit.
* | | |11 = The bit-width of data word is 32-bit.
* |[6] |MONO |Monaural Data Control
* | | |0 = Data is stereo format.
* | | |1 = Data is monaural format.
* | | |Note: When chip records data, RXLCH (I2S_CTL0[23]) indicates which channel data will be saved if monaural format is selected.
* |[7] |ORDER |Stereo Data Order in FIFO
* | | |In 8-bit/16-bit data width, this bit is used to select whether the even or odd channel data is stored in higher byte
* | | |In 24-bit data width, this is used to select the left/right alignment method of audio data which is stored in data memory consisted of 32-bit FIFO entries.
* | | |0 = Even channel data at high byte in 8-bit/16-bit data width.
* | | |LSB of 24-bit audio data in each channel is aligned to right side in 32-bit FIFO entries.
* | | |1 = Even channel data at low byte in 8-bit/16-bit data width.
* | | |MSB of 24-bit audio data in each channel is aligned to left side in 32-bit FIFO entries.
* |[8] |SLAVE |Slave Mode Enable Bit
* | | |0 = Master mode.
* | | |1 = Slave mode.
* | | |Note: I2S can operate as master or slave
* | | |For Master mode, I2S_BCLK and I2S_LRCLK pins are output mode and send out bit clock to Audio CODEC chip
* | | |In Slave mode, I2S_BCLK and I2S_LRCLK pins are input mode and I2S_BCLK and I2S_LRCLK signals are received from outer Audio CODEC chip.
* |[15] |MCLKEN |Master Clock Enable Bit
* | | |If MCLKEN is set to 1, I2S controller will generate master clock on I2S_MCLK pin for external audio devices.
* | | |0 = Master clock Disabled.
* | | |1 = Master clock Enabled.
* |[18] |TXFBCLR |Transmit FIFO Buffer Clear
* | | |0 = No Effect.
* | | |1 = Clear TX FIFO.
* | | |Note 1: Write 1 to clear transmit FIFO, internal pointer is reset to FIFO start point, and TXCNT (I2S_STATUS1[12:8]) returns 0 and transmit FIFO becomes empty but data in transmit FIFO is not changed.
* | | |Note 2: This bit is clear by hardware automatically, read it return 0.
* |[19] |RXFBCLR |Receive FIFO Buffer Clear
* | | |0 = No Effect.
* | | |1 = Clear RX FIFO.
* | | |Note 1: Write 1 to clear receive FIFO, internal pointer is reset to FIFO start point, and RXCNT (I2S_STATUS1[20:16]) returns 0 and receive FIFO becomes empty.
* | | |Note 2: This bit is cleared by hardware automatically, read it return 0.
* |[20] |TXPDMAEN |Transmit PDMA Enable Bit
* | | |0 = Transmit PDMA function Disabled.
* | | |1 = Transmit PDMA function Enabled.
* |[21] |RXPDMAEN |Receive PDMA Enable Bit
* | | |0 = Receive PDMA function Disabled.
* | | |1 = Receive PDMA function Enabled.
* |[23] |RXLCH |Receive Left Channel Enable Bit
* | | |When monaural format is selected (MONO = 1), I2S will receive channel1 data if RXLCH is set to 0, and receive channel0 data if RXLCH is set to 1.
* | | |0 = Receive channel1 data in MONO mode.
* | | |1 = Receive channel0 data in MONO mode.
* |[26:24] |FORMAT |Data Format Selection
* | | |000 = I2S standard data format.
* | | |001 = I2S with MSB justified.
* | | |010 = I2S with LSB justified.
* | | |011 = Reserved.
* | | |100 = PCM standard data format.
* | | |101 = PCM with MSB justified.
* | | |110 = PCM with LSB justified.
* | | |111 = Reserved.
* |[27] |PCMSYNC |PCM Synchronization Pulse Length Selection
* | | |This bit field is used to select the high pulse length of frame synchronization signal in PCM protocol
* | | |0 = One BCLK period.
* | | |1 = One channel period.
* | | |Note: This bit is only available in master mode
* |[29:28] |CHWIDTH |Channel Width
* | | |This bit fields are used to define the length of audio channel
* | | |If CHWIDTH < DATWIDTH, the hardware will set the real channel length as the bit-width of audio data which is defined by DATWIDTH.
* | | |00 = The bit-width of each audio channel is 8-bit.
* | | |01 = The bit-width of each audio channel is 16-bit.
* | | |10 = The bit-width of each audio channel is 24-bit.
* | | |11 = The bit-width of each audio channel is 32-bit.
* |[31:30] |TDMCHNUM |TDM Channel Number
* | | |This bit fields are used to define the TDM channel number in one audio frame while PCM mode (FORMAT[2] = 1).
* | | |00 = 2 channels in audio frame.
* | | |01 = 4 channels in audio frame.
* | | |10 = 6 channels in audio frame.
* | | |11 = 8 channels in audio frame.
* @var I2S_T::CLKDIV
* Offset: 0x04 I2S Clock Divider Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[6:0] |MCLKDIV |Master Clock Divider
* | | |If chip external crystal frequency is (2xMCLKDIV)*256fs then software can program these bits to generate 256fs clock frequency to audio codec chip
* | | |If MCLKDIV is set to 0, MCLK is the same as external clock input.
* | | |For example, sampling rate is 24 kHz and chip external crystal clock is 12.288 MHz, set MCLKDIV = 1.
* | | |F_MCLK = F_I2SCLK/(2x(MCLKDIV)) (When MCLKDIV is >= 1).
* | | |F_MCLK = F_I2SCLK (When MCLKDIV is set to 0).
* | | |Note: F_MCLK is the frequency of MCLK, and F_I2SCLK is the frequency of the I2S_CLK
* |[17:8] |BCLKDIV |Bit Clock Divider
* | | |The I2S controller will generate bit clock in Master mode
* | | |Software can program these bit fields to generate sampling rate clock frequency.
* | | |F_BCLK= F_I2SCLK / (2*(BCLKDIV + 1)).
* | | |Note: F_BCLK is the frequency of BCLK and F_I2SCLK is the frequency of I2S_CLK
* @var I2S_T::IEN
* Offset: 0x08 I2S Interrupt Enable Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |RXUDFIEN |Receive FIFO Underflow Interrupt Enable Bit
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* | | |Note: If software reads receive FIFO when it is empty then RXUDIF (I2S_STATUS0[8]) flag is set to 1
* | | |If RXUDFIEN bit is enabled, interrupt occurs.
* |[1] |RXOVFIEN |Receive FIFO Overflow Interrupt Enable Bit
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* | | |Note: Interrupt occurs if this bit is set to 1 and RXOVIF (I2S_STATUS0[9]) flag is set to 1
* |[2] |RXTHIEN |Receive FIFO Threshold Level Interrupt Enable Bit
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* | | |Note: Interrupt occurs if this bit is set to 1 and data words in receive FIFO is larger than RXTH (I2S_CTL1[19:16]).
* |[8] |TXUDFIEN |Transmit FIFO Underflow Interrupt Enable Bit
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* | | |Note: Interrupt occur if this bit is set to 1 and TXUDIF (I2S_STATUS0[16]) flag is set to 1.
* |[9] |TXOVFIEN |Transmit FIFO Overflow Interrupt Enable Bit
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* | | |Note: Interrupt occurs if this bit is set to 1 and TXOVIF (I2S_STATUS0[17]) flag is set to 1
* |[10] |TXTHIEN |Transmit FIFO Threshold Level Interrupt Enable Bit
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* | | |Note: Interrupt occurs if this bit is set to 1 and data words in transmit FIFO is less than or equal to TXTH (I2S_CTL1[11:8]).
* |[16] |CH0ZCIEN |Channel0 Zero-cross Interrupt Enable Bit
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* | | |Note 1: Interrupt occurs if this bit is set to 1 and channel0 zero-cross
* | | |Note 2: Channel0 also means left audio channel while I2S (FORMAT[2]=0) or 2-channel PCM mode.
* |[17] |CH1ZCIEN |Channel1 Zero-cross Interrupt Enable Bit
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* | | |Note 1: Interrupt occurs if this bit is set to 1 and channel1 zero-cross
* | | |Note 2: Channel1 also means right audio channel while I2S (FORMAT[2]=0) or 2-channel PCM mode.
* |[18] |CH2ZCIEN |Channel2 Zero-cross Interrupt Enable Bit
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* | | |Note 1: Interrupt occurs if this bit is set to 1 and channel2 zero-cross
* | | |Note 2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.
* |[19] |CH3ZCIEN |Channel3 Zero-cross Interrupt Enable Bit
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* | | |Note 1: Interrupt occurs if this bit is set to 1 and channel3 zero-cross
* | | |Note 2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.
* |[20] |CH4ZCIEN |Channel4 Zero-cross Interrupt Enable Bit
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* | | |Note 1: Interrupt occurs if this bit is set to 1 and channel4 zero-cross
* | | |Note 2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x2, 0x3.
* |[21] |CH5ZCIEN |Channel5 Zero-cross Interrupt Enable Bit
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* | | |Note 1: Interrupt occurs if this bit is set to 1 and channel5 zero-cross
* | | |Note 2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x2, 0x3.
* |[22] |CH6ZCIEN |Channel6 Zero-cross Interrupt Enable Bit
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* | | |Note 1: Interrupt occurs if this bit is set to 1 and channel6 zero-cross
* | | |Note 2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x3.
* |[23] |CH7ZCIEN |Channel7 Zero-cross Interrupt Enable Bit
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* | | |Note 1: Interrupt occurs if this bit is set to 1 and channel7 zero-cross
* | | |Note 2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x3.
* @var I2S_T::STATUS0
* Offset: 0x0C I2S Status Register 0
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |I2SINT |I2S Interrupt Flag (Read Only)
* | | |0 = No I2S interrupt.
* | | |1 = I2S interrupt.
* | | |Note: It is wire-OR of I2STXINT and I2SRXINT bits.
* |[1] |I2SRXINT |I2S Receive Interrupt (Read Only)
* | | |0 = No receive interrupt.
* | | |1 = Receive interrupt.
* |[2] |I2STXINT |I2S Transmit Interrupt (Read Only)
* | | |0 = No transmit interrupt.
* | | |1 = Transmit interrupt.
* |[5:3] |DATACH |Transmission Data Channel (Read Only)
* | | |This bit fields are used to indicate which audio channel is current transmit data belong.
* | | |000 = channel0 (means left channel while 2-channel I2S/PCM mode).
* | | |001 = channel1 (means right channel while 2-channel I2S/PCM mode).
* | | |010 = channel2 (available while 4-channel TDM PCM mode).
* | | |011 = channel3 (available while 4-channel TDM PCM mode).
* | | |100 = channel4 (available while 6-channel TDM PCM mode).
* | | |101 = channel5 (available while 6-channel TDM PCM mode).
* | | |110 = channel6 (available while 8-channel TDM PCM mode).
* | | |111 = channel7 (available while 8-channel TDM PCM mode).
* |[8] |RXUDIF |Receive FIFO Underflow Interrupt Flag
* | | |0 = No underflow occur.
* | | |1 = Underflow occur.
* | | |Note 1: When receive FIFO is empty, and software reads the receive FIFO again
* | | |This bit will be set to 1, and it indicates underflow situation occurs.
* | | |Note 2: Write 1 to clear this bit to 0
* |[9] |RXOVIF |Receive FIFO Overflow Interrupt Flag
* | | |0 = No overflow occur.
* | | |1 = Overflow occur.
* | | |Note 1: When receive FIFO is full and receive hardware attempt to write data into receive FIFO then this bit is set to 1, data in 1st buffer is overwritten.
* | | |Note 2: Write 1 to clear this bit to 0.
* |[10] |RXTHIF |Receive FIFO Threshold Interrupt Flag (Read Only)
* | | |0 = Data word(s) in FIFO is less than or equal to threshold level.
* | | |1 = Data word(s) in FIFO is larger than threshold level.
* | | |Note: When data word(s) in receive FIFO is larger than threshold value set in RXTH (I2S_CTL1[19:16]) the RXTHIF bit becomes to 1
* | | |It keeps at 1 till RXCNT (I2S_STATUS1[20:16]) is less than or equal to RXTH (I2S_CTL1[19:16]) after software read RXFIFO register.
* |[11] |RXFULL |Receive FIFO Full (Read Only)
* | | |0 = Not full.
* | | |1 = Full.
* | | |Note: This bit reflects data words number in receive FIFO is 16.
* |[12] |RXEMPTY |Receive FIFO Empty (Read Only)
* | | |0 = Not empty.
* | | |1 = Empty.
* | | |Note: This bit reflects data words number in receive FIFO is 0.
* |[16] |TXUDIF |Transmit FIFO Underflow Interrupt Flag
* | | |0 = No underflow.
* | | |1 = Underflow.
* | | |Note 1: This bit will be set to 1 when shift logic hardware read data from transmitting FIFO and the filling data level in transmitting FIFO is not enough for one audio frame.
* | | |Note 2: Write 1 to clear this bit to 0.
* |[17] |TXOVIF |Transmit FIFO Overflow Interrupt Flag
* | | |0 = No overflow.
* | | |1 = Overflow.
* | | |Note 1: Write data to transmit FIFO when it is full and this bit set to 1
* | | |Note 2: Write 1 to clear this bit to 0.
* |[18] |TXTHIF |Transmit FIFO Threshold Interrupt Flag (Read Only)
* | | |0 = Data word(s) in FIFO is larger than threshold level.
* | | |1 = Data word(s) in FIFO is less than or equal to threshold level.
* | | |Note: When data word(s) in transmit FIFO is less than or equal to threshold value set in TXTH (I2S_CTL1[11:8]) the TXTHIF bit becomes to 1
* | | |It keeps at 1 till TXCNT (I2S_STATUS1[12:8]) is larger than TXTH (I2S_CTL1[11:8]) after software write TXFIFO register.
* |[19] |TXFULL |Transmit FIFO Full (Read Only)
* | | |This bit reflect data word number in transmit FIFO is 16
* | | |0 = Not full.
* | | |1 = Full.
* |[20] |TXEMPTY |Transmit FIFO Empty (Read Only)
* | | |This bit reflect data word number in transmit FIFO is 0
* | | |0 = Not empty.
* | | |1 = Empty.
* |[21] |TXBUSY |Transmit Busy (Read Only)
* | | |0 = Transmit shift buffer is empty.
* | | |1 = Transmit shift buffer is busy.
* | | |Note: This bit is cleared to 0 when all data in transmit FIFO and shift buffer is shifted out
* | | |And set to 1 when 1st data is load to shift buffer
* @var I2S_T::TXFIFO
* Offset: 0x10 I2S Transmit FIFO Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |TXFIFO |Transmit FIFO Bits
* | | |The I2S contains 16 words (16x32 bits) data buffer for data transmit
* | | |Write data to this register to prepare data for transmit
* | | |The remaining word number is indicated by TXCNT (I2S_STATUS1[12:8]).
* @var I2S_T::RXFIFO
* Offset: 0x14 I2S Receive FIFO Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |RXFIFO |Receive FIFO Bits
* | | |I2S contains 16 words (16x32 bits) data buffer for data receive
* | | |Read this register to get data in FIFO
* | | |The remaining data word number is indicated by RXCNT (I2S_STATUS1[20:16]).
* @var I2S_T::CTL1
* Offset: 0x20 I2S Control Register 1
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |CH0ZCEN |Channel0 Zero-cross Detection Enable Bit
* | | |0 = channel0 zero-cross detect Disabled.
* | | |1 = channel0 zero-cross detect Enabled.
* | | |Note 1: Channel0 also means left audio channel while I2S (FORMAT[2]=0) or 2-channel PCM mode.
* | | |Note 2: If this bit is set to 1, when channel0 data sign bit change or next shift data bits are all 0 then CH0ZCIF(I2S_STATUS1[0]) flag is set to 1.
* | | |Note 3: If CH0ZCIF flag is set to 1, the channel0 will be mute.
* |[1] |CH1ZCEN |Channel1 Zero-cross Detect Enable Bit
* | | |0 = channel1 zero-cross detect Disabled.
* | | |1 = channel1 zero-cross detect Enabled.
* | | |Note 1: Channel1 also means right audio channel while I2S (FORMAT[2]=0) or 2-channel PCM mode.
* | | |Note 2: If this bit is set to 1, when channel1 data sign bit change or next shift data bits are all 0 then CH1ZCIF(I2S_STATUS1[1]) flag is set to 1.
* | | |Note 3: If CH1ZCIF flag is set to 1, the channel1 will be mute.
* |[2] |CH2ZCEN |Channel2 Zero-cross Detect Enable Bit
* | | |0 = channel2 zero-cross detect Disabled.
* | | |1 = channel2 zero-cross detect Enabled.
* | | |Note 1: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.
* | | |Note 2: If this bit is set to 1, when channel2 data sign bit change or next shift data bits are all 0 then CH2ZCIF(I2S_STATUS1[2]) flag is set to 1.
* | | |Note 3: If CH2ZCIF flag is set to 1, the channel2 will be mute.
* |[3] |CH3ZCEN |Channel3 Zero-cross Detect Enable Bit
* | | |0 = channel3 zero-cross detect Disabled.
* | | |1 = channel3 zero-cross detect Enabled.
* | | |Note 1: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.
* | | |Note 2: If this bit is set to 1, when channel3 data sign bit change or next shift data bits are all 0 then CH3ZCIF(I2S_STATUS1[3]) flag is set to 1.
* | | |Note 3: If CH3ZCIF flag is set to 1, the channel3 will be mute.
* |[4] |CH4ZCEN |Channel4 Zero-cross Detect Enable Bit
* | | |0 = channel4 zero-cross detect Disabled.
* | | |1 = channel4 zero-cross detect Enabled.
* | | |Note 1: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x2, 0x3.
* | | |Note 2: If this bit is set to 1, when channel4 data sign bit change or next shift data bits are all 0 then CH4ZCIF(I2S_STATUS1[4]) flag is set to 1.
* | | |Note 3: If CH4ZCIF flag is set to 1, the channel4 will be mute.
* |[5] |CH5ZCEN |Channel5 Zero-cross Detect Enable Bit
* | | |0 = channel5 zero-cross detect Disabled.
* | | |1 = channel5 zero-cross detect Enabled.
* | | |Note 1: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x2, 0x3.
* | | |Note 2: If this bit is set to 1, when channel5 data sign bit change or next shift data bits are all 0 then CH5ZCIF(I2S_STATUS1[5]) flag is set to 1.
* | | |Note 3: If CH5ZCIF flag is set to 1, the channel5 will be mute.
* |[6] |CH6ZCEN |Channel6 Zero-cross Detect Enable Bit
* | | |0 = channel6 zero-cross detect Disabled.
* | | |1 = channel6 zero-cross detect Enabled.
* | | |Note 1: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x3.
* | | |Note 2: If this bit is set to 1, when channel6 data sign bit change or next shift data bits are all 0 then CH6ZCIF(I2S_STATUS1[6]) flag is set to 1.
* | | |Note 3: If CH6ZCIF flag is set to 1, the channel6 will be mute.
* |[7] |CH7ZCEN |Channel7 Zero-cross Detect Enable Bit
* | | |0 = channel7 zero-cross detect Disabled.
* | | |1 = channel7 zero-cross detect Enabled.
* | | |Note 1: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x3.
* | | |Note 2: If this bit is set to 1, when channel7 data sign bit change or next shift data bits are all 0 then CH7ZCIF (I2S_STATUS1[7]) flag is set to 1.
* | | |Note 3: If CH7ZCIF flag is set to 1, the channel7 will be mute.
* |[11:8] |TXTH |Transmit FIFO Threshold Level
* | | |0000 = 0 data word in transmit FIFO.
* | | |0001 = 1 data word in transmit FIFO.
* | | |0010 = 2 data words in transmit FIFO.
* | | |....
* | | |1110 = 14 data words in transmit FIFO.
* | | |1111 = 15 data words in transmit FIFO.
* | | |Note: If remain data word number in transmit FIFO is less than or equal to threshold level then TXTHIF (I2S_STATUS0[18]) flag is set.
* |[19:16] |RXTH |Receive FIFO Threshold Level
* | | |0000 = 1 data word in receive FIFO.
* | | |0001 = 2 data words in receive FIFO.
* | | |0010 = 3 data words in receive FIFO.
* | | |....
* | | |1110 = 15 data words in receive FIFO.
* | | |1111 = 16 data words in receive FIFO.
* | | |Note: When received data word number in receive buffer is larger than threshold level then RXTHIF (I2S_STATUS0[10]) flag is set.
* |[24] |PBWIDTH |Peripheral Bus Data Width Selection
* | | |This bit is used to choice the available data width of APB bus
* | | |It must be set to 1 while PDMA function is enable and it is set to 16-bit transmission mode
* | | |0 = 32 bits data width.
* | | |1 = 16 bits data width.
* | | |Note 1: If PBWIDTH=1, the low 16 bits of 32-bit data bus are available.
* | | |Note 2: If PBWIDTH=1, the transmitting FIFO level will be increased after two FIFO write operations.
* | | |Note 3: If PBWIDTH=1, the receiving FIFO level will be decreased after two FIFO read operations.
* |[25] |PB16ORD |FIFO Read/Write Order in 16-bit Width of Peripheral Bus
* | | |When PBWIDTH = 1, the data FIFO will be increased or decreased by two peripheral bus access
* | | |This bit is used to select the order of FIFO access operations to meet the 32-bit transmitting/receiving FIFO entries.
* | | |0 = Low 16-bit read/write access first.
* | | |1 = High 16-bit read/write access first.
* | | |Note: This bit is available while PBWIDTH = 1.
* @var I2S_T::STATUS1
* Offset: 0x24 I2S Status Register 1
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |CH0ZCIF |Channel0 Zero-cross Interrupt Flag
* | | |It indicates channel0 next sample data sign bit is changed or all data bits are 0.
* | | |0 = No zero-cross in channel0.
* | | |1 = Channel0 zero-cross is detected.
* | | |Note 1: Write 1 to clear this bit to 0.
* | | |Note 2: Channel0 also means left audio channel while I2S (FORMAT[2]=0) or 2-channel PCM mode.
* |[1] |CH1ZCIF |Channel1 Zero-cross Interrupt Flag
* | | |It indicates channel1 next sample data sign bit is changed or all data bits are 0.
* | | |0 = No zero-cross in channel1.
* | | |1 = Channel1 zero-cross is detected.
* | | |Note 1: Write 1 to clear this bit to 0.
* | | |Note 2: Channel1 also means right audio channel while I2S (FORMAT[2]=0) or 2-channel PCM mode.
* |[2] |CH2ZCIF |Channel2 Zero-cross Interrupt Flag
* | | |It indicates channel2 next sample data sign bit is changed or all data bits are 0.
* | | |0 = No zero-cross in channel2.
* | | |1 = Channel2 zero-cross is detected.
* | | |Note 1: Write 1 to clear this bit to 0.
* | | |Note 2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.
* |[3] |CH3ZCIF |Channel3 Zero-cross Interrupt Flag
* | | |It indicates channel3 next sample data sign bit is changed or all data bits are 0.
* | | |0 = No zero-cross in channel3.
* | | |1 = Channel3 zero-cross is detected.
* | | |Note 1: Write 1 to clear this bit to 0.
* | | |Note 2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.
* |[4] |CH4ZCIF |Channel4 Zero-cross Interrupt Flag
* | | |It indicates channel4 next sample data sign bit is changed or all data bits are 0.
* | | |0 = No zero-cross in channel4.
* | | |1 = Channel4 zero-cross is detected.
* | | |Note 1: Write 1 to clear this bit to 0.
* | | |Note 2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x2, 0x3.
* |[5] |CH5ZCIF |Channel5 Zero-cross Interrupt Flag
* | | |It indicates channel5 next sample data sign bit is changed or all data bits are 0.
* | | |0 = No zero-cross in channel5.
* | | |1 = Channel5 zero-cross is detected.
* | | |Note 1: Write 1 to clear this bit to 0.
* | | |Note 2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x2, 0x3.
* |[6] |CH6ZCIF |Channel6 Zero-cross Interrupt Flag
* | | |It indicates channel6 next sample data sign bit is changed or all data bits are 0.
* | | |0 = No zero-cross in channel6.
* | | |1 = Channel6 zero-cross is detected.
* | | |Note 1: Write 1 to clear this bit to 0.
* | | |Note 2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x3.
* |[7] |CH7ZCIF |Channel7 Zero-cross Interrupt Flag
* | | |It indicates channel7 next sample data sign bit is changed or all data bits are 0.
* | | |0 = No zero-cross in channel7.
* | | |1 = Channel7 zero-cross is detected.
* | | |Note 1: Write 1 to clear this bit to 0.
* | | |Note 2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x3.
* |[12:8] |TXCNT |Transmit FIFO Level (Read Only)
* | | |These bits indicate the number of available entries in transmit FIFO
* | | |00000 = No data.
* | | |00001 = 1 word in transmit FIFO.
* | | |00010 = 2 words in transmit FIFO.
* | | |....
* | | |01110 = 14 words in transmit FIFO.
* | | |01111 = 15 words in transmit FIFO.
* | | |10000 = 16 words in transmit FIFO.
* | | |Others are reserved.
* |[20:16] |RXCNT |Receive FIFO Level (Read Only)
* | | |These bits indicate the number of available entries in receive FIFO
* | | |00000 = No data.
* | | |00001 = 1 word in receive FIFO.
* | | |00010 = 2 words in receive FIFO.
* | | |....
* | | |01110 = 14 words in receive FIFO.
* | | |01111 = 15 words in receive FIFO.
* | | |10000 = 16 words in receive FIFO.
* | | |Others are reserved.
*/
__IO uint32_t CTL0; /*!< [0x0000] I2S Control Register 0 */
__IO uint32_t CLKDIV; /*!< [0x0004] I2S Clock Divider Register */
__IO uint32_t IEN; /*!< [0x0008] I2S Interrupt Enable Register */
__IO uint32_t STATUS0; /*!< [0x000c] I2S Status Register 0 */
__O uint32_t TXFIFO; /*!< [0x0010] I2S Transmit FIFO Register */
__I uint32_t RXFIFO; /*!< [0x0014] I2S Receive FIFO Register */
__I uint32_t RESERVE0[2];
__IO uint32_t CTL1; /*!< [0x0020] I2S Control Register 1 */
__IO uint32_t STATUS1; /*!< [0x0024] I2S Status Register 1 */
} I2S_T;
/**
@addtogroup I2S_CONST I2S Bit Field Definition
Constant Definitions for I2S Controller
@{ */
#define I2S_CTL0_I2SEN_Pos (0) /*!< I2S_T::CTL0: I2SEN Position */
#define I2S_CTL0_I2SEN_Msk (0x1ul << I2S_CTL0_I2SEN_Pos) /*!< I2S_T::CTL0: I2SEN Mask */
#define I2S_CTL0_TXEN_Pos (1) /*!< I2S_T::CTL0: TXEN Position */
#define I2S_CTL0_TXEN_Msk (0x1ul << I2S_CTL0_TXEN_Pos) /*!< I2S_T::CTL0: TXEN Mask */
#define I2S_CTL0_RXEN_Pos (2) /*!< I2S_T::CTL0: RXEN Position */
#define I2S_CTL0_RXEN_Msk (0x1ul << I2S_CTL0_RXEN_Pos) /*!< I2S_T::CTL0: RXEN Mask */
#define I2S_CTL0_MUTE_Pos (3) /*!< I2S_T::CTL0: MUTE Position */
#define I2S_CTL0_MUTE_Msk (0x1ul << I2S_CTL0_MUTE_Pos) /*!< I2S_T::CTL0: MUTE Mask */
#define I2S_CTL0_DATWIDTH_Pos (4) /*!< I2S_T::CTL0: DATWIDTH Position */
#define I2S_CTL0_DATWIDTH_Msk (0x3ul << I2S_CTL0_DATWIDTH_Pos) /*!< I2S_T::CTL0: DATWIDTH Mask */
#define I2S_CTL0_MONO_Pos (6) /*!< I2S_T::CTL0: MONO Position */
#define I2S_CTL0_MONO_Msk (0x1ul << I2S_CTL0_MONO_Pos) /*!< I2S_T::CTL0: MONO Mask */
#define I2S_CTL0_ORDER_Pos (7) /*!< I2S_T::CTL0: ORDER Position */
#define I2S_CTL0_ORDER_Msk (0x1ul << I2S_CTL0_ORDER_Pos) /*!< I2S_T::CTL0: ORDER Mask */
#define I2S_CTL0_SLAVE_Pos (8) /*!< I2S_T::CTL0: SLAVE Position */
#define I2S_CTL0_SLAVE_Msk (0x1ul << I2S_CTL0_SLAVE_Pos) /*!< I2S_T::CTL0: SLAVE Mask */
#define I2S_CTL0_MCLKEN_Pos (15) /*!< I2S_T::CTL0: MCLKEN Position */
#define I2S_CTL0_MCLKEN_Msk (0x1ul << I2S_CTL0_MCLKEN_Pos) /*!< I2S_T::CTL0: MCLKEN Mask */
#define I2S_CTL0_TXFBCLR_Pos (18) /*!< I2S_T::CTL0: TXFBCLR Position */
#define I2S_CTL0_TXFBCLR_Msk (0x1ul << I2S_CTL0_TXFBCLR_Pos) /*!< I2S_T::CTL0: TXFBCLR Mask */
#define I2S_CTL0_RXFBCLR_Pos (19) /*!< I2S_T::CTL0: RXFBCLR Position */
#define I2S_CTL0_RXFBCLR_Msk (0x1ul << I2S_CTL0_RXFBCLR_Pos) /*!< I2S_T::CTL0: RXFBCLR Mask */
#define I2S_CTL0_TXPDMAEN_Pos (20) /*!< I2S_T::CTL0: TXPDMAEN Position */
#define I2S_CTL0_TXPDMAEN_Msk (0x1ul << I2S_CTL0_TXPDMAEN_Pos) /*!< I2S_T::CTL0: TXPDMAEN Mask */
#define I2S_CTL0_RXPDMAEN_Pos (21) /*!< I2S_T::CTL0: RXPDMAEN Position */
#define I2S_CTL0_RXPDMAEN_Msk (0x1ul << I2S_CTL0_RXPDMAEN_Pos) /*!< I2S_T::CTL0: RXPDMAEN Mask */
#define I2S_CTL0_RXLCH_Pos (23) /*!< I2S_T::CTL0: RXLCH Position */
#define I2S_CTL0_RXLCH_Msk (0x1ul << I2S_CTL0_RXLCH_Pos) /*!< I2S_T::CTL0: RXLCH Mask */
#define I2S_CTL0_FORMAT_Pos (24) /*!< I2S_T::CTL0: FORMAT Position */
#define I2S_CTL0_FORMAT_Msk (0x7ul << I2S_CTL0_FORMAT_Pos) /*!< I2S_T::CTL0: FORMAT Mask */
#define I2S_CTL0_PCMSYNC_Pos (27) /*!< I2S_T::CTL0: PCMSYNC Position */
#define I2S_CTL0_PCMSYNC_Msk (0x1ul << I2S_CTL0_PCMSYNC_Pos) /*!< I2S_T::CTL0: PCMSYNC Mask */
#define I2S_CTL0_CHWIDTH_Pos (28) /*!< I2S_T::CTL0: CHWIDTH Position */
#define I2S_CTL0_CHWIDTH_Msk (0x3ul << I2S_CTL0_CHWIDTH_Pos) /*!< I2S_T::CTL0: CHWIDTH Mask */
#define I2S_CTL0_TDMCHNUM_Pos (30) /*!< I2S_T::CTL0: TDMCHNUM Position */
#define I2S_CTL0_TDMCHNUM_Msk (0x3ul << I2S_CTL0_TDMCHNUM_Pos) /*!< I2S_T::CTL0: TDMCHNUM Mask */
#define I2S_CLKDIV_MCLKDIV_Pos (0) /*!< I2S_T::CLKDIV: MCLKDIV Position */
#define I2S_CLKDIV_MCLKDIV_Msk (0x7ful << I2S_CLKDIV_MCLKDIV_Pos) /*!< I2S_T::CLKDIV: MCLKDIV Mask */
#define I2S_CLKDIV_BCLKDIV_Pos (8) /*!< I2S_T::CLKDIV: BCLKDIV Position */
#define I2S_CLKDIV_BCLKDIV_Msk (0x3fful << I2S_CLKDIV_BCLKDIV_Pos) /*!< I2S_T::CLKDIV: BCLKDIV Mask */
#define I2S_IEN_RXUDFIEN_Pos (0) /*!< I2S_T::IEN: RXUDFIEN Position */
#define I2S_IEN_RXUDFIEN_Msk (0x1ul << I2S_IEN_RXUDFIEN_Pos) /*!< I2S_T::IEN: RXUDFIEN Mask */
#define I2S_IEN_RXOVFIEN_Pos (1) /*!< I2S_T::IEN: RXOVFIEN Position */
#define I2S_IEN_RXOVFIEN_Msk (0x1ul << I2S_IEN_RXOVFIEN_Pos) /*!< I2S_T::IEN: RXOVFIEN Mask */
#define I2S_IEN_RXTHIEN_Pos (2) /*!< I2S_T::IEN: RXTHIEN Position */
#define I2S_IEN_RXTHIEN_Msk (0x1ul << I2S_IEN_RXTHIEN_Pos) /*!< I2S_T::IEN: RXTHIEN Mask */
#define I2S_IEN_TXUDFIEN_Pos (8) /*!< I2S_T::IEN: TXUDFIEN Position */
#define I2S_IEN_TXUDFIEN_Msk (0x1ul << I2S_IEN_TXUDFIEN_Pos) /*!< I2S_T::IEN: TXUDFIEN Mask */
#define I2S_IEN_TXOVFIEN_Pos (9) /*!< I2S_T::IEN: TXOVFIEN Position */
#define I2S_IEN_TXOVFIEN_Msk (0x1ul << I2S_IEN_TXOVFIEN_Pos) /*!< I2S_T::IEN: TXOVFIEN Mask */
#define I2S_IEN_TXTHIEN_Pos (10) /*!< I2S_T::IEN: TXTHIEN Position */
#define I2S_IEN_TXTHIEN_Msk (0x1ul << I2S_IEN_TXTHIEN_Pos) /*!< I2S_T::IEN: TXTHIEN Mask */
#define I2S_IEN_CH0ZCIEN_Pos (16) /*!< I2S_T::IEN: CH0ZCIEN Position */
#define I2S_IEN_CH0ZCIEN_Msk (0x1ul << I2S_IEN_CH0ZCIEN_Pos) /*!< I2S_T::IEN: CH0ZCIEN Mask */
#define I2S_IEN_CH1ZCIEN_Pos (17) /*!< I2S_T::IEN: CH1ZCIEN Position */
#define I2S_IEN_CH1ZCIEN_Msk (0x1ul << I2S_IEN_CH1ZCIEN_Pos) /*!< I2S_T::IEN: CH1ZCIEN Mask */
#define I2S_IEN_CH2ZCIEN_Pos (18) /*!< I2S_T::IEN: CH2ZCIEN Position */
#define I2S_IEN_CH2ZCIEN_Msk (0x1ul << I2S_IEN_CH2ZCIEN_Pos) /*!< I2S_T::IEN: CH2ZCIEN Mask */
#define I2S_IEN_CH3ZCIEN_Pos (19) /*!< I2S_T::IEN: CH3ZCIEN Position */
#define I2S_IEN_CH3ZCIEN_Msk (0x1ul << I2S_IEN_CH3ZCIEN_Pos) /*!< I2S_T::IEN: CH3ZCIEN Mask */
#define I2S_IEN_CH4ZCIEN_Pos (20) /*!< I2S_T::IEN: CH4ZCIEN Position */
#define I2S_IEN_CH4ZCIEN_Msk (0x1ul << I2S_IEN_CH4ZCIEN_Pos) /*!< I2S_T::IEN: CH4ZCIEN Mask */
#define I2S_IEN_CH5ZCIEN_Pos (21) /*!< I2S_T::IEN: CH5ZCIEN Position */
#define I2S_IEN_CH5ZCIEN_Msk (0x1ul << I2S_IEN_CH5ZCIEN_Pos) /*!< I2S_T::IEN: CH5ZCIEN Mask */
#define I2S_IEN_CH6ZCIEN_Pos (22) /*!< I2S_T::IEN: CH6ZCIEN Position */
#define I2S_IEN_CH6ZCIEN_Msk (0x1ul << I2S_IEN_CH6ZCIEN_Pos) /*!< I2S_T::IEN: CH6ZCIEN Mask */
#define I2S_IEN_CH7ZCIEN_Pos (23) /*!< I2S_T::IEN: CH7ZCIEN Position */
#define I2S_IEN_CH7ZCIEN_Msk (0x1ul << I2S_IEN_CH7ZCIEN_Pos) /*!< I2S_T::IEN: CH7ZCIEN Mask */
#define I2S_STATUS0_I2SINT_Pos (0) /*!< I2S_T::STATUS0: I2SINT Position */
#define I2S_STATUS0_I2SINT_Msk (0x1ul << I2S_STATUS0_I2SINT_Pos) /*!< I2S_T::STATUS0: I2SINT Mask */
#define I2S_STATUS0_I2SRXINT_Pos (1) /*!< I2S_T::STATUS0: I2SRXINT Position */
#define I2S_STATUS0_I2SRXINT_Msk (0x1ul << I2S_STATUS0_I2SRXINT_Pos) /*!< I2S_T::STATUS0: I2SRXINT Mask */
#define I2S_STATUS0_I2STXINT_Pos (2) /*!< I2S_T::STATUS0: I2STXINT Position */
#define I2S_STATUS0_I2STXINT_Msk (0x1ul << I2S_STATUS0_I2STXINT_Pos) /*!< I2S_T::STATUS0: I2STXINT Mask */
#define I2S_STATUS0_DATACH_Pos (3) /*!< I2S_T::STATUS0: DATACH Position */
#define I2S_STATUS0_DATACH_Msk (0x7ul << I2S_STATUS0_DATACH_Pos) /*!< I2S_T::STATUS0: DATACH Mask */
#define I2S_STATUS0_RXUDIF_Pos (8) /*!< I2S_T::STATUS0: RXUDIF Position */
#define I2S_STATUS0_RXUDIF_Msk (0x1ul << I2S_STATUS0_RXUDIF_Pos) /*!< I2S_T::STATUS0: RXUDIF Mask */
#define I2S_STATUS0_RXOVIF_Pos (9) /*!< I2S_T::STATUS0: RXOVIF Position */
#define I2S_STATUS0_RXOVIF_Msk (0x1ul << I2S_STATUS0_RXOVIF_Pos) /*!< I2S_T::STATUS0: RXOVIF Mask */
#define I2S_STATUS0_RXTHIF_Pos (10) /*!< I2S_T::STATUS0: RXTHIF Position */
#define I2S_STATUS0_RXTHIF_Msk (0x1ul << I2S_STATUS0_RXTHIF_Pos) /*!< I2S_T::STATUS0: RXTHIF Mask */
#define I2S_STATUS0_RXFULL_Pos (11) /*!< I2S_T::STATUS0: RXFULL Position */
#define I2S_STATUS0_RXFULL_Msk (0x1ul << I2S_STATUS0_RXFULL_Pos) /*!< I2S_T::STATUS0: RXFULL Mask */
#define I2S_STATUS0_RXEMPTY_Pos (12) /*!< I2S_T::STATUS0: RXEMPTY Position */
#define I2S_STATUS0_RXEMPTY_Msk (0x1ul << I2S_STATUS0_RXEMPTY_Pos) /*!< I2S_T::STATUS0: RXEMPTY Mask */
#define I2S_STATUS0_TXUDIF_Pos (16) /*!< I2S_T::STATUS0: TXUDIF Position */
#define I2S_STATUS0_TXUDIF_Msk (0x1ul << I2S_STATUS0_TXUDIF_Pos) /*!< I2S_T::STATUS0: TXUDIF Mask */
#define I2S_STATUS0_TXOVIF_Pos (17) /*!< I2S_T::STATUS0: TXOVIF Position */
#define I2S_STATUS0_TXOVIF_Msk (0x1ul << I2S_STATUS0_TXOVIF_Pos) /*!< I2S_T::STATUS0: TXOVIF Mask */
#define I2S_STATUS0_TXTHIF_Pos (18) /*!< I2S_T::STATUS0: TXTHIF Position */
#define I2S_STATUS0_TXTHIF_Msk (0x1ul << I2S_STATUS0_TXTHIF_Pos) /*!< I2S_T::STATUS0: TXTHIF Mask */
#define I2S_STATUS0_TXFULL_Pos (19) /*!< I2S_T::STATUS0: TXFULL Position */
#define I2S_STATUS0_TXFULL_Msk (0x1ul << I2S_STATUS0_TXFULL_Pos) /*!< I2S_T::STATUS0: TXFULL Mask */
#define I2S_STATUS0_TXEMPTY_Pos (20) /*!< I2S_T::STATUS0: TXEMPTY Position */
#define I2S_STATUS0_TXEMPTY_Msk (0x1ul << I2S_STATUS0_TXEMPTY_Pos) /*!< I2S_T::STATUS0: TXEMPTY Mask */
#define I2S_STATUS0_TXBUSY_Pos (21) /*!< I2S_T::STATUS0: TXBUSY Position */
#define I2S_STATUS0_TXBUSY_Msk (0x1ul << I2S_STATUS0_TXBUSY_Pos) /*!< I2S_T::STATUS0: TXBUSY Mask */
#define I2S_TXFIFO_TXFIFO_Pos (0) /*!< I2S_T::TXFIFO: TXFIFO Position */
#define I2S_TXFIFO_TXFIFO_Msk (0xfffffffful << I2S_TXFIFO_TXFIFO_Pos) /*!< I2S_T::TXFIFO: TXFIFO Mask */
#define I2S_RXFIFO_RXFIFO_Pos (0) /*!< I2S_T::RXFIFO: RXFIFO Position */
#define I2S_RXFIFO_RXFIFO_Msk (0xfffffffful << I2S_RXFIFO_RXFIFO_Pos) /*!< I2S_T::RXFIFO: RXFIFO Mask */
#define I2S_CTL1_CH0ZCEN_Pos (0) /*!< I2S_T::CTL1: CH0ZCEN Position */
#define I2S_CTL1_CH0ZCEN_Msk (0x1ul << I2S_CTL1_CH0ZCEN_Pos) /*!< I2S_T::CTL1: CH0ZCEN Mask */
#define I2S_CTL1_CH1ZCEN_Pos (1) /*!< I2S_T::CTL1: CH1ZCEN Position */
#define I2S_CTL1_CH1ZCEN_Msk (0x1ul << I2S_CTL1_CH1ZCEN_Pos) /*!< I2S_T::CTL1: CH1ZCEN Mask */
#define I2S_CTL1_CH2ZCEN_Pos (2) /*!< I2S_T::CTL1: CH2ZCEN Position */
#define I2S_CTL1_CH2ZCEN_Msk (0x1ul << I2S_CTL1_CH2ZCEN_Pos) /*!< I2S_T::CTL1: CH2ZCEN Mask */
#define I2S_CTL1_CH3ZCEN_Pos (3) /*!< I2S_T::CTL1: CH3ZCEN Position */
#define I2S_CTL1_CH3ZCEN_Msk (0x1ul << I2S_CTL1_CH3ZCEN_Pos) /*!< I2S_T::CTL1: CH3ZCEN Mask */
#define I2S_CTL1_CH4ZCEN_Pos (4) /*!< I2S_T::CTL1: CH4ZCEN Position */
#define I2S_CTL1_CH4ZCEN_Msk (0x1ul << I2S_CTL1_CH4ZCEN_Pos) /*!< I2S_T::CTL1: CH4ZCEN Mask */
#define I2S_CTL1_CH5ZCEN_Pos (5) /*!< I2S_T::CTL1: CH5ZCEN Position */
#define I2S_CTL1_CH5ZCEN_Msk (0x1ul << I2S_CTL1_CH5ZCEN_Pos) /*!< I2S_T::CTL1: CH5ZCEN Mask */
#define I2S_CTL1_CH6ZCEN_Pos (6) /*!< I2S_T::CTL1: CH6ZCEN Position */
#define I2S_CTL1_CH6ZCEN_Msk (0x1ul << I2S_CTL1_CH6ZCEN_Pos) /*!< I2S_T::CTL1: CH6ZCEN Mask */
#define I2S_CTL1_CH7ZCEN_Pos (7) /*!< I2S_T::CTL1: CH7ZCEN Position */
#define I2S_CTL1_CH7ZCEN_Msk (0x1ul << I2S_CTL1_CH7ZCEN_Pos) /*!< I2S_T::CTL1: CH7ZCEN Mask */
#define I2S_CTL1_TXTH_Pos (8) /*!< I2S_T::CTL1: TXTH Position */
#define I2S_CTL1_TXTH_Msk (0xful << I2S_CTL1_TXTH_Pos) /*!< I2S_T::CTL1: TXTH Mask */
#define I2S_CTL1_RXTH_Pos (16) /*!< I2S_T::CTL1: RXTH Position */
#define I2S_CTL1_RXTH_Msk (0xful << I2S_CTL1_RXTH_Pos) /*!< I2S_T::CTL1: RXTH Mask */
#define I2S_CTL1_PBWIDTH_Pos (24) /*!< I2S_T::CTL1: PBWIDTH Position */
#define I2S_CTL1_PBWIDTH_Msk (0x1ul << I2S_CTL1_PBWIDTH_Pos) /*!< I2S_T::CTL1: PBWIDTH Mask */
#define I2S_CTL1_PB16ORD_Pos (25) /*!< I2S_T::CTL1: PB16ORD Position */
#define I2S_CTL1_PB16ORD_Msk (0x1ul << I2S_CTL1_PB16ORD_Pos) /*!< I2S_T::CTL1: PB16ORD Mask */
#define I2S_STATUS1_CH0ZCIF_Pos (0) /*!< I2S_T::STATUS1: CH0ZCIF Position */
#define I2S_STATUS1_CH0ZCIF_Msk (0x1ul << I2S_STATUS1_CH0ZCIF_Pos) /*!< I2S_T::STATUS1: CH0ZCIF Mask */
#define I2S_STATUS1_CH1ZCIF_Pos (1) /*!< I2S_T::STATUS1: CH1ZCIF Position */
#define I2S_STATUS1_CH1ZCIF_Msk (0x1ul << I2S_STATUS1_CH1ZCIF_Pos) /*!< I2S_T::STATUS1: CH1ZCIF Mask */
#define I2S_STATUS1_CH2ZCIF_Pos (2) /*!< I2S_T::STATUS1: CH2ZCIF Position */
#define I2S_STATUS1_CH2ZCIF_Msk (0x1ul << I2S_STATUS1_CH2ZCIF_Pos) /*!< I2S_T::STATUS1: CH2ZCIF Mask */
#define I2S_STATUS1_CH3ZCIF_Pos (3) /*!< I2S_T::STATUS1: CH3ZCIF Position */
#define I2S_STATUS1_CH3ZCIF_Msk (0x1ul << I2S_STATUS1_CH3ZCIF_Pos) /*!< I2S_T::STATUS1: CH3ZCIF Mask */
#define I2S_STATUS1_CH4ZCIF_Pos (4) /*!< I2S_T::STATUS1: CH4ZCIF Position */
#define I2S_STATUS1_CH4ZCIF_Msk (0x1ul << I2S_STATUS1_CH4ZCIF_Pos) /*!< I2S_T::STATUS1: CH4ZCIF Mask */
#define I2S_STATUS1_CH5ZCIF_Pos (5) /*!< I2S_T::STATUS1: CH5ZCIF Position */
#define I2S_STATUS1_CH5ZCIF_Msk (0x1ul << I2S_STATUS1_CH5ZCIF_Pos) /*!< I2S_T::STATUS1: CH5ZCIF Mask */
#define I2S_STATUS1_CH6ZCIF_Pos (6) /*!< I2S_T::STATUS1: CH6ZCIF Position */
#define I2S_STATUS1_CH6ZCIF_Msk (0x1ul << I2S_STATUS1_CH6ZCIF_Pos) /*!< I2S_T::STATUS1: CH6ZCIF Mask */
#define I2S_STATUS1_CH7ZCIF_Pos (7) /*!< I2S_T::STATUS1: CH7ZCIF Position */
#define I2S_STATUS1_CH7ZCIF_Msk (0x1ul << I2S_STATUS1_CH7ZCIF_Pos) /*!< I2S_T::STATUS1: CH7ZCIF Mask */
#define I2S_STATUS1_TXCNT_Pos (8) /*!< I2S_T::STATUS1: TXCNT Position */
#define I2S_STATUS1_TXCNT_Msk (0x1ful << I2S_STATUS1_TXCNT_Pos) /*!< I2S_T::STATUS1: TXCNT Mask */
#define I2S_STATUS1_RXCNT_Pos (16) /*!< I2S_T::STATUS1: RXCNT Position */
#define I2S_STATUS1_RXCNT_Msk (0x1ful << I2S_STATUS1_RXCNT_Pos) /*!< I2S_T::STATUS1: RXCNT Mask */
/**@}*/ /* I2S_CONST */
/**@}*/ /* end of I2S register group */
/**@}*/ /* end of REGISTER group */
#if defined ( __CC_ARM )
#pragma no_anon_unions
#endif
#endif /* __I2S_REG_H__ */

409
bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/kpi_reg.h Normal file
View File

@ -0,0 +1,409 @@
/**************************************************************************//**
* @file kpi_reg.h
* @version V1.00
* @brief KPI register definition header file
*
* SPDX-License-Identifier: Apache-2.0
* @copyright (C) 20 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __KPI_REG_H__
#define __KPI_REG_H__
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
/**
@addtogroup REGISTER Control Register
@{
*/
/**
@addtogroup Keypad Interface (KPI)
Memory Mapped Structure for KPI Controller
@{ */
typedef struct
{
/**
* @var KPI_T::KPICONF
* Offset: 0x00 Keypad Configuration Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |ENKP |Keypad Scan Enable Bit
* | | |Setting this bit high enables the key scan function.
* | | |0 = Keypad scan Disabled.
* | | |1 = Keypad scan Enabled.
* |[1] |PKINTEN |Press Key Interrupt Enable Bit
* | | |The keypad controller will generate an interrupt when the controller detects any effective key press.
* | | |0 = Keypad press interrupt Disabled.
* | | |1 = Keypad press interrupt Enabled.
* | | |Note: The bit will be reset when KPI reset occurs.
* |[2] |RKINTEN |Release Key Interrupt Enable Bit
* | | |The keypad controller will generate an interrupt when the controller detects keypad status changes from press to release.
* | | |0 = Keypad release interrupt Disabled.
* | | |1 = Keypad release interrupt Enabled.
* | | |Note: The bit will be reset when KPI reset occurs.
* |[3] |INTEN |Key Interrupt Enable Bit
* | | |0 = Keypad interrupt Disabled.
* | | |1 = Keypad interrupt Enabled.
* | | |Note: The bit will be reset when KPI reset occurs.
* |[5] |WAKEUP |Lower Power Wakeup Enable Bit
* | | |Setting this bit enables low power wakeup.
* | | |0 = Wakeup Disabled.
* | | |1 = Wakeup Enabled.
* | | |Note: Setting the bit will force all KPI scan out to low.
* |[15:8] |PRESCALE |Row Scan Cycle Pre-scale Value
* | | |This value is used to pre-scale row scan cycle.
* | | |The pre-scale counter is clocked by the divided crystal clock, xCLOCK.
* | | |The divided number is from 1 to 256.
* | | |E.g.If the crystal clock is 1Mhz then the xCLOCK period is 1us.
* | | |If the keypad matric is 3x3 then
* | | |Each row scan time = xCLOCK x PRESCALE x PrescaleDivider.
* | | |Key array scan time = Each row scan time x ROWS.
* | | |Example scan time for PRESCALE = 0x40, and PrescaleDivider = 0x1F.
* | | |Each row scan time = 1us x 65 x 32 = 2.08ms.
* | | |Scan time = 2.08 x 3 = 6.24ms.
* | | |Note:
* | | |When PRESCALE is determined, De-bounce sampling cycle should not exceed the half of (PRESCALE x PrescaleDivider),
* | | |in the above example, and if scan row delay cycle is 4 xclock
* | | |The maximum DBCLKSEL should be 4*256 xCLOCK, bouncing time is 1ms.
* |[19:16] |DBCLKSEL |Scan in De-bounce Sampling Cycle Selection
* | | |0000 = Reserved.
* | | |0001 = Reserved.
* | | |0010 = Reserved.
* | | |0011 = Sample interrupt input once per 8 clocks.
* | | |0100 = Sample interrupt input once per 16 clocks.
* | | |0101 = Sample interrupt input once per 32 clocks.
* | | |0110 = Sample interrupt input once per 64 clocks.
* | | |0111 = Sample interrupt input once per 128 clocks.
* | | |1000 = Sample interrupt input once per 256 clocks.
* | | |1001 = Sample interrupt input once per 512 clocks.
* | | |1010 = Sample interrupt input once per 1024 clocks.
* | | |1011 = Sample interrupt input once per 2048 clocks.
* | | |1100 = Sample interrupt input once per 4096 clocks.
* | | |1101 = Sample interrupt input once per 8192 clocks.
* | | |1110 = reserved.
* | | |1111 = reserved.
* | | |Note:
* | | |scan row delay cycle < debounce sampling cycle.
* | | |row scan time > scan row delay cycle + (2 * debounce sampling cycle).
* | | |row scan time = prescale * 32 (xclock).
* | | |xclock = 1 MHz ~32 kHz.
* | | |bouncing time last for 1ms
* | | |For example, if xclock = 1 MHz,.
* | | |debounce sampling cycle choose 1024 xclock,
* | | |and scan row delay cycle choose 8 xclock,
* | | |row scan time should choose larger than (8+2048) xclock,
* | | |suppose PrescaleDivider = 0x1F, then prescale = 65 (2056/32 = 64.25).
* |[23:22] |SCANROWD |Scan Row Delay
* | | |Setting delay cycle when row change.
* | | |00 = 4 KPI engine clock cycle.
* | | |01 = 8 KPI engine clock cycle.
* | | |10 = 16 KPI engine clock cycle.
* | | |11 = 32 KPI engine clock cycle.
* | | |Note:
* | | |scan row delay cycle < debounce sampling cycle.
* | | |row scan time > scan row delay cycle + (2 * debounce sampling cycle).
* |[26:24] |KCOL |Keypad Matrix COL Number
* | | |The keypad matrix is set by ROW x COL. The COL number can be set 1 to 8.
* | | |000 = 1.
* | | |001 = 2.
* | | |010 = 3.
* | | |011 = 4.
* | | |100 = 5.
* | | |101 = 6.
* | | |110 = 7.
* | | |111 = 8.
* |[30:28] |KROW |Keypad Matrix ROW Number
* | | |The keypad matrix is set by ROW x COL. The ROW number can be set 2 to 6.
* | | |000 = reserved.
* | | |001 = 2.
* | | |010 = 3.
* | | |011 = 4.
* | | |100 = 5.
* | | |101 = 6.
* | | |110 = Reserved.
* | | |111 = Reserved.
* @var KPI_T::KPI3KCONF
* Offset: 0x04 Keypad 3-keys Configuration Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[2:0] |K30C |The #0 Key Column Address
* |[5:3] |K30R |The #0 Key Row Address
* | | |The #0 means the row address and the column address is the lowest of the specified 3-keys
* |[10:8] |K31C |The #1 Key Column Address
* |[13:11] |K31R |The #1 Key Row Address
* | | |The #1 means the row address and the column address is the 2nd of the specified 3-keys
* |[18:16] |K32C |The #2 Key Column Address
* |[21:19] |K32R |The #2 Key Row Address
* | | |The #2 means the row address and the column address is the highest of the specified 3-keys
* |[24] |EN3KYRST |Enable Three-key Reset
* | | |Setting this bit enables hardware reset when three-key is detected
* | | |0 = Three-key function Disabled.
* | | |1 = Three-key function Enabled.
* | | |Note: The bit will be reset when KPI reset occurs.
* @var KPI_T::KPISTATUS
* Offset: 0x08 Keypad Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |PDWAKE |Power Down Wakeup Flag
* | | |This flag indicates the chip is woken up from power down by keypad.
* | | |When READ:
* | | |0 = No wakeup.
* | | |1 = Wake-up by keypad.
* | | |When WRITE:
* | | |0 = No operation.
* | | |1 = Clear interrupt flag.
* |[1] |RST3KEY |3-keys Reset Flag
* | | |This bit will be set after 3-keys reset occurs.
* | | |When READ:
* | | |0 = No reset.
* | | |1 = 3 keys reset interrupt occurred.
* | | |When WRITE:
* | | |0 = No operation.
* | | |1 = Clear interrupt flag.
* |[2] |KEYINT |Key Interrupt
* | | |This bit indicates the key scan interrupt is active when any key press or release or three key reset or wake up.
* | | |When READ:
* | | |0 = No reset.
* | | |1 = Key press/release/3-key reset/wakeup interrupt occurred.
* |[3] |RKEYINT |Release Key Interrupt
* | | |This bit indicates that some keys (one or multiple key) have been released.
* | | |When READ:
* | | |0 = No key release.
* | | |1 = At least one key release.
* | | |Note: To clear RKEYINT, software must clear each releasing event that are shown on u201Ckey releasing eventu201D.
* | | |C code example:
* | | |DWORD RKE0, RKE1
* | | |PKE0 = reg_read(KPIKRE0); PKE1 = reg_read(KPIKRE1);.
* | | |Reg_write(KPIKRE0, RKE0); Reg_write(KPIKRE1, RKE1)
* |[4] |PKEYINT |Press Key Interrupt
* | | |This bit indicates that some keys (one or multiple key) have been pressed.
* | | |When READ:
* | | |0 = No key press.
* | | |1 = At least one key press.
* | | |Note: To clear PKEYINT, software must clear each pressing event that are shown on u201CKPIKPE1, KPIKPE0u201D.
* | | |C code example:
* | | |DWORD PKE0, PKE1
* | | |PKE0 = reg_read(KPIKPE0); PKE1 = reg_read(KPIKPE1);.
* | | |Reg_write(KPIKPE0, PKE0); Reg_write(KPIKPE1, PKE1)
* @var KPI_T::KPIRSTC
* Offset: 0x0C Keypad Reset Period Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |RSTC |3-key Reset Period Count
* | | |The keypad controller generates a reset signal when it detects 3-key match condition, if the EN3KYRST (KPI3KCONF[24]) is set
* | | |The RSTC is used to control the reset period.
* | | |Reset period = 64 * RSTC XCLOCK.
* @var KPI_T::KPIKEST0
* Offset: 0x10 Keypad State Register 0
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |KESTmn |Key State
* | | |KESTm,n: m is row number, n is column number
* | | |0 = Key m,n is pressing.
* | | |1 = Key m,n is releasing.
* @var KPI_T::KPIKEST1
* Offset: 0x14 Keypad State Register 1
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |KESTmn |Key State
* | | |KESTm,n: m is row number, n is column number
* | | |0 = Key m,n is pressing.
* | | |1 = Key m,n is releasing.
* @var KPI_T::KPIKPE0
* Offset: 0x18 Lower 32 Key Press Event Indicator
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |KPEmn |Lower 32 Key Press Event Change Indicator
* | | |KPE mn[X] = 1, m=row, n=column:.
* | | |0 = No key event.
* | | |1 = Corresponding key has a high to low event change.
* | | |Note:
* | | |Hardware will set this bit, and software should clear this bit by writing 1.
* | | |Software can clear PKEYINT (KPISTATUS[4]) by writing 1 bit by bit to this register.
* @var KPI_T::KPIKPE1
* Offset: 0x1C Upper 32 Key Press Event Indicator
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |KPEmn |Upper 32 Key Press Event Change Indicator
* | | |KPE mn[X] = 1, m=row, n=column:.
* | | |0 = No key event.
* | | |1 = Corresponding key has a high to low event change.
* | | |Note:
* | | |Hardware will set this bit, and software should clear this bit by writing 1.
* | | |Software can clear PKEYINT (KPISTATUS[4]) by writing 1 bit by bit to this register.
* @var KPI_T::KPIKRE0
* Offset: 0x20 Lower 32 Key Release Event Indicator
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |KREmn |Lower 32 Key Release Event Change Indicator
* | | |KRE mn[X] = 1, m=row, n=column:.
* | | |0 = No key event.
* | | |1 = Corresponding key has a low to high event change.
* | | |Note:
* | | |Hardware will set this bit, and software should clear this bit by writing 1.
* | | |Software can clear RKEYINT (KPISTATUS[3]) by writing 1 bit by bit to this register.
* @var KPI_T::KPIKRE1
* Offset: 0x24 Upper 32 Key Release Event Indicator
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |KREmn |Upper 32 Key Release Event Change Indicator
* | | |KRE mn[X] = 1, m=row, n=column:.
* | | |0 = No key event.
* | | |1 = Corresponding key has a low to high event change.
* | | |Note:
* | | |Hardware will set this bit, and software should clear this bit by writing 1.
* | | |Software can clear RKEYINT (KPISTATUS[3]) by writing 1 bit by bit to this register.
* @var KPI_T::KPIPRESCALDIV
* Offset: 0x28 Pre-scale Divider
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |PRESCALDIV|Pre-scale Divider
* | | |This value is used to divide RESCALE that is set in KPICONF[15:8]
* | | |The prescale divider counter is clocked by the divided crystal clock, xCLOCK
* | | |The number is from 1 to 256.
* | | |E.g. If the crystal clock is 1Mhz then the xCLOCK period is 1us. If the keypad matrix is 3x3. Then,
* | | |each row scan time = xCLOCK x PRESCALE x PrescaleDivider.
* | | |key array scan time = each row scan time x ROWS.
* | | |example scan time for PRESCALE = 0x40, and PrescaleDivider = 0x1F.
* | | |each row scan time = 1us x 65 x 32 = 2.08ms.
* | | |scan time = 2.08 x 3 = 6.24ms.
* | | |Note:
* | | |When PRESCALE (KPICONF[15:8]) is determined, De-bounce sampling cycle should not exceed the half of (PRESCALE x PrescaleDivider),
* | | |in the above example, and if scan row delay cycle is 4 xclock
* | | |The maximum DBCLKSEL(KPICONF[19:16]) should be 1024 x clock, bouncing time is 1ms.
*/
__IO uint32_t KPICONF; /*!< [0x0000] Keypad Configuration Register */
__IO uint32_t KPI3KCONF; /*!< [0x0004] Keypad 3-keys Configuration Register */
__IO uint32_t KPISTATUS; /*!< [0x0008] Keypad Status Register */
__IO uint32_t KPIRSTC; /*!< [0x000c] Keypad Reset Period Control Register */
__I uint32_t KPIKEST0; /*!< [0x0010] Keypad State Register 0 */
__I uint32_t KPIKEST1; /*!< [0x0014] Keypad State Register 1 */
__IO uint32_t KPIKPE0; /*!< [0x0018] Lower 32 Key Press Event Indicator */
__IO uint32_t KPIKPE1; /*!< [0x001c] Upper 32 Key Press Event Indicator */
__IO uint32_t KPIKRE0; /*!< [0x0020] Lower 32 Key Release Event Indicator */
__IO uint32_t KPIKRE1; /*!< [0x0024] Upper 32 Key Release Event Indicator */
__IO uint32_t KPIPRESCALDIV; /*!< [0x0028] Pre-scale Divider */
} KPI_T;
/**
@addtogroup KPI_CONST KPI Bit Field Definition
Constant Definitions for KPI Controller
@{ */
#define KPI_KPICONF_ENKP_Pos (0) /*!< KPI_T::KPICONF: ENKP Position */
#define KPI_KPICONF_ENKP_Msk (0x1ul << KPI_KPICONF_ENKP_Pos) /*!< KPI_T::KPICONF: ENKP Mask */
#define KPI_KPICONF_PKINTEN_Pos (1) /*!< KPI_T::KPICONF: PKINTEN Position */
#define KPI_KPICONF_PKINTEN_Msk (0x1ul << KPI_KPICONF_PKINTEN_Pos) /*!< KPI_T::KPICONF: PKINTEN Mask */
#define KPI_KPICONF_RKINTEN_Pos (2) /*!< KPI_T::KPICONF: RKINTEN Position */
#define KPI_KPICONF_RKINTEN_Msk (0x1ul << KPI_KPICONF_RKINTEN_Pos) /*!< KPI_T::KPICONF: RKINTEN Mask */
#define KPI_KPICONF_INTEN_Pos (3) /*!< KPI_T::KPICONF: INTEN Position */
#define KPI_KPICONF_INTEN_Msk (0x1ul << KPI_KPICONF_INTEN_Pos) /*!< KPI_T::KPICONF: INTEN Mask */
#define KPI_KPICONF_WAKEUP_Pos (5) /*!< KPI_T::KPICONF: WAKEUP Position */
#define KPI_KPICONF_WAKEUP_Msk (0x1ul << KPI_KPICONF_WAKEUP_Pos) /*!< KPI_T::KPICONF: WAKEUP Mask */
#define KPI_KPICONF_PRESCALE_Pos (8) /*!< KPI_T::KPICONF: PRESCALE Position */
#define KPI_KPICONF_PRESCALE_Msk (0xfful << KPI_KPICONF_PRESCALE_Pos) /*!< KPI_T::KPICONF: PRESCALE Mask */
#define KPI_KPICONF_DBCLKSEL_Pos (16) /*!< KPI_T::KPICONF: DBCLKSEL Position */
#define KPI_KPICONF_DBCLKSEL_Msk (0xful << KPI_KPICONF_DBCLKSEL_Pos) /*!< KPI_T::KPICONF: DBCLKSEL Mask */
#define KPI_KPICONF_SCANROWD_Pos (22) /*!< KPI_T::KPICONF: SCANROWD Position */
#define KPI_KPICONF_SCANROWD_Msk (0x3ul << KPI_KPICONF_SCANROWD_Pos) /*!< KPI_T::KPICONF: SCANROWD Mask */
#define KPI_KPICONF_KCOL_Pos (24) /*!< KPI_T::KPICONF: KCOL Position */
#define KPI_KPICONF_KCOL_Msk (0x7ul << KPI_KPICONF_KCOL_Pos) /*!< KPI_T::KPICONF: KCOL Mask */
#define KPI_KPICONF_KROW_Pos (28) /*!< KPI_T::KPICONF: KROW Position */
#define KPI_KPICONF_KROW_Msk (0x7ul << KPI_KPICONF_KROW_Pos) /*!< KPI_T::KPICONF: KROW Mask */
#define KPI_KPI3KCONF_K30C_Pos (0) /*!< KPI_T::KPI3KCONF: K30C Position */
#define KPI_KPI3KCONF_K30C_Msk (0x7ul << KPI_KPI3KCONF_K30C_Pos) /*!< KPI_T::KPI3KCONF: K30C Mask */
#define KPI_KPI3KCONF_K30R_Pos (3) /*!< KPI_T::KPI3KCONF: K30R Position */
#define KPI_KPI3KCONF_K30R_Msk (0x7ul << KPI_KPI3KCONF_K30R_Pos) /*!< KPI_T::KPI3KCONF: K30R Mask */
#define KPI_KPI3KCONF_K31C_Pos (8) /*!< KPI_T::KPI3KCONF: K31C Position */
#define KPI_KPI3KCONF_K31C_Msk (0x7ul << KPI_KPI3KCONF_K31C_Pos) /*!< KPI_T::KPI3KCONF: K31C Mask */
#define KPI_KPI3KCONF_K31R_Pos (11) /*!< KPI_T::KPI3KCONF: K31R Position */
#define KPI_KPI3KCONF_K31R_Msk (0x7ul << KPI_KPI3KCONF_K31R_Pos) /*!< KPI_T::KPI3KCONF: K31R Mask */
#define KPI_KPI3KCONF_K32C_Pos (16) /*!< KPI_T::KPI3KCONF: K32C Position */
#define KPI_KPI3KCONF_K32C_Msk (0x7ul << KPI_KPI3KCONF_K32C_Pos) /*!< KPI_T::KPI3KCONF: K32C Mask */
#define KPI_KPI3KCONF_K32R_Pos (19) /*!< KPI_T::KPI3KCONF: K32R Position */
#define KPI_KPI3KCONF_K32R_Msk (0x7ul << KPI_KPI3KCONF_K32R_Pos) /*!< KPI_T::KPI3KCONF: K32R Mask */
#define KPI_KPI3KCONF_EN3KYRST_Pos (24) /*!< KPI_T::KPI3KCONF: EN3KYRST Position */
#define KPI_KPI3KCONF_EN3KYRST_Msk (0x1ul << KPI_KPI3KCONF_EN3KYRST_Pos) /*!< KPI_T::KPI3KCONF: EN3KYRST Mask */
#define KPI_KPISTATUS_PDWAKE_Pos (0) /*!< KPI_T::KPISTATUS: PDWAKE Position */
#define KPI_KPISTATUS_PDWAKE_Msk (0x1ul << KPI_KPISTATUS_PDWAKE_Pos) /*!< KPI_T::KPISTATUS: PDWAKE Mask */
#define KPI_KPISTATUS_RST3KEY_Pos (1) /*!< KPI_T::KPISTATUS: RST3KEY Position */
#define KPI_KPISTATUS_RST3KEY_Msk (0x1ul << KPI_KPISTATUS_RST3KEY_Pos) /*!< KPI_T::KPISTATUS: RST3KEY Mask */
#define KPI_KPISTATUS_KEYINT_Pos (2) /*!< KPI_T::KPISTATUS: KEYINT Position */
#define KPI_KPISTATUS_KEYINT_Msk (0x1ul << KPI_KPISTATUS_KEYINT_Pos) /*!< KPI_T::KPISTATUS: KEYINT Mask */
#define KPI_KPISTATUS_RKEYINT_Pos (3) /*!< KPI_T::KPISTATUS: RKEYINT Position */
#define KPI_KPISTATUS_RKEYINT_Msk (0x1ul << KPI_KPISTATUS_RKEYINT_Pos) /*!< KPI_T::KPISTATUS: RKEYINT Mask */
#define KPI_KPISTATUS_PKEYINT_Pos (4) /*!< KPI_T::KPISTATUS: PKEYINT Position */
#define KPI_KPISTATUS_PKEYINT_Msk (0x1ul << KPI_KPISTATUS_PKEYINT_Pos) /*!< KPI_T::KPISTATUS: PKEYINT Mask */
#define KPI_KPIRSTC_RSTC_Pos (0) /*!< KPI_T::KPIRSTC: RSTC Position */
#define KPI_KPIRSTC_RSTC_Msk (0xfful << KPI_KPIRSTC_RSTC_Pos) /*!< KPI_T::KPIRSTC: RSTC Mask */
#define KPI_KPIKEST0_KESTmn_Pos (0) /*!< KPI_T::KPIKEST0: KESTmn Position */
#define KPI_KPIKEST0_KESTmn_Msk (0xfffffffful << KPI_KPIKEST0_KESTmn_Pos) /*!< KPI_T::KPIKEST0: KESTmn Mask */
#define KPI_KPIKEST1_KESTmn_Pos (0) /*!< KPI_T::KPIKEST1: KESTmn Position */
#define KPI_KPIKEST1_KESTmn_Msk (0xfffful << KPI_KPIKEST1_KESTmn_Pos) /*!< KPI_T::KPIKEST1: KESTmn Mask */
#define KPI_KPIKPE0_KPEmn_Pos (0) /*!< KPI_T::KPIKPE0: KPEmn Position */
#define KPI_KPIKPE0_KPEmn_Msk (0xfffffffful << KPI_KPIKPE0_KPEmn_Pos) /*!< KPI_T::KPIKPE0: KPEmn Mask */
#define KPI_KPIKPE1_KPEmn_Pos (0) /*!< KPI_T::KPIKPE1: KPEmn Position */
#define KPI_KPIKPE1_KPEmn_Msk (0xfffful << KPI_KPIKPE1_KPEmn_Pos) /*!< KPI_T::KPIKPE1: KPEmn Mask */
#define KPI_KPIKRE0_KREmn_Pos (0) /*!< KPI_T::KPIKRE0: KREmn Position */
#define KPI_KPIKRE0_KREmn_Msk (0xfffffffful << KPI_KPIKRE0_KREmn_Pos) /*!< KPI_T::KPIKRE0: KREmn Mask */
#define KPI_KPIKRE1_KREmn_Pos (0) /*!< KPI_T::KPIKRE1: KREmn Position */
#define KPI_KPIKRE1_KREmn_Msk (0xfffful << KPI_KPIKRE1_KREmn_Pos) /*!< KPI_T::KPIKRE1: KREmn Mask */
#define KPI_KPIPRESCALDIV_PRESCALDIV_Pos (0) /*!< KPI_T::KPIPRESCALDIV: PRESCALDIV Position*/
#define KPI_KPIPRESCALDIV_PRESCALDIV_Msk (0xfful << KPI_KPIPRESCALDIV_PRESCALDIV_Pos) /*!< KPI_T::KPIPRESCALDIV: PRESCALDIV Mask */
/**@}*/ /* KPI_CONST */
/**@}*/ /* end of KPI register group */
#if defined ( __CC_ARM )
#pragma no_anon_unions
#endif
#endif /* __KPI_REG_H__ */

473
bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/ks_reg.h Normal file
View File

@ -0,0 +1,473 @@
/**************************************************************************//**
* @file ks_reg.h
* @brief Key Store register definition header file
*
* SPDX-License-Identifier: Apache-2.0
* @copyright (C) 2021 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __KS_REG_H__
#define __KS_REG_H__
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
/**
@addtogroup REGISTER Control Register
@{
*/
/*---------------------- Key Store -------------------------*/
/**
@addtogroup KS Key Store(KS)
Memory Mapped Structure for KS Controller
@{ */
typedef struct
{
/**
* @var KS_T::CTL
* Offset: 0x00 Key Store Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |START |Key Store Start Control Bit
* | | |0 = No operation.
* | | |1 = Start the operation.
* |[3:1] |OPMODE |Key Store Operation Mode
* | | |000 = Read operation.
* | | |001 = Create operation.
* | | |010 = Erase one key operation.
* | | |011 = Erase all keys operation (only for SRAM).
* | | |100 = Revoke key operation.
* | | |101 = Data Remanence prevention operation (only for SRAM).
* | | |Others = reserved.
* |[7] |CONT |Read/Write Key Continue Bit
* | | |0 = Read/Write key operation is not continuous to previous operation.
* | | |1 = Read/Write key operation is continuous to previous operation.
* |[8] |INIT |Key Store Initialization
* | | |User should check BUSY(KS_STS[2]) is 0, and then write 1 to this bit and START(KS_CTL[0[), Key Store will start initialization.
* | | |After the Key Store is initialized, INIT will be cleared.
* |[10] |SILENT |Silent Access Enable Bit
* | | |0 = Silent access Disabled.
* | | |1 = Silent access Enabled.
* |[11] |SCMB |Data Scramble Enable Bit
* | | |0 = Data scramble Disabled.
* | | |1 = Data scramble Enabled.
* |[14] |TCLR |Tamper Event Clear Control Bit
* | | |0 = Key Store does not clear all keys at SRAM and revoke all OTP keys when tamper event occurs.
* | | |1 = Key Store clears all keys at SRAM and revoke all OTP keys when tamper event occurs.
* |[15] |IEN |Key Store Interrupt Enable Bit
* | | |0 = Key Store interrupt Disabled.
* | | |1 = Key Store interrupt Enabled.
* @var KS_T::METADATA
* Offset: 0x04 Key Store Metadata Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |SEC |Secure Key Selection Bit
* | | |0 = Set key as the non-secure key.
* | | |1 = Set key as the secure key.
* |[2] |READABLE |Key Readable Control Bit
* | | |0 = key is un-readable.
* | | |1 = key is readable.
* |[3] |RVK |Key Revoke Control Bit
* | | |0 = Key current selected will not be changed.
* | | |1 = key current selected will be change to revoked state.
* |[4] |BS |Booting State Selection Bit
* | | |0 = Set key used at all state.
* | | |1 = Set key used at boot loader state 1 (BL1 state).
* |[12:8] |SIZE |Key Size Selection Bits
* | | |00000 = 128 bits.
* | | |00001 = 163 bits.
* | | |00010 = 192 bits.
* | | |00011 = 224 bits.
* | | |00100 = 233 bits.
* | | |00101 = 255 bits.
* | | |00110 = 256 bits.
* | | |00111 = 283 bits.
* | | |01000 = 384 bits.
* | | |01001 = 409 bits.
* | | |01010 = 512 bits.
* | | |01011 = 521 bits.
* | | |01100 = 571 bits.
* | | |10000 = 1024 bits.
* | | |10001 = 1536 bits.
* | | |10010 = 2048 bits.
* | | |10011 = 3072 bits.
* | | |10100 = 4096 bits.
* | | |Others = reserved.
* |[18:16] |OWNER |Key Owner Selection Bits
* | | |000 = AES.
* | | |001 = HMAC.
* | | |010 = RSA exponent blind key for SCAP(CRYPTO_RSA_CTL[8]) = 1 and CRT(CRYPTO_RSA_CTL[2]) = 0 .
* | | |011 = RSA middle data, p, q and private key.
* | | |100 = ECC.
* | | |101 = CPU.
* | | |Others = reserved.
* |[25:20] |NUMBER |Key Number
* | | |Before read or erase one key operation is started, user should write the key number to be operated
* | | |When create operation is finished, user can read these bits to get its key number.
* |[31:30] |DST |Key Location Selection Bits
* | | |00 = Key is in SRAM.
* | | |10 = Key is in OTP.
* | | |Others = reserved.
* @var KS_T::STS
* Offset: 0x08 Key Store Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |IF |Key Store Finish Interrupt Flag (Write 1 to Clear)
* | | |This bit is cleared by writing 1 and it has no effect by writing 0.
* | | |0 = No Key Store interrupt.
* | | |1 = Key Store operation done interrupt.
* |[1] |EIF |Key Store Error Flag (Write 1 to Clear)
* | | |This bit is cleared by writing 1 and it has no effect by writing 0.
* | | |0 = No Key Store error.
* | | |1 = Key Store error interrupt.
* |[2] |BUSY |Key Store Busy Flag (Read Only)
* | | |0 = Key Store is idle or finished.
* | | |1 = Key Store is busy.
* |[3] |SRAMFULL |Key Storage at SRAM Full Status Bit (Read Only)
* | | |0 = Key Storage at SRAM is not full.
* | | |1 = Key Storage at SRAM is full.
* |[7] |INITDONE |Key Store Initialization Done Status (Read Only)
* | | |0 = Key Store is un-initialized.
* | | |1 = Key Store is initialized.
* |[8] |RAMINV |Key Store SRAM Invert Status (Read Only)
* | | |0 = Key Store key in SRAM is normal.
* | | |1 = Key Store key in SRAM is inverted.
* @var KS_T::REMAIN
* Offset: 0x0C Key Store Remaining Space Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[12:0] |RRMNG |Key Store SRAM Remaining Space
* | | |The RRMNG shows the remaining byte count space of SRAM
* @var KS_T::SCMBKEY0
* Offset: 0x10 Key Store Scramble Key Word 0 Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |SCMBKEY |Key Store Scramble Key
* | | |When SCMB(KS_CTL[]) is set to 1, user should write the scramble key in this register before new key stores in Key Store
* | | |If user does not write the scramble key in this register, the Key Store will use previous scramble key to execute data scramble function.
* @var KS_T::SCMBKEY1
* Offset: 0x14 Key Store Scramble Key Word 1 Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |SCMBKEY |Key Store Scramble Key
* | | |When SCMB(KS_CTL[]) is set to 1, user should write the scramble key in this register before new key stores in Key Store
* | | |If user does not write the scramble key in this register, the Key Store will use previous scramble key to execute data scramble function.
* @var KS_T::SCMBKEY2
* Offset: 0x18 Key Store Scramble Key Word 2 Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |SCMBKEY |Key Store Scramble Key
* | | |When SCMB(KS_CTL[]) is set to 1, user should write the scramble key in this register before new key stores in Key Store
* | | |If user does not write the scramble key in this register, the Key Store will use previous scramble key to execute data scramble function.
* @var KS_T::SCMBKEY3
* Offset: 0x1C Key Store Scramble Key Word 3 Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |SCMBKEY |Key Store Scramble Key
* | | |When SCMB(KS_CTL[]) is set to 1, user should write the scramble key in this register before new key stores in Key Store
* | | |If user does not write the scramble key in this register, the Key Store will use previous scramble key to execute data scramble function.
* @var KS_T::KEY0
* Offset: 0x20 Key Store Entry Key Word 0 Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |KEY |Key Data (Read/Write, Read to Clear)
* | | |These registers will be cleared if Key Store executes the write operation or CPU completes the reading key.
* @var KS_T::KEY1
* Offset: 0x24 Key Store Entry Key Word 1 Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |KEY |Key Data (Read/Write, Read to Clear)
* | | |These registers will be cleared if Key Store executes the write operation or CPU completes the reading key.
* @var KS_T::KEY2
* Offset: 0x28 Key Store Entry Key Word 2 Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |KEY |Key Data (Read/Write, Read to Clear)
* | | |These registers will be cleared if Key Store executes the write operation or CPU completes the reading key.
* @var KS_T::KEY3
* Offset: 0x2C Key Store Entry Key Word 3 Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |KEY |Key Data (Read/Write, Read to Clear)
* | | |These registers will be cleared if Key Store executes the write operation or CPU completes the reading key.
* @var KS_T::KEY4
* Offset: 0x30 Key Store Entry Key Word 4 Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |KEY |Key Data (Read/Write, Read to Clear)
* | | |These registers will be cleared if Key Store executes the write operation or CPU completes the reading key.
* @var KS_T::KEY5
* Offset: 0x34 Key Store Entry Key Word 5 Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |KEY |Key Data (Read/Write, Read to Clear)
* | | |These registers will be cleared if Key Store executes the write operation or CPU completes the reading key.
* @var KS_T::KEY6
* Offset: 0x38 Key Store Entry Key Word 6 Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |KEY |Key Data (Read/Write, Read to Clear)
* | | |These registers will be cleared if Key Store executes the write operation or CPU completes the reading key.
* @var KS_T::KEY7
* Offset: 0x3C Key Store Entry Key Word 7 Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |KEY |Key Data (Read/Write, Read to Clear)
* | | |These registers will be cleared if Key Store executes the write operation or CPU completes the reading key.
* @var KS_T::OTPSTS
* Offset: 0x40 Key Store OTP Keys Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |KEY0 |OTP Key 0 Used Status
* | | |0 = OTP key 0 is unused.
* | | |1 = OTP key 0 is used.
* | | |Note: When chip is in RMA stage, this bit will be set to 1 and key is revoked after initialization if key is existed.
* |[1] |KEY1 |OTP Key 1 Used Status
* | | |0 = OTP key 1 is unused.
* | | |1 = OTP key 1 is used.
* | | |Note: When chip is in RMA stage, this bit will be set to 1 and key is revoked after initialization if key is existed.
* |[2] |KEY2 |OTP Key 2 Used Status
* | | |0 = OTP key 2 is unused.
* | | |1 = OTP key 2 is used.
* | | |Note: When chip is in RMA stage, this bit will be set to 1 and key is revoked after initialization if key is existed.
* |[3] |KEY3 |OTP Key 3 Used Status
* | | |0 = OTP key 3 is unused.
* | | |1 = OTP key 3 is used.
* | | |Note: When chip is in RMA stage, this bit will be set to 1 and key is revoked after initialization if key is existed.
* |[4] |KEY4 |OTP Key 4 Used Status
* | | |0 = OTP key 4 is unused.
* | | |1 = OTP key 4 is used.
* | | |Note: When chip is in RMA stage, this bit will be set to 1 and key is revoked after initialization if key is existed.
* |[5] |KEY5 |OTP Key 5 Used Status
* | | |0 = OTP key 5 is unused.
* | | |1 = OTP key 5 is used.
* | | |Note: When chip is in RMA stage, this bit will be set to 1 and key is revoked after initialization if key is existed.
* |[6] |KEY6 |OTP Key 6 Used Status
* | | |0 = OTP key 6 is unused.
* | | |1 = OTP key 6 is used.
* | | |Note: When chip is in RMA stage, this bit will be set to 1 and key is revoked after initialization if key is existed.
* |[7] |KEY7 |OTP Key 7 Used Status
* | | |0 = OTP key 7 is unused.
* | | |1 = OTP key 7 is used.
* | | |Note: When chip is in RMA stage, this bit will be set to 1 and key is revoked after initialization if key is existed.
* |[8] |KEY8 |OTP Key 8 Used Status
* | | |0 = OTP key 8 is unused.
* | | |1 = OTP key 8 is used.
* | | |Note: When chip is in RMA stage, this bit will be set to 1 and key is revoked after initialization if key is existed.
* @var KS_T::REMKCNT
* Offset: 0x44 Key Store Remaining Key Count Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[5:0] |RRMKCNT |Key Store SRAM Remaining Key Count
* | | |The RRMKCNT shows the remaining key count for SRAM.
*/
__IO uint32_t CTL; /*!< [0x0000] Key Store Control Register */
__IO uint32_t METADATA; /*!< [0x0004] Key Store Metadata Register */
__IO uint32_t STS; /*!< [0x0008] Key Store Status Register */
__I uint32_t REMAIN; /*!< [0x000c] Key Store Remaining Space Register */
__IO uint32_t SCMBKEY0; /*!< [0x0010] Key Store Scramble Key Word 0 Register */
__IO uint32_t SCMBKEY1; /*!< [0x0014] Key Store Scramble Key Word 1 Register */
__IO uint32_t SCMBKEY2; /*!< [0x0018] Key Store Scramble Key Word 2 Register */
__IO uint32_t SCMBKEY3; /*!< [0x001c] Key Store Scramble Key Word 3 Register */
__IO uint32_t KEY0; /*!< [0x0020] Key Store Entry Key Word 0 Register */
__IO uint32_t KEY1; /*!< [0x0024] Key Store Entry Key Word 1 Register */
__IO uint32_t KEY2; /*!< [0x0028] Key Store Entry Key Word 2 Register */
__IO uint32_t KEY3; /*!< [0x002c] Key Store Entry Key Word 3 Register */
__IO uint32_t KEY4; /*!< [0x0030] Key Store Entry Key Word 4 Register */
__IO uint32_t KEY5; /*!< [0x0034] Key Store Entry Key Word 5 Register */
__IO uint32_t KEY6; /*!< [0x0038] Key Store Entry Key Word 6 Register */
__IO uint32_t KEY7; /*!< [0x003c] Key Store Entry Key Word 7 Register */
__I uint32_t OTPSTS; /*!< [0x0040] Key Store OTP Keys Status Register */
__I uint32_t REMKCNT; /*!< [0x0044] Key Store Remaining Key Count Register */
} KS_T;
typedef struct
{
__IO uint32_t CTL; /*!< [0x0000] Key Store Control Register */
__IO uint32_t METADATA; /*!< [0x0004] Key Store Metadata Register */
__IO uint32_t STS; /*!< [0x0008] Key Store Status Register */
__I uint32_t REMAIN; /*!< [0x000c] Key Store Remaining Space Register */
__I uint32_t RESERVE0[4];
__IO uint32_t KEY0; /*!< [0x0020] Key Store Entry Key Word 0 Register */
__IO uint32_t KEY1; /*!< [0x0024] Key Store Entry Key Word 1 Register */
__IO uint32_t KEY2; /*!< [0x0028] Key Store Entry Key Word 2 Register */
__IO uint32_t KEY3; /*!< [0x002c] Key Store Entry Key Word 3 Register */
__IO uint32_t KEY4; /*!< [0x0030] Key Store Entry Key Word 4 Register */
__IO uint32_t KEY5; /*!< [0x0034] Key Store Entry Key Word 5 Register */
__IO uint32_t KEY6; /*!< [0x0038] Key Store Entry Key Word 6 Register */
__IO uint32_t KEY7; /*!< [0x003c] Key Store Entry Key Word 7 Register */
__I uint32_t OTPSTS; /*!< [0x0040] Key Store OTP Keys Status Register */
__I uint32_t REMKCNT; /*!< [0x0044] Key Store Remaining Key Count Register */
} NS_KS_T;
/**
@addtogroup KS_CONST KS Bit Field Definition
Constant Definitions for KS Controller
@{ */
#define KS_CTL_START_Pos (0) /*!< KS_T::CTL: START Position */
#define KS_CTL_START_Msk (0x1ul << KS_CTL_START_Pos) /*!< KS_T::CTL: START Mask */
#define KS_CTL_OPMODE_Pos (1) /*!< KS_T::CTL: OPMODE Position */
#define KS_CTL_OPMODE_Msk (0x7ul << KS_CTL_OPMODE_Pos) /*!< KS_T::CTL: OPMODE Mask */
#define KS_CTL_CONT_Pos (7) /*!< KS_T::CTL: CONT Position */
#define KS_CTL_CONT_Msk (0x1ul << KS_CTL_CONT_Pos) /*!< KS_T::CTL: CONT Mask */
#define KS_CTL_INIT_Pos (8) /*!< KS_T::CTL: INIT Position */
#define KS_CTL_INIT_Msk (0x1ul << KS_CTL_INIT_Pos) /*!< KS_T::CTL: INIT Mask */
#define KS_CTL_SILENT_Pos (10) /*!< KS_T::CTL: SILENT Position */
#define KS_CTL_SILENT_Msk (0x1ul << KS_CTL_SILENT_Pos) /*!< KS_T::CTL: SILENT Mask */
#define KS_CTL_SCMB_Pos (11) /*!< KS_T::CTL: SCMB Position */
#define KS_CTL_SCMB_Msk (0x1ul << KS_CTL_SCMB_Pos) /*!< KS_T::CTL: SCMB Mask */
#define KS_CTL_TCLR_Pos (14) /*!< KS_T::CTL: TCLR Position */
#define KS_CTL_TCLR_Msk (0x1ul << KS_CTL_TCLR_Pos) /*!< KS_T::CTL: TCLR Mask */
#define KS_CTL_IEN_Pos (15) /*!< KS_T::CTL: IEN Position */
#define KS_CTL_IEN_Msk (0x1ul << KS_CTL_IEN_Pos) /*!< KS_T::CTL: IEN Mask */
#define KS_METADATA_SEC_Pos (0) /*!< KS_T::METADATA: SEC Position */
#define KS_METADATA_SEC_Msk (0x1ul << KS_METADATA_SEC_Pos) /*!< KS_T::METADATA: SEC Mask */
#define KS_METADATA_READABLE_Pos (2) /*!< KS_T::METADATA: READABLE Position */
#define KS_METADATA_READABLE_Msk (0x1ul << KS_METADATA_READABLE_Pos) /*!< KS_T::METADATA: READABLE Mask */
#define KS_METADATA_RVK_Pos (3) /*!< KS_T::METADATA: RVK Position */
#define KS_METADATA_RVK_Msk (0x1ul << KS_METADATA_RVK_Pos) /*!< KS_T::METADATA: RVK Mask */
#define KS_METADATA_BS_Pos (4) /*!< KS_T::METADATA: BS Position */
#define KS_METADATA_BS_Msk (0x1ul << KS_METADATA_BS_Pos) /*!< KS_T::METADATA: BS Mask */
#define KS_METADATA_SIZE_Pos (8) /*!< KS_T::METADATA: SIZE Position */
#define KS_METADATA_SIZE_Msk (0x1ful << KS_METADATA_SIZE_Pos) /*!< KS_T::METADATA: SIZE Mask */
#define KS_METADATA_OWNER_Pos (16) /*!< KS_T::METADATA: OWNER Position */
#define KS_METADATA_OWNER_Msk (0x7ul << KS_METADATA_OWNER_Pos) /*!< KS_T::METADATA: OWNER Mask */
#define KS_METADATA_NUMBER_Pos (20) /*!< KS_T::METADATA: NUMBER Position */
#define KS_METADATA_NUMBER_Msk (0x3ful << KS_METADATA_NUMBER_Pos) /*!< KS_T::METADATA: NUMBER Mask */
#define KS_METADATA_DST_Pos (30) /*!< KS_T::METADATA: DST Position */
#define KS_METADATA_DST_Msk (0x3ul << KS_METADATA_DST_Pos) /*!< KS_T::METADATA: DST Mask */
#define KS_STS_IF_Pos (0) /*!< KS_T::STS: IF Position */
#define KS_STS_IF_Msk (0x1ul << KS_STS_IF_Pos) /*!< KS_T::STS: IF Mask */
#define KS_STS_EIF_Pos (1) /*!< KS_T::STS: EIF Position */
#define KS_STS_EIF_Msk (0x1ul << KS_STS_EIF_Pos) /*!< KS_T::STS: EIF Mask */
#define KS_STS_BUSY_Pos (2) /*!< KS_T::STS: BUSY Position */
#define KS_STS_BUSY_Msk (0x1ul << KS_STS_BUSY_Pos) /*!< KS_T::STS: BUSY Mask */
#define KS_STS_SRAMFULL_Pos (3) /*!< KS_T::STS: SRAMFULL Position */
#define KS_STS_SRAMFULL_Msk (0x1ul << KS_STS_SRAMFULL_Pos) /*!< KS_T::STS: SRAMFULL Mask */
#define KS_STS_INITDONE_Pos (7) /*!< KS_T::STS: INITDONE Position */
#define KS_STS_INITDONE_Msk (0x1ul << KS_STS_INITDONE_Pos) /*!< KS_T::STS: INITDONE Mask */
#define KS_STS_RAMINV_Pos (8) /*!< KS_T::STS: RAMINV Position */
#define KS_STS_RAMINV_Msk (0x1ul << KS_STS_RAMINV_Pos) /*!< KS_T::STS: RAMINV Mask */
#define KS_REMAIN_RRMNG_Pos (0) /*!< KS_T::REMAIN: RRMNG Position */
#define KS_REMAIN_RRMNG_Msk (0x1ffful << KS_REMAIN_RRMNG_Pos) /*!< KS_T::REMAIN: RRMNG Mask */
#define KS_SCMBKEY0_SCMBKEY_Pos (0) /*!< KS_T::SCMBKEY0: SCMBKEY Position */
#define KS_SCMBKEY0_SCMBKEY_Msk (0xfffffffful << KS_SCMBKEY0_SCMBKEY_Pos) /*!< KS_T::SCMBKEY0: SCMBKEY Mask */
#define KS_SCMBKEY1_SCMBKEY_Pos (0) /*!< KS_T::SCMBKEY1: SCMBKEY Position */
#define KS_SCMBKEY1_SCMBKEY_Msk (0xfffffffful << KS_SCMBKEY1_SCMBKEY_Pos) /*!< KS_T::SCMBKEY1: SCMBKEY Mask */
#define KS_SCMBKEY2_SCMBKEY_Pos (0) /*!< KS_T::SCMBKEY2: SCMBKEY Position */
#define KS_SCMBKEY2_SCMBKEY_Msk (0xfffffffful << KS_SCMBKEY2_SCMBKEY_Pos) /*!< KS_T::SCMBKEY2: SCMBKEY Mask */
#define KS_SCMBKEY3_SCMBKEY_Pos (0) /*!< KS_T::SCMBKEY3: SCMBKEY Position */
#define KS_SCMBKEY3_SCMBKEY_Msk (0xfffffffful << KS_SCMBKEY3_SCMBKEY_Pos) /*!< KS_T::SCMBKEY3: SCMBKEY Mask */
#define KS_KEY0_KEY_Pos (0) /*!< KS_T::KEY0: KEY Position */
#define KS_KEY0_KEY_Msk (0xfffffffful << KS_KEY0_KEY_Pos) /*!< KS_T::KEY0: KEY Mask */
#define KS_KEY1_KEY_Pos (0) /*!< KS_T::KEY1: KEY Position */
#define KS_KEY1_KEY_Msk (0xfffffffful << KS_KEY1_KEY_Pos) /*!< KS_T::KEY1: KEY Mask */
#define KS_KEY2_KEY_Pos (0) /*!< KS_T::KEY2: KEY Position */
#define KS_KEY2_KEY_Msk (0xfffffffful << KS_KEY2_KEY_Pos) /*!< KS_T::KEY2: KEY Mask */
#define KS_KEY3_KEY_Pos (0) /*!< KS_T::KEY3: KEY Position */
#define KS_KEY3_KEY_Msk (0xfffffffful << KS_KEY3_KEY_Pos) /*!< KS_T::KEY3: KEY Mask */
#define KS_KEY4_KEY_Pos (0) /*!< KS_T::KEY4: KEY Position */
#define KS_KEY4_KEY_Msk (0xfffffffful << KS_KEY4_KEY_Pos) /*!< KS_T::KEY4: KEY Mask */
#define KS_KEY5_KEY_Pos (0) /*!< KS_T::KEY5: KEY Position */
#define KS_KEY5_KEY_Msk (0xfffffffful << KS_KEY5_KEY_Pos) /*!< KS_T::KEY5: KEY Mask */
#define KS_KEY6_KEY_Pos (0) /*!< KS_T::KEY6: KEY Position */
#define KS_KEY6_KEY_Msk (0xfffffffful << KS_KEY6_KEY_Pos) /*!< KS_T::KEY6: KEY Mask */
#define KS_KEY7_KEY_Pos (0) /*!< KS_T::KEY7: KEY Position */
#define KS_KEY7_KEY_Msk (0xfffffffful << KS_KEY7_KEY_Pos) /*!< KS_T::KEY7: KEY Mask */
#define KS_OTPSTS_KEY0_Pos (0) /*!< KS_T::OTPSTS: KEY0 Position */
#define KS_OTPSTS_KEY0_Msk (0x1ul << KS_OTPSTS_KEY0_Pos) /*!< KS_T::OTPSTS: KEY0 Mask */
#define KS_OTPSTS_KEY1_Pos (1) /*!< KS_T::OTPSTS: KEY1 Position */
#define KS_OTPSTS_KEY1_Msk (0x1ul << KS_OTPSTS_KEY1_Pos) /*!< KS_T::OTPSTS: KEY1 Mask */
#define KS_OTPSTS_KEY2_Pos (2) /*!< KS_T::OTPSTS: KEY2 Position */
#define KS_OTPSTS_KEY2_Msk (0x1ul << KS_OTPSTS_KEY2_Pos) /*!< KS_T::OTPSTS: KEY2 Mask */
#define KS_OTPSTS_KEY3_Pos (3) /*!< KS_T::OTPSTS: KEY3 Position */
#define KS_OTPSTS_KEY3_Msk (0x1ul << KS_OTPSTS_KEY3_Pos) /*!< KS_T::OTPSTS: KEY3 Mask */
#define KS_OTPSTS_KEY4_Pos (4) /*!< KS_T::OTPSTS: KEY4 Position */
#define KS_OTPSTS_KEY4_Msk (0x1ul << KS_OTPSTS_KEY4_Pos) /*!< KS_T::OTPSTS: KEY4 Mask */
#define KS_OTPSTS_KEY5_Pos (5) /*!< KS_T::OTPSTS: KEY5 Position */
#define KS_OTPSTS_KEY5_Msk (0x1ul << KS_OTPSTS_KEY5_Pos) /*!< KS_T::OTPSTS: KEY5 Mask */
#define KS_OTPSTS_KEY6_Pos (6) /*!< KS_T::OTPSTS: KEY6 Position */
#define KS_OTPSTS_KEY6_Msk (0x1ul << KS_OTPSTS_KEY6_Pos) /*!< KS_T::OTPSTS: KEY6 Mask */
#define KS_OTPSTS_KEY7_Pos (7) /*!< KS_T::OTPSTS: KEY7 Position */
#define KS_OTPSTS_KEY7_Msk (0x1ul << KS_OTPSTS_KEY7_Pos) /*!< KS_T::OTPSTS: KEY7 Mask */
#define KS_OTPSTS_KEY8_Pos (8) /*!< KS_T::OTPSTS: KEY8 Position */
#define KS_OTPSTS_KEY8_Msk (0x1ul << KS_OTPSTS_KEY8_Pos) /*!< KS_T::OTPSTS: KEY8 Mask */
#define KS_REMKCNT_RRMKCNT_Pos (0) /*!< KS_T::REMKCNT: RRMKCNT Position */
#define KS_REMKCNT_RRMKCNT_Msk (0x3ful << KS_REMKCNT_RRMKCNT_Pos) /*!< KS_T::REMKCNT: RRMKCNT Mask */
/**@}*/ /* KS_CONST */
/**@}*/ /* end of KS register group */
/**@}*/ /* end of REGISTER group */
#if defined ( __CC_ARM )
#pragma no_anon_unions
#endif
#endif /* __KS_REG_H__ */

1050
bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/ma35d1.h Normal file
View File

File diff suppressed because it is too large Load Diff

2850
bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/nfi_reg.h Normal file
View File

File diff suppressed because it is too large Load Diff

346
bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/otp_reg.h Normal file
View File

@ -0,0 +1,346 @@
/**************************************************************************//**
* @file otp_reg.h
* @brief OTP driver header file
*
* SPDX-License-Identifier: Apache-2.0
* @copyright (C) 2021 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __OTP_REG_H__
#define __OTP_REG_H__
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
/**
@addtogroup REGISTER Control Register
@{
*/
/**
@addtogroup OTP One-Time Programming Controller(OTP)
Memory Mapped Structure for OTP Controller
@{ */
typedef struct
{
/**
* @var OTP_T::CTL
* Offset: 0x00 OTP Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |START |OTP Start Control Bit
* | | |0 = No operation.
* | | |1 = Start the operation.
* |[7:4] |CMD |OTP Command Selection Bits
* | | |0x0 = Read command.
* | | |0x1 = Program command.
* | | |0x2 = Read only lock command.
* | | |0x3 = Fault Tolerance Mechanism command.
* | | |0x7 = Read checker command.
* | | |0xB = Read company ID
* | | |0xC = Read device ID
* | | |0xD = Read unique ID
* | | |Others = reserved.
* @var OTP_T::STS
* Offset: 0x04 OTP Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |BUSY |OTP Busy Flag (Read Only)
* | | |0 = OTP is idle or finished.
* | | |1 = OTP is busy.
* |[1] |PFF |OTP Program Fail Flag (Write 1 to Clear)
* | | |This bit is cleared by writing 1 and it has no effect by writing 0.
* | | |0 = No OTP programming operation failed.
* | | |1 = OTP programming operation is failed.
* |[2] |ADDRFF |OTP Address Fail Flag (Write 1 to Clear)
* | | |This bit is cleared by writing 1 and it has no effect by writing 0.
* | | |0 = OTP Address is legal.
* | | |1 = OTP Address is illegal.
* |[3] |FTMFF |OTP Fault Tolerance Mechanism Fail Flag (Write 1 to Clear)
* | | |This bit is set after Fault Tolerance Mechanism command is triggered and address is assigned to a block without available spare memory.
* | | |This bit is cleared by writing 1 and it has no effect by writing 0.
* | | |0 = No OTP fault tolerance mechanism failed.
* | | |1 = OTP fault tolerance mechanism failed.
* |[4] |CMDFF |OTP Command Fail Flag (Write 1 to Clear)
* | | |This bit is set after program command or Fault Tolerance Mechanism command is triggered and address is assigned a locked block.
* | | |This bit is cleared by writing 1 and it has no effect by writing 0.
* | | |0 = No OTP command failed.
* | | |1 = OTP command is failed.
* @var OTP_T::ADDR
* Offset: 0x08 OTP Address Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[11:0] |ADDR |OTP Address
* | | |OTP_ADDR register is byte addressable.
* | | |If OTP_ADDR is written to illegal region and START(OTP_CTL[0]) bit is triggered, ADDRFF(OTP_STS[2]) will be set and this operation will not be executed.
* @var OTP_T::DATA
* Offset: 0x0C OTP Data Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |DATA |OTP Data
* | | |Writing data to OTP_DATA register before OTP program operation.
* | | |Reading data from OTP_DATA register after OTP read operation.
* | | |Writing password, 0x55aa_92d6, before OTP read only lock operation or OTP Fault Tolerance Mechanism operation.
* @var OTP_T::USMSTS0
* Offset: 0x10 OTP Unused Spare Memory 0 Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[3:2] |BLK1 |Block 1 Unused Spare Memory
* | | |Maximum unused spare memory is 2.
* |[5:4] |BLK2 |Block 2 Unused Spare Memory
* | | |Maximum unused spare memory is 0.
* |[7:6] |BLK3 |Block 3 Unused Spare Memory
* | | |Maximum unused spare memory is 2.
* |[9:8] |BLK4 |Block 4 Unused Spare Memory
* | | |Maximum unused spare memory is 2.
* |[11:10] |BLK5 |Block 5 Unused Spare Memory
* | | |Maximum unused spare memory is 0.
* |[13:12] |BLK6 |Block 6 Unused Spare Memory
* | | |Maximum unused spare memory is 0.
* |[15:14] |BLK7 |Block 7 Unused Spare Memory
* | | |Maximum unused spare memory is 0.
* |[17:16] |BLK8 |Block 8 Unused Spare Memory
* | | |Maximum unused spare memory is 1.
* |[19:18] |BLK9 |Block 9 Unused Spare Memory
* | | |Maximum unused spare memory is 1.
* |[21:20] |BLK10 |Block 10 Unused Spare Memory
* | | |Maximum unused spare memory is 1.
* |[23:22] |BLK11 |Block 11 Unused Spare Memory
* | | |Maximum unused spare memory is 1.
* |[25:24] |BLK12 |Block 12 Unused Spare Memory
* | | |Maximum unused spare memory is 1.
* |[27:26] |BLK13 |Block 13 Unused Spare Memory
* | | |Maximum unused spare memory is 1.
* |[29:28] |BLK14 |Block 14 Unused Spare Memory
* | | |Maximum unused spare memory is 1.
* |[31:30] |BLK15 |Block 15 Unused Spare Memory
* | | |Maximum unused spare memory is 1.
* @var OTP_T::USMSTS1
* Offset: 0x14 OTP Unused Spare Memory 1 Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[1:0] |BLK16 |Block 16 Unused Spare Memory
* | | |Maximum unused spare memory is 1.
* @var OTP_T::OTP_CTL
* Offset: 0x800 Non-secure OTP Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |START |OTP Start Control Bit
* | | |0 = No operation.
* | | |1 = Start the operation.
* |[6:4] |CMD |OTP Command Selection Bits
* | | |0x0 = Read command.
* | | |0x1 = Program command.
* | | |0x2 = Read only lock command.
* | | |0x3 = Fault Tolerance Mechanism command.
* | | |0x7 = Read checker command.
* | | |0xB = Read company ID
* | | |0xC = Read device ID
* | | |0xD = Read unique ID
* | | |Others = reserved.
* @var OTP_T::OTP_STS
* Offset: 0x804 Non-secure OTP Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |BUSY |OTP Busy Flag (Read Only)
* | | |0 = OTP is idle or finished.
* | | |1 = OTP is busy.
* |[1] |PFF |OTP Program Fail Flag (Write 1 to Clear)
* | | |This bit is cleared by writing 1 and it has no effect by writing 0.
* | | |0 = No OTP programming operation failed.
* | | |1 = OTP programming operation failed.
* |[2] |ADDRFF |OTP Address Fail Flag (Write 1 to Clear)
* | | |This bit is cleared by writing 1 and it has no effect by writing 0.
* | | |0 = OTP Address is legal.
* | | |1 = OTP Address is illegal.
* |[3] |FTMFF |OTP Fault Tolerance Mechanism Fail Flag (Write 1 to Clear)
* | | |This bit is set after Fault Tolerance Mechanism command is triggered and address is assigned to a block without available spare memory.
* | | |This bit is cleared by writing 1 and it has no effect by writing 0.
* | | |0 = No OTP fault tolerance mechanism failed.
* | | |1 = OTP fault tolerance mechanism is failed.
* |[4] |CMDFF |OTP Command Fail Flag (Write 1 to Clear)
* | | |This bit is set after program command or Fault Tolerance Mechanism command is triggered and address is assigned to a locked block.
* | | |This bit is cleared by writing 1 and it has no effect by writing 0.
* | | |0 = No OTP command failed.
* | | |1 = OTP command failed.
* @var OTP_T::OTP_ADDR
* Offset: 0x808 Non-secure OTP Address Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[11:0] |ADDR |OTP Address
* | | |OTP_ADDR register is byte addressable.
* | | |If OTP_ADDR is written to illegal region and START(OTP_CTL[0]) bit is triggered, ADDRFF(OTP_STS[2]) will be set and this operation will not be executed.
* @var OTP_T::OTP_DATA
* Offset: 0x80C Non-secure OTP Data Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |DATA |OTP Data
* | | |Writing data to OTP_DATA register before OTP program operation.
* | | |Reading data from OTP_DATA register after OTP read operation.
* | | |Writing password, 0x55aa_92d6, before OTP read only lock operation or OTP Fault Tolerance Mechanism operation.
* @var OTP_T::OTP_USMSTS
* Offset: 0x810 Non-secure OTP Unused Spare Memory Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:6] |BLK3 |Block 3 Unused Spare Memory
* | | |Maximum unused spare memory is 2.
* |[9:8] |BLK4 |Block 4 Unused Spare Memory
* | | |Maximum unused spare memory is 2.
* |[15:14] |BLK7 |Block 7 Unused Spare Memory
* | | |Maximum unused spare memory is 0.
*/
__IO uint32_t CTL; /*!< [0x0000] OTP Control Register */
__IO uint32_t STS; /*!< [0x0004] OTP Status Register */
__IO uint32_t ADDR; /*!< [0x0008] OTP Address Register */
__IO uint32_t DATA; /*!< [0x000c] OTP Data Register */
__I uint32_t USMSTS0; /*!< [0x0010] OTP Unused Spare Memory 0 Status Register */
__I uint32_t USMSTS1; /*!< [0x0014] OTP Unused Spare Memory 1 Status Register */
__I uint32_t RESERVE0[506];
__IO uint32_t OTP_CTL; /*!< [0x0800] Non-secure OTP Control Register */
__IO uint32_t OTP_STS; /*!< [0x0804] Non-secure OTP Status Register */
__IO uint32_t OTP_ADDR; /*!< [0x0808] Non-secure OTP Address Register */
__IO uint32_t OTP_DATA; /*!< [0x080c] Non-secure OTP Data Register */
__I uint32_t OTP_USMSTS; /*!< [0x0810] Non-secure OTP Unused Spare Memory Status Register */
} OTP_T;
/**
@addtogroup OTP_CONST OTP Bit Field Definition
Constant Definitions for OTP Controller
@{ */
#define OTP_CTL_START_Pos (0) /*!< OTP_T::CTL: START Position */
#define OTP_CTL_START_Msk (0x1ul << OTP_CTL_START_Pos) /*!< OTP_T::CTL: START Mask */
#define OTP_CTL_CMD_Pos (4) /*!< OTP_T::CTL: CMD Position */
#define OTP_CTL_CMD_Msk (0xful << OTP_CTL_CMD_Pos) /*!< OTP_T::CTL: CMD Mask */
#define OTP_STS_BUSY_Pos (0) /*!< OTP_T::STS: BUSY Position */
#define OTP_STS_BUSY_Msk (0x1ul << OTP_STS_BUSY_Pos) /*!< OTP_T::STS: BUSY Mask */
#define OTP_STS_PFF_Pos (1) /*!< OTP_T::STS: PFF Position */
#define OTP_STS_PFF_Msk (0x1ul << OTP_STS_PFF_Pos) /*!< OTP_T::STS: PFF Mask */
#define OTP_STS_ADDRFF_Pos (2) /*!< OTP_T::STS: ADDRFF Position */
#define OTP_STS_ADDRFF_Msk (0x1ul << OTP_STS_ADDRFF_Pos) /*!< OTP_T::STS: ADDRFF Mask */
#define OTP_STS_FTMFF_Pos (3) /*!< OTP_T::STS: FTMFF Position */
#define OTP_STS_FTMFF_Msk (0x1ul << OTP_STS_FTMFF_Pos) /*!< OTP_T::STS: FTMFF Mask */
#define OTP_STS_CMDFF_Pos (4) /*!< OTP_T::STS: CMDFF Position */
#define OTP_STS_CMDFF_Msk (0x1ul << OTP_STS_CMDFF_Pos) /*!< OTP_T::STS: CMDFF Mask */
#define OTP_ADDR_ADDR_Pos (0) /*!< OTP_T::ADDR: ADDR Position */
#define OTP_ADDR_ADDR_Msk (0xffful << OTP_ADDR_ADDR_Pos) /*!< OTP_T::ADDR: ADDR Mask */
#define OTP_DATA_DATA_Pos (0) /*!< OTP_T::DATA: DATA Position */
#define OTP_DATA_DATA_Msk (0xfffffffful << OTP_DATA_DATA_Pos) /*!< OTP_T::DATA: DATA Mask */
#define OTP_USMSTS0_BLK1_Pos (2) /*!< OTP_T::USMSTS0: BLK1 Position */
#define OTP_USMSTS0_BLK1_Msk (0x3ul << OTP_USMSTS0_BLK1_Pos) /*!< OTP_T::USMSTS0: BLK1 Mask */
#define OTP_USMSTS0_BLK2_Pos (4) /*!< OTP_T::USMSTS0: BLK2 Position */
#define OTP_USMSTS0_BLK2_Msk (0x3ul << OTP_USMSTS0_BLK2_Pos) /*!< OTP_T::USMSTS0: BLK2 Mask */
#define OTP_USMSTS0_BLK3_Pos (6) /*!< OTP_T::USMSTS0: BLK3 Position */
#define OTP_USMSTS0_BLK3_Msk (0x3ul << OTP_USMSTS0_BLK3_Pos) /*!< OTP_T::USMSTS0: BLK3 Mask */
#define OTP_USMSTS0_BLK4_Pos (8) /*!< OTP_T::USMSTS0: BLK4 Position */
#define OTP_USMSTS0_BLK4_Msk (0x3ul << OTP_USMSTS0_BLK4_Pos) /*!< OTP_T::USMSTS0: BLK4 Mask */
#define OTP_USMSTS0_BLK5_Pos (10) /*!< OTP_T::USMSTS0: BLK5 Position */
#define OTP_USMSTS0_BLK5_Msk (0x3ul << OTP_USMSTS0_BLK5_Pos) /*!< OTP_T::USMSTS0: BLK5 Mask */
#define OTP_USMSTS0_BLK6_Pos (12) /*!< OTP_T::USMSTS0: BLK6 Position */
#define OTP_USMSTS0_BLK6_Msk (0x3ul << OTP_USMSTS0_BLK6_Pos) /*!< OTP_T::USMSTS0: BLK6 Mask */
#define OTP_USMSTS0_BLK7_Pos (14) /*!< OTP_T::USMSTS0: BLK7 Position */
#define OTP_USMSTS0_BLK7_Msk (0x3ul << OTP_USMSTS0_BLK7_Pos) /*!< OTP_T::USMSTS0: BLK7 Mask */
#define OTP_USMSTS0_BLK8_Pos (16) /*!< OTP_T::USMSTS0: BLK8 Position */
#define OTP_USMSTS0_BLK8_Msk (0x3ul << OTP_USMSTS0_BLK8_Pos) /*!< OTP_T::USMSTS0: BLK8 Mask */
#define OTP_USMSTS0_BLK9_Pos (18) /*!< OTP_T::USMSTS0: BLK9 Position */
#define OTP_USMSTS0_BLK9_Msk (0x3ul << OTP_USMSTS0_BLK9_Pos) /*!< OTP_T::USMSTS0: BLK9 Mask */
#define OTP_USMSTS0_BLK10_Pos (20) /*!< OTP_T::USMSTS0: BLK10 Position */
#define OTP_USMSTS0_BLK10_Msk (0x3ul << OTP_USMSTS0_BLK10_Pos) /*!< OTP_T::USMSTS0: BLK10 Mask */
#define OTP_USMSTS0_BLK11_Pos (22) /*!< OTP_T::USMSTS0: BLK11 Position */
#define OTP_USMSTS0_BLK11_Msk (0x3ul << OTP_USMSTS0_BLK11_Pos) /*!< OTP_T::USMSTS0: BLK11 Mask */
#define OTP_USMSTS0_BLK12_Pos (24) /*!< OTP_T::USMSTS0: BLK12 Position */
#define OTP_USMSTS0_BLK12_Msk (0x3ul << OTP_USMSTS0_BLK12_Pos) /*!< OTP_T::USMSTS0: BLK12 Mask */
#define OTP_USMSTS0_BLK13_Pos (26) /*!< OTP_T::USMSTS0: BLK13 Position */
#define OTP_USMSTS0_BLK13_Msk (0x3ul << OTP_USMSTS0_BLK13_Pos) /*!< OTP_T::USMSTS0: BLK13 Mask */
#define OTP_USMSTS0_BLK14_Pos (28) /*!< OTP_T::USMSTS0: BLK14 Position */
#define OTP_USMSTS0_BLK14_Msk (0x3ul << OTP_USMSTS0_BLK14_Pos) /*!< OTP_T::USMSTS0: BLK14 Mask */
#define OTP_USMSTS0_BLK15_Pos (30) /*!< OTP_T::USMSTS0: BLK15 Position */
#define OTP_USMSTS0_BLK15_Msk (0x3ul << OTP_USMSTS0_BLK15_Pos) /*!< OTP_T::USMSTS0: BLK15 Mask */
#define OTP_USMSTS1_BLK16_Pos (0) /*!< OTP_T::USMSTS1: BLK16 Position */
#define OTP_USMSTS1_BLK16_Msk (0x3ul << OTP_USMSTS1_BLK16_Pos) /*!< OTP_T::USMSTS1: BLK16 Mask */
#define OTP_OTP_CTL_START_Pos (0) /*!< OTP_T::OTP_CTL: START Position */
#define OTP_OTP_CTL_START_Msk (0x1ul << OTP_OTP_CTL_START_Pos) /*!< OTP_T::OTP_CTL: START Mask */
#define OTP_OTP_CTL_CMD_Pos (4) /*!< OTP_T::OTP_CTL: CMD Position */
#define OTP_OTP_CTL_CMD_Msk (0x7ul << OTP_OTP_CTL_CMD_Pos) /*!< OTP_T::OTP_CTL: CMD Mask */
#define OTP_OTP_STS_BUSY_Pos (0) /*!< OTP_T::OTP_STS: BUSY Position */
#define OTP_OTP_STS_BUSY_Msk (0x1ul << OTP_OTP_STS_BUSY_Pos) /*!< OTP_T::OTP_STS: BUSY Mask */
#define OTP_OTP_STS_PFF_Pos (1) /*!< OTP_T::OTP_STS: PFF Position */
#define OTP_OTP_STS_PFF_Msk (0x1ul << OTP_OTP_STS_PFF_Pos) /*!< OTP_T::OTP_STS: PFF Mask */
#define OTP_OTP_STS_ADDRFF_Pos (2) /*!< OTP_T::OTP_STS: ADDRFF Position */
#define OTP_OTP_STS_ADDRFF_Msk (0x1ul << OTP_OTP_STS_ADDRFF_Pos) /*!< OTP_T::OTP_STS: ADDRFF Mask */
#define OTP_OTP_STS_FTMFF_Pos (3) /*!< OTP_T::OTP_STS: FTMFF Position */
#define OTP_OTP_STS_FTMFF_Msk (0x1ul << OTP_OTP_STS_FTMFF_Pos) /*!< OTP_T::OTP_STS: FTMFF Mask */
#define OTP_OTP_STS_CMDFF_Pos (4) /*!< OTP_T::OTP_STS: CMDFF Position */
#define OTP_OTP_STS_CMDFF_Msk (0x1ul << OTP_OTP_STS_CMDFF_Pos) /*!< OTP_T::OTP_STS: CMDFF Mask */
#define OTP_OTP_ADDR_ADDR_Pos (0) /*!< OTP_T::OTP_ADDR: ADDR Position */
#define OTP_OTP_ADDR_ADDR_Msk (0xffful << OTP_OTP_ADDR_ADDR_Pos) /*!< OTP_T::OTP_ADDR: ADDR Mask */
#define OTP_OTP_DATA_DATA_Pos (0) /*!< OTP_T::OTP_DATA: DATA Position */
#define OTP_OTP_DATA_DATA_Msk (0xfffffffful << OTP_OTP_DATA_DATA_Pos) /*!< OTP_T::OTP_DATA: DATA Mask */
#define OTP_OTP_USMSTS_BLK3_Pos (6) /*!< OTP_T::OTP_USMSTS: BLK3 Position */
#define OTP_OTP_USMSTS_BLK3_Msk (0x3ul << OTP_OTP_USMSTS_BLK3_Pos) /*!< OTP_T::OTP_USMSTS: BLK3 Mask */
#define OTP_OTP_USMSTS_BLK4_Pos (8) /*!< OTP_T::OTP_USMSTS: BLK4 Position */
#define OTP_OTP_USMSTS_BLK4_Msk (0x3ul << OTP_OTP_USMSTS_BLK4_Pos) /*!< OTP_T::OTP_USMSTS: BLK4 Mask */
#define OTP_OTP_USMSTS_BLK7_Pos (14) /*!< OTP_T::OTP_USMSTS: BLK7 Position */
#define OTP_OTP_USMSTS_BLK7_Msk (0x3ul << OTP_OTP_USMSTS_BLK7_Pos) /*!< OTP_T::OTP_USMSTS: BLK7 Mask */
/**@}*/ /* OTP_CONST */
/**@}*/ /* end of OTP register group */
/**@}*/ /* end of REGISTER group */
#if defined ( __CC_ARM )
#pragma no_anon_unions
#endif
#endif //__OTP_REG_H__

1020
bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/pdma_reg.h Normal file
View File

File diff suppressed because it is too large Load Diff

76
bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/plm_reg.h Normal file
View File

@ -0,0 +1,76 @@
/**************************************************************************//**
* @file plm_reg.h
* @brief PLM register definition header file
*
* SPDX-License-Identifier: Apache-2.0
* @copyright (C) 2021 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __PLM_REG_H__
#define __PLM_REG_H__
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
/******************************************************************************/
/* Device Specific Peripheral registers structures */
/******************************************************************************/
/** @addtogroup REGISTER Control Register
@{
*/
/*---------------------- Product Life-cycle Manager -------------------------*/
/**
@addtogroup PLM Product Life-cycle Manager(PLM)
Memory Mapped Structure for PLM Controller
@{ */
typedef struct
{
/**
* @var PLM_T::STS
* Offset: 0x04 Product Life-cycle Status Register (TZNS)
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[2:0] |STAGE |Current Product Lifecycle Stage (Read Only)
* | | |0x1 = Develop Stage.
* | | |0x3 = Deployed Stage.
* | | |0x7 = RMA Stage.
* | | |0x5 = RMA Stage.
* | | |Others = Error stage.
* |[31:24] |RVCODE |Read Verify Code (Read Only)
* | | |Read Verify Code should be 0xA5
*/
__I uint32_t RESERVE0[1];
__I uint32_t STS; /*!< [0x0004] Product Life-cycle Status Register (TZNS) */
} PLM_T;
/**
@addtogroup PLM_CONST PLM Bit Field Definition
Constant Definitions for PLM Controller
@{ */
#define PLM_STS_STAGE_Pos (0) /*!< PLM_T::STS: STAGE Position */
#define PLM_STS_STAGE_Msk (0x7ul << PLM_STS_STAGE_Pos) /*!< PLM_T::STS: STAGE Mask */
#define PLM_STS_RVCODE_Pos (24) /*!< PLM_T::STS: RVCODE Position */
#define PLM_STS_RVCODE_Msk (0xfful << PLM_STS_RVCODE_Pos) /*!< PLM_T::STS: RVCODE Mask */
/**@}*/ /* PLM_CONST */
/**@}*/ /* end of PLM register group */
/**@}*/ /* end of REGISTER group */
#if defined ( __CC_ARM )
#pragma no_anon_unions
#endif
#endif /* __PLM_REG_H__ */

314
bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/qei_reg.h Normal file
View File

@ -0,0 +1,314 @@
/**************************************************************************//**
* @file qei_reg.h
* @brief QEI register definition header file
*
* SPDX-License-Identifier: Apache-2.0
* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __QEI_REG_H__
#define __QEI_REG_H__
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
/**
@addtogroup REGISTER Control Register
@{
*/
/**
@addtogroup QEI Quadrature Encoder Interface(QEI)
Memory Mapped Structure for QEI Controller
@{ */
typedef struct
{
/**
* @var QEI_T::CNT
* Offset: 0x00 QEI Counter Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |CNT |Quadrature Encoder Interface Counter
* | | |A 32-bit up/down counter
* | | |When an effective phase pulse is detected, this counter is increased by one if the bit DIRF (QEI_STATUS[8]) is one or decreased by one if the bit DIRF(QEI_STATUS[8]) is zero
* | | |This register performs an integrator which count value is proportional to the encoder position
* | | |The pulse counter may be initialized to a predetermined value by one of three events occurs:
* | | |1. Software is written if QEIEN (QEI_CTL[29]) = 0.
* | | |2. Compare-match event if QEIEN(QEI_CTL[29])=1 and QEI is in compare-counting mode.
* | | |3. Index signal change if QEIEN(QEI_CTL[29])=1 and IDXRLDEN (QEI_CTL[27])=1.
* @var QEI_T::CNTHOLD
* Offset: 0x04 QEI Counter Hold Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |CNTHOLD |Quadrature Encoder Interface Counter Hold
* | | |When bit HOLDCNT (QEI_CTL[24]) goes from low to high, the CNT(QEI_CNT[31:0]) is copied into CNTHOLD (QEI_CNTHOLD[31:0]) register.
* @var QEI_T::CNTLATCH
* Offset: 0x08 QEI Counter Index Latch Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |CNTLATCH |Quadrature Encoder Interface Counter Index Latch
* | | |When the IDXF (QEI_STATUS[0]) bit is set, the CNT(QEI_CNT[31:0]) is copied into CNTLATCH (QEI_CNTLATCH[31:0]) register.
* @var QEI_T::CNTCMP
* Offset: 0x0C QEI Counter Compare Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |CNTCMP |Quadrature Encoder Interface Counter Compare
* | | |If the QEI controller is in the compare-counting mode CMPEN (QEI_CTL[28]) =1, when the value of CNT(QEI_CNT[31:0]) matches CNTCMP(QEI_CNTCMP[31:0]), CMPF will be set
* | | |This register is software writable.
* @var QEI_T::CNTMAX
* Offset: 0x14 QEI Pre-set Maximum Count Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |CNTMAX |Quadrature Encoder Interface Preset Maximum Count
* | | |This register value determined by user stores the maximum value which may be the number of the QEI counter for the QEI controller compare-counting mode
* @var QEI_T::CTL
* Offset: 0x18 QEI Controller Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[2:0] |NFCLKSEL |Noise Filter Clock Pre-divide Selection
* | | |To determine the sampling frequency of the Noise Filter clock .
* | | |000 = QEI_CLK.
* | | |001 = QEI_CLK/2.
* | | |010 = QEI_CLK/4.
* | | |011 = QEI_CLK/16.
* | | |100 = QEI_CLK/32.
* | | |101 = QEI_CLK/64.
* |[3] |NFDIS |QEI Controller Input Noise Filter Disable Bit
* | | |0 = The noise filter of QEI controller Enabled.
* | | |1 = The noise filter of QEI controller Disabled.
* |[4] |CHAEN |QEA Input to QEI Controller Enable Bit
* | | |0 = QEA input to QEI Controller Disabled.
* | | |1 = QEA input to QEI Controller Enabled.
* |[5] |CHBEN |QEB Input to QEI Controller Enable Bit
* | | |0 = QEB input to QEI Controller Disabled.
* | | |1 = QEB input to QEI Controller Enabled.
* |[6] |IDXEN |IDX Input to QEI Controller Enable Bit
* | | |0 = IDX input to QEI Controller Disabled.
* | | |1 = IDX input to QEI Controller Enabled.
* |[9:8] |MODE |QEI Counting Mode Selection
* | | |There are four quadrature encoder pulse counter operation modes.
* | | |00 = X4 Free-counting Mode.
* | | |01 = X2 Free-counting Mode.
* | | |10 = X4 Compare-counting Mode.
* | | |11 = X2 Compare-counting Mode.
* |[12] |CHAINV |Inverse QEA Input Polarity
* | | |0 = Not inverse QEA input polarity.
* | | |1 = QEA input polarity is inversed to QEI controller.
* |[13] |CHBINV |Inverse QEB Input Polarity
* | | |0 = Not inverse QEB input polarity.
* | | |1 = QEB input polarity is inversed to QEI controller.
* |[14] |IDXINV |Inverse IDX Input Polarity
* | | |0 = Not inverse IDX input polarity.
* | | |1 = IDX input polarity is inversed to QEI controller.
* |[16] |OVUNIEN |OVUNF Trigger QEI Interrupt Enable Bit
* | | |0 = OVUNF can trigger QEI controller interrupt Disabled.
* | | |1 = OVUNF can trigger QEI controller interrupt Enabled.
* |[17] |DIRIEN |DIRCHGF Trigger QEI Interrupt Enable Bit
* | | |0 = DIRCHGF can trigger QEI controller interrupt Disabled.
* | | |1 = DIRCHGF can trigger QEI controller interrupt Enabled.
* |[18] |CMPIEN |CMPF Trigger QEI Interrupt Enable Bit
* | | |0 = CMPF can trigger QEI controller interrupt Disabled.
* | | |1 = CMPF can trigger QEI controller interrupt Enabled.
* |[19] |IDXIEN |IDXF Trigger QEI Interrupt Enable Bit
* | | |0 = The IDXF can trigger QEI interrupt Disabled.
* | | |1 = The IDXF can trigger QEI interrupt Enabled.
* |[20] |HOLDTMR0 |Hold QEI_CNT by Timer 0
* | | |0 = TIF (TIMER0_INTSTS[0]) has no effect on HOLDCNT.
* | | |1 = A rising edge of bit TIF(TIMER0_INTSTS[0]) in timer 0 sets HOLDCNT to 1.
* |[21] |HOLDTMR1 |Hold QEI_CNT by Timer 1
* | | |0 = TIF(TIMER1_INTSTS[0]) has no effect on HOLDCNT.
* | | |1 = A rising edge of bit TIF (TIMER1_INTSTS[0]) in timer 1 sets HOLDCNT to 1.
* |[22] |HOLDTMR2 |Hold QEI_CNT by Timer 2
* | | |0 = TIF(TIMER2_INTSTS[0]) has no effect on HOLDCNT.
* | | |1 = A rising edge of bit TIF(TIMER2_INTSTS[0]) in timer 2 sets HOLDCNT to 1.
* |[23] |HOLDTMR3 |Hold QEI_CNT by Timer 3
* | | |0 = TIF (TIMER3_INTSTS[0]) has no effect on HOLDCNT.
* | | |1 = A rising edge of bit TIF(TIMER3_INTSTS[0]) in timer 3 sets HOLDCNT to 1.
* |[24] |HOLDCNT |Hold QEI_CNT Control
* | | |When this bit is set from low to high, the CNT(QEI_CNT[31:0]) is copied into CNTHOLD(QEI_CNTHOLD[31:0])
* | | |This bit may be set by writing 1 to it or Timer0~Timer3 interrupt flag TIF (TIMERx_INTSTS[0]).
* | | |0 = No operation.
* | | |1 = QEI_CNT content is captured and stored in CNTHOLD(QEI_CNTHOLD[31:0]).
* | | |Note: This bit is automatically cleared after QEI_CNTHOLD holds QEI_CNT value.
* |[25] |IDXLATEN |Index Latch QEI_CNT Enable Bit
* | | |If this bit is set to high, the CNT(QEI_CNT[31:0]) content will be latched into CNTLATCH (QEI_CNTLATCH[31:0]) at every rising on signal CHX.
* | | |0 = The index signal latch QEI counter function Disabled.
* | | |1 = The index signal latch QEI counter function Enabled.
* |[27] |IDXRLDEN |Index Trigger QEI_CNT Reload Enable Bit
* | | |When this bit is high and a rising edge comes on signal CHX, the CNT(QEI_CNT[31:0]) will be reset to zero if the counter is in up-counting type (DIRF(QEI_STATUS[8]) = 1); while the CNT(QEI_CNT[31:0]) will be reloaded with CNTMAX (QEI_CNTMAX[31:0]) content if the counter is in down-counting type (DIRF(QEI_STATUS[8]) = 0).
* | | |0 = Reload function Disabled.
* | | |1 = QEI_CNT re-initialized by Index signal Enabled.
* |[28] |CMPEN |The Compare Function Enable Bit
* | | |The compare function in QEI controller is to compare the dynamic counting QEI_CNT with the compare register CNTCMP( QEI_CNTCMP[31:0]), if CNT(QEI_CNT[31:0]) reaches CNTCMP( QEI_CNTCMP[31:0]), the flag CMPF will be set.
* | | |0 = Compare function Disabled.
* | | |1 = Compare function Enabled.
* |[29] |QEIEN |Quadrature Encoder Interface Controller Enable Bit
* | | |0 = QEI controller function Disabled.
* | | |1 = QEI controller function Enabled.
* @var QEI_T::STATUS
* Offset: 0x2C QEI Controller Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |IDXF |IDX Detected Flag
* | | |When the QEI controller detects a rising edge on signal CHX it will set flag IDXF to high.
* | | |0 = No rising edge detected on signal CHX.
* | | |1 = A rising edge occurs on signal CHX.
* | | |Note: This bit is only cleared by writing 1 to it.
* |[1] |CMPF |Compare-match Flag
* | | |If the QEI compare function is enabled, the flag is set by hardware while QEI counter up or down counts and reach to the CNTCMP(QEI_CNTCMP[31:0]).
* | | |0 = QEI counter does not match with CNTCMP(QEI_CNTCMP[31:0]).
* | | |1 = QEI counter counts to the same as CNTCMP(QEI_CNTCMP[31:0]).
* | | |Note: This bit is only cleared by writing 1 to it.
* |[2] |OVUNF |QEI Counter Overflow or Underflow Flag
* | | |Flag is set by hardware while CNT(QEI_CNT[31:0]) overflows from 0xFFFF_FFFF to zero in free-counting mode or from the CNTMAX (QEI_CNTMAX[31:0]) to zero in compare-counting mode
* | | |Similarly, the flag is set while QEI counter underflows from zero to 0xFFFF_FFFF or CNTMAX (QEI_CNTMAX[31:0]).
* | | |0 = No overflow or underflow occurs in QEI counter.
* | | |1 = QEI counter occurs counting overflow or underflow.
* | | |Note: This bit is only cleared by writing 1 to it.
* |[3] |DIRCHGF |Direction Change Flag
* | | |Flag is set by hardware while QEI counter counting direction is changed.
* | | |Software can clear this bit by writing 1 to it.
* | | |0 = No change in QEI counter counting direction.
* | | |1 = QEI counter counting direction is changed.
* | | |Note: This bit is only cleared by writing 1 to it.
* |[8] |DIRF |QEI Counter Counting Direction Indication
* | | |0 = QEI Counter is in down-counting.
* | | |1 = QEI Counter is in up-counting.
* | | |Note: This bit is set/reset by hardware according to the phase detection between CHA and CHB.
*/
__IO uint32_t CNT; /*!< [0x0000] QEI Counter Register */
__IO uint32_t CNTHOLD; /*!< [0x0004] QEI Counter Hold Register */
__IO uint32_t CNTLATCH; /*!< [0x0008] QEI Counter Index Latch Register */
__IO uint32_t CNTCMP; /*!< [0x000c] QEI Counter Compare Register */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE0[1];
/// @endcond //HIDDEN_SYMBOLS
__IO uint32_t CNTMAX; /*!< [0x0014] QEI Pre-set Maximum Count Register */
__IO uint32_t CTL; /*!< [0x0018] QEI Controller Control Register */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE1[4];
/// @endcond //HIDDEN_SYMBOLS
__IO uint32_t STATUS; /*!< [0x002c] QEI Controller Status Register */
} QEI_T;
/**
@addtogroup QEI_CONST QEI Bit Field Definition
Constant Definitions for QEI Controller
@{ */
#define QEI_CNT_CNT_Pos (0) /*!< QEI_T::CNT: CNT Position */
#define QEI_CNT_CNT_Msk (0xfffffffful << QEI_CNT_CNT_Pos) /*!< QEI_T::CNT: CNT Mask */
#define QEI_CNTHOLD_CNTHOLD_Pos (0) /*!< QEI_T::CNTHOLD: CNTHOLD Position */
#define QEI_CNTHOLD_CNTHOLD_Msk (0xfffffffful << QEI_CNTHOLD_CNTHOLD_Pos) /*!< QEI_T::CNTHOLD: CNTHOLD Mask */
#define QEI_CNTLATCH_CNTLATCH_Pos (0) /*!< QEI_T::CNTLATCH: CNTLATCH Position */
#define QEI_CNTLATCH_CNTLATCH_Msk (0xfffffffful << QEI_CNTLATCH_CNTLATCH_Pos) /*!< QEI_T::CNTLATCH: CNTLATCH Mask */
#define QEI_CNTCMP_CNTCMP_Pos (0) /*!< QEI_T::CNTCMP: CNTCMP Position */
#define QEI_CNTCMP_CNTCMP_Msk (0xfffffffful << QEI_CNTCMP_CNTCMP_Pos) /*!< QEI_T::CNTCMP: CNTCMP Mask */
#define QEI_CNTMAX_CNTMAX_Pos (0) /*!< QEI_T::CNTMAX: CNTMAX Position */
#define QEI_CNTMAX_CNTMAX_Msk (0xfffffffful << QEI_CNTMAX_CNTMAX_Pos) /*!< QEI_T::CNTMAX: CNTMAX Mask */
#define QEI_CTL_NFCLKSEL_Pos (0) /*!< QEI_T::CTL: NFCLKSEL Position */
#define QEI_CTL_NFCLKSEL_Msk (0x7ul << QEI_CTL_NFCLKSEL_Pos) /*!< QEI_T::CTL: NFCLKSEL Mask */
#define QEI_CTL_NFDIS_Pos (3) /*!< QEI_T::CTL: NFDIS Position */
#define QEI_CTL_NFDIS_Msk (0x1ul << QEI_CTL_NFDIS_Pos) /*!< QEI_T::CTL: NFDIS Mask */
#define QEI_CTL_CHAEN_Pos (4) /*!< QEI_T::CTL: CHAEN Position */
#define QEI_CTL_CHAEN_Msk (0x1ul << QEI_CTL_CHAEN_Pos) /*!< QEI_T::CTL: CHAEN Mask */
#define QEI_CTL_CHBEN_Pos (5) /*!< QEI_T::CTL: CHBEN Position */
#define QEI_CTL_CHBEN_Msk (0x1ul << QEI_CTL_CHBEN_Pos) /*!< QEI_T::CTL: CHBEN Mask */
#define QEI_CTL_IDXEN_Pos (6) /*!< QEI_T::CTL: IDXEN Position */
#define QEI_CTL_IDXEN_Msk (0x1ul << QEI_CTL_IDXEN_Pos) /*!< QEI_T::CTL: IDXEN Mask */
#define QEI_CTL_MODE_Pos (8) /*!< QEI_T::CTL: MODE Position */
#define QEI_CTL_MODE_Msk (0x3ul << QEI_CTL_MODE_Pos) /*!< QEI_T::CTL: MODE Mask */
#define QEI_CTL_CHAINV_Pos (12) /*!< QEI_T::CTL: CHAINV Position */
#define QEI_CTL_CHAINV_Msk (0x1ul << QEI_CTL_CHAINV_Pos) /*!< QEI_T::CTL: CHAINV Mask */
#define QEI_CTL_CHBINV_Pos (13) /*!< QEI_T::CTL: CHBINV Position */
#define QEI_CTL_CHBINV_Msk (0x1ul << QEI_CTL_CHBINV_Pos) /*!< QEI_T::CTL: CHBINV Mask */
#define QEI_CTL_IDXINV_Pos (14) /*!< QEI_T::CTL: IDXINV Position */
#define QEI_CTL_IDXINV_Msk (0x1ul << QEI_CTL_IDXINV_Pos) /*!< QEI_T::CTL: IDXINV Mask */
#define QEI_CTL_OVUNIEN_Pos (16) /*!< QEI_T::CTL: OVUNIEN Position */
#define QEI_CTL_OVUNIEN_Msk (0x1ul << QEI_CTL_OVUNIEN_Pos) /*!< QEI_T::CTL: OVUNIEN Mask */
#define QEI_CTL_DIRIEN_Pos (17) /*!< QEI_T::CTL: DIRIEN Position */
#define QEI_CTL_DIRIEN_Msk (0x1ul << QEI_CTL_DIRIEN_Pos) /*!< QEI_T::CTL: DIRIEN Mask */
#define QEI_CTL_CMPIEN_Pos (18) /*!< QEI_T::CTL: CMPIEN Position */
#define QEI_CTL_CMPIEN_Msk (0x1ul << QEI_CTL_CMPIEN_Pos) /*!< QEI_T::CTL: CMPIEN Mask */
#define QEI_CTL_IDXIEN_Pos (19) /*!< QEI_T::CTL: IDXIEN Position */
#define QEI_CTL_IDXIEN_Msk (0x1ul << QEI_CTL_IDXIEN_Pos) /*!< QEI_T::CTL: IDXIEN Mask */
#define QEI_CTL_HOLDTMR0_Pos (20) /*!< QEI_T::CTL: HOLDTMR0 Position */
#define QEI_CTL_HOLDTMR0_Msk (0x1ul << QEI_CTL_HOLDTMR0_Pos) /*!< QEI_T::CTL: HOLDTMR0 Mask */
#define QEI_CTL_HOLDTMR1_Pos (21) /*!< QEI_T::CTL: HOLDTMR1 Position */
#define QEI_CTL_HOLDTMR1_Msk (0x1ul << QEI_CTL_HOLDTMR1_Pos) /*!< QEI_T::CTL: HOLDTMR1 Mask */
#define QEI_CTL_HOLDTMR2_Pos (22) /*!< QEI_T::CTL: HOLDTMR2 Position */
#define QEI_CTL_HOLDTMR2_Msk (0x1ul << QEI_CTL_HOLDTMR2_Pos) /*!< QEI_T::CTL: HOLDTMR2 Mask */
#define QEI_CTL_HOLDTMR3_Pos (23) /*!< QEI_T::CTL: HOLDTMR3 Position */
#define QEI_CTL_HOLDTMR3_Msk (0x1ul << QEI_CTL_HOLDTMR3_Pos) /*!< QEI_T::CTL: HOLDTMR3 Mask */
#define QEI_CTL_HOLDCNT_Pos (24) /*!< QEI_T::CTL: HOLDCNT Position */
#define QEI_CTL_HOLDCNT_Msk (0x1ul << QEI_CTL_HOLDCNT_Pos) /*!< QEI_T::CTL: HOLDCNT Mask */
#define QEI_CTL_IDXLATEN_Pos (25) /*!< QEI_T::CTL: IDXLATEN Position */
#define QEI_CTL_IDXLATEN_Msk (0x1ul << QEI_CTL_IDXLATEN_Pos) /*!< QEI_T::CTL: IDXLATEN Mask */
#define QEI_CTL_IDXRLDEN_Pos (27) /*!< QEI_T::CTL: IDXRLDEN Position */
#define QEI_CTL_IDXRLDEN_Msk (0x1ul << QEI_CTL_IDXRLDEN_Pos) /*!< QEI_T::CTL: IDXRLDEN Mask */
#define QEI_CTL_CMPEN_Pos (28) /*!< QEI_T::CTL: CMPEN Position */
#define QEI_CTL_CMPEN_Msk (0x1ul << QEI_CTL_CMPEN_Pos) /*!< QEI_T::CTL: CMPEN Mask */
#define QEI_CTL_QEIEN_Pos (29) /*!< QEI_T::CTL: QEIEN Position */
#define QEI_CTL_QEIEN_Msk (0x1ul << QEI_CTL_QEIEN_Pos) /*!< QEI_T::CTL: QEIEN Mask */
#define QEI_STATUS_IDXF_Pos (0) /*!< QEI_T::STATUS: IDXF Position */
#define QEI_STATUS_IDXF_Msk (0x1ul << QEI_STATUS_IDXF_Pos) /*!< QEI_T::STATUS: IDXF Mask */
#define QEI_STATUS_CMPF_Pos (1) /*!< QEI_T::STATUS: CMPF Position */
#define QEI_STATUS_CMPF_Msk (0x1ul << QEI_STATUS_CMPF_Pos) /*!< QEI_T::STATUS: CMPF Mask */
#define QEI_STATUS_OVUNF_Pos (2) /*!< QEI_T::STATUS: OVUNF Position */
#define QEI_STATUS_OVUNF_Msk (0x1ul << QEI_STATUS_OVUNF_Pos) /*!< QEI_T::STATUS: OVUNF Mask */
#define QEI_STATUS_DIRCHGF_Pos (3) /*!< QEI_T::STATUS: DIRCHGF Position */
#define QEI_STATUS_DIRCHGF_Msk (0x1ul << QEI_STATUS_DIRCHGF_Pos) /*!< QEI_T::STATUS: DIRCHGF Mask */
#define QEI_STATUS_DIRF_Pos (8) /*!< QEI_T::STATUS: DIRF Position */
#define QEI_STATUS_DIRF_Msk (0x1ul << QEI_STATUS_DIRF_Pos) /*!< QEI_T::STATUS: DIRF Mask */
/**@}*/ /* QEI_CONST */
/**@}*/ /* end of QEI register group */
/**@}*/ /* end of REGISTER group */
#if defined ( __CC_ARM )
#pragma no_anon_unions
#endif
#endif /* __QEI_REG_H__ */

661
bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/qspi_reg.h Normal file
View File

@ -0,0 +1,661 @@
/**************************************************************************//**
* @file qspi_reg.h
* @brief QSPI register definition header file
*
* SPDX-License-Identifier: Apache-2.0
* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __QSPI_REG_H__
#define __QSPI_REG_H__
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
/**
@addtogroup REGISTER Control Register
@{
*/
/**
@addtogroup QSPI Serial Peripheral Interface Controller(QSPI)
Memory Mapped Structure for QSPI Controller
@{ */
typedef struct
{
/**
* @var QSPI_T::CTL
* Offset: 0x00 QSPI Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |SPIEN |QSPI Transfer Control Enable Bit
* | | |In Master mode, the transfer will start when there is data in the FIFO buffer after this bit is set to 1
* | | |In Slave mode, this device is ready to receive data when this bit is set to 1.
* | | |0 = Transfer control Disabled.
* | | |1 = Transfer control Enabled.
* | | |Note: Before changing the configurations of QSPIx_CTL, QSPIx_CLKDIV, QSPIx_SSCTL and QSPIx_FIFOCTL, registers, user shall clear the SPIEN (QSPIx_CTL[0]) and confirm the SPIENSTS (QSPIx_STATUS[15]) is 0.
* |[1] |RXNEG |Receive on Negative Edge
* | | |0 = Received data input signal is latched on the rising edge of QSPI bus clock.
* | | |1 = Received data input signal is latched on the falling edge of QSPI bus clock.
* |[2] |TXNEG |Transmit on Negative Edge
* | | |0 = Transmitted data output signal is changed on the rising edge of QSPI bus clock.
* | | |1 = Transmitted data output signal is changed on the falling edge of QSPI bus clock.
* | | |Note: In TX DTR mode, TXNEG equals to CLKPOL (QSPI_CTL[3]).
* |[3] |CLKPOL |Clock Polarity
* | | |0 = QSPI bus clock is idle low.
* | | |1 = QSPI bus clock is idle high.
* |[7:4] |SUSPITV |Suspend Interval for Master Only
* | | |The four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer
* | | |The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word
* | | |The default value is 0x3
* | | |The period of the suspend interval is obtained according to the following equation.
* | | |(SUSPITV[3:0] + 0.5) * period of QSPI_CLK clock cycle
* | | |Example:
* | | |SUSPITV = 0x0 : 0.5 QSPI_CLK clock cycle.
* | | |SUSPITV = 0x1 : 1.5 QSPI_CLK clock cycle.
* | | |
* | | |SUSPITV = 0xE : 14.5 QSPI_CLK clock cycle.
* | | |SUSPITV = 0xF : 15.5 QSPI_CLK clock cycle.
* | | |Note: In TX DTR mode, SUSPITV equals to 0x0.
* |[12:8] |DWIDTH |Data Width
* | | |This field specifies how many bits can be transmitted / received in one transaction
* | | |The minimum bit length is 8 bits and can up to 32 bits.
* | | |DWIDTH = 0x08 : 8 bits.
* | | |DWIDTH = 0x09 : 9 bits.
* | | |
* | | |DWIDTH = 0x1F : 31 bits.
* | | |DWIDTH = 0x00 : 32 bits.
* | | |Note 1: This bit field will decide the depth of TX/RX FIFO configuration in SPI mode
* | | |Therefore, changing this bit field will clear TX/RX FIFO by hardware automatically.
* | | |Note 2: When user changes data width, the clear functions of TXFIFO and RXFIFO will be triggered by hardware automatically
* | | |User can read status register FIFOCLR (QSPI_STATUS[22]) to check status of clear function of TXFIFO and RXFIFO
* | | |After status register FIFOCLR is 0, user can write TXFIFO or read RXFIFO correctly.
* |[13] |LSB |Send LSB First
* | | |0 = The MSB, which bit of transmit/receive register depends on the setting of DWIDTH, is transmitted/received first.
* | | |1 = The LSB, bit 0 of the QSPIx TX register, is sent first to the QSPI data output pin, and the first bit received from the QSPI data input pin will be put in the LSB position of the RX register (bit 0 of QSPIx_RX).
* |[14] |HALFDPX |QSPI Half-duplex Transfer Enable Bit
* | | |This bit is used to select full-duplex or half-duplex for QSPI transfer
* | | |The bit field DATDIR (QSPIx_CTL[20]) can be used to set the data direction in half-duplex transfer.
* | | |0 = QSPI operates in full-duplex transfer Disabled.
* | | |1 = QSPI operates in half-duplex transfer Enabled.
* |[15] |RXONLY |Receive-only Mode Enable Bit for Master Only
* | | |This bit field is only available in Master mode
* | | |In receive-only mode, QSPI Master will generate QSPI bus clock continuously for receiving data bit from SPI slave device and assert the BUSY status.
* | | |0 = Receive-only mode Disabled.
* | | |1 = Receive-only mode Enabled.
* |[16] |TWOBIT |2-bit Transfer Mode Enable Bit
* | | |0 = 2-bit transfer mode Disabled.
* | | |1 = 2-bit transfer mode Enabled.
* | | |Note: When 2-bit transfer mode is enabled, the first serial transmitted bit data is from the first FIFO buffer data, and the 2nd serial transmitted bit data is from the second FIFO buffer data
* | | |As the same as transmitted function, the first received bit data is stored into the first FIFO buffer and the 2nd received bit data is stored into the second FIFO buffer at the same time.
* |[17] |UNITIEN |Unit Transfer Interrupt Enable Bit
* | | |0 = QSPI unit transfer interrupt Disabled.
* | | |1 = QSPI unit transfer interrupt Enabled.
* |[18] |SLAVE |Slave Mode Control
* | | |0 = Master mode.
* | | |1 = Slave mode.
* |[19] |REORDER |Byte Reorder Function Enable Bit
* | | |0 = Byte Reorder function Disabled.
* | | |1 = Byte Reorder function Enabled
* | | |A byte suspend interval will be inserted among each byte
* | | |The period of the byte suspend interval depends on the setting of SUSPITV.
* | | |Note: Byte Reorder function is only available if DWIDTH is defined as 16, 24, and 32 bits.
* |[20] |DATDIR |Data Port Direction Control
* | | |This bit is used to select the data input/output direction in half-duplex transfer and Dual/Quad transfer
* | | |0 = QSPI data is input direction.
* | | |1 = QSPI data is output direction.
* |[21] |DUALIOEN |Dual I/O Mode Enable Bit
* | | |0 = Dual I/O mode Disabled.
* | | |1 = Dual I/O mode Enabled.
* |[22] |QUADIOEN |Quad I/O Mode Enable Bit
* | | |0 = Quad I/O mode Disabled.
* | | |1 = Quad I/O mode Enabled.
* |[23] |DTREN |Transmit Double Transfer Rate Mode Enable Bit
* | | |In master mode, QSPI DTR function usually uses for SPI Flash controller, which this SPI Flash supports DTR commands as 0xED, 0xBD, and 0x0D.
* | | |0 = DTR mode Disabled.
* | | |1 = DTR mode Enabled.
* | | |Note: QSPI master mode supports DTR mode, and QSPI slave mode does not support this mode.
* @var QSPI_T::CLKDIV
* Offset: 0x04 QSPI Clock Divider Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[8:0] |DIVIDER |Clock Divider
* | | |The value in this field is the frequency divider for generating the peripheral clock, fspi_eclk, and the QSPI bus clock of QSPI Master
* | | |The frequency is obtained according to the following equation.
* | | |where
* | | |is the peripheral clock source, which is defined in the clock control register, CLK_CLKSEL4.
* | | |Note: The time interval must be larger than or equal 5 peripheral clock cycles between releasing QSPI IP software reset and setting this clock divider register.
* @var QSPI_T::SSCTL
* Offset: 0x08 QSPI Slave Select Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |SS0 |Slave Selection Control 0 for Master Only
* | | |If AUTOSS bit is cleared to 0,
* | | |0 = set the QSPIx_SS0 line to inactive state.
* | | |1 = set the QSPIx_SS0 line to active state.
* | | |If the AUTOSS bit is set to 1,
* | | |0 = Keep the QSPIx_SS0 line at inactive state.
* | | |1 = QSPIx_SS0 line will be automatically driven to active state for the duration of data transfer, and will be driven to inactive state for the rest of the time
* | | |The active state of QSPIx_SS0 is specified in SSACTPOL (QSPIx_SSCTL[2]).
* |[1] |SS1 |Slave Selection Control 1 for Master Only
* | | |If AUTOSS bit is cleared to 0,
* | | |0 = set the QSPIx_SS1 line to inactive state.
* | | |1 = set the QSPIx_SS1 line to active state.
* | | |If the AUTOSS bit is set to 1,
* | | |0 = Keep the QSPIx_SS1 line at inactive state.
* | | |1 = QSPIx_SS1 line will be automatically driven to active state for the duration of data transfer, and will be driven to inactive state for the rest of the time
* | | |The active state of QSPIx_SS1 is specified in SSACTPOL (QSPIx_SSCTL[2]).
* |[2] |SSACTPOL |Slave Selection Active Polarity
* | | |This bit defines the active polarity of slave selection signal (QSPIx_SS0 and QSPIx_SS1).
* | | |0 = The slave selection signal QSPIx_SS0/ QSPIx_SS1 is active low.
* | | |1 = The slave selection signal QSPIx_SS0/ QSPIx_SS1 is active high.
* |[3] |AUTOSS |Automatic Slave Selection Function Enable Bit for Master Only
* | | |0 = Automatic slave selection function Disabled
* | | |Slave selection signal will be asserted/de-asserted according to SS0 (QSPIx_SSCTL[0]) or SS1 (QSPIx_SSCTL[1]).
* | | |1 = Automatic slave selection function Enabled.
* |[4] |SLV3WIRE |Slave 3-wire Mode Enable Bit
* | | |In Slave 3-wire mode, the QSPI controller can work with 3-wire interface including QSPIx_CLK, QSPIx_MISO and QSPIx_MOSI pins.
* | | |0 = 4-wire bi-direction interface Disabled.
* | | |1 = 3-wire bi-direction interface Enabled.
* |[5] |SLVTOIEN |Slave Mode Time-out Interrupt Enable Bit
* | | |0 = Slave mode time-out interrupt Disabled.
* | | |1 = Slave mode time-out interrupt Enabled.
* |[6] |SLVTORST |Slave Mode Time-out Reset Control
* | | |0 = When Slave mode time-out event occurs, the TX and RX control circuit will not be reset.
* | | |1 = When Slave mode time-out event occurs, the TX and RX control circuit will be reset by hardware.
* |[8] |SLVBEIEN |Slave Mode Bit Count Error Interrupt Enable Bit
* | | |0 = Slave mode bit count error interrupt Disabled.
* | | |1 = Slave mode bit count error interrupt Enabled.
* |[9] |SLVURIEN |Slave Mode TX Under Run Interrupt Enable Bit
* | | |0 = Slave mode TX under run interrupt Disabled.
* | | |1 = Slave mode TX under run interrupt Enabled.
* |[12] |SSACTIEN |Slave Select Active Interrupt Enable Bit
* | | |0 = Slave select active interrupt Disabled.
* | | |1 = Slave select active interrupt Enabled.
* |[13] |SSINAIEN |Slave Select Inactive Interrupt Enable Bit
* | | |0 = Slave select inactive interrupt Disabled.
* | | |1 = Slave select inactive interrupt Enabled.
* |[31:16] |SLVTOCNT |Slave Mode Time-out Period
* | | |In Slave mode, these bits indicate the time-out period when there is bus clock input during slave select active
* | | |The clock source of the time-out counter is Slave peripheral clock
* | | |If the value is 0, it indicates the slave mode time-out function is disabled.
* @var QSPI_T::PDMACTL
* Offset: 0x0C QSPI PDMA Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |TXPDMAEN |Transmit PDMA Enable Bit
* | | |0 = Transmit PDMA function Disabled.
* | | |1 = Transmit PDMA function Enabled.
* | | |Note 1: In QSPI Master mode with full duplex transfer, if both TX and RX PDMA functions are enabled, RX PDMA function cannot be enabled prior to TX PDMA function
* | | |User can enable TX PDMA function firstly or enable both functions simultaneously.
* | | |Note 2: In QSPI Master mode with full duplex transfer, if both TX and RX PDMA functions are enabled, TX PDMA function cannot be disabled prior to RX PDMA function
* | | |User can disable RX PDMA function firstly or disable both functions simultaneously.
* |[1] |RXPDMAEN |Receive PDMA Enable Bit
* | | |0 = Receive PDMA function Disabled.
* | | |1 = Receive PDMA function Enabled.
* |[2] |PDMARST |PDMA Reset
* | | |0 = No effect.
* | | |1 = Reset the PDMA control logic of the QSPI controller. This bit will be automatically cleared to 0.
* @var QSPI_T::FIFOCTL
* Offset: 0x10 QSPI FIFO Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |RXRST |Receive Reset
* | | |0 = No effect.
* | | |1 = Reset receive FIFO pointer and receive circuit
* | | |The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1
* | | |This bit will be cleared to 0 by hardware about 3 system clock cycles + 2 peripheral clock cycles after it is set to 1
* | | |User can read TXRXRST (QSPIx_STATUS[23]) to check if reset is accomplished or not.
* |[1] |TXRST |Transmit Reset
* | | |0 = No effect.
* | | |1 = Reset transmit FIFO pointer and transmit circuit
* | | |The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1
* | | |This bit will be cleared to 0 by hardware about 3 system clock cycles + 2 peripheral clock cycles after it is set to 1
* | | |User can read TXRXRST (QSPIx_STATUS[23]) to check if reset is accomplished or not.
* | | |Note: If TX underflow event occurs in QSPI Slave mode, this bit can be used to make QSPI return to idle state.
* |[2] |RXTHIEN |Receive FIFO Threshold Interrupt Enable Bit
* | | |0 = RX FIFO threshold interrupt Disabled.
* | | |1 = RX FIFO threshold interrupt Enabled.
* |[3] |TXTHIEN |Transmit FIFO Threshold Interrupt Enable Bit
* | | |0 = TX FIFO threshold interrupt Disabled.
* | | |1 = TX FIFO threshold interrupt Enabled.
* |[4] |RXTOIEN |Receive Time-out Interrupt Enable Bit
* | | |0 = Receive time-out interrupt Disabled.
* | | |1 = Receive time-out interrupt Enabled.
* |[5] |RXOVIEN |Receive FIFO Overrun Interrupt Enable Bit
* | | |0 = Receive FIFO overrun interrupt Disabled.
* | | |1 = Receive FIFO overrun interrupt Enabled.
* |[6] |TXUFPOL |TX Underflow Data Polarity
* | | |0 = The QSPI data out is keep 0 if there is TX underflow event in Slave mode.
* | | |1 = The QSPI data out is keep 1 if there is TX underflow event in Slave mode.
* | | |Note 1: The TX underflow event occurs if there is no any data in TX FIFO when the slave selection signal is active.
* | | |Note 2: When TX underflow event occurs, QSPIx_MISO pin state will be determined by this setting even though TX FIFO is not empty afterward
* | | |Data stored in TX FIFO will be sent through QSPIx_MISO pin in the next transfer frame.
* |[7] |TXUFIEN |TX Underflow Interrupt Enable Bit
* | | |When TX underflow event occurs in Slave mode, TXUFIF (QSPIx_STATUS[19]) will be set to 1
* | | |This bit is used to enable the TX underflow interrupt.
* | | |0 = Slave TX underflow interrupt Disabled.
* | | |1 = Slave TX underflow interrupt Enabled.
* |[8] |RXFBCLR |Receive FIFO Buffer Clear
* | | |0 = No effect.
* | | |1 = Clear receive FIFO pointer
* | | |The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1
* | | |This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1.
* | | |Note: The RX shift register will not be cleared.
* |[9] |TXFBCLR |Transmit FIFO Buffer Clear
* | | |0 = No effect.
* | | |1 = Clear transmit FIFO pointer
* | | |The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1
* | | |This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1.
* | | |Note: The TX shift register will not be cleared.
* |[10] |SLVBERX |RX FIFO Write Data Enable Bit When Slave Mode Bit Count Error
* | | |0 = Uncompleted RX data will be dropped from RX FIFO when bit count error event happen in SPI slave mode.
* | | |1 = Uncompleted RX data will be written into RX FIFO when bit count error event happen in SPI slave mode
* | | |User can read SLVBENUM (QSPIx_STATUS2[29:24]) to know that the effective bit number of uncompleted RX data when SPI slave bit count error happened.
* |[26:24] |RXTH |Receive FIFO Threshold
* | | |If the valid data count of the receive FIFO buffer is larger than the RXTH setting, the RXTHIF bit will be set to 1, else the RXTHIF bit will be cleared to 0.
* |[30:28] |TXTH |Transmit FIFO Threshold
* | | |If the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting, the TXTHIF bit will be set to 1, else the TXTHIF bit will be cleared to 0
* @var QSPI_T::STATUS
* Offset: 0x14 QSPI Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |BUSY |Busy Status (Read Only)
* | | |0 = QSPI controller is in idle state.
* | | |1 = QSPI controller is in busy state.
* | | |The following lists the bus busy conditions:
* | | |u00B7 SPIEN (QSPIx_CTL[0]) = 1 and TXEMPTY = 0.
* | | |u00B7 For QSPI Master mode, SPIEN (QSPIx_CTL[0]) = 1 and TXEMPTY = 1 but the current transaction is not finished yet.
* | | |u00B7 For QSPI Master mode, SPIEN (QSPIx_CTL[0]) = 1 and RXONLY = 1.
* | | |u00B7 For QSPI Slave mode, SPIEN (QSPIx_CTL[0]) = 1 and there is serial clock input into the QSPI core logic when slave select is active.
* | | |u00B7 For QSPI Slave mode, SPIEN (QSPIx_CTL[0]) = 1 and the transmit buffer or transmit shift register is not empty even if the slave select is inactive.
* | | |Note: By applications, this SPI bus flag should be used with other status registers in SPIx_STATUS such as TXCNT, RXCNT, TXTHIF, TXFULL, TXEMPTY, RXTHIF, RXFULL, RXEMPTY, and UNITIF
* | | |Therefore, the SPI transfer done events of TX/RX operations can be obtained at the correct timing point.
* |[1] |UNITIF |Unit Transfer Interrupt Flag
* | | |0 = No transaction has been finished since this bit was cleared to 0.
* | | |1 = QSPI controller has finished one unit transfer.
* | | |Note: This bit will be cleared by writing 1 to it.
* |[2] |SSACTIF |Slave Select Active Interrupt Flag
* | | |0 = Slave select active interrupt was cleared or not occurred.
* | | |1 = Slave select active interrupt event occurred.
* | | |Note: Only available in Slave mode. This bit will be cleared by writing 1 to it.
* |[3] |SSINAIF |Slave Select Inactive Interrupt Flag
* | | |0 = Slave select inactive interrupt was cleared or not occurred.
* | | |1 = Slave select inactive interrupt event occurred.
* | | |Note: Only available in Slave mode. This bit will be cleared by writing 1 to it.
* |[4] |SSLINE |Slave Select Line Bus Status (Read Only)
* | | |0 = The slave select line status is 0.
* | | |1 = The slave select line status is 1.
* | | |Note: This bit is only available in Slave mode
* | | |If SSACTPOL (QSPIx_SSCTL[2]) is set 0, and the SSLINE is 1, the QSPI slave select is in inactive status.
* |[5] |SLVTOIF |Slave Time-out Interrupt Flag
* | | |When the slave select is active and the value of SLVTOCNT is not 0, if the bus clock is detected, the slave time-out counter in QSPI controller logic will be started
* | | |When the value of time-out counter is greater than or equal to the value of SLVTOCNT (QSPIx_SSCTL[31:16]) before one transaction is done, the slave time-out interrupt event will be asserted.
* | | |0 = Slave time-out is not active.
* | | |1 = Slave time-out is active.
* | | |Note: This bit will be cleared by writing 1 to it.
* |[6] |SLVBEIF |Slave Mode Bit Count Error Interrupt Flag
* | | |In Slave mode, when the slave select line goes to inactive state, if bit counter is mismatch with DWIDTH, this interrupt flag will be set to 1.
* | | |0 = No Slave mode bit count error event.
* | | |1 = Slave mode bit count error event occurred.
* | | |Note: If the slave select active but there is no any bus clock input, the SLVBEIF also active when the slave select goes to inactive state
* | | |This bit will be cleared by writing 1 to it.
* |[7] |SLVURIF |Slave Mode TX Under Run Interrupt Flag
* | | |In Slave mode, if TX underflow event occurs and the slave select line goes to inactive state, this interrupt flag will be set to 1.
* | | |0 = No Slave TX under run event.
* | | |1 = Slave TX under run event occurred.
* | | |Note: This bit will be cleared by writing 1 to it.
* |[8] |RXEMPTY |Receive FIFO Buffer Empty Indicator (Read Only)
* | | |0 = Receive FIFO buffer is not empty.
* | | |1 = Receive FIFO buffer is empty.
* |[9] |RXFULL |Receive FIFO Buffer Full Indicator (Read Only)
* | | |0 = Receive FIFO buffer is not full.
* | | |1 = Receive FIFO buffer is full.
* |[10] |RXTHIF |Receive FIFO Threshold Interrupt Flag (Read Only)
* | | |0 = The valid data count within the receive FIFO buffer is smaller than or equal to the setting value of RXTH.
* | | |1 = The valid data count within the receive FIFO buffer is larger than the setting value of RXTH.
* |[11] |RXOVIF |Receive FIFO Overrun Interrupt Flag
* | | |When the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1.
* | | |0 = No FIFO is overrun.
* | | |1 = Receive FIFO is overrun.
* | | |Note: This bit will be cleared by writing 1 to it.
* |[12] |RXTOIF |Receive Time-out Interrupt Flag
* | | |0 = No receive FIFO time-out event.
* | | |1 = Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 QSPI peripheral clock periods in Master mode or over 576 QSPI peripheral clock periods in Slave mode
* | | |When the received FIFO buffer is read by software, the time-out status will be cleared automatically.
* | | |Note: This bit will be cleared by writing 1 to it.
* |[15] |SPIENSTS |QSPI Enable Status (Read Only)
* | | |0 = QSPI controller Disabled.
* | | |1 = QSPI controller Enabled.
* | | |Note: The QSPI peripheral clock is asynchronous with the system clock
* | | |In order to make sure the QSPI control logic is disabled, this bit indicates the real status of QSPI controller.
* |[16] |TXEMPTY |Transmit FIFO Buffer Empty Indicator (Read Only)
* | | |0 = Transmit FIFO buffer is not empty.
* | | |1 = Transmit FIFO buffer is empty.
* |[17] |TXFULL |Transmit FIFO Buffer Full Indicator (Read Only)
* | | |0 = Transmit FIFO buffer is not full.
* | | |1 = Transmit FIFO buffer is full.
* | | |Note: TXFULL flag does not go high when TXPDMAEN is set to 1.
* |[18] |TXTHIF |Transmit FIFO Threshold Interrupt Flag (Read Only)
* | | |0 = The valid data count within the transmit FIFO buffer is larger than the setting value of TXTH.
* | | |1 = The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TXTH.
* |[19] |TXUFIF |TX Underflow Interrupt Flag
* | | |When the TX underflow event occurs, this bit will be set to 1, the state of data output pin depends on the setting of TXUFPOL.
* | | |0 = No effect.
* | | |1 = No data in Transmit FIFO and TX shift register when the slave selection signal is active.
* | | |Note 1: This bit will be cleared by writing 1 to it.
* | | |Note 2: If reset slave's transmission circuit when slave selection signal is active, this flag will be set to 1 after 2 peripheral clock cycles + 3 system clock cycles since the reset operation is done.
* |[22] |FIFOCLR |TXFIFO or RXFIFO Clear Status (Read Only)
* | | |User can check the status of this bit to monitor the clear function of TXFIFO or RXFIFO is doing or done.
* | | |0 = The clear function of TXFBCLR or RXFBCLR is done.
* | | |1 = Doing the clear function of TXFBCLR or RXFBCLR.
* |[23] |TXRXRST |TX or RX Reset Status (Read Only)
* | | |0 = The reset function of TXRST or RXRST is done.
* | | |1 = Doing the reset function of TXRST or RXRST.
* | | |Note: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles
* | | |User can check the status of this bit to monitor the reset function is doing or done.
* |[27:24] |RXCNT |Receive FIFO Data Count (Read Only)
* | | |This bit field indicates the valid data count of receive FIFO buffer.
* |[31:28] |TXCNT |Transmit FIFO Data Count (Read Only)
* | | |This bit field indicates the valid data count of transmit FIFO buffer.
* @var QSPI_T::STATUS2
* Offset: 0x18 QSPI Status2 Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[13:8] |RXCPDMA |Receive FIFO Data Count When RXPDMA Enable Only (Read Only)
* | | |This bit field indicates the valid data count of receive FIFO buffer when RXPDMA (QSPIx_PDMACTL[1]) is enabled.
* |[21:16] |TXCPDMA |Transmit FIFO Data Count When TXPDMA Enable Only (Read Only)
* | | |This bit field indicates the valid data count of transmit FIFO buffer when TXPDMA (QSPIx_PDMACTL[0]) is enabled.
* |[29:24] |SLVBENUM |Effective Bit Number of Uncompleted RX Data
* | | |In slave mode, this status register indicates that effective bit number of uncompleted RX data when SLVBERX (QSPIx_FIFOCTL[10]) is enabled and RX bit count error event happen in SPI slave mode.
* | | |This status register will be fixed to 0x0 when SLVBERX (QSPIx_FIFOCTL[10]) is disabled.
* | | |Note: This register will be cleared to 0x0 when user writes 0x1 to SLVBEIF (QSPIx_STATUS[6]).
* @var QSPI_T::TX
* Offset: 0x20 QSPI Data Transmit Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |TX |Data Transmit Register
* | | |The data transmit registers pass through the transmitted data into the 8-level transmit FIFO buffers
* | | |The number of valid bits depends on the setting of DWIDTH (QSPIx_CTL[12:8]).
* | | |If DWIDTH is set to 0x08, the bits TX[7:0] will be transmitted
* | | |If DWIDTH is set to 0x00, the QSPI controller will perform a 32-bit transfer.
* | | |Note: In Master mode, the QSPI controller will start to transfer the QSPI bus clock after 1 APB clock and 6 peripheral clock cycles after user writes to this register.
* @var QSPI_T::RX
* Offset: 0x30 QSPI Data Receive Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |RX |Data Receive Register (Read Only)
* | | |There are 8-level FIFO buffers in this controller
* | | |The data receive register holds the data received from QSPI data input pin
* | | |If the RXEMPTY (QSPIx_STATUS[8) is not set to 1, the receive FIFO buffers can be accessed through software by reading this register.
*/
__IO uint32_t CTL; /*!< [0x0000] QSPI Control Register */
__IO uint32_t CLKDIV; /*!< [0x0004] QSPI Clock Divider Register */
__IO uint32_t SSCTL; /*!< [0x0008] QSPI Slave Select Control Register */
__IO uint32_t PDMACTL; /*!< [0x000c] QSPI PDMA Control Register */
__IO uint32_t FIFOCTL; /*!< [0x0010] QSPI FIFO Control Register */
__IO uint32_t STATUS; /*!< [0x0014] QSPI Status Register */
__I uint32_t STATUS2; /*!< [0x0018] QSPI Status2 Register */
__I uint32_t RESERVE0[1];
__O uint32_t TX; /*!< [0x0020] QSPI Data Transmit Register */
__I uint32_t RESERVE1[3];
__I uint32_t RX; /*!< [0x0030] QSPI Data Receive Register */
__I uint32_t RESERVE2[5]; /*!< [0x0034] Reserved */
__IO uint32_t INTERNAL; /*!< [0x0048] SPI Internal Control Register */
__I uint32_t RESERVE3; /*!< [0x004C] Reserved */
__I uint32_t VER_NUM; /*!< [0x0050] SPI Version Number Register */
__I uint32_t RESERVE4[3]; /*!< [0x0054] Reserved */
} QSPI_T;
/**
@addtogroup QSPI_CONST QSPI Bit Field Definition
Constant Definitions for QSPI Controller
@{ */
#define QSPI_CTL_SPIEN_Pos (0) /*!< QSPI_T::CTL: SPIEN Position */
#define QSPI_CTL_SPIEN_Msk (0x1ul << QSPI_CTL_SPIEN_Pos) /*!< QSPI_T::CTL: SPIEN Mask */
#define QSPI_CTL_RXNEG_Pos (1) /*!< QSPI_T::CTL: RXNEG Position */
#define QSPI_CTL_RXNEG_Msk (0x1ul << QSPI_CTL_RXNEG_Pos) /*!< QSPI_T::CTL: RXNEG Mask */
#define QSPI_CTL_TXNEG_Pos (2) /*!< QSPI_T::CTL: TXNEG Position */
#define QSPI_CTL_TXNEG_Msk (0x1ul << QSPI_CTL_TXNEG_Pos) /*!< QSPI_T::CTL: TXNEG Mask */
#define QSPI_CTL_CLKPOL_Pos (3) /*!< QSPI_T::CTL: CLKPOL Position */
#define QSPI_CTL_CLKPOL_Msk (0x1ul << QSPI_CTL_CLKPOL_Pos) /*!< QSPI_T::CTL: CLKPOL Mask */
#define QSPI_CTL_SUSPITV_Pos (4) /*!< QSPI_T::CTL: SUSPITV Position */
#define QSPI_CTL_SUSPITV_Msk (0xful << QSPI_CTL_SUSPITV_Pos) /*!< QSPI_T::CTL: SUSPITV Mask */
#define QSPI_CTL_DWIDTH_Pos (8) /*!< QSPI_T::CTL: DWIDTH Position */
#define QSPI_CTL_DWIDTH_Msk (0x1ful << QSPI_CTL_DWIDTH_Pos) /*!< QSPI_T::CTL: DWIDTH Mask */
#define QSPI_CTL_LSB_Pos (13) /*!< QSPI_T::CTL: LSB Position */
#define QSPI_CTL_LSB_Msk (0x1ul << QSPI_CTL_LSB_Pos) /*!< QSPI_T::CTL: LSB Mask */
#define QSPI_CTL_HALFDPX_Pos (14) /*!< QSPI_T::CTL: HALFDPX Position */
#define QSPI_CTL_HALFDPX_Msk (0x1ul << QSPI_CTL_HALFDPX_Pos) /*!< QSPI_T::CTL: HALFDPX Mask */
#define QSPI_CTL_RXONLY_Pos (15) /*!< QSPI_T::CTL: RXONLY Position */
#define QSPI_CTL_RXONLY_Msk (0x1ul << QSPI_CTL_RXONLY_Pos) /*!< QSPI_T::CTL: RXONLY Mask */
#define QSPI_CTL_TWOBIT_Pos (16) /*!< QSPI_T::CTL: TWOBIT Position */
#define QSPI_CTL_TWOBIT_Msk (0x1ul << QSPI_CTL_TWOBIT_Pos) /*!< QSPI_T::CTL: TWOBIT Mask */
#define QSPI_CTL_UNITIEN_Pos (17) /*!< QSPI_T::CTL: UNITIEN Position */
#define QSPI_CTL_UNITIEN_Msk (0x1ul << QSPI_CTL_UNITIEN_Pos) /*!< QSPI_T::CTL: UNITIEN Mask */
#define QSPI_CTL_SLAVE_Pos (18) /*!< QSPI_T::CTL: SLAVE Position */
#define QSPI_CTL_SLAVE_Msk (0x1ul << QSPI_CTL_SLAVE_Pos) /*!< QSPI_T::CTL: SLAVE Mask */
#define QSPI_CTL_REORDER_Pos (19) /*!< QSPI_T::CTL: REORDER Position */
#define QSPI_CTL_REORDER_Msk (0x1ul << QSPI_CTL_REORDER_Pos) /*!< QSPI_T::CTL: REORDER Mask */
#define QSPI_CTL_DATDIR_Pos (20) /*!< QSPI_T::CTL: DATDIR Position */
#define QSPI_CTL_DATDIR_Msk (0x1ul << QSPI_CTL_DATDIR_Pos) /*!< QSPI_T::CTL: DATDIR Mask */
#define QSPI_CTL_DUALIOEN_Pos (21) /*!< QSPI_T::CTL: DUALIOEN Position */
#define QSPI_CTL_DUALIOEN_Msk (0x1ul << QSPI_CTL_DUALIOEN_Pos) /*!< QSPI_T::CTL: DUALIOEN Mask */
#define QSPI_CTL_QUADIOEN_Pos (22) /*!< QSPI_T::CTL: QUADIOEN Position */
#define QSPI_CTL_QUADIOEN_Msk (0x1ul << QSPI_CTL_QUADIOEN_Pos) /*!< QSPI_T::CTL: QUADIOEN Mask */
#define QSPI_CTL_DTREN_Pos (23) /*!< QSPI_T::CTL: DTREN Position */
#define QSPI_CTL_DTREN_Msk (0x1ul << QSPI_CTL_DTREN_Pos) /*!< QSPI_T::CTL: DTREN Mask */
#define QSPI_CLKDIV_DIVIDER_Pos (0) /*!< QSPI_T::CLKDIV: DIVIDER Position */
#define QSPI_CLKDIV_DIVIDER_Msk (0x1fful << QSPI_CLKDIV_DIVIDER_Pos) /*!< QSPI_T::CLKDIV: DIVIDER Mask */
#define QSPI_SSCTL_SS_Pos (0) /*!< QSPI_T::SSCTL: SS Position */
#define QSPI_SSCTL_SS_Msk (0x1ul << QSPI_SSCTL_SS_Pos) /*!< QSPI_T::SSCTL: SS Mask */
#define QSPI_SSCTL_SS0_Pos (0) /*!< QSPI_T::SSCTL: SS0 Position */
#define QSPI_SSCTL_SS0_Msk (0x1ul << QSPI_SSCTL_SS0_Pos) /*!< QSPI_T::SSCTL: SS0 Mask */
#define QSPI_SSCTL_SS1_Pos (1) /*!< QSPI_T::SSCTL: SS1 Position */
#define QSPI_SSCTL_SS1_Msk (0x1ul << QSPI_SSCTL_SS1_Pos) /*!< QSPI_T::SSCTL: SS1 Mask */
#define QSPI_SSCTL_SSACTPOL_Pos (2) /*!< QSPI_T::SSCTL: SSACTPOL Position */
#define QSPI_SSCTL_SSACTPOL_Msk (0x1ul << QSPI_SSCTL_SSACTPOL_Pos) /*!< QSPI_T::SSCTL: SSACTPOL Mask */
#define QSPI_SSCTL_AUTOSS_Pos (3) /*!< QSPI_T::SSCTL: AUTOSS Position */
#define QSPI_SSCTL_AUTOSS_Msk (0x1ul << QSPI_SSCTL_AUTOSS_Pos) /*!< QSPI_T::SSCTL: AUTOSS Mask */
#define QSPI_SSCTL_SLV3WIRE_Pos (4) /*!< QSPI_T::SSCTL: SLV3WIRE Position */
#define QSPI_SSCTL_SLV3WIRE_Msk (0x1ul << QSPI_SSCTL_SLV3WIRE_Pos) /*!< QSPI_T::SSCTL: SLV3WIRE Mask */
#define QSPI_SSCTL_SLVTOIEN_Pos (5) /*!< QSPI_T::SSCTL: SLVTOIEN Position */
#define QSPI_SSCTL_SLVTOIEN_Msk (0x1ul << QSPI_SSCTL_SLVTOIEN_Pos) /*!< QSPI_T::SSCTL: SLVTOIEN Mask */
#define QSPI_SSCTL_SLVTORST_Pos (6) /*!< QSPI_T::SSCTL: SLVTORST Position */
#define QSPI_SSCTL_SLVTORST_Msk (0x1ul << QSPI_SSCTL_SLVTORST_Pos) /*!< QSPI_T::SSCTL: SLVTORST Mask */
#define QSPI_SSCTL_SLVBEIEN_Pos (8) /*!< QSPI_T::SSCTL: SLVBEIEN Position */
#define QSPI_SSCTL_SLVBEIEN_Msk (0x1ul << QSPI_SSCTL_SLVBEIEN_Pos) /*!< QSPI_T::SSCTL: SLVBEIEN Mask */
#define QSPI_SSCTL_SLVURIEN_Pos (9) /*!< QSPI_T::SSCTL: SLVURIEN Position */
#define QSPI_SSCTL_SLVURIEN_Msk (0x1ul << QSPI_SSCTL_SLVURIEN_Pos) /*!< QSPI_T::SSCTL: SLVURIEN Mask */
#define QSPI_SSCTL_SSACTIEN_Pos (12) /*!< QSPI_T::SSCTL: SSACTIEN Position */
#define QSPI_SSCTL_SSACTIEN_Msk (0x1ul << QSPI_SSCTL_SSACTIEN_Pos) /*!< QSPI_T::SSCTL: SSACTIEN Mask */
#define QSPI_SSCTL_SSINAIEN_Pos (13) /*!< QSPI_T::SSCTL: SSINAIEN Position */
#define QSPI_SSCTL_SSINAIEN_Msk (0x1ul << QSPI_SSCTL_SSINAIEN_Pos) /*!< QSPI_T::SSCTL: SSINAIEN Mask */
#define QSPI_SSCTL_SLVTOCNT_Pos (16) /*!< QSPI_T::SSCTL: SLVTOCNT Position */
#define QSPI_SSCTL_SLVTOCNT_Msk (0xfffful << QSPI_SSCTL_SLVTOCNT_Pos) /*!< QSPI_T::SSCTL: SLVTOCNT Mask */
#define QSPI_PDMACTL_TXPDMAEN_Pos (0) /*!< QSPI_T::PDMACTL: TXPDMAEN Position */
#define QSPI_PDMACTL_TXPDMAEN_Msk (0x1ul << QSPI_PDMACTL_TXPDMAEN_Pos) /*!< QSPI_T::PDMACTL: TXPDMAEN Mask */
#define QSPI_PDMACTL_RXPDMAEN_Pos (1) /*!< QSPI_T::PDMACTL: RXPDMAEN Position */
#define QSPI_PDMACTL_RXPDMAEN_Msk (0x1ul << QSPI_PDMACTL_RXPDMAEN_Pos) /*!< QSPI_T::PDMACTL: RXPDMAEN Mask */
#define QSPI_PDMACTL_PDMARST_Pos (2) /*!< QSPI_T::PDMACTL: PDMARST Position */
#define QSPI_PDMACTL_PDMARST_Msk (0x1ul << QSPI_PDMACTL_PDMARST_Pos) /*!< QSPI_T::PDMACTL: PDMARST Mask */
#define QSPI_FIFOCTL_RXRST_Pos (0) /*!< QSPI_T::FIFOCTL: RXRST Position */
#define QSPI_FIFOCTL_RXRST_Msk (0x1ul << QSPI_FIFOCTL_RXRST_Pos) /*!< QSPI_T::FIFOCTL: RXRST Mask */
#define QSPI_FIFOCTL_TXRST_Pos (1) /*!< QSPI_T::FIFOCTL: TXRST Position */
#define QSPI_FIFOCTL_TXRST_Msk (0x1ul << QSPI_FIFOCTL_TXRST_Pos) /*!< QSPI_T::FIFOCTL: TXRST Mask */
#define QSPI_FIFOCTL_RXTHIEN_Pos (2) /*!< QSPI_T::FIFOCTL: RXTHIEN Position */
#define QSPI_FIFOCTL_RXTHIEN_Msk (0x1ul << QSPI_FIFOCTL_RXTHIEN_Pos) /*!< QSPI_T::FIFOCTL: RXTHIEN Mask */
#define QSPI_FIFOCTL_TXTHIEN_Pos (3) /*!< QSPI_T::FIFOCTL: TXTHIEN Position */
#define QSPI_FIFOCTL_TXTHIEN_Msk (0x1ul << QSPI_FIFOCTL_TXTHIEN_Pos) /*!< QSPI_T::FIFOCTL: TXTHIEN Mask */
#define QSPI_FIFOCTL_RXTOIEN_Pos (4) /*!< QSPI_T::FIFOCTL: RXTOIEN Position */
#define QSPI_FIFOCTL_RXTOIEN_Msk (0x1ul << QSPI_FIFOCTL_RXTOIEN_Pos) /*!< QSPI_T::FIFOCTL: RXTOIEN Mask */
#define QSPI_FIFOCTL_RXOVIEN_Pos (5) /*!< QSPI_T::FIFOCTL: RXOVIEN Position */
#define QSPI_FIFOCTL_RXOVIEN_Msk (0x1ul << QSPI_FIFOCTL_RXOVIEN_Pos) /*!< QSPI_T::FIFOCTL: RXOVIEN Mask */
#define QSPI_FIFOCTL_TXUFPOL_Pos (6) /*!< QSPI_T::FIFOCTL: TXUFPOL Position */
#define QSPI_FIFOCTL_TXUFPOL_Msk (0x1ul << QSPI_FIFOCTL_TXUFPOL_Pos) /*!< QSPI_T::FIFOCTL: TXUFPOL Mask */
#define QSPI_FIFOCTL_TXUFIEN_Pos (7) /*!< QSPI_T::FIFOCTL: TXUFIEN Position */
#define QSPI_FIFOCTL_TXUFIEN_Msk (0x1ul << QSPI_FIFOCTL_TXUFIEN_Pos) /*!< QSPI_T::FIFOCTL: TXUFIEN Mask */
#define QSPI_FIFOCTL_RXFBCLR_Pos (8) /*!< QSPI_T::FIFOCTL: RXFBCLR Position */
#define QSPI_FIFOCTL_RXFBCLR_Msk (0x1ul << QSPI_FIFOCTL_RXFBCLR_Pos) /*!< QSPI_T::FIFOCTL: RXFBCLR Mask */
#define QSPI_FIFOCTL_TXFBCLR_Pos (9) /*!< QSPI_T::FIFOCTL: TXFBCLR Position */
#define QSPI_FIFOCTL_TXFBCLR_Msk (0x1ul << QSPI_FIFOCTL_TXFBCLR_Pos) /*!< QSPI_T::FIFOCTL: TXFBCLR Mask */
#define QSPI_FIFOCTL_SLVBERX_Pos (10) /*!< QSPI_T::FIFOCTL: SLVBERX Position */
#define QSPI_FIFOCTL_SLVBERX_Msk (0x1ul << QSPI_FIFOCTL_SLVBERX_Pos) /*!< QSPI_T::FIFOCTL: SLVBERX Mask */
#define QSPI_FIFOCTL_RXTH_Pos (24) /*!< QSPI_T::FIFOCTL: RXTH Position */
#define QSPI_FIFOCTL_RXTH_Msk (0x7ul << QSPI_FIFOCTL_RXTH_Pos) /*!< QSPI_T::FIFOCTL: RXTH Mask */
#define QSPI_FIFOCTL_TXTH_Pos (28) /*!< QSPI_T::FIFOCTL: TXTH Position */
#define QSPI_FIFOCTL_TXTH_Msk (0x7ul << QSPI_FIFOCTL_TXTH_Pos) /*!< QSPI_T::FIFOCTL: TXTH Mask */
#define QSPI_STATUS_BUSY_Pos (0) /*!< QSPI_T::STATUS: BUSY Position */
#define QSPI_STATUS_BUSY_Msk (0x1ul << QSPI_STATUS_BUSY_Pos) /*!< QSPI_T::STATUS: BUSY Mask */
#define QSPI_STATUS_UNITIF_Pos (1) /*!< QSPI_T::STATUS: UNITIF Position */
#define QSPI_STATUS_UNITIF_Msk (0x1ul << QSPI_STATUS_UNITIF_Pos) /*!< QSPI_T::STATUS: UNITIF Mask */
#define QSPI_STATUS_SSACTIF_Pos (2) /*!< QSPI_T::STATUS: SSACTIF Position */
#define QSPI_STATUS_SSACTIF_Msk (0x1ul << QSPI_STATUS_SSACTIF_Pos) /*!< QSPI_T::STATUS: SSACTIF Mask */
#define QSPI_STATUS_SSINAIF_Pos (3) /*!< QSPI_T::STATUS: SSINAIF Position */
#define QSPI_STATUS_SSINAIF_Msk (0x1ul << QSPI_STATUS_SSINAIF_Pos) /*!< QSPI_T::STATUS: SSINAIF Mask */
#define QSPI_STATUS_SSLINE_Pos (4) /*!< QSPI_T::STATUS: SSLINE Position */
#define QSPI_STATUS_SSLINE_Msk (0x1ul << QSPI_STATUS_SSLINE_Pos) /*!< QSPI_T::STATUS: SSLINE Mask */
#define QSPI_STATUS_SLVTOIF_Pos (5) /*!< QSPI_T::STATUS: SLVTOIF Position */
#define QSPI_STATUS_SLVTOIF_Msk (0x1ul << QSPI_STATUS_SLVTOIF_Pos) /*!< QSPI_T::STATUS: SLVTOIF Mask */
#define QSPI_STATUS_SLVBEIF_Pos (6) /*!< QSPI_T::STATUS: SLVBEIF Position */
#define QSPI_STATUS_SLVBEIF_Msk (0x1ul << QSPI_STATUS_SLVBEIF_Pos) /*!< QSPI_T::STATUS: SLVBEIF Mask */
#define QSPI_STATUS_SLVURIF_Pos (7) /*!< QSPI_T::STATUS: SLVURIF Position */
#define QSPI_STATUS_SLVURIF_Msk (0x1ul << QSPI_STATUS_SLVURIF_Pos) /*!< QSPI_T::STATUS: SLVURIF Mask */
#define QSPI_STATUS_RXEMPTY_Pos (8) /*!< QSPI_T::STATUS: RXEMPTY Position */
#define QSPI_STATUS_RXEMPTY_Msk (0x1ul << QSPI_STATUS_RXEMPTY_Pos) /*!< QSPI_T::STATUS: RXEMPTY Mask */
#define QSPI_STATUS_RXFULL_Pos (9) /*!< QSPI_T::STATUS: RXFULL Position */
#define QSPI_STATUS_RXFULL_Msk (0x1ul << QSPI_STATUS_RXFULL_Pos) /*!< QSPI_T::STATUS: RXFULL Mask */
#define QSPI_STATUS_RXTHIF_Pos (10) /*!< QSPI_T::STATUS: RXTHIF Position */
#define QSPI_STATUS_RXTHIF_Msk (0x1ul << QSPI_STATUS_RXTHIF_Pos) /*!< QSPI_T::STATUS: RXTHIF Mask */
#define QSPI_STATUS_RXOVIF_Pos (11) /*!< QSPI_T::STATUS: RXOVIF Position */
#define QSPI_STATUS_RXOVIF_Msk (0x1ul << QSPI_STATUS_RXOVIF_Pos) /*!< QSPI_T::STATUS: RXOVIF Mask */
#define QSPI_STATUS_RXTOIF_Pos (12) /*!< QSPI_T::STATUS: RXTOIF Position */
#define QSPI_STATUS_RXTOIF_Msk (0x1ul << QSPI_STATUS_RXTOIF_Pos) /*!< QSPI_T::STATUS: RXTOIF Mask */
#define QSPI_STATUS_SPIENSTS_Pos (15) /*!< QSPI_T::STATUS: SPIENSTS Position */
#define QSPI_STATUS_SPIENSTS_Msk (0x1ul << QSPI_STATUS_SPIENSTS_Pos) /*!< QSPI_T::STATUS: SPIENSTS Mask */
#define QSPI_STATUS_TXEMPTY_Pos (16) /*!< QSPI_T::STATUS: TXEMPTY Position */
#define QSPI_STATUS_TXEMPTY_Msk (0x1ul << QSPI_STATUS_TXEMPTY_Pos) /*!< QSPI_T::STATUS: TXEMPTY Mask */
#define QSPI_STATUS_TXFULL_Pos (17) /*!< QSPI_T::STATUS: TXFULL Position */
#define QSPI_STATUS_TXFULL_Msk (0x1ul << QSPI_STATUS_TXFULL_Pos) /*!< QSPI_T::STATUS: TXFULL Mask */
#define QSPI_STATUS_TXTHIF_Pos (18) /*!< QSPI_T::STATUS: TXTHIF Position */
#define QSPI_STATUS_TXTHIF_Msk (0x1ul << QSPI_STATUS_TXTHIF_Pos) /*!< QSPI_T::STATUS: TXTHIF Mask */
#define QSPI_STATUS_TXUFIF_Pos (19) /*!< QSPI_T::STATUS: TXUFIF Position */
#define QSPI_STATUS_TXUFIF_Msk (0x1ul << QSPI_STATUS_TXUFIF_Pos) /*!< QSPI_T::STATUS: TXUFIF Mask */
#define QSPI_STATUS_FIFOCLR_Pos (22) /*!< QSPI_T::STATUS: FIFOCLR Position */
#define QSPI_STATUS_FIFOCLR_Msk (0x1ul << QSPI_STATUS_FIFOCLR_Pos) /*!< QSPI_T::STATUS: FIFOCLR Mask */
#define QSPI_STATUS_TXRXRST_Pos (23) /*!< QSPI_T::STATUS: TXRXRST Position */
#define QSPI_STATUS_TXRXRST_Msk (0x1ul << QSPI_STATUS_TXRXRST_Pos) /*!< QSPI_T::STATUS: TXRXRST Mask */
#define QSPI_STATUS_RXCNT_Pos (24) /*!< QSPI_T::STATUS: RXCNT Position */
#define QSPI_STATUS_RXCNT_Msk (0xful << QSPI_STATUS_RXCNT_Pos) /*!< QSPI_T::STATUS: RXCNT Mask */
#define QSPI_STATUS_TXCNT_Pos (28) /*!< QSPI_T::STATUS: TXCNT Position */
#define QSPI_STATUS_TXCNT_Msk (0xful << QSPI_STATUS_TXCNT_Pos) /*!< QSPI_T::STATUS: TXCNT Mask */
#define QSPI_STATUS2_RXCPDMA_Pos (8) /*!< QSPI_T::STATUS2: RXCPDMA Position */
#define QSPI_STATUS2_RXCPDMA_Msk (0x3ful << QSPI_STATUS2_RXCPDMA_Pos) /*!< QSPI_T::STATUS2: RXCPDMA Mask */
#define QSPI_STATUS2_TXCPDMA_Pos (16) /*!< QSPI_T::STATUS2: TXCPDMA Position */
#define QSPI_STATUS2_TXCPDMA_Msk (0x3ful << QSPI_STATUS2_TXCPDMA_Pos) /*!< QSPI_T::STATUS2: TXCPDMA Mask */
#define QSPI_STATUS2_SLVBENUM_Pos (24) /*!< QSPI_T::STATUS2: SLVBENUM Position */
#define QSPI_STATUS2_SLVBENUM_Msk (0x3ful << QSPI_STATUS2_SLVBENUM_Pos) /*!< QSPI_T::STATUS2: SLVBENUM Mask */
#define QSPI_TX_TX_Pos (0) /*!< QSPI_T::TX: TX Position */
#define QSPI_TX_TX_Msk (0xfffffffful << QSPI_TX_TX_Pos) /*!< QSPI_T::TX: TX Mask */
#define QSPI_RX_RX_Pos (0) /*!< QSPI_T::RX: RX Position */
#define QSPI_RX_RX_Msk (0xfffffffful << QSPI_RX_RX_Pos) /*!< QSPI_T::RX: RX Mask */
#define QSPI_INTERNAL_MRXPHASE_Pos (12) /*!< QSPI_T::INTERNAL: CLKDLY_SEL Position */
#define QSPI_INTERNAL_MRXPHASE_Msk (0xful << QSPI_INTERNAL_MRXPHASE_Pos) /*!< QSPI_T::INTERNAL: CLKDLY_SEL Mask */
/**@}*/ /* QSPI_CONST */
/**@}*/ /* end of QSPI register group */
/**@}*/ /* end of REGISTER group */
#if defined ( __CC_ARM )
#pragma no_anon_unions
#endif
#endif /* __QSPI_REG_H__ */

1318
bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/rtc_reg.h Normal file
View File

File diff suppressed because it is too large Load Diff

972
bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/sc_reg.h Normal file
View File

@ -0,0 +1,972 @@
/**************************************************************************//**
* @file sc_reg.h
* @brief SC register definition header file
*
* SPDX-License-Identifier: Apache-2.0
* @copyright (C) 2020~2021 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __SC_REG_H__
#define __SC_REG_H__
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
/**
@addtogroup REGISTER Control Register
@{
*/
/**
@addtogroup SC Smart Card Host Interface Controller(SC)
Memory Mapped Structure for SC Controller
@{ */
typedef struct
{
/**
* @var SC_T::DAT
* Offset: 0x00 SC Receive/Transmit Holding Buffer Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |DAT |Receive/Transmit Holding Buffer
* | | |Write Operation:
* | | |By writing data to DAT, the SC will send out an 8-bit data.
* | | |Note: If SCEN (SCn_CTL[0]) is not enabled, DAT cannot be programmed.
* | | |Read Operation:
* | | |By reading DAT, the SC will return an 8-bit received data.
* @var SC_T::CTL
* Offset: 0x04 SC Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |SCEN |SC Controller Enable Bit
* | | |Set this bit to 1 to enable SC operation. If this bit is cleared,
* | | |0 = SC will force all transition to IDLE state.
* | | |1 = SC controller is enabled and all function can work correctly.
* | | |Note: SCEN must be set to 1 before filling in other SC registers, or smart card will not work properly.
* |[1] |RXOFF |RX Transition Disable Control Bit
* | | |This bit is used for disable RX transition function.
* | | |0 = The receiver Enabled.
* | | |1 = The receiver Disabled.
* | | |Note: If AUTOCEN (SCn_CTL[3]) is enabled, this field is ignored.
* |[2] |TXOFF |TX Transition Disable Control Bit
* | | |This bit is used for disable TX transition function.
* | | |0 = The transceiver Enabled.
* | | |1 = The transceiver Disabled.
* |[3] |AUTOCEN |Auto Convention Enable Bit
* | | |This bit is used for enable auto convention function.
* | | |0 = Auto-convention Disabled.
* | | |1 = Auto-convention Enabled.
* | | |If user enables auto convention function, the setting step must be done before Answer to Reset (ATR) state and the first data must be 0x3B or 0x3F
* | | |After hardware received first data and stored it at buffer, hardware will decided the convention and change the CONSEL (SCn_CTL[5:4]) bits automatically when received first data is 0x3B or 0x3F
* | | |If received first byte is 0x3B, TS is direct convention, CONSEL (SCn_CTL[5:4]) will be set to 00 automatically, otherwise the TS is inverse convention, and CONSEL (SCn_CTL[5:4]) will be set to 11.
* | | |If the first data is not 0x3B or 0x3F, hardware will set ACERRIF (SCn_INTSTS[10]) and generate an interrupt to CPU when ACERRIEN (SCn_INTEN[10]) is enabled.
* |[5:4] |CONSEL |Convention Selection
* | | |00 = Direct convention.
* | | |01 = Reserved.
* | | |10 = Reserved.
* | | |11 = Inverse convention.
* | | |Note: If AUTOCEN (SCn_CTL[3]) is enabled, this field is ignored.
* |[7:6] |RXTRGLV |RX Buffer Trigger Level
* | | |When the number of bytes in the receiving buffer equals the RXTRGLV, the RDAIF will be set
* | | |If RDAIEN (SCn_INTEN[0]) is enabled, an interrupt will be generated to CPU.
* | | |00 = RX Buffer Trigger Level with 01 bytes.
* | | |01 = RX Buffer Trigger Level with 02 bytes.
* | | |10 = RX Buffer Trigger Level with 03 bytes.
* | | |11 = Reserved.
* |[12:8] |BGT |Block Guard Time
* | | |Block guard time means the minimum interval between the leading edges of two consecutive characters between different transfer directions
* | | |This field indicates the counter for the bit length of block guard time
* | | |According to ISO 7816-3, in T = 0 mode, user must fill 15 (real block guard time = 16.5) to this field; in T = 1 mode, user must fill 21 (real block guard time = 22.5) to it.
* | | |Note: The real block guard time is BGT + 1.
* |[14:13] |TMRSEL |Timer Channel Selection
* | | |00 = All internal timer function Disabled.
* | | |11 = Internal 24 bit timer and two 8 bit timers Enabled
* | | |User can configure them by setting SCn_TMRCTL0[23:0], SCn_TMRCTL1[7:0] and SCn_TMRCTL2[7:0].
* | | |Other configurations are reserved
* |[15] |NSB |Stop Bit Length
* | | |This field indicates the length of stop bit.
* | | |0 = The stop bit length is 2 ETU.
* | | |1= The stop bit length is 1 ETU.
* | | |Note 1: The default stop bit length is 2. SC and UART adopts NSB to program the stop bit length.
* | | |Note 2: In UART mode, RX can receive the data sequence in 1 stop bit or 2 stop bits with NSB is set to 0.
* |[18:16] |RXRTY |RX Error Retry Count Number
* | | |This field indicates the maximum number of receiver retries that are allowed when parity error has occurred
* | | |Note 1: The real retry number is RXRTY + 1, so 8 is the maximum retry number.
* | | |Note 2: This field cannot be changed when RXRTYEN enabled
* | | |The change flow is to disable RXRTYEN first and then fill in new retry value.
* |[19] |RXRTYEN |RX Error Retry Enable Bit
* | | |This bit enables receiver retry function when parity error has occurred.
* | | |0 = RX error retry function Disabled.
* | | |1 = RX error retry function Enabled.
* | | |Note: User must fill in the RXRTY value before enabling this bit.
* |[22:20] |TXRTY |TX Error Retry Count Number
* | | |This field indicates the maximum number of transmitter retries that are allowed when parity error has occurred.
* | | |Note 1: The real retry number is TXRTY + 1, so 8 is the maximum retry number.
* | | |Note 2: This field cannot be changed when TXRTYEN enabled
* | | |The change flow is to disable TXRTYEN first and then fill in new retry value.
* |[23] |TXRTYEN |TX Error Retry Enable Bit
* | | |This bit enables transmitter retry function when parity error has occurred.
* | | |0 = TX error retry function Disabled.
* | | |1 = TX error retry function Enabled.
* |[25:24] |CDDBSEL |Card Detect De-bounce Selection
* | | |This field indicates the card detect de-bounce selection.
* | | |00 = De-bounce sample card insert once per 384 (128 * 3) SC module clocks and de-bounce sample card removal once per 128 SC module clocks.
* | | |Other configurations are reserved.
* |[26] |CDLV |Card Detect Level Selection
* | | |0 = When hardware detects the card detect pin (SCn_CD) from high to low, it indicates a card is detected.
* | | |1 = When hardware detects the card detect pin (SCn_CD) from low to high, it indicates a card is detected.
* | | |Note: User must select card detect level before Smart Card controller enabled.
* |[30] |SYNC |SYNC Flag Indicator (Read Only)
* | | |Due to synchronization, user should check this bit before writing a new value to RXRTY and TXRTY fields.
* | | |0 = Synchronizing is completed, and user can write new data to RXRTY and TXRTY.
* | | |1 = Last value is synchronizing.
* @var SC_T::ALTCTL
* Offset: 0x08 SC Alternate Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |TXRST |TX Software Reset
* | | |When TXRST is set, all the bytes in the transmit buffer and TX internal state machine will be cleared.
* | | |0 = No effect.
* | | |1 = Reset the TX internal state machine and pointers.
* | | |Note: This bit will be auto cleared after reset is complete.
* |[1] |RXRST |RX Software Reset
* | | |When RXRST is set, all the bytes in the receive buffer and RX internal state machine will be cleared.
* | | |0 = No effect.
* | | |1 = Reset the RX internal state machine and pointers.
* | | |Note: This bit will be auto cleared after reset is complete.
* |[2] |DACTEN |Deactivation Sequence Generator Enable Bit
* | | |This bit enables SC controller to initiate the card by deactivation sequence.
* | | |0 = No effect.
* | | |1 = Deactivation sequence generator Enabled.
* | | |Note 1: When the deactivation sequence completed, this bit will be cleared automatically and the INITIF (SCn_INTSTS[8]) will be set to 1.
* | | |Note 2: This field will be cleared by TXRST (SCn_ALTCTL[0]) and RXRST (SCn_ALTCTL[1])
* | | |Thus, do not fill in this bit DACTEN, TXRST and RXRST at the same time.
* | | |Note 3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed.
* |[3] |ACTEN |Activation Sequence Generator Enable Bit
* | | |This bit enables SC controller to initiate the card by activation sequence.
* | | |0 = No effect.
* | | |1 = Activation sequence generator Enabled.
* | | |Note 1: When the activation sequence completed, this bit will be cleared automatically and the INITIF (SCn_INTSTS[8]) will be set to 1.
* | | |Note 2: This field will be cleared by TXRST (SCn_ALTCTL[0]) and RXRST (SCn_ALTCTL[1])
* | | |Thus, do not fill in this bit ACTEN, TXRST and RXRST at the same time.
* | | |Note 3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed.
* | | |Note 4: During the activation sequence, RX is disabled automatically and cannot receive data
* | | |After the activation sequence completion, RXOFF (SCn_CTL[1]) keeps the state before hardware activation.
* |[4] |WARSTEN |Warm Reset Sequence Generator Enable Bit
* | | |This bit enables SC controller to initiate the card by warm reset sequence.
* | | |0 = No effect.
* | | |1 = Warm reset sequence generator Enabled.
* | | |Note 1: When the warm reset sequence completed, this bit will be cleared automatically and the INITIF (SCn_INTSTS[8]) will be set to 1.
* | | |Note 2: This field will be cleared by TXRST (SCn_ALTCTL[0]) and RXRST (SCn_ALTCTL[1])
* | | |Thus, do not fill in this bit WARSTEN, TXRST and RXRST at the same time.
* | | |Note 3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed.
* | | |Note 4: During the warm reset sequence, RX is disabled automatically and cannot receive data
* | | |After the warm reset sequence completion, RXOFF (SCn_CTL[1]) keeps the state before perform warm reset sequence.
* |[5] |CNTEN0 |Internal Timer0 Start Enable Bit
* | | |This bit enables Timer 0 to start counting
* | | |User can fill 0 to stop it and set 1 to reload and count
* | | |The counter unit is ETU base.
* | | |0 = Stop counting.
* | | |1 = Start counting.
* | | |Note 1: This field is used for internal 24 bit timer when TMRSEL (SCn_CTL[14:13]) is 11 only.
* | | |Note 2: If the operation mode is not in auto-reload mode (SCn_TMRCTL0[26] = 0), this bit will be auto-cleared by hardware.
* | | |Note 3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed.
* |[6] |CNTEN1 |Internal Timer1 Start Enable Bit
* | | |This bit enables Timer 1 to start counting
* | | |User can fill 0 to stop it and set 1 to reload and count
* | | |The counter unit is ETU base.
* | | |0 = Stop counting.
* | | |1 = Start counting.
* | | |Note 1: This field is used for internal 8 bit timer when TMRSEL(SCn_CTL[14:13]) is 11 only
* | | |Do not fill CNTEN1 when TMRSEL (SCn_CTL[14:13]) is not equal to 11.
* | | |Note 2: If the operation mode is not in auto-reload mode (SCn_TMRCTL1[26] = 0), this bit will be auto-cleared by hardware.
* | | |Note 3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed.
* |[7] |CNTEN2 |Internal Timer2 Start Enable Bit
* | | |This bit enables Timer 2 to start counting
* | | |User can fill 0 to stop it and set 1 to reload and count
* | | |The counter unit is ETU base.
* | | |0 = Stop counting.
* | | |1 = Start counting.
* | | |Note 1: This field is used for internal 8 bit timer when TMRSEL (SCn_CTL[14:13]) is 11 only
* | | |Do not fill in CNTEN2 when TMRSEL (SCn_CTL[14:13]) is not equal to 11.
* | | |Note 2: If the operation mode is not in auto-reload mode (SCn_TMRCTL2[26] = 0), this bit will be auto-cleared by hardware.
* | | |Note 3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed.
* |[9:8] |INITSEL |Initial Timing Selection
* | | |This field indicates the initial timing of hardware activation, warm-reset or deactivation.
* | | |The unit of initial timing is SC module clock.
* | | |Activation: refer to SC Activation Sequence in Figure 6.25-4.
* | | |Warm-reset: refer to Warm-Reset Sequence in Figure 6.25-5.
* | | |Deactivation: refer to Deactivation Sequence in Figure 6.25-6.
* | | |Note: When setting activation and warm reset in Timer0 operation mode 0011, it may have deviation at most 128 SC module clock cycles.
* |[11] |ADACEN |Auto Deactivation When Card Removal
* | | |This bit is used for enable hardware auto deactivation when smart card is removed.
* | | |0 = Auto deactivation Disabled.
* | | |1 = Auto deactivation Enabled.
* | | |Note: When the card is removed, hardware will stop any process and then do deactivation sequence if this bit is set
* | | |If auto deactivation process completes, hardware will set INITIF (SCn_INTSTS[8]) also.
* |[12] |RXBGTEN |Receiver Block Guard Time Function Enable Bit
* | | |This bit enables the receiver block guard time function.
* | | |0 = Receiver block guard time function Disabled.
* | | |1 = Receiver block guard time function Enabled.
* |[13] |ACTSTS0 |Internal Timer0 Active Status (Read Only)
* | | |This bit indicates the timer counter status of timer0.
* | | |0 = Timer0 is not active.
* | | |1 = Timer0 is active.
* | | |Note: Timer0 is active does not always mean timer0 is counting the CNT (SCn_TMRCTL0[23:0]).
* |[14] |ACTSTS1 |Internal Timer1 Active Status (Read Only)
* | | |This bit indicates the timer counter status of timer1.
* | | |0 = Timer1 is not active.
* | | |1 = Timer1 is active.
* | | |Note: Timer1 is active does not always mean timer1 is counting the CNT (SCn_TMRCTL1[7:0]).
* |[15] |ACTSTS2 |Internal Timer2 Active Status (Read Only)
* | | |This bit indicates the timer counter status of timer2.
* | | |0 = Timer2 is not active.
* | | |1 = Timer2 is active.
* | | |Note: Timer2 is active does not always mean timer2 is counting the CNT (SCn_TMRCTL2[7:0]).
* |[31] |SYNC |SYNC Flag Indicator (Read Only)
* | | |Due to synchronization, user should check this bit when writing a new value to SCn_ALTCTL register.
* | | |0 = Synchronizing is completed; user can write new data to SCn_ALTCTL register.
* | | |1 = Last value is synchronizing.
* @var SC_T::EGT
* Offset: 0x0C SC Extra Guard Time Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |EGT |Extra Guard Time
* | | |This field indicates the extra guard time value.
* | | |Note: The extra guard time unit is ETU base.
* @var SC_T::RXTOUT
* Offset: 0x10 SC Receive Buffer Time-out Counter Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[8:0] |RFTM |SC Receiver FIFO Time-out Counter
* | | |The time-out down counter resets and starts counting whenever the RX buffer received a new data
* | | |Once the counter decrease to 1 and no new data is received or CPU does not read data by reading SCn_DAT, a receiver time-out flag RXTOIF (SCn_INTSTS[9]) will be set, and hardware will generate an interrupt to CPU when RXTOIEN (SCn_INTEN[9]) is enabled.
* | | |Note 1: The counter unit is ETU based and the interval of time-out is RFTM + 0.5.
* | | |Note 2: Filling in all 0 to this field indicates to disable this function.
* @var SC_T::ETUCTL
* Offset: 0x14 SC Element Time Unit Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[11:0] |ETURDIV |ETU Rate Divider
* | | |The field is used for ETU clock rate divider.
* | | |The real ETU is ETURDIV + 1.
* | | |Note: User can configure this field, but this field must be greater than 0x04.
* @var SC_T::INTEN
* Offset: 0x18 SC Interrupt Enable Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |RDAIEN |Receive Data Reach Interrupt Enable Bit
* | | |This field is used to enable received data reaching trigger level RXTRGLV (SCn_CTL[7:6]) interrupt.
* | | |0 = Receive data reach trigger level interrupt Disabled.
* | | |1 = Receive data reach trigger level interrupt Enabled.
* |[1] |TBEIEN |Transmit Buffer Empty Interrupt Enable Bit
* | | |This field is used to enable transmit buffer empty interrupt.
* | | |0 = Transmit buffer empty interrupt Disabled.
* | | |1 = Transmit buffer empty interrupt Enabled.
* |[2] |TERRIEN |Transfer Error Interrupt Enable Bit
* | | |This field is used to enable transfer error interrupt
* | | |The transfer error states is at SCn_STATUS register which includes receiver break error BEF (SCn_STATUS[6]), frame error FEF (SCn_STATUS[5]), parity error PEF (SCn_STATUS[4]), receive buffer overflow error RXOV (SCn_STATUS[0]), transmit buffer overflow error TXOV (SCn_STATUS[8]), receiver retry over limit error RXOVERR (SCn_STATUS[22]) and transmitter retry over limit error TXOVERR (SCn_STATUS[30]).
* | | |0 = Transfer error interrupt Disabled.
* | | |1 = Transfer error interrupt Enabled.
* |[3] |TMR0IEN |Timer0 Interrupt Enable Bit
* | | |This field is used to enable Timer0 interrupt function.
* | | |0 = Timer0 interrupt Disabled.
* | | |1 = Timer0 interrupt Enabled.
* |[4] |TMR1IEN |Timer1 Interrupt Enable Bit
* | | |This field is used to enable the Timer1 interrupt function.
* | | |0 = Timer1 interrupt Disabled.
* | | |1 = Timer1 interrupt Enabled.
* |[5] |TMR2IEN |Timer2 Interrupt Enable Bit
* | | |This field is used to enable Timer2 interrupt function.
* | | |0 = Timer2 interrupt Disabled.
* | | |1 = Timer2 interrupt Enabled.
* |[6] |BGTIEN |Block Guard Time Interrupt Enable Bit
* | | |This field is used to enable block guard time interrupt in receive direction.
* | | |0 = Block guard time interrupt Disabled.
* | | |1 = Block guard time interrupt Enabled.
* | | |Note: This bit is valid only for receive direction block guard time.
* |[7] |CDIEN |Card Detect Interrupt Enable Bit
* | | |This field is used to enable card detect interrupt
* | | |The card detect status is CDPINSTS (SCn_STATUS[13]).
* | | |0 = Card detect interrupt Disabled.
* | | |1 = Card detect interrupt Enabled.
* |[8] |INITIEN |Initial End Interrupt Enable Bit
* | | |This field is used to enable activation (ACTEN (SCn_ALTCTL[3] = 1)), deactivation (DACTEN (SCn_ALTCTL[2] = 1)) and warm reset (WARSTEN (SCn_ALTCTL [4])) sequence complete interrupt.
* | | |0 = Initial end interrupt Disabled.
* | | |1 = Initial end interrupt Enabled.
* |[9] |RXTOIEN |Receiver Buffer Time-out Interrupt Enable Bit
* | | |This field is used to enable receiver buffer time-out interrupt.
* | | |0 = Receiver buffer time-out interrupt Disabled.
* | | |1 = Receiver buffer time-out interrupt Enabled.
* |[10] |ACERRIEN |Auto Convention Error Interrupt Enable Bit
* | | |This field is used to enable auto-convention error interrupt.
* | | |0 = Auto-convention error interrupt Disabled.
* | | |1 = Auto-convention error interrupt Enabled.
* @var SC_T::INTSTS
* Offset: 0x1C SC Interrupt Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |RDAIF |Receive Data Reach Interrupt Status Flag (Read Only)
* | | |This field is used for received data reaching trigger level RXTRGLV (SCn_CTL[7:6]) interrupt status flag.
* | | |0 = Number of receive buffer is less than RXTRGLV setting.
* | | |1 = Number of receive buffer data equals the RXTRGLV setting.
* | | |Note: This bit is read only
* | | |If user reads data from SCn_DAT and receiver buffer data byte number is less than RXTRGLV, this bit will be cleared automatically.
* |[1] |TBEIF |Transmit Buffer Empty Interrupt Status Flag (Read Only)
* | | |This field is used for transmit buffer empty interrupt status flag.
* | | |0 = Transmit buffer is not empty.
* | | |1 = Transmit buffer is empty.
* | | |Note: This bit is read only
* | | |If user wants to clear this bit, user must write data to DAT (SCn_DAT[7:0]) and then this bit will be cleared automatically.
* |[2] |TERRIF |Transfer Error Interrupt Status Flag
* | | |This field is used for transfer error interrupt status flag
* | | |The transfer error states is at SCn_STATUS register which includes receiver break error BEF (SCn_STATUS[6]), frame error FEF (SCn_STATUS[5], parity error PEF (SCn_STATUS[4] and receive buffer overflow error RXOV (SCn_STATUS[0]), transmit buffer overflow error TXOV (SCn_STATUS[8]), receiver retry over limit error RXOVERR (SCn_STATUS[22] or transmitter retry over limit error TXOVERR (SCn_STATUS[30]).
* | | |0 = Transfer error interrupt did not occur.
* | | |1 = Transfer error interrupt occurred.
* | | |Note 1: This field is the status flag of BEF, FEF, PEF, RXOV, TXOV, RXOVERR or TXOVERR.
* | | |Note 2: This bit can be cleared by writing 1 to it.
* |[3] |TMR0IF |Timer0 Interrupt Status Flag
* | | |This field is used for Timer0 interrupt status flag.
* | | |0 = Timer0 interrupt did not occur.
* | | |1 = Timer0 interrupt occurred.
* | | |Note: This bit can be cleared by writing 1 to it.
* |[4] |TMR1IF |Timer1 Interrupt Status Flag
* | | |This field is used for Timer1 interrupt status flag.
* | | |0 = Timer1 interrupt did not occur.
* | | |1 = Timer1 interrupt occurred.
* | | |Note: This bit can be cleared by writing 1 to it.
* |[5] |TMR2IF |Timer2 Interrupt Status Flag
* | | |This field is used for Timer2 interrupt status flag.
* | | |0 = Timer2 interrupt did not occur.
* | | |1 = Timer2 interrupt occurred.
* | | |Note: This bit can be cleared by writing 1 to it.
* |[6] |BGTIF |Block Guard Time Interrupt Status Flag
* | | |This field is used for indicate block guard time interrupt status flag in receive direction.
* | | |0 = Block guard time interrupt did not occur.
* | | |1 = Block guard time interrupt occurred.
* | | |Note 1: This bit is valid only when RXBGTEN (SCn_ALTCTL[12]) is enabled.
* | | |Note 2: This bit can be cleared by writing 1 to it.
* |[7] |CDIF |Card Detect Interrupt Status Flag (Read Only)
* | | |This field is used for card detect interrupt status flag
* | | |The card detect status is CINSERT (SCn_STATUS[12]) and CREMOVE (SCn_STATUS[11]).
* | | |0 = Card detect event did not occur.
* | | |1 = Card detect event occurred.
* | | |Note: This bit is read only; user must to clear CINSERT or CREMOVE status to clear it.
* |[8] |INITIF |Initial End Interrupt Status Flag
* | | |This field is used for activation (ACTEN (SCn_ALTCTL[3])), deactivation (DACTEN (SCn_ALTCTL[2])) and warm reset (WARSTEN (SCn_ALTCTL[4])) sequence interrupt status flag.
* | | |0 = Initial sequence is not complete.
* | | |1 = Initial sequence is completed.
* | | |Note: This bit can be cleared by writing 1 to it.
* |[9] |RXTOIF |Receive Buffer Time-out Interrupt Status Flag (Read Only)
* | | |This field is used for indicate receive buffer time-out interrupt status flag.
* | | |0 = Receive buffer time-out interrupt did not occur.
* | | |1 = Receive buffer time-out interrupt occurred.
* | | |Note: This bit is read only; user must read all receive buffer remaining data by reading SCn_DAT register to clear it.
* |[10] |ACERRIF |Auto Convention Error Interrupt Status Flag
* | | |This field indicates auto convention sequence error.
* | | |0 = Received TS at ATR state is 0x3B or 0x3F.
* | | |1 = Received TS at ATR state is neither 0x3B nor 0x3F.
* | | |Note: This bit can be cleared by writing 1 to it.
* @var SC_T::STATUS
* Offset: 0x20 SC Transfer Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |RXOV |Receive Overflow Error Status Flag
* | | |This bit is set when RX buffer overflow.
* | | |0 = RX buffer is not overflow.
* | | |1 = RX buffer is overflow when the number of received bytes is greater than RX buffer size (4 bytes).
* | | |Note: This bit can be cleared by writing 1 to it.
* |[1] |RXEMPTY |Receive Buffer Empty Status Flag (Read Only)
* | | |This bit indicates RX buffer empty or not.
* | | |0 = RX buffer is not empty.
* | | |1 = RX buffer is empty, it means the last byte of RX buffer has read from DAT (SCn_DAT[7:0]) by CPU.
* |[2] |RXFULL |Receive Buffer Full Status Flag (Read Only)
* | | |This bit indicates Rx buffer full or not.
* | | |0 = RX buffer count is less than 4.
* | | |1 = RX buffer count equals to 4.
* |[4] |PEF |Receiver Parity Error Status Flag
* | | |This bit is set to logic 1 whenever the received character does not have a valid "parity bit".
* | | |0 = Receiver parity error flag did not occur.
* | | |1 = Receiver parity error flag occurred.
* | | |Note 1: This bit can be cleared by writing 1 to it.
* | | |Note 2: If CPU sets receiver retries function by setting RXRTYEN (SCn_CTL[19]), hardware will not set this flag.
* |[5] |FEF |Receiver Frame Error Status Flag
* | | |This bit is set to logic 1 whenever the received character does not have a valid "stop bit" (that is, the stop bit following the last data bit or parity bit is detected as logic 0).
* | | |0 = Receiver frame error flag did not occur.
* | | |1 = Receiver frame error flag occurred.
* | | |Note 1: This bit can be cleared by writing 1 to it.
* | | |Note 2: If CPU sets receiver retries function by setting RXRTYEN (SCn_CTL[19]), hardware will not set this flag.
* |[6] |BEF |Receiver Break Error Status Flag
* | | |This bit is set to logic 1 whenever the received data input (RX) held in the "spacing state" (logic 0) is longer than a full word transmission time (that is, the total time of start bit + data bits + parity bit + stop bits).
* | | |0 = Receiver break error flag did not occur.
* | | |1 = Receiver break error flag occurred.
* | | |Note 1: This bit can be cleared by writing 1 to it.
* | | |Note 2: If CPU sets receiver retries function by setting RXRTYEN (SCn_CTL[19]), hardware will not set this flag.
* |[8] |TXOV |Transmit Overflow Error Interrupt Status Flag
* | | |This bit is set when TX buffer overflow.
* | | |0 = TX buffer is not overflow.
* | | |1 = TX buffer is overflow when TX buffer is full and an additional write operation to DAT (SCn_DAT[7:0]).
* | | |Note: This bit can be cleared by writing 1 to it.
* |[9] |TXEMPTY |Transmit Buffer Empty Status Flag (Read Only)
* | | |This bit indicates TX buffer empty or not.
* | | |0 = TX buffer is not empty.
* | | |1 = TX buffer is empty; it means the last byte of TX buffer has been transferred to Transmitter Shift Register.
* | | |Note: This bit will be cleared when writing data into DAT (SCn_DAT[7:0]).
* |[10] |TXFULL |Transmit Buffer Full Status Flag (Read Only)
* | | |This bit indicates TX buffer full or not.
* | | |0 = TX buffer count is less than 4.
* | | |1 = TX buffer count equals to 4.
* |[11] |CREMOVE |Card Removal Status of SCn_CD Pin
* | | |This bit is set whenever card has been removal.
* | | |0 = No effect.
* | | |1 = Card removed.
* | | |Note 1: This bit can be cleared by writing 1 to it.
* | | |Note 2: Card detect function will start after SCEN (SCn_CTL[0]) set.
* |[12] |CINSERT |Card Insert Status of SCn_CD Pin
* | | |This bit is set whenever card has been inserted.
* | | |0 = No effect.
* | | |1 = Card insert.
* | | |Note 1: This bit can be cleared by writing 1 to it.
* | | |Note 2: The card detect function will start after SCEN (SCn_CTL[0]) set.
* |[13] |CDPINSTS |Card Detect Pin Status (Read Only)
* | | |This bit is the pin status of SCn_CD.
* | | |0 = The SCn_CD pin state at low.
* | | |1 = The SCn_CD pin state at high.
* |[18:16] |RXPOINT |Receive Buffer Pointer Status (Read Only)
* | | |This field indicates the RX buffer pointer status
* | | |When SC controller receives one byte from external device, RXPOINT increases one
* | | |When one byte of RX buffer is read by CPU, RXPOINT decreases one.
* |[21] |RXRERR |Receiver Retry Error
* | | |This bit is used for receiver error retry and set by hardware.
* | | |0 = No RX retry transfer.
* | | |1 = RX has any error and retries transfer.
* | | |Note 1: This bit can be cleared by writing 1 to it.
* | | |Note 2 This bit is a flag and cannot generate any interrupt to CPU.
* | | |Note 3: If CPU enables receiver retries function by setting RXRTYEN (SCn_CTL[19]), hardware will not set this flag.
* |[22] |RXOVERR |Receiver over Retry Error
* | | |This bit is used for receiver retry counts over than retry number limitation.
* | | |0 = Receiver retries counts is less than RXRTY (SCn_CTL[18:16]) + 1.
* | | |1 = Receiver retries counts is equal or over than RXRTY (SCn_CTL[18:16]) + 1.
* | | |Note 1: This bit can be cleared by writing 1 to it.
* | | |Note 2: If CPU enables receiver retries function by setting RXRTYEN (SCn_CTL[19]), hardware will not set this flag.
* |[23] |RXACT |Receiver in Active Status Flag (Read Only)
* | | |This bit indicates RX transfer status.
* | | |0 = This bit is cleared automatically when RX transfer is finished.
* | | |1 = This bit is set by hardware when RX transfer is in active.
* |[26:24] |TXPOINT |Transmit Buffer Pointer Status (Read Only)
* | | |This field indicates the TX buffer pointer status
* | | |When CPU writes data into SCn_DAT, TXPOINT increases one
* | | |When one byte of TX buffer is transferred to transmitter shift register, TXPOINT decreases one.
* |[29] |TXRERR |Transmitter Retry Error
* | | |This bit is used for indicate transmitter error retry and set by hardware.
* | | |0 = No TX retry transfer.
* | | |1 = TX has any error and retries transfer.
* | | |Note 1: This bit can be cleared by writing 1 to it.
* | | |Note 2: This bit is a flag and cannot generate any interrupt to CPU.
* |[30] |TXOVERR |Transmitter over Retry Error
* | | |This bit is used for transmitter retry counts over than retry number limitation.
* | | |0 = Transmitter retries counts is less than TXRTY (SCn_CTL[22:20]) + 1.
* | | |1 = Transmitter retries counts is equal or over to TXRTY (SCn_CTL[22:20]) + 1.
* | | |Note: This bit can be cleared by writing 1 to it.
* |[31] |TXACT |Transmit in Active Status Flag (Read Only)
* | | |This bit indicates TX transmit status.
* | | |0 = This bit is cleared automatically when TX transfer is finished or the last byte transmission has completed.
* | | |1 = Transmit is active and this bit is set by hardware when TX transfer is in active and the STOP bit of the last byte has not been transmitted.
* @var SC_T::PINCTL
* Offset: 0x24 SC Pin Control State Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |PWREN |SCn_PWR Pin Signal
* | | |User can set PWRINV (SCn_PINCTL[11]) and PWREN (SCn_PINCTL[0]) to decide SCn_PWR pin is in high or low level.
* | | |Write this field to drive SCn_PWR pin
* | | |Refer PWRINV (SCn_PINCTL[11]) description for programming SCn_PWR pin voltage level.
* | | |Read this field to get SCn_PWR signal status.
* | | |0 = SCn_PWR signal status is low.
* | | |1 = SCn_PWR signal status is high.
* | | |Note: When operating at activation, warm reset or deactivation mode, this bit will be changed automatically
* | | |Thus, do not fill in this field when operating in these modes.
* |[1] |RSTEN |SCn_RST Pin Signal
* | | |User can set RSTEN (SCn_PINCTL[1]) to decide SCn_RST pin is in high or low level.
* | | |Write this field to drive SCn_RST pin.
* | | |0 = Drive SCn_RST pin to low.
* | | |1 = Drive SCn_RST pin to high.
* | | |Read this field to get SCn_RST signal status.
* | | |0 = SCn_RST signal status is low.
* | | |1 = SCn_RST signal status is high.
* | | |Note: When operating at activation, warm reset or deactivation mode, this bit will be changed automatically
* | | |Thus, do not fill in this field when operating in these modes.
* |[6] |CLKKEEP |SC Clock Enable Bit
* | | |0 = SC clock generation Disabled.
* | | |1 = SC clock always keeps free running.
* | | |Note: When operating in activation, warm reset or deactivation mode, this bit will be changed automatically
* | | |Thus, do not fill in this field when operating in these modes.
* |[9] |SCDATA |SCn_DATA Pin Signal
* | | |This bit is the signal status of SCn_DATA but user can drive SCn_DATA pin to high or low by setting this bit.
* | | |0 = Drive SCn_DATA pin to low.
* | | |1 = Drive SCn_DATA pin to high.
* | | |Read this field to get SCn_DATA signal status.
* | | |0 = SCn_DATA signal status is low.
* | | |1 = SCn_DATA signal status is high.
* | | |Note: When SC is at activation, warm reset or deactivation mode, this bit will be changed automatically
* | | |Thus, do not fill in this field when SC is in these modes.
* |[11] |PWRINV |SCn_PWR Pin Inverse
* | | |This bit is used for inverse the SCn_PWR pin.
* | | |There are four kinds of combination for SCn_PWR pin setting by PWRINV (SCn_PINCTL[11]) and PWREN (SCn_PINCTL[0]).
* | | |PWRINV (SCn_PINCTL[11]) is bit 1 and PWREN (SCn_PINCTL[0]) is bit 0 and all conditions as below list,
* | | |00 = SCn_PWR pin is 0.
* | | |01 = SCn_PWR pin is 1.
* | | |10 = SCn_PWR pin is 1.
* | | |11 = SCn_PWR pin is 0.
* | | |Note: User must select PWRINV (SCn_PINCTL[11]) before smart card is enabled by SCEN (SCn_CTL[0]).
* |[16] |DATASTS |SCn_DATA Pin Status (Read Only)
* | | |This bit is the pin status of SCn_DATA.
* | | |0 = The SCn_DATA pin status is low.
* | | |1 = The SCn_DATA pin status is high.
* |[17] |PWRSTS |SCn_PWR Pin Status (Read Only)
* | | |This bit is the pin status of SCn_PWR.
* | | |0 = SCn_PWR pin to low.
* | | |1 = SCn_PWR pin to high.
* |[18] |RSTSTS |SCn_RST Pin Status (Read Only)
* | | |This bit is the pin status of SCn_RST.
* | | |0 = SCn_RST pin is low.
* | | |1 = SCn_RST pin is high.
* |[30] |SYNC |SYNC Flag Indicator (Read Only)
* | | |Due to synchronization, user should check this bit when writing a new value to SCn_PINCTL register.
* | | |0 = Synchronizing is completed; user can write new data to SCn_PINCTL register.
* | | |1 = Last value is synchronizing.
* @var SC_T::TMRCTL0
* Offset: 0x28 SC Internal Timer0 Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[23:0] |CNT |Timer0 Counter Value
* | | |This field indicates the internal Timer0 counter values.
* | | |Note: Unit of Timer0 counter is ETU base.
* |[27:24] |OPMODE |Timer0 Operation Mode Selection
* | | |This field indicates the internal 24-bit Timer0 operation selection.
* | | |Refer to Table 6.25-3 for programming Timer0.
* |[31] |SYNC |SYNC Flag Indicator (Read Only)
* | | |Due to synchronization, user should check this bit when writing a new value to the SCn_TMRCTL0 register.
* | | |0 = Synchronizing is completed; user can write new data to SCn_TMRCTL0 register.
* | | |1 = Last value is synchronizing.
* @var SC_T::TMRCTL1
* Offset: 0x2C SC Internal Timer1 Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |CNT |Timer 1 Counter Value
* | | |This field indicates the internal Timer1 counter values.
* | | |Note: Unit of Timer1 counter is ETU base.
* |[27:24] |OPMODE |Timer 1 Operation Mode Selection
* | | |This field indicates the internal 8-bit Timer1 operation selection.
* | | |Refer to Table 6.25-3 for programming Timer1.
* |[31] |SYNC |SYNC Flag Indicator (Read Only)
* | | |Due to synchronization, software should check this bit when writing a new value to SCn_TMRCTL1 register.
* | | |0 = Synchronizing is completed; user can write new data to SCn_TMRCTL1 register.
* | | |1 = Last value is synchronizing.
* @var SC_T::TMRCTL2
* Offset: 0x30 SC Internal Timer2 Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |CNT |Timer 2 Counter Value
* | | |This field indicates the internal Timer2 counter values.
* | | |Note: Unit of Timer2 counter is ETU base.
* |[27:24] |OPMODE |Timer 2 Operation Mode Selection
* | | |This field indicates the internal 8-bit Timer2 operation selection
* | | |Refer to Table 6.25-3 for programming Timer2.
* |[31] |SYNC |SYNC Flag Indicator (Read Only)
* | | |Due to synchronization, user should check this bit when writing a new value to SCn_TMRCTL2 register.
* | | |0 = Synchronizing is completed; user can write new data to SCn_TMRCTL2 register.
* | | |1 = Last value is synchronizing.
* @var SC_T::UARTCTL
* Offset: 0x34 SC UART Mode Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |UARTEN |UART Mode Enable Bit
* | | |Sets this bit to enable UART mode function.
* | | |0 = Smart Card mode.
* | | |1 = UART mode.
* | | |Note 1: When operating in UART mode, user must set CONSEL (SCn_CTL[5:4]) = 00 and AUTOCEN (SCn_CTL[3]) = 0.
* | | |Note 2: When operating in Smart Card mode, user must set UARTEN (SCn_UARTCTL[0]) = 0.
* | | |Note 3: When UART mode is enabled, hardware will generate a reset to reset FIFO and internal state machine.
* |[5:4] |WLS |Word Length Selection
* | | |This field is used for select UART data length.
* | | |00 = Word length is 8 bits.
* | | |01 = Word length is 7 bits.
* | | |10 = Word length is 6 bits.
* | | |11 = Word length is 5 bits.
* | | |Note: In smart card mode, this WLS must be 00.
* |[6] |PBOFF |Parity Bit Disable Bit
* | | |Sets this bit is used for disable parity check function.
* | | |0 = Parity bit is generated or checked between the last data word and stop bit of the serial data.
* | | |1 = Parity bit is not generated (transmitting data) or checked (receiving data) during transfer.
* | | |Note: In smart card mode, this field must be 0 (default setting is with parity bit).
* |[7] |OPE |Odd Parity Enable Bit
* | | |This is used for odd/even parity selection.
* | | |0 = Even number of logic 1 are transmitted or check the data word and parity bits in receiving mode.
* | | |1 = Odd number of logic 1 are transmitted or check the data word and parity bits in receiving mode.
* | | |Note: This bit has effect only when PBOFF bit is 0.
* @var SC_T::ACTCTL
* Offset: 0x4C SC Activation Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[4:0] |T1EXT |T1 Extend Time of Hardware Activation
* | | |This field provide the configurable cycles to extend the activation time T1 period.
* | | |The cycle scaling factor is 2048.
* | | |Extend cycles = (filled value * 2048) cycles.
* | | |Refer to SC activation sequence in Figure 6.25-4.
* | | |For example,
* | | |SCLK = 4 MHz, each cycle = 0.25us.
* | | |Filled 20 to this field
* | | |Extend time = 20 * 2048 * 0.25us = 10.24 MS.
* | | |Note: Setting 0 to this field conforms to the protocol ISO/IEC 7816-3
*/
__IO uint32_t DAT; /*!< [0x0000] SC Receive/Transmit Holding Buffer Register */
__IO uint32_t CTL; /*!< [0x0004] SC Control Register */
__IO uint32_t ALTCTL; /*!< [0x0008] SC Alternate Control Register */
__IO uint32_t EGT; /*!< [0x000c] SC Extra Guard Time Register */
__IO uint32_t RXTOUT; /*!< [0x0010] SC Receive Buffer Time-out Counter Register */
__IO uint32_t ETUCTL; /*!< [0x0014] SC Element Time Unit Control Register */
__IO uint32_t INTEN; /*!< [0x0018] SC Interrupt Enable Control Register */
__IO uint32_t INTSTS; /*!< [0x001c] SC Interrupt Status Register */
__IO uint32_t STATUS; /*!< [0x0020] SC Transfer Status Register */
__IO uint32_t PINCTL; /*!< [0x0024] SC Pin Control State Register */
__IO uint32_t TMRCTL0; /*!< [0x0028] SC Internal Timer0 Control Register */
__IO uint32_t TMRCTL1; /*!< [0x002c] SC Internal Timer1 Control Register */
__IO uint32_t TMRCTL2; /*!< [0x0030] SC Internal Timer2 Control Register */
__IO uint32_t UARTCTL; /*!< [0x0034] SC UART Mode Control Register */
__I uint32_t RESERVE0[5];
__IO uint32_t ACTCTL; /*!< [0x004c] SC Activation Control Register */
} SC_T;
/**
@addtogroup SC_CONST SC Bit Field Definition
Constant Definitions for SC Controller
@{ */
#define SC_DAT_DAT_Pos (0) /*!< SC_T::DAT: DAT Position */
#define SC_DAT_DAT_Msk (0xfful << SC_DAT_DAT_Pos) /*!< SC_T::DAT: DAT Mask */
#define SC_CTL_SCEN_Pos (0) /*!< SC_T::CTL: SCEN Position */
#define SC_CTL_SCEN_Msk (0x1ul << SC_CTL_SCEN_Pos) /*!< SC_T::CTL: SCEN Mask */
#define SC_CTL_RXOFF_Pos (1) /*!< SC_T::CTL: RXOFF Position */
#define SC_CTL_RXOFF_Msk (0x1ul << SC_CTL_RXOFF_Pos) /*!< SC_T::CTL: RXOFF Mask */
#define SC_CTL_TXOFF_Pos (2) /*!< SC_T::CTL: TXOFF Position */
#define SC_CTL_TXOFF_Msk (0x1ul << SC_CTL_TXOFF_Pos) /*!< SC_T::CTL: TXOFF Mask */
#define SC_CTL_AUTOCEN_Pos (3) /*!< SC_T::CTL: AUTOCEN Position */
#define SC_CTL_AUTOCEN_Msk (0x1ul << SC_CTL_AUTOCEN_Pos) /*!< SC_T::CTL: AUTOCEN Mask */
#define SC_CTL_CONSEL_Pos (4) /*!< SC_T::CTL: CONSEL Position */
#define SC_CTL_CONSEL_Msk (0x3ul << SC_CTL_CONSEL_Pos) /*!< SC_T::CTL: CONSEL Mask */
#define SC_CTL_RXTRGLV_Pos (6) /*!< SC_T::CTL: RXTRGLV Position */
#define SC_CTL_RXTRGLV_Msk (0x3ul << SC_CTL_RXTRGLV_Pos) /*!< SC_T::CTL: RXTRGLV Mask */
#define SC_CTL_BGT_Pos (8) /*!< SC_T::CTL: BGT Position */
#define SC_CTL_BGT_Msk (0x1ful << SC_CTL_BGT_Pos) /*!< SC_T::CTL: BGT Mask */
#define SC_CTL_TMRSEL_Pos (13) /*!< SC_T::CTL: TMRSEL Position */
#define SC_CTL_TMRSEL_Msk (0x3ul << SC_CTL_TMRSEL_Pos) /*!< SC_T::CTL: TMRSEL Mask */
#define SC_CTL_NSB_Pos (15) /*!< SC_T::CTL: NSB Position */
#define SC_CTL_NSB_Msk (0x1ul << SC_CTL_NSB_Pos) /*!< SC_T::CTL: NSB Mask */
#define SC_CTL_RXRTY_Pos (16) /*!< SC_T::CTL: RXRTY Position */
#define SC_CTL_RXRTY_Msk (0x7ul << SC_CTL_RXRTY_Pos) /*!< SC_T::CTL: RXRTY Mask */
#define SC_CTL_RXRTYEN_Pos (19) /*!< SC_T::CTL: RXRTYEN Position */
#define SC_CTL_RXRTYEN_Msk (0x1ul << SC_CTL_RXRTYEN_Pos) /*!< SC_T::CTL: RXRTYEN Mask */
#define SC_CTL_TXRTY_Pos (20) /*!< SC_T::CTL: TXRTY Position */
#define SC_CTL_TXRTY_Msk (0x7ul << SC_CTL_TXRTY_Pos) /*!< SC_T::CTL: TXRTY Mask */
#define SC_CTL_TXRTYEN_Pos (23) /*!< SC_T::CTL: TXRTYEN Position */
#define SC_CTL_TXRTYEN_Msk (0x1ul << SC_CTL_TXRTYEN_Pos) /*!< SC_T::CTL: TXRTYEN Mask */
#define SC_CTL_CDDBSEL_Pos (24) /*!< SC_T::CTL: CDDBSEL Position */
#define SC_CTL_CDDBSEL_Msk (0x3ul << SC_CTL_CDDBSEL_Pos) /*!< SC_T::CTL: CDDBSEL Mask */
#define SC_CTL_CDLV_Pos (26) /*!< SC_T::CTL: CDLV Position */
#define SC_CTL_CDLV_Msk (0x1ul << SC_CTL_CDLV_Pos) /*!< SC_T::CTL: CDLV Mask */
#define SC_CTL_SYNC_Pos (30) /*!< SC_T::CTL: SYNC Position */
#define SC_CTL_SYNC_Msk (0x1ul << SC_CTL_SYNC_Pos) /*!< SC_T::CTL: SYNC Mask */
#define SC_ALTCTL_TXRST_Pos (0) /*!< SC_T::ALTCTL: TXRST Position */
#define SC_ALTCTL_TXRST_Msk (0x1ul << SC_ALTCTL_TXRST_Pos) /*!< SC_T::ALTCTL: TXRST Mask */
#define SC_ALTCTL_RXRST_Pos (1) /*!< SC_T::ALTCTL: RXRST Position */
#define SC_ALTCTL_RXRST_Msk (0x1ul << SC_ALTCTL_RXRST_Pos) /*!< SC_T::ALTCTL: RXRST Mask */
#define SC_ALTCTL_DACTEN_Pos (2) /*!< SC_T::ALTCTL: DACTEN Position */
#define SC_ALTCTL_DACTEN_Msk (0x1ul << SC_ALTCTL_DACTEN_Pos) /*!< SC_T::ALTCTL: DACTEN Mask */
#define SC_ALTCTL_ACTEN_Pos (3) /*!< SC_T::ALTCTL: ACTEN Position */
#define SC_ALTCTL_ACTEN_Msk (0x1ul << SC_ALTCTL_ACTEN_Pos) /*!< SC_T::ALTCTL: ACTEN Mask */
#define SC_ALTCTL_WARSTEN_Pos (4) /*!< SC_T::ALTCTL: WARSTEN Position */
#define SC_ALTCTL_WARSTEN_Msk (0x1ul << SC_ALTCTL_WARSTEN_Pos) /*!< SC_T::ALTCTL: WARSTEN Mask */
#define SC_ALTCTL_CNTEN0_Pos (5) /*!< SC_T::ALTCTL: CNTEN0 Position */
#define SC_ALTCTL_CNTEN0_Msk (0x1ul << SC_ALTCTL_CNTEN0_Pos) /*!< SC_T::ALTCTL: CNTEN0 Mask */
#define SC_ALTCTL_CNTEN1_Pos (6) /*!< SC_T::ALTCTL: CNTEN1 Position */
#define SC_ALTCTL_CNTEN1_Msk (0x1ul << SC_ALTCTL_CNTEN1_Pos) /*!< SC_T::ALTCTL: CNTEN1 Mask */
#define SC_ALTCTL_CNTEN2_Pos (7) /*!< SC_T::ALTCTL: CNTEN2 Position */
#define SC_ALTCTL_CNTEN2_Msk (0x1ul << SC_ALTCTL_CNTEN2_Pos) /*!< SC_T::ALTCTL: CNTEN2 Mask */
#define SC_ALTCTL_INITSEL_Pos (8) /*!< SC_T::ALTCTL: INITSEL Position */
#define SC_ALTCTL_INITSEL_Msk (0x3ul << SC_ALTCTL_INITSEL_Pos) /*!< SC_T::ALTCTL: INITSEL Mask */
#define SC_ALTCTL_ADACEN_Pos (11) /*!< SC_T::ALTCTL: ADACEN Position */
#define SC_ALTCTL_ADACEN_Msk (0x1ul << SC_ALTCTL_ADACEN_Pos) /*!< SC_T::ALTCTL: ADACEN Mask */
#define SC_ALTCTL_RXBGTEN_Pos (12) /*!< SC_T::ALTCTL: RXBGTEN Position */
#define SC_ALTCTL_RXBGTEN_Msk (0x1ul << SC_ALTCTL_RXBGTEN_Pos) /*!< SC_T::ALTCTL: RXBGTEN Mask */
#define SC_ALTCTL_ACTSTS0_Pos (13) /*!< SC_T::ALTCTL: ACTSTS0 Position */
#define SC_ALTCTL_ACTSTS0_Msk (0x1ul << SC_ALTCTL_ACTSTS0_Pos) /*!< SC_T::ALTCTL: ACTSTS0 Mask */
#define SC_ALTCTL_ACTSTS1_Pos (14) /*!< SC_T::ALTCTL: ACTSTS1 Position */
#define SC_ALTCTL_ACTSTS1_Msk (0x1ul << SC_ALTCTL_ACTSTS1_Pos) /*!< SC_T::ALTCTL: ACTSTS1 Mask */
#define SC_ALTCTL_ACTSTS2_Pos (15) /*!< SC_T::ALTCTL: ACTSTS2 Position */
#define SC_ALTCTL_ACTSTS2_Msk (0x1ul << SC_ALTCTL_ACTSTS2_Pos) /*!< SC_T::ALTCTL: ACTSTS2 Mask */
#define SC_ALTCTL_SYNC_Pos (31) /*!< SC_T::ALTCTL: SYNC Position */
#define SC_ALTCTL_SYNC_Msk (0x1ul << SC_ALTCTL_SYNC_Pos) /*!< SC_T::ALTCTL: SYNC Mask */
#define SC_EGT_EGT_Pos (0) /*!< SC_T::EGT: EGT Position */
#define SC_EGT_EGT_Msk (0xfful << SC_EGT_EGT_Pos) /*!< SC_T::EGT: EGT Mask */
#define SC_RXTOUT_RFTM_Pos (0) /*!< SC_T::RXTOUT: RFTM Position */
#define SC_RXTOUT_RFTM_Msk (0x1fful << SC_RXTOUT_RFTM_Pos) /*!< SC_T::RXTOUT: RFTM Mask */
#define SC_ETUCTL_ETURDIV_Pos (0) /*!< SC_T::ETUCTL: ETURDIV Position */
#define SC_ETUCTL_ETURDIV_Msk (0xffful << SC_ETUCTL_ETURDIV_Pos) /*!< SC_T::ETUCTL: ETURDIV Mask */
#define SC_INTEN_RDAIEN_Pos (0) /*!< SC_T::INTEN: RDAIEN Position */
#define SC_INTEN_RDAIEN_Msk (0x1ul << SC_INTEN_RDAIEN_Pos) /*!< SC_T::INTEN: RDAIEN Mask */
#define SC_INTEN_TBEIEN_Pos (1) /*!< SC_T::INTEN: TBEIEN Position */
#define SC_INTEN_TBEIEN_Msk (0x1ul << SC_INTEN_TBEIEN_Pos) /*!< SC_T::INTEN: TBEIEN Mask */
#define SC_INTEN_TERRIEN_Pos (2) /*!< SC_T::INTEN: TERRIEN Position */
#define SC_INTEN_TERRIEN_Msk (0x1ul << SC_INTEN_TERRIEN_Pos) /*!< SC_T::INTEN: TERRIEN Mask */
#define SC_INTEN_TMR0IEN_Pos (3) /*!< SC_T::INTEN: TMR0IEN Position */
#define SC_INTEN_TMR0IEN_Msk (0x1ul << SC_INTEN_TMR0IEN_Pos) /*!< SC_T::INTEN: TMR0IEN Mask */
#define SC_INTEN_TMR1IEN_Pos (4) /*!< SC_T::INTEN: TMR1IEN Position */
#define SC_INTEN_TMR1IEN_Msk (0x1ul << SC_INTEN_TMR1IEN_Pos) /*!< SC_T::INTEN: TMR1IEN Mask */
#define SC_INTEN_TMR2IEN_Pos (5) /*!< SC_T::INTEN: TMR2IEN Position */
#define SC_INTEN_TMR2IEN_Msk (0x1ul << SC_INTEN_TMR2IEN_Pos) /*!< SC_T::INTEN: TMR2IEN Mask */
#define SC_INTEN_BGTIEN_Pos (6) /*!< SC_T::INTEN: BGTIEN Position */
#define SC_INTEN_BGTIEN_Msk (0x1ul << SC_INTEN_BGTIEN_Pos) /*!< SC_T::INTEN: BGTIEN Mask */
#define SC_INTEN_CDIEN_Pos (7) /*!< SC_T::INTEN: CDIEN Position */
#define SC_INTEN_CDIEN_Msk (0x1ul << SC_INTEN_CDIEN_Pos) /*!< SC_T::INTEN: CDIEN Mask */
#define SC_INTEN_INITIEN_Pos (8) /*!< SC_T::INTEN: INITIEN Position */
#define SC_INTEN_INITIEN_Msk (0x1ul << SC_INTEN_INITIEN_Pos) /*!< SC_T::INTEN: INITIEN Mask */
#define SC_INTEN_RXTOIEN_Pos (9) /*!< SC_T::INTEN: RXTOIEN Position */
#define SC_INTEN_RXTOIEN_Msk (0x1ul << SC_INTEN_RXTOIEN_Pos) /*!< SC_T::INTEN: RXTOIEN Mask */
#define SC_INTEN_ACERRIEN_Pos (10) /*!< SC_T::INTEN: ACERRIEN Position */
#define SC_INTEN_ACERRIEN_Msk (0x1ul << SC_INTEN_ACERRIEN_Pos) /*!< SC_T::INTEN: ACERRIEN Mask */
#define SC_INTSTS_RDAIF_Pos (0) /*!< SC_T::INTSTS: RDAIF Position */
#define SC_INTSTS_RDAIF_Msk (0x1ul << SC_INTSTS_RDAIF_Pos) /*!< SC_T::INTSTS: RDAIF Mask */
#define SC_INTSTS_TBEIF_Pos (1) /*!< SC_T::INTSTS: TBEIF Position */
#define SC_INTSTS_TBEIF_Msk (0x1ul << SC_INTSTS_TBEIF_Pos) /*!< SC_T::INTSTS: TBEIF Mask */
#define SC_INTSTS_TERRIF_Pos (2) /*!< SC_T::INTSTS: TERRIF Position */
#define SC_INTSTS_TERRIF_Msk (0x1ul << SC_INTSTS_TERRIF_Pos) /*!< SC_T::INTSTS: TERRIF Mask */
#define SC_INTSTS_TMR0IF_Pos (3) /*!< SC_T::INTSTS: TMR0IF Position */
#define SC_INTSTS_TMR0IF_Msk (0x1ul << SC_INTSTS_TMR0IF_Pos) /*!< SC_T::INTSTS: TMR0IF Mask */
#define SC_INTSTS_TMR1IF_Pos (4) /*!< SC_T::INTSTS: TMR1IF Position */
#define SC_INTSTS_TMR1IF_Msk (0x1ul << SC_INTSTS_TMR1IF_Pos) /*!< SC_T::INTSTS: TMR1IF Mask */
#define SC_INTSTS_TMR2IF_Pos (5) /*!< SC_T::INTSTS: TMR2IF Position */
#define SC_INTSTS_TMR2IF_Msk (0x1ul << SC_INTSTS_TMR2IF_Pos) /*!< SC_T::INTSTS: TMR2IF Mask */
#define SC_INTSTS_BGTIF_Pos (6) /*!< SC_T::INTSTS: BGTIF Position */
#define SC_INTSTS_BGTIF_Msk (0x1ul << SC_INTSTS_BGTIF_Pos) /*!< SC_T::INTSTS: BGTIF Mask */
#define SC_INTSTS_CDIF_Pos (7) /*!< SC_T::INTSTS: CDIF Position */
#define SC_INTSTS_CDIF_Msk (0x1ul << SC_INTSTS_CDIF_Pos) /*!< SC_T::INTSTS: CDIF Mask */
#define SC_INTSTS_INITIF_Pos (8) /*!< SC_T::INTSTS: INITIF Position */
#define SC_INTSTS_INITIF_Msk (0x1ul << SC_INTSTS_INITIF_Pos) /*!< SC_T::INTSTS: INITIF Mask */
#define SC_INTSTS_RXTOIF_Pos (9) /*!< SC_T::INTSTS: RXTOIF Position */
#define SC_INTSTS_RXTOIF_Msk (0x1ul << SC_INTSTS_RXTOIF_Pos) /*!< SC_T::INTSTS: RXTOIF Mask */
#define SC_INTSTS_ACERRIF_Pos (10) /*!< SC_T::INTSTS: ACERRIF Position */
#define SC_INTSTS_ACERRIF_Msk (0x1ul << SC_INTSTS_ACERRIF_Pos) /*!< SC_T::INTSTS: ACERRIF Mask */
#define SC_STATUS_RXOV_Pos (0) /*!< SC_T::STATUS: RXOV Position */
#define SC_STATUS_RXOV_Msk (0x1ul << SC_STATUS_RXOV_Pos) /*!< SC_T::STATUS: RXOV Mask */
#define SC_STATUS_RXEMPTY_Pos (1) /*!< SC_T::STATUS: RXEMPTY Position */
#define SC_STATUS_RXEMPTY_Msk (0x1ul << SC_STATUS_RXEMPTY_Pos) /*!< SC_T::STATUS: RXEMPTY Mask */
#define SC_STATUS_RXFULL_Pos (2) /*!< SC_T::STATUS: RXFULL Position */
#define SC_STATUS_RXFULL_Msk (0x1ul << SC_STATUS_RXFULL_Pos) /*!< SC_T::STATUS: RXFULL Mask */
#define SC_STATUS_PEF_Pos (4) /*!< SC_T::STATUS: PEF Position */
#define SC_STATUS_PEF_Msk (0x1ul << SC_STATUS_PEF_Pos) /*!< SC_T::STATUS: PEF Mask */
#define SC_STATUS_FEF_Pos (5) /*!< SC_T::STATUS: FEF Position */
#define SC_STATUS_FEF_Msk (0x1ul << SC_STATUS_FEF_Pos) /*!< SC_T::STATUS: FEF Mask */
#define SC_STATUS_BEF_Pos (6) /*!< SC_T::STATUS: BEF Position */
#define SC_STATUS_BEF_Msk (0x1ul << SC_STATUS_BEF_Pos) /*!< SC_T::STATUS: BEF Mask */
#define SC_STATUS_TXOV_Pos (8) /*!< SC_T::STATUS: TXOV Position */
#define SC_STATUS_TXOV_Msk (0x1ul << SC_STATUS_TXOV_Pos) /*!< SC_T::STATUS: TXOV Mask */
#define SC_STATUS_TXEMPTY_Pos (9) /*!< SC_T::STATUS: TXEMPTY Position */
#define SC_STATUS_TXEMPTY_Msk (0x1ul << SC_STATUS_TXEMPTY_Pos) /*!< SC_T::STATUS: TXEMPTY Mask */
#define SC_STATUS_TXFULL_Pos (10) /*!< SC_T::STATUS: TXFULL Position */
#define SC_STATUS_TXFULL_Msk (0x1ul << SC_STATUS_TXFULL_Pos) /*!< SC_T::STATUS: TXFULL Mask */
#define SC_STATUS_CREMOVE_Pos (11) /*!< SC_T::STATUS: CREMOVE Position */
#define SC_STATUS_CREMOVE_Msk (0x1ul << SC_STATUS_CREMOVE_Pos) /*!< SC_T::STATUS: CREMOVE Mask */
#define SC_STATUS_CINSERT_Pos (12) /*!< SC_T::STATUS: CINSERT Position */
#define SC_STATUS_CINSERT_Msk (0x1ul << SC_STATUS_CINSERT_Pos) /*!< SC_T::STATUS: CINSERT Mask */
#define SC_STATUS_CDPINSTS_Pos (13) /*!< SC_T::STATUS: CDPINSTS Position */
#define SC_STATUS_CDPINSTS_Msk (0x1ul << SC_STATUS_CDPINSTS_Pos) /*!< SC_T::STATUS: CDPINSTS Mask */
#define SC_STATUS_RXPOINT_Pos (16) /*!< SC_T::STATUS: RXPOINT Position */
#define SC_STATUS_RXPOINT_Msk (0x7ul << SC_STATUS_RXPOINT_Pos) /*!< SC_T::STATUS: RXPOINT Mask */
#define SC_STATUS_RXRERR_Pos (21) /*!< SC_T::STATUS: RXRERR Position */
#define SC_STATUS_RXRERR_Msk (0x1ul << SC_STATUS_RXRERR_Pos) /*!< SC_T::STATUS: RXRERR Mask */
#define SC_STATUS_RXOVERR_Pos (22) /*!< SC_T::STATUS: RXOVERR Position */
#define SC_STATUS_RXOVERR_Msk (0x1ul << SC_STATUS_RXOVERR_Pos) /*!< SC_T::STATUS: RXOVERR Mask */
#define SC_STATUS_RXACT_Pos (23) /*!< SC_T::STATUS: RXACT Position */
#define SC_STATUS_RXACT_Msk (0x1ul << SC_STATUS_RXACT_Pos) /*!< SC_T::STATUS: RXACT Mask */
#define SC_STATUS_TXPOINT_Pos (24) /*!< SC_T::STATUS: TXPOINT Position */
#define SC_STATUS_TXPOINT_Msk (0x7ul << SC_STATUS_TXPOINT_Pos) /*!< SC_T::STATUS: TXPOINT Mask */
#define SC_STATUS_TXRERR_Pos (29) /*!< SC_T::STATUS: TXRERR Position */
#define SC_STATUS_TXRERR_Msk (0x1ul << SC_STATUS_TXRERR_Pos) /*!< SC_T::STATUS: TXRERR Mask */
#define SC_STATUS_TXOVERR_Pos (30) /*!< SC_T::STATUS: TXOVERR Position */
#define SC_STATUS_TXOVERR_Msk (0x1ul << SC_STATUS_TXOVERR_Pos) /*!< SC_T::STATUS: TXOVERR Mask */
#define SC_STATUS_TXACT_Pos (31) /*!< SC_T::STATUS: TXACT Position */
#define SC_STATUS_TXACT_Msk (0x1ul << SC_STATUS_TXACT_Pos) /*!< SC_T::STATUS: TXACT Mask */
#define SC_PINCTL_PWREN_Pos (0) /*!< SC_T::PINCTL: PWREN Position */
#define SC_PINCTL_PWREN_Msk (0x1ul << SC_PINCTL_PWREN_Pos) /*!< SC_T::PINCTL: PWREN Mask */
#define SC_PINCTL_RSTEN_Pos (1) /*!< SC_T::PINCTL: RSTEN Position */
#define SC_PINCTL_RSTEN_Msk (0x1ul << SC_PINCTL_RSTEN_Pos) /*!< SC_T::PINCTL: RSTEN Mask */
#define SC_PINCTL_CLKKEEP_Pos (6) /*!< SC_T::PINCTL: CLKKEEP Position */
#define SC_PINCTL_CLKKEEP_Msk (0x1ul << SC_PINCTL_CLKKEEP_Pos) /*!< SC_T::PINCTL: CLKKEEP Mask */
#define SC_PINCTL_SCDATA_Pos (9) /*!< SC_T::PINCTL: SCDATA Position */
#define SC_PINCTL_SCDATA_Msk (0x1ul << SC_PINCTL_SCDATA_Pos) /*!< SC_T::PINCTL: SCDATA Mask */
#define SC_PINCTL_PWRINV_Pos (11) /*!< SC_T::PINCTL: PWRINV Position */
#define SC_PINCTL_PWRINV_Msk (0x1ul << SC_PINCTL_PWRINV_Pos) /*!< SC_T::PINCTL: PWRINV Mask */
#define SC_PINCTL_DATASTS_Pos (16) /*!< SC_T::PINCTL: DATASTS Position */
#define SC_PINCTL_DATASTS_Msk (0x1ul << SC_PINCTL_DATASTS_Pos) /*!< SC_T::PINCTL: DATASTS Mask */
#define SC_PINCTL_PWRSTS_Pos (17) /*!< SC_T::PINCTL: PWRSTS Position */
#define SC_PINCTL_PWRSTS_Msk (0x1ul << SC_PINCTL_PWRSTS_Pos) /*!< SC_T::PINCTL: PWRSTS Mask */
#define SC_PINCTL_RSTSTS_Pos (18) /*!< SC_T::PINCTL: RSTSTS Position */
#define SC_PINCTL_RSTSTS_Msk (0x1ul << SC_PINCTL_RSTSTS_Pos) /*!< SC_T::PINCTL: RSTSTS Mask */
#define SC_PINCTL_SYNC_Pos (30) /*!< SC_T::PINCTL: SYNC Position */
#define SC_PINCTL_SYNC_Msk (0x1ul << SC_PINCTL_SYNC_Pos) /*!< SC_T::PINCTL: SYNC Mask */
#define SC_TMRCTL0_CNT_Pos (0) /*!< SC_T::TMRCTL0: CNT Position */
#define SC_TMRCTL0_CNT_Msk (0xfffffful << SC_TMRCTL0_CNT_Pos) /*!< SC_T::TMRCTL0: CNT Mask */
#define SC_TMRCTL0_OPMODE_Pos (24) /*!< SC_T::TMRCTL0: OPMODE Position */
#define SC_TMRCTL0_OPMODE_Msk (0xful << SC_TMRCTL0_OPMODE_Pos) /*!< SC_T::TMRCTL0: OPMODE Mask */
#define SC_TMRCTL0_SYNC_Pos (31) /*!< SC_T::TMRCTL0: SYNC Position */
#define SC_TMRCTL0_SYNC_Msk (0x1ul << SC_TMRCTL0_SYNC_Pos) /*!< SC_T::TMRCTL0: SYNC Mask */
#define SC_TMRCTL1_CNT_Pos (0) /*!< SC_T::TMRCTL1: CNT Position */
#define SC_TMRCTL1_CNT_Msk (0xfful << SC_TMRCTL1_CNT_Pos) /*!< SC_T::TMRCTL1: CNT Mask */
#define SC_TMRCTL1_OPMODE_Pos (24) /*!< SC_T::TMRCTL1: OPMODE Position */
#define SC_TMRCTL1_OPMODE_Msk (0xful << SC_TMRCTL1_OPMODE_Pos) /*!< SC_T::TMRCTL1: OPMODE Mask */
#define SC_TMRCTL1_SYNC_Pos (31) /*!< SC_T::TMRCTL1: SYNC Position */
#define SC_TMRCTL1_SYNC_Msk (0x1ul << SC_TMRCTL1_SYNC_Pos) /*!< SC_T::TMRCTL1: SYNC Mask */
#define SC_TMRCTL2_CNT_Pos (0) /*!< SC_T::TMRCTL2: CNT Position */
#define SC_TMRCTL2_CNT_Msk (0xfful << SC_TMRCTL2_CNT_Pos) /*!< SC_T::TMRCTL2: CNT Mask */
#define SC_TMRCTL2_OPMODE_Pos (24) /*!< SC_T::TMRCTL2: OPMODE Position */
#define SC_TMRCTL2_OPMODE_Msk (0xful << SC_TMRCTL2_OPMODE_Pos) /*!< SC_T::TMRCTL2: OPMODE Mask */
#define SC_TMRCTL2_SYNC_Pos (31) /*!< SC_T::TMRCTL2: SYNC Position */
#define SC_TMRCTL2_SYNC_Msk (0x1ul << SC_TMRCTL2_SYNC_Pos) /*!< SC_T::TMRCTL2: SYNC Mask */
#define SC_UARTCTL_UARTEN_Pos (0) /*!< SC_T::UARTCTL: UARTEN Position */
#define SC_UARTCTL_UARTEN_Msk (0x1ul << SC_UARTCTL_UARTEN_Pos) /*!< SC_T::UARTCTL: UARTEN Mask */
#define SC_UARTCTL_WLS_Pos (4) /*!< SC_T::UARTCTL: WLS Position */
#define SC_UARTCTL_WLS_Msk (0x3ul << SC_UARTCTL_WLS_Pos) /*!< SC_T::UARTCTL: WLS Mask */
#define SC_UARTCTL_PBOFF_Pos (6) /*!< SC_T::UARTCTL: PBOFF Position */
#define SC_UARTCTL_PBOFF_Msk (0x1ul << SC_UARTCTL_PBOFF_Pos) /*!< SC_T::UARTCTL: PBOFF Mask */
#define SC_UARTCTL_OPE_Pos (7) /*!< SC_T::UARTCTL: OPE Position */
#define SC_UARTCTL_OPE_Msk (0x1ul << SC_UARTCTL_OPE_Pos) /*!< SC_T::UARTCTL: OPE Mask */
#define SC_ACTCTL_T1EXT_Pos (0) /*!< SC_T::ACTCTL: T1EXT Position */
#define SC_ACTCTL_T1EXT_Msk (0x1ful << SC_ACTCTL_T1EXT_Pos) /*!< SC_T::ACTCTL: T1EXT Mask */
/**@}*/ /* SC_CONST */
/**@}*/ /* end of SC register group */
/**@}*/ /* end of REGISTER group */
#if defined ( __CC_ARM )
#pragma no_anon_unions
#endif
#endif /* __SC_REG_H__ */

2670
bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/sdh_reg.h Normal file
View File

File diff suppressed because it is too large Load Diff

893
bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/spi_reg.h Normal file
View File

@ -0,0 +1,893 @@
/**************************************************************************//**
* @file spi_reg.h
* @brief SPI register definition header file
*
* SPDX-License-Identifier: Apache-2.0
* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __SPI_REG_H__
#define __SPI_REG_H__
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
/**
@addtogroup REGISTER Control Register
@{
*/
/**
@addtogroup SPI Serial Peripheral Interface Controller(SPI)
Memory Mapped Structure for SPI Controller
@{ */
typedef struct
{
/**
* @var SPI_T::CTL
* Offset: 0x00 SPI Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |SPIEN |SPI Transfer Control Enable Bit
* | | |In Master mode, the transfer will start when there is data in the FIFO buffer after this bit is set to 1
* | | |In Slave mode, this device is ready to receive data when this bit is set to 1.
* | | |0 = Transfer control Disabled.
* | | |1 = Transfer control Enabled.
* | | |Note: Before changing the configurations of SPIx_CTL, SPIx_CLKDIV, SPIx_SSCTL and SPIx_FIFOCTL, registers, user shall clear the SPIEN (SPIx_CTL[0]) and confirm the SPIENSTS (SPIx_STATUS[15]) is 0.
* |[1] |RXNEG |Receive on Negative Edge
* | | |0 = Received data input signal is latched on the rising edge of SPI bus clock.
* | | |1 = Received data input signal is latched on the falling edge of SPI bus clock.
* |[2] |TXNEG |Transmit on Negative Edge
* | | |0 = Transmitted data output signal is changed on the rising edge of SPI bus clock.
* | | |1 = Transmitted data output signal is changed on the falling edge of SPI bus clock.
* |[3] |CLKPOL |Clock Polarity
* | | |0 = SPI bus clock is idle low.
* | | |1 = SPI bus clock is idle high.
* |[7:4] |SUSPITV |Suspend Interval for Master Only
* | | |The four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer
* | | |The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word
* | | |The default value is 0x3
* | | |The period of the suspend interval is obtained according to the following equation.
* | | |(SUSPITV[3:0] + 0.5) * period of SPI_CLK clock cycle
* | | |Example:
* | | |SUSPITV = 0x0 : 0.5 SPI_CLK clock cycle.
* | | |SUSPITV = 0x1 : 1.5 SPI_CLK clock cycle.
* | | |
* | | |SUSPITV = 0xE : 14.5 SPI_CLK clock cycle.
* | | |SUSPITV = 0xF : 15.5 SPI_CLK clock cycle.
* |[12:8] |DWIDTH |Data Width
* | | |This field specifies how many bits can be transmitted / received in one transaction
* | | |The minimum bit length is 8 bits and can up to 32 bits.
* | | |DWIDTH = 0x08 : 8 bits.
* | | |DWIDTH = 0x09 : 9 bits.
* | | |
* | | |DWIDTH = 0x1F : 31 bits.
* | | |DWIDTH = 0x00 : 32 bits.
* | | |Note 1: This bit field will decide the depth of TX/RX FIFO configuration in SPI mode
* | | |Therefore, changing this bit field will clear TX/RX FIFO by hardware automatically.
* | | |Note 2: When user changes data width, the clear functions of TXFIFO and RXFIFO will be triggered by hardware automatically
* | | |User can read status register FIFOCLR (SPI_STATUS[22]) to check status of clear function of TXFIFO and RXFIFO
* | | |After status register FIFOCLR is 0, user can write TXFIFO or read RXFIFO correctly.
* |[13] |LSB |Send LSB First
* | | |0 = The MSB, which bit of transmit/receive register depends on the setting of DWIDTH, is transmitted/received first.
* | | |1 = The LSB, bit 0 of the SPI TX register, is sent first to the SPI data output pin, and the first bit received from the SPI data input pin will be put in the LSB position of the RX register (bit 0 of SPI_RX).
* |[14] |HALFDPX |SPI Half-duplex Transfer Enable Bit
* | | |This bit is used to select full-duplex or half-duplex for SPI transfer
* | | |The bit field DATDIR (SPIx_CTL[20]) can be used to set the data direction in half-duplex transfer.
* | | |0 = SPI operates in full-duplex transfer Disabled.
* | | |1 = SPI operates in half-duplex transfer Enabled.
* |[15] |RXONLY |Receive-only Mode Enable Bit for Master Only
* | | |This bit field is only available in Master mode
* | | |In receive-only mode, SPI Master will generate SPI bus clock continuously for receiving data bit from SPI slave device and assert the BUSY status.
* | | |0 = Receive-only mode Disabled.
* | | |1 = Receive-only mode Enabled.
* |[17] |UNITIEN |Unit Transfer Interrupt Enable Bit
* | | |0 = SPI unit transfer interrupt Disabled.
* | | |1 = SPI unit transfer interrupt Enabled.
* |[18] |SLAVE |Slave Mode Control
* | | |0 = Master mode.
* | | |1 = Slave mode.
* |[19] |REORDER |Byte Reorder Function Enable Bit
* | | |0 = Byte Reorder function Disabled.
* | | |1 = Byte Reorder function Enabled
* | | |A byte suspend interval will be inserted among each byte
* | | |The period of the byte suspend interval depends on the setting of SUSPITV.
* | | |Note: Byte Reorder function is only available if DWIDTH is defined as 16, 24, and 32 bits.
* |[20] |DATDIR |Data Port Direction Control
* | | |This bit is used to select the data input/output direction in half-duplex transfer and Dual/Quad transfer
* | | |0 = SPI data is input direction.
* | | |1 = SPI data is output direction.
* @var SPI_T::CLKDIV
* Offset: 0x04 SPI Clock Divider Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[8:0] |DIVIDER |Clock Divider
* | | |The value in this field is the frequency divider for generating the peripheral clock, fspi_eclk, and the SPI bus clock of SPI Master
* | | |The frequency is obtained according to the following equation.
* | | |where
* | | |is the peripheral clock source, which is defined in the clock control register, CLK_CLKSEL4.
* | | |Note 1: Not supported in I2S mode.
* | | |Note 2: The time interval must be larger than or equal 5 peripheral clock cycles between releasing SPI IP software reset and setting this clock divider register.
* @var SPI_T::SSCTL
* Offset: 0x08 SPI Slave Select Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |SS0 |Slave Selection Control 0 for Master Only
* | | |If AUTOSS bit is cleared to 0,
* | | |0 = Set the SPIx_SS0 line to inactive state.
* | | |1 = Set the SPIx_SS0 line to active state.
* | | |If the AUTOSS bit is set to 1,
* | | |0 = Keep the SPIx_SS0 line at inactive state.
* | | |1 = SPIx_SS0 line will be automatically driven to active state for the duration of data transfer, and will be driven to inactive state for the rest of the time
* | | |The active state of SPIx_SS0 is specified in SSACTPOL (SPIx_SSCTL[2]).
* |[1] |SS1 |Slave Selection Control 1 for Master Only
* | | |If AUTOSS bit is cleared to 0,
* | | |0 = Set the SPIx_SS1 line to inactive state.
* | | |1 = Set the SPIx_SS1 line to active state.
* | | |If the AUTOSS bit is set to 1,
* | | |0 = Keep the SPIx_SS1 line at inactive state.
* | | |1 = SPIx_SS1 line will be automatically driven to active state for the duration of data transfer, and will be driven to inactive state for the rest of the time
* | | |The active state of SPIx_SS1 is specified in SSACTPOL (SPIx_SSCTL[2]).
* |[2] |SSACTPOL |Slave Selection Active Polarity
* | | |This bit defines the active polarity of slave selection signal (SPIx_SS0 and SPIx_SS1).
* | | |0 = The slave selection signal SPIx_SS0/ SPIx_SS1 is active low.
* | | |1 = The slave selection signal SPIx_SS0/ SPIx_SS1 is active high.
* |[3] |AUTOSS |Automatic Slave Selection Function Enable Bit for Master Only
* | | |0 = Automatic slave selection function Disabled
* | | |Slave selection signal will be asserted/de-asserted according to SS0 (SPIx_SSCTL[0]) or SS1 (SPIx_SSCTL[1]).
* | | |1 = Automatic slave selection function Enabled.
* |[4] |SLV3WIRE |Slave 3-wire Mode Enable Bit for SPI Slave Mode Only
* | | |In Slave 3-wire mode, the SPI controller can work with 3-wire interface including SPIx_CLK, SPIx_MISO and SPIx_MOSI pins.
* | | |0 = 4-wire bi-direction interface Disabled.
* | | |1 = 3-wire bi-direction interface Enabled.
* | | |Note: The value of this register equals to control register SLAVE (SPIx_I2SCTL[8]) when I2S mode is enabled.
* |[8] |SLVBEIEN |Slave Mode Bit Count Error Interrupt Enable Bit
* | | |0 = Slave mode bit count error interrupt Disabled.
* | | |1 = Slave mode bit count error interrupt Enabled.
* |[9] |SLVURIEN |Slave Mode TX Under Run Interrupt Enable Bit
* | | |0 = Slave mode TX under run interrupt Disabled.
* | | |1 = Slave mode TX under run interrupt Enabled.
* |[12] |SSACTIEN |Slave Select Active Interrupt Enable Bit
* | | |0 = Slave select active interrupt Disabled.
* | | |1 = Slave select active interrupt Enabled.
* |[13] |SSINAIEN |Slave Select Inactive Interrupt Enable Bit
* | | |0 = Slave select inactive interrupt Disabled.
* | | |1 = Slave select inactive interrupt Enabled.
* @var SPI_T::PDMACTL
* Offset: 0x0C SPI PDMA Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |TXPDMAEN |Transmit PDMA Enable Bit
* | | |0 = Transmit PDMA function Disabled.
* | | |1 = Transmit PDMA function Enabled.
* | | |Note 1: In SPI Master mode with full duplex transfer, if both TX and RX PDMA functions are enabled, RX PDMA function cannot be enabled prior to TX PDMA function
* | | |User can enable TX PDMA function firstly or enable both functions simultaneously.
* | | |Note 2: In SPI Master mode with full duplex transfer, if both TX and RX PDMA functions are enabled, TX PDMA function cannot be disabled prior to RX PDMA function
* | | |User can disable RX PDMA function firstly or disable both functions simultaneously.
* |[1] |RXPDMAEN |Receive PDMA Enable Bit
* | | |0 = Receive PDMA function Disabled.
* | | |1 = Receive PDMA function Enabled.
* |[2] |PDMARST |PDMA Reset
* | | |0 = No effect.
* | | |1 = Reset the PDMA control logic of the SPI controller. This bit will be automatically cleared to 0.
* @var SPI_T::FIFOCTL
* Offset: 0x10 SPI FIFO Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |RXRST |Receive Reset
* | | |0 = No effect.
* | | |1 = Reset receive FIFO pointer and receive circuit
* | | |The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1
* | | |This bit will be cleared to 0 by hardware about 3 system clock cycles + 2 peripheral clock cycles after it is set to 1
* | | |User can read TXRXRST (SPIx_STATUS[23]) to check if reset is accomplished or not.
* |[1] |TXRST |Transmit Reset
* | | |0 = No effect.
* | | |1 = Reset transmit FIFO pointer and transmit circuit
* | | |The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1
* | | |This bit will be cleared to 0 by hardware about 3 system clock cycles + 2 peripheral clock cycles after it is set to 1
* | | |User can read TXRXRST (SPIx_STATUS[23]) to check if reset is accomplished or not.
* | | |Note: If TX underflow event occurs in SPI Slave mode, this bit can be used to make SPI return to idle state.
* |[2] |RXTHIEN |Receive FIFO Threshold Interrupt Enable Bit
* | | |0 = RX FIFO threshold interrupt Disabled.
* | | |1 = RX FIFO threshold interrupt Enabled.
* |[3] |TXTHIEN |Transmit FIFO Threshold Interrupt Enable Bit
* | | |0 = TX FIFO threshold interrupt Disabled.
* | | |1 = TX FIFO threshold interrupt Enabled.
* |[4] |RXTOIEN |Slave Receive Time-out Interrupt Enable Bit
* | | |0 = Receive time-out interrupt Disabled.
* | | |1 = Receive time-out interrupt Enabled.
* |[5] |RXOVIEN |Receive FIFO Overrun Interrupt Enable Bit
* | | |0 = Receive FIFO overrun interrupt Disabled.
* | | |1 = Receive FIFO overrun interrupt Enabled.
* |[6] |TXUFPOL |TX Underflow Data Polarity
* | | |0 = The SPI data out is keep 0 if there is TX underflow event in Slave mode.
* | | |1 = The SPI data out is keep 1 if there is TX underflow event in Slave mode.
* | | |Note 1: The TX underflow event occurs if there is no any data in TX FIFO when the slave selection signal is active.
* | | |Note 2: This bit should be set as 0 in I2S mode.
* | | |Note 3: When TX underflow event occurs, SPIx_MISO pin state will be determined by this setting even though TX FIFO is not empty afterward
* | | |Data stored in TX FIFO will be sent through SPIx_MISO pin in the next transfer frame.
* |[7] |TXUFIEN |TX Underflow Interrupt Enable Bit
* | | |When TX underflow event occurs in Slave mode, TXUFIF (SPIx_STATUS[19]) will be set to 1
* | | |This bit is used to enable the TX underflow interrupt.
* | | |0 = Slave TX underflow interrupt Disabled.
* | | |1 = Slave TX underflow interrupt Enabled.
* |[8] |RXFBCLR |Receive FIFO Buffer Clear
* | | |0 = No effect.
* | | |1 = Clear receive FIFO pointer
* | | |The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1
* | | |This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1.
* | | |Note: The RX shift register will not be cleared.
* |[9] |TXFBCLR |Transmit FIFO Buffer Clear
* | | |0 = No effect.
* | | |1 = Clear transmit FIFO pointer
* | | |The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1
* | | |This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1.
* | | |Note: The TX shift register will not be cleared.
* |[10] |SLVBERX |RX FIFO Write Data Enable Bit When Slave Mode Bit Count Error for SPI Slave Mode Only
* | | |0 = Uncompleted RX data will be dropped from RX FIFO when bit count error event happen in SPI slave mode.
* | | |1 = Uncompleted RX data will be written into RX FIFO when bit count error event happen in SPI slave mode
* | | |User can read SLVBENUM (SPIx_STATUS2[29:24]) to know that the effective bit number of uncompleted RX data when SPI slave bit count error happened.
* |[26:24] |RXTH |Receive FIFO Threshold
* | | |If the valid data count of the receive FIFO buffer is larger than the RXTH setting, the RXTHIF bit will be set to 1, else the RXTHIF bit will be cleared to 0
* | | |The MSB of this bit field is only meaningful while SPI mode 8~16 bits of data length.
* |[30:28] |TXTH |Transmit FIFO Threshold
* | | |If the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting, the TXTHIF bit will be set to 1, else the TXTHIF bit will be cleared to 0
* | | |The MSB of this bit field is only meaningful while SPI mode 8~16 bits of data length
* @var SPI_T::STATUS
* Offset: 0x14 SPI Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |BUSY |Busy Status (Read Only)
* | | |0 = SPI controller is in idle state.
* | | |1 = SPI controller is in busy state.
* | | |The following lists the bus busy conditions:
* | | |a. SPIEN (SPIx_CTL[0]) = 1 and TXEMPTY = 0.
* | | |b
* | | |For SPI Master mode, SPIEN (SPIx_CTL[0]) = 1 and TXEMPTY = 1 but the current transaction is not finished yet.
* | | |c. For SPI Master mode, SPIEN (SPIx_CTL[0]) = 1 and RXONLY = 1.
* | | |d
* | | |For SPI Slave mode, SPIEN (SPIx_CTL[0]) = 1 and there is serial clock input into the SPI core logic when slave select is active.
* | | |e
* | | |For SPI Slave mode, SPIEN (SPIx_CTL[0]) = 1 and the transmit buffer or transmit shift register is not empty even if the slave select is inactive.
* | | |Note: By applications, this SPI bus flag should be used with other status registers in SPIx_STATUS such as TXCNT, RXCNT, TXTHIF, TXFULL, TXEMPTY, RXTHIF, RXFULL, RXEMPTY, and UNITIF
* | | |Therefore the SPI transfer done events of TX/RX operations can be obtained at correct timing point.
* |[1] |UNITIF |Unit Transfer Interrupt Flag
* | | |0 = No transaction has been finished since this bit was cleared to 0.
* | | |1 = SPI controller has finished one unit transfer.
* | | |Note: This bit will be cleared by writing 1 to it.
* |[2] |SSACTIF |Slave Select Active Interrupt Flag
* | | |0 = Slave select active interrupt was cleared or not occurred.
* | | |1 = Slave select active interrupt event occurred.
* | | |Note: Only available in Slave mode. This bit will be cleared by writing 1 to it.
* |[3] |SSINAIF |Slave Select Inactive Interrupt Flag
* | | |0 = Slave select inactive interrupt was cleared or not occurred.
* | | |1 = Slave select inactive interrupt event occurred.
* | | |Note: Only available in Slave mode. This bit will be cleared by writing 1 to it.
* |[4] |SSLINE |Slave Select Line Bus Status (Read Only)
* | | |0 = The slave select line status is 0.
* | | |1 = The slave select line status is 1.
* | | |Note: This bit is only available in Slave mode
* | | |If SSACTPOL (SPIx_SSCTL[2]) is set 0, and the SSLINE is 1, the SPI slave select is in inactive status.
* |[6] |SLVBEIF |Slave Mode Bit Count Error Interrupt Flag
* | | |In Slave mode, when the slave select line goes to inactive state, if bit counter is mismatched with DWIDTH, this interrupt flag will be set to 1.
* | | |0 = No Slave mode bit count error event.
* | | |1 = Slave mode bit count error event occurred.
* | | |Note: If the slave select active but there is no any bus clock input, the SLVBEIF also active when the slave select goes to inactive state
* | | |This bit will be cleared by writing 1 to it.
* |[7] |SLVURIF |Slave Mode TX Under Run Interrupt Flag
* | | |In Slave mode, if TX underflow event occurs and the slave select line goes to inactive state, this interrupt flag will be set to 1.
* | | |0 = No Slave TX under run event.
* | | |1 = Slave TX under run event occurred.
* | | |Note: This bit will be cleared by writing 1 to it.
* |[8] |RXEMPTY |Receive FIFO Buffer Empty Indicator (Read Only)
* | | |0 = Receive FIFO buffer is not empty.
* | | |1 = Receive FIFO buffer is empty.
* |[9] |RXFULL |Receive FIFO Buffer Full Indicator (Read Only)
* | | |0 = Receive FIFO buffer is not full.
* | | |1 = Receive FIFO buffer is full.
* |[10] |RXTHIF |Receive FIFO Threshold Interrupt Flag (Read Only)
* | | |0 = The valid data count within the receive FIFO buffer is smaller than or equal to the setting value of RXTH.
* | | |1 = The valid data count within the receive FIFO buffer is larger than the setting value of RXTH.
* |[11] |RXOVIF |Receive FIFO Overrun Interrupt Flag
* | | |When the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1.
* | | |0 = No FIFO is overrun.
* | | |1 = Receive FIFO is overrun.
* | | |Note: This bit will be cleared by writing 1 to it.
* |[12] |RXTOIF |Receive Time-out Interrupt Flag
* | | |0 = No receive FIFO time-out event.
* | | |1 = Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 SPI peripheral clock periods in Master mode or over 576 SPI peripheral clock periods in Slave mode
* | | |When the received FIFO buffer is read by software, the time-out status will be cleared automatically.
* | | |Note: This bit will be cleared by writing 1 to it.
* |[15] |SPIENSTS |SPI Enable Status (Read Only)
* | | |0 = SPI controller Disabled.
* | | |1 = SPI controller Enabled.
* | | |Note: The SPI peripheral clock is asynchronous with the system clock
* | | |In order to make sure the SPI control logic is disabled, this bit indicates the real status of SPI controller.
* |[16] |TXEMPTY |Transmit FIFO Buffer Empty Indicator (Read Only)
* | | |0 = Transmit FIFO buffer is not empty.
* | | |1 = Transmit FIFO buffer is empty.
* |[17] |TXFULL |Transmit FIFO Buffer Full Indicator (Read Only)
* | | |0 = Transmit FIFO buffer is not full.
* | | |1 = Transmit FIFO buffer is full.
* | | |Note: TXFULL flag does not go high when TXPDMAEN is set to 1.
* |[18] |TXTHIF |Transmit FIFO Threshold Interrupt Flag (Read Only)
* | | |0 = The valid data count within the transmit FIFO buffer is larger than the setting value of TXTH.
* | | |1 = The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TXTH.
* |[19] |TXUFIF |TX Underflow Interrupt Flag
* | | |When the TX underflow event occurs, this bit will be set to 1, the state of data output pin depends on the setting of TXUFPOL.
* | | |0 = No effect.
* | | |1 = No data in Transmit FIFO and TX shift register when the slave selection signal is active.
* | | |Note 1: This bit will be cleared by writing 1 to it.
* | | |Note 2: If reset slave's transmission circuit when slave selection signal is active, this flag will be set to 1 after 2 peripheral clock cycles + 3 system clock cycles since the reset operation is done.
* |[22] |FIFOCLR |TXFIFO or RXFIFO Clear Status (Read Only)
* | | |User can check the status of this bit to monitor the clear function of TXFIFO or RXFIFO is doing or done.
* | | |0 = The clear function of TXFBCLR or RXFBCLR is done.
* | | |1 = Doing the clear function of TXFBCLR or RXFBCLR.
* |[23] |TXRXRST |TX or RX Reset Status (Read Only)
* | | |0 = The reset function of TXRST or RXRST is done.
* | | |1 = Doing the reset function of TXRST or RXRST.
* | | |Note: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles
* | | |User can check the status of this bit to monitor the reset function is doing or done.
* |[27:24] |RXCNT |Receive FIFO Data Count (Read Only)
* | | |This bit field indicates the valid data count of receive FIFO buffer.
* |[31:28] |TXCNT |Transmit FIFO Data Count (Read Only)
* | | |This bit field indicates the valid data count of transmit FIFO buffer.
* @var SPI_T::STATUS2
* Offset: 0x18 SPI Status2 Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[12:8] |RXCPDMA |Receive FIFO Data Count When RXPDMA Enable Only (Read Only)
* | | |This bit field indicates the valid data count of receive FIFO buffer when RXPDMA (QSPIx_PDMACTL[1]) enabled.
* |[20:16] |TXCPDMA |Transmit FIFO Data Count When TXPDMA Enable Only (Read Only)
* | | |This bit field indicates the valid data count of transmit FIFO buffer when TXPDMA (QSPIx_PDMACTL[0]) enabled.
* |[29:24] |SLVBENUM |Effective Bit Number of Uncompleted RX Data for SPI Slave Mode Only
* | | |This status register indicates that effective bit number of uncompleted RX data when SLVBERX (SPIx_FIFOCTL[10]) is enabled and RX bit count error event happen in SPI slave mode.
* | | |This status register will be fixed to 0x0 when SLVBERX (SPIx_FIFOCTL[10]) is disabled.
* | | |Note: This register will be cleared to 0x0 when user write 0x1 to SLVBEIF (SPIx_STATUS[6]).
* @var SPI_T::TX
* Offset: 0x20 SPI Data Transmit Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |TX |Data Transmit Register
* | | |The data transmit registers pass through the transmitted data into the 4-level transmit FIFO buffers
* | | |The number of valid bits depends on the setting of DWIDTH (SPIx_CTL[12:8]) in SPI mode or WDWIDTH (SPIx_I2SCTL[5:4]) in I2S mode.
* | | |In SPI mode, if DWIDTH is set to 0x08, the bits TX[7:0] will be transmitted
* | | |If DWIDTH is set to 0x00, the SPI controller will perform a 32-bit transfer.
* | | |In I2S mode, if WDWIDTH (SPIx_I2SCTL[5:4]) is set to 0x2, the data width of audio channel is 24-bit and corresponding to TX[23:0]
* | | |If WDWIDTH is set as 0x0, 0x1, or 0x3, all bits of this field are valid and referred to the data arrangement in I2S mode FIFO operation section
* | | |Note: In Master mode, the SPI controller will start to transfer the SPI bus clock after 1 APB clock and 6 peripheral clock cycles after user writes to this register.
* @var SPI_T::RX
* Offset: 0x30 SPI Data Receive Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |RX |Data Receive Register (Read Only)
* | | |There are 4-level FIFO buffers in this controller
* | | |The data receive register holds the data received from SPI data input pin
* | | |If the RXEMPTY (SPIx_STATUS[8] or SPIx_I2SSTS[8]) is not set to 1, the receive FIFO buffers can be accessed through software by reading this register.
* @var SPI_T::I2SCTL
* Offset: 0x60 I2S Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |I2SEN |I2S Controller Enable Bit
* | | |0 = I2S mode Disabled.
* | | |1 = I2S mode Enabled.
* | | |Note 1: If enabling this bit, I2Sx_BCLK will start to output in Master mode.
* | | |Note 2: Before changing the configurations of SPIx_I2SCTL, SPIx_I2SCLK, SPIx_FIFOCTL, registers, user shall clear the I2SEN (SPIx_I2SCTL[0]) and confirm the I2SENSTS (SPIx_I2SSTS[15]) is 0.
* |[1] |TXEN |Transmit Enable Bit
* | | |0 = Data transmit Disabled.
* | | |1 = Data transmit Enabled.
* |[2] |RXEN |Receive Enable Bit
* | | |0 = Data receive Disabled.
* | | |1 = Data receive Enabled.
* |[3] |MUTE |Transmit Mute Enable Bit
* | | |0 = Transmit data is shifted from buffer.
* | | |1 = Transmit channel zero.
* |[5:4] |WDWIDTH |Word Width
* | | |00 = data size is 8-bit.
* | | |01 = data size is 16-bit.
* | | |10 = data size is 24-bit.
* | | |11 = data size is 32-bit.
* |[6] |MONO |Monaural Data
* | | |0 = Data is stereo format.
* | | |1 = Data is monaural format.
* |[7] |ORDER |Stereo Data Order in FIFO
* | | |0 = Left channel data at high byte.
* | | |1 = Left channel data at low byte.
* |[8] |SLAVE |Slave Mode
* | | |I2S can operate as master or slave
* | | |For Master mode, I2Sx_BCLK and I2Sx_LRCLK pins are output mode and send bit clock from this chip to audio CODEC chip
* | | |In Slave mode, I2Sx_BCLK and I2Sx_LRCLK pins are input mode and I2Sx_BCLK and I2Sx_LRCLK signals are received from outer audio CODEC chip.
* | | |0 = Master mode.
* | | |1 = Slave mode.
* |[15] |MCLKEN |Master Clock Enable Bit
* | | |If MCLKEN is set to 1, I2S controller will generate master clock on SPIx_I2SMCLK pin for external audio devices.
* | | |0 = Master clock Disabled.
* | | |1 = Master clock Enabled.
* |[16] |RZCEN |Right Channel Zero Cross Detection Enable Bit
* | | |If this bit is set to 1, when right channel data sign bit change or next shift data bits are all 0 then RZCIF flag in SPIx_I2SSTS register is set to 1
* | | |This function is only available in transmit operation.
* | | |0 = Right channel zero cross detection Disabled.
* | | |1 = Right channel zero cross detection Enabled.
* |[17] |LZCEN |Left Channel Zero Cross Detection Enable Bit
* | | |If this bit is set to 1, when left channel data sign bit changes or next shift data bits are all 0 then LZCIF flag in SPIx_I2SSTS register is set to 1
* | | |This function is only available in transmit operation.
* | | |0 = Left channel zero cross detection Disabled.
* | | |1 = Left channel zero cross detection Enabled.
* |[23] |RXLCH |Receive Left Channel Enable Bit
* | | |When monaural format is selected (MONO = 1), I2S controller will receive right channel data if RXLCH is set to 0, and receive left channel data if RXLCH is set to 1.
* | | |0 = Receive right channel data in Mono mode.
* | | |1 = Receive left channel data in Mono mode.
* |[24] |RZCIEN |Right Channel Zero Cross Interrupt Enable Bit
* | | |Interrupt occurs if this bit is set to 1 and right channel zero cross event occurs.
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* |[25] |LZCIEN |Left Channel Zero Cross Interrupt Enable Bit
* | | |Interrupt occurs if this bit is set to 1 and left channel zero cross event occurs.
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* |[29:28] |FORMAT |Data Format Selection
* | | |00 = I2S data format.
* | | |01 = MSB justified data format.
* | | |10 = PCM mode A.
* | | |11 = PCM mode B.
* |[31] |SLVERRIEN |Bit Number Error Interrupt Enable Bit for Slave Mode
* | | |Interrupt occurs if this bit is set to 1 and bit number error event occurs.
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* @var SPI_T::I2SCLK
* Offset: 0x64 I2S Clock Divider Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[6:0] |MCLKDIV |Master Clock Divider
* | | |If MCLKEN is set to 1, I2S controller will generate master clock for external audio devices
* | | |The frequency of master clock, fMCLK, is determined by the following expressions:
* | | |If MCLKDIV >= 1,.
* | | |If MCLKDIV = 0,.
* | | |where
* | | |is the frequency of I2S peripheral clock source, which is defined in the clock control register CLK_CLKSEL4
* | | |In general, the master clock rate is 256 times sampling clock rate.
* |[17:8] |BCLKDIV |Bit Clock Divider
* | | |The I2S controller will generate bit clock in Master mode
* | | |The clock frequency of bit clock, fBCLK, is determined by the following expression:
* | | |where
* | | |is the frequency of I2S peripheral clock source, which is defined in the clock control register CLK_CLKSEL4.
* | | |In I2S Slave mode, this field is used to define the frequency of peripheral clock and it's determined by .
* | | |The peripheral clock frequency in I2S Slave mode must be equal to or faster than 6 times of input bit clock.
* | | |Note: The time interval must be larger than or equal 5 peripheral clock cycles between releasing SPI IP software reset and setting this clock divider register.
* |[24] |I2SMODE |I2S Clock Divider Number Selection for I2S Mode and SPI Mode
* | | |User sets I2SMODE to set frequency of peripheral clock of I2S mode or SPI mode when BCLKDIV (SPIx_I2SCLK[17:8]) or DIVIDER (SPIx_CLKDIV[8:0]) are set.
* | | |User needs to set I2SMODE before I2SEN (SPIx_I2SCTL[0]) or SPIEN (SPIx_CTL[0]) is enabled.
* | | |0 = The frequency of peripheral clock set to SPI mode.
* | | |1 = The frequency of peripheral clock set to I2S mode.
* |[25] |I2SSLAVE |I2S Clock Divider Number Selection for I2S Slave Mode and I2S Master Mode
* | | |User sets I2SSLAVE to set frequency of peripheral clock of I2S master mode and I2S slave mode when BCLKDIV (SPIx_I2SCLK[17:8]) is set.
* | | |User needs to set I2SSLAVE before I2SEN (SPIx_I2SCTL[0]) is enabled.
* | | |0 = The frequency of peripheral clock set to I2S master mode.
* | | |1 = The frequency of peripheral clock set to I2S slave mode.
* @var SPI_T::I2SSTS
* Offset: 0x68 I2S Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[4] |RIGHT |Right Channel (Read Only)
* | | |This bit indicates the current transmit data is belong to which channel.
* | | |0 = Left channel.
* | | |1 = Right channel.
* |[8] |RXEMPTY |Receive FIFO Buffer Empty Indicator (Read Only)
* | | |0 = Receive FIFO buffer is not empty.
* | | |1 = Receive FIFO buffer is empty.
* |[9] |RXFULL |Receive FIFO Buffer Full Indicator (Read Only)
* | | |0 = Receive FIFO buffer is not full.
* | | |1 = Receive FIFO buffer is full.
* |[10] |RXTHIF |Receive FIFO Threshold Interrupt Flag (Read Only)
* | | |0 = The valid data count within the receive FIFO buffer is smaller than or equal to the setting value of RXTH.
* | | |1 = The valid data count within the receive FIFO buffer is larger than the setting value of RXTH.
* | | |Note: If RXTHIEN = 1 and RXTHIF = 1, the SPI/I2S controller will generate a SPI interrupt request.
* |[11] |RXOVIF |Receive FIFO Overrun Interrupt Flag
* | | |When the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1.
* | | |Note: This bit will be cleared by writing 1 to it.
* |[12] |RXTOIF |Receive Time-out Interrupt Flag
* | | |0 = No receive FIFO time-out event.
* | | |1 = Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 SPI peripheral clock period in Master mode or over 576 SPI peripheral clock period in Slave mode
* | | |When the received FIFO buffer is read by software, the time-out status will be cleared automatically.
* | | |Note: This bit will be cleared by writing 1 to it.
* |[15] |I2SENSTS |I2S Enable Status (Read Only)
* | | |0 = The SPI/I2S control logic Disabled.
* | | |1 = The SPI/I2S control logic Enabled.
* | | |Note: The SPI peripheral clock is asynchronous with the system clock
* | | |In order to make sure the SPI/I2S control logic is disabled, this bit indicates the real status of SPI/I2S control logic for user.
* |[16] |TXEMPTY |Transmit FIFO Buffer Empty Indicator (Read Only)
* | | |0 = Transmit FIFO buffer is not empty.
* | | |1 = Transmit FIFO buffer is empty.
* |[17] |TXFULL |Transmit FIFO Buffer Full Indicator (Read Only)
* | | |0 = Transmit FIFO buffer is not full.
* | | |1 = Transmit FIFO buffer is full.
* |[18] |TXTHIF |Transmit FIFO Threshold Interrupt Flag (Read Only)
* | | |0 = The valid data count within the transmit FIFO buffer is larger than the setting value of TXTH.
* | | |1 = The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TXTH.
* | | |Note: If TXTHIEN = 1 and TXTHIF = 1, the SPI/I2S controller will generate a SPI interrupt request.
* |[19] |TXUFIF |Transmit FIFO Underflow Interrupt Flag
* | | |When the transmit FIFO buffer is empty and there is no datum written into the FIFO buffer, if there is more bus clock input, this bit will be set to 1.
* | | |Note: This bit will be cleared by writing 1 to it.
* |[20] |RZCIF |Right Channel Zero Cross Interrupt Flag
* | | |0 = No zero cross event occurred on right channel.
* | | |1 = Zero cross event occurred on right channel.
* |[21] |LZCIF |Left Channel Zero Cross Interrupt Flag
* | | |0 = No zero cross event occurred on left channel.
* | | |1 = Zero cross event occurred on left channel.
* |[22] |SLVERRIF |Bit Number Error Interrupt Flag for Slave Mode
* | | |0 = No bit number error event occurred.
* | | |1 = Bit number error event occurred.
* | | |Note: This bit will be cleared by writing 1 to it.
* |[23] |TXRXRST |TX or RX Reset Status (Read Only)
* | | |0 = The reset function of TXRST or RXRST is done.
* | | |1 = Doing the reset function of TXRST or RXRST.
* | | |Note: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles
* | | |User can check the status of this bit to monitor the reset function is doing or done.
* |[26:24] |RXCNT |Receive FIFO Data Count (Read Only)
* | | |This bit field indicates the valid data count of receive FIFO buffer.
* |[30:28] |TXCNT |Transmit FIFO Data Count (Read Only)
* | | |This bit field indicates the valid data count of transmit FIFO buffer.
*/
__IO uint32_t CTL; /*!< [0x0000] SPI Control Register */
__IO uint32_t CLKDIV; /*!< [0x0004] SPI Clock Divider Register */
__IO uint32_t SSCTL; /*!< [0x0008] SPI Slave Select Control Register */
__IO uint32_t PDMACTL; /*!< [0x000c] SPI PDMA Control Register */
__IO uint32_t FIFOCTL; /*!< [0x0010] SPI FIFO Control Register */
__IO uint32_t STATUS; /*!< [0x0014] SPI Status Register */
__I uint32_t STATUS2; /*!< [0x0018] SPI Status2 Register */
__I uint32_t RESERVE0[1];
__O uint32_t TX; /*!< [0x0020] SPI Data Transmit Register */
__I uint32_t RESERVE1[3];
__I uint32_t RX; /*!< [0x0030] SPI Data Receive Register */
__I uint32_t RESERVE2[5]; /*!< [0x0034] Reserved */
__IO uint32_t INTERNAL; /*!< [0x0048] SPI Internal Control Register */
__I uint32_t RESERVE3; /*!< [0x004C] Reserved */
__I uint32_t VER_NUM; /*!< [0x0050] SPI Version Number Register */
__I uint32_t RESERVE4[3]; /*!< [0x0054] Reserved */
__IO uint32_t I2SCTL; /*!< [0x0060] I2S Control Register */
__IO uint32_t I2SCLK; /*!< [0x0064] I2S Clock Divider Control Register */
__IO uint32_t I2SSTS; /*!< [0x0068] I2S Status Register */
} SPI_T;
/**
@addtogroup SPI_CONST SPI Bit Field Definition
Constant Definitions for SPI Controller
@{ */
#define SPI_CTL_SPIEN_Pos (0) /*!< SPI_T::CTL: SPIEN Position */
#define SPI_CTL_SPIEN_Msk (0x1ul << SPI_CTL_SPIEN_Pos) /*!< SPI_T::CTL: SPIEN Mask */
#define SPI_CTL_RXNEG_Pos (1) /*!< SPI_T::CTL: RXNEG Position */
#define SPI_CTL_RXNEG_Msk (0x1ul << SPI_CTL_RXNEG_Pos) /*!< SPI_T::CTL: RXNEG Mask */
#define SPI_CTL_TXNEG_Pos (2) /*!< SPI_T::CTL: TXNEG Position */
#define SPI_CTL_TXNEG_Msk (0x1ul << SPI_CTL_TXNEG_Pos) /*!< SPI_T::CTL: TXNEG Mask */
#define SPI_CTL_CLKPOL_Pos (3) /*!< SPI_T::CTL: CLKPOL Position */
#define SPI_CTL_CLKPOL_Msk (0x1ul << SPI_CTL_CLKPOL_Pos) /*!< SPI_T::CTL: CLKPOL Mask */
#define SPI_CTL_SUSPITV_Pos (4) /*!< SPI_T::CTL: SUSPITV Position */
#define SPI_CTL_SUSPITV_Msk (0xful << SPI_CTL_SUSPITV_Pos) /*!< SPI_T::CTL: SUSPITV Mask */
#define SPI_CTL_DWIDTH_Pos (8) /*!< SPI_T::CTL: DWIDTH Position */
#define SPI_CTL_DWIDTH_Msk (0x1ful << SPI_CTL_DWIDTH_Pos) /*!< SPI_T::CTL: DWIDTH Mask */
#define SPI_CTL_LSB_Pos (13) /*!< SPI_T::CTL: LSB Position */
#define SPI_CTL_LSB_Msk (0x1ul << SPI_CTL_LSB_Pos) /*!< SPI_T::CTL: LSB Mask */
#define SPI_CTL_HALFDPX_Pos (14) /*!< SPI_T::CTL: HALFDPX Position */
#define SPI_CTL_HALFDPX_Msk (0x1ul << SPI_CTL_HALFDPX_Pos) /*!< SPI_T::CTL: HALFDPX Mask */
#define SPI_CTL_RXONLY_Pos (15) /*!< SPI_T::CTL: RXONLY Position */
#define SPI_CTL_RXONLY_Msk (0x1ul << SPI_CTL_RXONLY_Pos) /*!< SPI_T::CTL: RXONLY Mask */
#define SPI_CTL_UNITIEN_Pos (17) /*!< SPI_T::CTL: UNITIEN Position */
#define SPI_CTL_UNITIEN_Msk (0x1ul << SPI_CTL_UNITIEN_Pos) /*!< SPI_T::CTL: UNITIEN Mask */
#define SPI_CTL_SLAVE_Pos (18) /*!< SPI_T::CTL: SLAVE Position */
#define SPI_CTL_SLAVE_Msk (0x1ul << SPI_CTL_SLAVE_Pos) /*!< SPI_T::CTL: SLAVE Mask */
#define SPI_CTL_REORDER_Pos (19) /*!< SPI_T::CTL: REORDER Position */
#define SPI_CTL_REORDER_Msk (0x1ul << SPI_CTL_REORDER_Pos) /*!< SPI_T::CTL: REORDER Mask */
#define SPI_CTL_DATDIR_Pos (20) /*!< SPI_T::CTL: DATDIR Position */
#define SPI_CTL_DATDIR_Msk (0x1ul << SPI_CTL_DATDIR_Pos) /*!< SPI_T::CTL: DATDIR Mask */
#define SPI_CLKDIV_DIVIDER_Pos (0) /*!< SPI_T::CLKDIV: DIVIDER Position */
#define SPI_CLKDIV_DIVIDER_Msk (0x1fful << SPI_CLKDIV_DIVIDER_Pos) /*!< SPI_T::CLKDIV: DIVIDER Mask */
#define SPI_SSCTL_SS_Pos (0) /*!< SPI_T::SSCTL: SS Position */
#define SPI_SSCTL_SS_Msk (0x1ul << SPI_SSCTL_SS_Pos) /*!< SPI_T::SSCTL: SS Mask */
#define SPI_SSCTL_SS0_Pos (0) /*!< SPI_T::SSCTL: SS0 Position */
#define SPI_SSCTL_SS0_Msk (0x1ul << SPI_SSCTL_SS0_Pos) /*!< SPI_T::SSCTL: SS0 Mask */
#define SPI_SSCTL_SS1_Pos (1) /*!< SPI_T::SSCTL: SS1 Position */
#define SPI_SSCTL_SS1_Msk (0x1ul << SPI_SSCTL_SS1_Pos) /*!< SPI_T::SSCTL: SS1 Mask */
#define SPI_SSCTL_SSACTPOL_Pos (2) /*!< SPI_T::SSCTL: SSACTPOL Position */
#define SPI_SSCTL_SSACTPOL_Msk (0x1ul << SPI_SSCTL_SSACTPOL_Pos) /*!< SPI_T::SSCTL: SSACTPOL Mask */
#define SPI_SSCTL_AUTOSS_Pos (3) /*!< SPI_T::SSCTL: AUTOSS Position */
#define SPI_SSCTL_AUTOSS_Msk (0x1ul << SPI_SSCTL_AUTOSS_Pos) /*!< SPI_T::SSCTL: AUTOSS Mask */
#define SPI_SSCTL_SLV3WIRE_Pos (4) /*!< SPI_T::SSCTL: SLV3WIRE Position */
#define SPI_SSCTL_SLV3WIRE_Msk (0x1ul << SPI_SSCTL_SLV3WIRE_Pos) /*!< SPI_T::SSCTL: SLV3WIRE Mask */
#define SPI_SSCTL_SLVBEIEN_Pos (8) /*!< SPI_T::SSCTL: SLVBEIEN Position */
#define SPI_SSCTL_SLVBEIEN_Msk (0x1ul << SPI_SSCTL_SLVBEIEN_Pos) /*!< SPI_T::SSCTL: SLVBEIEN Mask */
#define SPI_SSCTL_SLVURIEN_Pos (9) /*!< SPI_T::SSCTL: SLVURIEN Position */
#define SPI_SSCTL_SLVURIEN_Msk (0x1ul << SPI_SSCTL_SLVURIEN_Pos) /*!< SPI_T::SSCTL: SLVURIEN Mask */
#define SPI_SSCTL_SSACTIEN_Pos (12) /*!< SPI_T::SSCTL: SSACTIEN Position */
#define SPI_SSCTL_SSACTIEN_Msk (0x1ul << SPI_SSCTL_SSACTIEN_Pos) /*!< SPI_T::SSCTL: SSACTIEN Mask */
#define SPI_SSCTL_SSINAIEN_Pos (13) /*!< SPI_T::SSCTL: SSINAIEN Position */
#define SPI_SSCTL_SSINAIEN_Msk (0x1ul << SPI_SSCTL_SSINAIEN_Pos) /*!< SPI_T::SSCTL: SSINAIEN Mask */
#define SPI_PDMACTL_TXPDMAEN_Pos (0) /*!< SPI_T::PDMACTL: TXPDMAEN Position */
#define SPI_PDMACTL_TXPDMAEN_Msk (0x1ul << SPI_PDMACTL_TXPDMAEN_Pos) /*!< SPI_T::PDMACTL: TXPDMAEN Mask */
#define SPI_PDMACTL_RXPDMAEN_Pos (1) /*!< SPI_T::PDMACTL: RXPDMAEN Position */
#define SPI_PDMACTL_RXPDMAEN_Msk (0x1ul << SPI_PDMACTL_RXPDMAEN_Pos) /*!< SPI_T::PDMACTL: RXPDMAEN Mask */
#define SPI_PDMACTL_PDMARST_Pos (2) /*!< SPI_T::PDMACTL: PDMARST Position */
#define SPI_PDMACTL_PDMARST_Msk (0x1ul << SPI_PDMACTL_PDMARST_Pos) /*!< SPI_T::PDMACTL: PDMARST Mask */
#define SPI_FIFOCTL_RXRST_Pos (0) /*!< SPI_T::FIFOCTL: RXRST Position */
#define SPI_FIFOCTL_RXRST_Msk (0x1ul << SPI_FIFOCTL_RXRST_Pos) /*!< SPI_T::FIFOCTL: RXRST Mask */
#define SPI_FIFOCTL_TXRST_Pos (1) /*!< SPI_T::FIFOCTL: TXRST Position */
#define SPI_FIFOCTL_TXRST_Msk (0x1ul << SPI_FIFOCTL_TXRST_Pos) /*!< SPI_T::FIFOCTL: TXRST Mask */
#define SPI_FIFOCTL_RXTHIEN_Pos (2) /*!< SPI_T::FIFOCTL: RXTHIEN Position */
#define SPI_FIFOCTL_RXTHIEN_Msk (0x1ul << SPI_FIFOCTL_RXTHIEN_Pos) /*!< SPI_T::FIFOCTL: RXTHIEN Mask */
#define SPI_FIFOCTL_TXTHIEN_Pos (3) /*!< SPI_T::FIFOCTL: TXTHIEN Position */
#define SPI_FIFOCTL_TXTHIEN_Msk (0x1ul << SPI_FIFOCTL_TXTHIEN_Pos) /*!< SPI_T::FIFOCTL: TXTHIEN Mask */
#define SPI_FIFOCTL_RXTOIEN_Pos (4) /*!< SPI_T::FIFOCTL: RXTOIEN Position */
#define SPI_FIFOCTL_RXTOIEN_Msk (0x1ul << SPI_FIFOCTL_RXTOIEN_Pos) /*!< SPI_T::FIFOCTL: RXTOIEN Mask */
#define SPI_FIFOCTL_RXOVIEN_Pos (5) /*!< SPI_T::FIFOCTL: RXOVIEN Position */
#define SPI_FIFOCTL_RXOVIEN_Msk (0x1ul << SPI_FIFOCTL_RXOVIEN_Pos) /*!< SPI_T::FIFOCTL: RXOVIEN Mask */
#define SPI_FIFOCTL_TXUFPOL_Pos (6) /*!< SPI_T::FIFOCTL: TXUFPOL Position */
#define SPI_FIFOCTL_TXUFPOL_Msk (0x1ul << SPI_FIFOCTL_TXUFPOL_Pos) /*!< SPI_T::FIFOCTL: TXUFPOL Mask */
#define SPI_FIFOCTL_TXUFIEN_Pos (7) /*!< SPI_T::FIFOCTL: TXUFIEN Position */
#define SPI_FIFOCTL_TXUFIEN_Msk (0x1ul << SPI_FIFOCTL_TXUFIEN_Pos) /*!< SPI_T::FIFOCTL: TXUFIEN Mask */
#define SPI_FIFOCTL_RXFBCLR_Pos (8) /*!< SPI_T::FIFOCTL: RXFBCLR Position */
#define SPI_FIFOCTL_RXFBCLR_Msk (0x1ul << SPI_FIFOCTL_RXFBCLR_Pos) /*!< SPI_T::FIFOCTL: RXFBCLR Mask */
#define SPI_FIFOCTL_TXFBCLR_Pos (9) /*!< SPI_T::FIFOCTL: TXFBCLR Position */
#define SPI_FIFOCTL_TXFBCLR_Msk (0x1ul << SPI_FIFOCTL_TXFBCLR_Pos) /*!< SPI_T::FIFOCTL: TXFBCLR Mask */
#define SPI_FIFOCTL_SLVBERX_Pos (10) /*!< SPI_T::FIFOCTL: SLVBERX Position */
#define SPI_FIFOCTL_SLVBERX_Msk (0x1ul << SPI_FIFOCTL_SLVBERX_Pos) /*!< SPI_T::FIFOCTL: SLVBERX Mask */
#define SPI_FIFOCTL_RXTH_Pos (24) /*!< SPI_T::FIFOCTL: RXTH Position */
#define SPI_FIFOCTL_RXTH_Msk (0x7ul << SPI_FIFOCTL_RXTH_Pos) /*!< SPI_T::FIFOCTL: RXTH Mask */
#define SPI_FIFOCTL_TXTH_Pos (28) /*!< SPI_T::FIFOCTL: TXTH Position */
#define SPI_FIFOCTL_TXTH_Msk (0x7ul << SPI_FIFOCTL_TXTH_Pos) /*!< SPI_T::FIFOCTL: TXTH Mask */
#define SPI_STATUS_BUSY_Pos (0) /*!< SPI_T::STATUS: BUSY Position */
#define SPI_STATUS_BUSY_Msk (0x1ul << SPI_STATUS_BUSY_Pos) /*!< SPI_T::STATUS: BUSY Mask */
#define SPI_STATUS_UNITIF_Pos (1) /*!< SPI_T::STATUS: UNITIF Position */
#define SPI_STATUS_UNITIF_Msk (0x1ul << SPI_STATUS_UNITIF_Pos) /*!< SPI_T::STATUS: UNITIF Mask */
#define SPI_STATUS_SSACTIF_Pos (2) /*!< SPI_T::STATUS: SSACTIF Position */
#define SPI_STATUS_SSACTIF_Msk (0x1ul << SPI_STATUS_SSACTIF_Pos) /*!< SPI_T::STATUS: SSACTIF Mask */
#define SPI_STATUS_SSINAIF_Pos (3) /*!< SPI_T::STATUS: SSINAIF Position */
#define SPI_STATUS_SSINAIF_Msk (0x1ul << SPI_STATUS_SSINAIF_Pos) /*!< SPI_T::STATUS: SSINAIF Mask */
#define SPI_STATUS_SSLINE_Pos (4) /*!< SPI_T::STATUS: SSLINE Position */
#define SPI_STATUS_SSLINE_Msk (0x1ul << SPI_STATUS_SSLINE_Pos) /*!< SPI_T::STATUS: SSLINE Mask */
#define SPI_STATUS_SLVBEIF_Pos (6) /*!< SPI_T::STATUS: SLVBEIF Position */
#define SPI_STATUS_SLVBEIF_Msk (0x1ul << SPI_STATUS_SLVBEIF_Pos) /*!< SPI_T::STATUS: SLVBEIF Mask */
#define SPI_STATUS_SLVURIF_Pos (7) /*!< SPI_T::STATUS: SLVURIF Position */
#define SPI_STATUS_SLVURIF_Msk (0x1ul << SPI_STATUS_SLVURIF_Pos) /*!< SPI_T::STATUS: SLVURIF Mask */
#define SPI_STATUS_RXEMPTY_Pos (8) /*!< SPI_T::STATUS: RXEMPTY Position */
#define SPI_STATUS_RXEMPTY_Msk (0x1ul << SPI_STATUS_RXEMPTY_Pos) /*!< SPI_T::STATUS: RXEMPTY Mask */
#define SPI_STATUS_RXFULL_Pos (9) /*!< SPI_T::STATUS: RXFULL Position */
#define SPI_STATUS_RXFULL_Msk (0x1ul << SPI_STATUS_RXFULL_Pos) /*!< SPI_T::STATUS: RXFULL Mask */
#define SPI_STATUS_RXTHIF_Pos (10) /*!< SPI_T::STATUS: RXTHIF Position */
#define SPI_STATUS_RXTHIF_Msk (0x1ul << SPI_STATUS_RXTHIF_Pos) /*!< SPI_T::STATUS: RXTHIF Mask */
#define SPI_STATUS_RXOVIF_Pos (11) /*!< SPI_T::STATUS: RXOVIF Position */
#define SPI_STATUS_RXOVIF_Msk (0x1ul << SPI_STATUS_RXOVIF_Pos) /*!< SPI_T::STATUS: RXOVIF Mask */
#define SPI_STATUS_RXTOIF_Pos (12) /*!< SPI_T::STATUS: RXTOIF Position */
#define SPI_STATUS_RXTOIF_Msk (0x1ul << SPI_STATUS_RXTOIF_Pos) /*!< SPI_T::STATUS: RXTOIF Mask */
#define SPI_STATUS_SPIENSTS_Pos (15) /*!< SPI_T::STATUS: SPIENSTS Position */
#define SPI_STATUS_SPIENSTS_Msk (0x1ul << SPI_STATUS_SPIENSTS_Pos) /*!< SPI_T::STATUS: SPIENSTS Mask */
#define SPI_STATUS_TXEMPTY_Pos (16) /*!< SPI_T::STATUS: TXEMPTY Position */
#define SPI_STATUS_TXEMPTY_Msk (0x1ul << SPI_STATUS_TXEMPTY_Pos) /*!< SPI_T::STATUS: TXEMPTY Mask */
#define SPI_STATUS_TXFULL_Pos (17) /*!< SPI_T::STATUS: TXFULL Position */
#define SPI_STATUS_TXFULL_Msk (0x1ul << SPI_STATUS_TXFULL_Pos) /*!< SPI_T::STATUS: TXFULL Mask */
#define SPI_STATUS_TXTHIF_Pos (18) /*!< SPI_T::STATUS: TXTHIF Position */
#define SPI_STATUS_TXTHIF_Msk (0x1ul << SPI_STATUS_TXTHIF_Pos) /*!< SPI_T::STATUS: TXTHIF Mask */
#define SPI_STATUS_TXUFIF_Pos (19) /*!< SPI_T::STATUS: TXUFIF Position */
#define SPI_STATUS_TXUFIF_Msk (0x1ul << SPI_STATUS_TXUFIF_Pos) /*!< SPI_T::STATUS: TXUFIF Mask */
#define SPI_STATUS_FIFOCLR_Pos (22) /*!< SPI_T::STATUS: FIFOCLR Position */
#define SPI_STATUS_FIFOCLR_Msk (0x1ul << SPI_STATUS_FIFOCLR_Pos) /*!< SPI_T::STATUS: FIFOCLR Mask */
#define SPI_STATUS_TXRXRST_Pos (23) /*!< SPI_T::STATUS: TXRXRST Position */
#define SPI_STATUS_TXRXRST_Msk (0x1ul << SPI_STATUS_TXRXRST_Pos) /*!< SPI_T::STATUS: TXRXRST Mask */
#define SPI_STATUS_RXCNT_Pos (24) /*!< SPI_T::STATUS: RXCNT Position */
#define SPI_STATUS_RXCNT_Msk (0xful << SPI_STATUS_RXCNT_Pos) /*!< SPI_T::STATUS: RXCNT Mask */
#define SPI_STATUS_TXCNT_Pos (28) /*!< SPI_T::STATUS: TXCNT Position */
#define SPI_STATUS_TXCNT_Msk (0xful << SPI_STATUS_TXCNT_Pos) /*!< SPI_T::STATUS: TXCNT Mask */
#define SPI_STATUS2_RXCPDMA_Pos (8) /*!< SPI_T::STATUS2: RXCPDMA Position */
#define SPI_STATUS2_RXCPDMA_Msk (0x1ful << SPI_STATUS2_RXCPDMA_Pos) /*!< SPI_T::STATUS2: RXCPDMA Mask */
#define SPI_STATUS2_TXCPDMA_Pos (16) /*!< SPI_T::STATUS2: TXCPDMA Position */
#define SPI_STATUS2_TXCPDMA_Msk (0x1ful << SPI_STATUS2_TXCPDMA_Pos) /*!< SPI_T::STATUS2: TXCPDMA Mask */
#define SPI_STATUS2_SLVBENUM_Pos (24) /*!< SPI_T::STATUS2: SLVBENUM Position */
#define SPI_STATUS2_SLVBENUM_Msk (0x3ful << SPI_STATUS2_SLVBENUM_Pos) /*!< SPI_T::STATUS2: SLVBENUM Mask */
#define SPI_TX_TX_Pos (0) /*!< SPI_T::TX: TX Position */
#define SPI_TX_TX_Msk (0xfffffffful << SPI_TX_TX_Pos) /*!< SPI_T::TX: TX Mask */
#define SPI_RX_RX_Pos (0) /*!< SPI_T::RX: RX Position */
#define SPI_RX_RX_Msk (0xfffffffful << SPI_RX_RX_Pos) /*!< SPI_T::RX: RX Mask */
#define SPI_INTERNAL_MRXPHASE_Pos (12) /*!< SPI_T::INTERNAL: CLKDLY_SEL Position */
#define SPI_INTERNAL_MRXPHASE_Msk (0xful << SPI_INTERNAL_MRXPHASE_Pos) /*!< SPI_T::INTERNAL: CLKDLY_SEL Mask */
#define SPI_I2SCTL_I2SEN_Pos (0) /*!< SPI_T::I2SCTL: I2SEN Position */
#define SPI_I2SCTL_I2SEN_Msk (0x1ul << SPI_I2SCTL_I2SEN_Pos) /*!< SPI_T::I2SCTL: I2SEN Mask */
#define SPI_I2SCTL_TXEN_Pos (1) /*!< SPI_T::I2SCTL: TXEN Position */
#define SPI_I2SCTL_TXEN_Msk (0x1ul << SPI_I2SCTL_TXEN_Pos) /*!< SPI_T::I2SCTL: TXEN Mask */
#define SPI_I2SCTL_RXEN_Pos (2) /*!< SPI_T::I2SCTL: RXEN Position */
#define SPI_I2SCTL_RXEN_Msk (0x1ul << SPI_I2SCTL_RXEN_Pos) /*!< SPI_T::I2SCTL: RXEN Mask */
#define SPI_I2SCTL_MUTE_Pos (3) /*!< SPI_T::I2SCTL: MUTE Position */
#define SPI_I2SCTL_MUTE_Msk (0x1ul << SPI_I2SCTL_MUTE_Pos) /*!< SPI_T::I2SCTL: MUTE Mask */
#define SPI_I2SCTL_WDWIDTH_Pos (4) /*!< SPI_T::I2SCTL: WDWIDTH Position */
#define SPI_I2SCTL_WDWIDTH_Msk (0x3ul << SPI_I2SCTL_WDWIDTH_Pos) /*!< SPI_T::I2SCTL: WDWIDTH Mask */
#define SPI_I2SCTL_MONO_Pos (6) /*!< SPI_T::I2SCTL: MONO Position */
#define SPI_I2SCTL_MONO_Msk (0x1ul << SPI_I2SCTL_MONO_Pos) /*!< SPI_T::I2SCTL: MONO Mask */
#define SPI_I2SCTL_ORDER_Pos (7) /*!< SPI_T::I2SCTL: ORDER Position */
#define SPI_I2SCTL_ORDER_Msk (0x1ul << SPI_I2SCTL_ORDER_Pos) /*!< SPI_T::I2SCTL: ORDER Mask */
#define SPI_I2SCTL_SLAVE_Pos (8) /*!< SPI_T::I2SCTL: SLAVE Position */
#define SPI_I2SCTL_SLAVE_Msk (0x1ul << SPI_I2SCTL_SLAVE_Pos) /*!< SPI_T::I2SCTL: SLAVE Mask */
#define SPI_I2SCTL_MCLKEN_Pos (15) /*!< SPI_T::I2SCTL: MCLKEN Position */
#define SPI_I2SCTL_MCLKEN_Msk (0x1ul << SPI_I2SCTL_MCLKEN_Pos) /*!< SPI_T::I2SCTL: MCLKEN Mask */
#define SPI_I2SCTL_RZCEN_Pos (16) /*!< SPI_T::I2SCTL: RZCEN Position */
#define SPI_I2SCTL_RZCEN_Msk (0x1ul << SPI_I2SCTL_RZCEN_Pos) /*!< SPI_T::I2SCTL: RZCEN Mask */
#define SPI_I2SCTL_LZCEN_Pos (17) /*!< SPI_T::I2SCTL: LZCEN Position */
#define SPI_I2SCTL_LZCEN_Msk (0x1ul << SPI_I2SCTL_LZCEN_Pos) /*!< SPI_T::I2SCTL: LZCEN Mask */
#define SPI_I2SCTL_RXLCH_Pos (23) /*!< SPI_T::I2SCTL: RXLCH Position */
#define SPI_I2SCTL_RXLCH_Msk (0x1ul << SPI_I2SCTL_RXLCH_Pos) /*!< SPI_T::I2SCTL: RXLCH Mask */
#define SPI_I2SCTL_RZCIEN_Pos (24) /*!< SPI_T::I2SCTL: RZCIEN Position */
#define SPI_I2SCTL_RZCIEN_Msk (0x1ul << SPI_I2SCTL_RZCIEN_Pos) /*!< SPI_T::I2SCTL: RZCIEN Mask */
#define SPI_I2SCTL_LZCIEN_Pos (25) /*!< SPI_T::I2SCTL: LZCIEN Position */
#define SPI_I2SCTL_LZCIEN_Msk (0x1ul << SPI_I2SCTL_LZCIEN_Pos) /*!< SPI_T::I2SCTL: LZCIEN Mask */
#define SPI_I2SCTL_FORMAT_Pos (28) /*!< SPI_T::I2SCTL: FORMAT Position */
#define SPI_I2SCTL_FORMAT_Msk (0x3ul << SPI_I2SCTL_FORMAT_Pos) /*!< SPI_T::I2SCTL: FORMAT Mask */
#define SPI_I2SCTL_SLVERRIEN_Pos (31) /*!< SPI_T::I2SCTL: SLVERRIEN Position */
#define SPI_I2SCTL_SLVERRIEN_Msk (0x1ul << SPI_I2SCTL_SLVERRIEN_Pos) /*!< SPI_T::I2SCTL: SLVERRIEN Mask */
#define SPI_I2SCLK_MCLKDIV_Pos (0) /*!< SPI_T::I2SCLK: MCLKDIV Position */
#define SPI_I2SCLK_MCLKDIV_Msk (0x7ful << SPI_I2SCLK_MCLKDIV_Pos) /*!< SPI_T::I2SCLK: MCLKDIV Mask */
#define SPI_I2SCLK_BCLKDIV_Pos (8) /*!< SPI_T::I2SCLK: BCLKDIV Position */
#define SPI_I2SCLK_BCLKDIV_Msk (0x3fful << SPI_I2SCLK_BCLKDIV_Pos) /*!< SPI_T::I2SCLK: BCLKDIV Mask */
#define SPI_I2SCLK_I2SMODE_Pos (24) /*!< SPI_T::I2SCLK: I2SMODE Position */
#define SPI_I2SCLK_I2SMODE_Msk (0x1ul << SPI_I2SCLK_I2SMODE_Pos) /*!< SPI_T::I2SCLK: I2SMODE Mask */
#define SPI_I2SCLK_I2SSLAVE_Pos (25) /*!< SPI_T::I2SCLK: I2SSLAVE Position */
#define SPI_I2SCLK_I2SSLAVE_Msk (0x1ul << SPI_I2SCLK_I2SSLAVE_Pos) /*!< SPI_T::I2SCLK: I2SSLAVE Mask */
#define SPI_I2SSTS_RIGHT_Pos (4) /*!< SPI_T::I2SSTS: RIGHT Position */
#define SPI_I2SSTS_RIGHT_Msk (0x1ul << SPI_I2SSTS_RIGHT_Pos) /*!< SPI_T::I2SSTS: RIGHT Mask */
#define SPI_I2SSTS_RXEMPTY_Pos (8) /*!< SPI_T::I2SSTS: RXEMPTY Position */
#define SPI_I2SSTS_RXEMPTY_Msk (0x1ul << SPI_I2SSTS_RXEMPTY_Pos) /*!< SPI_T::I2SSTS: RXEMPTY Mask */
#define SPI_I2SSTS_RXFULL_Pos (9) /*!< SPI_T::I2SSTS: RXFULL Position */
#define SPI_I2SSTS_RXFULL_Msk (0x1ul << SPI_I2SSTS_RXFULL_Pos) /*!< SPI_T::I2SSTS: RXFULL Mask */
#define SPI_I2SSTS_RXTHIF_Pos (10) /*!< SPI_T::I2SSTS: RXTHIF Position */
#define SPI_I2SSTS_RXTHIF_Msk (0x1ul << SPI_I2SSTS_RXTHIF_Pos) /*!< SPI_T::I2SSTS: RXTHIF Mask */
#define SPI_I2SSTS_RXOVIF_Pos (11) /*!< SPI_T::I2SSTS: RXOVIF Position */
#define SPI_I2SSTS_RXOVIF_Msk (0x1ul << SPI_I2SSTS_RXOVIF_Pos) /*!< SPI_T::I2SSTS: RXOVIF Mask */
#define SPI_I2SSTS_RXTOIF_Pos (12) /*!< SPI_T::I2SSTS: RXTOIF Position */
#define SPI_I2SSTS_RXTOIF_Msk (0x1ul << SPI_I2SSTS_RXTOIF_Pos) /*!< SPI_T::I2SSTS: RXTOIF Mask */
#define SPI_I2SSTS_I2SENSTS_Pos (15) /*!< SPI_T::I2SSTS: I2SENSTS Position */
#define SPI_I2SSTS_I2SENSTS_Msk (0x1ul << SPI_I2SSTS_I2SENSTS_Pos) /*!< SPI_T::I2SSTS: I2SENSTS Mask */
#define SPI_I2SSTS_TXEMPTY_Pos (16) /*!< SPI_T::I2SSTS: TXEMPTY Position */
#define SPI_I2SSTS_TXEMPTY_Msk (0x1ul << SPI_I2SSTS_TXEMPTY_Pos) /*!< SPI_T::I2SSTS: TXEMPTY Mask */
#define SPI_I2SSTS_TXFULL_Pos (17) /*!< SPI_T::I2SSTS: TXFULL Position */
#define SPI_I2SSTS_TXFULL_Msk (0x1ul << SPI_I2SSTS_TXFULL_Pos) /*!< SPI_T::I2SSTS: TXFULL Mask */
#define SPI_I2SSTS_TXTHIF_Pos (18) /*!< SPI_T::I2SSTS: TXTHIF Position */
#define SPI_I2SSTS_TXTHIF_Msk (0x1ul << SPI_I2SSTS_TXTHIF_Pos) /*!< SPI_T::I2SSTS: TXTHIF Mask */
#define SPI_I2SSTS_TXUFIF_Pos (19) /*!< SPI_T::I2SSTS: TXUFIF Position */
#define SPI_I2SSTS_TXUFIF_Msk (0x1ul << SPI_I2SSTS_TXUFIF_Pos) /*!< SPI_T::I2SSTS: TXUFIF Mask */
#define SPI_I2SSTS_RZCIF_Pos (20) /*!< SPI_T::I2SSTS: RZCIF Position */
#define SPI_I2SSTS_RZCIF_Msk (0x1ul << SPI_I2SSTS_RZCIF_Pos) /*!< SPI_T::I2SSTS: RZCIF Mask */
#define SPI_I2SSTS_LZCIF_Pos (21) /*!< SPI_T::I2SSTS: LZCIF Position */
#define SPI_I2SSTS_LZCIF_Msk (0x1ul << SPI_I2SSTS_LZCIF_Pos) /*!< SPI_T::I2SSTS: LZCIF Mask */
#define SPI_I2SSTS_SLVERRIF_Pos (22) /*!< SPI_T::I2SSTS: SLVERRIF Position */
#define SPI_I2SSTS_SLVERRIF_Msk (0x1ul << SPI_I2SSTS_SLVERRIF_Pos) /*!< SPI_T::I2SSTS: SLVERRIF Mask */
#define SPI_I2SSTS_TXRXRST_Pos (23) /*!< SPI_T::I2SSTS: TXRXRST Position */
#define SPI_I2SSTS_TXRXRST_Msk (0x1ul << SPI_I2SSTS_TXRXRST_Pos) /*!< SPI_T::I2SSTS: TXRXRST Mask */
#define SPI_I2SSTS_RXCNT_Pos (24) /*!< SPI_T::I2SSTS: RXCNT Position */
#define SPI_I2SSTS_RXCNT_Msk (0x7ul << SPI_I2SSTS_RXCNT_Pos) /*!< SPI_T::I2SSTS: RXCNT Mask */
#define SPI_I2SSTS_TXCNT_Pos (28) /*!< SPI_T::I2SSTS: TXCNT Position */
#define SPI_I2SSTS_TXCNT_Msk (0x7ul << SPI_I2SSTS_TXCNT_Pos) /*!< SPI_T::I2SSTS: TXCNT Mask */
/**@}*/ /* SPI_CONST */
/**@}*/ /* end of SPI register group */
/**@}*/ /* end of REGISTER group */
#if defined ( __CC_ARM )
#pragma no_anon_unions
#endif
#endif /* __SPI_REG_H__ */

932
bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/ssmcc_reg.h Normal file
View File

@ -0,0 +1,932 @@
/**************************************************************************//**
* @file ssmcc_reg.h
* @brief SSMCC register definition header file
*
* SPDX-License-Identifier: Apache-2.0
* @copyright (C) 2021 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __SSMCC_REG_H__
#define __SSMCC_REG_H__
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
/******************************************************************************/
/* Device Specific Peripheral registers structures */
/******************************************************************************/
/** @addtogroup REGISTER Control Register
@{
*/
typedef struct
{
/**
* @var FAIL_T::ADDRESS_LOW
* Offset: 0x20 Contains the lower 32 bits of the address of the first access that failed a region permission check in the associated filter unit.
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |addr_status_low|If a region permission check fails or a region overlap occurs, this field returns the ACE-Lite address bits [31:0] of the first f. You must clear the associated interrupt status before this field can return the address of accesses of subsequent permission checks or region overlap failures. This occurs even if the ACTION register does not enable the interrupt. If the status flag for the filter unit in the INT_STATUS register is already set, new region permission check failures in the same filter unit do not update the associated fail status group of registers.
* @var FAIL_T::ADDRESS_HIGH
* Offset: 0x24 Reserved
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* @var FAIL_T::CONTROL
* Offset: 0x28 Contains the control status information of the first access that failed a region permission check in the associated filter unit.
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[20] |Privileged|If a region permission check fails or a region overlap occurs, this field indicates whether it was an unprivileged or privileged access attempt You must clear the associated interrupt status before this field can return the values of accesses of subsequent permission checks or region overlap failures 0 Unprivileged access 1 Privileged access If the status flag for the filter unit in the INT_STATUS register is already set, new region permission check failures in the same filter unit do not update the associated fail status group of registers.
* |[21] |Non_secure|If a region permission check fails or a region overlap occurs, this field indicates whether it was a Secure or Non- secure access attempt You must clear the associated interrupt status before this field can return the direction of accesses of subsequent permission checks or region overlap failures 0 Secure access 1 Non-secure access If the status flag for the filter unit in the INT_STATUS register is already set, new region permission check failures in the same filter unit do not update the associated fail status group of registers.
* |[24] |Direction |If a region permission check fails or a region overlap occurs, this field indicates whether the failed access was a read or write access attempt You must clear the associated interrupt status before this field can return the direction of accesses of subsequent permission checks or region overlap failures 0 Read access 1 Write access If the status flag for the filter unit in the INT_STATUS register is already set, new region permission check failures in the same filter unit do not update the associated fail status group of registers.
* @var FAIL_T::ID
* Offset: 0x2C Contains the master ACE-Lite ARID or AWID of the first access that failed a region permission check in the associated filter unit.
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[5:0] |id |If a region permission check fails or a region overlap occurs, this field returns the ACE-Lite ID values of the first failed access If the status flag for the filter unit in the INT_STATUS register is already set, new region permission check failures in the same filter unit do not update the associated fail status group of registers.
* |[27:24] |vnet |If a region permission check fails or a region overlap occurs, this field returns the VN number of the first failed access, from either ARVNET<x> or AWVNET<x> as appropriate If the status flag for the filter unit in the INT_STATUS register is already set, new region permission check failures in the same filter unit do not update the associated fail status group of registers.
*/
__I uint32_t ADDRESS_LOW; /*!< [0x0000] Contains the lower 32 bits of the address of the first access that failed a region permission check in the associated filter unit. */
__IO uint32_t ADDRESS_HIGH; /*!< [0x0004] Reserved */
__I uint32_t CONTROL; /*!< [0x0008] Contains the control status information of the first access that failed a region permission check in the associated filter unit. */
__I uint32_t ID; /*!< [0x000c] Contains the master ACE-Lite ARID or AWID of the first access that failed a region permission check in the associated filter unit. */
} FAIL_STS_T;
typedef struct
{
__IO uint32_t BASE_LOW; /*!< [0x0000] */
__IO uint32_t BASE_HIGH; /*!< [0x0004] */
__IO uint32_t TOP_LOW; /*!< [0x0008] */
__IO uint32_t TOP_HIGH; /*!< [0x000c] */
__IO uint32_t ATTRIBUTES; /*!< [0x0010] */
__IO uint32_t ID_ACCESS; /*!< [0x0014] */
__I uint32_t RESERVE2[2]; /*!< [0x0018] */
} REGION_T;
/*---------------------- System Security Memory Configuration Controller -------------------------*/
/**
@addtogroup SSMCC System Security Memory Configuration Controller(SSMCC)
Memory Mapped Structure for SSMCC Controller
@{ */
typedef struct
{
/**
* @var SSMCC_T::SCWP
* Offset: 0x00 Security Configuration Write Protect Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |ENABLE |Write Protection Enable Bit
* | | |0 = Security Configuration Write Protection Disabled.
* | | |1 = Security Configuration Write Protection Enabled.
* |[1] |LOCK |Write Protection Enable and Lock Bit (Write 1 to Set)
* | | |0 = Security Configuration Write Protection Disabled.
* | | |1 = Security Configuration Write Protection Enabled.
* | | |Note: This bit can only be cleared by system reset.
* |[31:16] |WVCODE |Write Verify Code
* | | |Read operation:
* | | |Reserved, all zeros.
* | | |Write operation:
* | | |0x475A = The write verify code, 0x475A, is needed to do a valid write to SSMCC_SCWP.
* | | |Others = Invalid write verify code.
*/
__IO uint32_t SCWP; /*!< [0x0000] Security Configuration Write Protect Register */
} SSMCC_T;
/**
@addtogroup SSMCC_CONST SSMCC Bit Field Definition
Constant Definitions for SSMCC Controller
@{ */
#define SSMCC_SCWP_ENABLE_Pos (0) /*!< SSMCC_T::SCWP: ENABLE Position */
#define SSMCC_SCWP_ENABLE_Msk (0x1ul << SSMCC_SCWP_ENABLE_Pos) /*!< SSMCC_T::SCWP: ENABLE Mask */
#define SSMCC_SCWP_LOCK_Pos (1) /*!< SSMCC_T::SCWP: LOCK Position */
#define SSMCC_SCWP_LOCK_Msk (0x1ul << SSMCC_SCWP_LOCK_Pos) /*!< SSMCC_T::SCWP: LOCK Mask */
#define SSMCC_SCWP_WVCODE_Pos (16) /*!< SSMCC_T::SCWP: WVCODE Position */
#define SSMCC_SCWP_WVCODE_Msk (0xfffful << SSMCC_SCWP_WVCODE_Pos) /*!< SSMCC_T::SCWP: WVCODE Mask */
/**@}*/ /* SSMCC_CONST */
/**@}*/ /* end of SSMCC register group */
/*---------------------- TrustZone Address Space Controller -------------------------*/
/**
@addtogroup TZC TrustZone Address Space Controller(TZC)
Memory Mapped Structure for TZC Controller
@{ */
typedef struct
{
/**
* @var TZC_T::BUILD_CONFIG
* Offset: 0x00 Provides information about the configuration of the TZC-400.
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[4:0] |no_of_regions|Defines the number of regions that the TZC-400 provides: 0b01000 Nine regions All other values Reserved.
* |[13:8] |address_width|Defines the width of the ACE-Lite address bus: 0b011111 32 bits 0b100011 36 bits 0b100111 40 bits 0b101111 48 bits 0b111111 64 bits All other values Reserved.
* |[25:24] |no_of_filters|Defines the number of filter units in the design implementation: 0b00 One filter unit 0b01 Two filter units 0b10 Reserved 0b11 Four filter units.
* @var TZC_T::ACTION
* Offset: 0x04 Controls the interrupt and bus response signaling behavior of the TZC-400 when region permission failures occur.
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[1:0] |reaction_value|Controls how the TZC-400 uses the BRESPS[1:0], RRESPS[1:0], and TZCINT signals when a region permission failure occurs, excluding region overlap errors The settings for these bits are: 0b00 Sets TZCINT LOW and issues an OKAY response 0b01 Sets TZCINT LOW and issues a DECERR response 0b10 Sets TZCINT HIGH and issues an OKAY response 0b11 Sets TZCINT HIGH and issues a DECERR response When a region overlap for region 1 and higher occurs, this field also determines how TZCINT is set The settings are: 0b00, 0b01 TZCINT LOW 0b10, 0b11 TZCINT HIGH.
* @var TZC_T::GATE_KEEPER
* Offset: 0x08 Provides control and status for the gate keeper in each filter unit implemented
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[3:0] |open_request|Each bit in this field requests the gate of the associated filter unit to be open or closed Each bit is associated as follows: bit 0 Filter 0 bit 1 Filter 1 bit 2 Filter 2 bit 3 Filter 3. Set the open_request bit to 1, to request the gate to be open Set the open_request bit to 0, to request the gate to be closed If any of the associated filter units are not implemented, the corresponding open_request bits are unused,
* |[19:16] |open_status|The current state of the gate keeper in each filter unit The bit associations are as follows: bit 16 Filter 0 gate keeper status bit 17 Filter 1 gate keeper status bit 18 Filter 2 gate keeper status bit 19 Filter 3 gate keeper status When a bit is set to 1, the gate keeper permits access to its associated filter, that is, it is open When a bit is set to 0, the gate keeper no longer permits access to its associated filter, that is, it is closed This bit is set to 0 when both of the following conditions are fulfilled:This means that the gate keeper always waits for outstanding accesses to complete &#8226; The gate keeper no longer permits access to its associated filter &#8226; All outstanding accesses through the filter unit are complete If any of the associated filter units are not implemented, the corresponding gate keeper bits are unused,
* @var TZC_T::SPECULATION_CTRL
* Offset: 0x0C Controls the read access speculation and write access speculation.
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |read_spec_disable|Controls read access speculation Note This bit is ignored and assumed to be zero at a filter unit if the corresponding QVNENABLE<x> signal is HIGH You can set this bit as follows: 0 Enables read access speculation This is the default setting 1 Disables read access speculation.
* |[1] |write_spec_disable|Controls write acc. Note This bit is ignored and assumed to be zero at a filter unit if the corresponding QVNENABLE<x> signal is HIGH. Set this bit as follows: 0 Enables write access speculation. This is the default setting. 1 Disables write access speculation.
* @var TZC_T::INT_STATUS
* Offset: 0x10 Contains the status of the interrupt signal, TZCINT, that reports access security violations or region overlap errors.
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[3:0] |status |Each bit is associated as follows: bit 0 Filter 0 bit 1 Filter 1 bit 2 Filter 2 bit 3 Filter 3. Each bit in this field indicates the status of the interrupt from each filter unit as follows: 0 Interrupt is not asserted 1 Interrupt is asserted and waiting to be cleared This bit is set even if the ACTION register is set to not drive the interrupt output TZCINT HIGH Therefore, the status acts as an indicator that a region permission check failure or an overlap error has occurred at a particular filter unit.
* |[11:8] |overrun |The bit associations are as follows: bit 8 Filter 0 bit 9 Filter 1 bit 10 Filter 2 bit 11 Filter 3. When a bit is set to 1, it indicates the occurrence of two or more region permission or region overlapping failures at the associated filter unit after the interrupt was cleared by the associated bit This bit is set even if the ACTION register is set to not drive the interrupt Clear the interrupt status of the associated bit in the INT_CLEAR register to also clear this field.
* |[19:16] |overlap |The bit associations are as follows: bit 16 Filter 0 bit 17 Filter 1 bit 18 Filter 2 bit 19 Filter 3 When a bit is set to 1, it indicates a violation of the overlap region configuration rules for the associated filter unit This occurs when an access matches with two enabled regions at the same time unless the overlap is only with Region 0. This bit is set even if the ACTION register is set to not drive the interrupt When this bit is 1, the interrupt status bit is also set to 1. Clear the interrupt status of the associated bit to also clear this field
* @var TZC_T::INT_CLEAR
* Offset: 0x14 Clears the interrupt.
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[3:0] |clear |Contains the control bits to clear interrupts The bit associations are as follows: bit 0 Filter 0 bit 1 Filter 1 bit 2 Filter 2 bit 3 Filter 3. Write a 1 to any of these bits to clear the associated status, overrun, and overlap bits in the INT_STATUS register.
* @var TZC_T::FAIL_ADDRESS_LOW_0
* Offset: 0x20 Contains the lower 32 bits of the address of the first access that failed a region permission check in the associated filter unit.
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |addr_status_low|If a region permission check fails or a region overlap occurs, this field returns the ACE-Lite address bits [31:0] of the first f. You must clear the associated interrupt status before this field can return the address of accesses of subsequent permission checks or region overlap failures. This occurs even if the ACTION register does not enable the interrupt. If the status flag for the filter unit in the INT_STATUS register is already set, new region permission check failures in the same filter unit do not update the associated fail status group of registers.
* @var TZC_T::FAIL_ADDRESS_HIGH_0
* Offset: 0x24 Reserved
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* @var TZC_T::FAIL_CONTROL_0
* Offset: 0x28 Contains the control status information of the first access that failed a region permission check in the associated filter unit.
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[20] |Privileged|If a region permission check fails or a region overlap occurs, this field indicates whether it was an unprivileged or privileged access attempt You must clear the associated interrupt status before this field can return the values of accesses of subsequent permission checks or region overlap failures 0 Unprivileged access 1 Privileged access If the status flag for the filter unit in the INT_STATUS register is already set, new region permission check failures in the same filter unit do not update the associated fail status group of registers.
* |[21] |Non_secure|If a region permission check fails or a region overlap occurs, this field indicates whether it was a Secure or Non- secure access attempt You must clear the associated interrupt status before this field can return the direction of accesses of subsequent permission checks or region overlap failures 0 Secure access 1 Non-secure access If the status flag for the filter unit in the INT_STATUS register is already set, new region permission check failures in the same filter unit do not update the associated fail status group of registers.
* |[24] |Direction |If a region permission check fails or a region overlap occurs, this field indicates whether the failed access was a read or write access attempt You must clear the associated interrupt status before this field can return the direction of accesses of subsequent permission checks or region overlap failures 0 Read access 1 Write access If the status flag for the filter unit in the INT_STATUS register is already set, new region permission check failures in the same filter unit do not update the associated fail status group of registers.
* @var TZC_T::FAIL_ID_0
* Offset: 0x2C Contains the master ACE-Lite ARID or AWID of the first access that failed a region permission check in the associated filter unit.
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[5:0] |id |If a region permission check fails or a region overlap occurs, this field returns the ACE-Lite ID values of the first failed access If the status flag for the filter unit in the INT_STATUS register is already set, new region permission check failures in the same filter unit do not update the associated fail status group of registers.
* |[27:24] |vnet |If a region permission check fails or a region overlap occurs, this field returns the VN number of the first failed access, from either ARVNET<x> or AWVNET<x> as appropriate If the status flag for the filter unit in the INT_STATUS register is already set, new region permission check failures in the same filter unit do not update the associated fail status group of registers.
* @var TZC_T::FAIL_ADDRESS_LOW_1
* Offset: 0x30 Contains the lower 32 bits of the address of the first access that failed a region permission check in the associated filter unit.
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |addr_status_low|If a region permission check fails or a region overlap occurs, this field returns the ACE-Lite address bits [31:0] of the first f. You must clear the associated interrupt status before this field can return the address of accesses of subsequent permission checks or region overlap failures. This occurs even if the ACTION register does not enable the interrupt. If the status flag for the filter unit in the INT_STATUS register is already set, new region permission check failures in the same filter unit do not update the associated fail status group of registers.
* @var TZC_T::FAIL_ADDRESS_HIGH_1
* Offset: 0x34 Reserved
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* @var TZC_T::FAIL_CONTROL_1
* Offset: 0x38 Contains the control status information of the first access that failed a region permission check in the associated filter unit.
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[20] |Privileged|If a region permission check fails or a region overlap occurs, this field indicates whether it was an unprivileged or privileged access attempt You must clear the associated interrupt status before this field can return the values of accesses of subsequent permission checks or region overlap failures 0 Unprivileged access 1 Privileged access If the status flag for the filter unit in the INT_STATUS register is already set, new region permission check failures in the same filter unit do not update the associated fail status group of registers.
* |[21] |Non_secure|If a region permission check fails or a region overlap occurs, this field indicates whether it was a Secure or Non- secure access attempt You must clear the associated interrupt status before this field can return the direction of accesses of subsequent permission checks or region overlap failures 0 Secure access 1 Non-secure access If the status flag for the filter unit in the INT_STATUS register is already set, new region permission check failures in the same filter unit do not update the associated fail status group of registers.
* |[24] |Direction |If a region permission check fails or a region overlap occurs, this field indicates whether the failed access was a read or write access attempt You must clear the associated interrupt status before this field can return the direction of accesses of subsequent permission checks or region overlap failures 0 Read access 1 Write access If the status flag for the filter unit in the INT_STATUS register is already set, new region permission check failures in the same filter unit do not update the associated fail status group of registers.
* @var TZC_T::FAIL_ID_1
* Offset: 0x3C Contains the master ACE-Lite ARID or AWID of the first access that failed a region permission check in the associated filter unit.
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[5:0] |id |If a region permission check fails or a region overlap occurs, this field returns the ACE-Lite ID values of the first failed access If the status flag for the filter unit in the INT_STATUS register is already set, new region permission check failures in the same filter unit do not update the associated fail status group of registers.
* |[27:24] |vnet |If a region permission check fails or a region overlap occurs, this field returns the VN number of the first failed access, from either ARVNET<x> or AWVNET<x> as appropriate If the status flag for the filter unit in the INT_STATUS register is already set, new region permission check failures in the same filter unit do not update the associated fail status group of registers.
* @var TZC_T::FAIL_ADDRESS_LOW_2
* Offset: 0x40 Contains the lower 32 bits of the address of the first access that failed a region permission check in the associated filter unit.
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |addr_status_low|If a region permission check fails or a region overlap occurs, this field returns the ACE-Lite address bits [31:0] of the first f. You must clear the associated interrupt status before this field can return the address of accesses of subsequent permission checks or region overlap failures. This occurs even if the ACTION register does not enable the interrupt. If the status flag for the filter unit in the INT_STATUS register is already set, new region permission check failures in the same filter unit do not update the associated fail status group of registers.
* @var TZC_T::FAIL_ADDRESS_HIGH_2
* Offset: 0x44 Reserved
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* @var TZC_T::FAIL_CONTROL_2
* Offset: 0x48 Contains the control status information of the first access that failed a region permission check in the associated filter unit.
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[20] |Privileged|If a region permission check fails or a region overlap occurs, this field indicates whether it was an unprivileged or privileged access attempt You must clear the associated interrupt status before this field can return the values of accesses of subsequent permission checks or region overlap failures 0 Unprivileged access 1 Privileged access If the status flag for the filter unit in the INT_STATUS register is already set, new region permission check failures in the same filter unit do not update the associated fail status group of registers.
* |[21] |Non_secure|If a region permission check fails or a region overlap occurs, this field indicates whether it was a Secure or Non- secure access attempt You must clear the associated interrupt status before this field can return the direction of accesses of subsequent permission checks or region overlap failures 0 Secure access 1 Non-secure access If the status flag for the filter unit in the INT_STATUS register is already set, new region permission check failures in the same filter unit do not update the associated fail status group of registers.
* |[24] |Direction |If a region permission check fails or a region overlap occurs, this field indicates whether the failed access was a read or write access attempt You must clear the associated interrupt status before this field can return the direction of accesses of subsequent permission checks or region overlap failures 0 Read access 1 Write access If the status flag for the filter unit in the INT_STATUS register is already set, new region permission check failures in the same filter unit do not update the associated fail status group of registers.
* @var TZC_T::FAIL_ID_2
* Offset: 0x4C Contains the master ACE-Lite ARID or AWID of the first access that failed a region permission check in the associated filter unit.
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[5:0] |id |If a region permission check fails or a region overlap occurs, this field returns the ACE-Lite ID values of the first failed access If the status flag for the filter unit in the INT_STATUS register is already set, new region permission check failures in the same filter unit do not update the associated fail status group of registers.
* |[27:24] |vnet |If a region permission check fails or a region overlap occurs, this field returns the VN number of the first failed access, from either ARVNET<x> or AWVNET<x> as appropriate If the status flag for the filter unit in the INT_STATUS register is already set, new region permission check failures in the same filter unit do not update the associated fail status group of registers.
* @var TZC_T::REGION_BASE_LOW_0
* Offset: 0x100 This register is read-only and is hard-wired to all zeros.
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:12] |base_address_low_n_|Controls the base address bits[31:12] of Region <n>
* | | |For Region 0, this field is read-only. The TZC-400 sets the base address of Region 0 to 0x0.
* @var TZC_T::REGION_BASE_HIGH_0
* Offset: 0x104 This register is read-only and is hard-wired to all zeros.
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* @var TZC_T::REGION_TOP_LOW_0
* Offset: 0x108 This register is read-only and is hard-wired to all 1.
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:12] |top_address_low_n_|Controls the region top address bits[31:12] of region <n>
* | | |For Region 0, this field is read-only and all bits are set HIGH.
* | | |.
* @var TZC_T::REGION_TOP_HIGH_0
* Offset: 0x10C This register is read-only and is hard-wired to all zeros.
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* @var TZC_T::REGION_ATTRIBUTES_0
* Offset: 0x110 Controls the permissions for Region 0.
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[3:0] |filter_en |Independent region enable for each filter unit Each bit is associated with a filter unit Set these bits as follows: Bit 0 For Filter 0 Bit 1 For Filter 1 Bit 2 For Filter 2 Bit 3 For Filter 3. When set HIGH, it enables the use of the current region programming for the associated filter For Region 0, all bits are set HIGH and cannot be modified.
* |[30] |s_rd_en |Secure global read enable This control bit defines the permissions for the Secure reads in the region Set this bit as follows: 0 Secure read to the region is not permitted 1 Permits Secure read to the region.
* |[31] |s_wr_en |Secure global write enable This control bit defines the permissions for the Secure writes in the region Set this bit as follows: 0 Secure write to the region is not permitted 1 Permits Secure write to the region.
* @var TZC_T::REGION_ID_ACCESS_0
* Offset: 0x114 Controls the Non-secure access based on the NSAID inputs for Region 0.
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |nsaid_rd_en|NSAID read enables
* | | |This enables NSAID inputs to define Non-secure read access permission Each bit of the nsaid_rd_en register field is associated with a value on the NSAIDR<x> signal as follows: Bit 0 Associated with NSAIDR<x> = 0
* | | |Bit 1 Associated with NSAIDR<x> = 1
* | | |Bit 2 Associated with NSAIDR<x> = 2
* | | |Bit 15 Associated with NSAIDR<x> = 15
* | | |<x> is the filter unit number
* | | |When any bit in this field is set HIGH, TZC-400 permits Non-secure read access to any access with the associated NSAIDR<x> value
* | | |For example, if NSAIDR<x> is 3 and the corresponding nsaid_rd_en[3] bit is set HIGH then TZC-400 permits the Non-secure read access to progress.
* |[31:16] |nsaid_wr_en|NSAID write enables
* | | |This enables NSAID inputs to define Non-secure write access permission Each bit of the nsaid_wr_en register field is associated with a value on the NSAIDW<x> signal as follows: Bit 16 Associated with NSAIDW<x> = 0
* | | |Bit 17 Associated with NSAIDW<x> = 1
* | | |Bit 18 Associated with NSAIDW<x> = 2
* | | |Bit 31 Associated with NSAIDW<x> = 15
* | | |<x> is the filter unit number
* | | |When any bit in this field is set to 1, TZC-400 permits Non-secure write access to any access with the associated NSAIDW<x> value
* | | |For example, if NSAIDW<x> is 3 and the corresponding nsaid_wr_en[3] bit is set HIGH then TZC-400 permits the Non-secure write access to progress.
* @var TZC_T::REGION_BASE_LOW_1
* Offset: 0x120 Controls the base address bits[31:12] of Region <n>.
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:12] |base_address_low_n_|Controls the base address bits[31:12] of Region <n> For Region 0, this field is read-only The TZC-400 sets the base address of Region 0 to 0x0 The TZC-400 only permits a region to start at a 4KB aligned address and address bits[11:0] are zeros.
* @var TZC_T::REGION_BASE_HIGH_1
* Offset: 0x124 Reserved
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* @var TZC_T::REGION_TOP_LOW_1
* Offset: 0x128 Controls the region top address bits[31:12] of Region <n>.
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:12] |top_address_low_n_|Controls the region top address bits[31:12] of region <n> This address points to the start of the next 4KB aligned address immediately outside the region.
* @var TZC_T::REGION_TOP_HIGH_1
* Offset: 0x12C Reserved
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* @var TZC_T::REGION_ATTRIBUTES_1
* Offset: 0x130 Controls the permissions and target filter region enables.
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[3:0] |filter_en |Independent region enable for each filter unit Each bit is associated with a filter unit Set these bits as follows: Bit 0 For Filter 0 Bit 1 For Filter 1 Bit 2 For Filter 2 Bit 3 For Filter 3. When set HIGH, it enables the use of the current region programming for the associated filter For Region 0, all bits are set HIGH and cannot be modified.
* |[30] |s_rd_en |Secure global read enable This control bit defines the permissions for the Secure reads in the region Set this bit as follows: 0 Secure read to the region is not permitted 1 Permits Secure read to the region.
* |[31] |s_wr_en |Secure global write enable This control bit defines the permissions for the Secure writes in the region Set this bit as follows: 0 Secure write to the region is not permitted 1 Permits Secure write to the region.
* @var TZC_T::REGION_ID_ACCESS_1
* Offset: 0x134 Controls the Non-secure access based on the NSAID inputs.
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |nsaid_rd_en|NSAID read enables
* | | |This enables NSAID inputs to define Non-secure read access permission Each bit of the nsaid_rd_en register field is associated with a value on the NSAIDR<x> signal as follows: Bit 0 Associated with NSAIDR<x> = 0
* | | |Bit 1 Associated with NSAIDR<x> = 1
* | | |Bit 2 Associated with NSAIDR<x> = 2
* | | |Bit 15 Associated with NSAIDR<x> = 15
* | | |<x> is the filter unit number
* | | |When any bit in this field is set HIGH, TZC-400 permits Non-secure read access to any access with the associated NSAIDR<x> value
* | | |For example, if NSAIDR<x> is 3 and the corresponding nsaid_rd_en[3] bit is set HIGH then TZC-400 permits the Non-secure read access to progress.
* |[31:16] |nsaid_wr_en|NSAID write enables
* | | |This enables NSAID inputs to define Non-secure write access permission Each bit of the nsaid_wr_en register field is associated with a value on the NSAIDW<x> signal as follows: Bit 16 Associated with NSAIDW<x> = 0
* | | |Bit 17 Associated with NSAIDW<x> = 1
* | | |Bit 18 Associated with NSAIDW<x> = 2
* | | |Bit 31 Associated with NSAIDW<x> = 15
* | | |<x> is the filter unit number
* | | |When any bit in this field is set to 1, TZC-400 permits Non-secure write access to any access with the associated NSAIDW<x> value
* | | |For example, if NSAIDW<x> is 3 and the corresponding nsaid_wr_en[3] bit is set HIGH then TZC-400 permits the Non-secure write access to progress.
* @var TZC_T::REGION_BASE_LOW_2
* Offset: 0x140 Controls the base address bits[31:12] of Region <n>.
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:12] |base_address_low_n_|Controls the base address bits[31:12] of Region <n> For Region 0, this field is read-only The TZC-400 sets the base address of Region 0 to 0x0 The TZC-400 only permits a region to start at a 4KB aligned address and address bits[11:0] are zeros.
* @var TZC_T::REGION_BASE_HIGH_2
* Offset: 0x144 Reserved
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* @var TZC_T::REGION_TOP_LOW_2
* Offset: 0x148 Controls the region top address bits[31:12] of Region <n>.
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:12] |top_address_low_n_|Controls the region top address bits[31:12] of region <n> This address points to the start of the next 4KB aligned address immediately outside the region.
* @var TZC_T::REGION_TOP_HIGH_2
* Offset: 0x14C Reserved
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* @var TZC_T::REGION_ATTRIBUTES_2
* Offset: 0x150 Controls the permissions and target filter region enables.
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[3:0] |filter_en |Independent region enable for each filter unit Each bit is associated with a filter unit Set these bits as follows: Bit 0 For Filter 0 Bit 1 For Filter 1 Bit 2 For Filter 2 Bit 3 For Filter 3. When set HIGH, it enables the use of the current region programming for the associated filter For Region 0, all bits are set HIGH and cannot be modified.
* |[30] |s_rd_en |Secure global read enable This control bit defines the permissions for the Secure reads in the region Set this bit as follows: 0 Secure read to the region is not permitted 1 Permits Secure read to the region.
* |[31] |s_wr_en |Secure global write enable This control bit defines the permissions for the Secure writes in the region Set this bit as follows: 0 Secure write to the region is not permitted 1 Permits Secure write to the region.
* @var TZC_T::REGION_ID_ACCESS_2
* Offset: 0x154 Controls the Non-secure access based on the NSAID inputs.
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |nsaid_rd_en|NSAID read enables
* | | |This enables NSAID inputs to define Non-secure read access permission Each bit of the nsaid_rd_en register field is associated with a value on the NSAIDR<x> signal as follows: Bit 0 Associated with NSAIDR<x> = 0
* | | |Bit 1 Associated with NSAIDR<x> = 1
* | | |Bit 2 Associated with NSAIDR<x> = 2
* | | |Bit 15 Associated with NSAIDR<x> = 15
* | | |<x> is the filter unit number
* | | |When any bit in this field is set HIGH, TZC-400 permits Non-secure read access to any access with the associated NSAIDR<x> value
* | | |For example, if NSAIDR<x> is 3 and the corresponding nsaid_rd_en[3] bit is set HIGH then TZC-400 permits the Non-secure read access to progress.
* |[31:16] |nsaid_wr_en|NSAID write enables
* | | |This enables NSAID inputs to define Non-secure write access permission Each bit of the nsaid_wr_en register field is associated with a value on the NSAIDW<x> signal as follows: Bit 16 Associated with NSAIDW<x> = 0
* | | |Bit 17 Associated with NSAIDW<x> = 1
* | | |Bit 18 Associated with NSAIDW<x> = 2
* | | |Bit 31 Associated with NSAIDW<x> = 15
* | | |<x> is the filter unit number
* | | |When any bit in this field is set to 1, TZC-400 permits Non-secure write access to any access with the associated NSAIDW<x> value
* | | |For example, if NSAIDW<x> is 3 and the corresponding nsaid_wr_en[3] bit is set HIGH then TZC-400 permits the Non-secure write access to progress.
* @var TZC_T::REGION_BASE_LOW_3
* Offset: 0x160 Controls the base address bits[31:12] of Region <n>.
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:12] |base_address_low_n_|Controls the base address bits[31:12] of Region <n> For Region 0, this field is read-only The TZC-400 sets the base address of Region 0 to 0x0 The TZC-400 only permits a region to start at a 4KB aligned address and address bits[11:0] are zeros.
* @var TZC_T::REGION_BASE_HIGH_3
* Offset: 0x164 Reserved
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* @var TZC_T::REGION_TOP_LOW_3
* Offset: 0x168 Controls the region top address bits[31:12] of Region <n>.
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:12] |top_address_low_n_|Controls the region top address bits[31:12] of region <n> This address points to the start of the next 4KB aligned address immediately outside the region.
* @var TZC_T::REGION_TOP_HIGH_3
* Offset: 0x16C Reserved
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* @var TZC_T::REGION_ATTRIBUTES_3
* Offset: 0x170 Controls the permissions and target filter region enables.
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[3:0] |filter_en |Independent region enable for each filter unit Each bit is associated with a filter unit Set these bits as follows: Bit 0 For Filter 0 Bit 1 For Filter 1 Bit 2 For Filter 2 Bit 3 For Filter 3. When set HIGH, it enables the use of the current region programming for the associated filter For Region 0, all bits are set HIGH and cannot be modified.
* |[30] |s_rd_en |Secure global read enable This control bit defines the permissions for the Secure reads in the region Set this bit as follows: 0 Secure read to the region is not permitted 1 Permits Secure read to the region.
* |[31] |s_wr_en |Secure global write enable This control bit defines the permissions for the Secure writes in the region Set this bit as follows: 0 Secure write to the region is not permitted 1 Permits Secure write to the region.
* @var TZC_T::REGION_ID_ACCESS_3
* Offset: 0x174 Controls the Non-secure access based on the NSAID inputs.
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |nsaid_rd_en|NSAID read enables
* | | |This enables NSAID inputs to define Non-secure read access permission Each bit of the nsaid_rd_en register field is associated with a value on the NSAIDR<x> signal as follows: Bit 0 Associated with NSAIDR<x> = 0
* | | |Bit 1 Associated with NSAIDR<x> = 1
* | | |Bit 2 Associated with NSAIDR<x> = 2
* | | |Bit 15 Associated with NSAIDR<x> = 15
* | | |<x> is the filter unit number
* | | |When any bit in this field is set HIGH, TZC-400 permits Non-secure read access to any access with the associated NSAIDR<x> value
* | | |For example, if NSAIDR<x> is 3 and the corresponding nsaid_rd_en[3] bit is set HIGH then TZC-400 permits the Non-secure read access to progress.
* |[31:16] |nsaid_wr_en|NSAID write enables
* | | |This enables NSAID inputs to define Non-secure write access permission Each bit of the nsaid_wr_en register field is associated with a value on the NSAIDW<x> signal as follows: Bit 16 Associated with NSAIDW<x> = 0
* | | |Bit 17 Associated with NSAIDW<x> = 1
* | | |Bit 18 Associated with NSAIDW<x> = 2
* | | |Bit 31 Associated with NSAIDW<x> = 15
* | | |<x> is the filter unit number
* | | |When any bit in this field is set to 1, TZC-400 permits Non-secure write access to any access with the associated NSAIDW<x> value
* | | |For example, if NSAIDW<x> is 3 and the corresponding nsaid_wr_en[3] bit is set HIGH then TZC-400 permits the Non-secure write access to progress.
* @var TZC_T::REGION_BASE_LOW_4
* Offset: 0x180 Controls the base address bits[31:12] of Region <n>.
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:12] |base_address_low_n_|Controls the base address bits[31:12] of Region <n> For Region 0, this field is read-only The TZC-400 sets the base address of Region 0 to 0x0 The TZC-400 only permits a region to start at a 4KB aligned address and address bits[11:0] are zeros.
* @var TZC_T::REGION_BASE_HIGH_4
* Offset: 0x184 Reserved
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* @var TZC_T::REGION_TOP_LOW_4
* Offset: 0x188 Controls the region top address bits[31:12] of Region <n>.
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:12] |top_address_low_n_|Controls the region top address bits[31:12] of region <n> This address points to the start of the next 4KB aligned address immediately outside the region.
* @var TZC_T::REGION_TOP_HIGH_4
* Offset: 0x18C Reserved
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* @var TZC_T::REGION_ATTRIBUTES_4
* Offset: 0x190 Controls the permissions and target filter region enables.
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[3:0] |filter_en |Independent region enable for each filter unit Each bit is associated with a filter unit Set these bits as follows: Bit 0 For Filter 0 Bit 1 For Filter 1 Bit 2 For Filter 2 Bit 3 For Filter 3. When set HIGH, it enables the use of the current region programming for the associated filter For Region 0, all bits are set HIGH and cannot be modified.
* |[30] |s_rd_en |Secure global read enable This control bit defines the permissions for the Secure reads in the region Set this bit as follows: 0 Secure read to the region is not permitted 1 Permits Secure read to the region.
* |[31] |s_wr_en |Secure global write enable This control bit defines the permissions for the Secure writes in the region Set this bit as follows: 0 Secure write to the region is not permitted 1 Permits Secure write to the region.
* @var TZC_T::REGION_ID_ACCESS_4
* Offset: 0x194 Controls the Non-secure access based on the NSAID inputs.
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |nsaid_rd_en|NSAID read enables
* | | |This enables NSAID inputs to define Non-secure read access permission Each bit of the nsaid_rd_en register field is associated with a value on the NSAIDR<x> signal as follows: Bit 0 Associated with NSAIDR<x> = 0
* | | |Bit 1 Associated with NSAIDR<x> = 1
* | | |Bit 2 Associated with NSAIDR<x> = 2
* | | |Bit 15 Associated with NSAIDR<x> = 15
* | | |<x> is the filter unit number
* | | |When any bit in this field is set HIGH, TZC-400 permits Non-secure read access to any access with the associated NSAIDR<x> value
* | | |For example, if NSAIDR<x> is 3 and the corresponding nsaid_rd_en[3] bit is set HIGH then TZC-400 permits the Non-secure read access to progress.
* |[31:16] |nsaid_wr_en|NSAID write enables
* | | |This enables NSAID inputs to define Non-secure write access permission Each bit of the nsaid_wr_en register field is associated with a value on the NSAIDW<x> signal as follows: Bit 16 Associated with NSAIDW<x> = 0
* | | |Bit 17 Associated with NSAIDW<x> = 1
* | | |Bit 18 Associated with NSAIDW<x> = 2
* | | |Bit 31 Associated with NSAIDW<x> = 15
* | | |<x> is the filter unit number
* | | |When any bit in this field is set to 1, TZC-400 permits Non-secure write access to any access with the associated NSAIDW<x> value
* | | |For example, if NSAIDW<x> is 3 and the corresponding nsaid_wr_en[3] bit is set HIGH then TZC-400 permits the Non-secure write access to progress.
* @var TZC_T::REGION_BASE_LOW_5
* Offset: 0x1A0 Controls the base address bits[31:12] of Region <n>.
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:12] |base_address_low_n_|Controls the base address bits[31:12] of Region <n> For Region 0, this field is read-only The TZC-400 sets the base address of Region 0 to 0x0 The TZC-400 only permits a region to start at a 4KB aligned address and address bits[11:0] are zeros.
* @var TZC_T::REGION_BASE_HIGH_5
* Offset: 0x1A4 Reserved
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* @var TZC_T::REGION_TOP_LOW_5
* Offset: 0x1A8 Controls the region top address bits[31:12] of Region <n>.
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:12] |top_address_low_n_|Controls the region top address bits[31:12] of region <n> This address points to the start of the next 4KB aligned address immediately outside the region.
* @var TZC_T::REGION_TOP_HIGH_5
* Offset: 0x1AC Reserved
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* @var TZC_T::REGION_ATTRIBUTES_5
* Offset: 0x1B0 Controls the permissions and target filter region enables.
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[3:0] |filter_en |Independent region enable for each filter unit Each bit is associated with a filter unit Set these bits as follows: Bit 0 For Filter 0 Bit 1 For Filter 1 Bit 2 For Filter 2 Bit 3 For Filter 3. When set HIGH, it enables the use of the current region programming for the associated filter For Region 0, all bits are set HIGH and cannot be modified.
* |[30] |s_rd_en |Secure global read enable This control bit defines the permissions for the Secure reads in the region Set this bit as follows: 0 Secure read to the region is not permitted 1 Permits Secure read to the region.
* |[31] |s_wr_en |Secure global write enable This control bit defines the permissions for the Secure writes in the region Set this bit as follows: 0 Secure write to the region is not permitted 1 Permits Secure write to the region.
* @var TZC_T::REGION_ID_ACCESS_5
* Offset: 0x1B4 Controls the Non-secure access based on the NSAID inputs.
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |nsaid_rd_en|NSAID read enables
* | | |This enables NSAID inputs to define Non-secure read access permission Each bit of the nsaid_rd_en register field is associated with a value on the NSAIDR<x> signal as follows: Bit 0 Associated with NSAIDR<x> = 0
* | | |Bit 1 Associated with NSAIDR<x> = 1
* | | |Bit 2 Associated with NSAIDR<x> = 2
* | | |Bit 15 Associated with NSAIDR<x> = 15
* | | |<x> is the filter unit number
* | | |When any bit in this field is set HIGH, TZC-400 permits Non-secure read access to any access with the associated NSAIDR<x> value
* | | |For example, if NSAIDR<x> is 3 and the corresponding nsaid_rd_en[3] bit is set HIGH then TZC-400 permits the Non-secure read access to progress.
* |[31:16] |nsaid_wr_en|NSAID write enables
* | | |This enables NSAID inputs to define Non-secure write access permission Each bit of the nsaid_wr_en register field is associated with a value on the NSAIDW<x> signal as follows: Bit 16 Associated with NSAIDW<x> = 0
* | | |Bit 17 Associated with NSAIDW<x> = 1
* | | |Bit 18 Associated with NSAIDW<x> = 2
* | | |Bit 31 Associated with NSAIDW<x> = 15
* | | |<x> is the filter unit number
* | | |When any bit in this field is set to 1, TZC-400 permits Non-secure write access to any access with the associated NSAIDW<x> value
* | | |For example, if NSAIDW<x> is 3 and the corresponding nsaid_wr_en[3] bit is set HIGH then TZC-400 permits the Non-secure write access to progress.
* @var TZC_T::REGION_BASE_LOW_6
* Offset: 0x1C0 Controls the base address bits[31:12] of Region <n>.
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:12] |base_address_low_n_|Controls the base address bits[31:12] of Region <n> For Region 0, this field is read-only The TZC-400 sets the base address of Region 0 to 0x0 The TZC-400 only permits a region to start at a 4KB aligned address and address bits[11:0] are zeros.
* @var TZC_T::REGION_BASE_HIGH_6
* Offset: 0x1C4 Reserved
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* @var TZC_T::REGION_TOP_LOW_6
* Offset: 0x1C8 Controls the region top address bits[31:12] of Region <n>.
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:12] |top_address_low_n_|Controls the region top address bits[31:12] of region <n> This address points to the start of the next 4KB aligned address immediately outside the region.
* @var TZC_T::REGION_TOP_HIGH_6
* Offset: 0x1CC Reserved
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* @var TZC_T::REGION_ATTRIBUTES_6
* Offset: 0x1D0 Controls the permissions and target filter region enables.
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[3:0] |filter_en |Independent region enable for each filter unit Each bit is associated with a filter unit Set these bits as follows: Bit 0 For Filter 0 Bit 1 For Filter 1 Bit 2 For Filter 2 Bit 3 For Filter 3. When set HIGH, it enables the use of the current region programming for the associated filter For Region 0, all bits are set HIGH and cannot be modified.
* |[30] |s_rd_en |Secure global read enable This control bit defines the permissions for the Secure reads in the region Set this bit as follows: 0 Secure read to the region is not permitted 1 Permits Secure read to the region.
* |[31] |s_wr_en |Secure global write enable This control bit defines the permissions for the Secure writes in the region Set this bit as follows: 0 Secure write to the region is not permitted 1 Permits Secure write to the region.
* @var TZC_T::REGION_ID_ACCESS_6
* Offset: 0x1D4 Controls the Non-secure access based on the NSAID inputs.
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |nsaid_rd_en|NSAID read enables
* | | |This enables NSAID inputs to define Non-secure read access permission Each bit of the nsaid_rd_en register field is associated with a value on the NSAIDR<x> signal as follows: Bit 0 Associated with NSAIDR<x> = 0
* | | |Bit 1 Associated with NSAIDR<x> = 1
* | | |Bit 2 Associated with NSAIDR<x> = 2
* | | |Bit 15 Associated with NSAIDR<x> = 15
* | | |<x> is the filter unit number
* | | |When any bit in this field is set HIGH, TZC-400 permits Non-secure read access to any access with the associated NSAIDR<x> value
* | | |For example, if NSAIDR<x> is 3 and the corresponding nsaid_rd_en[3] bit is set HIGH then TZC-400 permits the Non-secure read access to progress.
* |[31:16] |nsaid_wr_en|NSAID write enables
* | | |This enables NSAID inputs to define Non-secure write access permission Each bit of the nsaid_wr_en register field is associated with a value on the NSAIDW<x> signal as follows: Bit 16 Associated with NSAIDW<x> = 0
* | | |Bit 17 Associated with NSAIDW<x> = 1
* | | |Bit 18 Associated with NSAIDW<x> = 2
* | | |Bit 31 Associated with NSAIDW<x> = 15
* | | |<x> is the filter unit number
* | | |When any bit in this field is set to 1, TZC-400 permits Non-secure write access to any access with the associated NSAIDW<x> value
* | | |For example, if NSAIDW<x> is 3 and the corresponding nsaid_wr_en[3] bit is set HIGH then TZC-400 permits the Non-secure write access to progress.
* @var TZC_T::REGION_BASE_LOW_7
* Offset: 0x1E0 Controls the base address bits[31:12] of Region <n>.
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:12] |base_address_low_n_|Controls the base address bits[31:12] of Region <n> For Region 0, this field is read-only The TZC-400 sets the base address of Region 0 to 0x0 The TZC-400 only permits a region to start at a 4KB aligned address and address bits[11:0] are zeros.
* @var TZC_T::REGION_BASE_HIGH_7
* Offset: 0x1E4 Reserved
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* @var TZC_T::REGION_TOP_LOW_7
* Offset: 0x1E8 Controls the region top address bits[31:12] of Region <n>.
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:12] |top_address_low_n_|Controls the region top address bits[31:12] of region <n> This address points to the start of the next 4KB aligned address immediately outside the region.
* @var TZC_T::REGION_TOP_HIGH_7
* Offset: 0x1EC Reserved
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* @var TZC_T::REGION_ATTRIBUTES_7
* Offset: 0x1F0 Controls the permissions and target filter region enables.
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[3:0] |filter_en |Independent region enable for each filter unit Each bit is associated with a filter unit Set these bits as follows: Bit 0 For Filter 0 Bit 1 For Filter 1 Bit 2 For Filter 2 Bit 3 For Filter 3. When set HIGH, it enables the use of the current region programming for the associated filter For Region 0, all bits are set HIGH and cannot be modified.
* |[30] |s_rd_en |Secure global read enable This control bit defines the permissions for the Secure reads in the region Set this bit as follows: 0 Secure read to the region is not permitted 1 Permits Secure read to the region.
* |[31] |s_wr_en |Secure global write enable This control bit defines the permissions for the Secure writes in the region Set this bit as follows: 0 Secure write to the region is not permitted 1 Permits Secure write to the region.
* @var TZC_T::REGION_ID_ACCESS_7
* Offset: 0x1F4 Controls the Non-secure access based on the NSAID inputs.
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |nsaid_rd_en|NSAID read enables
* | | |This enables NSAID inputs to define Non-secure read access permission Each bit of the nsaid_rd_en register field is associated with a value on the NSAIDR<x> signal as follows: Bit 0 Associated with NSAIDR<x> = 0
* | | |Bit 1 Associated with NSAIDR<x> = 1
* | | |Bit 2 Associated with NSAIDR<x> = 2
* | | |Bit 15 Associated with NSAIDR<x> = 15
* | | |<x> is the filter unit number
* | | |When any bit in this field is set HIGH, TZC-400 permits Non-secure read access to any access with the associated NSAIDR<x> value
* | | |For example, if NSAIDR<x> is 3 and the corresponding nsaid_rd_en[3] bit is set HIGH then TZC-400 permits the Non-secure read access to progress.
* |[31:16] |nsaid_wr_en|NSAID write enables
* | | |This enables NSAID inputs to define Non-secure write access permission Each bit of the nsaid_wr_en register field is associated with a value on the NSAIDW<x> signal as follows: Bit 16 Associated with NSAIDW<x> = 0
* | | |Bit 17 Associated with NSAIDW<x> = 1
* | | |Bit 18 Associated with NSAIDW<x> = 2
* | | |Bit 31 Associated with NSAIDW<x> = 15
* | | |<x> is the filter unit number
* | | |When any bit in this field is set to 1, TZC-400 permits Non-secure write access to any access with the associated NSAIDW<x> value
* | | |For example, if NSAIDW<x> is 3 and the corresponding nsaid_wr_en[3] bit is set HIGH then TZC-400 permits the Non-secure write access to progress.
* @var TZC_T::REGION_BASE_LOW_8
* Offset: 0x200 Controls the base address bits[31:12] of Region <n>.
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:12] |base_address_low_n_|Controls the base address bits[31:12] of Region <n> For Region 0, this field is read-only The TZC-400 sets the base address of Region 0 to 0x0 The TZC-400 only permits a region to start at a 4KB aligned address and address bits[11:0] are zeros.
* @var TZC_T::REGION_BASE_HIGH_8
* Offset: 0x204 Reserved
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* @var TZC_T::REGION_TOP_LOW_8
* Offset: 0x208 Controls the region top address bits[31:12] of Region <n>.
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:12] |top_address_low_n_|Controls the region top address bits[31:12] of region <n> This address points to the start of the next 4KB aligned address immediately outside the region.
* @var TZC_T::REGION_TOP_HIGH_8
* Offset: 0x20C Reserved
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* @var TZC_T::REGION_ATTRIBUTES_8
* Offset: 0x210 Controls the permissions and target filter region enables.
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[3:0] |filter_en |Independent region enable for each filter unit Each bit is associated with a filter unit Set these bits as follows: Bit 0 For Filter 0 Bit 1 For Filter 1 Bit 2 For Filter 2 Bit 3 For Filter 3. When set HIGH, it enables the use of the current region programming for the associated filter For Region 0, all bits are set HIGH and cannot be modified.
* |[30] |s_rd_en |Secure global read enable This control bit defines the permissions for the Secure reads in the region Set this bit as follows: 0 Secure read to the region is not permitted 1 Permits Secure read to the region.
* |[31] |s_wr_en |Secure global write enable This control bit defines the permissions for the Secure writes in the region Set this bit as follows: 0 Secure write to the region is not permitted 1 Permits Secure write to the region.
* @var TZC_T::REGION_ID_ACCESS_8
* Offset: 0x214 Controls the Non-secure access based on the NSAID inputs.
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |nsaid_rd_en|NSAID read enables
* | | |This enables NSAID inputs to define Non-secure read access permission Each bit of the nsaid_rd_en register field is associated with a value on the NSAIDR<x> signal as follows: Bit 0 Associated with NSAIDR<x> = 0
* | | |Bit 1 Associated with NSAIDR<x> = 1
* | | |Bit 2 Associated with NSAIDR<x> = 2
* | | |Bit 15 Associated with NSAIDR<x> = 15
* | | |<x> is the filter unit number
* | | |When any bit in this field is set HIGH, TZC-400 permits Non-secure read access to any access with the associated NSAIDR<x> value
* | | |For example, if NSAIDR<x> is 3 and the corresponding nsaid_rd_en[3] bit is set HIGH then TZC-400 permits the Non-secure read access to progress.
* |[31:16] |nsaid_wr_en|NSAID write enables
* | | |This enables NSAID inputs to define Non-secure write access permission Each bit of the nsaid_wr_en register field is associated with a value on the NSAIDW<x> signal as follows: Bit 16 Associated with NSAIDW<x> = 0
* | | |Bit 17 Associated with NSAIDW<x> = 1
* | | |Bit 18 Associated with NSAIDW<x> = 2
* | | |Bit 31 Associated with NSAIDW<x> = 15
* | | |<x> is the filter unit number
* | | |When any bit in this field is set to 1, TZC-400 permits Non-secure write access to any access with the associated NSAIDW<x> value
* | | |For example, if NSAIDW<x> is 3 and the corresponding nsaid_wr_en[3] bit is set HIGH then TZC-400 permits the Non-secure write access to progress.
* @var TZC_T::PID4
* Offset: 0xFD0 Provides the following information about the peripheral configuration u2022 4KB_count. u2022 Jep106_c_code.
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[3:0] |jep106_c_code|The JEP106 continuation code value represents how many 0x7F continuation characters occur in the manufacturer identity code These bits read back as 0x4 For information on the JEP106 standard, see the Additional reading section.
* |[7:4] |4KB_count |The number of 4KB address blocks required to access the registers, expressed in powers of 2 These bits read back as 0x0 This means that the TZC-400 occupies a single 4KB address block.
* @var TZC_T::PID0
* Offset: 0xFE0 The PID0 register provides the following information about the peripheral configuration: u2022 part_number_0.
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |part_number_0|These bits read back as 0x60
* @var TZC_T::PID1
* Offset: 0xFE4 The PID1 register provides the following information about the peripheral configuration: u2022 part_number_1. u2022 Jep106_id_3_0.
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[3:0] |part_number_1|These bits read back as 0x4.
* |[7:4] |jep106_id_3_0|JEP106 identity code [3:0] See the JEP106, Standard Manufacturer Identification Code These bits read back as 0xB because ARM is the peripheral designer.
* @var TZC_T::PID2
* Offset: 0xFE8 The PID2 register provides the following information about the peripheral configuration: u2022 Jep106_id_6_4. u2022 Revision number. u2022 JEDEC use flag.
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[2:0] |jep106_id_6_4|JEP106 identity code [6:4] See the JEP106, Standard Manufacturer Identification Code These bits read back as 0b011 because ARM is the peripheral designer.
* |[3] |jedec_used|This indicates that the TZC-400 uses a manufacturer identity code that was allocated by JEDEC according to JEP106 This bit always reads back as 0x1.
* |[7:4] |revision |Identifies the revision of the TZC-400 For revision r0p1, this field is set to 0x2.
* @var TZC_T::PID3
* Offset: 0xFEC The PID3 register provides the following information about the peripheral configuration: u2022 Mod Number. u2022 RevAnd.
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[3:0] |mod_number|This is set to 0x0.
* |[7:4] |RevAnd |The top-level RTL provides a 4-bit input, USERPID3REVAND, that is normally tied LOW and provides a read value of 0x0 When silicon is available, and if metal fixes are required, the manufacturer can modify the tie-offs to indicate a revision of the silicon.
* @var TZC_T::CID0
* Offset: 0xFF0 This is one of four 8-bit registers that together hold a 32-bit component ID value.
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |comp_id_0 |These bits read back as 0x0D
* @var TZC_T::CID1
* Offset: 0xFF4 This is one of four 8-bit registers, that together hold a 32-bit component ID value.
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |comp_id_0 |These bits read back as 0xF0
* @var TZC_T::CID2
* Offset: 0xFF8 This is one of four 8-bit registers, that together hold a 32-bit component ID value.
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |comp_id_2 |These bits read back as 0x05
* @var TZC_T::CID3
* Offset: 0xFFC This is one of four 8-bit registers that together hold a 32-bit component ID value.
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |comp_id_3 |These bits read back as 0xB1
*/
__I uint32_t BUILD_CONFIG; /*!< [0x0000] Provides information about the configuration of the TZC-400. */
__IO uint32_t ACTION; /*!< [0x0004] Controls the interrupt and bus response signaling behavior of the TZC-400 when region permission failures occur. */
__IO uint32_t GATE_KEEPER; /*!< [0x0008] Provides control and status for the gate keeper in each filter unit implemented */
__IO uint32_t SPECULATION_CTRL; /*!< [0x000c] Controls the read access speculation and write access speculation. */
__I uint32_t INT_STATUS; /*!< [0x0010] Contains the status of the interrupt signal, TZCINT, that reports access security violations or region overlap errors. */
__O uint32_t INT_CLEAR; /*!< [0x0014] Clears the interrupt. */
__I uint32_t RESERVE0[2];
FAIL_STS_T FAIL[3]; /*!< [0x0020] Failed regions */
__I uint32_t RESERVE1[44];
/*!< [0x0100] This register is read-only and is hard-wired to all zeros. */
REGION_T REGION[9]; /*!< [0x0100] All structure regions in TZC. */
__I uint32_t RESERVE10[876];
__I uint32_t PID4; /*!< [0x0fd0] Provides the following information about the peripheral configuration u2022 4KB_count. u2022 Jep106_c_code. */
__I uint32_t RESERVE11[3];
__I uint32_t PID0; /*!< [0x0fe0] The PID0 register provides the following information about the peripheral configuration: u2022 part_number_0. */
__I uint32_t PID1; /*!< [0x0fe4] The PID1 register provides the following information about the peripheral configuration: u2022 part_number_1. u2022 Jep106_id_3_0. */
__I uint32_t PID2; /*!< [0x0fe8] The PID2 register provides the following information about the peripheral configuration: u2022 Jep106_id_6_4. u2022 Revision number. u2022 JEDEC use flag. */
__I uint32_t PID3; /*!< [0x0fec] The PID3 register provides the following information about the peripheral configuration: u2022 Mod Number. u2022 RevAnd. */
__I uint32_t CID0; /*!< [0x0ff0] This is one of four 8-bit registers that together hold a 32-bit component ID value. */
__I uint32_t CID1; /*!< [0x0ff4] This is one of four 8-bit registers, that together hold a 32-bit component ID value. */
__I uint32_t CID2; /*!< [0x0ff8] This is one of four 8-bit registers, that together hold a 32-bit component ID value. */
__I uint32_t CID3; /*!< [0x0ffc] This is one of four 8-bit registers that together hold a 32-bit component ID value. */
} TZC_T;
/**
@addtogroup TZC_CONST TZC Bit Field Definition
Constant Definitions for TZC Controller
@{ */
#define TZC_BUILD_CONFIG_no_of_regions_Pos (0) /*!< TZC_T::BUILD_CONFIG: no_of_regions Position*/
#define TZC_BUILD_CONFIG_no_of_regions_Msk (0x1ful << TZC_BUILD_CONFIG_no_of_regions_Pos) /*!< TZC_T::BUILD_CONFIG: no_of_regions Mask*/
#define TZC_BUILD_CONFIG_address_width_Pos (8) /*!< TZC_T::BUILD_CONFIG: address_width Position*/
#define TZC_BUILD_CONFIG_address_width_Msk (0x3ful << TZC_BUILD_CONFIG_address_width_Pos) /*!< TZC_T::BUILD_CONFIG: address_width Mask*/
#define TZC_BUILD_CONFIG_no_of_filters_Pos (24) /*!< TZC_T::BUILD_CONFIG: no_of_filters Position*/
#define TZC_BUILD_CONFIG_no_of_filters_Msk (0x3ul << TZC_BUILD_CONFIG_no_of_filters_Pos) /*!< TZC_T::BUILD_CONFIG: no_of_filters Mask*/
#define TZC_ACTION_reaction_value_Pos (0) /*!< TZC_T::ACTION: reaction_value Position*/
#define TZC_ACTION_reaction_value_Msk (0x3ul << TZC_ACTION_reaction_value_Pos) /*!< TZC_T::ACTION: reaction_value Mask */
#define TZC_GATE_KEEPER_open_request_Pos (0) /*!< TZC_T::GATE_KEEPER: open_request Position*/
#define TZC_GATE_KEEPER_open_request_Msk (0xful << TZC_GATE_KEEPER_open_request_Pos) /*!< TZC_T::GATE_KEEPER: open_request Mask */
#define TZC_GATE_KEEPER_open_status_Pos (16) /*!< TZC_T::GATE_KEEPER: open_status Position*/
#define TZC_GATE_KEEPER_open_status_Msk (0xful << TZC_GATE_KEEPER_open_status_Pos) /*!< TZC_T::GATE_KEEPER: open_status Mask */
#define TZC_SPECULATION_CTRL_read_spec_disable_Pos (0) /*!< TZC_T::SPECULATION_CTRL: read_spec_disable Position*/
#define TZC_SPECULATION_CTRL_read_spec_disable_Msk (0x1ul << TZC_SPECULATION_CTRL_read_spec_disable_Pos) /*!< TZC_T::SPECULATION_CTRL: read_spec_disable Mask*/
#define TZC_SPECULATION_CTRL_write_spec_disable_Pos (1) /*!< TZC_T::SPECULATION_CTRL: write_spec_disable Position*/
#define TZC_SPECULATION_CTRL_write_spec_disable_Msk (0x1ul << TZC_SPECULATION_CTRL_write_spec_disable_Pos) /*!< TZC_T::SPECULATION_CTRL: write_spec_disable Mask*/
#define TZC_INT_STATUS_status_Pos (0) /*!< TZC_T::INT_STATUS: status Position */
#define TZC_INT_STATUS_status_Msk (0xful << TZC_INT_STATUS_status_Pos) /*!< TZC_T::INT_STATUS: status Mask */
#define TZC_INT_STATUS_overrun_Pos (8) /*!< TZC_T::INT_STATUS: overrun Position */
#define TZC_INT_STATUS_overrun_Msk (0xful << TZC_INT_STATUS_overrun_Pos) /*!< TZC_T::INT_STATUS: overrun Mask */
#define TZC_INT_STATUS_overlap_Pos (16) /*!< TZC_T::INT_STATUS: overlap Position */
#define TZC_INT_STATUS_overlap_Msk (0xful << TZC_INT_STATUS_overlap_Pos) /*!< TZC_T::INT_STATUS: overlap Mask */
#define TZC_INT_CLEAR_clear_Pos (0) /*!< TZC_T::INT_CLEAR: clear Position */
#define TZC_INT_CLEAR_clear_Msk (0xful << TZC_INT_CLEAR_clear_Pos) /*!< TZC_T::INT_CLEAR: clear Mask */
#define TZC_FAIL_ADDRESS_LOW_addr_status_low_Pos (0) /*!< TZC_T::FAIL_ADDRESS_LOW: addr_status_low Position*/
#define TZC_FAIL_ADDRESS_LOW_addr_status_low_Msk (0xfffffffful << TZC_FAIL_ADDRESS_LOW_addr_status_low_Pos) /*!< TZC_T::FAIL_ADDRESS_LOW: addr_status_low Mask*/
#define TZC_FAIL_CONTROL_Privileged_Pos (20) /*!< TZC_T::FAIL_CONTROL: Privileged Position*/
#define TZC_FAIL_CONTROL_Privileged_Msk (0x1ul << TZC_FAIL_CONTROL_Privileged_Pos) /*!< TZC_T::FAIL_CONTROL: Privileged Mask*/
#define TZC_FAIL_CONTROL_Non_secure_Pos (21) /*!< TZC_T::FAIL_CONTROL: Non_secure Position*/
#define TZC_FAIL_CONTROL_Non_secure_Msk (0x1ul << TZC_FAIL_CONTROL_Non_secure_Pos) /*!< TZC_T::FAIL_CONTROL: Non_secure Mask*/
#define TZC_FAIL_CONTROL_Direction_Pos (24) /*!< TZC_T::FAIL_CONTROL: Direction Position*/
#define TZC_FAIL_CONTROL_Direction_Msk (0x1ul << TZC_FAIL_CONTROL_Direction_Pos) /*!< TZC_T::FAIL_CONTROL: Direction Mask */
#define TZC_FAIL_ID_id_Pos (0) /*!< TZC_T::FAIL_ID: id Position */
#define TZC_FAIL_ID_id_Msk (0x3ful << TZC_FAIL_ID_id_Pos) /*!< TZC_T::FAIL_ID: id Mask */
#define TZC_FAIL_ID_vnet_Pos (24) /*!< TZC_T::FAIL_ID: vnet Position */
#define TZC_FAIL_ID_vnet_Msk (0xful << TZC_FAIL_ID_vnet_Pos) /*!< TZC_T::FAIL_ID: vnet Mask */
#define TZC_REGION_BASE_LOW_base_address_low_n_Pos (12) /*!< TZC_T::REGION_BASE_LOW: base_address_low_n_ Position*/
#define TZC_REGION_BASE_LOW_base_address_low_n_Msk (0xffffful << TZC_REGION_BASE_LOW_base_address_low_n_Pos) /*!< TZC_T::REGION_BASE_LOW: base_address_low_n_ Mask*/
#define TZC_REGION_TOP_LOW_top_address_low_n_Pos (12) /*!< TZC_T::REGION_TOP_LOW: top_address_low_n_ Position*/
#define TZC_REGION_TOP_LOW_top_address_low_n_Msk (0xffffful << TZC_REGION_TOP_LOW_top_address_low_n_Pos) /*!< TZC_T::REGION_TOP_LOW: top_address_low_n_ Mask*/
#define TZC_REGION_ATTRIBUTES_filter_en_Pos (0) /*!< TZC_T::REGION_ATTRIBUTES: filter_en Position*/
#define TZC_REGION_ATTRIBUTES_filter_en_Msk (0xful << TZC_REGION_ATTRIBUTES_filter_en_Pos) /*!< TZC_T::REGION_ATTRIBUTES: filter_en Mask*/
#define TZC_REGION_ATTRIBUTES_s_rd_en_Pos (30) /*!< TZC_T::REGION_ATTRIBUTES: s_rd_en Position*/
#define TZC_REGION_ATTRIBUTES_s_rd_en_Msk (0x1ul << TZC_REGION_ATTRIBUTES_s_rd_en_Pos) /*!< TZC_T::REGION_ATTRIBUTES: s_rd_en Mask*/
#define TZC_REGION_ATTRIBUTES_s_wr_en_Pos (31) /*!< TZC_T::REGION_ATTRIBUTES: s_wr_en Position*/
#define TZC_REGION_ATTRIBUTES_s_wr_en_Msk (0x1ul << TZC_REGION_ATTRIBUTES_s_wr_en_Pos) /*!< TZC_T::REGION_ATTRIBUTES: s_wr_en Mask*/
#define TZC_REGION_ID_ACCESS_nsaid_rd_en_Pos (0) /*!< TZC_T::REGION_ID_ACCESS: nsaid_rd_en Position*/
#define TZC_REGION_ID_ACCESS_nsaid_rd_en_Msk (0xfffful << TZC_REGION_ID_ACCESS_nsaid_rd_en_Pos) /*!< TZC_T::REGION_ID_ACCESS: nsaid_rd_en Mask*/
#define TZC_REGION_ID_ACCESS_nsaid_wr_en_Pos (16) /*!< TZC_T::REGION_ID_ACCESS: nsaid_wr_en Position*/
#define TZC_REGION_ID_ACCESS_nsaid_wr_en_Msk (0xfffful << TZC_REGION_ID_ACCESS_nsaid_wr_en_Pos) /*!< TZC_T::REGION_ID_ACCESS: nsaid_wr_en Mask*/
#define TZC_PID4_jep106_c_code_Pos (0) /*!< TZC_T::PID4: jep106_c_code Position */
#define TZC_PID4_jep106_c_code_Msk (0xful << TZC_PID4_jep106_c_code_Pos) /*!< TZC_T::PID4: jep106_c_code Mask */
#define TZC_PID4_4KB_count_Pos (4) /*!< TZC_T::PID4: 4KB_count Position */
#define TZC_PID4_4KB_count_Msk (0xful << TZC_PID4_4KB_count_Pos) /*!< TZC_T::PID4: 4KB_count Mask */
#define TZC_PID0_part_number_0_Pos (0) /*!< TZC_T::PID0: part_number_0 Position */
#define TZC_PID0_part_number_0_Msk (0xfful << TZC_PID0_part_number_0_Pos) /*!< TZC_T::PID0: part_number_0 Mask */
#define TZC_PID1_part_number_1_Pos (0) /*!< TZC_T::PID1: part_number_1 Position */
#define TZC_PID1_part_number_1_Msk (0xful << TZC_PID1_part_number_1_Pos) /*!< TZC_T::PID1: part_number_1 Mask */
#define TZC_PID1_jep106_id_3_0_Pos (4) /*!< TZC_T::PID1: jep106_id_3_0 Position */
#define TZC_PID1_jep106_id_3_0_Msk (0xful << TZC_PID1_jep106_id_3_0_Pos) /*!< TZC_T::PID1: jep106_id_3_0 Mask */
#define TZC_PID2_jep106_id_6_4_Pos (0) /*!< TZC_T::PID2: jep106_id_6_4 Position */
#define TZC_PID2_jep106_id_6_4_Msk (0x7ul << TZC_PID2_jep106_id_6_4_Pos) /*!< TZC_T::PID2: jep106_id_6_4 Mask */
#define TZC_PID2_jedec_used_Pos (3) /*!< TZC_T::PID2: jedec_used Position */
#define TZC_PID2_jedec_used_Msk (0x1ul << TZC_PID2_jedec_used_Pos) /*!< TZC_T::PID2: jedec_used Mask */
#define TZC_PID2_revision_Pos (4) /*!< TZC_T::PID2: revision Position */
#define TZC_PID2_revision_Msk (0xful << TZC_PID2_revision_Pos) /*!< TZC_T::PID2: revision Mask */
#define TZC_PID3_mod_number_Pos (0) /*!< TZC_T::PID3: mod_number Position */
#define TZC_PID3_mod_number_Msk (0xful << TZC_PID3_mod_number_Pos) /*!< TZC_T::PID3: mod_number Mask */
#define TZC_PID3_RevAnd_Pos (4) /*!< TZC_T::PID3: RevAnd Position */
#define TZC_PID3_RevAnd_Msk (0xful << TZC_PID3_RevAnd_Pos) /*!< TZC_T::PID3: RevAnd Mask */
#define TZC_CID0_comp_id_0_Pos (0) /*!< TZC_T::CID0: comp_id_0 Position */
#define TZC_CID0_comp_id_0_Msk (0xfful << TZC_CID0_comp_id_0_Pos) /*!< TZC_T::CID0: comp_id_0 Mask */
#define TZC_CID1_comp_id_0_Pos (0) /*!< TZC_T::CID1: comp_id_0 Position */
#define TZC_CID1_comp_id_0_Msk (0xfful << TZC_CID1_comp_id_0_Pos) /*!< TZC_T::CID1: comp_id_0 Mask */
#define TZC_CID2_comp_id_2_Pos (0) /*!< TZC_T::CID2: comp_id_2 Position */
#define TZC_CID2_comp_id_2_Msk (0xfful << TZC_CID2_comp_id_2_Pos) /*!< TZC_T::CID2: comp_id_2 Mask */
#define TZC_CID3_comp_id_3_Pos (0) /*!< TZC_T::CID3: comp_id_3 Position */
#define TZC_CID3_comp_id_3_Msk (0xfful << TZC_CID3_comp_id_3_Pos) /*!< TZC_T::CID3: comp_id_3 Mask */
/**@}*/ /* TZC_CONST */
/**@}*/ /* end of TZC register group */
/**@}*/ /* end of REGISTER group */
#if defined ( __CC_ARM )
#pragma no_anon_unions
#endif
#endif /* __SSMCC_REG_H__ */

2625
bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/sspcc_reg.h Normal file
View File

File diff suppressed because it is too large Load Diff

5816
bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/sys_reg.h Normal file
View File

File diff suppressed because it is too large Load Diff

65
bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/system_ma35d1.h Normal file
View File

@ -0,0 +1,65 @@
/**************************************************************************//**
* @file system_ma35d1_rtp.h
* @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File
*
* SPDX-License-Identifier: Apache-2.0
* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __SYSTEM_MA35D1_RTP_H__
#define __SYSTEM_MA35D1_RTP_H__
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
/*----------------------------------------------------------------------------
Define clocks
*----------------------------------------------------------------------------*/
#define __HSI (24000000UL) /*!< PLL default output is 50MHz */
#define __HXT (24000000UL) /*!< External Crystal Clock Frequency */
#define __LXT (32768UL) /*!< External Crystal Clock Frequency 32.768KHz */
#define __HIRC (12000000UL) /*!< Internal 12M RC Oscillator Frequency */
#define __LIRC (30000UL) /*!< Internal 10K RC Oscillator Frequency */
#define __SYS_OSC_CLK ( ___HSI) /* Main oscillator frequency */
#define __SYSTEM_CLOCK (1UL*__HXT)
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
extern uint32_t CyclesPerUs; /*!< Cycles per micro second */
extern uint32_t PllClock; /*!< PLL Output Clock Frequency */
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the micro controller system.
* Initialize the System and update the SystemCoreClock variable.
*/
extern void SystemInit(void);
/**
* Update SystemCoreClock variable
*
* @param none
* @return none
*
* @brief Updates the SystemCoreClock with current core Clock
* retrieved from cpu registers.
*/
extern void SystemCoreClockUpdate(void);
#ifdef __cplusplus
}
#endif
#endif /* __SYSTEM_MA35D1_RTP_H__ */

1069
bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/timer_reg.h Normal file
View File

File diff suppressed because it is too large Load Diff

922
bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/trng_reg.h Normal file
View File

@ -0,0 +1,922 @@
/**************************************************************************//**
* @file trng_reg.h
* @brief True Random Number Generator register definition header file
*
* SPDX-License-Identifier: Apache-2.0
* @copyright (C) 2021 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __TRNG_REG_H__
#define __TRNG_REG_H__
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
/**
@addtogroup REGISTER Control Register
@{
*/
/*---------------------- True Random Number Generator -------------------------*/
/**
@addtogroup TRNG True Random Number Generator(TRNG)
Memory Mapped Structure for TRNG Controller
@{ */
typedef struct
{
/**
* @var TRNG_T::CTL
* Offset: 0x00 The CTRL register is used to cause the TRNG NIST to execute one of a number of actions.
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[3:0] |CMD |Execute a Command
* | | |Enumerated values not listed are 'reserved'.
* | | |0000 = (NOP): Execute a NOP.
* | | |0001 = (GEN_NOISE): Generate full-entropy seed from noise.
* | | |0010 = (GEN_NONCE): Generate seed from host-written nonce.
* | | |0011 = (CREATE_STATE): Move DRBG to create state.
* | | |0100 = (RENEW_STATE): Move DRBG to renew state.
* | | |0101 = (REFRESH_ADDIN): Move DRBG to refresh addin.
* | | |0110 = (GEN_RANDOM): Generate a random number.
* | | |0111 = (ADVANCE_STATE): Advance DRBG state.
* | | |1000 = (RUN_KAT): Run KAT on DRBG or entropy source.
* | | |1111 = (ZEROIZE): Zeroize.
* @var TRNG_T::MODE
* Offset: 0x04 The MODE register is used to enable or disable certain run-time features within the TRNG NIST.
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |SEC_ALG |Select Security Strength in DRBG
* | | |0 = (SEC_128): AES-128.
* | | |1 = (SEC_256): AES-256.
* |[3] |PRED_RESIST|Prediction Resistance
* | | |0 = (PRED_DISABLE): Prediction resistance is not required.
* | | |1 = (PRED_ENABLED): Prediction resistance is required.
* |[4] |ADDIN_PRESENT|Availability of the Additional Input
* | | |0 = (ADDIN_NOT_REQ): No Additional Input required from host.
* | | |1 = (ADDIN_REQ): Additional input must be provided by host.
* |[6:5] |KAT_VEC |Select Test Vectors for Known-answer Test
* | | |00 = (KAT_VEC0): KAT vector 0.
* | | |01 = (KAT_VEC1): KAT vector 1.
* | | |10 = (KAT_VEC2): KAT vector 2.
* | | |11 = (KAT_ALL): Run all 3 KAT vectors.
* |[8:7] |KAT_SEL |Select Test Component for Known-answer Test
* | | |00 = (KAT_DRBG): KAT on DRBG.
* | | |01 = (KAT_DF): KAT on conditioning component (Derivation Function).
* | | |10 = (KAT_BOTH): KAT on both DRBG and DF.
* | | |11 = Reserved.
* @var TRNG_T::SMODE
* Offset: 0x08 The SMODE register is used to enable or disable certain MISSION mode run-time features.
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |NONCE |Set the Core in Nonce Seeding Mode
* | | |0 = (NONCE_DISABLED): Disable nonce mode.
* | | |1 = (NONCE_ENABLED): Enable nonce mode.
* |[1] |MISSION_MODE|Operating Mode
* | | |0 = (RST_TEST_MODE): test mode.
* | | |1 = (RST_MISSION_MODE): mission mode.
* | | |Note: Any change to the state of this field (1 to 0 or 0 to 1) causes the TRNG NIST to zeroize itself.
* |[9:2] |MAX_REJECTS|Maximum Number of Consecutive Bit Rejections Before Issuing Ring Tweak
* | | |Default is to 10 (0xa).
* |[23:16] |INDIV_HT_DISABLE|Statistical Health Tests Individually
* | | |0 = Disable.
* | | |1 = Enable.
* | | |INDIV_HT_DISABLE[0] = Repetition Count test on raw entropy.
* | | |INDIV_HT_DISABLE[1] = Adaptive Proportion test on raw entropy.
* | | |INDIV_HT_DISABLE[2] = Monobit test on raw entropy.
* | | |INDIV_HT_DISABLE[3] = Poker test on raw entropy.
* | | |INDIV_HT_DISABLE[4] = Run test on raw entropy.
* | | |INDIV_HT_DISABLE[5] = Long Run test on raw entropy.
* | | |INDIV_HT_DISABLE[6] = Auto-correlation test on raw entropy.
* | | |INDIV_HT_DISABLE[7] = Repetition Count test on entropy source output.
* | | |Note: Users only can enable/disable statistical health test in TEST mode
* | | |This field cannot change in MISSION mode and its value is always 0 in MISSION mode.
* |[31] |NOISE_COLLECT|Raw Noise Collection Mode
* | | |0 = Disable.
* | | |1 = Enable.
* | | |Note: Users only can enable/disable raw noise collection in TEST mode
* | | |This bit cannot be set to 1 in MISSION mode.
* @var TRNG_T::STAT
* Offset: 0x0C The STAT register allows the user to monitor the internal status of the TRNG NIST.
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[3:0] |LAST_CMD |Last Command
* | | |0000 = (NOP).
* | | |0001 = (GEN_NOISE).
* | | |0011 = (GEN_NONCE).
* | | |0011 = (CREATE_STATE).
* | | |0100 = (RENEW_STATE).
* | | |0101 = (REFRESH_ADDIN).
* | | |0110 = (GEN_RANDOM).
* | | |0111 = (ADVANCE_STATE).
* | | |1000 = (RUN_KAT).
* | | |1111 = (ZEROIZE).
* | | |Others = Reserved.
* |[4] |SEC_ALG |Reflects State of MODE.SEC_ALG
* | | |0 = (SEC_ALG_0): Maximum security strength set to 128.
* | | |1 =(SEC_ALG_1): Maximum security strength set to 256.
* |[5] |NONCE_MODE|Reflects State of SMODE.NONCE
* | | |0 = (NONCE_DISABLE): Nonce mode disabled.
* | | |1 = (NONCE_ENABLE): Nonce mode enabled (allows CTRL.CMD value of 2).
* |[6] |MISSION_MODE|Reflects State of SMODE.MISSION_MODE
* | | |0 = (SEC_MODE_MISSION): Core is in TEST mode.
* | | |1 = (SEC_MODE_TEST): Core is in MISSION mode.
* |[8:7] |DRBG_STATE|Reflects How a DRBG State Is Instantiated
* | | |00 = (DRBG_NOT_INIT): State is not instantiated.
* | | |01 = (DRBG_NS): State is instantiated using the built-in noise source.
* | | |10 = (DRBG_HOST): State is instantiated using the host-provided nonce.
* | | |11 = Reserved.
* |[9] |STARTUP_TEST_STUCK|Indicates Whether the Startup Test Is Stuck
* | | |0 = (STARTUP_TEST_NOT_STUCK): Startup test is not stuck (yet).
* | | |1 = (STARTUP_TEST_IS_STUCK): Startup test is highly likely stuck.
* | | |Note: Only valid when sticky startup test feature Is enabled.
* |[10] |STARTUP_TEST_IN_PROG|Indicates Whether the Startup Test Is in Progress
* | | |0 = (STARTUP_TEST_NOT_STUCK): Startup test is finished.
* | | |1 = (STARTUP_TEST_IS_STUCK): Startup test is in progress.
* |[31] |BUSY |State of the Core
* | | |0 = (BUSY_NOT): Idle.
* | | |1 = (BUSY_EXEC): Currently executing a command.
* @var TRNG_T::IE
* Offset: 0x10 The IE register is used to enable or disable interrupts within the TRNG NIST.
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |ZEROIZED |Include or Exclude ZEROIZED Interrupt Contribution
* | | |0 = (ZEROIZED_DIS): Disable ZEROIZED interrupt contribution.
* | | |1 = (ZEROIZED_EN): Enable ZEROIZED interrupt contribution.
* |[1] |KAT_COMPLETED|Include or Exclude KAT_COMPLETED Interrupt Contribution
* | | |0 = (KAT_COMPLETED_DIS): Disable KAT_COMPLETED interrupt contribution.
* | | |1 = (KAT_COMPLETED_EN): Enable KAT_COMPLETED interrupt contribution.
* |[2] |NOISE_RDY |Include or Exclude NOISE_RDY Interrupt Contribution
* | | |0 = (NOISE_RDY_DIS): Disable NOISE_RDY interrupt contribution.
* | | |1 = (NOISE_RDY_EN): Enable NOISE_RDY interrupt contribution.
* |[3] |ALARMS |Include or Exclude ALARMS Interrupt Contribution
* | | |0 = (ALARMS_DIS): Disable ALARMS interrupt contribution.
* | | |1 = (ALARMS_EN): Enable ALARMS interrupt contribution.
* |[4] |DONE |Include or Exclude DONE Interrupt Contribution
* | | |0 = (DONE_DIS): Disable DONE interrupt contribution.
* | | |1 = (DONE_EN): Enable DONE interrupt contribution.
* |[31] |GLBL |Global Interrupt Enable Signal for the TRNG NIST
* | | |0 = (GLBL_DIS): Disable GLBL interrupt contribution.
* | | |1 = (GLBL_EN): Enable GLBL interrupt contribution.
* @var TRNG_T::ISTAT
* Offset: 0x14 The ISTAT register allows the user to monitor the interrupt contributions of the TRNG NIST.
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |ZEROIZED |ZEROIZED Flag
* | | |Indicates the Completion of the ZEROIZE Operation
* | | |0 = (ZEROIZED_R0): R0: No unacknowledged ZEROIZED.
* | | | (ZEROIZED_W0): W0: NOP.
* | | |1 = (ZEROIZED_R1): R1: Unacknowledged ZEROIZED.
* | | | (ZEROIZED_W1): W1: Clear ZEROIZED flag.
* |[1] |KAT_COMPLETED|KAT_COMPLETED Flag
* | | |Indicates the Completion of the RUN_KAT Command
* | | |0 = (KAT_COMPLETED_R0): R0: No unacknowledged KAT_COMPLETED.
* | | | (KAT_COMPLETED_W0): W0: NOP.
* | | |1 = (KAT_COMPLETED_R1): R1: Unacknowledged KAT_COMPLETED.
* | | | (KAT_COMPLETED_W1): W1: Clear KAT_COMPLETED flag.
* |[2] |NOISE_RDY |NOISE_RDY Flag
* | | |When TRNG NIST is generating a full-entropy seed in the self-seeding mode, MISSION_MODE(TRNG_SMODE[1]) is 0 (TEST mode) and SMODE.NOISE_COLLECT is set to 1, the NOISE_RDY bit informs the user when 512 bits of noise have been generated
* | | |This interrupt never happens in the MISSION mode of operation.
* | | |0 = (NOISE_RDY_R0): R0: No unacknowledged noise generation completion.
* | | | (NOISE_RDY_W0): W0: NOP.
* | | |1 = (NOISE_RDY_R1): R1: Unacknowledged noise generation completion.
* | | | (NOISE_RDY_W1): W1: Clear NOISE_RDY flag.
* |[3] |ALARMS |ALARMS Flag
* | | |The ALARMS bit allows the user to poll failures
* | | |When an alarm occurs, an automatic zeroize happens
* | | |Clearing this interrupt also clears the O_alarm pin.
* | | |0 = (ALARMS_R0): R0: No unacknowledged ALARMS.
* | | | (ALARMS_W0): W0: NOP.
* | | |1 = (ALARMS_R1): R1: Unacknowledged ALARMS.
* | | | (ALARMS_W1): W1: Clear ALARMS flag.
* |[4] |DONE |DONE Flag
* | | |The DONE bit allows the user to poll the completion of all commands except RUN_KAT and ZEROIZE which have their own interrupt.
* | | |0 = (DONE_R0): R0: No unacknowledged command completion.
* | | | (DONE_W0): W0: NOP.
* | | |1 = (DONE_R1): R1: Unacknowledged command completion.
* | | | (DONE_W1): W1: Clear DONE flag.
* @var TRNG_T::ALARMS
* Offset: 0x18 The ALARMS register allows the user to monitor the source of critical alarms.
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[3:0] |FAILED_TEST_ID|FAILED_TEST_ID Error Flag
* | | |When an alarm is issued, the FAILED_TEST_ID field shows which test has failed
* | | |This fields only shows the first detected failed test and it should not be assumed that the remaining statistical tests are passed.
* | | |0000 = (FAILED_TEST_ID_0): no failure.
* | | |0001 = (FAILED_TEST_ID_1): failure in both KAT and statistical tests.
* | | |0010 = (FAILED_TEST_ID_2): KAT test failure.
* | | |0011 = (FAILED_TEST_ID_3): Monobit test failure.
* | | |0100 = (FAILED_TEST_ID_4): Run test failure.
* | | |0101 = (FAILED_TEST_ID_5): Long Run test failure.
* | | |0110 = (FAILED_TEST_ID_6): Auto-correlation test failure.
* | | |0111 = (FAILED_TEST_ID_7): Poker test failure.
* | | |1000 = (FAILED_TEST_ID_8): Repetition Count test failure.
* | | |1001 = (FAILED_TEST_ID_9): Adaptive Proportion test failure.
* | | |Others = Reserved.
* |[4] |ILLEGAL_CMD_SEQ|ILLEGAL_CMD_SEQ Error Flag
* | | |The ILLEGAL_CMD_SEQ field indicates that the SOFTWARE Driver has executed an illegal command sequence.
* | | |0 = (ILLEGAL_CMD_SEQ _0): no failure.
* | | |1 = (ILLEGAL_CMD_SEQ _1): Executed an illegal command sequence.
* |[5] |FAILED_SEED_ST_HT|FAILED_SEED_ST_HT Error Flag
* | | |The FAILED_SEED_ST_HT field indicates that the statistical tests applied on the entropy source output is failed (Only valid when entropy source output statistical health test feature is included).
* | | |0 = (FAILED_SEED_ST_HT_0): no failure.
* | | |1 = (FAILED_SEED_ST_HT_1): Entropy source health test is failed.
* @var TRNG_T::COREKIT_REL
* Offset: 0x1C Contains the static coreKit release information.
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |REL_NUM |The CoreKit Release Version In Pseudo-BCD
* | | |For example, release '2.35e-lca04' is encoded as 0x235e.
* | | |This TRNG version is 0x300a.
* |[23:16] |EXT_VER |The CoreKit Release Extension Version Number
* | | |For example, release '2.35e-lp04' is encoded as 0x4.
* | | |GA releases has a value of 0.
* |[31:28] |EXT_ENUM |The CoreKit Release Extension Type
* | | |For example, release '2.35e-lca04' is encoded as 0x1.
* | | |0000 = (EXT_ENUM_GA): GA release.
* | | |0001 = (EXT_ENUM_LCA): LCA release.
* | | |0010 = (EXT_ENUM_EA): EA release.
* | | |0011 = (EXT_ENUM_LP): LP release.
* | | |0100 = (EXT_ENUM_LPC): LPC release.
* | | |0101 = (EXT_ENUM_SOW): SOW release.
* | | |Others = Reserved.
* @var TRNG_T::FEATURES
* Offset: 0x20 The FEATURES register returns the state of various build-time parameter values.
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |SECURE_RST_STATE|The Core Resets to MISSION or TEST Mode
* | | |0 = test mode.
* | | |1 = mission mode.
* |[3:1] |DIAG_LEVEL_ST_HLT|Level Of Diagnostic Circuitry For The Health Test
* |[6:4] |DIAG_LEVEL_CLP800|Level Of Diagnostic Circuitry For TRNG When Noise Source
* |[7] |DIAG_LEVEL_NS|Level Of Diagnostic Circuitry For Noise Source Output Registers
* |[8] |PS_PRESENT|The NPA_DATAx Registers Is used As A Personalization String During The Create_State Command
* | | |0 = No.
* | | |1 = Yes.
* |[9] |AES_256 |The Instantiated AES
* | | |0 = AES-128.
* | | |1 = AES-256.
* @var TRNG_T::RAND0
* Offset: 0x24 The RAND0 register is used by the host to read bits [31:0] of the newly generated 128-bit random data.
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |RAND |Random Data Word
* @var TRNG_T::RAND1
* Offset: 0x28 The RAND1 register is used by the host to read bits [63:32] of the newly generated 128-bit random data.
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |RAND |Random Data Word
* @var TRNG_T::RAND2
* Offset: 0x2C The RAND2 register is used by the host to read bits [95:64] of the newly generated 128-bit random data.
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |RAND |Random Data Word
* @var TRNG_T::RAND3
* Offset: 0x30 The RAND3 register is used by the host to read bits [127:96] of the newly generated 128-bit random data.
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |RAND |Random Data Word
* @var TRNG_T::NPA_DATA0
* Offset: 0x34 The NPA_DATA0 register holds Noise/Nonce/Personalization String/Additional Input - bits [31:0].
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |NPA_DATA |NPA data word
* | | |Noise/Nonce can be stored in register NPA_DATA0 ~ NPA_DATA15.
* | | |Personalization String/Additional Input can be stored in register NPA_DATA0 ~ NPA_DATA11.
* @var TRNG_T::NPA_DATA1
* Offset: 0x38 The NPA_DATA1 register holds Noise/Nonce/Personalization String/Additional Input - bits [63:32].
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |NPA_DATA |NPA data word
* | | |Noise/Nonce can be stored in register NPA_DATA0 ~ NPA_DATA15.
* | | |Personalization String/Additional Input can be stored in register NPA_DATA0 ~ NPA_DATA11.
* @var TRNG_T::NPA_DATA2
* Offset: 0x3C The NPA_DATA2 register holds Noise/Nonce/Personalization String/Additional Input - bits [95:64].
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |NPA_DATA |NPA data word
* | | |Noise/Nonce can be stored in register NPA_DATA0 ~ NPA_DATA15.
* | | |Personalization String/Additional Input can be stored in register NPA_DATA0 ~ NPA_DATA11.
* @var TRNG_T::NPA_DATA3
* Offset: 0x40 The NPA_DATA3 register holds Noise/Nonce/Personalization String/Additional Input - bits [127:96].
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |NPA_DATA |NPA data word
* | | |Noise/Nonce can be stored in register NPA_DATA0 ~ NPA_DATA15.
* | | |Personalization String/Additional Input can be stored in register NPA_DATA0 ~ NPA_DATA11.
* @var TRNG_T::NPA_DATA4
* Offset: 0x44 The NPA_DATA4 register holds Noise/Nonce/Personalization String/Additional Input - bits [159:128].
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |NPA_DATA |NPA data word
* | | |Noise/Nonce can be stored in register NPA_DATA0 ~ NPA_DATA15.
* | | |Personalization String/Additional Input can be stored in register NPA_DATA0 ~ NPA_DATA11.
* @var TRNG_T::NPA_DATA5
* Offset: 0x48 The NPA_DATA5 register holds Noise/Nonce/Personalization String/Additional Input - bits [191:160].
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |NPA_DATA |NPA data word
* | | |Noise/Nonce can be stored in register NPA_DATA0 ~ NPA_DATA15.
* | | |Personalization String/Additional Input can be stored in register NPA_DATA0 ~ NPA_DATA11.
* @var TRNG_T::NPA_DATA6
* Offset: 0x4C The NPA_DATA6 register holds Noise/Nonce/Personalization String/Additional Input - bits [223:192].
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |NPA_DATA |NPA data word
* | | |Noise/Nonce can be stored in register NPA_DATA0 ~ NPA_DATA15.
* | | |Personalization String/Additional Input can be stored in register NPA_DATA0 ~ NPA_DATA11.
* @var TRNG_T::NPA_DATA7
* Offset: 0x50 The NPA_DATA7 register holds Noise/Nonce/Personalization String/Additional Input - bits [255:224].
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |NPA_DATA |NPA data word
* | | |Noise/Nonce can be stored in register NPA_DATA0 ~ NPA_DATA15.
* | | |Personalization String/Additional Input can be stored in register NPA_DATA0 ~ NPA_DATA11.
* @var TRNG_T::NPA_DATA8
* Offset: 0x54 The NPA_DATA8 register holds Noise/Nonce/Personalization String/Additional Input - bits [287:256].
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |NPA_DATA |NPA data word
* | | |Noise/Nonce can be stored in register NPA_DATA0 ~ NPA_DATA15.
* | | |Personalization String/Additional Input can be stored in register NPA_DATA0 ~ NPA_DATA11.
* @var TRNG_T::NPA_DATA9
* Offset: 0x58 The NPA_DATA9 register holds Noise/Nonce/Personalization String/Additional Input - bits [319:288].
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |NPA_DATA |NPA data word
* | | |Noise/Nonce can be stored in register NPA_DATA0 ~ NPA_DATA15.
* | | |Personalization String/Additional Input can be stored in register NPA_DATA0 ~ NPA_DATA11.
* @var TRNG_T::NPA_DATA10
* Offset: 0x5C The NPA_DATA10 register holds Noise/Nonce/Personalization String/Additional Input - bits [351:320].
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |NPA_DATA |NPA data word
* | | |Noise/Nonce can be stored in register NPA_DATA0 ~ NPA_DATA15.
* | | |Personalization String/Additional Input can be stored in register NPA_DATA0 ~ NPA_DATA11.
* @var TRNG_T::NPA_DATA11
* Offset: 0x60 The NPA_DATA11 register holds Noise/Nonce/Personalization String/Additional Input - bits [383:352].
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |NPA_DATA |NPA data word
* | | |Noise/Nonce can be stored in register NPA_DATA0 ~ NPA_DATA15.
* | | |Personalization String/Additional Input can be stored in register NPA_DATA0 ~ NPA_DATA11.
* @var TRNG_T::NPA_DATA12
* Offset: 0x64 The NPA_DATA12 register holds Noise/Nonce - bits [415:384].
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |NPA_DATA |NPA data word
* | | |Noise/Nonce can be stored in register NPA_DATA0 ~ NPA_DATA15.
* | | |Personalization String/Additional Input can be stored in register NPA_DATA0 ~ NPA_DATA11.
* @var TRNG_T::NPA_DATA13
* Offset: 0x68 The NPA_DATA13 register holds Noise/Nonce - bits [447:416].
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |NPA_DATA |NPA data word
* | | |Noise/Nonce can be stored in register NPA_DATA0 ~ NPA_DATA15.
* | | |Personalization String/Additional Input can be stored in register NPA_DATA0 ~ NPA_DATA11.
* @var TRNG_T::NPA_DATA14
* Offset: 0x6C The NPA_DATA14 register holds Noise/Nonce - bits [479:448].
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |NPA_DATA |NPA data word
* | | |Noise/Nonce can be stored in register NPA_DATA0 ~ NPA_DATA15.
* | | |Personalization String/Additional Input can be stored in register NPA_DATA0 ~ NPA_DATA11.
* @var TRNG_T::NPA_DATA15
* Offset: 0x70 The NPA_DATA15 register holds Noise/Nonce - bits [511:480].
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |NPA_DATA |NPA data word
* | | |Noise/Nonce can be stored in register NPA_DATA0 ~ NPA_DATA15.
* | | |Personalization String/Additional Input can be stored in register NPA_DATA0 ~ NPA_DATA11.
* @var TRNG_T::SEED0
* Offset: 0x74 The SEED0 register holds seed value used in the DRBG - bits [31:0].
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |SEED |SEED data word
* @var TRNG_T::SEED1
* Offset: 0x78 The SEED1 register holds seed value used in the DRBG - bits [63:32].
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |SEED |SEED data word
* @var TRNG_T::SEED2
* Offset: 0x7C The SEED2 register holds seed value used in the DRBG - bits [95:64].
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |SEED |SEED data word
* @var TRNG_T::SEED3
* Offset: 0x80 The SEED3 register holds seed value used in the DRBG - bits [127:96].
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |SEED |SEED data word
* @var TRNG_T::SEED4
* Offset: 0x84 The SEED4 register holds seed value used in the DRBG - bits [159:128].
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |SEED |SEED data word
* @var TRNG_T::SEED5
* Offset: 0x88 The SEED5 register holds seed value used in the DRBG - bits [191:160].
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |SEED |SEED data word
* @var TRNG_T::SEED6
* Offset: 0x8C The SEED6 register holds seed value used in the DRBG - bits [223:192].
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |SEED |SEED data word
* @var TRNG_T::SEED7
* Offset: 0x90 The SEED7 register holds seed value used in the DRBG - bits [255:224].
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |SEED |SEED data word
* @var TRNG_T::SEED8
* Offset: 0x94 The SEED8 register holds seed value used in the DRBG - bits [287:256].
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |SEED |SEED data word
* @var TRNG_T::SEED9
* Offset: 0x98 The SEED9 register holds seed value used in the DRBG - bits [319:288].
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |SEED |SEED data word
* @var TRNG_T::SEED10
* Offset: 0x9C The SEED10 register holds seed value used in the DRBG - bits [351:320].
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |SEED |SEED data word
* @var TRNG_T::SEED11
* Offset: 0xA0 The SEED11 register holds seed value used in the DRBG - bits [383:352].
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |SEED |SEED data word
* @var TRNG_T::TIME_TO_SEED
* Offset: 0xD0 The Time-to-Seed (TTS) register records the number of clock cycles taken to collect the set of raw noise bits used by the previous GEN_NOISE command.
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |TTS |TRNG Time To Seed Shows the number of system clock cycles taken to generate raw noise for the last GEN_NOISE command.
* @var TRNG_T::BUILD_CFG0
* Offset: 0xF0 Contains build-time TRNG NIST parameter settings.
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[1:0] |CORE_TYPE |Core Type
* | | |00 = (CORE_TYPE_BASE_TRNG): TRNG.
* | | |01 = (CORE_TYPE_BASE_TRNG_WITH_ESM_NONCE): TRNG with ESM nonce I/O.
* | | |10 = (CORE_TYPE_NIST_TRNG): TRNG NIST.
* | | |11 = (CORE_TYPE_NIST_TRNG_WITH_EDU): TRNG NIST with EDU.
* |[7] |BG8 |Indicates Number Of Bit Generators Present
* | | |0 = (SIX_BGS): 6 Bit Generators present.
* | | |1 = (EIGHT_BGS): 8 Bit Generators present..
* |[9:8] |CDC_SYNC_DEPTH|Depth Of The CDC Resynchronizer Chains
* | | |00 = (CDC_RESYNC_4): CDC resynchronizer depth 4.
* | | |01 = Reserved.
* | | |10 = (CDC_RESYNC_2): CDC resynchronizer depth 2.
* | | |11 = (CDC_RESYNC_3): CDC resynchronizer depth 3.
* |[10] |BACKGROUND_NOISE|Indicates Background Noise Collection Is Present
* | | |0 = (BACKGROUND_NOISE _NOT_PRESENT): not present.
* | | |1 = (BACKGROUND_NOISE_PRESENT): present..
* |[11] |EDU_PRESENT|Indicates EDU Is Present
* | | |0 = (EDU_PRESENT_NOT_PRESENT): not present.
* | | |1 = (EDU_PRESENT_PRESENT): present..
* |[12] |AES_DATAPATH|AES Datapath Width
* | | |0 = (AES_DATAPATH_32): 32-bit datapath.
* | | |1 = (AES_DATAPATH_128): 128-bit datapath.
* |[13] |AES_MAX_KEY_SIZE|AES Max Key Size
* | | |0 = (AES_MAX_KEY_SIZE_128): 128-bit key.
* | | |1 = (AES_MAX_KEY_SIZE_256): 256-bit key.
* |[14] |PERSONALIZATION_STR|Personalization String Used
* | | |0 = (PS_NOT_PRESENT): not present.
* | | |1 = (PS_PRESENT): present.
* @var TRNG_T::BUILD_CFG1
* Offset: 0xF4 Contains additional build-time TRNG NIST parameter settings.
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |NUM_RAW_NOISE_BLKS|Number of Raw Noise Blocks Used for Start-up Test
* |[8] |STICKY_STARTUP|Sticky-startup Test Present
* | | |0 = (STICKY_STARTUP_TEST_NOT_PRESENT): not present.
* | | |1 = (STICKY_STARTUP_TEST_PRESENT): present.
* |[12] |AUTO_CORRELATION_TEST|Auto-correlation Test Present
* | | |0 = (AUTO_CORRELATION_TEST_NOT_PRESENT): not present.
* | | |1 = (AUTO_CORRELATION_TEST_PRESENT): present.
* |[13] |MONOBIT_TEST|Monobit Test Present
* | | |0 = (MONOBIT_TEST_NOT_PRESENT): not present.
* | | |1 = (MONOBIT_TEST_PRESENT): present.
* |[14] |RUN_TEST |Run Test Present
* | | |0 = (RUN_TEST_NOT_PRESENT): not present.
* | | |1 = (RUN_TEST_PRESENT): present.
* |[15] |POKER_TEST|Poker Test Present
* | | |0 = (POKER_TEST_NOT_PRESENT): not present.
* | | |1 = (POKER_TEST_PRESENT): present.
* |[18:16] |RAW_HT_ADAP_TEST|Raw Health Adaptive Proportion Test
* | | |000 = (RAW_HT_ADAP_TEST_NOT_PRESENT): not present.
* | | |001 = (RAW_HT_ADAP_TEST_1K_SAMPLES): 1k samples per window.
* | | |010 = (RAW_HT_ADAP_TEST_2K_SAMPLES): 2k samples per window.
* | | |011 = (RAW_HT_ADAP_TEST_4K_SAMPLES): 4k samples per window.
* | | |100 = (RAW_HT_ADAP_TEST_8K_SAMPLES): 8k samples per window.
* | | |101 = (RAW_HT_ADAP_TEST_16K_SAMPLES): 16k samples per window.
* | | |110 = (RAW_HT_ADAP_TEST_32K_SAMPLES): 32k samples per window.
* | | |111 = (RAW_HT_ADAP_TEST_64K_SAMPLES): 64k samples per window.
* |[19] |RAW_HT_REP_TEST|Raw Health Repetition Test Present
* | | |0 = (RAW_HT_REP_TEST_NOT_PRESENT): not present.
* | | |1 = (RAW_HT_REP_TEST_PRESENT): present.
* |[22:20] |ENT_SRC_REP_SMPL_SIZE|Entropy Source: Sample Size
* | | |000 = (ENT_SRC_REP_SMPL_SIZE_1): Sample size 1.
* | | |001 = (ENT_SRC_REP_SMPL_SIZE_2): Sample size 2.
* | | |010 = (ENT_SRC_REP_SMPL_SIZE_4): Sample size 4.
* | | |011 = (ENT_SRC_REP_SMPL_SIZE_8): Sample size 8.
* | | |100 = (ENT_SRC_REP_SMPL_SIZE_16): Sample size 16.
* | | |101 = (ENT_SRC_REP_SMPL_SIZE_32): Sample size 32.
* | | |110 = (ENT_SRC_REP_SMPL_SIZE_64): Sample size 64.
* | | |111 = (ENT_SRC_REP_SMPL_SIZE_128): Sample size 128.
* |[23] |ENT_SRC_REP_TEST|Entropy Source Repetition Test Present
* | | |0 = (ENT_SRC_REP_TEST_NOT_PRESENT): not present.
* | | |1 = (ENT_SRC_REP_TEST_PRESENT): present.
* |[30:24] |ENT_SRC_REP_MIN_ENTROPY|Entropy Source Repetition Minimum Entropy Per Bit
*/
__O uint32_t CTL; /*!< [0x0000] The CTRL register is used to cause the TRNG NIST to execute one of a number of actions. */
__IO uint32_t MODE; /*!< [0x0004] The MODE register is used to enable or disable certain run-time features within the TRNG NIST. */
__IO uint32_t SMODE; /*!< [0x0008] The SMODE register is used to enable or disable certain MISSION mode run-time features. */
__I uint32_t STAT; /*!< [0x000c] The STAT register allows the user to monitor the internal status of the TRNG NIST. */
__IO uint32_t IE; /*!< [0x0010] The IE register is used to enable or disable interrupts within the TRNG NIST. */
__IO uint32_t ISTAT; /*!< [0x0014] The ISTAT register allows the user to monitor the interrupt contributions of the TRNG NIST. */
__IO uint32_t ALARMS; /*!< [0x0018] The ALARMS register allows the user to monitor the source of critical alarms. */
__I uint32_t COREKIT_REL; /*!< [0x001c] Contains the static coreKit release information. */
__I uint32_t FEATURES; /*!< [0x0020] The FEATURES register returns the state of various build-time parameter values. */
__I uint32_t RAND0; /*!< [0x0024] The RAND0 register is used by the host to read bits [31:0] of the newly generated 128-bit random data. */
__I uint32_t RAND1; /*!< [0x0028] The RAND1 register is used by the host to read bits [63:32] of the newly generated 128-bit random data. */
__I uint32_t RAND2; /*!< [0x002c] The RAND2 register is used by the host to read bits [95:64] of the newly generated 128-bit random data. */
__I uint32_t RAND3; /*!< [0x0030] The RAND3 register is used by the host to read bits [127:96] of the newly generated 128-bit random data. */
__IO uint32_t NPA_DATA0; /*!< [0x0034] The NPA_DATA0 register holds Noise/Nonce/Personalization String/Additional Input - bits [31:0]. */
__IO uint32_t NPA_DATA1; /*!< [0x0038] The NPA_DATA1 register holds Noise/Nonce/Personalization String/Additional Input - bits [63:32]. */
__IO uint32_t NPA_DATA2; /*!< [0x003c] The NPA_DATA2 register holds Noise/Nonce/Personalization String/Additional Input - bits [95:64]. */
__IO uint32_t NPA_DATA3; /*!< [0x0040] The NPA_DATA3 register holds Noise/Nonce/Personalization String/Additional Input - bits [127:96]. */
__IO uint32_t NPA_DATA4; /*!< [0x0044] The NPA_DATA4 register holds Noise/Nonce/Personalization String/Additional Input - bits [159:128]. */
__IO uint32_t NPA_DATA5; /*!< [0x0048] The NPA_DATA5 register holds Noise/Nonce/Personalization String/Additional Input - bits [191:160]. */
__IO uint32_t NPA_DATA6; /*!< [0x004c] The NPA_DATA6 register holds Noise/Nonce/Personalization String/Additional Input - bits [223:192]. */
__IO uint32_t NPA_DATA7; /*!< [0x0050] The NPA_DATA7 register holds Noise/Nonce/Personalization String/Additional Input - bits [255:224]. */
__IO uint32_t NPA_DATA8; /*!< [0x0054] The NPA_DATA8 register holds Noise/Nonce/Personalization String/Additional Input - bits [287:256]. */
__IO uint32_t NPA_DATA9; /*!< [0x0058] The NPA_DATA9 register holds Noise/Nonce/Personalization String/Additional Input - bits [319:288]. */
__IO uint32_t NPA_DATA10; /*!< [0x005c] The NPA_DATA10 register holds Noise/Nonce/Personalization String/Additional Input - bits [351:320]. */
__IO uint32_t NPA_DATA11; /*!< [0x0060] The NPA_DATA11 register holds Noise/Nonce/Personalization String/Additional Input - bits [383:352]. */
__IO uint32_t NPA_DATA12; /*!< [0x0064] The NPA_DATA12 register holds Noise/Nonce - bits [415:384]. */
__IO uint32_t NPA_DATA13; /*!< [0x0068] The NPA_DATA13 register holds Noise/Nonce - bits [447:416]. */
__IO uint32_t NPA_DATA14; /*!< [0x006c] The NPA_DATA14 register holds Noise/Nonce - bits [479:448]. */
__IO uint32_t NPA_DATA15; /*!< [0x0070] The NPA_DATA15 register holds Noise/Nonce - bits [511:480]. */
__IO uint32_t SEED0; /*!< [0x0074] The SEED0 register holds seed value used in the DRBG - bits [31:0]. */
__IO uint32_t SEED1; /*!< [0x0078] The SEED1 register holds seed value used in the DRBG - bits [63:32]. */
__IO uint32_t SEED2; /*!< [0x007c] The SEED2 register holds seed value used in the DRBG - bits [95:64]. */
__IO uint32_t SEED3; /*!< [0x0080] The SEED3 register holds seed value used in the DRBG - bits [127:96]. */
__IO uint32_t SEED4; /*!< [0x0084] The SEED4 register holds seed value used in the DRBG - bits [159:128]. */
__IO uint32_t SEED5; /*!< [0x0088] The SEED5 register holds seed value used in the DRBG - bits [191:160]. */
__IO uint32_t SEED6; /*!< [0x008c] The SEED6 register holds seed value used in the DRBG - bits [223:192]. */
__IO uint32_t SEED7; /*!< [0x0090] The SEED7 register holds seed value used in the DRBG - bits [255:224]. */
__IO uint32_t SEED8; /*!< [0x0094] The SEED8 register holds seed value used in the DRBG - bits [287:256]. */
__IO uint32_t SEED9; /*!< [0x0098] The SEED9 register holds seed value used in the DRBG - bits [319:288]. */
__IO uint32_t SEED10; /*!< [0x009c] The SEED10 register holds seed value used in the DRBG - bits [351:320]. */
__IO uint32_t SEED11; /*!< [0x00a0] The SEED11 register holds seed value used in the DRBG - bits [383:352]. */
__I uint32_t RESERVE0[11];
__I uint32_t TIME_TO_SEED; /*!< [0x00d0] The Time-to-Seed (TTS) register records the number of clock cycles taken to collect the set of raw noise bits used by the previous GEN_NOISE command. */
__I uint32_t RESERVE1[7];
__I uint32_t BUILD_CFG0; /*!< [0x00f0] Contains build-time TRNG NIST parameter settings. */
__I uint32_t BUILD_CFG1; /*!< [0x00f4] Contains additional build-time TRNG NIST parameter settings. */
} TRNG_T;
/**
@addtogroup TRNG_CONST TRNG Bit Field Definition
Constant Definitions for TRNG Controller
@{ */
#define TRNG_CTL_CMD_Pos (0) /*!< TRNG_T::CTL: CMD Position */
#define TRNG_CTL_CMD_Msk (0xful << TRNG_CTL_CMD_Pos) /*!< TRNG_T::CTL: CMD Mask */
#define TRNG_MODE_SEC_ALG_Pos (0) /*!< TRNG_T::MODE: SEC_ALG Position */
#define TRNG_MODE_SEC_ALG_Msk (0x1ul << TRNG_MODE_SEC_ALG_Pos) /*!< TRNG_T::MODE: SEC_ALG Mask */
#define TRNG_MODE_PRED_RESIST_Pos (3) /*!< TRNG_T::MODE: PRED_RESIST Position */
#define TRNG_MODE_PRED_RESIST_Msk (0x1ul << TRNG_MODE_PRED_RESIST_Pos) /*!< TRNG_T::MODE: PRED_RESIST Mask */
#define TRNG_MODE_ADDIN_PRESENT_Pos (4) /*!< TRNG_T::MODE: ADDIN_PRESENT Position */
#define TRNG_MODE_ADDIN_PRESENT_Msk (0x1ul << TRNG_MODE_ADDIN_PRESENT_Pos) /*!< TRNG_T::MODE: ADDIN_PRESENT Mask */
#define TRNG_MODE_KAT_VEC_Pos (5) /*!< TRNG_T::MODE: KAT_VEC Position */
#define TRNG_MODE_KAT_VEC_Msk (0x3ul << TRNG_MODE_KAT_VEC_Pos) /*!< TRNG_T::MODE: KAT_VEC Mask */
#define TRNG_MODE_KAT_SEL_Pos (7) /*!< TRNG_T::MODE: KAT_SEL Position */
#define TRNG_MODE_KAT_SEL_Msk (0x3ul << TRNG_MODE_KAT_SEL_Pos) /*!< TRNG_T::MODE: KAT_SEL Mask */
#define TRNG_SMODE_NONCE_Pos (0) /*!< TRNG_T::SMODE: NONCE Position */
#define TRNG_SMODE_NONCE_Msk (0x1ul << TRNG_SMODE_NONCE_Pos) /*!< TRNG_T::SMODE: NONCE Mask */
#define TRNG_SMODE_MISSION_MODE_Pos (1) /*!< TRNG_T::SMODE: MISSION_MODE Position */
#define TRNG_SMODE_MISSION_MODE_Msk (0x1ul << TRNG_SMODE_MISSION_MODE_Pos) /*!< TRNG_T::SMODE: MISSION_MODE Mask */
#define TRNG_SMODE_MAX_REJECTS_Pos (2) /*!< TRNG_T::SMODE: MAX_REJECTS Position */
#define TRNG_SMODE_MAX_REJECTS_Msk (0xfful << TRNG_SMODE_MAX_REJECTS_Pos) /*!< TRNG_T::SMODE: MAX_REJECTS Mask */
#define TRNG_SMODE_INDIV_HT_DISABLE_Pos (16) /*!< TRNG_T::SMODE: INDIV_HT_DISABLE Position*/
#define TRNG_SMODE_INDIV_HT_DISABLE_Msk (0xfful << TRNG_SMODE_INDIV_HT_DISABLE_Pos) /*!< TRNG_T::SMODE: INDIV_HT_DISABLE Mask */
#define TRNG_SMODE_NOISE_COLLECT_Pos (31) /*!< TRNG_T::SMODE: NOISE_COLLECT Position */
#define TRNG_SMODE_NOISE_COLLECT_Msk (0x1ul << TRNG_SMODE_NOISE_COLLECT_Pos) /*!< TRNG_T::SMODE: NOISE_COLLECT Mask */
#define TRNG_STAT_LAST_CMD_Pos (0) /*!< TRNG_T::STAT: LAST_CMD Position */
#define TRNG_STAT_LAST_CMD_Msk (0xful << TRNG_STAT_LAST_CMD_Pos) /*!< TRNG_T::STAT: LAST_CMD Mask */
#define TRNG_STAT_SEC_ALG_Pos (4) /*!< TRNG_T::STAT: SEC_ALG Position */
#define TRNG_STAT_SEC_ALG_Msk (0x1ul << TRNG_STAT_SEC_ALG_Pos) /*!< TRNG_T::STAT: SEC_ALG Mask */
#define TRNG_STAT_NONCE_MODE_Pos (5) /*!< TRNG_T::STAT: NONCE_MODE Position */
#define TRNG_STAT_NONCE_MODE_Msk (0x1ul << TRNG_STAT_NONCE_MODE_Pos) /*!< TRNG_T::STAT: NONCE_MODE Mask */
#define TRNG_STAT_MISSION_MODE_Pos (6) /*!< TRNG_T::STAT: MISSION_MODE Position */
#define TRNG_STAT_MISSION_MODE_Msk (0x1ul << TRNG_STAT_MISSION_MODE_Pos) /*!< TRNG_T::STAT: MISSION_MODE Mask */
#define TRNG_STAT_DRBG_STATE_Pos (7) /*!< TRNG_T::STAT: DRBG_STATE Position */
#define TRNG_STAT_DRBG_STATE_Msk (0x3ul << TRNG_STAT_DRBG_STATE_Pos) /*!< TRNG_T::STAT: DRBG_STATE Mask */
#define TRNG_STAT_STARTUP_TEST_STUCK_Pos (9) /*!< TRNG_T::STAT: STARTUP_TEST_STUCK Position*/
#define TRNG_STAT_STARTUP_TEST_STUCK_Msk (0x1ul << TRNG_STAT_STARTUP_TEST_STUCK_Pos) /*!< TRNG_T::STAT: STARTUP_TEST_STUCK Mask */
#define TRNG_STAT_STARTUP_TEST_IN_PROG_Pos (10) /*!< TRNG_T::STAT: STARTUP_TEST_IN_PROG Position*/
#define TRNG_STAT_STARTUP_TEST_IN_PROG_Msk (0x1ul << TRNG_STAT_STARTUP_TEST_IN_PROG_Pos) /*!< TRNG_T::STAT: STARTUP_TEST_IN_PROG Mask*/
#define TRNG_STAT_BUSY_Pos (31) /*!< TRNG_T::STAT: BUSY Position */
#define TRNG_STAT_BUSY_Msk (0x1ul << TRNG_STAT_BUSY_Pos) /*!< TRNG_T::STAT: BUSY Mask */
#define TRNG_IE_ZEROIZED_Pos (0) /*!< TRNG_T::IE: ZEROIZED Position */
#define TRNG_IE_ZEROIZED_Msk (0x1ul << TRNG_IE_ZEROIZED_Pos) /*!< TRNG_T::IE: ZEROIZED Mask */
#define TRNG_IE_KAT_COMPLETED_Pos (1) /*!< TRNG_T::IE: KAT_COMPLETED Position */
#define TRNG_IE_KAT_COMPLETED_Msk (0x1ul << TRNG_IE_KAT_COMPLETED_Pos) /*!< TRNG_T::IE: KAT_COMPLETED Mask */
#define TRNG_IE_NOISE_RDY_Pos (2) /*!< TRNG_T::IE: NOISE_RDY Position */
#define TRNG_IE_NOISE_RDY_Msk (0x1ul << TRNG_IE_NOISE_RDY_Pos) /*!< TRNG_T::IE: NOISE_RDY Mask */
#define TRNG_IE_ALARMS_Pos (3) /*!< TRNG_T::IE: ALARMS Position */
#define TRNG_IE_ALARMS_Msk (0x1ul << TRNG_IE_ALARMS_Pos) /*!< TRNG_T::IE: ALARMS Mask */
#define TRNG_IE_DONE_Pos (4) /*!< TRNG_T::IE: DONE Position */
#define TRNG_IE_DONE_Msk (0x1ul << TRNG_IE_DONE_Pos) /*!< TRNG_T::IE: DONE Mask */
#define TRNG_IE_GLBL_Pos (31) /*!< TRNG_T::IE: GLBL Position */
#define TRNG_IE_GLBL_Msk (0x1ul << TRNG_IE_GLBL_Pos) /*!< TRNG_T::IE: GLBL Mask */
#define TRNG_ISTAT_ZEROIZED_Pos (0) /*!< TRNG_T::ISTAT: ZEROIZED Position */
#define TRNG_ISTAT_ZEROIZED_Msk (0x1ul << TRNG_ISTAT_ZEROIZED_Pos) /*!< TRNG_T::ISTAT: ZEROIZED Mask */
#define TRNG_ISTAT_KAT_COMPLETED_Pos (1) /*!< TRNG_T::ISTAT: KAT_COMPLETED Position */
#define TRNG_ISTAT_KAT_COMPLETED_Msk (0x1ul << TRNG_ISTAT_KAT_COMPLETED_Pos) /*!< TRNG_T::ISTAT: KAT_COMPLETED Mask */
#define TRNG_ISTAT_NOISE_RDY_Pos (2) /*!< TRNG_T::ISTAT: NOISE_RDY Position */
#define TRNG_ISTAT_NOISE_RDY_Msk (0x1ul << TRNG_ISTAT_NOISE_RDY_Pos) /*!< TRNG_T::ISTAT: NOISE_RDY Mask */
#define TRNG_ISTAT_ALARMS_Pos (3) /*!< TRNG_T::ISTAT: ALARMS Position */
#define TRNG_ISTAT_ALARMS_Msk (0x1ul << TRNG_ISTAT_ALARMS_Pos) /*!< TRNG_T::ISTAT: ALARMS Mask */
#define TRNG_ISTAT_DONE_Pos (4) /*!< TRNG_T::ISTAT: DONE Position */
#define TRNG_ISTAT_DONE_Msk (0x1ul << TRNG_ISTAT_DONE_Pos) /*!< TRNG_T::ISTAT: DONE Mask */
#define TRNG_ALARMS_FAILED_TEST_ID_Pos (0) /*!< TRNG_T::ALARMS: FAILED_TEST_ID Position*/
#define TRNG_ALARMS_FAILED_TEST_ID_Msk (0xful << TRNG_ALARMS_FAILED_TEST_ID_Pos) /*!< TRNG_T::ALARMS: FAILED_TEST_ID Mask */
#define TRNG_ALARMS_ILLEGAL_CMD_SEQ_Pos (4) /*!< TRNG_T::ALARMS: ILLEGAL_CMD_SEQ Position*/
#define TRNG_ALARMS_ILLEGAL_CMD_SEQ_Msk (0x1ul << TRNG_ALARMS_ILLEGAL_CMD_SEQ_Pos) /*!< TRNG_T::ALARMS: ILLEGAL_CMD_SEQ Mask */
#define TRNG_ALARMS_FAILED_SEED_ST_HT_Pos (5) /*!< TRNG_T::ALARMS: FAILED_SEED_ST_HT Position*/
#define TRNG_ALARMS_FAILED_SEED_ST_HT_Msk (0x1ul << TRNG_ALARMS_FAILED_SEED_ST_HT_Pos) /*!< TRNG_T::ALARMS: FAILED_SEED_ST_HT Mask */
#define TRNG_COREKIT_REL_REL_NUM_Pos (0) /*!< TRNG_T::COREKIT_REL: REL_NUM Position */
#define TRNG_COREKIT_REL_REL_NUM_Msk (0xfffful << TRNG_COREKIT_REL_REL_NUM_Pos) /*!< TRNG_T::COREKIT_REL: REL_NUM Mask */
#define TRNG_COREKIT_REL_EXT_VER_Pos (16) /*!< TRNG_T::COREKIT_REL: EXT_VER Position */
#define TRNG_COREKIT_REL_EXT_VER_Msk (0xfful << TRNG_COREKIT_REL_EXT_VER_Pos) /*!< TRNG_T::COREKIT_REL: EXT_VER Mask */
#define TRNG_COREKIT_REL_EXT_ENUM_Pos (28) /*!< TRNG_T::COREKIT_REL: EXT_ENUM Position */
#define TRNG_COREKIT_REL_EXT_ENUM_Msk (0xful << TRNG_COREKIT_REL_EXT_ENUM_Pos) /*!< TRNG_T::COREKIT_REL: EXT_ENUM Mask */
#define TRNG_FEATURES_SECURE_RST_STATE_Pos (0) /*!< TRNG_T::FEATURES: SECURE_RST_STATE Position*/
#define TRNG_FEATURES_SECURE_RST_STATE_Msk (0x1ul << TRNG_FEATURES_SECURE_RST_STATE_Pos) /*!< TRNG_T::FEATURES: SECURE_RST_STATE Mask*/
#define TRNG_FEATURES_DIAG_LEVEL_ST_HLT_Pos (1) /*!< TRNG_T::FEATURES: DIAG_LEVEL_ST_HLT Position*/
#define TRNG_FEATURES_DIAG_LEVEL_ST_HLT_Msk (0x7ul << TRNG_FEATURES_DIAG_LEVEL_ST_HLT_Pos) /*!< TRNG_T::FEATURES: DIAG_LEVEL_ST_HLT Mask*/
#define TRNG_FEATURES_DIAG_LEVEL_CLP800_Pos (4) /*!< TRNG_T::FEATURES: DIAG_LEVEL_CLP800 Position*/
#define TRNG_FEATURES_DIAG_LEVEL_CLP800_Msk (0x7ul << TRNG_FEATURES_DIAG_LEVEL_CLP800_Pos) /*!< TRNG_T::FEATURES: DIAG_LEVEL_CLP800 Mask*/
#define TRNG_FEATURES_DIAG_LEVEL_NS_Pos (7) /*!< TRNG_T::FEATURES: DIAG_LEVEL_NS Position*/
#define TRNG_FEATURES_DIAG_LEVEL_NS_Msk (0x1ul << TRNG_FEATURES_DIAG_LEVEL_NS_Pos) /*!< TRNG_T::FEATURES: DIAG_LEVEL_NS Mask */
#define TRNG_FEATURES_PS_PRESENT_Pos (8) /*!< TRNG_T::FEATURES: PS_PRESENT Position */
#define TRNG_FEATURES_PS_PRESENT_Msk (0x1ul << TRNG_FEATURES_PS_PRESENT_Pos) /*!< TRNG_T::FEATURES: PS_PRESENT Mask */
#define TRNG_FEATURES_AES_256_Pos (9) /*!< TRNG_T::FEATURES: AES_256 Position */
#define TRNG_FEATURES_AES_256_Msk (0x1ul << TRNG_FEATURES_AES_256_Pos) /*!< TRNG_T::FEATURES: AES_256 Mask */
#define TRNG_RAND0_RAND_Pos (0) /*!< TRNG_T::RAND0: RAND Position */
#define TRNG_RAND0_RAND_Msk (0xfffffffful << TRNG_RAND0_RAND_Pos) /*!< TRNG_T::RAND0: RAND Mask */
#define TRNG_RAND1_RAND_Pos (0) /*!< TRNG_T::RAND1: RAND Position */
#define TRNG_RAND1_RAND_Msk (0xfffffffful << TRNG_RAND1_RAND_Pos) /*!< TRNG_T::RAND1: RAND Mask */
#define TRNG_RAND2_RAND_Pos (0) /*!< TRNG_T::RAND2: RAND Position */
#define TRNG_RAND2_RAND_Msk (0xfffffffful << TRNG_RAND2_RAND_Pos) /*!< TRNG_T::RAND2: RAND Mask */
#define TRNG_RAND3_RAND_Pos (0) /*!< TRNG_T::RAND3: RAND Position */
#define TRNG_RAND3_RAND_Msk (0xfffffffful << TRNG_RAND3_RAND_Pos) /*!< TRNG_T::RAND3: RAND Mask */
#define TRNG_NPA_DATA0_NPA_DATA_Pos (0) /*!< TRNG_T::NPA_DATA0: NPA_DATA Position */
#define TRNG_NPA_DATA0_NPA_DATA_Msk (0xfffffffful << TRNG_NPA_DATA0_NPA_DATA_Pos) /*!< TRNG_T::NPA_DATA0: NPA_DATA Mask */
#define TRNG_NPA_DATA1_NPA_DATA_Pos (0) /*!< TRNG_T::NPA_DATA1: NPA_DATA Position */
#define TRNG_NPA_DATA1_NPA_DATA_Msk (0xfffffffful << TRNG_NPA_DATA1_NPA_DATA_Pos) /*!< TRNG_T::NPA_DATA1: NPA_DATA Mask */
#define TRNG_NPA_DATA2_NPA_DATA_Pos (0) /*!< TRNG_T::NPA_DATA2: NPA_DATA Position */
#define TRNG_NPA_DATA2_NPA_DATA_Msk (0xfffffffful << TRNG_NPA_DATA2_NPA_DATA_Pos) /*!< TRNG_T::NPA_DATA2: NPA_DATA Mask */
#define TRNG_NPA_DATA3_NPA_DATA_Pos (0) /*!< TRNG_T::NPA_DATA3: NPA_DATA Position */
#define TRNG_NPA_DATA3_NPA_DATA_Msk (0xfffffffful << TRNG_NPA_DATA3_NPA_DATA_Pos) /*!< TRNG_T::NPA_DATA3: NPA_DATA Mask */
#define TRNG_NPA_DATA4_NPA_DATA_Pos (0) /*!< TRNG_T::NPA_DATA4: NPA_DATA Position */
#define TRNG_NPA_DATA4_NPA_DATA_Msk (0xfffffffful << TRNG_NPA_DATA4_NPA_DATA_Pos) /*!< TRNG_T::NPA_DATA4: NPA_DATA Mask */
#define TRNG_NPA_DATA5_NPA_DATA_Pos (0) /*!< TRNG_T::NPA_DATA5: NPA_DATA Position */
#define TRNG_NPA_DATA5_NPA_DATA_Msk (0xfffffffful << TRNG_NPA_DATA5_NPA_DATA_Pos) /*!< TRNG_T::NPA_DATA5: NPA_DATA Mask */
#define TRNG_NPA_DATA6_NPA_DATA_Pos (0) /*!< TRNG_T::NPA_DATA6: NPA_DATA Position */
#define TRNG_NPA_DATA6_NPA_DATA_Msk (0xfffffffful << TRNG_NPA_DATA6_NPA_DATA_Pos) /*!< TRNG_T::NPA_DATA6: NPA_DATA Mask */
#define TRNG_NPA_DATA7_NPA_DATA_Pos (0) /*!< TRNG_T::NPA_DATA7: NPA_DATA Position */
#define TRNG_NPA_DATA7_NPA_DATA_Msk (0xfffffffful << TRNG_NPA_DATA7_NPA_DATA_Pos) /*!< TRNG_T::NPA_DATA7: NPA_DATA Mask */
#define TRNG_NPA_DATA8_NPA_DATA_Pos (0) /*!< TRNG_T::NPA_DATA8: NPA_DATA Position */
#define TRNG_NPA_DATA8_NPA_DATA_Msk (0xfffffffful << TRNG_NPA_DATA8_NPA_DATA_Pos) /*!< TRNG_T::NPA_DATA8: NPA_DATA Mask */
#define TRNG_NPA_DATA9_NPA_DATA_Pos (0) /*!< TRNG_T::NPA_DATA9: NPA_DATA Position */
#define TRNG_NPA_DATA9_NPA_DATA_Msk (0xfffffffful << TRNG_NPA_DATA9_NPA_DATA_Pos) /*!< TRNG_T::NPA_DATA9: NPA_DATA Mask */
#define TRNG_NPA_DATA10_NPA_DATA_Pos (0) /*!< TRNG_T::NPA_DATA10: NPA_DATA Position */
#define TRNG_NPA_DATA10_NPA_DATA_Msk (0xfffffffful << TRNG_NPA_DATA10_NPA_DATA_Pos) /*!< TRNG_T::NPA_DATA10: NPA_DATA Mask */
#define TRNG_NPA_DATA11_NPA_DATA_Pos (0) /*!< TRNG_T::NPA_DATA11: NPA_DATA Position */
#define TRNG_NPA_DATA11_NPA_DATA_Msk (0xfffffffful << TRNG_NPA_DATA11_NPA_DATA_Pos) /*!< TRNG_T::NPA_DATA11: NPA_DATA Mask */
#define TRNG_NPA_DATA12_NPA_DATA_Pos (0) /*!< TRNG_T::NPA_DATA12: NPA_DATA Position */
#define TRNG_NPA_DATA12_NPA_DATA_Msk (0xfffffffful << TRNG_NPA_DATA12_NPA_DATA_Pos) /*!< TRNG_T::NPA_DATA12: NPA_DATA Mask */
#define TRNG_NPA_DATA13_NPA_DATA_Pos (0) /*!< TRNG_T::NPA_DATA13: NPA_DATA Position */
#define TRNG_NPA_DATA13_NPA_DATA_Msk (0xfffffffful << TRNG_NPA_DATA13_NPA_DATA_Pos) /*!< TRNG_T::NPA_DATA13: NPA_DATA Mask */
#define TRNG_NPA_DATA14_NPA_DATA_Pos (0) /*!< TRNG_T::NPA_DATA14: NPA_DATA Position */
#define TRNG_NPA_DATA14_NPA_DATA_Msk (0xfffffffful << TRNG_NPA_DATA14_NPA_DATA_Pos) /*!< TRNG_T::NPA_DATA14: NPA_DATA Mask */
#define TRNG_NPA_DATA15_NPA_DATA_Pos (0) /*!< TRNG_T::NPA_DATA15: NPA_DATA Position */
#define TRNG_NPA_DATA15_NPA_DATA_Msk (0xfffffffful << TRNG_NPA_DATA15_NPA_DATA_Pos) /*!< TRNG_T::NPA_DATA15: NPA_DATA Mask */
#define TRNG_SEED0_SEED_Pos (0) /*!< TRNG_T::SEED0: SEED Position */
#define TRNG_SEED0_SEED_Msk (0xfffffffful << TRNG_SEED0_SEED_Pos) /*!< TRNG_T::SEED0: SEED Mask */
#define TRNG_SEED1_SEED_Pos (0) /*!< TRNG_T::SEED1: SEED Position */
#define TRNG_SEED1_SEED_Msk (0xfffffffful << TRNG_SEED1_SEED_Pos) /*!< TRNG_T::SEED1: SEED Mask */
#define TRNG_SEED2_SEED_Pos (0) /*!< TRNG_T::SEED2: SEED Position */
#define TRNG_SEED2_SEED_Msk (0xfffffffful << TRNG_SEED2_SEED_Pos) /*!< TRNG_T::SEED2: SEED Mask */
#define TRNG_SEED3_SEED_Pos (0) /*!< TRNG_T::SEED3: SEED Position */
#define TRNG_SEED3_SEED_Msk (0xfffffffful << TRNG_SEED3_SEED_Pos) /*!< TRNG_T::SEED3: SEED Mask */
#define TRNG_SEED4_SEED_Pos (0) /*!< TRNG_T::SEED4: SEED Position */
#define TRNG_SEED4_SEED_Msk (0xfffffffful << TRNG_SEED4_SEED_Pos) /*!< TRNG_T::SEED4: SEED Mask */
#define TRNG_SEED5_SEED_Pos (0) /*!< TRNG_T::SEED5: SEED Position */
#define TRNG_SEED5_SEED_Msk (0xfffffffful << TRNG_SEED5_SEED_Pos) /*!< TRNG_T::SEED5: SEED Mask */
#define TRNG_SEED6_SEED_Pos (0) /*!< TRNG_T::SEED6: SEED Position */
#define TRNG_SEED6_SEED_Msk (0xfffffffful << TRNG_SEED6_SEED_Pos) /*!< TRNG_T::SEED6: SEED Mask */
#define TRNG_SEED7_SEED_Pos (0) /*!< TRNG_T::SEED7: SEED Position */
#define TRNG_SEED7_SEED_Msk (0xfffffffful << TRNG_SEED7_SEED_Pos) /*!< TRNG_T::SEED7: SEED Mask */
#define TRNG_SEED8_SEED_Pos (0) /*!< TRNG_T::SEED8: SEED Position */
#define TRNG_SEED8_SEED_Msk (0xfffffffful << TRNG_SEED8_SEED_Pos) /*!< TRNG_T::SEED8: SEED Mask */
#define TRNG_SEED9_SEED_Pos (0) /*!< TRNG_T::SEED9: SEED Position */
#define TRNG_SEED9_SEED_Msk (0xfffffffful << TRNG_SEED9_SEED_Pos) /*!< TRNG_T::SEED9: SEED Mask */
#define TRNG_SEED10_SEED_Pos (0) /*!< TRNG_T::SEED10: SEED Position */
#define TRNG_SEED10_SEED_Msk (0xfffffffful << TRNG_SEED10_SEED_Pos) /*!< TRNG_T::SEED10: SEED Mask */
#define TRNG_SEED11_SEED_Pos (0) /*!< TRNG_T::SEED11: SEED Position */
#define TRNG_SEED11_SEED_Msk (0xfffffffful << TRNG_SEED11_SEED_Pos) /*!< TRNG_T::SEED11: SEED Mask */
#define TRNG_TIME_TO_SEED_TTS_Pos (0) /*!< TRNG_T::TIME_TO_SEED: TTS Position */
#define TRNG_TIME_TO_SEED_TTS_Msk (0xfffffffful << TRNG_TIME_TO_SEED_TTS_Pos) /*!< TRNG_T::TIME_TO_SEED: TTS Mask */
#define TRNG_BUILD_CFG0_CORE_TYPE_Pos (0) /*!< TRNG_T::BUILD_CFG0: CORE_TYPE Position */
#define TRNG_BUILD_CFG0_CORE_TYPE_Msk (0x3ul << TRNG_BUILD_CFG0_CORE_TYPE_Pos) /*!< TRNG_T::BUILD_CFG0: CORE_TYPE Mask */
#define TRNG_BUILD_CFG0_BG8_Pos (7) /*!< TRNG_T::BUILD_CFG0: BG8 Position */
#define TRNG_BUILD_CFG0_BG8_Msk (0x1ul << TRNG_BUILD_CFG0_BG8_Pos) /*!< TRNG_T::BUILD_CFG0: BG8 Mask */
#define TRNG_BUILD_CFG0_CDC_SYNC_DEPTH_Pos (8) /*!< TRNG_T::BUILD_CFG0: CDC_SYNC_DEPTH Position*/
#define TRNG_BUILD_CFG0_CDC_SYNC_DEPTH_Msk (0x3ul << TRNG_BUILD_CFG0_CDC_SYNC_DEPTH_Pos) /*!< TRNG_T::BUILD_CFG0: CDC_SYNC_DEPTH Mask*/
#define TRNG_BUILD_CFG0_BACKGROUND_NOISE_Pos (10) /*!< TRNG_T::BUILD_CFG0: BACKGROUND_NOISE Position*/
#define TRNG_BUILD_CFG0_BACKGROUND_NOISE_Msk (0x1ul << TRNG_BUILD_CFG0_BACKGROUND_NOISE_Pos) /*!< TRNG_T::BUILD_CFG0: BACKGROUND_NOISE Mask*/
#define TRNG_BUILD_CFG0_EDU_PRESENT_Pos (11) /*!< TRNG_T::BUILD_CFG0: EDU_PRESENT Position*/
#define TRNG_BUILD_CFG0_EDU_PRESENT_Msk (0x1ul << TRNG_BUILD_CFG0_EDU_PRESENT_Pos) /*!< TRNG_T::BUILD_CFG0: EDU_PRESENT Mask */
#define TRNG_BUILD_CFG0_AES_DATAPATH_Pos (12) /*!< TRNG_T::BUILD_CFG0: AES_DATAPATH Position*/
#define TRNG_BUILD_CFG0_AES_DATAPATH_Msk (0x1ul << TRNG_BUILD_CFG0_AES_DATAPATH_Pos) /*!< TRNG_T::BUILD_CFG0: AES_DATAPATH Mask */
#define TRNG_BUILD_CFG0_AES_MAX_KEY_SIZE_Pos (13) /*!< TRNG_T::BUILD_CFG0: AES_MAX_KEY_SIZE Position*/
#define TRNG_BUILD_CFG0_AES_MAX_KEY_SIZE_Msk (0x1ul << TRNG_BUILD_CFG0_AES_MAX_KEY_SIZE_Pos) /*!< TRNG_T::BUILD_CFG0: AES_MAX_KEY_SIZE Mask*/
#define TRNG_BUILD_CFG0_PERSONALIZATION_STR_Pos (14) /*!< TRNG_T::BUILD_CFG0: PERSONALIZATION_STR Position*/
#define TRNG_BUILD_CFG0_PERSONALIZATION_STR_Msk (0x1ul << TRNG_BUILD_CFG0_PERSONALIZATION_STR_Pos) /*!< TRNG_T::BUILD_CFG0: PERSONALIZATION_STR Mask*/
#define TRNG_BUILD_CFG1_NUM_RAW_NOISE_BLKS_Pos (0) /*!< TRNG_T::BUILD_CFG1: NUM_RAW_NOISE_BLKS Position*/
#define TRNG_BUILD_CFG1_NUM_RAW_NOISE_BLKS_Msk (0xfful << TRNG_BUILD_CFG1_NUM_RAW_NOISE_BLKS_Pos) /*!< TRNG_T::BUILD_CFG1: NUM_RAW_NOISE_BLKS Mask*/
#define TRNG_BUILD_CFG1_STICKY_STARTUP_Pos (8) /*!< TRNG_T::BUILD_CFG1: STICKY_STARTUP Position*/
#define TRNG_BUILD_CFG1_STICKY_STARTUP_Msk (0x1ul << TRNG_BUILD_CFG1_STICKY_STARTUP_Pos) /*!< TRNG_T::BUILD_CFG1: STICKY_STARTUP Mask*/
#define TRNG_BUILD_CFG1_AUTO_CORRELATION_TEST_Pos (12) /*!< TRNG_T::BUILD_CFG1: AUTO_CORRELATION_TEST Position*/
#define TRNG_BUILD_CFG1_AUTO_CORRELATION_TEST_Msk (0x1ul << TRNG_BUILD_CFG1_AUTO_CORRELATION_TEST_Pos) /*!< TRNG_T::BUILD_CFG1: AUTO_CORRELATION_TEST Mask*/
#define TRNG_BUILD_CFG1_MONOBIT_TEST_Pos (13) /*!< TRNG_T::BUILD_CFG1: MONOBIT_TEST Position*/
#define TRNG_BUILD_CFG1_MONOBIT_TEST_Msk (0x1ul << TRNG_BUILD_CFG1_MONOBIT_TEST_Pos) /*!< TRNG_T::BUILD_CFG1: MONOBIT_TEST Mask */
#define TRNG_BUILD_CFG1_RUN_TEST_Pos (14) /*!< TRNG_T::BUILD_CFG1: RUN_TEST Position */
#define TRNG_BUILD_CFG1_RUN_TEST_Msk (0x1ul << TRNG_BUILD_CFG1_RUN_TEST_Pos) /*!< TRNG_T::BUILD_CFG1: RUN_TEST Mask */
#define TRNG_BUILD_CFG1_POKER_TEST_Pos (15) /*!< TRNG_T::BUILD_CFG1: POKER_TEST Position*/
#define TRNG_BUILD_CFG1_POKER_TEST_Msk (0x1ul << TRNG_BUILD_CFG1_POKER_TEST_Pos) /*!< TRNG_T::BUILD_CFG1: POKER_TEST Mask */
#define TRNG_BUILD_CFG1_RAW_HT_ADAP_TEST_Pos (16) /*!< TRNG_T::BUILD_CFG1: RAW_HT_ADAP_TEST Position*/
#define TRNG_BUILD_CFG1_RAW_HT_ADAP_TEST_Msk (0x7ul << TRNG_BUILD_CFG1_RAW_HT_ADAP_TEST_Pos) /*!< TRNG_T::BUILD_CFG1: RAW_HT_ADAP_TEST Mask*/
#define TRNG_BUILD_CFG1_RAW_HT_REP_TEST_Pos (19) /*!< TRNG_T::BUILD_CFG1: RAW_HT_REP_TEST Position*/
#define TRNG_BUILD_CFG1_RAW_HT_REP_TEST_Msk (0x1ul << TRNG_BUILD_CFG1_RAW_HT_REP_TEST_Pos) /*!< TRNG_T::BUILD_CFG1: RAW_HT_REP_TEST Mask*/
#define TRNG_BUILD_CFG1_ENT_SRC_REP_SMPL_SIZE_Pos (20) /*!< TRNG_T::BUILD_CFG1: ENT_SRC_REP_SMPL_SIZE Position*/
#define TRNG_BUILD_CFG1_ENT_SRC_REP_SMPL_SIZE_Msk (0x7ul << TRNG_BUILD_CFG1_ENT_SRC_REP_SMPL_SIZE_Pos) /*!< TRNG_T::BUILD_CFG1: ENT_SRC_REP_SMPL_SIZE Mask*/
#define TRNG_BUILD_CFG1_ENT_SRC_REP_TEST_Pos (23) /*!< TRNG_T::BUILD_CFG1: ENT_SRC_REP_TEST Position*/
#define TRNG_BUILD_CFG1_ENT_SRC_REP_TEST_Msk (0x1ul << TRNG_BUILD_CFG1_ENT_SRC_REP_TEST_Pos) /*!< TRNG_T::BUILD_CFG1: ENT_SRC_REP_TEST Mask*/
#define TRNG_BUILD_CFG1_ENT_SRC_REP_MIN_ENTROPY_Pos (24) /*!< TRNG_T::BUILD_CFG1: ENT_SRC_REP_MIN_ENTROPY Position*/
#define TRNG_BUILD_CFG1_ENT_SRC_REP_MIN_ENTROPY_Msk (0x7ful << TRNG_BUILD_CFG1_ENT_SRC_REP_MIN_ENTROPY_Pos) /*!< TRNG_T::BUILD_CFG1: ENT_SRC_REP_MIN_ENTROPY Mask*/
/**@}*/ /* TRNG_CONST */
/**@}*/ /* end of TRNG register group */
/**@}*/ /* end of REGISTER group */
#if defined ( __CC_ARM )
#pragma no_anon_unions
#endif
#endif /* __TRNG_REG_H__ */

1061
bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/uart_reg.h Normal file
View File

File diff suppressed because it is too large Load Diff

3918
bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/umctl2_reg.h Normal file
View File

File diff suppressed because it is too large Load Diff

796
bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/usbh_reg.h Normal file
View File

@ -0,0 +1,796 @@
/**************************************************************************//**
* @file usbh_reg.h
* @brief USBH register definition header file
*
* SPDX-License-Identifier: Apache-2.0
* @copyright (C) 2021 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __USBH_REG_H__
#define __USBH_REG_H__
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
/**
@addtogroup REGISTER Control Register
@{
*/
/**
@addtogroup USBH USB Host Controller(USBH)
Memory Mapped Structure for USBH Controller
@{ */
typedef struct
{
/**
* @var USBH_T::HcRevision
* Offset: 0x00 Host Controller Revision Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |REV |Revision Number
* | | |Indicates the Open HCI Specification revision number implemented by the Hardware
* | | |Host Controller supports 1.1 specification.
* | | |(X.Y = XYh).
* @var USBH_T::HcControl
* Offset: 0x04 Host Controller Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[1:0] |CBSR |Control Bulk Service Ratio
* | | |This specifies the service ratio between Control and Bulk EDs
* | | |Before processing any of the non-periodic lists, HC must compare the ratio specified with its internal count on how many nonempty Control EDs have been processed, in determining whether to continue serving another Control ED or switching to Bulk EDs
* | | |The internal count will be retained when crossing the frame boundary
* | | |In case of reset, HCD is responsible for restoring this value.
* | | |00 = Number of Control EDs over Bulk EDs served is 1:1.
* | | |01 = Number of Control EDs over Bulk EDs served is 2:1.
* | | |10 = Number of Control EDs over Bulk EDs served is 3:1.
* | | |11 = Number of Control EDs over Bulk EDs served is 4:1.
* |[2] |PLE |Periodic List Enable Bit
* | | |When set, this bit enables processing of the Periodic (interrupt and isochronous) list
* | | |The Host Controller checks this bit prior to attempting any periodic transfers in a frame.
* | | |0 = Processing of the Periodic (Interrupt and Isochronous) list after next SOF (Start-Of-Frame) Disabled.
* | | |1 = Processing of the Periodic (Interrupt and Isochronous) list in the next frame Enabled.
* | | |Note: To enable the processing of the Isochronous list, user has to set both PLE and IE (HcControl[3]) high.
* |[3] |IE |Isochronous List Enable Bit
* | | |Both ISOEn and PLE (HcControl[2]) high enables Host Controller to process the Isochronous list
* | | |Either ISOEn or PLE (HcControl[2]) is low disables Host Controller to process the Isochronous list.
* | | |0 = Processing of the Isochronous list after next SOF (Start-Of-Frame) Disabled.
* | | |1 = Processing of the Isochronous list in the next frame Enabled, if the PLE (HcControl[2]) is high, too.
* |[4] |CLE |Control List Enable Bit
* | | |0 = Processing of the Control list after next SOF (Start-Of-Frame) Disabled.
* | | |1 = Processing of the Control list in the next frame Enabled.
* |[5] |BLE |Bulk List Enable Bit
* | | |0 = Processing of the Bulk list after next SOF (Start-Of-Frame) Disabled.
* | | |1 = Processing of the Bulk list in the next frame Enabled.
* |[7:6] |HCFS |Host Controller Functional State
* | | |This field sets the Host Controller state
* | | |The Controller may force a state change from USBSUSPEND to USBRESUME after detecting resume signaling from a downstream port
* | | |States are:
* | | |00 = USBSUSPEND.
* | | |01 = USBOPERATIONAL.
* | | |10 = USBRESUME.
* | | |11 = USBRESET.
* @var USBH_T::HcCommandStatus
* Offset: 0x08 Host Controller Command Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |HCR |Host Controller Reset
* | | |This bit is set to initiate the software reset of Host Controller
* | | |This bit is cleared by the Host Controller, upon completed of the reset operation.
* | | |This bit, when set, didn't reset the Root Hub and no subsequent reset signaling be asserted to its downstream ports.
* | | |0 = Host Controller is not in software reset state.
* | | |1 = Host Controller is in software reset state.
* |[1] |CLF |Control List Filled
* | | |Set high to indicate there is an active TD on the Control List
* | | |It may be set by either software or the Host Controller and cleared by the Host Controller each time it begins processing the head of the Control List.
* | | |0 = No active TD found or Host Controller begins to process the head of the Control list.
* | | |1 = An active TD added or found on the Control list.
* |[2] |BLF |Bulk List Filled
* | | |Set high to indicate there is an active TD on the Bulk list
* | | |This bit may be set by either software or the Host Controller and cleared by the Host Controller each time it begins processing the head of the Bulk list.
* | | |0 = No active TD found or Host Controller begins to process the head of the Bulk list.
* | | |1 = An active TD added or found on the Bulk list.
* |[17:16] |SOC |Schedule Overrun Count (Read Only)
* | | |These bits are incremented on each scheduling overrun error
* | | |It is initialized to 00b and wraps around at 11b
* | | |This will be incremented when a scheduling overrun is detected even if SO (HcInterruptStatus[0]) has already been set.
* @var USBH_T::HcInterruptStatus
* Offset: 0x0C Host Controller Interrupt Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |SO |Scheduling Overrun
* | | |Set when the List Processor determines a Schedule Overrun has occurred.
* | | |0 = Schedule Overrun didn't occur.
* | | |1 = Schedule Overrun has occurred.
* | | |Note: This bit is cleared by writing 1 to it.
* |[1] |WDH |Write Back Done Head
* | | |Set after the Host Controller has written HcDoneHead to HccaDoneHead
* | | |Further updates of the HccaDoneHead will not occur until this bit has been cleared.
* | | |0 = Host Controller didn't update HccaDoneHead.
* | | |1 = Host Controller has written HcDoneHead to HccaDoneHead.
* | | |Note: This bit is cleared by writing 1 to it.
* |[2] |SF |Start of Frame
* | | |Set when the Frame Management functional block signals a 'Start of Frame' event
* | | |Host Control generates a SOF token at the same time.
* | | |0 = Not the start of a frame.
* | | |1 = Indicate the start of a frame and Host Controller generates a SOF token.
* | | |Note: This bit is cleared by writing 1 to it.
* |[3] |RD |Resume Detected
* | | |Set when Host Controller detects resume signaling on a downstream port.
* | | |0 = No resume signaling detected on a downstream port.
* | | |1 = Resume signaling detected on a downstream port.
* | | |Note: This bit is cleared by writing 1 to it.
* |[5] |FNO |Frame Number Overflow
* | | |This bit is set when bit 15 of Frame Number changes from 1 to 0 or from 0 to 1.
* | | |0 = The bit 15 of Frame Number didn't change.
* | | |1 = The bit 15 of Frame Number changes from 1 to 0 or from 0 to 1.
* | | |Note: This bit is cleared by writing 1 to it.
* |[6] |RHSC |Root Hub Status Change
* | | |This bit is set when the content of HcRhStatus or the content of HcRhPortStatus register has changed.
* | | |0 = The content of HcRhStatus and the content of HcRhPortStatus register didn't change.
* | | |1 = The content of HcRhStatus or the content of HcRhPortStatus register has changed.
* | | |Note: This bit is cleared by writing h'1f to HcRhPortStatus6[20:16].
* @var USBH_T::HcInterruptEnable
* Offset: 0x10 Host Controller Interrupt Enable Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |SO |Scheduling Overrun Enable Bit
* | | |Write Operation:
* | | |0 = No effect.
* | | |1 = Interrupt generation due to SO (HcInterruptStatus[0]) Enabled.
* | | |Read Operation:
* | | |0 = Interrupt generation due to SO (HcInterruptStatus[0]) Disabled.
* | | |1 = Interrupt generation due to SO (HcInterruptStatus[0]) Enabled.
* |[1] |WDH |Write Back Done Head Enable Bit
* | | |Write Operation:
* | | |0 = No effect.
* | | |1 = Interrupt generation due to WDH (HcInterruptStatus[1]) Enabled.
* | | |Read Operation:
* | | |0 = Interrupt generation due to WDH (HcInterruptStatus[1]) Disabled.
* | | |1 = Interrupt generation due to WDH (HcInterruptStatus[1]) Enabled.
* |[2] |SF |Start of Frame Enable Bit
* | | |Write Operation:
* | | |0 = No effect.
* | | |1 = Interrupt generation due to SF (HcInterruptStatus[2]) Enabled.
* | | |Read Operation:
* | | |0 = Interrupt generation due to SF (HcInterruptStatus[2]) Disabled.
* | | |1 = Interrupt generation due to SF (HcInterruptStatus[2]) Enabled.
* |[3] |RD |Resume Detected Enable Bit
* | | |Write Operation:
* | | |0 = No effect.
* | | |1 = Interrupt generation due to RD (HcInterruptStatus[3]) Enabled.
* | | |Read Operation:
* | | |0 = Interrupt generation due to RD (HcInterruptStatus[3]) Disabled.
* | | |1 = Interrupt generation due to RD (HcInterruptStatus[3]) Enabled.
* |[5] |FNO |Frame Number Overflow Enable Bit
* | | |Write Operation:
* | | |0 = No effect.
* | | |1 = Interrupt generation due to FNO (HcInterruptStatus[5]) Enabled.
* | | |Read Operation:
* | | |0 = Interrupt generation due to FNO (HcInterruptStatus[5]) Disabled.
* | | |1 = Interrupt generation due to FNO (HcInterruptStatus[5]) Enabled.
* |[6] |RHSC |Root Hub Status Change Enable Bit
* | | |Write Operation:
* | | |0 = No effect.
* | | |1 = Interrupt generation due to RHSC (HcInterruptStatus[6]) Enabled.
* | | |Read Operation:
* | | |0 = Interrupt generation due to RHSC (HcInterruptStatus[6]) Disabled.
* | | |1 = Interrupt generation due to RHSC (HcInterruptStatus[6]) Enabled.
* |[31] |MIE |Master Interrupt Enable Bit
* | | |This bit is a global interrupt enable
* | | |A write of '1' allows interrupts to be enabled via the specific enable bits listed above.
* | | |Write Operation:
* | | |0 = No effect.
* | | |1 = Interrupt generation due to RHSC (HcInterruptStatus[6]), FNO (HcInterruptStatus[5]), RD (HcInterruptStatus[3]), SF (HcInterruptStatus[2]), WDH (HcInterruptStatus[1]) or SO (HcInterruptStatus[0]) Enabled if the corresponding bit in HcInterruptEnable is high.
* | | |Read Operation:
* | | |0 = Interrupt generation due to RHSC (HcInterruptStatus[6]), FNO (HcInterruptStatus[5]), RD (HcInterruptStatus[3]), SF (HcInterruptStatus[2]), WDH (HcInterruptStatus[1]) or SO (HcInterruptStatus[0]) Disabled even if the corresponding bit in HcInterruptEnable is high.
* | | |1 = Interrupt generation due to RHSC (HcInterruptStatus[6]), FNO (HcInterruptStatus[5]), RD (HcInterruptStatus[3]), SF (HcInterruptStatus[2]), WDH (HcInterruptStatus[1]) or SO (HcInterruptStatus[0]) Enabled if the corresponding bit in HcInterruptEnable is high.
* @var USBH_T::HcInterruptDisable
* Offset: 0x14 Host Controller Interrupt Disable Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |SO |Scheduling Overrun Disable Bit
* | | |Write Operation:
* | | |0 = No effect.
* | | |1 = Interrupt generation due to SO (HcInterruptStatus[0]) Disabled.
* | | |Read Operation:
* | | |0 = Interrupt generation due to SO (HcInterruptStatus[0]) Disabled.
* | | |1 = Interrupt generation due to SO (HcInterruptStatus[0]) Enabled.
* |[1] |WDH |Write Back Done Head Disable Bit
* | | |Write Operation:
* | | |0 = No effect.
* | | |1 = Interrupt generation due to WDH (HcInterruptStatus[1]) Disabled.
* | | |Read Operation:
* | | |0 = Interrupt generation due to WDH (HcInterruptStatus[1]) Disabled.
* | | |1 = Interrupt generation due to WDH (HcInterruptStatus[1]) Enabled.
* |[2] |SF |Start of Frame Disable Bit
* | | |Write Operation:
* | | |0 = No effect.
* | | |1 = Interrupt generation due to SF (HcInterruptStatus[2]) Disabled.
* | | |Read Operation:
* | | |0 = Interrupt generation due to SF (HcInterruptStatus[2]) Disabled.
* | | |1 = Interrupt generation due to SF (HcInterruptStatus[2]) Enabled.
* |[3] |RD |Resume Detected Disable Bit
* | | |Write Operation:
* | | |0 = No effect.
* | | |1 = Interrupt generation due to RD (HcInterruptStatus[3]) Disabled.
* | | |Read Operation:
* | | |0 = Interrupt generation due to RD (HcInterruptStatus[3]) Disabled.
* | | |1 = Interrupt generation due to RD (HcInterruptStatus[3]) Enabled.
* |[5] |FNO |Frame Number Overflow Disable Bit
* | | |Write Operation:
* | | |0 = No effect.
* | | |1 = Interrupt generation due to FNO (HcInterruptStatus[5]) Disabled.
* | | |Read Operation:
* | | |0 = Interrupt generation due to FNO (HcInterruptStatus[5]) Disabled.
* | | |1 = Interrupt generation due to FNO (HcInterruptStatus[5]) Enabled.
* |[6] |RHSC |Root Hub Status Change Disable Bit
* | | |Write Operation:
* | | |0 = No effect.
* | | |1 = Interrupt generation due to RHSC (HcInterruptStatus[6]) Disabled.
* | | |Read Operation:
* | | |0 = Interrupt generation due to RHSC (HcInterruptStatus[6]) Disabled.
* | | |1 = Interrupt generation due to RHSC (HcInterruptStatus[6]) Enabled.
* |[31] |MIE |Master Interrupt Disable Bit
* | | |Global interrupt disable. Writing '1' to disable all interrupts.
* | | |Write Operation:
* | | |0 = No effect.
* | | |1 = Interrupt generation due to RHSC (HcInterruptStatus[6]), FNO (HcInterruptStatus[5]), RD (HcInterruptStatus[3]), SF (HcInterruptStatus[2]), WDH (HcInterruptStatus[1]) or SO (HcInterruptStatus[0]) Disabled if the corresponding bit in HcInterruptEnable is high.
* | | |Read Operation:
* | | |0 = Interrupt generation due to RHSC (HcInterruptStatus[6]), FNO (HcInterruptStatus[5]), RD (HcInterruptStatus[3]), SF (HcInterruptStatus[2]), WDH (HcInterruptStatus[1]) or SO (HcInterruptStatus[0]) Disabled even if the corresponding bit in HcInterruptEnable is high.
* | | |1 = Interrupt generation due to RHSC (HcInterruptStatus[6]), FNO (HcInterruptStatus[5]), RD (HcInterruptStatus[3]), SF (HcInterruptStatus[2]), WDH (HcInterruptStatus[1]) or SO (HcInterruptStatus[0]) Enabled if the corresponding bit in HcInterruptEnable is high.
* @var USBH_T::HcHCCA
* Offset: 0x18 Host Controller Communication Area Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:8] |HCCA |Host Controller Communication Area
* | | |Pointer to indicate base address of the Host Controller Communication Area (HCCA).
* @var USBH_T::HcPeriodCurrentED
* Offset: 0x1C Host Controller Period Current ED Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:4] |PCED |Periodic Current ED
* | | |Pointer to indicate physical address of the current Isochronous or Interrupt Endpoint Descriptor.
* @var USBH_T::HcControlHeadED
* Offset: 0x20 Host Controller Control Head ED Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:4] |CHED |Control Head ED
* | | |Pointer to indicate physical address of the first Endpoint Descriptor of the Control list.
* @var USBH_T::HcControlCurrentED
* Offset: 0x24 Host Controller Control Current ED Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:4] |CCED |Control Current Head ED
* | | |Pointer to indicate the physical address of the current Endpoint Descriptor of the Control list.
* @var USBH_T::HcBulkHeadED
* Offset: 0x28 Host Controller Bulk Head ED Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:4] |BHED |Bulk Head ED
* | | |Pointer to indicate the physical address of the first Endpoint Descriptor of the Bulk list.
* @var USBH_T::HcBulkCurrentED
* Offset: 0x2C Host Controller Bulk Current ED Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:4] |BCED |Bulk Current Head ED
* | | |Pointer to indicate the physical address of the current endpoint of the Bulk list.
* @var USBH_T::HcDoneHead
* Offset: 0x30 Host Controller Done Head Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:4] |DH |Done Head
* | | |Pointer to indicate the physical address of the last completed Transfer Descriptor that was added to the Done queue.
* @var USBH_T::HcFmInterval
* Offset: 0x34 Host Controller Frame Interval Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[13:0] |FI |Frame Interval
* | | |This field specifies the length of a frame as (bit times - 1)
* | | |For 12,000 bit times in a frame, a value of 11,999 is stored here.
* |[29:16] |FSMPS |FS Largest Data Packet
* | | |This field specifies a value that is loaded into the Largest Data Packet Counter at the beginning of each frame.
* |[31] |FIT |Frame Interval Toggle
* | | |This bit is toggled by Host Controller Driver when it loads a new value into FI (HcFmInterval[13:0]).
* | | |0 = Host Controller Driver didn't load new value into FI (HcFmInterval[13:0]).
* | | |1 = Host Controller Driver loads a new value into FI (HcFmInterval[13:0]).
* @var USBH_T::HcFmRemaining
* Offset: 0x38 Host Controller Frame Remaining Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[13:0] |FR |Frame Remaining
* | | |When the Host Controller is in the USBOPERATIONAL state, this 14-bit field decrements each 12 MHz clock period
* | | |When the count reaches 0, (end of frame) the counter reloads with Frame Interval
* | | |In addition, the counter loads when the Host Controller transitions into USBOPERATIONAL.
* |[31] |FRT |Frame Remaining Toggle
* | | |This bit is loaded from the FIT (HcFmInterval[31]) whenever FR (HcFmRemaining[13:0]) reaches 0.
* @var USBH_T::HcFmNumber
* Offset: 0x3C Host Controller Frame Number Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |FN |Frame Number
* | | |This 16-bit incrementing counter field is incremented coincident with the re-load of FR (HcFmRemaining[13:0])
* | | |The count rolls over from 'FFFFh' to '0h.'
* @var USBH_T::HcPeriodicStart
* Offset: 0x40 Host Controller Periodic Start Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[13:0] |PS |Periodic Start
* | | |This field contains a value used by the List Processor to determine where in a frame the Periodic List processing must begin.
* @var USBH_T::HcLSThreshold
* Offset: 0x44 Host Controller Low-speed Threshold Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[11:0] |LST |Low-speed Threshold
* | | |This field contains a value which is compared to the FR (HcFmRemaining[13:0]) field prior to initiating a Low-speed transaction
* | | |The transaction is started only if FR (HcFmRemaining[13:0]) >= this field
* | | |The value is calculated by Host Controller Driver with the consideration of transmission and setup overhead.
* @var USBH_T::HcRhDescriptorA
* Offset: 0x48 Host Controller Root Hub Descriptor A Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |NDP |Number Downstream Ports
* | | |USB host control supports two downstream ports and only one port is available in this series of chip.
* | | |Note: NDP = 6 in this series of chip.
* |[8] |PSM |Power Switching Mode
* | | |This bit is used to specify how the power switching of the Root Hub ports is controlled.
* | | |0 = Global switching.
* | | |1 = Individual switching.
* |[11] |OCPM |Overcurrent Protection Mode
* | | |This bit describes how the overcurrent status for the Root Hub ports reported
* | | |This bit is only valid when NOCP (HcRhDescriptorA[12]) is cleared.
* | | |0 = Global overcurrent.
* | | |1 = Individual overcurrent.
* |[12] |NOCP |No overcurrent Protection
* | | |This bit describes how the overcurrent status for the Root Hub ports reported.
* | | |0 = Overcurrent status is reported.
* | | |1 = Overcurrent status is not reported.
* @var USBH_T::HcRhDescriptorB
* Offset: 0x4C Host Controller Root Hub Descriptor B Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:16] |PPCM |Port Power Control Mask
* | | |Global power switching
* | | |This field is only valid if PowerSwitchingMode is set (individual port switching)
* | | |When set, the port only responds to individual port power switching commands (Set/Clear Port Power)
* | | |When cleared, the port only responds to global power switching commands (Set/Clear Global Power).
* | | |0 = Port power controlled by global power switching.
* | | |1 = Port power controlled by port power switching.
* | | |Note: PPCM[15:2] and PPCM[0] are reserved.
* @var USBH_T::HcRhStatus
* Offset: 0x50 Host Controller Root Hub Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |LPS |Clear Global Power
* | | |In global power mode (PSM (HcRhDescriptorA[8]) = 0), this bit is written to one to clear all ports' power.
* | | |This bit always read as zero.
* | | |Write Operation:
* | | |0 = No effect.
* | | |1 = Clear global power.
* |[1] |OCI |Overcurrent Indicator (Read Only)
* | | |This bit reflects the state of the overcurrent status pin
* | | |This field is only valid if NOCP (HcRhDescriptorA[12]) and OCPM (HcRhDescriptorA[11]) are cleared.
* | | |0 = No overcurrent condition.
* | | |1 = Overcurrent condition.
* |[15] |DRWE |Device Remote Wakeup Enable Bit
* | | |This bit controls if port's Connect Status Change as a remote wake-up event.
* | | |Write Operation:
* | | |0 = No effect.
* | | |1 = Connect Status Change as a remote wake-up event Enabled.
* | | |Read Operation:
* | | |0 = Connect Status Change as a remote wake-up event Disabled.
* | | |1 = Connect Status Change as a remote wake-up event Enabled.
* |[16] |LPSC |Set Global Power
* | | |In global power mode (PSM (HcRhDescriptorA[8]) = 0), this bit is written to one to enable power to all ports.
* | | |This bit always read as zero.
* | | |Write Operation:
* | | |0 = No effect.
* | | |1 = Set global power.
* |[17] |OCIC |Overcurrent Indicator Change
* | | |This bit is set by hardware when a change has occurred in OCI (HcRhStatus[1]).
* | | |Write 1 to clear this bit to zero.
* | | |0 = OCI (HcRhStatus[1]) didn't change.
* | | |1 = OCI (HcRhStatus[1]) change.
* |[31] |CRWE |Clear Remote Wake-up Enable Bit
* | | |This bit is use to clear DRWE (HcRhStatus[15]).
* | | |This bit always read as zero.
* | | |Write Operation:
* | | |0 = No effect.
* | | |1 = Clear DRWE (HcRhStatus[15]).
* @var USBH_T::HcRhPortStatus
* Offset: 0x54 Host Controller Root Hub Port Status
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |CCS |Current Connect Status or Clear Port Enable
* | | |Write Operation:
* | | |0 = No effect.
* | | |1 = Clear port enable.
* | | |Read Operation:
* | | |0 = No device connected.
* | | |1 = Device connected.
* |[1] |PES |Port Enable Status or Set Port Enable
* | | |Write Operation:
* | | |0 = No effect.
* | | |1 = Set port enable.
* | | |Read Operation:
* | | |0 = Port Disabled.
* | | |1 = Port Enabled.
* |[2] |PSS |Port Suspend Status or Set Port Suspend
* | | |This bit indicates the port is suspended
* | | |Write Operation:
* | | |0 = No effect.
* | | |1 = Set port suspend.
* | | |Read Operation:
* | | |0 = Port is not suspended.
* | | |1 = Port is selectively suspended.
* |[3] |POCI |Port overcurrent Indicator or Clear Port Suspend
* | | |This bit reflects the state of the overcurrent status pin dedicated to this port
* | | |This field is only valid if NOCP (HcRhDescriptorA[12]) is cleared and OCPM (HcRhDescriptorA[11]) is set.
* | | |This bit is also used to initiate the selective result sequence for the port.
* | | |Write Operation:
* | | |0 = No effect.
* | | |1 = Clear port suspend.
* | | |Read Operation:
* | | |0 = No overcurrent condition.
* | | |1 = Overcurrent condition.
* |[4] |PRS |Port Reset Status or Set Port Reset
* | | |This bit reflects the reset state of the port.
* | | |Write Operation:
* | | |0 = No effect.
* | | |1 = Set port reset.
* | | |Read Operation
* | | |0 = Port reset signal is not active.
* | | |1 = Port reset signal is active.
* |[8] |PPS |Port Power Status or Set Port Power
* | | |This bit reflects the power state of the port regardless of the power switching mode.
* | | |Write Operation:
* | | |0 = No effect.
* | | |1 = Port Power Enabled.
* | | |Read Operation:
* | | |0 = Port power is Disabled.
* | | |1 = Port power is Enabled.
* |[9] |LSDA |Low Speed Device Attached or Clear Port Power
* | | |This bit defines the speed (and bus idle) of the attached device
* | | |It is only valid when CCS (HcRhPortStatus[0]) is set.
* | | |This bit is also used to clear port power.
* | | |Write Operation:
* | | |0 = No effect.
* | | |1 = Clear PPS (HcRhPortStatus[8]).
* | | |Read Operation:
* | | |0 = Full Speed device.
* | | |1 = Low-speed device.
* |[16] |CSC |Connect Status Change
* | | |This bit indicates connect or disconnect event has been detected (CCS (HcRhPortStatus[0]) changed).
* | | |Write 1 to clear this bit to zero.
* | | |0 = No connect/disconnect event (CCS (HcRhPortStatus[0]) didn't change).
* | | |1 = Hardware detection of connect/disconnect event (CCS (HcRhPortStatus[0]) changed).
* |[17] |PESC |Port Enable Status Change
* | | |This bit indicates that the port has been disabled (PES (HcRhPortStatus6[1]) cleared) due to a hardware event.
* | | |Write 1 to clear this bit to zero.
* | | |0 = PES (HcRhPortStatus[1]) didn't change.
* | | |1 = PES (HcRhPortStatus[1]) changed.
* |[18] |PSSC |Port Suspend Status Change
* | | |This bit indicates the completion of the selective resume sequence for the port.
* | | |Write 1 to clear this bit to zero.
* | | |0 = Port resume is not completed.
* | | |1 = Port resume completed.
* |[19] |OCIC |Port overcurrent Indicator Change
* | | |This bit is set when POCI (HcRhPortStatus[3]) changes.
* | | |Write 1 to clear this bit to zero.
* | | |0 = POCI (HcRhPortStatus[3]) didn't change.
* | | |1 = POCI (HcRhPortStatus[3]) changes.
* |[20] |PRSC |Port Reset Status Change
* | | |This bit indicates that the port reset signal has completed.
* | | |Write 1 to clear this bit to zero.
* | | |0 = Port reset is not complete.
* | | |1 = Port reset is complete.
* @var USBH_T::HcPhyControl
* Offset: 0x200 Host Controller PHY Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[1] |ABORT |AHB Bus ERROR Response
* | | |This bit indicates there is an ERROR response received in AHB bus.
* | | |0 = No ERROR response received.
* | | |1 = ERROR response received.
* | | |Note: This bit is cleared by writing 1 to it.
* |[3] |OCAL |Overcurrent Active Low
* | | |This bit controls the polarity of overcurrent flag from external power IC.
* | | |0 = Overcurrent flag is high active.
* | | |1 = Overcurrent flag is low active.
* |[4] |PPCAL |Port Power Control Active Low
* | | |This bit controls the polarity of port power control to external power IC.
* | | |0 = Port power control is high active.
* | | |1 = Port power control is low active.
* |[16] |DPRT1 |Disable Port 1
* | | |This bit controls if the connection between USB host controller and transceiver of port 1 is disabled
* | | |If the connection is disabled, the USB host controller will not recognize any event of USB bus.
* | | |Set this bit high, the transceiver of port 1 will also be forced into the standby mode no matter what USB host controller operation is.
* | | |0 = The connection between USB host controller and transceiver of port 1 Enabled.
* | | |1 = The connection between USB host controller and transceiver of port 1 Disabled and the transceiver of port 1 will also be forced into the standby mode.
*/
__I uint32_t HcRevision; /*!< [0x0000] Host Controller Revision Register */
__IO uint32_t HcControl; /*!< [0x0004] Host Controller Control Register */
__IO uint32_t HcCommandStatus; /*!< [0x0008] Host Controller Command Status Register */
__IO uint32_t HcInterruptStatus; /*!< [0x000c] Host Controller Interrupt Status Register */
__IO uint32_t HcInterruptEnable; /*!< [0x0010] Host Controller Interrupt Enable Register */
__IO uint32_t HcInterruptDisable; /*!< [0x0014] Host Controller Interrupt Disable Register */
__IO uint32_t HcHCCA; /*!< [0x0018] Host Controller Communication Area Register */
__IO uint32_t HcPeriodCurrentED; /*!< [0x001c] Host Controller Period Current ED Register */
__IO uint32_t HcControlHeadED; /*!< [0x0020] Host Controller Control Head ED Register */
__IO uint32_t HcControlCurrentED; /*!< [0x0024] Host Controller Control Current ED Register */
__IO uint32_t HcBulkHeadED; /*!< [0x0028] Host Controller Bulk Head ED Register */
__IO uint32_t HcBulkCurrentED; /*!< [0x002c] Host Controller Bulk Current ED Register */
__IO uint32_t HcDoneHead; /*!< [0x0030] Host Controller Done Head Register */
__IO uint32_t HcFmInterval; /*!< [0x0034] Host Controller Frame Interval Register */
__I uint32_t HcFmRemaining; /*!< [0x0038] Host Controller Frame Remaining Register */
__I uint32_t HcFmNumber; /*!< [0x003c] Host Controller Frame Number Register */
__IO uint32_t HcPeriodicStart; /*!< [0x0040] Host Controller Periodic Start Register */
__IO uint32_t HcLSThreshold; /*!< [0x0044] Host Controller Low-speed Threshold Register */
__IO uint32_t HcRhDescriptorA; /*!< [0x0048] Host Controller Root Hub Descriptor A Register */
__IO uint32_t HcRhDescriptorB; /*!< [0x004c] Host Controller Root Hub Descriptor B Register */
__IO uint32_t HcRhStatus; /*!< [0x0050] Host Controller Root Hub Status Register */
__IO uint32_t HcRhPortStatus[1]; /*!< [0x0054] Host Controller Root Hub Port Status */
__I uint32_t RESERVE0[106];
__IO uint32_t HcPhyControl; /*!< [0x0200] Host Controller PHY Control Register */
} USBH_T;
/**
@addtogroup USBH_CONST USBH Bit Field Definition
Constant Definitions for USBH Controller
@{ */
#define USBH_HcRevision_REV_Pos (0) /*!< USBH_T::HcRevision: REV Position */
#define USBH_HcRevision_REV_Msk (0xfful << USBH_HcRevision_REV_Pos) /*!< USBH_T::HcRevision: REV Mask */
#define USBH_HcControl_CBSR_Pos (0) /*!< USBH_T::HcControl: CBSR Position */
#define USBH_HcControl_CBSR_Msk (0x3ul << USBH_HcControl_CBSR_Pos) /*!< USBH_T::HcControl: CBSR Mask */
#define USBH_HcControl_PLE_Pos (2) /*!< USBH_T::HcControl: PLE Position */
#define USBH_HcControl_PLE_Msk (0x1ul << USBH_HcControl_PLE_Pos) /*!< USBH_T::HcControl: PLE Mask */
#define USBH_HcControl_IE_Pos (3) /*!< USBH_T::HcControl: IE Position */
#define USBH_HcControl_IE_Msk (0x1ul << USBH_HcControl_IE_Pos) /*!< USBH_T::HcControl: IE Mask */
#define USBH_HcControl_CLE_Pos (4) /*!< USBH_T::HcControl: CLE Position */
#define USBH_HcControl_CLE_Msk (0x1ul << USBH_HcControl_CLE_Pos) /*!< USBH_T::HcControl: CLE Mask */
#define USBH_HcControl_BLE_Pos (5) /*!< USBH_T::HcControl: BLE Position */
#define USBH_HcControl_BLE_Msk (0x1ul << USBH_HcControl_BLE_Pos) /*!< USBH_T::HcControl: BLE Mask */
#define USBH_HcControl_HCFS_Pos (6) /*!< USBH_T::HcControl: HCFS Position */
#define USBH_HcControl_HCFS_Msk (0x3ul << USBH_HcControl_HCFS_Pos) /*!< USBH_T::HcControl: HCFS Mask */
#define USBH_HcCommandStatus_HCR_Pos (0) /*!< USBH_T::HcCommandStatus: HCR Position*/
#define USBH_HcCommandStatus_HCR_Msk (0x1ul << USBH_HcCommandStatus_HCR_Pos) /*!< USBH_T::HcCommandStatus: HCR Mask */
#define USBH_HcCommandStatus_CLF_Pos (1) /*!< USBH_T::HcCommandStatus: CLF Position*/
#define USBH_HcCommandStatus_CLF_Msk (0x1ul << USBH_HcCommandStatus_CLF_Pos) /*!< USBH_T::HcCommandStatus: CLF Mask */
#define USBH_HcCommandStatus_BLF_Pos (2) /*!< USBH_T::HcCommandStatus: BLF Position*/
#define USBH_HcCommandStatus_BLF_Msk (0x1ul << USBH_HcCommandStatus_BLF_Pos) /*!< USBH_T::HcCommandStatus: BLF Mask */
#define USBH_HcCommandStatus_SOC_Pos (16) /*!< USBH_T::HcCommandStatus: SOC Position*/
#define USBH_HcCommandStatus_SOC_Msk (0x3ul << USBH_HcCommandStatus_SOC_Pos) /*!< USBH_T::HcCommandStatus: SOC Mask */
#define USBH_HcInterruptStatus_SO_Pos (0) /*!< USBH_T::HcInterruptStatus: SO Position*/
#define USBH_HcInterruptStatus_SO_Msk (0x1ul << USBH_HcInterruptStatus_SO_Pos) /*!< USBH_T::HcInterruptStatus: SO Mask */
#define USBH_HcInterruptStatus_WDH_Pos (1) /*!< USBH_T::HcInterruptStatus: WDH Position*/
#define USBH_HcInterruptStatus_WDH_Msk (0x1ul << USBH_HcInterruptStatus_WDH_Pos) /*!< USBH_T::HcInterruptStatus: WDH Mask */
#define USBH_HcInterruptStatus_SF_Pos (2) /*!< USBH_T::HcInterruptStatus: SF Position*/
#define USBH_HcInterruptStatus_SF_Msk (0x1ul << USBH_HcInterruptStatus_SF_Pos) /*!< USBH_T::HcInterruptStatus: SF Mask */
#define USBH_HcInterruptStatus_RD_Pos (3) /*!< USBH_T::HcInterruptStatus: RD Position*/
#define USBH_HcInterruptStatus_RD_Msk (0x1ul << USBH_HcInterruptStatus_RD_Pos) /*!< USBH_T::HcInterruptStatus: RD Mask */
#define USBH_HcInterruptStatus_FNO_Pos (5) /*!< USBH_T::HcInterruptStatus: FNO Position*/
#define USBH_HcInterruptStatus_FNO_Msk (0x1ul << USBH_HcInterruptStatus_FNO_Pos) /*!< USBH_T::HcInterruptStatus: FNO Mask */
#define USBH_HcInterruptStatus_RHSC_Pos (6) /*!< USBH_T::HcInterruptStatus: RHSC Position*/
#define USBH_HcInterruptStatus_RHSC_Msk (0x1ul << USBH_HcInterruptStatus_RHSC_Pos) /*!< USBH_T::HcInterruptStatus: RHSC Mask */
#define USBH_HcInterruptEnable_SO_Pos (0) /*!< USBH_T::HcInterruptEnable: SO Position*/
#define USBH_HcInterruptEnable_SO_Msk (0x1ul << USBH_HcInterruptEnable_SO_Pos) /*!< USBH_T::HcInterruptEnable: SO Mask */
#define USBH_HcInterruptEnable_WDH_Pos (1) /*!< USBH_T::HcInterruptEnable: WDH Position*/
#define USBH_HcInterruptEnable_WDH_Msk (0x1ul << USBH_HcInterruptEnable_WDH_Pos) /*!< USBH_T::HcInterruptEnable: WDH Mask */
#define USBH_HcInterruptEnable_SF_Pos (2) /*!< USBH_T::HcInterruptEnable: SF Position*/
#define USBH_HcInterruptEnable_SF_Msk (0x1ul << USBH_HcInterruptEnable_SF_Pos) /*!< USBH_T::HcInterruptEnable: SF Mask */
#define USBH_HcInterruptEnable_RD_Pos (3) /*!< USBH_T::HcInterruptEnable: RD Position*/
#define USBH_HcInterruptEnable_RD_Msk (0x1ul << USBH_HcInterruptEnable_RD_Pos) /*!< USBH_T::HcInterruptEnable: RD Mask */
#define USBH_HcInterruptEnable_FNO_Pos (5) /*!< USBH_T::HcInterruptEnable: FNO Position*/
#define USBH_HcInterruptEnable_FNO_Msk (0x1ul << USBH_HcInterruptEnable_FNO_Pos) /*!< USBH_T::HcInterruptEnable: FNO Mask */
#define USBH_HcInterruptEnable_RHSC_Pos (6) /*!< USBH_T::HcInterruptEnable: RHSC Position*/
#define USBH_HcInterruptEnable_RHSC_Msk (0x1ul << USBH_HcInterruptEnable_RHSC_Pos) /*!< USBH_T::HcInterruptEnable: RHSC Mask */
#define USBH_HcInterruptEnable_MIE_Pos (31) /*!< USBH_T::HcInterruptEnable: MIE Position*/
#define USBH_HcInterruptEnable_MIE_Msk (0x1ul << USBH_HcInterruptEnable_MIE_Pos) /*!< USBH_T::HcInterruptEnable: MIE Mask */
#define USBH_HcInterruptDisable_SO_Pos (0) /*!< USBH_T::HcInterruptDisable: SO Position*/
#define USBH_HcInterruptDisable_SO_Msk (0x1ul << USBH_HcInterruptDisable_SO_Pos) /*!< USBH_T::HcInterruptDisable: SO Mask */
#define USBH_HcInterruptDisable_WDH_Pos (1) /*!< USBH_T::HcInterruptDisable: WDH Position*/
#define USBH_HcInterruptDisable_WDH_Msk (0x1ul << USBH_HcInterruptDisable_WDH_Pos) /*!< USBH_T::HcInterruptDisable: WDH Mask */
#define USBH_HcInterruptDisable_SF_Pos (2) /*!< USBH_T::HcInterruptDisable: SF Position*/
#define USBH_HcInterruptDisable_SF_Msk (0x1ul << USBH_HcInterruptDisable_SF_Pos) /*!< USBH_T::HcInterruptDisable: SF Mask */
#define USBH_HcInterruptDisable_RD_Pos (3) /*!< USBH_T::HcInterruptDisable: RD Position*/
#define USBH_HcInterruptDisable_RD_Msk (0x1ul << USBH_HcInterruptDisable_RD_Pos) /*!< USBH_T::HcInterruptDisable: RD Mask */
#define USBH_HcInterruptDisable_FNO_Pos (5) /*!< USBH_T::HcInterruptDisable: FNO Position*/
#define USBH_HcInterruptDisable_FNO_Msk (0x1ul << USBH_HcInterruptDisable_FNO_Pos) /*!< USBH_T::HcInterruptDisable: FNO Mask */
#define USBH_HcInterruptDisable_RHSC_Pos (6) /*!< USBH_T::HcInterruptDisable: RHSC Position*/
#define USBH_HcInterruptDisable_RHSC_Msk (0x1ul << USBH_HcInterruptDisable_RHSC_Pos) /*!< USBH_T::HcInterruptDisable: RHSC Mask*/
#define USBH_HcInterruptDisable_MIE_Pos (31) /*!< USBH_T::HcInterruptDisable: MIE Position*/
#define USBH_HcInterruptDisable_MIE_Msk (0x1ul << USBH_HcInterruptDisable_MIE_Pos) /*!< USBH_T::HcInterruptDisable: MIE Mask */
#define USBH_HcHCCA_HCCA_Pos (8) /*!< USBH_T::HcHCCA: HCCA Position */
#define USBH_HcHCCA_HCCA_Msk (0xfffffful << USBH_HcHCCA_HCCA_Pos) /*!< USBH_T::HcHCCA: HCCA Mask */
#define USBH_HcPeriodCurrentED_PCED_Pos (4) /*!< USBH_T::HcPeriodCurrentED: PCED Position*/
#define USBH_HcPeriodCurrentED_PCED_Msk (0xffffffful << USBH_HcPeriodCurrentED_PCED_Pos) /*!< USBH_T::HcPeriodCurrentED: PCED Mask */
#define USBH_HcControlHeadED_CHED_Pos (4) /*!< USBH_T::HcControlHeadED: CHED Position*/
#define USBH_HcControlHeadED_CHED_Msk (0xffffffful << USBH_HcControlHeadED_CHED_Pos) /*!< USBH_T::HcControlHeadED: CHED Mask */
#define USBH_HcControlCurrentED_CCED_Pos (4) /*!< USBH_T::HcControlCurrentED: CCED Position*/
#define USBH_HcControlCurrentED_CCED_Msk (0xffffffful << USBH_HcControlCurrentED_CCED_Pos) /*!< USBH_T::HcControlCurrentED: CCED Mask*/
#define USBH_HcBulkHeadED_BHED_Pos (4) /*!< USBH_T::HcBulkHeadED: BHED Position */
#define USBH_HcBulkHeadED_BHED_Msk (0xffffffful << USBH_HcBulkHeadED_BHED_Pos) /*!< USBH_T::HcBulkHeadED: BHED Mask */
#define USBH_HcBulkCurrentED_BCED_Pos (4) /*!< USBH_T::HcBulkCurrentED: BCED Position*/
#define USBH_HcBulkCurrentED_BCED_Msk (0xffffffful << USBH_HcBulkCurrentED_BCED_Pos) /*!< USBH_T::HcBulkCurrentED: BCED Mask */
#define USBH_HcDoneHead_DH_Pos (4) /*!< USBH_T::HcDoneHead: DH Position */
#define USBH_HcDoneHead_DH_Msk (0xffffffful << USBH_HcDoneHead_DH_Pos) /*!< USBH_T::HcDoneHead: DH Mask */
#define USBH_HcFmInterval_FI_Pos (0) /*!< USBH_T::HcFmInterval: FI Position */
#define USBH_HcFmInterval_FI_Msk (0x3ffful << USBH_HcFmInterval_FI_Pos) /*!< USBH_T::HcFmInterval: FI Mask */
#define USBH_HcFmInterval_FSMPS_Pos (16) /*!< USBH_T::HcFmInterval: FSMPS Position */
#define USBH_HcFmInterval_FSMPS_Msk (0x3ffful << USBH_HcFmInterval_FSMPS_Pos) /*!< USBH_T::HcFmInterval: FSMPS Mask */
#define USBH_HcFmInterval_FIT_Pos (31) /*!< USBH_T::HcFmInterval: FIT Position */
#define USBH_HcFmInterval_FIT_Msk (0x1ul << USBH_HcFmInterval_FIT_Pos) /*!< USBH_T::HcFmInterval: FIT Mask */
#define USBH_HcFmRemaining_FR_Pos (0) /*!< USBH_T::HcFmRemaining: FR Position */
#define USBH_HcFmRemaining_FR_Msk (0x3ffful << USBH_HcFmRemaining_FR_Pos) /*!< USBH_T::HcFmRemaining: FR Mask */
#define USBH_HcFmRemaining_FRT_Pos (31) /*!< USBH_T::HcFmRemaining: FRT Position */
#define USBH_HcFmRemaining_FRT_Msk (0x1ul << USBH_HcFmRemaining_FRT_Pos) /*!< USBH_T::HcFmRemaining: FRT Mask */
#define USBH_HcFmNumber_FN_Pos (0) /*!< USBH_T::HcFmNumber: FN Position */
#define USBH_HcFmNumber_FN_Msk (0xfffful << USBH_HcFmNumber_FN_Pos) /*!< USBH_T::HcFmNumber: FN Mask */
#define USBH_HcPeriodicStart_PS_Pos (0) /*!< USBH_T::HcPeriodicStart: PS Position */
#define USBH_HcPeriodicStart_PS_Msk (0x3ffful << USBH_HcPeriodicStart_PS_Pos) /*!< USBH_T::HcPeriodicStart: PS Mask */
#define USBH_HcLSThreshold_LST_Pos (0) /*!< USBH_T::HcLSThreshold: LST Position */
#define USBH_HcLSThreshold_LST_Msk (0xffful << USBH_HcLSThreshold_LST_Pos) /*!< USBH_T::HcLSThreshold: LST Mask */
#define USBH_HcRhDescriptorA_NDP_Pos (0) /*!< USBH_T::HcRhDescriptorA: NDP Position*/
#define USBH_HcRhDescriptorA_NDP_Msk (0xfful << USBH_HcRhDescriptorA_NDP_Pos) /*!< USBH_T::HcRhDescriptorA: NDP Mask */
#define USBH_HcRhDescriptorA_PSM_Pos (8) /*!< USBH_T::HcRhDescriptorA: PSM Position*/
#define USBH_HcRhDescriptorA_PSM_Msk (0x1ul << USBH_HcRhDescriptorA_PSM_Pos) /*!< USBH_T::HcRhDescriptorA: PSM Mask */
#define USBH_HcRhDescriptorA_OCPM_Pos (11) /*!< USBH_T::HcRhDescriptorA: OCPM Position*/
#define USBH_HcRhDescriptorA_OCPM_Msk (0x1ul << USBH_HcRhDescriptorA_OCPM_Pos) /*!< USBH_T::HcRhDescriptorA: OCPM Mask */
#define USBH_HcRhDescriptorA_NOCP_Pos (12) /*!< USBH_T::HcRhDescriptorA: NOCP Position*/
#define USBH_HcRhDescriptorA_NOCP_Msk (0x1ul << USBH_HcRhDescriptorA_NOCP_Pos) /*!< USBH_T::HcRhDescriptorA: NOCP Mask */
#define USBH_HcRhDescriptorB_PPCM_Pos (16) /*!< USBH_T::HcRhDescriptorB: PPCM Position*/
#define USBH_HcRhDescriptorB_PPCM_Msk (0xfffful << USBH_HcRhDescriptorB_PPCM_Pos) /*!< USBH_T::HcRhDescriptorB: PPCM Mask */
#define USBH_HcRhStatus_LPS_Pos (0) /*!< USBH_T::HcRhStatus: LPS Position */
#define USBH_HcRhStatus_LPS_Msk (0x1ul << USBH_HcRhStatus_LPS_Pos) /*!< USBH_T::HcRhStatus: LPS Mask */
#define USBH_HcRhStatus_OCI_Pos (1) /*!< USBH_T::HcRhStatus: OCI Position */
#define USBH_HcRhStatus_OCI_Msk (0x1ul << USBH_HcRhStatus_OCI_Pos) /*!< USBH_T::HcRhStatus: OCI Mask */
#define USBH_HcRhStatus_DRWE_Pos (15) /*!< USBH_T::HcRhStatus: DRWE Position */
#define USBH_HcRhStatus_DRWE_Msk (0x1ul << USBH_HcRhStatus_DRWE_Pos) /*!< USBH_T::HcRhStatus: DRWE Mask */
#define USBH_HcRhStatus_LPSC_Pos (16) /*!< USBH_T::HcRhStatus: LPSC Position */
#define USBH_HcRhStatus_LPSC_Msk (0x1ul << USBH_HcRhStatus_LPSC_Pos) /*!< USBH_T::HcRhStatus: LPSC Mask */
#define USBH_HcRhStatus_OCIC_Pos (17) /*!< USBH_T::HcRhStatus: OCIC Position */
#define USBH_HcRhStatus_OCIC_Msk (0x1ul << USBH_HcRhStatus_OCIC_Pos) /*!< USBH_T::HcRhStatus: OCIC Mask */
#define USBH_HcRhStatus_CRWE_Pos (31) /*!< USBH_T::HcRhStatus: CRWE Position */
#define USBH_HcRhStatus_CRWE_Msk (0x1ul << USBH_HcRhStatus_CRWE_Pos) /*!< USBH_T::HcRhStatus: CRWE Mask */
#define USBH_HcRhPortStatus_CCS_Pos (0) /*!< USBH_T::HcRhPortStatus: CCS Position */
#define USBH_HcRhPortStatus_CCS_Msk (0x1ul << USBH_HcRhPortStatus_CCS_Pos) /*!< USBH_T::HcRhPortStatus: CCS Mask */
#define USBH_HcRhPortStatus_PES_Pos (1) /*!< USBH_T::HcRhPortStatus: PES Position */
#define USBH_HcRhPortStatus_PES_Msk (0x1ul << USBH_HcRhPortStatus_PES_Pos) /*!< USBH_T::HcRhPortStatus: PES Mask */
#define USBH_HcRhPortStatus_PSS_Pos (2) /*!< USBH_T::HcRhPortStatus: PSS Position */
#define USBH_HcRhPortStatus_PSS_Msk (0x1ul << USBH_HcRhPortStatus_PSS_Pos) /*!< USBH_T::HcRhPortStatus: PSS Mask */
#define USBH_HcRhPortStatus_POCI_Pos (3) /*!< USBH_T::HcRhPortStatus: POCI Position*/
#define USBH_HcRhPortStatus_POCI_Msk (0x1ul << USBH_HcRhPortStatus_POCI_Pos) /*!< USBH_T::HcRhPortStatus: POCI Mask */
#define USBH_HcRhPortStatus_PRS_Pos (4) /*!< USBH_T::HcRhPortStatus: PRS Position */
#define USBH_HcRhPortStatus_PRS_Msk (0x1ul << USBH_HcRhPortStatus_PRS_Pos) /*!< USBH_T::HcRhPortStatus: PRS Mask */
#define USBH_HcRhPortStatus_PPS_Pos (8) /*!< USBH_T::HcRhPortStatus: PPS Position */
#define USBH_HcRhPortStatus_PPS_Msk (0x1ul << USBH_HcRhPortStatus_PPS_Pos) /*!< USBH_T::HcRhPortStatus: PPS Mask */
#define USBH_HcRhPortStatus_LSDA_Pos (9) /*!< USBH_T::HcRhPortStatus: LSDA Position*/
#define USBH_HcRhPortStatus_LSDA_Msk (0x1ul << USBH_HcRhPortStatus_LSDA_Pos) /*!< USBH_T::HcRhPortStatus: LSDA Mask */
#define USBH_HcRhPortStatus_CSC_Pos (16) /*!< USBH_T::HcRhPortStatus: CSC Position */
#define USBH_HcRhPortStatus_CSC_Msk (0x1ul << USBH_HcRhPortStatus_CSC_Pos) /*!< USBH_T::HcRhPortStatus: CSC Mask */
#define USBH_HcRhPortStatus_PESC_Pos (17) /*!< USBH_T::HcRhPortStatus: PESC Position*/
#define USBH_HcRhPortStatus_PESC_Msk (0x1ul << USBH_HcRhPortStatus_PESC_Pos) /*!< USBH_T::HcRhPortStatus: PESC Mask */
#define USBH_HcRhPortStatus_PSSC_Pos (18) /*!< USBH_T::HcRhPortStatus: PSSC Position*/
#define USBH_HcRhPortStatus_PSSC_Msk (0x1ul << USBH_HcRhPortStatus_PSSC_Pos) /*!< USBH_T::HcRhPortStatus: PSSC Mask */
#define USBH_HcRhPortStatus_OCIC_Pos (19) /*!< USBH_T::HcRhPortStatus: OCIC Position*/
#define USBH_HcRhPortStatus_OCIC_Msk (0x1ul << USBH_HcRhPortStatus_OCIC_Pos) /*!< USBH_T::HcRhPortStatus: OCIC Mask */
#define USBH_HcRhPortStatus_PRSC_Pos (20) /*!< USBH_T::HcRhPortStatus: PRSC Position*/
#define USBH_HcRhPortStatus_PRSC_Msk (0x1ul << USBH_HcRhPortStatus_PRSC_Pos) /*!< USBH_T::HcRhPortStatus: PRSC Mask */
#define USBH_HcPhyControl_ABORT_Pos (1) /*!< USBH_T::HcPhyControl: ABORT Position */
#define USBH_HcPhyControl_ABORT_Msk (0x1ul << USBH_HcPhyControl_ABORT_Pos) /*!< USBH_T::HcPhyControl: ABORT Mask */
#define USBH_HcPhyControl_OCAL_Pos (3) /*!< USBH_T::HcPhyControl: OCAL Position */
#define USBH_HcPhyControl_OCAL_Msk (0x1ul << USBH_HcPhyControl_OCAL_Pos) /*!< USBH_T::HcPhyControl: OCAL Mask */
#define USBH_HcPhyControl_PPCAL_Pos (4) /*!< USBH_T::HcPhyControl: PPCAL Position */
#define USBH_HcPhyControl_PPCAL_Msk (0x1ul << USBH_HcPhyControl_PPCAL_Pos) /*!< USBH_T::HcPhyControl: PPCAL Mask */
#define USBH_HcPhyControl_DPRT1_Pos (16) /*!< USBH_T::HcPhyControl: DPRT1 Position */
#define USBH_HcPhyControl_DPRT1_Msk (0x1ul << USBH_HcPhyControl_DPRT1_Pos) /*!< USBH_T::HcPhyControl: DPRT1 Mask */
/**@}*/ /* USBH_CONST */
/**@}*/ /* end of USBH register group */
/**@}*/ /* end of REGISTER group */
#if defined ( __CC_ARM )
#pragma no_anon_unions
#endif
#endif /* __USBH_REG_H__ */

179
bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/wdt_reg.h Normal file
View File

@ -0,0 +1,179 @@
/**************************************************************************//**
* @file wdt_reg.h
* @brief WDT register definition header file
*
* SPDX-License-Identifier: Apache-2.0
* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __WDT_REG_H__
#define __WDT_REG_H__
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
/**
@addtogroup REGISTER Control Register
@{
*/
/**
@addtogroup WDT Watch Dog Timer Controller(WDT)
Memory Mapped Structure for WDT Controller
@{ */
typedef struct
{
/**
* @var WDT_T::CTL
* Offset: 0x00 WDT Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[1] |RSTEN |WDT Time-out Reset Enable Bit (Write Protect)
* | | |Setting this bit will enable the WDT time-out reset function if the WDT up counter value has not been cleared after the specific WDT reset delay period expires.
* | | |0 = WDT time-out reset function Disabled.
* | | |1 = WDT time-out reset function Enabled.
* | | |Note: This bit is write protected
* | | |Refer to the SYS_RLKTZS register or SYS_RLKTZNS register or SYS_RLKSUBM register.
* |[2] |RSTF |WDT Time-out Reset Flag
* | | |This bit indicates the system has been reset by WDT time-out reset or not.
* | | |0 = WDT time-out reset did not occur.
* | | |1 = WDT time-out reset occurred.
* | | |Note: This bit is cleared by writing 1 to it.
* |[3] |IF |WDT Time-out Interrupt Flag
* | | |This bit will be set to 1 while WDT up counter value reaches the selected WDT time-out interval.
* | | |0 = WDT time-out interrupt did not occur.
* | | |1 = WDT time-out interrupt occurred.
* | | |Note: This bit is cleared by writing 1 to it.
* |[4] |WKEN |WDT Time-out Wake-up Function Control (Write Protect)
* | | |If this bit is set to 1, while WDT time-out interrupt flag IF (WDT_CTL[3]) is generated to 1 and interrupt enable bit INTEN (WDT_CTL[6]) is enabled, the WDT time-out interrupt signal will generate a wake-up trigger event to chip.
* | | |0 = Wake-up trigger event Disabled if WDT time-out interrupt signal generated.
* | | |1 = Wake-up trigger event Enabled if WDT time-out interrupt signal generated.
* | | |Note 1: This bit is write protected
* | | |Refer to the SYS_RLKTZS register or SYS_RLKTZNS register or SYS_RLKSUBM register.
* | | |Note 2: Chip can be woken up by WDT time-out interrupt signal generated only if WDT clock source is selected to 32 kHz internal low speed RC oscillator (LIRC) or LXT.
* |[5] |WKF |WDT Time-out Wake-up Flag
* | | |This bit indicates the interrupt wake-up flag status of WDT
* | | |0 = WDT does not cause chip wake-up.
* | | |1 = Chip wake-up from Idle or Power-down mode if WDT time-out interrupt signal generated.
* | | |Note: This bit is cleared by writing 1 to it.
* |[6] |INTEN |WDT Time-out Interrupt Enable Bit (Write Protect)
* | | |If this bit is enabled, the WDT time-out interrupt signal is generated and inform to CPU.
* | | |0 = WDT time-out interrupt Disabled.
* | | |1 = WDT time-out interrupt Enabled.
* | | |Note: This bit is write protected
* | | |Refer to the SYS_RLKTZS register or SYS_RLKTZNS register or SYS_RLKSUBM register.
* |[7] |WDTEN |WDT Enable Bit (Write Protect)
* | | |0 = WDT Disabled (This action will reset the internal up counter value).
* | | |1 = WDT Enabled.
* | | |Note 1: This bit is write protected
* | | |Refer to the SYS_RLKTZS register or SYS_RLKTZNS register or SYS_RLKSUBM register.
* | | |Note 2: If CWDTEN[2:0] (combined by Config0[31] and Config0[4:3]) bits is not configured to 111, this bit is forced as 1 and user cannot change this bit to 0.
* |[11:8] |TOUTSEL |WDT Time-out Interval Selection (Write Protect)
* | | |These three bits select the time-out interval period for the WDT.
* | | |0000 = 24 * WDT_CLK.
* | | |0001 = 26 * WDT_CLK.
* | | |0010 = 28 * WDT_CLK.
* | | |0011 = 210 * WDT_CLK.
* | | |0100= 212 * WDT_CLK.
* | | |0101 = 214 * WDT_CLK.
* | | |0110 = 216 * WDT_CLK.
* | | |0111 = 218 * WDT_CLK.
* | | |1000 = 220 * WDT_CLK.
* | | |Note: This bit is write protected
* | | |Refer to the SYS_RLKTZS register or SYS_RLKTZNS register or SYS_RLKSUBM register.
* |[30] |SYNC |WDT Enable Control SYNC Flag Indicator (Read Only)
* | | |If user executes enable/disable WDTEN (WDT_CTL[7]), this flag can be indicated enable/disable WDTEN function is completed or not.
* | | |0 = Set WDTEN bit is completed.
* | | |1 = Set WDTEN bit is synchronizing and not become active yet.
* | | |Note: Performing enable or disable WDTEN bit needs 2 * WDT_CLK period to become active.
* |[31] |ICEDEBUG |ICE Debug Mode Acknowledge Disable Bit (Write Protect)
* | | |0 = ICE debug mode acknowledgement affects WDT counting.
* | | |WDT up counter will be held while CPU is held by ICE.
* | | |1 = ICE debug mode acknowledgement Disabled.
* | | |WDT up counter will keep going no matter CPU is held by ICE or not.
* | | |Note: This bit is write protected
* | | |Refer to the SYS_RLKTZS register or SYS_RLKTZNS register or SYS_RLKSUBM register
* @var WDT_T::ALTCTL
* Offset: 0x04 WDT Alternative Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[1:0] |RSTDSEL |WDT Reset Delay Selection (Write Protect)
* | | |When WDT time-out happened, user has a time named WDT Reset Delay Period to clear WDT counter by programming 0x5AA5 to RSTCNT to prevent WDT time-out reset happened.
* | | |User can select a suitable setting of RSTDSEL for different WDT Reset Delay Period.
* | | |00 = WDT Reset Delay Period is 1026 * WDT_CLK.
* | | |01 = WDT Reset Delay Period is 130 * WDT_CLK.
* | | |10 = WDT Reset Delay Period is 18 * WDT_CLK.
* | | |11 = WDT Reset Delay Period is 3 * WDT_CLK.
* | | |Note 1: This bit is write protected
* | | |Refer to the SYS_RLKTZS register or SYS_RLKTZNS register or SYS_RLKSUBM register.
* | | |Note 2: This register will be reset to 0 if WDT time-out reset happened.
* @var WDT_T::RSTCNT
* Offset: 0x08 WDT Reset Counter Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |RSTCNT |WDT Reset Counter Register
* | | |Writing 0x00005AA5 to this field will reset the internal 20-bit WDT up counter value to 0.
* | | |Note: Performing RSTCNT to reset counter needs 2 * WDT_CLK period to become active.
*/
__IO uint32_t CTL; /*!< [0x0000] WDT Control Register */
__IO uint32_t ALTCTL; /*!< [0x0004] WDT Alternative Control Register */
__O uint32_t RSTCNT; /*!< [0x0008] WDT Reset Counter Register */
} WDT_T;
/**
@addtogroup WDT_CONST WDT Bit Field Definition
Constant Definitions for WDT Controller
@{ */
#define WDT_CTL_RSTEN_Pos (1) /*!< WDT_T::CTL: RSTEN Position */
#define WDT_CTL_RSTEN_Msk (0x1ul << WDT_CTL_RSTEN_Pos) /*!< WDT_T::CTL: RSTEN Mask */
#define WDT_CTL_RSTF_Pos (2) /*!< WDT_T::CTL: RSTF Position */
#define WDT_CTL_RSTF_Msk (0x1ul << WDT_CTL_RSTF_Pos) /*!< WDT_T::CTL: RSTF Mask */
#define WDT_CTL_IF_Pos (3) /*!< WDT_T::CTL: IF Position */
#define WDT_CTL_IF_Msk (0x1ul << WDT_CTL_IF_Pos) /*!< WDT_T::CTL: IF Mask */
#define WDT_CTL_WKEN_Pos (4) /*!< WDT_T::CTL: WKEN Position */
#define WDT_CTL_WKEN_Msk (0x1ul << WDT_CTL_WKEN_Pos) /*!< WDT_T::CTL: WKEN Mask */
#define WDT_CTL_WKF_Pos (5) /*!< WDT_T::CTL: WKF Position */
#define WDT_CTL_WKF_Msk (0x1ul << WDT_CTL_WKF_Pos) /*!< WDT_T::CTL: WKF Mask */
#define WDT_CTL_INTEN_Pos (6) /*!< WDT_T::CTL: INTEN Position */
#define WDT_CTL_INTEN_Msk (0x1ul << WDT_CTL_INTEN_Pos) /*!< WDT_T::CTL: INTEN Mask */
#define WDT_CTL_WDTEN_Pos (7) /*!< WDT_T::CTL: WDTEN Position */
#define WDT_CTL_WDTEN_Msk (0x1ul << WDT_CTL_WDTEN_Pos) /*!< WDT_T::CTL: WDTEN Mask */
#define WDT_CTL_TOUTSEL_Pos (8) /*!< WDT_T::CTL: TOUTSEL Position */
#define WDT_CTL_TOUTSEL_Msk (0xful << WDT_CTL_TOUTSEL_Pos) /*!< WDT_T::CTL: TOUTSEL Mask */
#define WDT_CTL_SYNC_Pos (30) /*!< WDT_T::CTL: SYNC Position */
#define WDT_CTL_SYNC_Msk (0x1ul << WDT_CTL_SYNC_Pos) /*!< WDT_T::CTL: SYNC Mask */
#define WDT_CTL_ICEDEBUG_Pos (31) /*!< WDT_T::CTL: ICEDEBUG Position */
#define WDT_CTL_ICEDEBUG_Msk (0x1ul << WDT_CTL_ICEDEBUG_Pos) /*!< WDT_T::CTL: ICEDEBUG Mask */
#define WDT_ALTCTL_RSTDSEL_Pos (0) /*!< WDT_T::ALTCTL: RSTDSEL Position */
#define WDT_ALTCTL_RSTDSEL_Msk (0x3ul << WDT_ALTCTL_RSTDSEL_Pos) /*!< WDT_T::ALTCTL: RSTDSEL Mask */
#define WDT_RSTCNT_RSTCNT_Pos (0) /*!< WDT_T::RSTCNT: RSTCNT Position */
#define WDT_RSTCNT_RSTCNT_Msk (0xfffffffful << WDT_RSTCNT_RSTCNT_Pos) /*!< WDT_T::RSTCNT: RSTCNT Mask */
/**@}*/ /* WDT_CONST */
/**@}*/ /* end of WDT register group */
/**@}*/ /* end of REGISTER group */
#if defined ( __CC_ARM )
#pragma no_anon_unions
#endif
#endif /* __WDT_REG_H__ */

1034
bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/whc_reg.h Normal file
View File

File diff suppressed because it is too large Load Diff

147
bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/wwdt_reg.h Normal file
View File

@ -0,0 +1,147 @@
/**************************************************************************//**
* @file wwdt_reg.h
* @brief WWDT register definition header file
*
* SPDX-License-Identifier: Apache-2.0
* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __WWDT_REG_H__
#define __WWDT_REG_H__
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
/**
@addtogroup REGISTER Control Register
@{
*/
/**
@addtogroup WWDT Window Watchdog Timer(WWDT)
Memory Mapped Structure for WWDT Controller
@{ */
typedef struct
{
/**
* @var WWDT_T::RLDCNT
* Offset: 0x00 WWDT Reload Counter Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |RLDCNT |WWDT Reload Counter Register
* | | |Writing 0x00005AA5 to this register will reload the WWDT counter value to 0x3F.
* | | |Note: User can only write WWDT_RLDCNT register to reload WWDT counter value when current WWDT counter value between 0 and CMPDAT (WWDT_CTL[21:16])
* | | |If user writes WWDT_RLDCNT when current WWDT counter value is larger than CMPDAT, WWDT reset signal will be generated.
* @var WWDT_T::CTL
* Offset: 0x04 WWDT Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |WWDTEN |WWDT Enable Bit
* | | |0 = WWDT counter is stopped.
* | | |1 = WWDT counter starts counting.
* |[1] |INTEN |WWDT Interrupt Enable Bit
* | | |If this bit is enabled, the WWDT counter compare match interrupt signal is generated and inform to CPU.
* | | |0 = WWDT counter compare match interrupt Disabled.
* | | |1 = WWDT counter compare match interrupt Enabled.
* |[11:8] |PSCSEL |WWDT Counter Prescale Period Selection
* | | |0000 = Pre-scale is 1; Max time-out period is 1 * 64 * WWDT_CLK.
* | | |0001 = Pre-scale is 2; Max time-out period is 2 * 64 * WWDT_CLK.
* | | |0010 = Pre-scale is 4; Max time-out period is 4 * 64 * WWDT_CLK.
* | | |0011 = Pre-scale is 8; Max time-out period is 8 * 64 * WWDT_CLK.
* | | |0100 = Pre-scale is 16; Max time-out period is 16 * 64 * WWDT_CLK.
* | | |0101 = Pre-scale is 32; Max time-out period is 32 * 64 * WWDT_CLK.
* | | |0110 = Pre-scale is 64; Max time-out period is 64 * 64 * WWDT_CLK.
* | | |0111 = Pre-scale is 128; Max time-out period is 128 * 64 * WWDT_CLK.
* | | |1000 = Pre-scale is 192; Max time-out period is 192 * 64 * WWDT_CLK.
* | | |1001 = Pre-scale is 256; Max time-out period is 256 * 64 * WWDT_CLK.
* | | |1010 = Pre-scale is 384; Max time-out period is 384 * 64 * WWDT_CLK.
* | | |1011 = Pre-scale is 512; Max time-out period is 512 * 64 * WWDT_CLK.
* | | |1100 = Pre-scale is 768; Max time-out period is 768 * 64 * WWDT_CLK.
* | | |1101 = Pre-scale is 1024; Max time-out period is 1024 * 64 * WWDT_CLK.
* | | |1110 = Pre-scale is 1536; Max time-out period is 1536 * 64 * WWDT_CLK.
* | | |1111 = Pre-scale is 2048; Max time-out period is 2048 * 64 * WWDT_CLK.
* |[21:16] |CMPDAT |WWDT Window Compare Register
* | | |Set this register to adjust the valid reload window.
* | | |Note: User can only write WWDT_RLDCNT register to reload WWDT counter value when current WWDT counter value between 0 and CMPDAT
* | | |If user writes WWDT_RLDCNT register when current WWDT counter value larger than CMPDAT, WWDT reset signal will generate.
* |[31] |ICEDEBUG |ICE Debug Mode Acknowledge Disable Bit
* | | |0 = ICE debug mode acknowledgement effects WWDT counting.
* | | |WWDT down counter will be held while CPU is held by ICE.
* | | |1 = ICE debug mode acknowledgement Disabled.
* | | |Note: WWDT down counter will keep going no matter CPU is held by ICE or not.
* @var WWDT_T::STATUS
* Offset: 0x08 WWDT Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |WWDTIF |WWDT Compare Match Interrupt Flag
* | | |This bit indicates the interrupt flag status of WWDT while WWDT counter value matches CMPDAT (WWDT_CTL[21:16]).
* | | |0 = No effect.
* | | |1 = WWDT counter value matches CMPDAT.
* | | |Note: This bit is cleared by writing 1 to it.
* |[1] |WWDTRF |WWDT Timer-out Reset Flag
* | | |This bit indicates the system has been reset by WWDT time-out reset or not.
* | | |0 = WWDT time-out reset did not occur.
* | | |1 = WWDT time-out reset occurred.
* | | |Note: This bit is cleared by writing 1 to it.
* @var WWDT_T::CNT
* Offset: 0x0C WWDT Counter Value Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[5:0] |CNTDAT |WWDT Counter Value
* | | |CNTDAT will be updated continuously to monitor 6-bit WWDT down counter value.
*/
__O uint32_t RLDCNT; /*!< [0x0000] WWDT Reload Counter Register */
__IO uint32_t CTL; /*!< [0x0004] WWDT Control Register */
__IO uint32_t STATUS; /*!< [0x0008] WWDT Status Register */
__I uint32_t CNT; /*!< [0x000c] WWDT Counter Value Register */
} WWDT_T;
/**
@addtogroup WWDT_CONST WWDT Bit Field Definition
Constant Definitions for WWDT Controller
@{ */
#define WWDT_RLDCNT_RLDCNT_Pos (0) /*!< WWDT_T::RLDCNT: RLDCNT Position */
#define WWDT_RLDCNT_RLDCNT_Msk (0xfffffffful << WWDT_RLDCNT_RLDCNT_Pos) /*!< WWDT_T::RLDCNT: RLDCNT Mask */
#define WWDT_CTL_WWDTEN_Pos (0) /*!< WWDT_T::CTL: WWDTEN Position */
#define WWDT_CTL_WWDTEN_Msk (0x1ul << WWDT_CTL_WWDTEN_Pos) /*!< WWDT_T::CTL: WWDTEN Mask */
#define WWDT_CTL_INTEN_Pos (1) /*!< WWDT_T::CTL: INTEN Position */
#define WWDT_CTL_INTEN_Msk (0x1ul << WWDT_CTL_INTEN_Pos) /*!< WWDT_T::CTL: INTEN Mask */
#define WWDT_CTL_PSCSEL_Pos (8) /*!< WWDT_T::CTL: PSCSEL Position */
#define WWDT_CTL_PSCSEL_Msk (0xful << WWDT_CTL_PSCSEL_Pos) /*!< WWDT_T::CTL: PSCSEL Mask */
#define WWDT_CTL_CMPDAT_Pos (16) /*!< WWDT_T::CTL: CMPDAT Position */
#define WWDT_CTL_CMPDAT_Msk (0x3ful << WWDT_CTL_CMPDAT_Pos) /*!< WWDT_T::CTL: CMPDAT Mask */
#define WWDT_CTL_ICEDEBUG_Pos (31) /*!< WWDT_T::CTL: ICEDEBUG Position */
#define WWDT_CTL_ICEDEBUG_Msk (0x1ul << WWDT_CTL_ICEDEBUG_Pos) /*!< WWDT_T::CTL: ICEDEBUG Mask */
#define WWDT_STATUS_WWDTIF_Pos (0) /*!< WWDT_T::STATUS: WWDTIF Position */
#define WWDT_STATUS_WWDTIF_Msk (0x1ul << WWDT_STATUS_WWDTIF_Pos) /*!< WWDT_T::STATUS: WWDTIF Mask */
#define WWDT_STATUS_WWDTRF_Pos (1) /*!< WWDT_T::STATUS: WWDTRF Position */
#define WWDT_STATUS_WWDTRF_Msk (0x1ul << WWDT_STATUS_WWDTRF_Pos) /*!< WWDT_T::STATUS: WWDTRF Mask */
#define WWDT_CNT_CNTDAT_Pos (0) /*!< WWDT_T::CNT: CNTDAT Position */
#define WWDT_CNT_CNTDAT_Msk (0x3ful << WWDT_CNT_CNTDAT_Pos) /*!< WWDT_T::CNT: CNTDAT Mask */
/**@}*/ /* WWDT_CONST */
/**@}*/ /* end of WWDT register group */
/**@}*/ /* end of REGISTER group */
#if defined ( __CC_ARM )
#pragma no_anon_unions
#endif
#endif /* __WWDT_REG_H__ */

488
bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Source/ARM/startup_ma35d1_subm.s Normal file
View File

@ -0,0 +1,488 @@
;/******************************************************************************
; * @file startup_ma35d1_subm.s
; * @brief CMSIS Cortex-M4 Core Device Startup File
; *
; * SPDX-License-Identifier: Apache-2.0
; * @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
;*****************************************************************************/
;/*
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;*/
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
IF :LNOT: :DEF: Stack_Size
Stack_Size EQU 0x00001000
ENDIF
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
EXPORT __initial_sp
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
IF :LNOT: :DEF: Heap_Size
Heap_Size EQU 0x00000100
ENDIF
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD LVD_IRQHandler ; 0
DCD Default_Handler ; 1
DCD PWRWU_IRQHandler ; 2
DCD HWSEM0_IRQHandler ; 3
DCD CKFAIL_IRQHandler ; 4
DCD WHC0_IRQHandler ; 5
DCD RTC_IRQHandler ; 6
DCD TAMPER_IRQHandler ; 7
DCD WDT2_IRQHandler ; 8
DCD WWDT2_IRQHandler ; 9
DCD EINT0_IRQHandler ; 10
DCD EINT1_IRQHandler ; 11
DCD EINT2_IRQHandler ; 12
DCD EINT3_IRQHandler ; 13
DCD Default_Handler ; 14
DCD Default_Handler ; 15
DCD GPA_IRQHandler ; 16
DCD GPB_IRQHandler ; 17
DCD GPC_IRQHandler ; 18
DCD GPD_IRQHandler ; 19
DCD Default_Handler ; 20
DCD Default_Handler ; 21
DCD TMR2_IRQHandler ; 22
DCD TMR3_IRQHandler ; 23
DCD BRAKE0_IRQHandler ; 24
DCD EPWM0P0_IRQHandler ; 25
DCD EPWM0P1_IRQHandler ; 26
DCD EPWM0P2_IRQHandler ; 27
DCD QEI0_IRQHandler ; 28
DCD ECAP0_IRQHandler ; 29
DCD Default_Handler ; 30
DCD QSPI1_IRQHandler ; 31
DCD Default_Handler ; 32
DCD Default_Handler ; 33
DCD Default_Handler ; 34
DCD UART1_IRQHandler ; 35
DCD UART2_IRQHandler ; 36
DCD UART3_IRQHandler ; 37
DCD UART4_IRQHandler ; 38
DCD UART5_IRQHandler ; 39
DCD EADC00_IRQHandler ; 40
DCD EADC01_IRQHandler ; 41
DCD EADC02_IRQHandler ; 42
DCD EADC03_IRQHandler ; 43
DCD Default_Handler ; 44
DCD I2C1_IRQHandler ; 45
DCD I2S0_IRQHandler ; 46
DCD CANFD00_IRQHandler ; 47
DCD SC0_IRQHandler ; 48
DCD GPE_IRQHandler ; 49
DCD GPF_IRQHandler ; 50
DCD GPG_IRQHandler ; 51
DCD GPH_IRQHandler ; 52
DCD GPI_IRQHandler ; 53
DCD GPJ_IRQHandler ; 54
DCD TMR4_IRQHandler ; 55
DCD TMR5_IRQHandler ; 56
DCD TMR6_IRQHandler ; 57
DCD TMR7_IRQHandler ; 58
DCD BRAKE1_IRQHandler ; 59
DCD EPWM1P0_IRQHandler ; 60
DCD EPWM1P1_IRQHandler ; 61
DCD EPWM1P2_IRQHandler ; 62
DCD QEI1_IRQHandler ; 63
DCD ECAP1_IRQHandler ; 64
DCD SPI0_IRQHandler ; 65
DCD SPI1_IRQHandler ; 66
DCD PDMA2_IRQHandler ; 67
DCD PDMA3_IRQHandler ; 68
DCD UART6_IRQHandler ; 69
DCD UART7_IRQHandler ; 70
DCD UART8_IRQHandler ; 71
DCD UART9_IRQHandler ; 72
DCD UART10_IRQHandler ; 73
DCD UART11_IRQHandler ; 74
DCD I2C2_IRQHandler ; 75
DCD I2C3_IRQHandler ; 76
DCD I2S1_IRQHandler ; 77
DCD CANFD10_IRQHandler ; 78
DCD SC1_IRQHandler ; 79
DCD GPK_IRQHandler ; 80
DCD GPL_IRQHandler ; 81
DCD GPM_IRQHandler ; 82
DCD GPN_IRQHandler ; 83
DCD TMR8_IRQHandler ; 84
DCD TMR9_IRQHandler ; 85
DCD TMR10_IRQHandler ; 86
DCD TMR11_IRQHandler ; 87
DCD BRAKE2_IRQHandler ; 88
DCD EPWM2P0_IRQHandle ; 89
DCD EPWM2P1_IRQHandle ; 90
DCD EPWM2P2_IRQHandle ; 91
DCD QEI2_IRQHandler ; 92
DCD ECAP2_IRQHandler ; 93
DCD SPI2_IRQHandler ; 94
DCD SPI3_IRQHandler ; 95
DCD UART12_IRQHandler ; 96
DCD UART13_IRQHandler ; 97
DCD UART14_IRQHandler ; 98
DCD UART15_IRQHandler ; 99
DCD UART16_IRQHandler ; 100
DCD I2C4_IRQHandler ; 101
DCD I2C5_IRQHandler ; 102
DCD CANFD20_IRQHandler ; 103
DCD CANFD30_IRQHandler ; 104
DCD KPI_IRQHandler ; 105
DCD CANFD01_IRQHandler ; 106
DCD CANFD11_IRQHandler ; 107
DCD CANFD21_IRQHandler ; 108
DCD CANFD31_IRQHandler ; 109
DCD ADC0_IRQHandler ; 110
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler\
PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler\
PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT LVD_IRQHandler [WEAK]
EXPORT PWRWU_IRQHandler [WEAK]
EXPORT HWSEM0_IRQHandler [WEAK]
EXPORT CKFAIL_IRQHandler [WEAK]
EXPORT WHC0_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT WDT2_IRQHandler [WEAK]
EXPORT WWDT2_IRQHandler [WEAK]
EXPORT EINT0_IRQHandler [WEAK]
EXPORT EINT1_IRQHandler [WEAK]
EXPORT EINT2_IRQHandler [WEAK]
EXPORT EINT3_IRQHandler [WEAK]
EXPORT GPA_IRQHandler [WEAK]
EXPORT GPB_IRQHandler [WEAK]
EXPORT GPC_IRQHandler [WEAK]
EXPORT GPD_IRQHandler [WEAK]
EXPORT TMR2_IRQHandler [WEAK]
EXPORT TMR3_IRQHandler [WEAK]
EXPORT BRAKE0_IRQHandler [WEAK]
EXPORT EPWM0P0_IRQHandler [WEAK]
EXPORT EPWM0P1_IRQHandler [WEAK]
EXPORT EPWM0P2_IRQHandler [WEAK]
EXPORT QEI0_IRQHandler [WEAK]
EXPORT ECAP0_IRQHandler [WEAK]
EXPORT QSPI1_IRQHandler [WEAK]
EXPORT UART1_IRQHandler [WEAK]
EXPORT UART2_IRQHandler [WEAK]
EXPORT UART3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT EADC00_IRQHandler [WEAK]
EXPORT EADC01_IRQHandler [WEAK]
EXPORT EADC02_IRQHandler [WEAK]
EXPORT EADC03_IRQHandler [WEAK]
EXPORT I2C1_IRQHandler [WEAK]
EXPORT I2S0_IRQHandler [WEAK]
EXPORT CANFD00_IRQHandler [WEAK]
EXPORT SC0_IRQHandler [WEAK]
EXPORT GPE_IRQHandler [WEAK]
EXPORT GPF_IRQHandler [WEAK]
EXPORT GPG_IRQHandler [WEAK]
EXPORT GPH_IRQHandler [WEAK]
EXPORT GPI_IRQHandler [WEAK]
EXPORT GPJ_IRQHandler [WEAK]
EXPORT TMR4_IRQHandler [WEAK]
EXPORT TMR5_IRQHandler [WEAK]
EXPORT TMR6_IRQHandler [WEAK]
EXPORT TMR7_IRQHandler [WEAK]
EXPORT BRAKE1_IRQHandler [WEAK]
EXPORT EPWM1P0_IRQHandler [WEAK]
EXPORT EPWM1P1_IRQHandler [WEAK]
EXPORT EPWM1P2_IRQHandler [WEAK]
EXPORT QEI1_IRQHandler [WEAK]
EXPORT ECAP1_IRQHandler [WEAK]
EXPORT SPI0_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT PDMA2_IRQHandler [WEAK]
EXPORT PDMA3_IRQHandler [WEAK]
EXPORT UART6_IRQHandler [WEAK]
EXPORT UART7_IRQHandler [WEAK]
EXPORT UART8_IRQHandler [WEAK]
EXPORT UART9_IRQHandler [WEAK]
EXPORT UART10_IRQHandler [WEAK]
EXPORT UART11_IRQHandler [WEAK]
EXPORT I2C2_IRQHandler [WEAK]
EXPORT I2C3_IRQHandler [WEAK]
EXPORT I2S1_IRQHandler [WEAK]
EXPORT CANFD10_IRQHandler [WEAK]
EXPORT SC1_IRQHandler [WEAK]
EXPORT GPK_IRQHandler [WEAK]
EXPORT GPL_IRQHandler [WEAK]
EXPORT GPM_IRQHandler [WEAK]
EXPORT GPN_IRQHandler [WEAK]
EXPORT TMR8_IRQHandler [WEAK]
EXPORT TMR9_IRQHandler [WEAK]
EXPORT TMR10_IRQHandler [WEAK]
EXPORT TMR11_IRQHandler [WEAK]
EXPORT BRAKE2_IRQHandler [WEAK]
EXPORT EPWM2P0_IRQHandle [WEAK]
EXPORT EPWM2P1_IRQHandle [WEAK]
EXPORT EPWM2P2_IRQHandle [WEAK]
EXPORT QEI2_IRQHandler [WEAK]
EXPORT ECAP2_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART12_IRQHandler [WEAK]
EXPORT UART13_IRQHandler [WEAK]
EXPORT UART14_IRQHandler [WEAK]
EXPORT UART15_IRQHandler [WEAK]
EXPORT UART16_IRQHandler [WEAK]
EXPORT I2C4_IRQHandler [WEAK]
EXPORT I2C5_IRQHandler [WEAK]
EXPORT CANFD20_IRQHandler [WEAK]
EXPORT CANFD30_IRQHandler [WEAK]
EXPORT KPI_IRQHandler [WEAK]
EXPORT CANFD01_IRQHandler [WEAK]
EXPORT CANFD11_IRQHandler [WEAK]
EXPORT CANFD21_IRQHandler [WEAK]
EXPORT CANFD31_IRQHandler [WEAK]
EXPORT ADC0_IRQHandler [WEAK]
LVD_IRQHandler
PWRWU_IRQHandler
HWSEM0_IRQHandler
CKFAIL_IRQHandler
WHC0_IRQHandler
RTC_IRQHandler
TAMPER_IRQHandler
WDT2_IRQHandler
WWDT2_IRQHandler
EINT0_IRQHandler
EINT1_IRQHandler
EINT2_IRQHandler
EINT3_IRQHandler
GPA_IRQHandler
GPB_IRQHandler
GPC_IRQHandler
GPD_IRQHandler
TMR2_IRQHandler
TMR3_IRQHandler
BRAKE0_IRQHandler
EPWM0P0_IRQHandler
EPWM0P1_IRQHandler
EPWM0P2_IRQHandler
QEI0_IRQHandler
ECAP0_IRQHandler
QSPI1_IRQHandler
UART1_IRQHandler
UART2_IRQHandler
UART3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
EADC00_IRQHandler
EADC01_IRQHandler
EADC02_IRQHandler
EADC03_IRQHandler
I2C1_IRQHandler
I2S0_IRQHandler
CANFD00_IRQHandler
SC0_IRQHandler
GPE_IRQHandler
GPF_IRQHandler
GPG_IRQHandler
GPH_IRQHandler
GPI_IRQHandler
GPJ_IRQHandler
TMR4_IRQHandler
TMR5_IRQHandler
TMR6_IRQHandler
TMR7_IRQHandler
BRAKE1_IRQHandler
EPWM1P0_IRQHandler
EPWM1P1_IRQHandler
EPWM1P2_IRQHandler
QEI1_IRQHandler
ECAP1_IRQHandler
SPI0_IRQHandler
SPI1_IRQHandler
PDMA2_IRQHandler
PDMA3_IRQHandler
UART6_IRQHandler
UART7_IRQHandler
UART8_IRQHandler
UART9_IRQHandler
UART10_IRQHandler
UART11_IRQHandler
I2C2_IRQHandler
I2C3_IRQHandler
I2S1_IRQHandler
CANFD10_IRQHandler
SC1_IRQHandler
GPK_IRQHandler
GPL_IRQHandler
GPM_IRQHandler
GPN_IRQHandler
TMR8_IRQHandler
TMR9_IRQHandler
TMR10_IRQHandler
TMR11_IRQHandler
BRAKE2_IRQHandler
EPWM2P0_IRQHandle
EPWM2P1_IRQHandle
EPWM2P2_IRQHandle
QEI2_IRQHandler
ECAP2_IRQHandler
SPI2_IRQHandler
SPI3_IRQHandler
UART12_IRQHandler
UART13_IRQHandler
UART14_IRQHandler
UART15_IRQHandler
UART16_IRQHandler
I2C4_IRQHandler
I2C5_IRQHandler
CANFD20_IRQHandler
CANFD30_IRQHandler
KPI_IRQHandler
CANFD01_IRQHandler
CANFD11_IRQHandler
CANFD21_IRQHandler
CANFD31_IRQHandler
ADC0_IRQHandler
B .
ENDP
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap PROC
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ENDP
ALIGN
ENDIF
END

352
bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Source/GCC/startup_ma35d1_subm.S Normal file
View File

@ -0,0 +1,352 @@
/****************************************************************************//**
* @file startup_ma35d1_subm.S
* @brief CMSIS Cortex-M4 Core Device Startup File
*
* SPDX-License-Identifier: Apache-2.0
* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
.syntax unified
.cpu cortex-m4
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval : None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
#ifndef __NO_SYSTEM_INIT
bl SystemInit
#endif
/* Copy the data segment initializers from flash to SRAM */
movs r1, #0
b LoopCopyDataInit
CopyDataInit:
ldr r3, =_sidata
ldr r3, [r3, r1]
str r3, [r0, r1]
adds r1, r1, #4
LoopCopyDataInit:
ldr r0, =_sdata
ldr r3, =_edata
adds r2, r0, r1
cmp r2, r3
bcc CopyDataInit
ldr r2, =_sbss
b LoopFillZerobss
/* Zero fill the bss segment. */
FillZerobss:
movs r3, #0
str r3, [r2], #4
LoopFillZerobss:
ldr r3, = _ebss
cmp r2, r3
bcc FillZerobss
/* Call the application's entry point.*/
bl entry
bx lr
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
* @param None
* @retval None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The minimal vector table for a Cortex M4. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.word _estack /* Top of Stack */
.word Reset_Handler /* Reset Handler */
.word NMI_Handler /* NMI Handler */
.word HardFault_Handler /* Hard Fault Handler */
.word MemManage_Handler /* MPU Fault Handler */
.word BusFault_Handler /* Bus Fault Handler */
.word UsageFault_Handler /* Usage Fault Handler */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word SVC_Handler /* SVCall Handler */
.word DebugMon_Handler /* Debug Monitor Handler */
.word 0 /* Reserved */
.word PendSV_Handler /* PendSV Handler */
.word SysTick_Handler /* SysTick Handler */
/* External interrupts */
.word LVD_IRQHandler /* 0 */
.word 0 /* 1 */
.word PWRWU_IRQHandler /* 2 */
.word HWSEM0_IRQHandler /* 3 */
.word CKFAIL_IRQHandler /* 4 */
.word WHC0_IRQHandler /* 5 */
.word RTC_IRQHandler /* 6 */
.word TAMPER_IRQHandler /* 7 */
.word WDT2_IRQHandler /* 8 */
.word WWDT2_IRQHandler /* 9 */
.word EINT0_IRQHandler /* 10 */
.word EINT1_IRQHandler /* 11 */
.word EINT2_IRQHandler /* 12 */
.word EINT3_IRQHandler /* 13 */
.word 0 /* 14 */
.word 0 /* 15 */
.word GPA_IRQHandler /* 16 */
.word GPB_IRQHandler /* 17 */
.word GPC_IRQHandler /* 18 */
.word GPD_IRQHandler /* 19 */
.word 0 /* 20 */
.word 0 /* 21 */
.word TMR2_IRQHandler /* 22 */
.word TMR3_IRQHandler /* 23 */
.word BRAKE0_IRQHandler /* 24 */
.word EPWM0P0_IRQHandler /* 25 */
.word EPWM0P1_IRQHandler /* 26 */
.word EPWM0P2_IRQHandler /* 27 */
.word QEI0_IRQHandler /* 28 */
.word ECAP0_IRQHandler /* 29 */
.word 0 /* 30 */
.word QSPI1_IRQHandler /* 31 */
.word 0 /* 32 */
.word 0 /* 33 */
.word 0 /* 34 */
.word UART1_IRQHandler /* 35 */
.word UART2_IRQHandler /* 36 */
.word UART3_IRQHandler /* 37 */
.word UART4_IRQHandler /* 38 */
.word UART5_IRQHandler /* 39 */
.word EADC00_IRQHandler /* 40 */
.word EADC01_IRQHandler /* 41 */
.word EADC02_IRQHandler /* 42 */
.word EADC03_IRQHandler /* 43 */
.word 0 /* 44 */
.word I2C1_IRQHandler /* 45 */
.word I2S0_IRQHandler /* 46 */
.word MCAN00_IRQHandler /* 47 */
.word SC0_IRQHandler /* 48 */
.word GPE_IRQHandler /* 49 */
.word GPF_IRQHandler /* 50 */
.word GPG_IRQHandler /* 51 */
.word GPH_IRQHandler /* 52 */
.word GPI_IRQHandler /* 53 */
.word GPJ_IRQHandler /* 54 */
.word TMR4_IRQHandler /* 55 */
.word TMR5_IRQHandler /* 56 */
.word TMR6_IRQHandler /* 57 */
.word TMR7_IRQHandler /* 58 */
.word BRAKE1_IRQHandler /* 59 */
.word EPWM1P0_IRQHandler /* 60 */
.word EPWM1P1_IRQHandler /* 61 */
.word EPWM1P2_IRQHandler /* 62 */
.word QEI1_IRQHandler /* 63 */
.word ECAP1_IRQHandler /* 64 */
.word SPI0_IRQHandler /* 65 */
.word SPI1_IRQHandler /* 66 */
.word PDMA2_IRQHandler /* 67 */
.word PDMA3_IRQHandler /* 68 */
.word UART6_IRQHandler /* 69 */
.word UART7_IRQHandler /* 70 */
.word UART8_IRQHandler /* 71 */
.word UART9_IRQHandler /* 72 */
.word UART10_IRQHandler /* 73 */
.word UART11_IRQHandler /* 74 */
.word I2C2_IRQHandler /* 75 */
.word I2C3_IRQHandler /* 76 */
.word I2S1_IRQHandler /* 77 */
.word MACN10_IRQHandler /* 78 */
.word SC1_IRQHandler /* 79 */
.word GPK_IRQHandler /* 80 */
.word GPL_IRQHandler /* 81 */
.word GPM_IRQHandler /* 82 */
.word GPN_IRQHandler /* 83 */
.word TMR8_IRQHandler /* 84 */
.word TMR9_IRQHandler /* 85 */
.word TMR10_IRQHandler /* 86 */
.word TMR11_IRQHandler /* 87 */
.word BRAKE2_IRQHandler /* 88 */
.word EPWM2P0_IRQHandler /* 89 */
.word EPWM2P1_IRQHandler /* 90 */
.word EPWM2P2_IRQHandler /* 91 */
.word QEI2_IRQHandler /* 92 */
.word ECAP2_IRQHandler /* 93 */
.word SPI2_IRQHandler /* 94 */
.word SPI3_IRQHandler /* 95 */
.word UART12_IRQHandler /* 96 */
.word UART13_IRQHandler /* 97 */
.word UART14_IRQHandler /* 98 */
.word UART15_IRQHandler /* 99 */
.word UART16_IRQHandler /* 100 */
.word I2C4_IRQHandler /* 101 */
.word I2C5_IRQHandler /* 102 */
.word MCAN20_IRQHandler /* 103 */
.word MCAN30_IRQHandler /* 104 */
.word KPI_IRQHandler /* 105 */
.word MCAN01_IRQHandler /* 106 */
.word MCAN11_IRQHandler /* 107 */
.word MCAN21_IRQHandler /* 108 */
.word MCAN31_IRQHandler /* 109 */
.word ADC0_IRQHandler /* 110 */
/* Macro to define default handlers. Default handler
* will be weak symbol and just dead loops. They can be
* overwritten by other handlers */
.macro def_irq_handler handler_name
.weak \handler_name
.set \handler_name, Default_Handler
.endm
def_irq_handler NMI_Handler
def_irq_handler HardFault_Handler
def_irq_handler MemManage_Handler
def_irq_handler BusFault_Handler
def_irq_handler UsageFault_Handler
def_irq_handler SVC_Handler
def_irq_handler DebugMon_Handler
def_irq_handler PendSV_Handler
def_irq_handler SysTick_Handler
def_irq_handler LVD_IRQHandler
def_irq_handler PWRWU_IRQHandler
def_irq_handler HWSEM0_IRQHandler
def_irq_handler CKFAIL_IRQHandler
def_irq_handler WHC0_IRQHandler
def_irq_handler RTC_IRQHandler
def_irq_handler TAMPER_IRQHandler
def_irq_handler WDT2_IRQHandler
def_irq_handler WWDT2_IRQHandler
def_irq_handler EINT0_IRQHandler
def_irq_handler EINT1_IRQHandler
def_irq_handler EINT2_IRQHandler
def_irq_handler EINT3_IRQHandler
def_irq_handler GPA_IRQHandler
def_irq_handler GPB_IRQHandler
def_irq_handler GPC_IRQHandler
def_irq_handler GPD_IRQHandler
def_irq_handler TMR2_IRQHandler
def_irq_handler TMR3_IRQHandler
def_irq_handler BRAKE0_IRQHandler
def_irq_handler EPWM0P0_IRQHandler
def_irq_handler EPWM0P1_IRQHandler
def_irq_handler EPWM0P2_IRQHandler
def_irq_handler QEI0_IRQHandler
def_irq_handler ECAP0_IRQHandler
def_irq_handler QSPI1_IRQHandler
def_irq_handler UART1_IRQHandler
def_irq_handler UART2_IRQHandler
def_irq_handler UART3_IRQHandler
def_irq_handler UART4_IRQHandler
def_irq_handler UART5_IRQHandler
def_irq_handler EADC00_IRQHandler
def_irq_handler EADC01_IRQHandler
def_irq_handler EADC02_IRQHandler
def_irq_handler EADC03_IRQHandler
def_irq_handler I2C1_IRQHandler
def_irq_handler I2S0_IRQHandler
def_irq_handler MCAN00_IRQHandler
def_irq_handler SC0_IRQHandler
def_irq_handler GPE_IRQHandler
def_irq_handler GPF_IRQHandler
def_irq_handler GPG_IRQHandler
def_irq_handler GPH_IRQHandler
def_irq_handler GPI_IRQHandler
def_irq_handler GPJ_IRQHandler
def_irq_handler TMR4_IRQHandler
def_irq_handler TMR5_IRQHandler
def_irq_handler TMR6_IRQHandler
def_irq_handler TMR7_IRQHandler
def_irq_handler BRAKE1_IRQHandler
def_irq_handler EPWM1P0_IRQHandler
def_irq_handler EPWM1P1_IRQHandler
def_irq_handler EPWM1P2_IRQHandler
def_irq_handler QEI1_IRQHandler
def_irq_handler ECAP1_IRQHandler
def_irq_handler SPI0_IRQHandler
def_irq_handler SPI1_IRQHandler
def_irq_handler PDMA2_IRQHandler
def_irq_handler PDMA3_IRQHandler
def_irq_handler UART6_IRQHandler
def_irq_handler UART7_IRQHandler
def_irq_handler UART8_IRQHandler
def_irq_handler UART9_IRQHandler
def_irq_handler UART10_IRQHandler
def_irq_handler UART11_IRQHandler
def_irq_handler I2C2_IRQHandler
def_irq_handler I2C3_IRQHandler
def_irq_handler I2S1_IRQHandler
def_irq_handler MACN10_IRQHandler
def_irq_handler SC1_IRQHandler
def_irq_handler GPK_IRQHandler
def_irq_handler GPL_IRQHandler
def_irq_handler GPM_IRQHandler
def_irq_handler GPN_IRQHandler
def_irq_handler TMR8_IRQHandler
def_irq_handler TMR9_IRQHandler
def_irq_handler TMR10_IRQHandler
def_irq_handler TMR11_IRQHandler
def_irq_handler BRAKE2_IRQHandler
def_irq_handler EPWM2P0_IRQHandler
def_irq_handler EPWM2P1_IRQHandler
def_irq_handler EPWM2P2_IRQHandler
def_irq_handler QEI2_IRQHandler
def_irq_handler ECAP2_IRQHandler
def_irq_handler SPI2_IRQHandler
def_irq_handler SPI3_IRQHandler
def_irq_handler UART12_IRQHandler
def_irq_handler UART13_IRQHandler
def_irq_handler UART14_IRQHandler
def_irq_handler UART15_IRQHandler
def_irq_handler UART16_IRQHandler
def_irq_handler I2C4_IRQHandler
def_irq_handler I2C5_IRQHandler
def_irq_handler MCAN20_IRQHandler
def_irq_handler MCAN30_IRQHandler
def_irq_handler KPI_IRQHandler
def_irq_handler MCAN01_IRQHandler
def_irq_handler MCAN11_IRQHandler
def_irq_handler MCAN21_IRQHandler
def_irq_handler MCAN31_IRQHandler
def_irq_handler ADC0_IRQHandler
.end

430
bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Source/IAR/startup_ma35d1_subm.s Normal file
View File

@ -0,0 +1,430 @@
;/******************************************************************************
; * @file startup_subm.s
; * @brief CMSIS Cortex-M4 Core Device Startup File
; *
; * SPDX-License-Identifier: Apache-2.0
; * @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
;*****************************************************************************/
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN HardFault_Handler
EXTERN SystemInit
PUBLIC __vector_table
PUBLIC __vector_table_0x1c
PUBLIC __Vectors
PUBLIC __Vectors_End
PUBLIC __Vectors_Size
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler
DCD NMI_Handler
DCD HardFault_Handler
DCD MemManage_Handler
DCD BusFault_Handler
DCD UsageFault_Handler
__vector_table_0x1c
DCD 0
DCD 0
DCD 0
DCD 0
DCD SVC_Handler
DCD DebugMon_Handler
DCD 0
DCD PendSV_Handler
DCD SysTick_Handler
; External Interrupts
DCD LVD_IRQHandler ; 0
DCD Default_Handler ; 1
DCD PWRWU_IRQHandler ; 2
DCD HWSEM0_IRQHandler ; 3
DCD CKFAIL_IRQHandler ; 4
DCD WHC0_IRQHandler ; 5
DCD RTC_IRQHandler ; 6
DCD TAMPER_IRQHandler ; 7
DCD WDT2_IRQHandler ; 8
DCD WWDT2_IRQHandler ; 9
DCD EINT0_IRQHandler ; 10
DCD EINT1_IRQHandler ; 11
DCD EINT2_IRQHandler ; 12
DCD EINT3_IRQHandler ; 13
DCD Default_Handler ; 14
DCD Default_Handler ; 15
DCD GPA_IRQHandler ; 16
DCD GPB_IRQHandler ; 17
DCD GPC_IRQHandler ; 18
DCD GPD_IRQHandler ; 19
DCD Default_Handler ; 20
DCD Default_Handler ; 21
DCD TMR2_IRQHandler ; 22
DCD TMR3_IRQHandler ; 23
DCD BRAKE0_IRQHandler ; 24
DCD EPWM0P0_IRQHandler ; 25
DCD EPWM0P1_IRQHandler ; 26
DCD EPWM0P2_IRQHandler ; 27
DCD QEI0_IRQHandler ; 28
DCD ECAP0_IRQHandler ; 29
DCD Default_Handler ; 30
DCD QSPI1_IRQHandler ; 31
DCD Default_Handler ; 32
DCD Default_Handler ; 33
DCD Default_Handler ; 34
DCD UART1_IRQHandler ; 35
DCD UART2_IRQHandler ; 36
DCD UART3_IRQHandler ; 37
DCD UART4_IRQHandler ; 38
DCD UART5_IRQHandler ; 39
DCD EADC00_IRQHandler ; 40
DCD EADC01_IRQHandler ; 41
DCD EADC02_IRQHandler ; 42
DCD EADC03_IRQHandler ; 43
DCD Default_Handler ; 44
DCD I2C1_IRQHandler ; 45
DCD I2S0_IRQHandler ; 46
DCD MCAN00_IRQHandler ; 47
DCD SC0_IRQHandler ; 48
DCD GPE_IRQHandler ; 49
DCD GPF_IRQHandler ; 50
DCD GPG_IRQHandler ; 51
DCD GPH_IRQHandler ; 52
DCD GPI_IRQHandler ; 53
DCD GPJ_IRQHandler ; 54
DCD TMR4_IRQHandler ; 55
DCD TMR5_IRQHandler ; 56
DCD TMR6_IRQHandler ; 57
DCD TMR7_IRQHandler ; 58
DCD BRAKE1_IRQHandler ; 59
DCD EPWM1P0_IRQHandler ; 60
DCD EPWM1P1_IRQHandler ; 61
DCD EPWM1P2_IRQHandler ; 62
DCD QEI1_IRQHandler ; 63
DCD ECAP1_IRQHandler ; 64
DCD SPI0_IRQHandler ; 65
DCD SPI1_IRQHandler ; 66
DCD PDMA2_IRQHandler ; 67
DCD PDMA3_IRQHandler ; 68
DCD UART6_IRQHandler ; 69
DCD UART7_IRQHandler ; 70
DCD UART8_IRQHandler ; 71
DCD UART9_IRQHandler ; 72
DCD UART10_IRQHandler ; 73
DCD UART11_IRQHandler ; 74
DCD I2C2_IRQHandler ; 75
DCD I2C3_IRQHandler ; 76
DCD I2S1_IRQHandler ; 77
DCD MACN10_IRQHandler ; 78
DCD SC1_IRQHandler ; 79
DCD GPK_IRQHandler ; 80
DCD GPL_IRQHandler ; 81
DCD GPM_IRQHandler ; 82
DCD GPN_IRQHandler ; 83
DCD TMR8_IRQHandler ; 84
DCD TMR9_IRQHandler ; 85
DCD TMR10_IRQHandler ; 86
DCD TMR11_IRQHandler ; 87
DCD BRAKE2_IRQHandler ; 88
DCD EPWM2P0_IRQHandle ; 89
DCD EPWM2P1_IRQHandle ; 90
DCD EPWM2P2_IRQHandle ; 91
DCD QEI2_IRQHandler ; 92
DCD ECAP2_IRQHandler ; 93
DCD SPI2_IRQHandler ; 94
DCD SPI3_IRQHandler ; 95
DCD UART12_IRQHandler ; 96
DCD UART13_IRQHandler ; 97
DCD UART14_IRQHandler ; 98
DCD UART15_IRQHandler ; 99
DCD UART16_IRQHandler ; 100
DCD I2C4_IRQHandler ; 101
DCD I2C5_IRQHandler ; 102
DCD MCAN20_IRQHandler ; 103
DCD MCAN30_IRQHandler ; 104
DCD KPI_IRQHandler ; 105
DCD MCAN01_IRQHandler ; 106
DCD MCAN11_IRQHandler ; 107
DCD MCAN21_IRQHandler ; 108
DCD MCAN31_IRQHandler ; 109
DCD ADC0_IRQHandler ; 110
__Vectors_End
__Vectors EQU __vector_table
__Vectors_Size EQU __Vectors_End - __Vectors
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:REORDER:NOROOT(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
NMI_Handler
B NMI_Handler
PUBWEAK MemManage_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
UsageFault_Handler
B UsageFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SVC_Handler
B SVC_Handler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK LVD_IRQHandler
PUBWEAK PWRWU_IRQHandler
PUBWEAK HWSEM0_IRQHandler
PUBWEAK CKFAIL_IRQHandler
PUBWEAK WHC0_IRQHandler
PUBWEAK RTC_IRQHandler
PUBWEAK TAMPER_IRQHandler
PUBWEAK WDT2_IRQHandler
PUBWEAK WWDT2_IRQHandler
PUBWEAK EINT0_IRQHandler
PUBWEAK EINT1_IRQHandler
PUBWEAK EINT2_IRQHandler
PUBWEAK EINT3_IRQHandler
PUBWEAK GPA_IRQHandler
PUBWEAK GPB_IRQHandler
PUBWEAK GPC_IRQHandler
PUBWEAK GPD_IRQHandler
PUBWEAK TMR2_IRQHandler
PUBWEAK TMR3_IRQHandler
PUBWEAK BRAKE0_IRQHandler
PUBWEAK EPWM0P0_IRQHandler
PUBWEAK EPWM0P1_IRQHandler
PUBWEAK EPWM0P2_IRQHandler
PUBWEAK QEI0_IRQHandler
PUBWEAK ECAP0_IRQHandler
PUBWEAK QSPI1_IRQHandler
PUBWEAK UART1_IRQHandler
PUBWEAK UART2_IRQHandler
PUBWEAK UART3_IRQHandler
PUBWEAK UART4_IRQHandler
PUBWEAK UART5_IRQHandler
PUBWEAK EADC00_IRQHandler
PUBWEAK EADC01_IRQHandler
PUBWEAK EADC02_IRQHandler
PUBWEAK EADC03_IRQHandler
PUBWEAK I2C1_IRQHandler
PUBWEAK I2S0_IRQHandler
PUBWEAK MCAN00_IRQHandler
PUBWEAK SC0_IRQHandler
PUBWEAK GPE_IRQHandler
PUBWEAK GPF_IRQHandler
PUBWEAK GPG_IRQHandler
PUBWEAK GPH_IRQHandler
PUBWEAK GPI_IRQHandler
PUBWEAK GPJ_IRQHandler
PUBWEAK TMR4_IRQHandler
PUBWEAK TMR5_IRQHandler
PUBWEAK TMR6_IRQHandler
PUBWEAK TMR7_IRQHandler
PUBWEAK BRAKE1_IRQHandler
PUBWEAK EPWM1P0_IRQHandler
PUBWEAK EPWM1P1_IRQHandler
PUBWEAK EPWM1P2_IRQHandler
PUBWEAK QEI1_IRQHandler
PUBWEAK ECAP1_IRQHandler
PUBWEAK SPI0_IRQHandler
PUBWEAK SPI1_IRQHandler
PUBWEAK PDMA2_IRQHandler
PUBWEAK PDMA3_IRQHandler
PUBWEAK UART6_IRQHandler
PUBWEAK UART7_IRQHandler
PUBWEAK UART8_IRQHandler
PUBWEAK UART9_IRQHandler
PUBWEAK UART10_IRQHandler
PUBWEAK UART11_IRQHandler
PUBWEAK I2C2_IRQHandler
PUBWEAK I2C3_IRQHandler
PUBWEAK I2S1_IRQHandler
PUBWEAK MACN10_IRQHandler
PUBWEAK SC1_IRQHandler
PUBWEAK GPK_IRQHandler
PUBWEAK GPL_IRQHandler
PUBWEAK GPM_IRQHandler
PUBWEAK GPN_IRQHandler
PUBWEAK TMR8_IRQHandler
PUBWEAK TMR9_IRQHandler
PUBWEAK TMR10_IRQHandler
PUBWEAK TMR11_IRQHandler
PUBWEAK BRAKE2_IRQHandler
PUBWEAK EPWM2P0_IRQHandle
PUBWEAK EPWM2P1_IRQHandle
PUBWEAK EPWM2P2_IRQHandle
PUBWEAK QEI2_IRQHandler
PUBWEAK ECAP2_IRQHandler
PUBWEAK SPI2_IRQHandler
PUBWEAK SPI3_IRQHandler
PUBWEAK UART12_IRQHandler
PUBWEAK UART13_IRQHandler
PUBWEAK UART14_IRQHandler
PUBWEAK UART15_IRQHandler
PUBWEAK UART16_IRQHandler
PUBWEAK I2C4_IRQHandler
PUBWEAK I2C5_IRQHandler
PUBWEAK MCAN20_IRQHandler
PUBWEAK MCAN30_IRQHandler
PUBWEAK KPI_IRQHandler
PUBWEAK MCAN01_IRQHandler
PUBWEAK MCAN11_IRQHandler
PUBWEAK MCAN21_IRQHandler
PUBWEAK MCAN31_IRQHandler
PUBWEAK ADC0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
LVD_IRQHandler
PWRWU_IRQHandler
HWSEM0_IRQHandler
CKFAIL_IRQHandler
WHC0_IRQHandler
RTC_IRQHandler
TAMPER_IRQHandler
WDT2_IRQHandler
WWDT2_IRQHandler
EINT0_IRQHandler
EINT1_IRQHandler
EINT2_IRQHandler
EINT3_IRQHandler
GPA_IRQHandler
GPB_IRQHandler
GPC_IRQHandler
GPD_IRQHandler
TMR2_IRQHandler
TMR3_IRQHandler
BRAKE0_IRQHandler
EPWM0P0_IRQHandler
EPWM0P1_IRQHandler
EPWM0P2_IRQHandler
QEI0_IRQHandler
ECAP0_IRQHandler
QSPI1_IRQHandler
UART1_IRQHandler
UART2_IRQHandler
UART3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
EADC00_IRQHandler
EADC01_IRQHandler
EADC02_IRQHandler
EADC03_IRQHandler
I2C1_IRQHandler
I2S0_IRQHandler
MCAN00_IRQHandler
SC0_IRQHandler
GPE_IRQHandler
GPF_IRQHandler
GPG_IRQHandler
GPH_IRQHandler
GPI_IRQHandler
GPJ_IRQHandler
TMR4_IRQHandler
TMR5_IRQHandler
TMR6_IRQHandler
TMR7_IRQHandler
BRAKE1_IRQHandler
EPWM1P0_IRQHandler
EPWM1P1_IRQHandler
EPWM1P2_IRQHandler
QEI1_IRQHandler
ECAP1_IRQHandler
SPI0_IRQHandler
SPI1_IRQHandler
PDMA2_IRQHandler
PDMA3_IRQHandler
UART6_IRQHandler
UART7_IRQHandler
UART8_IRQHandler
UART9_IRQHandler
UART10_IRQHandler
UART11_IRQHandler
I2C2_IRQHandler
I2C3_IRQHandler
I2S1_IRQHandler
MACN10_IRQHandler
SC1_IRQHandler
GPK_IRQHandler
GPL_IRQHandler
GPM_IRQHandler
GPN_IRQHandler
TMR8_IRQHandler
TMR9_IRQHandler
TMR10_IRQHandler
TMR11_IRQHandler
BRAKE2_IRQHandler
EPWM2P0_IRQHandle
EPWM2P1_IRQHandle
EPWM2P2_IRQHandle
QEI2_IRQHandler
ECAP2_IRQHandler
SPI2_IRQHandler
SPI3_IRQHandler
UART12_IRQHandler
UART13_IRQHandler
UART14_IRQHandler
UART15_IRQHandler
UART16_IRQHandler
I2C4_IRQHandler
I2C5_IRQHandler
MCAN20_IRQHandler
MCAN30_IRQHandler
KPI_IRQHandler
MCAN01_IRQHandler
MCAN11_IRQHandler
MCAN21_IRQHandler
MCAN31_IRQHandler
ADC0_IRQHandler
Default_Handler
B Default_Handler
END

67
bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Source/system_ma35d1_subm.c Normal file
View File

@ -0,0 +1,67 @@
/**************************************************************************//**
* @file startup_subm.c
* @brief CMSIS Cortex-M4 Core Peripheral Access Layer Source File
*
* SPDX-License-Identifier: Apache-2.0
* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#include "NuMicro.h"
/*----------------------------------------------------------------------------
DEFINES
*----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------
Clock Variable definitions
*----------------------------------------------------------------------------*/
uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/
uint32_t CyclesPerUs = (__HSI / 1000000UL); /* Cycles per micro second */
/*----------------------------------------------------------------------------
Clock functions
*----------------------------------------------------------------------------*/
void SystemCoreClockUpdate(void) /* Get Core Clock Frequency */
{
/* Update System Core Clock */
SystemCoreClock = 180000000;
CyclesPerUs = (SystemCoreClock + 500000UL) / 1000000UL;
}
/**
* @brief Set PF.2 and PF.3 to input mode
* @param None
* @return None
* @details GPIO default state could be configured as input or quasi through user config.
* To use HXT, PF.2 and PF.3 must not set as quasi mode. This function changes
* PF.2 and PF.3 to input mode no matter which mode they are working at.
*/
/**
* @brief Initialize the System
*
* @param none
* @return none
*/
void SystemInit(void)
{
/* Add your system initialize code here.
Do not use global variables because this function is called before
reaching pre-main. RW section maybe overwritten afterwards. */
/* FPU settings ------------------------------------------------------------*/
#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
SCB->CPACR |= ((3UL << 10 * 2) | /* set CP10 Full Access */
(3UL << 11 * 2)); /* set CP11 Full Access */
#endif
}

22
bsp/nuvoton/libraries/ma35/Device/SConscript Normal file
View File

@ -0,0 +1,22 @@
import rtconfig
Import('RTT_ROOT')
from building import *
# get current directory
cwd = GetCurrentDir()
src = []
if GetDepend('USE_MA35D1_SUBM'):
src += ['Nuvoton/MA35D1/Source/system_ma35d1_subm.c']
if rtconfig.CROSS_TOOL == 'gcc':
src = src + ['Nuvoton/MA35D1/Source/GCC/startup_ma35d1_subm.S']
elif rtconfig.CROSS_TOOL == 'keil':
src = src + ['Nuvoton/MA35D1/Source/ARM/startup_ma35d1_subm.s']
elif rtconfig.CROSS_TOOL == 'iar':
src = src + ['Nuvoton/MA35D1/Source/IAR/startup_ma35d1_subm.s']
path = [cwd + '/Nuvoton/MA35D1/Include',]
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path)
Return('group')

38
bsp/nuvoton/libraries/ma35/README.md Normal file
View File

@ -0,0 +1,38 @@
# MA35 Series
## MA35D1 Series Supported drivers
| Peripheral | rt_device_class_type | Device name |
| ------ | ---- | :------: |
| ADC_TOUCH | RT_Device_Class_Touch | ***adc_touch*** |
| CANFD | RT_Device_Class_CAN | ***canfd[0-3]*** |
| CCAP | RT_Device_Class_Miscellaneous | ***ccap[0-1]*** |
| DISP | RT_Device_Class_Grapnis () | ***dac[0-1]*** |
| EADC | RT_Device_Class_Miscellaneous (ADC) | ***eadc[0-1]*** |
| ECAP | RT_Device_Class_Miscellaneous (Input capture) | ***ecap[0-1]i[0-2]*** |
| GMAC | RT_Device_Class_NetIf | ***e[0-1]*** |
| EPWM | RT_Device_Class_Miscellaneous (PWM) | ***epwm[0-1]*** |
| EPWM (Capture function) | RT_Device_Class_Miscellaneous (Input capture) | ***epwm[0-1]i[0-5]*** |
| GPIO | RT_Device_Class_Miscellaneous (Pin) | ***gpio*** |
| GPIO | RT_Device_Class_I2CBUS | ***softi2c0[0-1]*** |
| I2C | RT_Device_Class_I2CBUS | ***i2c[0-4]*** |
| I2S | RT_Device_Class_Sound/RT_Device_Class_Pipe | ***sound[0, 1]*** |
| PDMA | N/A | ***N/A*** |
| QEI | RT_Device_Class_Miscellaneous (Pulse encoder) | ***qei[0-1]*** |
| QSPI | RT_Device_Class_SPIBUS | ***qspi[0-1]*** |
| RTC | RT_Device_Class_RTC | ***rtc*** |
| RTP | N/A | N/A |
| SC (UART function) | RT_Device_Class_Char | ***scuart[0-2]*** |
| SDIO | RT_Device_Class_Sdio | ***sdio[0-1]*** |
| SPI | RT_Device_Class_SPIBUS | ***spi[0-10]*** |
| SPI (I2S function) | RT_Device_Class_Sound/RT_Device_Class_Pipe | ***spii2s[0-10]*** |
| TIMER | RT_Device_Class_Timer | ***timer[0-3]*** |
| TIMER (PWM function) | RT_Device_Class_Miscellaneous (PWM) | ***tpwm[0-3]*** |
| UART | RT_Device_Class_Char | ***uart[0-7]*** |
| USBH, HSUSBH | RT_Device_Class_USBHost | ***usbh*** |
| WDT | RT_Device_Class_Miscellaneous (Watchdog) | ***wdt*** |
## Resources
* [Download MA35D1 TRM][1]
[1]:

15
bsp/nuvoton/libraries/ma35/SConscript Normal file
View File

@ -0,0 +1,15 @@
# RT-Thread building script for bridge
import os
from building import *
cwd = GetCurrentDir()
objs = []
list = os.listdir(cwd)
for d in list:
path = os.path.join(cwd, d)
if os.path.isfile(os.path.join(path, 'SConscript')):
objs = objs + SConscript(os.path.join(d, 'SConscript'))
Return('objs')

13
bsp/nuvoton/libraries/ma35/StdDriver/SConscript Normal file
View File

@ -0,0 +1,13 @@
# RT-Thread building script for component
Import('rtconfig')
from building import *
cwd = GetCurrentDir()
libs = []
src = Glob('*src/*.c') + Glob('src/*.cpp')
cpppath = [cwd + '/inc']
libpath = [cwd + '/lib']
group = DefineGroup('Libraries', src, depend = [''], CPPPATH = cpppath)
Return('group')

287
bsp/nuvoton/libraries/ma35/StdDriver/inc/nu_adc.h Normal file
View File

@ -0,0 +1,287 @@
/**************************************************************************//**
* @file nu_adc.h
* @brief ADC driver header file
*
* SPDX-License-Identifier: Apache-2.0
* @copyright(C) 2020 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __NU_ADC_H__
#define __NU_ADC_H__
#ifdef __cplusplus
extern "C"
{
#endif
/** @addtogroup Standard_Driver Standard Driver
@{
*/
/** @addtogroup ADC_Driver ADC Driver
@{
*/
/** @addtogroup ADC_EXPORTED_CONSTANTS ADC Exported Constants
@{
*/
#include "adc_reg.h"
#define ADC_CH_0_MASK (1UL << 0) /*!< ADC channel 0 mask \hideinitializer */
#define ADC_CH_1_MASK (1UL << 1) /*!< ADC channel 1 mask \hideinitializer */
#define ADC_CH_2_MASK (1UL << 2) /*!< ADC channel 2 mask \hideinitializer */
#define ADC_CH_3_MASK (1UL << 3) /*!< ADC channel 3 mask \hideinitializer */
#define ADC_CH_4_MASK (1UL << 4) /*!< ADC channel 4 mask \hideinitializer */
#define ADC_CH_5_MASK (1UL << 5) /*!< ADC channel 5 mask \hideinitializer */
#define ADC_CH_6_MASK (1UL << 6) /*!< ADC channel 6 mask \hideinitializer */
#define ADC_CH_7_MASK (1UL << 7) /*!< ADC channel 7 mask \hideinitializer */
#define ADC_CH_NUM 8 /*!< Total Channel number \hideinitializer */
#define ADC_HIGH_SPEED_MODE ADC_CONF_SPEED_Msk /*!< ADC working in high speed mode (3.2MHz <= ECLK <= 16MHz) \hideinitializer */
#define ADC_NORMAL_SPEED_MODE 0 /*!< ADC working in normal speed mode (ECLK < 3.2MHz) \hideinitializer */
#define ADC_REFSEL_VREF 0 /*!< ADC reference voltage source selection set to VREF \hideinitializer */
#define ADC_REFSEL_AVDD (3UL << ADC_CONF_REFSEL_Pos) /*!< ADC reference voltage source selection set to AVDD \hideinitializer */
#define ADC_INPUT_MODE_NORMAL_CONV 0 /*!< ADC works in normal conversion mode \hideinitializer */
#define ADC_INPUT_MODE_4WIRE_TOUCH 1 /*!< ADC works in 4-wire touch screen mode \hideinitializer */
#define ADC_INPUT_MODE_5WIRE_TOUCH 2 /*!< ADC works in 5-wire touch screen mode \hideinitializer */
/*@}*/ /* end of group ADC_EXPORTED_CONSTANTS */
/** @addtogroup ADC_EXPORTED_FUNCTIONS ADC Exported Functions
@{
*/
/**
* @brief Get the latest ADC conversion data
* @param[in] adc Base address of ADC module
* @param[in] u32ChNum Currently not used
* @return Latest ADC conversion data
* \hideinitializer
*/
#define ADC_GET_CONVERSION_DATA(adc, u32ChNum) ((adc)->DATA)
/**
* @brief Get the latest ADC conversion X data
* @param[in] adc Base address of ADC module
* @return Latest ADC conversion X data
* \hideinitializer
*/
#define ADC_GET_CONVERSION_XDATA(adc) ((adc)->XYDATA & ADC_XYDATA_XDATA_Msk)
/**
* @brief Get the latest ADC conversion Y data
* @param[in] adc Base address of ADC module
* @return Latest ADC conversion Y data
* \hideinitializer
*/
#define ADC_GET_CONVERSION_YDATA(adc) ((adc)->XYDATA >> ADC_XYDATA_YDATA_Pos)
/**
* @brief Get the latest ADC conversion Z1 data
* @param[in] adc Base address of ADC module
* @return Latest ADC conversion Z1 data
* \hideinitializer
*/
#define ADC_GET_CONVERSION_Z1DATA(adc) ((adc)->ZDATA & ADC_ZDATA_Z1DATA_Msk)
/**
* @brief Get the latest ADC conversion Z2 data
* @param[in] adc Base address of ADC module
* @return Latest ADC conversion Z2 data
* \hideinitializer
*/
#define ADC_GET_CONVERSION_Z2DATA(adc) ((adc)->ZDATA >> ADC_ZDATA_Z2DATA_Pos)
/**
* @brief Return the user-specified interrupt flags
* @param[in] adc Base address of ADC module
* @param[in] u32Mask Could be \ref ADC_IER_MIEN_Msk
* @return User specified interrupt flags
* \hideinitializer
*/
#define ADC_GET_INT_FLAG(adc, u32Mask) ((adc)->ISR & (u32Mask))
/**
* @brief This macro clear the selected interrupt status bits
* @param[in] adc Base address of ADC module
* @param[in] u32Mask Could be \ref ADC_IER_MIEN_Msk
* @return None
* \hideinitializer
*/
#define ADC_CLR_INT_FLAG(adc, u32Mask) ((adc)->ISR = (u32Mask))
/**
* @brief Return the user-specified interrupt flags
* @param[in] adc Base address of ADC module
* @param[in] u32Mask Could be \ref ADC_IER_MIEN_Msk
* @return User specified interrupt flags
* \hideinitializer
*/
#define ADC_GET_WKINT_FLAG(adc, u32Mask) ((adc)->WKISR & (u32Mask))
/**
* @brief Enable the interrupt(s) selected by u32Mask parameter.
* @param[in] adc Base address of ADC module
* @param[in] u32Mask Could be \ref ADC_IER_MIEN_Msk
* @return None
*/
#define ADC_ENABLE_INT(adc, u32Mask) ((adc)->IER |= u32Mask)
/**
* @brief Disable the interrupt(s) selected by u32Mask parameter.
* @param[in] adc Base address of ADC module
* @param[in] u32Mask Could be \ref ADC_IER_MIEN_Msk
* @return None
*/
#define ADC_DISABLE_INT(adc, u32Mask) ((adc)->IER &= ~u32Mask)
/**
* @brief Power down ADC module
* @param[in] adc Base address of ADC module
* @return None
* \hideinitializer
*/
#define ADC_POWER_DOWN(adc) ((adc)->CTL &= ~ADC_CTL_ADEN_Msk)
/**
* @brief Power on ADC module
* @param[in] adc Base address of ADC module
* @return None
* \hideinitializer
*/
#define ADC_POWER_ON(adc) ((adc)->CTL |= ADC_CTL_ADEN_Msk)
/**
* @brief Set ADC input channel. Enabled channel will be converted while ADC starts.
* @param[in] adc Base address of ADC module
* @param[in] u32Mask Channel enable bit. Each bit corresponds to a input channel. Bit 0 is channel 0, bit 1 is channel 1...
* @return None
* @note ADC can only convert 1 channel at a time. If more than 1 channels are enabled, only channel
* with smallest number will be convert.
* \hideinitializer
*/
#define ADC_SET_INPUT_CHANNEL(adc, u32Mask) do {uint32_t u32Ch = 0, i;\
for(i = 0; i < ADC_CH_NUM; i++) {\
if((u32Mask) & (1 << i)) {\
u32Ch = i;\
break;\
}\
}\
(adc)->CONF = ((adc)->CONF & ~ADC_CONF_CHSEL_Msk) | (u32Ch << ADC_CONF_CHSEL_Pos);\
}while(0)
/**
* @brief Start the A/D conversion.
* @param[in] adc Base address of ADC module
* @return None
* \hideinitializer
*/
#define ADC_START_CONV(adc) ((adc)->CTL |= ADC_CTL_MST_Msk)
/**
* @brief Set the reference voltage selection.
* @param[in] adc Base address of ADC module
* @param[in] u32Ref The reference voltage selection. Valid values are:
* - \ref ADC_REFSEL_VREF
* - \ref ADC_REFSEL_AVDD
* @return None
* \hideinitializer
*/
#define ADC_SET_REF_VOLTAGE(adc, u32Ref) ((adc)->CONF = ((adc)->CONF & ~ADC_CONF_REFSEL_Msk) | (u32Ref))
/**
* @brief Set ADC to convert X/Y coordinate
* @param[in] adc Base address of ADC module
* @return None
* \hideinitializer
*/
#define ADC_CONVERT_XY_MODE(adc) do {(adc)->CTL &= ~ADC_CTL_PEDEEN_Msk;\
(adc)->CONF |= ADC_CONF_TEN_Msk | ADC_CONF_ZEN_Msk;} while(0)
/**
* @brief Set ADC to detect pen down event
* @param[in] adc Base address of ADC module
* @return None
* \hideinitializer
*/
#define ADC_DETECT_PD_MODE(adc) do {(adc)->CONF &= ~(ADC_CONF_TEN_Msk | ADC_CONF_ZEN_Msk);\
(adc)->CTL |= ADC_CTL_PEDEEN_Msk;} while(0)
#define ADC_CONF_REFSEL_VREF (0<<ADC_CONF_REFSEL_Pos) /*!< ADC reference select VREF input or 2.5v buffer output */
#define ADC_CONF_REFSEL_YMYP (1<<ADC_CONF_REFSEL_Pos) /*!< ADC reference select YM vs YP */
#define ADC_CONF_REFSEL_XMXP (2<<ADC_CONF_REFSEL_Pos) /*!< ADC reference select XM vs XP */
#define ADC_CONF_REFSEL_AVDD33 (3<<ADC_CONF_REFSEL_Pos) /*!< ADC reference select AGND33 vs AVDD33 */
/** \brief Structure type of ADC_CMD
*/
typedef enum
{
START_MST, /*!<Menu Start Conversion with interrupt */
START_MST_POLLING, /*!<Menu Start Conversion with polling */
VBPOWER_ON, /*!<Enable ADC Internal Bandgap Power */
VBPOWER_OFF, /*!<Disable ADC Internal Bandgap Power */
VBAT_ON, /*!<Enable Voltage Battery conversion function */
VBAT_OFF, /*!<Disable Voltage Battery conversion function */
KPPOWER_ON, /*!<Enable ADC Keypad power */
KPPOWER_OFF, /*!<Disable ADC Keypad power */
KPCONV_ON, /*!<Enable Keypad conversion function */
KPCONV_OFF, /*!<Disable Keypad conversion function */
KPPRESS_ON, /*!<Enable Keypad press event */
KPPRESS_OFF, /*!<Disable Keypad press event */
KPUP_ON, /*!<Enable Keypad up event */
KPUP_OFF, /*!<Disable Keypad up event */
PEPOWER_ON, /*!<Enable Pen Down Power ,It can control pen down event */
PEPOWER_OFF, /*!<Disable Pen Power */
PEDEF_ON, /*!<Enable Pen Down Event Flag */
PEDEF_OFF, /*!<Disable Pen Down Event Flag */
WKP_ON, /*!<Enable Keypad Press Wake Up */
WKP_OFF, /*!<Disable Keypad Press Wake Up */
WKT_ON, /*!<Enable Pen Down Wake Up */
WKT_OFF, /*!<Disable Pen Down Wake Up */
SWITCH_5WIRE_ON, /*!<Wire Mode Switch to 5-Wire Configuration */
SWITCH_5WIRE_OFF, /*!<Wire Mode Switch to 4-Wire Configuration */
T_ON, /*!<Enable Touch detection function */
T_OFF, /*!<Disable Touch detection function */
TAVG_ON, /*!<Enable Touch Mean average for X and Y function */
TAVG_OFF, /*!<Disable Touch Mean average for X and Y function */
Z_ON, /*!<Enable Press measure function */
Z_OFF, /*!<Disable Press measure function */
TZAVG_ON, /*!<Enable Pressure Mean average for Z1 and Z2 function */
TZAVG_OFF, /*!<Disable Pressure Mean average for Z1 and Z2 function */
NAC_ON, /*!<Enable Normal AD Conversion */
NAC_OFF, /*!<Disable Normal AD Conversion */
SWITCH_CH, /*!<Switch Channel */
} ADC_CMD;
typedef int32_t(*ADC_CALLBACK)(uint32_t status, uint32_t userData);
void ADC_Open(ADC_T *adc,
uint32_t u32InputMode,
uint32_t u32OpMode,
uint32_t u32ChMask);
void ADC_Close(ADC_T *adc);
void ADC_EnableInt(ADC_T *adc, uint32_t u32Mask);
void ADC_DisableInt(ADC_T *adc, uint32_t u32Mask);
/*@}*/ /* end of group ADC_EXPORTED_FUNCTIONS */
/*@}*/ /* end of group ADC_Driver */
/*@}*/ /* end of group Standard_Driver */
#ifdef __cplusplus
}
#endif
#endif //__NU_ADC_H__

476
bsp/nuvoton/libraries/ma35/StdDriver/inc/nu_canfd.h Normal file
View File

@ -0,0 +1,476 @@
/****************************************************************************
* @file nu_canfd.h
* @version V1.00
* @brief CAN FD driver source file
*
* SPDX-License-Identifier: Apache-2.0
* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __NU_CANFD_H__
#define __NU_CANFD_H__
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
#include "NuMicro.h"
#ifdef __cplusplus
extern "C"
{
#endif
/** @addtogroup Standard_Driver Standard Driver
@{
*/
/** @addtogroup CANFD_Driver CAN_FD Driver
@{
*/
/** @addtogroup CANFD_EXPORTED_CONSTANTS CAN_FD Exported Constants
@{
*/
#define CANFD_OP_CAN_MODE 0
#define CANFD_OP_CAN_FD_MODE 1
/* Reserved number of elements in Message RAM - used for calculation of start addresses within RAM Configuration
some element_numbers set to less than max, to stay altogether below 256 words of Message RAM requirement*/
#define CANFD_MAX_11_BIT_FTR_ELEMS 128ul /*!< maximum is 128 11-bit Filter */
#define CANFD_MAX_29_BIT_FTR_ELEMS 64ul /*!< maximum is 64 29-bit Filter */
#define CANFD_MAX_RX_FIFO0_ELEMS 64ul /*!< maximum is 64 Rx FIFO 0 elements */
#define CANFD_MAX_RX_FIFO1_ELEMS 64ul /*!< maximum is 64 Rx FIFO 1 elements */
#define CANFD_MAX_RX_BUF_ELEMS 64ul /*!< maximum is 64 Rx Buffers */
#define CANFD_MAX_TX_BUF_ELEMS 32ul /*!< maximum is 32 Tx Buffers */
#define CANFD_MAX_TX_EVNT_FIFO_ELEMS 32ul /*!< maximum is 32 Tx Event FIFO elements */
/* CAN FD sram size */
#define CANFD_SRAM_SIZE 0x2000ul
#define CANFD_SRAM_OFFSET 0x200ul
/* CAN FD sram address */
#define CANFD_SRAM_BASE_ADDR(psCanfd) ((uint32_t)psCanfd + CANFD_SRAM_OFFSET)
/* CAN FD Mask all interrupt */
#define CANFD_INT_ALL_SIGNALS 0x3FFFFFFFul
/* Maximum size of a CAN FD frame. Must be a valid CAN FD value */
#define CANFD_MAX_MESSAGE_BYTES 64
/* Maximum size of a CAN FD frame. Must be a valid CAN FD value */
#define CANFD_MAX_MESSAGE_WORDS (CANFD_MAX_MESSAGE_BYTES/4)
/* Receive message buffer helper macro */
#define CANFD_RX_BUFFER_STD(id, mbIdx) ((7UL << 27) | ((id & 0x7FF) << 16) | (mbIdx & 0x3F))
/* Receive message buffer extended helper macro - low */
#define CANFD_RX_BUFFER_EXT_LOW(id, mbIdx) ((7UL << 29) | (id & 0x1FFFFFFFUL))
/* Receive message buffer extended helper macro - high */
#define CANFD_RX_BUFFER_EXT_HIGH(id, mbIdx) (mbIdx & 0x3FUL)
/* CAN FD Rx FIFO 0 Mask helper macro. */
#define CANFD_RX_FIFO0_STD_MASK(match, mask) ((2UL << 30) | (1UL << 27) | ((match & 0x7FF) << 16) | (mask & 0x7FF))
/* CAN FD Rx FIFO 0 extended Mask helper macro - low. */
#define CANFD_RX_FIFO0_EXT_MASK_LOW(match) ((1UL << 29) | (match & 0x1FFFFFFF))
/* CAN FD Rx FIFO 0 extended Mask helper macro - high. */
#define CANFD_RX_FIFO0_EXT_MASK_HIGH(mask) ((2UL << 30) | (mask & 0x1FFFFFFF))
/* CAN FD Rx FIFO 1 Mask helper macro. */
#define CANFD_RX_FIFO1_STD_MASK(match, mask) ((2UL << 30) | (2UL << 27) | ((match & 0x7FF) << 16) | (mask & 0x7FF))
/* CANFD Rx FIFO 1 extended Mask helper macro - low. */
#define CANFD_RX_FIFO1_EXT_MASK_LOW(match) ((2UL << 29) | (match & 0x1FFFFFFF))
/* CANFD Rx FIFO 1 extended Mask helper macro - high. */
#define CANFD_RX_FIFO1_EXT_MASK_HIGH(mask) ((2UL << 30) | (mask & 0x1FFFFFFF))
/**
* @brief Get the CAN Communication State Flag
*
* @param[in] canfd The pointer of the specified CANFD module
*
* @retval 0 Synchronizing - node is synchronizing on CANFD communication.
* @retval 1 Idle - node is neither receiver nor transmitter.
* @retval 2 Receiver - node is operating as receiver.
* @retval 3 Transmitter - node is operating as transmitter.
*
* @details This macro gets the CANFD communication state.
* \hideinitializer
*/
#define CANFD_GET_COMMUNICATION_STATE(canfd) (((canfd)->PSR & CANFD_PSR_ACT_Msk) >> CANFD_PSR_ACT_Pos)
/* CAN FD frame data field size. */
typedef enum
{
eCANFD_BYTE8 = 0, /*!< 8 byte data field. */
eCANFD_BYTE12 = 1, /*!< 12 byte data field. */
eCANFD_BYTE16 = 2, /*!< 16 byte data field. */
eCANFD_BYTE20 = 3, /*!< 20 byte data field. */
eCANFD_BYTE24 = 4, /*!< 24 byte data field. */
eCANFD_BYTE32 = 5, /*!< 32 byte data field. */
eCANFD_BYTE48 = 6, /*!< 48 byte data field. */
eCANFD_BYTE64 = 7 /*!< 64 byte data field. */
} E_CANFD_DATA_FIELD_SIZE;
/* CAN FD Tx FIFO/Queue Mode. */
typedef enum
{
eCANFD_QUEUE_MODE = 0, /*!< Tx FIFO operation. */
eCANFD_FIFO_MODE = 1 /*!< Tx Queue operation. */
} E_CANFD_MODE;
/* CAN FD Test & Bus monitor Mode. */
typedef enum
{
eCANFD_NORMAL = 0, /*!< None, Normal mode. */
/*
Support:
(1) to receive data frames
(2) to receive remote frames
(3) to give acknowledge to valid frames
Not support:
(1) data frames sending
(2) remote frames sending
(3) active error frames or overload frames sending
*/
eCANFD_RESTRICTED_OPERATION, /*!< Receive external RX frame and always keep recessive state or send dominate bit on ACK bit on TX pin. */
/*
Support:
(1) to receive valid data frames
(2) to receive valid remote frames
Not support:
(1) transmission start
(2) acknowledge to valid frames
*/
eCANFD_BUS_MONITOR, /*!< Receive external RX frame and always keep recessive state on TX pin. */
/*
Support:
(1) Loopback
(2) Also send out frames
Not support:
(1) to receive external frame
*/
eCANFD_LOOPBACK_EXTERNAL, /*!< Won't receive external RX frame. */
/*
Support:
(1) Loopback
Not support:
(1) to receive external frame
(2) transmission start
*/
eCANFD_LOOPBACK_INTERNAL /*!< Won't receive external RX frame and always keep recessive state on TX pin */
} E_CANFD_TEST_MODE;
/* TX Buffer Configuration Parameters */
typedef struct
{
E_CANFD_DATA_FIELD_SIZE eDataFieldSize; /*!< TX Buffer Data Field Size (8byte .. 64byte) */
E_CANFD_MODE eModeSel; /*!< select: CANFD_QUEUE_MODE/CANFD_FIFO_MODE */
uint32_t u32ElemCnt; /*!< Elements in FIFO/Queue */
uint32_t u32DBufNumber; /*!< Number of dedicated TX buffers */
} CANFD_TX_BUF_CONFIG_T;
/* Nominal Bit Timing Parameters */
typedef struct
{
uint32_t u32BitRate; /*!< Transceiver baud rate in bps */
uint16_t u16TDCOffset; /*!< Transceiver Delay Compensation Offset */
uint16_t u16TDCFltrWin; /*!< Transceiver Delay Compensation Filter Window Length */
uint8_t u8TDC; /*!< Transceiver Delay Compensation (1:Yes, 0:No) */
} CANFD_NBT_CONFIG_T;
/* Data Bit Timing Parameters */
typedef struct
{
uint32_t u32BitRate; /*!< Transceiver baud rate in bps */
uint16_t u16TDCOffset; /*!< Transceiver Delay Compensation Offset */
uint16_t u16TDCFltrWin; /*!< Transceiver Delay Compensation Filter Window Length */
uint8_t u8TDC; /*!< Transceiver Delay Compensation (1:Yes, 0:No) */
} CANFD_DBT_CONFIG_T;
/*! CAN FD protocol timing characteristic configuration structure. */
typedef struct
{
uint8_t u8PreDivider; /*!< Global Clock Division Factor. */
uint16_t u16NominalPrescaler; /*!< Nominal clock prescaler. */
uint8_t u8NominalRJumpwidth; /*!< Nominal Re-sync Jump Width. */
uint8_t u8NominalPhaseSeg1; /*!< Nominal Phase Segment 1. */
uint8_t u8NominalPhaseSeg2; /*!< Nominal Phase Segment 2. */
uint8_t u8NominalPropSeg; /*!< Nominal Propagation Segment. */
uint8_t u8DataPrescaler; /*!< Data clock prescaler. */
uint8_t u8DataRJumpwidth; /*!< Data Re-sync Jump Width. */
uint8_t u8DataPhaseSeg1; /*!< Data Phase Segment 1. */
uint8_t u8DataPhaseSeg2; /*!< Data Phase Segment 2. */
uint8_t u8DataPropSeg; /*!< Data Propagation Segment. */
} CANFD_TIMEING_CONFIG_T;
/* CAN FD module configuration structure. */
typedef struct
{
CANFD_NBT_CONFIG_T sNormBitRate; /*!< Normal bit rate. */
CANFD_DBT_CONFIG_T sDataBitRate; /*!< Data bit rate. */
CANFD_TIMEING_CONFIG_T sConfigBitTing; /*!< Bit timing config*/
uint8_t bFDEn; /*!< 1 == FD Operation enabled. */
uint8_t bBitRateSwitch; /*!< 1 == Bit Rate Switch enabled (only evaluated in HW, if FD operation enabled). */
E_CANFD_TEST_MODE evTestMode; /*!< See E_CANFD_TEST_MODE declaration. */
} CANFD_FD_BT_CONFIG_T;
/* CAN FD Message RAM Partitioning - i.e. Start Addresses (BYTE) */
typedef struct
{
uint32_t u32SIDFC_FLSSA; /*!<Standard ID Filter Configuration */
uint32_t u32XIDFC_FLESA; /*!<Extended ID Filter Configuration */
uint32_t u32RXF0C_F0SA; /*!< RX FIFO 0 Start Address */
uint32_t u32RXF1C_F1SA; /*!< RX FIFO 1 Start Address */
uint32_t u32RXBC_RBSA; /*!< Rx Buffer Configuration */
uint32_t u32TXEFC_EFSA; /*!< Tx Event FIFO Configuration */
uint32_t u32TXBC_TBSA; /*!< Tx Buffer Configuration */
} CANFD_RAM_PART_T;
/*CAN FD element size structure */
typedef struct
{
uint32_t u32SIDFC; /*!< Standard Message ID Filter element size in words */
uint32_t u32XIDFC; /*!< Extended Message ID Filter element size in words */
uint32_t u32RxFifo0; /*!< Rx FIFO0 element size in words */
uint32_t u32RxFifo1; /*!< Rx FIFO1 element size in words */
uint32_t u32RxBuf; /*!< Rx Buffer element size in words */
uint32_t u32TxBuf; /*!< Tx Buffer element size in words */
uint32_t u32TxEventFifo; /*!< Tx Event FIFO element size in words */
} CANFD_ELEM_SIZE_T;
/* CAN FD Message frame structure */
typedef struct
{
CANFD_FD_BT_CONFIG_T sBtConfig; /*!< Bit Timing Configuration */
CANFD_RAM_PART_T sMRamStartAddr; /*!< Absolute Byte Start Addresses for Element Types in Message RAM */
CANFD_ELEM_SIZE_T sElemSize; /*!< Size of Elements in Message RAM (RX Elem. in FIFO0, in FIFO1, TX Buffer) given in words */
CANFD_TX_BUF_CONFIG_T sTxConfig; /*!< TX Buffer Configuration */
uint32_t u32MRamSize; /*!< Size of the Message RAM: number of words */
} CANFD_FD_T;
/* CAN FD Message ID Type */
typedef enum
{
eCANFD_SID = 0, /*!< Standard frame format attribute. */
eCANFD_XID = 1 /*!< Extend frame format attribute. */
} E_CANFD_ID_TYPE;
/* CAN FD Rx Message Type */
typedef enum
{
eCANFD_RX_FIFO_0 = 0,
eCANFD_RX_FIFO_1 = 1,
eCANFD_RX_DBUF = 2
} E_CANFD_RX_BUF_TYPE;
/* CAN FD communication state.*/
typedef enum
{
eCANFD_SYNC = 0,
eCANFD_IDLE = 1,
eCANFD_RECEIVER = 2,
eCANFD_TRANSMITTER = 3
} E_CANFD_COMMUNICATION_STATE;
/* CAN FD Message receive Information: via which RX Buffers, etc. */
typedef struct
{
E_CANFD_RX_BUF_TYPE eRxBuf; /*!< Type of RX Buffer */
uint32_t u32BufIdx; /*!< RX Buffer: buffer index, if RX FIFO: GetIndex */
} CANFD_RX_INFO_T;
/* CAN FD frame type. */
typedef enum
{
eCANFD_DATA_FRM = 0, /*!< Data frame type attribute. */
eCANFD_REMOTE_FRM = 1 /*!< Remote frame type attribute. */
} E_CANFD_FRM_TYPE;
/* CAN FD Message Struct */
typedef struct
{
E_CANFD_ID_TYPE eIdType; /*! Standard ID or Extended ID */
CANFD_RX_INFO_T sRxInfo; /*! Information regarding the reception of the frame */
E_CANFD_FRM_TYPE eFrmType; /*! eCANFD_DATA_FRM/eCANFD_REMOTE_FRM */
uint32_t u32Id; /*! Standard ID (11bits) or Extended ID (29bits) */
uint32_t u32DLC; /*! Data Length */
union
{
uint32_t au32Data[CANFD_MAX_MESSAGE_WORDS]; /*!< Word access to buffer data. */
uint8_t au8Data[CANFD_MAX_MESSAGE_BYTES]; /*!< Byte access to buffer data. */
};
uint8_t u8MsgMarker; /*! Message marker (will be copied to TX Event FIFO element) */
uint8_t bFDFormat; /*! FD Format (1 = FD Format) */
uint8_t bBitRateSwitch; /*! Bit Rate Switch (1 = with Bit Rate Switch) */
uint8_t bErrStaInd; /*! Error State Indicator */
uint8_t bEvntFifoCon; /*! Event FIFO Control (1 = Store TX Event FIFO element after transmission)*/
} CANFD_FD_MSG_T;
/* Transmit and Receive message element structure. */
typedef struct
{
uint32_t u32Id; /*!< Message identifier and associated flags. */
uint32_t u32Config; /*!< Buffer configuration. */
union
{
uint32_t au32Data[CANFD_MAX_MESSAGE_WORDS]; /*!< Word access to buffer data. */
uint8_t au8Data[CANFD_MAX_MESSAGE_BYTES]; /*!< Byte access to buffer data. */
};
} CANFD_BUF_T;
/* Standard ID message filter element structure.*/
typedef struct
{
union
{
struct
{
uint32_t SFID2 : 11; /*!<Standard Filter ID 2. */
uint32_t reserved1 : 5;
uint32_t SFID1 : 11; /*!<Standard Filter ID 1. */
uint32_t SFEC : 3; /*!<Standard Filter Element Configuration */
uint32_t SFT : 2; /*!<Standard Filter Type */
};
struct
{
uint32_t VALUE; /*!< Access to filter as a word. */
};
};
} CANFD_STD_FILTER_T;
/* Extended ID message filter element structure.*/
typedef struct
{
union
{
struct
{
uint32_t EFID1 : 29; /*!< Extended Filter ID 1. */
uint32_t EFEC : 3; /*!< Extended Filter Element Configuration. */
uint32_t EFID2 : 29; /*!< Extended Filter ID 2. */
uint32_t reserved1 : 1;
uint32_t EFT : 2; /*!< Extended Filter Type. */
};
struct
{
uint32_t LOWVALUE; /*!< Access to filter low word. */
uint32_t HIGHVALUE; /*!< Access to filter high word. */
};
};
} CANFD_EXT_FILTER_T;
/* Accept Non-matching Frames (GFC Register) */
typedef enum
{
eCANFD_ACC_NON_MATCH_FRM_RX_FIFO0 = 0x0, /*!< Accept Non-Masking Frames in Rx FIFO 0. */
eCANFD_ACC_NON_MATCH_FRM_RX_FIFO1 = 0x1, /*!< Accept Non-Masking Frames in Rx FIFO 1. */
eCANFD_REJ_NON_MATCH_FRM = 0x3 /*!< Reject Non-Matching Frames. */
} E_CANFD_ACC_NON_MATCH_FRM;
/* Standard ID Filter Element Type */
typedef enum
{
eCANFD_SID_FLTR_TYPE_RANGE = 0x0, /*!< Range filter from SFID1 to SFID2. */
eCANFD_SID_FLTR_TYPE_DUAL = 0x1, /*!< Dual ID filter for SFID1 or SFID2. */
eCANFD_SID_FLTR_TYPE_CLASSIC = 0x2, /*!< Classic filter: SFID1 = filter, SFID2 = mask. */
eCANFD_SID_FLTR_TYPE_DIS = 0x3 /*!< Filter element disabled */
} E_CANFD_SID_FLTR_ELEM_TYPE;
/* Extended ID Filter Element Type */
typedef enum
{
eCANFD_XID_FLTR_TYPE_RANGE = 0x0, /*!< Range filter from EFID1 to EFID2. */
eCANFD_XID_FLTR_TYPE_DUAL = 0x1, /*!< Dual ID filter for EFID1 or EFID2. */
eCANFD_XID_FLTR_TYPE_CLASSIC = 0x2, /*!< Classic filter: EFID1=filter, EFID2=mask */
eCANFD_XID_FLTR_TYPE_RANGE_XIDAM_NOT_APP = 0x3 /*!< XID range filter from EFID1 to EFID2(EFID2 > EFID1), XIDAM not applied */
} E_CANFD_XID_FLTR_ELEM_TYPE;
/* Filter Element Configuration - Can be used for SFEC(Standard Id filter configuration) and EFEC(Extended Id filter configuration) */
typedef enum
{
eCANFD_FLTR_ELEM_DIS = 0x0, /*!< Filter Element Disable */
eCANFD_FLTR_ELEM_STO_FIFO0 = 0x1, /*!< Filter Element Store In Fifo0 */
eCANFD_FLTR_ELEM_STO_FIFO1 = 0x2, /*!< Filter Element Store In Fifo1 */
eCANFD_FLTR_ELEM_REJ_ID = 0x3, /*!< Filter Element RejectId */
eCANFD_FLTR_ELEM_SET_PRI = 0x4, /*!< Filter Element Set Priority */
eCANFD_FLTR_ELEM_SET_PRI_STO_FIFO0 = 0x5, /*!< Filter Element Set Priority And Store In Fifo0 */
eCANFD_FLTR_ELEM_SET_PRI_STO_FIFO1 = 0x6, /*!< Filter Element Set Priority And Store In Fifo1 */
eCANFD_FLTR_ELEM_STO_RX_BUF_OR_DBG_MSG = 0x7 /*!< Filter Element Store In Rx Buf Or Debug Msg */
} E_CANFD_FLTR_CONFIG;
/* TX Event FIFO Element Struct */
typedef struct
{
E_CANFD_ID_TYPE eIdType; /*!< Standard ID or Extended ID */
uint32_t u32Id; /*!< Standard ID (11bits) or Extended ID (29bits) */
uint32_t u32DLC; /*!< Data Length Code used in the frame on the bus */
uint32_t u32TxTs; /*!< Tx Timestamp */
uint32_t u32MsgMarker; /*!< Message marker */
uint8_t bErrStaInd; /*!< Error State Indicator */
uint8_t bRemote; /*!< Remote transmission request */
uint8_t bFDFormat; /*!< FD Format */
uint8_t bBitRateSwitch; /*!< Bit Rate Switch */
} CANFD_TX_EVNT_ELEM_T;
#define CANFD_TIMEOUT 1000000 /* 1 second time-out */
#define CANFD_OK ( 0L) /*!< CANFD operation OK */
#define CANFD_ERR_FAIL (-1L) /*!< CANFD operation failed */
#define CANFD_ERR_TIMEOUT (-2L) /*!< CANFD operation abort due to timeout error */
#define CANFD_READ_REG_TIMEOUT (48UL) /*!< CANFD read register time-out count */
void CANFD_Open(CANFD_T *canfd, CANFD_FD_T *psCanfdStr);
void CANFD_Close(CANFD_T *canfd);
void CANFD_EnableInt(CANFD_T *canfd, uint32_t u32IntLine0, uint32_t u32IntLine1, uint32_t u32TXBTIE, uint32_t u32TXBCIE);
void CANFD_DisableInt(CANFD_T *canfd, uint32_t u32IntLine0, uint32_t u32IntLine1, uint32_t u32TXBTIE, uint32_t u32TXBCIE);
uint32_t CANFD_TransmitTxMsg(CANFD_T *canfd, uint32_t u32TxBufIdx, CANFD_FD_MSG_T *psTxMsg);
uint32_t CANFD_TransmitDMsg(CANFD_T *canfd, uint32_t u32TxBufIdx, CANFD_FD_MSG_T *psTxMsg);
void CANFD_SetGFC(CANFD_T *canfd, E_CANFD_ACC_NON_MATCH_FRM eNMStdFrm, E_CANFD_ACC_NON_MATCH_FRM eEMExtFrm, uint32_t u32RejRmtStdFrm, uint32_t u32RejRmtExtFrm);
void CANFD_SetSIDFltr(CANFD_T *canfd, uint32_t u32FltrIdx, uint32_t u32Filter);
void CANFD_SetXIDFltr(CANFD_T *canfd, uint32_t u32FltrIdx, uint32_t u32FilterLow, uint32_t u32FilterHigh);
uint32_t CANFD_ReadRxBufMsg(CANFD_T *canfd, uint8_t u8MbIdx, CANFD_FD_MSG_T *psMsgBuf);
uint32_t CANFD_ReadRxFifoMsg(CANFD_T *canfd, uint8_t u8FifoIdx, CANFD_FD_MSG_T *psMsgBuf);
void CANFD_CopyDBufToMsgBuf(CANFD_BUF_T *psRxBuffer, CANFD_FD_MSG_T *psMsgBuf);
void CANFD_CopyRxFifoToMsgBuf(CANFD_BUF_T *psRxBuf, CANFD_FD_MSG_T *psMsgBuf);
uint32_t CANFD_GetRxFifoWaterLvl(CANFD_T *canfd, uint32_t u32RxFifoNum);
void CANFD_TxBufCancelReq(CANFD_T *canfd, uint32_t u32TxBufIdx);
uint32_t CANFD_IsTxBufCancelFin(CANFD_T *canfd, uint32_t u32TxBufIdx);
uint32_t CANFD_IsTxBufTransmitOccur(CANFD_T *canfd, uint32_t u32TxBufIdx);
uint32_t CANFD_GetTxEvntFifoWaterLvl(CANFD_T *canfd);
void CANFD_CopyTxEvntFifoToUsrBuf(CANFD_T *canfd, uint32_t u32TxEvntNum, CANFD_TX_EVNT_ELEM_T *psTxEvntElem);
void CANFD_GetBusErrCount(CANFD_T *canfd, uint8_t *pu8TxErrBuf, uint8_t *pu8RxErrBuf);
int32_t CANFD_RunToNormal(CANFD_T *canfd, uint8_t u8Enable);
void CANFD_GetDefaultConfig(CANFD_FD_T *psConfig, uint8_t u8OpMode);
void CANFD_ClearStatusFlag(CANFD_T *canfd, uint32_t u32InterruptFlag);
uint32_t CANFD_GetStatusFlag(CANFD_T *canfd, uint32_t u32IntTypeFlag);
uint32_t CANFD_ReadReg(__I uint32_t *pu32RegAddr);
/*@}*/ /* end of group CANFD_EXPORTED_FUNCTIONS */
/*@}*/ /* end of group CANFD_Driver */
/*@}*/ /* end of group Standard_Driver */
#ifdef __cplusplus
}
#endif
#if defined ( __CC_ARM )
#pragma no_anon_unions
#endif
#endif /* __NU_CANFD_H__ */

175
bsp/nuvoton/libraries/ma35/StdDriver/inc/nu_ccap.h Normal file
View File

@ -0,0 +1,175 @@
/**************************************************************************//**
* @file nu_ccap.h
* @version V3.00
* @brief M460 Series CCAP Driver Header File
*
* @copyright SPDX-License-Identifier: Apache-2.0
* @copyright Copyright (C) 2021 Nuvoton Technology Corp. All rights reserved.
******************************************************************************/
#ifndef __NU_CCAP_H__
#define __NU_CCAP_H__
#ifdef __cplusplus
extern "C"
{
#endif
/** @addtogroup Standard_Driver Standard Driver
@{
*/
/** @addtogroup CCAP_Driver CCAP Driver
@{
*/
/** @addtogroup CCAP_EXPORTED_CONSTANTS CCAP Exported Constants
@{
*/
/*---------------------------------------------------------------------------------------------------------*/
/* CTL constant definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define CCAP_CTL_CCAPEN (1ul<<CCAP_CTL_CCAPEN_Pos) /*!< CCAP CTL setting for enabling Camera Capture Interface \hideinitializer */
#define CCAP_CTL_PKTEN (1ul<<CCAP_CTL_PKTEN_Pos) /*!< CCAP CTL setting for enabling packet output mode \hideinitializer */
#define CCAP_CTL_PLNEN (1ul<<CCAP_CTL_PLNEN_Pos) /*!< CCAP CTL setting for enabling planar output mode \hideinitializer */
#define CCAP_CTL_SHUTTER (1ul<<CCAP_CTL_SHUTTER_Pos) /*!< CCAP CTL setting for enabling shutter mode \hideinitializer */
#define CCAP_CTL_UPDATE (1ul<<CCAP_CTL_UPDATE_Pos) /*!< CCAP CTL setting for enabling update register at new frame \hideinitializer */
#define CCAP_CTL_RESET (1ul<<CCAP_CTL_VPRST_Pos) /*!< CCAP CTL setting for capture reset \hideinitializer */
#define CCAP_CTL_MY8_MY4 (0ul<<CCAP_CTL_MY8_MY4_Pos) /*!< CCAP CTL setting for 4-bit data I/O interface with Mono \hideinitializer */
#define CCAP_CTL_MY8_MY8 (1ul<<CCAP_CTL_MY8_MY4_Pos) /*!< CCAP CTL setting for 8-bit data I/O interface with Mono \hideinitializer */
/*---------------------------------------------------------------------------------------------------------*/
/* PAR constant definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define CCAP_PAR_INFMT_YUV422 (0ul<<CCAP_PAR_INFMT_Pos) /*!< CCAP PAR setting for Sensor Input Data YUV422 Format \hideinitializer */
#define CCAP_PAR_INFMT_RGB565 (1ul<<CCAP_PAR_INFMT_Pos) /*!< CCAP PAR setting for Sensor Input Data RGB565 Format \hideinitializer */
#define CCAP_PAR_SENTYPE_CCIR601 (0ul<<CCAP_PAR_SENTYPE_Pos) /*!< CCAP PAR setting for Sensor Input CCIR601 Type \hideinitializer */
#define CCAP_PAR_SENTYPE_CCIR656 (1ul<<CCAP_PAR_SENTYPE_Pos) /*!< CCAP PAR setting for Sensor Input CCIR656 Type \hideinitializer */
#define CCAP_PAR_INDATORD_YUYV (0x0ul<<CCAP_PAR_INDATORD_Pos) /*!< CCAP PAR setting for Sensor Input Data Order, YUYV \hideinitializer */
#define CCAP_PAR_INDATORD_YVYU (0x1ul<<CCAP_PAR_INDATORD_Pos) /*!< CCAP PAR setting for Sensor Input Data Order, YVYU \hideinitializer */
#define CCAP_PAR_INDATORD_UYVY (0x2ul<<CCAP_PAR_INDATORD_Pos) /*!< CCAP PAR setting for Sensor Input Data Order, UYVY \hideinitializer */
#define CCAP_PAR_INDATORD_VYUY (0x3ul<<CCAP_PAR_INDATORD_Pos) /*!< CCAP PAR setting for Sensor Input Data Order, VYUY \hideinitializer */
#define CCAP_PAR_INDATORD_RGGB (0x0ul<<CCAP_PAR_INDATORD_Pos) /*!< CCAP PAR setting for Sensor Input Data Order, 0byte: R[0:4] G[5:8], 1byte G[0:2] R[3:8] \hideinitializer */
#define CCAP_PAR_INDATORD_BGGR (0x1ul<<CCAP_PAR_INDATORD_Pos) /*!< CCAP PAR setting for Sensor Input Data Order, 0byte: b[0:4] G[5:8], 1byte G[0:2] R[3:8] \hideinitializer */
#define CCAP_PAR_INDATORD_GBRG (0x2ul<<CCAP_PAR_INDATORD_Pos) /*!< CCAP PAR setting for Sensor Input Data Order, 0byte: G[0:3] G[4:8], 1byte G[0:4] G[5:8] \hideinitializer */
#define CCAP_PAR_INDATORD_GRBG (0x3ul<<CCAP_PAR_INDATORD_Pos) /*!< CCAP PAR setting for Sensor Input Data Order, 0byte: G[0:3] G[4:8], 1byte G[0:4] G[5:8] \hideinitializer */
#define CCAP_PAR_PLNFMT_YUV422 (0x0ul<<CCAP_PAR_PLNFMT_Pos) /*!< CCAP PAR setting for Image Data YUV422P Format Output to System Memory \hideinitializer */
#define CCAP_PAR_PLNFMT_YUV420 (0x1ul<<CCAP_PAR_PLNFMT_Pos) /*!< CCAP PAR setting for Image Data YUV420P Format Output to System Memory \hideinitializer */
#define CCAP_PAR_OUTFMT_YUV422 (0x0ul<<CCAP_PAR_OUTFMT_Pos) /*!< CCAP PAR setting for Image Data YUV422 Format Output to System Memory \hideinitializer */
#define CCAP_PAR_OUTFMT_ONLY_Y (0x1ul<<CCAP_PAR_OUTFMT_Pos) /*!< CCAP PAR setting for Image Data ONLY_Y Format Output to System Memory \hideinitializer */
#define CCAP_PAR_OUTFMT_RGB555 (0x2ul<<CCAP_PAR_OUTFMT_Pos) /*!< CCAP PAR setting for Image Data RGB555 Format Output to System Memory \hideinitializer */
#define CCAP_PAR_OUTFMT_RGB565 (0x3ul<<CCAP_PAR_OUTFMT_Pos) /*!< CCAP PAR setting for Image Data RGB565 Format Output to System Memory \hideinitializer */
#define CCAP_PAR_VSP_LOW (0x0ul<<CCAP_PAR_VSP_Pos) /*!< CCAP PAR setting for Sensor Vsync Polarity \hideinitializer */
#define CCAP_PAR_VSP_HIGH (0x1ul<<CCAP_PAR_VSP_Pos) /*!< CCAP PAR setting for Sensor Vsync Polarity \hideinitializer */
#define CCAP_PAR_HSP_LOW (0x0ul<<CCAP_PAR_HSP_Pos) /*!< CCAP PAR setting for Sensor Hsync Polarity \hideinitializer */
#define CCAP_PAR_HSP_HIGH (0x1ul<<CCAP_PAR_HSP_Pos) /*!< CCAP PAR setting for Sensor Hsync Polarity \hideinitializer */
#define CCAP_PAR_PCLKP_LOW (0x0ul<<CCAP_PAR_PCLKP_Pos) /*!< CCAP PAR setting for Sensor Pixel Clock Polarity \hideinitializer */
#define CCAP_PAR_PCLKP_HIGH (0x1ul<<CCAP_PAR_PCLKP_Pos) /*!< CCAP PAR setting for Sensor Pixel Clock Polarity \hideinitializer */
/*---------------------------------------------------------------------------------------------------------*/
/* INT constant definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define CCAP_INT_VIEN_ENABLE (0x1ul<<CCAP_INT_VIEN_Pos) /*!< VININT setting for Video Frame End Interrupt enable \hideinitializer */
#define CCAP_INT_MEIEN_ENABLE (0x1ul<<CCAP_INT_MEIEN_Pos) /*!< VININT setting for Bus Master Transfer Error Interrupt enable \hideinitializer */
#define CCAP_INT_ADDRMIEN_ENABLE (0x1ul<<CCAP_INT_ADDRMIEN_Pos) /*!< VININT setting for Memory Address Match Interrupt enable \hideinitializer */
/*---------------------------------------------------------------------------------------------------------*/
/* Define Error Code */
/*---------------------------------------------------------------------------------------------------------*/
#define CCAP_INVALID_INT ((int32_t)(0xFFFFFFFF-1))
#define CCAP_INVALID_BUF ((int32_t)(0xFFFFFFFF-2))
#define CCAP_INVALID_PIPE ((int32_t)(0xFFFFFFFF-3))
#define CCAP_TIMEOUT_ERR (-1) /*!< CCAP operation abort due to timeout error \hideinitializer */
/*@}*/ /* end of group CCAP_EXPORTED_CONSTANTS */
extern int32_t g_CCAP_i32ErrCode;
/** @addtogroup CCAP_EXPORTED_FUNCTIONS CCAP Exported Functions
@{
*/
/**
* @brief Is CCAP module stopped
*
* @param None
*
* @retval 0 CCAP module is enabled
* @retval 1 CCAP module is disabled(stopped)
*
* @details Check Camera Capture Interface module Enable or Disable(stopped)
* \hideinitializer
*/
#define CCAP_IS_STOPPED(ccap) ((ccap->CTL & CCAP_CTL_CCAPEN_Msk)?0:1)
/**
* @brief Clear CCAP flag
*
* @param[in] u32IntMask interrupt flags settings. It could be
* - \ref CCAP_INT_VINTF_Msk
* - \ref CCAP_INT_MEINTF_Msk
* - \ref CCAP_INT_ADDRMINTF_Msk
* - \ref CCAP_INT_MDINTF_Msk
*
* @return None
*
* @details Clear Camera Capture Interface interrupt flag
* \hideinitializer
*/
#define CCAP_CLR_INT_FLAG(ccap, u32IntMask) (ccap->INT |= (u32IntMask))
/**
* @brief Get CCAP Interrupt status
*
* @param None
*
* @return CCAP Interrupt Register
*
* @details Get Camera Capture Interface interrupt status.
* \hideinitializer
*/
#define CCAP_GET_INT_STS(ccap) (ccap->INT)
#define CCAP_SET_CTL(ccap, u32IntMask) (ccap->CTL |= u32IntMask)
#define CCAP_CLR_CTL(ccap, u32IntMask) (ccap->CTL &= ~u32IntMask)
void CCAP_Open(CCAP_T *ccap, uint32_t u32InFormat, uint32_t u32OutFormat);
void CCAP_SetCroppingWindow(CCAP_T *ccap, uint32_t u32VStart, uint32_t u32HStart, uint32_t u32Height, uint32_t u32Width);
void CCAP_SetPacketBuf(CCAP_T *ccap, uint32_t u32Address);
void CCAP_Close(CCAP_T *ccap);
void CCAP_EnableInt(CCAP_T *ccap, uint32_t u32IntMask);
void CCAP_DisableInt(CCAP_T *ccap, uint32_t u32IntMask);
void CCAP_Start(CCAP_T *ccap);
void CCAP_Stop(CCAP_T *ccap, uint32_t u32FrameComplete);
void CCAP_SetPacketScaling(CCAP_T *ccap, uint32_t u32VNumerator, uint32_t u32VDenominator, uint32_t u32HNumerator, uint32_t u32HDenominator);
void CCAP_SetPacketStride(CCAP_T *ccap, uint32_t u32Stride);
void CCAP_EnableMono(CCAP_T *ccap, uint32_t u32Interface);
void CCAP_DisableMono(CCAP_T *ccap);
void CCAP_EnableLumaYOne(CCAP_T *ccap, uint32_t u32th);
void CCAP_DisableLumaYOne(CCAP_T *ccap);
void CCAP_SetPlanarYBuf(CCAP_T *ccap, uint32_t u32Address);
void CCAP_SetPlanarUBuf(CCAP_T *ccap, uint32_t u32Address);
void CCAP_SetPlanarVBuf(CCAP_T *ccap, uint32_t u32Address);
void CCAP_SetPlanarScaling(CCAP_T *ccap, uint32_t u32VNumerator, uint32_t u32VDenominator, uint32_t u32HNumerator, uint32_t u32HDenominator);
void CCAP_SetPlanarStride(CCAP_T *ccap, uint32_t u32Stride);
/*@}*/ /* end of group CCAP_EXPORTED_FUNCTIONS */
/*@}*/ /* end of group CCAP_Driver */
/*@}*/ /* end of group Standard_Driver */
#ifdef __cplusplus
}
#endif
#endif //__NU_CCAP_H__

622
bsp/nuvoton/libraries/ma35/StdDriver/inc/nu_clk.h Normal file
View File

@ -0,0 +1,622 @@
/**************************************************************************//**
* @file CLK.h
* @brief CLK Driver Header File
*
* SPDX-License-Identifier: Apache-2.0
* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
******************************************************************************/
#ifndef __NU_CLK_H__
#define __NU_CLK_H__
#ifdef __cplusplus
extern "C"
{
#endif
/** @addtogroup Standard_Driver Standard Driver
@{
*/
/** @addtogroup CLK_Driver CLK Driver
@{
*/
/** @addtogroup CLK_EXPORTED_CONSTANTS CLK Exported Constants
@{
*/
#define FREQ_180MHZ 180000000UL /*!< 180 MHz \hideinitializer */
#define CAPLL (0x0UL)
#define SYSPLL (0x1UL)
#define DDRPLL (0x2UL)
#define APLL (0x3UL)
#define EPLL (0x4UL)
#define VPLL (0x5UL)
#define PLL_OPMODE_INTEGER (0x0UL)
#define PLL_OPMODE_FRACTIONAL (0x1UL)
#define PLL_OPMODE_SPREAD_SPECTRUM (0x2UL)
/*---------------------------------------------------------------------------------------------------------*/
/* CLKSEL0 constant definitions. (Write-protection) */
/*---------------------------------------------------------------------------------------------------------*/
#define CLK_CLKSEL0_CA35CKSEL_HXT (0x0UL<<CLK_CLKSEL0_CA35CKSEL_Pos) /*!< Select CA35CK clock source from high speed crystal */
#define CLK_CLKSEL0_CA35CKSEL_CAPLL (0x1UL<<CLK_CLKSEL0_CA35CKSEL_Pos) /*!< Select CA35CK clock source from CA-PLL */
#define CLK_CLKSEL0_CA35CKSEL_DDRPLL (0x2UL<<CLK_CLKSEL0_CA35CKSEL_Pos) /*!< Select CA35CK clock source from DDR-PLL */
#define CLK_CLKSEL0_SYSCK0SEL_EPLL_DIV2 (0x0UL<<CLK_CLKSEL0_SYSCK0SEL_Pos) /*!< Select SYSCK0 clock source from EPLL/2 */
#define CLK_CLKSEL0_SYSCK0SEL_SYSPLL (0x1UL<<CLK_CLKSEL0_SYSCK0SEL_Pos) /*!< Select SYSCK0 clock source from SYS-PLL */
#define CLK_CLKSEL0_LVRDBSEL_LIRC (0x0UL<<CLK_CLKSEL0_LVRDBSEL_Pos) /*!< Select LVRDB clock source from low speed oscillator */
#define CLK_CLKSEL0_LVRDBSEL_HIRC (0x1UL<<CLK_CLKSEL0_LVRDBSEL_Pos) /*!< Select LVRDB clock source from high speed oscillator */
#define CLK_CLKSEL0_SYSCK1SEL_HXT (0x0UL<<CLK_CLKSEL0_SYSCK1SEL_Pos) /*!< Select SYSCK1 clock source from high speed crystal */
#define CLK_CLKSEL0_SYSCK1SEL_SYSPLL (0x1UL<<CLK_CLKSEL0_SYSCK1SEL_Pos) /*!< Select SYSCK1 clock source from SYS-PLL */
#define CLK_CLKSEL0_RTPSTSEL_HXT (0x0UL<<CLK_CLKSEL0_RTPSTSEL_Pos) /*!< Select RTPST clock source from high speed crystal \hideinitializer */
#define CLK_CLKSEL0_RTPSTSEL_LXT (0x1UL<<CLK_CLKSEL0_RTPSTSEL_Pos) /*!< Select RTPST clock source from low speed crystal \hideinitializer */
#define CLK_CLKSEL0_RTPSTSEL_HXT_DIV2 (0x2UL<<CLK_CLKSEL0_RTPSTSEL_Pos) /*!< Select RTPST clock source from high speed crystal/2 \hideinitializer */
#define CLK_CLKSEL0_RTPSTSEL_SYSCLK1_DIV2 (0x3UL<<CLK_CLKSEL0_RTPSTSEL_Pos) /*!< Select RTPST clock source from SYSCLK1/2 \hideinitializer */
#define CLK_CLKSEL0_RTPSTSEL_HIRC (0x4UL<<CLK_CLKSEL0_RTPSTSEL_Pos) /*!< Select RTPST clock source from high speed oscillator \hideinitializer */
#define CLK_CLKSEL0_CCAP0SEL_HXT (0x0UL<<CLK_CLKSEL0_CCAP0SEL_Pos) /*!< Select CCAP0 clock source from high speed crystal */
#define CLK_CLKSEL0_CCAP0SEL_VPLL (0x1UL<<CLK_CLKSEL0_CCAP0SEL_Pos) /*!< Select CCAP0 clock source from VPLL */
#define CLK_CLKSEL0_CCAP0SEL_APLL (0x2UL<<CLK_CLKSEL0_CCAP0SEL_Pos) /*!< Select CCAP0 clock source from APLL */
#define CLK_CLKSEL0_CCAP0SEL_SYSPLL (0x3UL<<CLK_CLKSEL0_CCAP0SEL_Pos) /*!< Select CCAP0 clock source from SYS-PLL */
#define CLK_CLKSEL0_CCAP1SEL_HXT (0x0UL<<CLK_CLKSEL0_CCAP1SEL_Pos) /*!< Select CCAP1 clock source from high speed crystal */
#define CLK_CLKSEL0_CCAP1SEL_VPLL (0x1UL<<CLK_CLKSEL0_CCAP1SEL_Pos) /*!< Select CCAP1 clock source from VPLL */
#define CLK_CLKSEL0_CCAP1SEL_APLL (0x2UL<<CLK_CLKSEL0_CCAP1SEL_Pos) /*!< Select CCAP1 clock source from APLL */
#define CLK_CLKSEL0_CCAP1SEL_SYSPLL (0x3UL<<CLK_CLKSEL0_CCAP1SEL_Pos) /*!< Select CCAP1 clock source from SYS-PLL */
#define CLK_CLKSEL0_SD0SEL_SYSPLL (0x0UL<<CLK_CLKSEL0_SD0SEL_Pos) /*!< Select SD0 clock source from SYS-PLL */
#define CLK_CLKSEL0_SD0SEL_APLL (0x1UL<<CLK_CLKSEL0_SD0SEL_Pos) /*!< Select SD0 clock source from APLL */
#define CLK_CLKSEL0_SD1SEL_SYSPLL (0x0UL<<CLK_CLKSEL0_SD1SEL_Pos) /*!< Select SD1 clock source from SYS-PLL */
#define CLK_CLKSEL0_SD1SEL_APLL (0x1UL<<CLK_CLKSEL0_SD1SEL_Pos) /*!< Select SD1 clock source from APLL */
#define CLK_CLKSEL0_DCUSEL_EPLL_DIV2 (0x0UL<<CLK_CLKSEL0_DCUSEL_Pos) /*!< Select DCU clock source from EPLL/2 */
#define CLK_CLKSEL0_DCUSEL_SYSPLL (0x1UL<<CLK_CLKSEL0_DCUSEL_Pos) /*!< Select DCU clock source from SYS-PLL */
#define CLK_CLKSEL0_GFXSEL_EPLL (0x0UL<<CLK_CLKSEL0_GFXSEL_Pos) /*!< Select GFX clock source from EPLL */
#define CLK_CLKSEL0_GFXSEL_SYSPLL (0x1UL<<CLK_CLKSEL0_GFXSEL_Pos) /*!< Select GFX clock source from SYS-PLL */
#define CLK_CLKSEL0_DBGSEL_HIRC (0x0UL<<CLK_CLKSEL0_DBGSEL_Pos) /*!< Select DBG clock source from high speed oscillator */
#define CLK_CLKSEL0_DBGSEL_SYSPLL (0x1UL<<CLK_CLKSEL0_DBGSEL_Pos) /*!< Select DBG clock source from SYS-PLL */
/*---------------------------------------------------------------------------------------------------------*/
/* CLKSEL1 constant definitions. */
/*---------------------------------------------------------------------------------------------------------*/
#define CLK_CLKSEL1_TMR0SEL_HXT (0x0UL<<CLK_CLKSEL1_TMR0SEL_Pos) /*!< Select TMR0 clock source from high speed crystal */
#define CLK_CLKSEL1_TMR0SEL_LXT (0x1UL<<CLK_CLKSEL1_TMR0SEL_Pos) /*!< Select TMR0 clock source from low speed crystal */
#define CLK_CLKSEL1_TMR0SEL_PCLK0 (0x2UL<<CLK_CLKSEL1_TMR0SEL_Pos) /*!< Select TMR0 clock source from PCLK0 */
#define CLK_CLKSEL1_TMR0SEL_EXT (0x3UL<<CLK_CLKSEL1_TMR0SEL_Pos) /*!< Select TMR0 clock source from PCLK0 */
#define CLK_CLKSEL1_TMR0SEL_LIRC (0x5UL<<CLK_CLKSEL1_TMR0SEL_Pos) /*!< Select TMR0 clock source from low speed oscillator */
#define CLK_CLKSEL1_TMR0SEL_HIRC (0x7UL<<CLK_CLKSEL1_TMR0SEL_Pos) /*!< Select TMR0 clock source from high speed oscillator */
#define CLK_CLKSEL1_TMR1SEL_HXT (0x0UL<<CLK_CLKSEL1_TMR1SEL_Pos) /*!< Select TMR1 clock source from high speed crystal */
#define CLK_CLKSEL1_TMR1SEL_LXT (0x1UL<<CLK_CLKSEL1_TMR1SEL_Pos) /*!< Select TMR1 clock source from low speed crystal */
#define CLK_CLKSEL1_TMR1SEL_PCLK0 (0x2UL<<CLK_CLKSEL1_TMR1SEL_Pos) /*!< Select TMR1 clock source from PCLK0 */
#define CLK_CLKSEL1_TMR1SEL_EXT (0x3UL<<CLK_CLKSEL1_TMR1SEL_Pos) /*!< Select TMR1 clock source from external trigger */
#define CLK_CLKSEL1_TMR1SEL_LIRC (0x5UL<<CLK_CLKSEL1_TMR1SEL_Pos) /*!< Select TMR1 clock source from low speed oscillator */
#define CLK_CLKSEL1_TMR1SEL_HIRC (0x7UL<<CLK_CLKSEL1_TMR1SEL_Pos) /*!< Select TMR1 clock source from high speed oscillator */
#define CLK_CLKSEL1_TMR2SEL_HXT (0x0UL<<CLK_CLKSEL1_TMR2SEL_Pos) /*!< Select TMR2 clock source from high speed crystal */
#define CLK_CLKSEL1_TMR2SEL_LXT (0x1UL<<CLK_CLKSEL1_TMR2SEL_Pos) /*!< Select TMR2 clock source from low speed crystal */
#define CLK_CLKSEL1_TMR2SEL_PCLK1 (0x2UL<<CLK_CLKSEL1_TMR2SEL_Pos) /*!< Select TMR2 clock source from PCLK1 */
#define CLK_CLKSEL1_TMR2SEL_EXT (0x3UL<<CLK_CLKSEL1_TMR2SEL_Pos) /*!< Select TMR2 clock source from external trigger */
#define CLK_CLKSEL1_TMR2SEL_LIRC (0x5UL<<CLK_CLKSEL1_TMR2SEL_Pos) /*!< Select TMR2 clock source from low speed oscillator */
#define CLK_CLKSEL1_TMR2SEL_HIRC (0x7UL<<CLK_CLKSEL1_TMR2SEL_Pos) /*!< Select TMR2 clock source from high speed oscillator */
#define CLK_CLKSEL1_TMR3SEL_HXT (0x0UL<<CLK_CLKSEL1_TMR3SEL_Pos) /*!< Select TMR3 clock source from high speed crystal */
#define CLK_CLKSEL1_TMR3SEL_LXT (0x1UL<<CLK_CLKSEL1_TMR3SEL_Pos) /*!< Select TMR3 clock source from low speed crystal */
#define CLK_CLKSEL1_TMR3SEL_PCLK1 (0x2UL<<CLK_CLKSEL1_TMR3SEL_Pos) /*!< Select TMR3 clock source from PCLK1 */
#define CLK_CLKSEL1_TMR3SEL_EXT (0x3UL<<CLK_CLKSEL1_TMR3SEL_Pos) /*!< Select TMR3 clock source from external trigger */
#define CLK_CLKSEL1_TMR3SEL_LIRC (0x5UL<<CLK_CLKSEL1_TMR3SEL_Pos) /*!< Select TMR3 clock source from low speed oscillator */
#define CLK_CLKSEL1_TMR3SEL_HIRC (0x7UL<<CLK_CLKSEL1_TMR3SEL_Pos) /*!< Select TMR3 clock source from high speed oscillator */
#define CLK_CLKSEL1_TMR4SEL_HXT (0x0UL<<CLK_CLKSEL1_TMR4SEL_Pos) /*!< Select TMR4 clock source from high speed crystal */
#define CLK_CLKSEL1_TMR4SEL_LXT (0x1UL<<CLK_CLKSEL1_TMR4SEL_Pos) /*!< Select TMR4 clock source from low speed crystal */
#define CLK_CLKSEL1_TMR4SEL_PCLK2 (0x2UL<<CLK_CLKSEL1_TMR4SEL_Pos) /*!< Select TMR4 clock source from PCLK2 */
#define CLK_CLKSEL1_TMR4SEL_EXT (0x3UL<<CLK_CLKSEL1_TMR4SEL_Pos) /*!< Select TMR4 clock source from external trigger */
#define CLK_CLKSEL1_TMR4SEL_LIRC (0x5UL<<CLK_CLKSEL1_TMR4SEL_Pos) /*!< Select TMR4 clock source from low speed oscillator */
#define CLK_CLKSEL1_TMR4SEL_HIRC (0x7UL<<CLK_CLKSEL1_TMR4SEL_Pos) /*!< Select TMR4 clock source from high speed oscillator */
#define CLK_CLKSEL1_TMR5SEL_HXT (0x0UL<<CLK_CLKSEL1_TMR5SEL_Pos) /*!< Select TMR5 clock source from high speed crystal */
#define CLK_CLKSEL1_TMR5SEL_LXT (0x1UL<<CLK_CLKSEL1_TMR5SEL_Pos) /*!< Select TMR5 clock source from low speed crystal */
#define CLK_CLKSEL1_TMR5SEL_PCLK2 (0x2UL<<CLK_CLKSEL1_TMR5SEL_Pos) /*!< Select TMR5 clock source from PCLK2 */
#define CLK_CLKSEL1_TMR5SEL_EXT (0x3UL<<CLK_CLKSEL1_TMR5SEL_Pos) /*!< Select TMR5 clock source from external trigger */
#define CLK_CLKSEL1_TMR5SEL_LIRC (0x5UL<<CLK_CLKSEL1_TMR5SEL_Pos) /*!< Select TMR5 clock source from low speed oscillator */
#define CLK_CLKSEL1_TMR5SEL_HIRC (0x7UL<<CLK_CLKSEL1_TMR5SEL_Pos) /*!< Select TMR5 clock source from high speed oscillator */
#define CLK_CLKSEL1_TMR6SEL_HXT (0x0UL<<CLK_CLKSEL1_TMR6SEL_Pos) /*!< Select TMR6 clock source from high speed crystal */
#define CLK_CLKSEL1_TMR6SEL_LXT (0x1UL<<CLK_CLKSEL1_TMR6SEL_Pos) /*!< Select TMR6 clock source from low speed crystal */
#define CLK_CLKSEL1_TMR6SEL_PCLK0 (0x2UL<<CLK_CLKSEL1_TMR6SEL_Pos) /*!< Select TMR6 clock source from PCLK0 */
#define CLK_CLKSEL1_TMR6SEL_EXT (0x3UL<<CLK_CLKSEL1_TMR6SEL_Pos) /*!< Select TMR6 clock source from external trigger */
#define CLK_CLKSEL1_TMR6SEL_LIRC (0x5UL<<CLK_CLKSEL1_TMR6SEL_Pos) /*!< Select TMR6 clock source from low speed oscillator */
#define CLK_CLKSEL1_TMR6SEL_HIRC (0x7UL<<CLK_CLKSEL1_TMR6SEL_Pos) /*!< Select TMR6 clock source from high speed oscillator */
#define CLK_CLKSEL1_TMR7SEL_HXT (0x0UL<<CLK_CLKSEL1_TMR7SEL_Pos) /*!< Select TMR7 clock source from high speed crystal */
#define CLK_CLKSEL1_TMR7SEL_LXT (0x1UL<<CLK_CLKSEL1_TMR7SEL_Pos) /*!< Select TMR7 clock source from low speed crystal */
#define CLK_CLKSEL1_TMR7SEL_PCLK0 (0x2UL<<CLK_CLKSEL1_TMR7SEL_Pos) /*!< Select TMR7 clock source from PCLK0 */
#define CLK_CLKSEL1_TMR7SEL_EXT (0x3UL<<CLK_CLKSEL1_TMR7SEL_Pos) /*!< Select TMR7 clock source from external trigger */
#define CLK_CLKSEL1_TMR7SEL_LIRC (0x5UL<<CLK_CLKSEL1_TMR7SEL_Pos) /*!< Select TMR7 clock source from low speed oscillator */
#define CLK_CLKSEL1_TMR7SEL_HIRC (0x7UL<<CLK_CLKSEL1_TMR7SEL_Pos) /*!< Select TMR7 clock source from high speed oscillator */
/*---------------------------------------------------------------------------------------------------------*/
/* CLKSEL2 constant definitions. */
/*---------------------------------------------------------------------------------------------------------*/
#define CLK_CLKSEL2_TMR8SEL_HXT (0x0UL<<CLK_CLKSEL2_TMR8SEL_Pos) /*!< Select TMR8 clock source from high speed crystal */
#define CLK_CLKSEL2_TMR8SEL_LXT (0x1UL<<CLK_CLKSEL2_TMR8SEL_Pos) /*!< Select TMR8 clock source from low speed crystal */
#define CLK_CLKSEL2_TMR8SEL_PCLK1 (0x2UL<<CLK_CLKSEL2_TMR8SEL_Pos) /*!< Select TMR8 clock source from PCLK1 */
#define CLK_CLKSEL2_TMR8SEL_EXT (0x3UL<<CLK_CLKSEL2_TMR8SEL_Pos) /*!< Select TMR8 clock source from external trigger */
#define CLK_CLKSEL2_TMR8SEL_LIRC (0x5UL<<CLK_CLKSEL2_TMR8SEL_Pos) /*!< Select TMR8 clock source from low speed oscillator */
#define CLK_CLKSEL2_TMR8SEL_HIRC (0x7UL<<CLK_CLKSEL2_TMR8SEL_Pos) /*!< Select TMR8 clock source from high speed oscillator */
#define CLK_CLKSEL2_TMR9SEL_HXT (0x0UL<<CLK_CLKSEL2_TMR9SEL_Pos) /*!< Select TMR9 clock source from high speed crystal */
#define CLK_CLKSEL2_TMR9SEL_LXT (0x1UL<<CLK_CLKSEL2_TMR9SEL_Pos) /*!< Select TMR9 clock source from low speed crystal */
#define CLK_CLKSEL2_TMR9SEL_PCLK1 (0x2UL<<CLK_CLKSEL2_TMR9SEL_Pos) /*!< Select TMR9 clock source from PCLK1 */
#define CLK_CLKSEL2_TMR9SEL_EXT (0x3UL<<CLK_CLKSEL2_TMR9SEL_Pos) /*!< Select TMR9 clock source from external trigger */
#define CLK_CLKSEL2_TMR9SEL_LIRC (0x5UL<<CLK_CLKSEL2_TMR9SEL_Pos) /*!< Select TMR9 clock source from low speed oscillator */
#define CLK_CLKSEL2_TMR9SEL_HIRC (0x7UL<<CLK_CLKSEL2_TMR9SEL_Pos) /*!< Select TMR9 clock source from high speed oscillator */
#define CLK_CLKSEL2_TMR10SEL_HXT (0x0UL<<CLK_CLKSEL2_TMR10SEL_Pos) /*!< Select TMR10 clock source from high speed crystal */
#define CLK_CLKSEL2_TMR10SEL_LXT (0x1UL<<CLK_CLKSEL2_TMR10SEL_Pos) /*!< Select TMR10 clock source from low speed crystal */
#define CLK_CLKSEL2_TMR10SEL_PCLK2 (0x2UL<<CLK_CLKSEL2_TMR10SEL_Pos) /*!< Select TMR10 clock source from PCLK2 */
#define CLK_CLKSEL2_TMR10SEL_EXT (0x3UL<<CLK_CLKSEL2_TMR10SEL_Pos) /*!< Select TMR10 clock source from external trigger */
#define CLK_CLKSEL2_TMR10SEL_LIRC (0x5UL<<CLK_CLKSEL2_TMR10SEL_Pos) /*!< Select TMR10 clock source from low speed oscillator */
#define CLK_CLKSEL2_TMR10SEL_HIRC (0x7UL<<CLK_CLKSEL2_TMR10SEL_Pos) /*!< Select TMR10 clock source from high speed oscillator */
#define CLK_CLKSEL2_TMR11SEL_HXT (0x0UL<<CLK_CLKSEL2_TMR11SEL_Pos) /*!< Select TMR11 clock source from high speed crystal */
#define CLK_CLKSEL2_TMR11SEL_LXT (0x1UL<<CLK_CLKSEL2_TMR11SEL_Pos) /*!< Select TMR11 clock source from low speed crystal */
#define CLK_CLKSEL2_TMR11SEL_PCLK2 (0x2UL<<CLK_CLKSEL2_TMR11SEL_Pos) /*!< Select TMR11 clock source from PCLK2 */
#define CLK_CLKSEL2_TMR11SEL_EXT (0x3UL<<CLK_CLKSEL2_TMR11SEL_Pos) /*!< Select TMR11 clock source from external trigger */
#define CLK_CLKSEL2_TMR11SEL_LIRC (0x5UL<<CLK_CLKSEL2_TMR11SEL_Pos) /*!< Select TMR11 clock source from low speed oscillator */
#define CLK_CLKSEL2_TMR11SEL_HIRC (0x7UL<<CLK_CLKSEL2_TMR11SEL_Pos) /*!< Select TMR11 clock source from high speed oscillator */
#define CLK_CLKSEL2_UART0SEL_HXT (0x0UL<<CLK_CLKSEL2_UART0SEL_Pos) /*!< Select UART0 clock source from high speed crystal */
#define CLK_CLKSEL2_UART0SEL_SYSCLK1_DIV2 (0x1UL<<CLK_CLKSEL2_UART0SEL_Pos) /*!< Select UART0 clock source from SYSCLK1 */
#define CLK_CLKSEL2_UART1SEL_HXT (0x0UL<<CLK_CLKSEL2_UART1SEL_Pos) /*!< Select UART1 clock source from high speed crystal */
#define CLK_CLKSEL2_UART1SEL_SYSCLK1_DIV2 (0x1UL<<CLK_CLKSEL2_UART1SEL_Pos) /*!< Select UART1 clock source from SYSCLK1 */
#define CLK_CLKSEL2_UART2SEL_HXT (0x0UL<<CLK_CLKSEL2_UART2SEL_Pos) /*!< Select UART2 clock source from high speed crystal */
#define CLK_CLKSEL2_UART2SEL_SYSCLK1_DIV2 (0x1UL<<CLK_CLKSEL2_UART2SEL_Pos) /*!< Select UART2 clock source from SYSCLK1 */
#define CLK_CLKSEL2_UART3SEL_HXT (0x0UL<<CLK_CLKSEL2_UART3SEL_Pos) /*!< Select UART3 clock source from high speed crystal */
#define CLK_CLKSEL2_UART3SEL_SYSCLK1_DIV2 (0x1UL<<CLK_CLKSEL2_UART3SEL_Pos) /*!< Select UART3 clock source from SYSCLK1 */
#define CLK_CLKSEL2_UART4SEL_HXT (0x0UL<<CLK_CLKSEL2_UART4SEL_Pos) /*!< Select UART4 clock source from high speed crystal */
#define CLK_CLKSEL2_UART4SEL_SYSCLK1_DIV2 (0x1UL<<CLK_CLKSEL2_UART4SEL_Pos) /*!< Select UART4 clock source from SYSCLK1 */
#define CLK_CLKSEL2_UART5SEL_HXT (0x0UL<<CLK_CLKSEL2_UART5SEL_Pos) /*!< Select UART5 clock source from high speed crystal */
#define CLK_CLKSEL2_UART5SEL_SYSCLK1_DIV2 (0x1UL<<CLK_CLKSEL2_UART5SEL_Pos) /*!< Select UART5 clock source from SYSCLK1 */
#define CLK_CLKSEL2_UART6SEL_HXT (0x0UL<<CLK_CLKSEL2_UART6SEL_Pos) /*!< Select UART6 clock source from high speed crystal */
#define CLK_CLKSEL2_UART6SEL_SYSCLK1_DIV2 (0x1UL<<CLK_CLKSEL2_UART6SEL_Pos) /*!< Select UART6 clock source from SYSCLK1 */
#define CLK_CLKSEL2_UART7SEL_HXT (0x0UL<<CLK_CLKSEL2_UART7SEL_Pos) /*!< Select UART7 clock source from high speed crystal */
#define CLK_CLKSEL2_UART7SEL_SYSCLK1_DIV2 (0x1UL<<CLK_CLKSEL2_UART7SEL_Pos) /*!< Select UART7 clock source from SYSCLK1 */
/*---------------------------------------------------------------------------------------------------------*/
/* CLKSEL3 constant definitions. */
/*---------------------------------------------------------------------------------------------------------*/
#define CLK_CLKSEL3_UART8SEL_HXT (0x0UL<<CLK_CLKSEL3_UART8SEL_Pos) /*!< Select UART8 clock source from high speed crystal */
#define CLK_CLKSEL3_UART8SEL_SYSCLK1_DIV2 (0x1UL<<CLK_CLKSEL3_UART8SEL_Pos) /*!< Select UART8 clock source from SYSCLK1 */
#define CLK_CLKSEL3_UART9SEL_HXT (0x0UL<<CLK_CLKSEL3_UART9SEL_Pos) /*!< Select UART9 clock source from high speed crystal */
#define CLK_CLKSEL3_UART9SEL_SYSCLK1_DIV2 (0x1UL<<CLK_CLKSEL3_UART9SEL_Pos) /*!< Select UART9 clock source from SYSCLK1 */
#define CLK_CLKSEL3_UART10SEL_HXT (0x0UL<<CLK_CLKSEL3_UART10SEL_Pos) /*!< Select UART10 clock source from high speed crystal */
#define CLK_CLKSEL3_UART10SEL_SYSCLK1_DIV2 (0x1UL<<CLK_CLKSEL3_UART10SEL_Pos) /*!< Select UART10 clock source from SYSCLK1 */
#define CLK_CLKSEL3_UART11SEL_HXT (0x0UL<<CLK_CLKSEL3_UART11SEL_Pos) /*!< Select UART11 clock source from high speed crystal */
#define CLK_CLKSEL3_UART11SEL_SYSCLK1_DIV2 (0x1UL<<CLK_CLKSEL3_UART11SEL_Pos) /*!< Select UART11 clock source from SYSCLK1 */
#define CLK_CLKSEL3_UART12SEL_HXT (0x0UL<<CLK_CLKSEL3_UART12SEL_Pos) /*!< Select UART12 clock source from high speed crystal */
#define CLK_CLKSEL3_UART12SEL_SYSCLK1_DIV2 (0x1UL<<CLK_CLKSEL3_UART12SEL_Pos) /*!< Select UART12 clock source from SYSCLK1 */
#define CLK_CLKSEL3_UART13SEL_HXT (0x0UL<<CLK_CLKSEL3_UART13SEL_Pos) /*!< Select UART13 clock source from high speed crystal */
#define CLK_CLKSEL3_UART13SEL_SYSCLK1_DIV2 (0x1UL<<CLK_CLKSEL3_UART13SEL_Pos) /*!< Select UART13 clock source from SYSCLK1 */
#define CLK_CLKSEL3_UART14SEL_HXT (0x0UL<<CLK_CLKSEL3_UART14SEL_Pos) /*!< Select UART14 clock source from high speed crystal */
#define CLK_CLKSEL3_UART14SEL_SYSCLK1_DIV2 (0x1UL<<CLK_CLKSEL3_UART14SEL_Pos) /*!< Select UART14 clock source from SYSCLK1 */
#define CLK_CLKSEL3_UART15SEL_HXT (0x0UL<<CLK_CLKSEL3_UART15SEL_Pos) /*!< Select UART15 clock source from high speed crystal */
#define CLK_CLKSEL3_UART15SEL_SYSCLK1_DIV2 (0x1UL<<CLK_CLKSEL3_UART15SEL_Pos) /*!< Select UART15 clock source from SYSCLK1 */
#define CLK_CLKSEL3_UART16SEL_HXT (0x0UL<<CLK_CLKSEL3_UART16SEL_Pos) /*!< Select UART16 clock source from high speed crystal */
#define CLK_CLKSEL3_UART16SEL_SYSCLK1_DIV2 (0x1UL<<CLK_CLKSEL3_UART16SEL_Pos) /*!< Select UART16 clock source from SYSCLK1 */
#define CLK_CLKSEL3_WDT0SEL_LXT (0x1UL<<CLK_CLKSEL3_WDT0SEL_Pos) /*!< Select WDT0 clock source from low speed crystal */
#define CLK_CLKSEL3_WDT0SEL_PCLK3_DIV4096 (0x2UL<<CLK_CLKSEL3_WDT0SEL_Pos) /*!< Select WDT0 clock source from PCLK3/4096 */
#define CLK_CLKSEL3_WDT0SEL_LIRC (0x3UL<<CLK_CLKSEL3_WDT0SEL_Pos) /*!< Select WDT0 clock source from low speed oscillator */
#define CLK_CLKSEL3_WWDT0SEL_PCLK3_DIV4096 (0x2UL<<CLK_CLKSEL3_WWDT0SEL_Pos) /*!< Select WWDT0 clock source from PCLK3/4096 */
#define CLK_CLKSEL3_WWDT0SEL_LIRC (0x3UL<<CLK_CLKSEL3_WWDT0SEL_Pos) /*!< Select WWDT0 clock source from low speed oscillator */
#define CLK_CLKSEL3_WDT1SEL_LXT (0x1UL<<CLK_CLKSEL3_WDT1SEL_Pos) /*!< Select WDT1 clock source from low speed crystal */
#define CLK_CLKSEL3_WDT1SEL_PCLK3_DIV4096 (0x2UL<<CLK_CLKSEL3_WDT1SEL_Pos) /*!< Select WDT1 clock source from PCLK3/4096 */
#define CLK_CLKSEL3_WDT1SEL_LIRC (0x3UL<<CLK_CLKSEL3_WDT1SEL_Pos) /*!< Select WDT1 clock source from low speed oscillator */
#define CLK_CLKSEL3_WWDT1SEL_PCLK3_DIV4096 (0x2UL<<CLK_CLKSEL3_WWDT1SEL_Pos) /*!< Select WWDT1 clock source from PCLK3/4096 */
#define CLK_CLKSEL3_WWDT1SEL_LIRC (0x3UL<<CLK_CLKSEL3_WWDT1SEL_Pos) /*!< Select WWDT1 clock source from low speed oscillator */
#define CLK_CLKSEL3_WDT2SEL_LXT (0x1UL<<CLK_CLKSEL3_WDT2SEL_Pos) /*!< Select WDT2 clock source from low speed crystal */
#define CLK_CLKSEL3_WDT2SEL_PCLK4_DIV4096 (0x2UL<<CLK_CLKSEL3_WDT2SEL_Pos) /*!< Select WDT2 clock source from PCLK4/4096 */
#define CLK_CLKSEL3_WDT2SEL_LIRC (0x3UL<<CLK_CLKSEL3_WDT2SEL_Pos) /*!< Select WDT2 clock source from low speed oscillator */
#define CLK_CLKSEL3_WWDT2SEL_PCLK4_DIV4096 (0x2UL<<CLK_CLKSEL3_WWDT2SEL_Pos) /*!< Select WWDT2 clock source from PCLK4/4096 */
#define CLK_CLKSEL3_WWDT2SEL_LIRC (0x3UL<<CLK_CLKSEL3_WWDT2SEL_Pos) /*!< Select WWDT2 clock source from low speed oscillator */
/*---------------------------------------------------------------------------------------------------------*/
/* CLKSEL4 constant definitions. */
/*---------------------------------------------------------------------------------------------------------*/
#define CLK_CLKSEL4_SPI0SEL_PCLK1 (0x0UL<<CLK_CLKSEL4_SPI0SEL_Pos) /*!< Select SPI0 clock source from PCLK1 */
#define CLK_CLKSEL4_SPI0SEL_APLL (0x1UL<<CLK_CLKSEL4_SPI0SEL_Pos) /*!< Select SPI0 clock source from APLL */
#define CLK_CLKSEL4_SPI1SEL_PCLK2 (0x0UL<<CLK_CLKSEL4_SPI1SEL_Pos) /*!< Select SPI1 clock source from PCLK2 */
#define CLK_CLKSEL4_SPI1SEL_APLL (0x1UL<<CLK_CLKSEL4_SPI1SEL_Pos) /*!< Select SPI1 clock source from APLL */
#define CLK_CLKSEL4_SPI2SEL_PCLK1 (0x0UL<<CLK_CLKSEL4_SPI2SEL_Pos) /*!< Select SPI2 clock source from PCLK1 */
#define CLK_CLKSEL4_SPI2SEL_APLL (0x1UL<<CLK_CLKSEL4_SPI2SEL_Pos) /*!< Select SPI2 clock source from APLL */
#define CLK_CLKSEL4_SPI3SEL_PCLK2 (0x0UL<<CLK_CLKSEL4_SPI3SEL_Pos) /*!< Select SPI3 clock source from PCLK2 */
#define CLK_CLKSEL4_SPI3SEL_APLL (0x1UL<<CLK_CLKSEL4_SPI3SEL_Pos) /*!< Select SPI3 clock source from APLL */
#define CLK_CLKSEL4_QSPI0SEL_PCLK0 (0x0UL<<CLK_CLKSEL4_QSPI0SEL_Pos) /*!< Select QSPI0 clock source from PCLK0 */
#define CLK_CLKSEL4_QSPI0SEL_APLL (0x1UL<<CLK_CLKSEL4_QSPI0SEL_Pos) /*!< Select QSPI0 clock source from APLL */
#define CLK_CLKSEL4_QSPI1SEL_PCLK0 (0x0UL<<CLK_CLKSEL4_QSPI1SEL_Pos) /*!< Select QSPI1 clock source from PCLK0 */
#define CLK_CLKSEL4_QSPI1SEL_APLL (0x1UL<<CLK_CLKSEL4_QSPI1SEL_Pos) /*!< Select QSPI1 clock source from APLL */
#define CLK_CLKSEL4_I2S0SEL_APLL (0x0UL<<CLK_CLKSEL4_I2S0SEL_Pos) /*!< Select I2S0 clock source from APLL */
#define CLK_CLKSEL4_I2S0SEL_SYSCLK1_DIV2 (0x1UL<<CLK_CLKSEL4_I2S0SEL_Pos) /*!< Select I2S0 clock source from SYSCLK1/2 */
#define CLK_CLKSEL4_I2S1SEL_APLL (0x0UL<<CLK_CLKSEL4_I2S1SEL_Pos) /*!< Select I2S1 clock source from APLL */
#define CLK_CLKSEL4_I2S1SEL_SYSCLK1_DIV2 (0x1UL<<CLK_CLKSEL4_I2S1SEL_Pos) /*!< Select I2S1 clock source from SYSCLK1/2 */
#define CLK_CLKSEL4_CANFD0SEL_APLL (0x0UL<<CLK_CLKSEL4_CANFD0SEL_Pos) /*!< Select CANFD0 clock source from APLL */
#define CLK_CLKSEL4_CANFD0SEL_VPLL (0x1UL<<CLK_CLKSEL4_CANFD0SEL_Pos) /*!< Select CANFD0 clock source from VPLL */
#define CLK_CLKSEL4_CANFD1SEL_APLL (0x0UL<<CLK_CLKSEL4_CANFD1SEL_Pos) /*!< Select CANFD1 clock source from APLL */
#define CLK_CLKSEL4_CANFD1SEL_VPLL (0x1UL<<CLK_CLKSEL4_CANFD1SEL_Pos) /*!< Select CANFD1 clock source from VPLL */
#define CLK_CLKSEL4_CANFD2SEL_APLL (0x0UL<<CLK_CLKSEL4_CANFD2SEL_Pos) /*!< Select CANFD2 clock source from APLL */
#define CLK_CLKSEL4_CANFD2SEL_VPLL (0x1UL<<CLK_CLKSEL4_CANFD2SEL_Pos) /*!< Select CANFD2 clock source from VPLL */
#define CLK_CLKSEL4_CANFD3SEL_APLL (0x0UL<<CLK_CLKSEL4_CANFD3SEL_Pos) /*!< Select CANFD3 clock source from APLL */
#define CLK_CLKSEL4_CANFD3SEL_VPLL (0x1UL<<CLK_CLKSEL4_CANFD3SEL_Pos) /*!< Select CANFD3 clock source from VPLL */
#define CLK_CLKSEL4_CKOSEL_HXT (0x0UL<<CLK_CLKSEL4_CKOSEL_Pos) /*!< Select CKO clock source from high speed crystal */
#define CLK_CLKSEL4_CKOSEL_LXT (0x1UL<<CLK_CLKSEL4_CKOSEL_Pos) /*!< Select CKO clock source from low speed crystal */
#define CLK_CLKSEL4_CKOSEL_HIRC (0x2UL<<CLK_CLKSEL4_CKOSEL_Pos) /*!< Select CKO clock source from high speed oscillator */
#define CLK_CLKSEL4_CKOSEL_LIRC (0x3UL<<CLK_CLKSEL4_CKOSEL_Pos) /*!< Select CKO clock source from low speed oscillator */
#define CLK_CLKSEL4_CKOSEL_CAPLL_DIV4 (0x4UL<<CLK_CLKSEL4_CKOSEL_Pos) /*!< Select CKO clock source from CA-PLL/4 */
#define CLK_CLKSEL4_CKOSEL_SYSPLL (0x5UL<<CLK_CLKSEL4_CKOSEL_Pos) /*!< Select CKO clock source from SYS-PLL */
#define CLK_CLKSEL4_CKOSEL_DDRPLL (0x6UL<<CLK_CLKSEL4_CKOSEL_Pos) /*!< Select CKO clock source from CA-PLL */
#define CLK_CLKSEL4_CKOSEL_EPLL_DIV2 (0x7UL<<CLK_CLKSEL4_CKOSEL_Pos) /*!< Select CKO clock source from EPLL/2 */
#define CLK_CLKSEL4_CKOSEL_APLL (0x8UL<<CLK_CLKSEL4_CKOSEL_Pos) /*!< Select CKO clock source from APLL */
#define CLK_CLKSEL4_CKOSEL_VPLL (0x9UL<<CLK_CLKSEL4_CKOSEL_Pos) /*!< Select CKO clock source from VPLL */
#define CLK_CLKSEL4_SC0SEL_HXT (0x0UL<<CLK_CLKSEL4_SC0SEL_Pos) /*!< Select SC0 clock source from high speed crystal */
#define CLK_CLKSEL4_SC0SEL_PCLK4 (0x1UL<<CLK_CLKSEL4_SC0SEL_Pos) /*!< Select SC0 clock source from PCLK4 */
#define CLK_CLKSEL4_SC1SEL_HXT (0x0UL<<CLK_CLKSEL4_SC1SEL_Pos) /*!< Select SC1 clock source from high speed crystal */
#define CLK_CLKSEL4_SC1SEL_PCLK4 (0x1UL<<CLK_CLKSEL4_SC1SEL_Pos) /*!< Select SC1 clock source from PCLK4 */
#define CLK_CLKSEL4_KPISEL_HXT (0x0UL<<CLK_CLKSEL4_KPISEL_Pos) /*!< Select KPI clock source from high speed crystal */
#define CLK_CLKSEL4_KPISEL_LXT (0x1UL<<CLK_CLKSEL4_KPISEL_Pos) /*!< Select KPI clock source from low speed crystal */
/*---------------------------------------------------------------------------------------------------------*/
/* CLKDIV0 constant definitions. */
/*---------------------------------------------------------------------------------------------------------*/
#define CLK_CLKDIV0_CANFD0(x) (((x) - 1UL) << CLK_CLKDIV0_CANFD0DIV_Pos) /*!< CLKDIV0 Setting for CANFD0 clock divider. It could be 1~8 \hideinitializer */
#define CLK_CLKDIV0_CANFD1(x) (((x) - 1UL) << CLK_CLKDIV0_CANFD1DIV_Pos) /*!< CLKDIV0 Setting for CANFD1 clock divider. It could be 1~8 \hideinitializer */
#define CLK_CLKDIV0_CANFD2(x) (((x) - 1UL) << CLK_CLKDIV0_CANFD2DIV_Pos) /*!< CLKDIV0 Setting for CANFD2 clock divider. It could be 1~8 \hideinitializer */
#define CLK_CLKDIV0_CANFD3(x) (((x) - 1UL) << CLK_CLKDIV0_CANFD3DIV_Pos) /*!< CLKDIV0 Setting for CANFD3 clock divider. It could be 1~8 \hideinitializer */
#define CLK_CLKDIV0_DCUP(x) (((x) - 1UL) << CLK_CLKDIV0_DCUPDIV_Pos) /*!< CLKDIV0 Setting for DCUP clock divider. It could be 1~8 \hideinitializer */
#define CLK_CLKDIV0_ACLK0(x) (((x) - 1UL) << CLK_CLKDIV0_ACLK0DIV_Pos) /*!< CLKDIV0 Setting for ACLK0 clock divider. It could be 1~2 \hideinitializer */
#define CLK_CLKDIV0_GMAC0(x) (((x) - 1UL) << CLK_CLKDIV0_GMAC0DIV_Pos) /*!< CLKDIV0 Setting for GMAC0 clock divider. It could be 1~4 \hideinitializer */
#define CLK_CLKDIV0_GMAC1(x) (((x) - 1UL) << CLK_CLKDIV0_GMAC1DIV_Pos) /*!< CLKDIV0 Setting for GMAC1 clock divider. It could be 1~4 \hideinitializer */
/*---------------------------------------------------------------------------------------------------------*/
/* CLKDIV1 constant definitions. */
/*---------------------------------------------------------------------------------------------------------*/
#define CLK_CLKDIV1_SC0(x) (((x) - 1UL) << CLK_CLKDIV1_SC0DIV_Pos) /*!< CLKDIV1 Setting for SC0 clock divider. It could be 1~16 \hideinitializer */
#define CLK_CLKDIV1_SC1(x) (((x) - 1UL) << CLK_CLKDIV1_SC1DIV_Pos) /*!< CLKDIV1 Setting for SC1 clock divider. It could be 1~16 \hideinitializer */
#define CLK_CLKDIV1_CCAP0(x) (((x) - 1UL) << CLK_CLKDIV1_CCAP0DIV_Pos) /*!< CLKDIV1 Setting for CCAP0 clock divider. It could be 1~16 \hideinitializer */
#define CLK_CLKDIV1_CCAP1(x) (((x) - 1UL) << CLK_CLKDIV1_CCAP1DIV_Pos) /*!< CLKDIV1 Setting for CCAP1 clock divider. It could be 1~16 \hideinitializer */
#define CLK_CLKDIV1_UART0(x) (((x) - 1UL) << CLK_CLKDIV1_UART0DIV_Pos) /*!< CLKDIV1 Setting for UART0 clock divider. It could be 1~16 \hideinitializer */
#define CLK_CLKDIV1_UART1(x) (((x) - 1UL) << CLK_CLKDIV1_UART1DIV_Pos) /*!< CLKDIV1 Setting for UART1 clock divider. It could be 1~16 \hideinitializer */
#define CLK_CLKDIV1_UART2(x) (((x) - 1UL) << CLK_CLKDIV1_UART2DIV_Pos) /*!< CLKDIV1 Setting for UART2 clock divider. It could be 1~16 \hideinitializer */
#define CLK_CLKDIV1_UART3(x) (((x) - 1UL) << CLK_CLKDIV1_UART3DIV_Pos) /*!< CLKDIV1 Setting for UART3 clock divider. It could be 1~16 \hideinitializer */
/*---------------------------------------------------------------------------------------------------------*/
/* CLKDIV2 constant definitions. */
/*---------------------------------------------------------------------------------------------------------*/
#define CLK_CLKDIV2_UART4(x) (((x) - 1UL) << CLK_CLKDIV2_UART4DIV_Pos) /*!< CLKDIV2 Setting for UART4 clock divider. It could be 1~16 \hideinitializer */
#define CLK_CLKDIV2_UART5(x) (((x) - 1UL) << CLK_CLKDIV2_UART5DIV_Pos) /*!< CLKDIV2 Setting for UART5 clock divider. It could be 1~16 \hideinitializer */
#define CLK_CLKDIV2_UART6(x) (((x) - 1UL) << CLK_CLKDIV2_UART6DIV_Pos) /*!< CLKDIV2 Setting for UART6 clock divider. It could be 1~16 \hideinitializer */
#define CLK_CLKDIV2_UART7(x) (((x) - 1UL) << CLK_CLKDIV2_UART7DIV_Pos) /*!< CLKDIV2 Setting for UART7 clock divider. It could be 1~16 \hideinitializer */
#define CLK_CLKDIV2_UART8(x) (((x) - 1UL) << CLK_CLKDIV2_UART8DIV_Pos) /*!< CLKDIV2 Setting for UART8 clock divider. It could be 1~16 \hideinitializer */
#define CLK_CLKDIV2_UART9(x) (((x) - 1UL) << CLK_CLKDIV2_UART9DIV_Pos) /*!< CLKDIV2 Setting for UART9 clock divider. It could be 1~16 \hideinitializer */
#define CLK_CLKDIV2_UART10(x) (((x) - 1UL) << CLK_CLKDIV2_UART10DIV_Pos) /*!< CLKDIV2 Setting for UART10 clock divider. It could be 1~16 \hideinitializer */
#define CLK_CLKDIV2_UART11(x) (((x) - 1UL) << CLK_CLKDIV2_UART11DIV_Pos) /*!< CLKDIV2 Setting for UART11 clock divider. It could be 1~16 \hideinitializer */
/*---------------------------------------------------------------------------------------------------------*/
/* CLKDIV3 constant definitions. */
/*---------------------------------------------------------------------------------------------------------*/
#define CLK_CLKDIV3_UART12(x) (((x) - 1UL) << CLK_CLKDIV3_UART12DIV_Pos) /*!< CLKDIV3 Setting for UART12 clock divider. It could be 1~16 \hideinitializer */
#define CLK_CLKDIV3_UART13(x) (((x) - 1UL) << CLK_CLKDIV3_UART13DIV_Pos) /*!< CLKDIV3 Setting for UART13 clock divider. It could be 1~16 \hideinitializer */
#define CLK_CLKDIV3_UART14(x) (((x) - 1UL) << CLK_CLKDIV3_UART14DIV_Pos) /*!< CLKDIV3 Setting for UART14 clock divider. It could be 1~16 \hideinitializer */
#define CLK_CLKDIV3_UART15(x) (((x) - 1UL) << CLK_CLKDIV3_UART15DIV_Pos) /*!< CLKDIV3 Setting for UART15 clock divider. It could be 1~16 \hideinitializer */
#define CLK_CLKDIV3_UART16(x) (((x) - 1UL) << CLK_CLKDIV3_UART16DIV_Pos) /*!< CLKDIV3 Setting for UART16 clock divider. It could be 1~16 \hideinitializer */
/*---------------------------------------------------------------------------------------------------------*/
/* CLKDIV4 constant definitions. */
/*---------------------------------------------------------------------------------------------------------*/
#define CLK_CLKDIV4_EADC(x) (((x) - 1UL) << CLK_CLKDIV4_EADCDIV_Pos) /*!< CLKDIV4 Setting for EADC clock divider. It could be 1~16 \hideinitializer */
#define CLK_CLKDIV4_ADC(x) (((x) - 1UL) << CLK_CLKDIV4_ADCDIV_Pos) /*!< CLKDIV4 Setting for ADC clock divider. It could be 1~131072 \hideinitializer */
#define CLK_CLKDIV4_KPI(x) (((x) - 1UL) << CLK_CLKDIV4_KPIDIV_Pos) /*!< CLKDIV4 Setting for KPI clock divider. It could be 1~256 \hideinitializer */
/*---------------------------------------------------------------------------------------------------------*/
/* MODULE constant definitions. */
/*---------------------------------------------------------------------------------------------------------*/
/* APBCLK(31:29)|CLKSEL(28:26)|CLKSEL_Msk(25:22) |CLKSEL_Pos(21:17)|CLKDIV(16:14)|CLKDIV_Msk(13:10)|CLKDIV_Pos(9:5)|IP_EN_Pos(4:0) */
#define MODULE_APBCLK(x) (((x) >>29) & 0x7UL) /*!< Calculate SYSCLK/APBCLK offset on MODULE index, 0x0:SYSCLK0, 0x1:SYSCLK1, 0x2:APBCLK0, 0x3:APBCLK1, 0x4:APBCLK2 \hideinitializer */
#define MODULE_CLKSEL(x) (((x) >>26) & 0x7UL) /*!< Calculate CLKSEL offset on MODULE index, 0x0:CLKSEL0, 0x1:CLKSEL1, 0x2:CLKSEL2, 0x3:CLKSEL3, 0x4:CLKSEL4 \hideinitializer */
#define MODULE_CLKSEL_Msk(x) (((x) >>22) & 0xfUL) /*!< Calculate CLKSEL mask offset on MODULE index \hideinitializer */
#define MODULE_CLKSEL_Pos(x) (((x) >>17) & 0x1fUL) /*!< Calculate CLKSEL position offset on MODULE index \hideinitializer */
#define MODULE_CLKDIV(x) (((x) >>14) & 0x7UL) /*!< Calculate APBCLK CLKDIV on MODULE index, 0x0:CLKDIV0, 0x1:CLKDIV1, 0x2:CLKDIV2, 0x3:CLKDIV3, 0x4:CLKDIV4 \hideinitializer */
#define MODULE_CLKDIV_Msk(x) (((x) >>10) & 0xfUL) /*!< Calculate CLKDIV mask offset on MODULE index \hideinitializer */
#define MODULE_CLKDIV_Pos(x) (((x) >>5 ) & 0x1fUL) /*!< Calculate CLKDIV position offset on MODULE index \hideinitializer */
#define MODULE_IP_EN_Pos(x) (((x) >>0 ) & 0x1fUL) /*!< Calculate APBCLK offset on MODULE index \hideinitializer */
#define MODULE_NoMsk 0x0UL /*!< Not mask on MODULE index \hideinitializer */
#define NA MODULE_NoMsk /*!< Not Available \hideinitializer */
#define MODULE_APBCLK_ENC(x) (((x) & 0x07UL) << 29) /*!< MODULE index, 0x0:SYSCLK0, 0x1:SYSCLK1, 0x2:APBCLK0, 0x3:APBCLK1, 0x4:APBCLK2 \hideinitializer */
#define MODULE_CLKSEL_ENC(x) (((x) & 0x07UL) << 26) /*!< CLKSEL offset on MODULE index, 0x0:CLKSEL0, 0x1:CLKSEL1, 0x2:CLKSEL2, 0x3:CLKSEL3, 0x4:CLKSEL4 \hideinitializer */
#define MODULE_CLKSEL_Msk_ENC(x) (((x) & 0x0fUL) << 22) /*!< CLKSEL mask offset on MODULE index \hideinitializer */
#define MODULE_CLKSEL_Pos_ENC(x) (((x) & 0x1fUL) << 17) /*!< CLKSEL position offset on MODULE index \hideinitializer */
#define MODULE_CLKDIV_ENC(x) (((x) & 0x07UL) << 14) /*!< APBCLK CLKDIV on MODULE index, 0x0:CLKDIV0, 0x1:CLKDIV1, 0x2:CLKDIV2, 0x3:CLKDIV3, 0x4:CLKDIV4 \hideinitializer */
#define MODULE_CLKDIV_Msk_ENC(x) (((x) & 0x0fUL) << 10) /*!< CLKDIV mask offset on MODULE index \hideinitializer */
#define MODULE_CLKDIV_Pos_ENC(x) (((x) & 0x1fUL) << 5 ) /*!< CLKDIV position offset on MODULE index \hideinitializer */
#define MODULE_IP_EN_Pos_ENC(x) (((x) & 0x1fUL) << 0 ) /*!< AHBCLK/APBCLK offset on MODULE index \hideinitializer */
#define PDMA0_MODULE ((1UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(0UL<<0)) /*!< PDMA0 Module \hideinitializer */
#define PDMA1_MODULE ((1UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(1UL<<0)) /*!< PDMA1 Module \hideinitializer */
#define PDMA2_MODULE ((1UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(2UL<<0)) /*!< PDMA2 Module \hideinitializer */
#define PDMA3_MODULE ((1UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(3UL<<0)) /*!< PDMA3 Module \hideinitializer */
#define WH0_MODULE ((1UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(4UL<<0)) /*!< WH0 Module \hideinitializer */
#define WH1_MODULE ((1UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(5UL<<0)) /*!< WH1 Module \hideinitializer */
#define HWS_MODULE ((1UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(6UL<<0)) /*!< HWS Module \hideinitializer */
#define EBI_MODULE ((1UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(7UL<<0)) /*!< EBI Module \hideinitializer */
#define SRAM0_MODULE ((1UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(8UL<<0)) /*!< SRAM0 Module \hideinitializer */
#define SRAM1_MODULE ((1UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(9UL<<0)) /*!< SRAM1 Module \hideinitializer */
#define ROM_MODULE ((1UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(10UL<<0)) /*!< ROM Module \hideinitializer */
#define TRA_MODULE ((1UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(11UL<<0)) /*!< TRA Module \hideinitializer */
#define DBG_MODULE ((1UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(12UL<<0)) /*!< DBG Module \hideinitializer */
#define CLKO_MODULE ((1UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(13UL<<0)) /*!< CLKO Module \hideinitializer */
#define GTMR_MODULE ((1UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(14UL<<0)) /*!< GTMR Module \hideinitializer */
#define GPA_MODULE ((1UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(16UL<<0)) /*!< GPA Module \hideinitializer */
#define GPB_MODULE ((1UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(17UL<<0)) /*!< GPB Module \hideinitializer */
#define GPC_MODULE ((1UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(18UL<<0)) /*!< GPC Module \hideinitializer */
#define GPD_MODULE ((1UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(19UL<<0)) /*!< GPD Module \hideinitializer */
#define GPE_MODULE ((1UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(20UL<<0)) /*!< GPE Module \hideinitializer */
#define GPF_MODULE ((1UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(21UL<<0)) /*!< GPF Module \hideinitializer */
#define GPG_MODULE ((1UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(22UL<<0)) /*!< GPG Module \hideinitializer */
#define GPH_MODULE ((1UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(23UL<<0)) /*!< GPH Module \hideinitializer */
#define GPI_MODULE ((1UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(24UL<<0)) /*!< GPI Module \hideinitializer */
#define GPJ_MODULE ((1UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(25UL<<0)) /*!< GPJ Module \hideinitializer */
#define GPK_MODULE ((1UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(26UL<<0)) /*!< GPK Module \hideinitializer */
#define GPL_MODULE ((1UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(27UL<<0)) /*!< GPL Module \hideinitializer */
#define GPM_MODULE ((1UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(28UL<<0)) /*!< GPM Module \hideinitializer */
#define GPN_MODULE ((1UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(29UL<<0)) /*!< GPN Module \hideinitializer */
#define CA35_MODULE ((0UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(0UL<<0)) /*!< CA35 Module \hideinitializer */
#define RTP_MODULE ((0UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(1UL<<0)) /*!< RTP Module \hideinitializer */
#define TAHB_MODULE ((0UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(2UL<<0)) /*!< TAHB Module \hideinitializer */
#define LVRDB_MODULE ((0UL<<29)|(0UL<<26) |(0x1UL<<22) |(3UL<<17) |(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(3UL<<0)) /*!< LVRDB Module \hideinitializer */
#define DDR0_MODULE ((0UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(4UL<<0)) /*!< DDR0 Module \hideinitializer */
#define DDR6_MODULE ((0UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(5UL<<0)) /*!< DDR6 Module \hideinitializer */
#define CANFD0_MODULE ((0UL<<29)|(4<<26)|(1<<22)|(16<<17)|(0<<14)|(7<<10)|(0<<5)|(8UL<<0)) /*!< CANFD0 Module \hideinitializer */
#define CANFD1_MODULE ((0UL<<29)|(4<<26)|(1<<22)|(17<<17)|(0<<14)|(7<<10)|(4<<5)|(9UL<<0)) /*!< CANFD1 Module \hideinitializer */
#define CANFD2_MODULE ((0UL<<29)|(4<<26)|(1<<22)|(18<<17)|(0<<14)|(7<<10)|(8<<5)|(10UL<<0)) /*!< CANFD2 Module \hideinitializer */
#define CANFD3_MODULE ((0UL<<29)|(4<<26)|(1<<22)|(19<<17)|(0<<14)|(7<<10)|(12<<5)|(11UL<<0)) /*!< CANFD3 Module \hideinitializer */
#define SDH0_MODULE ((0UL<<29)|(0UL<<26) |(0x3UL<<22) |(0x10UL<<17) |(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(16UL<<0)) /*!< SDH0 Module */
#define SDH1_MODULE ((0UL<<29)|(0UL<<26) |(0x3UL<<22) |(0x12UL<<17) |(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(17UL<<0)) /*!< SDH1 Module */
#define NAND_MODULE ((0UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(18UL<<0)) /*!< NAND Module \hideinitializer */
#define USBD_MODULE ((0UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(19UL<<0)) /*!< USBD Module \hideinitializer */
#define USBH_MODULE ((0UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(20UL<<0)) /*!< USBH Module \hideinitializer */
#define HUSBH0_MODULE ((0UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(21UL<<0)) /*!< HUSBH0 Module \hideinitializer */
#define HUSBH1_MODULE ((0UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(22UL<<0)) /*!< HUSBH1 Module \hideinitializer */
#define GFX_MODULE ((0UL<<29)|(0UL<<26) |(0x1UL<<22) |(26UL<<17) |(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(24UL<<0)) /*!< GFX Module \hideinitializer */
#define VDEC_MODULE ((0UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(25UL<<0)) /*!< VDEC Module \hideinitializer */
#define DCU_MODULE ((0UL<<29)|(0UL<<26) |(0x1UL<<22) |(24UL<<17) |(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(26UL<<0)) /*!< DCU Module \hideinitializer */
#define GMAC0_MODULE ((0UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(0UL<<14) |(0x3UL<<10) |(28UL<<5) |(27UL<<0)) /*!< GMAC0 Module \hideinitializer */
#define GMAC1_MODULE ((0UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(0UL<<14) |(0x3UL<<10) |(30UL<<5) |(28UL<<0)) /*!< GMAC1 Module \hideinitializer */
#define CCAP0_MODULE ((0UL<<29)|(0UL<<26) |(0x3UL<<22) |(12UL<<17) |(1UL<<14) |(0xFUL<<10) |(8UL<<5) |(29UL<<0)) /*!< CCAP0 Module \hideinitializer */
#define CCAP1_MODULE ((0UL<<29)|(0UL<<26) |(0x3UL<<22) |(14UL<<17) |(1UL<<14) |(0xFUL<<10) |(12UL<<5) |(30UL<<0)) /*!< CCAP1 Module \hideinitializer */
#define TMR0_MODULE ((2UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(0UL<<0)) /*!< TMR0 Module \hideinitializer */
#define TMR1_MODULE ((2UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(1UL<<0)) /*!< TMR1 Module \hideinitializer */
#define TMR2_MODULE ((2UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(2UL<<0)) /*!< TMR2 Module \hideinitializer */
#define TMR3_MODULE ((2UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(3UL<<0)) /*!< TMR3 Module \hideinitializer */
#define TMR4_MODULE ((2UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(4UL<<0)) /*!< TMR4 Module \hideinitializer */
#define TMR5_MODULE ((2UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(5UL<<0)) /*!< TMR5 Module \hideinitializer */
#define TMR6_MODULE ((2UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(6UL<<0)) /*!< TMR6 Module \hideinitializer */
#define TMR7_MODULE ((2UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(7UL<<0)) /*!< TMR7 Module \hideinitializer */
#define TMR8_MODULE ((2UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(8UL<<0)) /*!< TMR8 Module \hideinitializer */
#define TMR9_MODULE ((2UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(9UL<<0)) /*!< TMR9 Module \hideinitializer */
#define TMR10_MODULE ((2UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(10UL<<0)) /*!< TMR10 Module \hideinitializer */
#define TMR11_MODULE ((2UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(11UL<<0)) /*!< TMR11 Module \hideinitializer */
#define UART0_MODULE ((2UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(12UL<<0)) /*!< UART0 Module \hideinitializer */
#define UART1_MODULE ((2UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(13UL<<0)) /*!< UART1 Module \hideinitializer */
#define UART2_MODULE ((2UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(14UL<<0)) /*!< UART2 Module \hideinitializer */
#define UART3_MODULE ((2UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(15UL<<0)) /*!< UART3 Module \hideinitializer */
#define UART4_MODULE ((2UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(16UL<<0)) /*!< UART4 Module \hideinitializer */
#define UART5_MODULE ((2UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(17UL<<0)) /*!< UART5 Module \hideinitializer */
#define UART6_MODULE ((2UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(18UL<<0)) /*!< UART6 Module \hideinitializer */
#define UART7_MODULE ((2UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(19UL<<0)) /*!< UART7 Module \hideinitializer */
#define UART8_MODULE ((2UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(20UL<<0)) /*!< UART8 Module \hideinitializer */
#define UART9_MODULE ((2UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(21UL<<0)) /*!< UART9 Module \hideinitializer */
#define UART10_MODULE ((2UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(22UL<<0)) /*!< UART10 Module \hideinitializer */
#define UART11_MODULE ((2UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(23UL<<0)) /*!< UART11 Module \hideinitializer */
#define UART12_MODULE ((2UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(24UL<<0)) /*!< UART12 Module \hideinitializer */
#define UART13_MODULE ((2UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(25UL<<0)) /*!< UART13 Module \hideinitializer */
#define UART14_MODULE ((2UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(26UL<<0)) /*!< UART14 Module \hideinitializer */
#define UART15_MODULE ((2UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(27UL<<0)) /*!< UART15 Module \hideinitializer */
#define UART16_MODULE ((2UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(28UL<<0)) /*!< UART16 Module \hideinitializer */
#define RTC_MODULE ((2UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(29UL<<0)) /*!< RTC Module \hideinitializer */
#define DDRP_MODULE ((2UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(30UL<<0)) /*!< DDRP Module \hideinitializer */
#define KPI_MODULE ((2UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(31UL<<0)) /*!< KPI Module \hideinitializer */
#define I2C0_MODULE ((3UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(0UL<<0)) /*!< I2C0 Module \hideinitializer */
#define I2C1_MODULE ((3UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(1UL<<0)) /*!< I2C1 Module \hideinitializer */
#define I2C2_MODULE ((3UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(2UL<<0)) /*!< I2C2 Module \hideinitializer */
#define I2C3_MODULE ((3UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(3UL<<0)) /*!< I2C3 Module \hideinitializer */
#define I2C4_MODULE ((3UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(4UL<<0)) /*!< I2C4 Module \hideinitializer */
#define I2C5_MODULE ((3UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(5UL<<0)) /*!< I2C5 Module \hideinitializer */
#define QSPI0_MODULE ((3UL<<29)|(4UL<<26) |(0x3UL<<22) |(8UL<<17) |(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(6UL<<0)) /*!< QSPI0 Module \hideinitializer */
#define QSPI1_MODULE ((3UL<<29)|(4UL<<26) |(0x3UL<<22) |(10UL<<17) |(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(7UL<<0)) /*!< QSPI1 Module \hideinitializer */
#define SC0_MODULE ((3UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(12UL<<0)) /*!< SC0 Module \hideinitializer */
#define SC1_MODULE ((3UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(13UL<<0)) /*!< SC1 Module \hideinitializer */
#define WDT0_MODULE ((3UL<<29)|(3UL<<26) |(0x3UL<<22) |(20UL<<17) |(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(16UL<<0)) /*!< WDT0 Module \hideinitializer */
#define WDT1_MODULE ((3UL<<29)|(3UL<<26) |(0x3UL<<22) |(24UL<<17) |(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(17UL<<0)) /*!< WDT1 Module \hideinitializer */
#define WDT2_MODULE ((3UL<<29)|(3UL<<26) |(0x3UL<<22) |(28UL<<17) |(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(18UL<<0)) /*!< WDT2 Module \hideinitializer */
#define EPWM0_MODULE ((3UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(24UL<<0)) /*!< EPWM0 Module \hideinitializer */
#define EPWM1_MODULE ((3UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(25UL<<0)) /*!< EPWM1 Module \hideinitializer */
#define EPWM2_MODULE ((3UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(26UL<<0)) /*!< EPWM2 Module \hideinitializer */
#define I2S0_MODULE ((4UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(0UL<<0)) /*!< I2S0 Module \hideinitializer */
#define I2S1_MODULE ((4UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(1UL<<0)) /*!< I2S1 Module \hideinitializer */
#define SSMCC_MODULE ((4UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(2UL<<0)) /*!< SSMCC Module \hideinitializer */
#define SSPCC_MODULE ((4UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(3UL<<0)) /*!< SSPCC Module \hideinitializer */
#define SPI0_MODULE ((4UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(4UL<<0)) /*!< SPI0 Module \hideinitializer */
#define SPI1_MODULE ((4UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(5UL<<0)) /*!< SPI1 Module \hideinitializer */
#define SPI2_MODULE ((4UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(6UL<<0)) /*!< SPI2 Module \hideinitializer */
#define SPI3_MODULE ((4UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(7UL<<0)) /*!< SPI3 Module \hideinitializer */
#define ECAP0_MODULE ((4UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(8UL<<0)) /*!< ECAP0 Module \hideinitializer */
#define ECAP1_MODULE ((4UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(9UL<<0)) /*!< ECAP1 Module \hideinitializer */
#define ECAP2_MODULE ((4UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(10UL<<0)) /*!< ECAP2 Module \hideinitializer */
#define QEI0_MODULE ((4UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(12UL<<0)) /*!< QEI0 Module \hideinitializer */
#define QEI1_MODULE ((4UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(13UL<<0)) /*!< QEI1 Module \hideinitializer */
#define QEI2_MODULE ((4UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(14UL<<0)) /*!< QEI2 Module \hideinitializer */
#define ADC_MODULE ((4UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(24UL<<0)) /*!< ADCModule \hideinitializer */
#define EADC0_MODULE ((4UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(25UL<<0)) /*!< EADC0 Module \hideinitializer */
/*@}*/ /* end of group CLK_EXPORTED_CONSTANTS */
/** @addtogroup CLK_EXPORTED_FUNCTIONS CLK Exported Functions
@{
*/
#if defined (USE_MA35D1_SUBM)
/*---------------------------------------------------------------------------------------------------------*/
/* static inline functions */
/*---------------------------------------------------------------------------------------------------------*/
/* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */
__STATIC_INLINE void CLK_SysTickDelay(uint32_t us);
__STATIC_INLINE void CLK_SysTickLongDelay(uint32_t us);
/**
* @brief This function execute delay function.
* @param[in] us Delay time. The Max value is 2^24 / CPU Clock(MHz). Ex:
* 72MHz => 233016us, 50MHz => 335544us,
* 48MHz => 349525us, 28MHz => 699050us ...
* @return None
* @details Use the SysTick to generate the delay time and the unit is in us.
* The SysTick clock source is from HCLK, i.e the same as system core clock.
*/
__STATIC_INLINE void CLK_SysTickDelay(uint32_t us)
{
SysTick->LOAD = us * CyclesPerUs;
SysTick->VAL = 0x0UL;
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk;
/* Waiting for down-count to zero */
while ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == 0UL)
{
}
/* Disable SysTick counter */
SysTick->CTRL = 0UL;
}
/**
* @brief This function execute long delay function.
* @param[in] us Delay time.
* @return None
* @details Use the SysTick to generate the long delay time and the UNIT is in us.
* The SysTick clock source is from HCLK, i.e the same as system core clock.
* User can use SystemCoreClockUpdate() to calculate CyclesPerUs automatically before using this function.
*/
__STATIC_INLINE void CLK_SysTickLongDelay(uint32_t us)
{
uint32_t delay;
/* It should <= 349525us for each delay loop */
delay = 349525UL;
do
{
if (us > delay)
{
us -= delay;
}
else
{
delay = us;
us = 0UL;
}
SysTick->LOAD = delay * CyclesPerUs;
SysTick->VAL = (0x0UL);
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk;
/* Waiting for down-count to zero */
while ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == 0UL);
/* Disable SysTick counter */
SysTick->CTRL = 0UL;
}
while (us > 0UL);
}
#else
void SystemCoreClockUpdate(void);
#endif
__STATIC_INLINE void CLK_SetPLLPowerDown(uint32_t u32PllIdx)
{
CLK->PLL[u32PllIdx].CTL1 |= CLK_PLLnCTL1_PD_Msk;
}
void CLK_DisableCKO(void);
void CLK_EnableCKO(uint32_t u32ClkSrc, uint32_t u32ClkDiv, uint32_t u32ClkDivBy1En);
void CLK_PowerDown(void);
uint32_t CLK_GetHXTFreq(void);
uint32_t CLK_GetLXTFreq(void);
uint32_t CLK_GetSYSCLK0Freq(void);
uint32_t CLK_GetSYSCLK1Freq(void);
uint32_t CLK_GetPCLK3Freq(void);
uint32_t CLK_GetCPUFreq(void);
uint32_t CLK_SetCoreClock(uint32_t u32Hclk);
void CLK_SetModuleClock(uint32_t u32ModuleIdx, uint32_t u32ClkSrc, uint32_t u32ClkDiv);
void CLK_SetSysTickClockSrc(uint32_t u32ClkSrc);
void CLK_EnableXtalRC(uint32_t u32ClkMask);
void CLK_DisableXtalRC(uint32_t u32ClkMask);
void CLK_EnableModuleClock(uint32_t u32ModuleIdx);
void CLK_DisableModuleClock(uint32_t u32ModuleIdx);
void CLK_DisablePLL(uint32_t u32PllIdx);
uint32_t CLK_WaitClockReady(uint32_t u32ClkMask);
void CLK_EnableSysTick(uint32_t u32ClkSrc, uint32_t u32Count);
void CLK_DisableSysTick(void);
uint32_t CLK_GetCAPLLClockFreq(void);
uint32_t CLK_GetPLLClockFreq(uint32_t u32PllIdx);
uint32_t CLK_GetModuleClockSource(uint32_t u32ModuleIdx);
uint32_t CLK_GetModuleClockDivider(uint32_t u32ModuleIdx);
uint32_t CLK_GetCAPLLClockFreq(void);
uint64_t CLK_SetPLLFreq(uint32_t u32PllIdx, uint32_t u32OpMode, uint64_t PllSrcClk, uint64_t u64PllFreq);
uint32_t CLK_GetPLLClockFreq(uint32_t u32PllIdx);
uint32_t CLK_GetPLLOpMode(uint32_t u32PllIdx);
#define CLK_GetPCLK0Freq() CLK_GetSYSCLK1Freq()
#define CLK_GetPCLK1Freq() CLK_GetSYSCLK1Freq()
#define CLK_GetPCLK2Freq() CLK_GetSYSCLK1Freq()
#define CLK_GetPCLK3Freq() (CLK_GetSYSCLK1Freq() / 2)
#define CLK_GetPCLK4Freq() (CLK_GetSYSCLK1Freq() / 2)
#define CLK_GetHCLK0Freq() CLK_GetSYSCLK1Freq()
#define CLK_GetHCLK1Freq() CLK_GetSYSCLK1Freq()
#define CLK_GetHCLK2Freq() CLK_GetSYSCLK1Freq()
#define CLK_GetHCLK3Freq() (CLK_GetSYSCLK1Freq() / 2)
#define CLK_GetCA35CPUFreq CLK_GetCAPLLClockFreq
/*@}*/ /* end of group CLK_EXPORTED_FUNCTIONS */
/*@}*/ /* end of group CLK_Driver */
/*@}*/ /* end of group Standard_Driver */
#ifdef __cplusplus
}
#endif
#endif /* __NU_CLK_H__ */

205
bsp/nuvoton/libraries/ma35/StdDriver/inc/nu_disp.h Normal file
View File

@ -0,0 +1,205 @@
/**************************************************************************//**
* @file nu_disp.h
* @brief DISP driver header file
*
* SPDX-License-Identifier: Apache-2.0
* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __NU_DISP_H__
#define __NU_DISP_H__
#ifdef __cplusplus
extern "C"
{
#endif
/** @addtogroup Standard_Driver Standard Driver
@{
*/
/** @addtogroup DISP_Driver DISP Driver
@{
*/
/** @addtogroup DISP_EXPORTED_CONSTANTS DISP Exported Constants
@{
*/
typedef enum
{
eDispLcd_1024x600 = 0,
eDispLcd_800x480 = 1,
eDispLcd_1920x1080 = 2,
eDispLcd_Cnt
} E_DISP_LCD;
typedef enum
{
ePolarity_Disable = -1,
ePolarity_Positive = 0,
ePolarity_Negative = 1
} E_POLARITY;
typedef enum
{
eDPIFmt_D16CFG1,
eDPIFmt_D16CFG2,
eDPIFmt_D16CFG3,
eDPIFmt_D18CFG1,
eDPIFmt_D18CFG2,
eDPIFmt_D24
} E_DPI_DATA_FMT;
typedef enum
{
eLayer_Video = 0,
eLayer_Overlay = 1,
eLayer_Cnt
} E_DISP_LAYER;
typedef enum
{
eYUV_709_BT709 = 1,
eYUV_2020_BT2020 = 3,
} E_YUV_STANDARD;
typedef enum
{
eFBFmt_X4R4G4B4 = 0,
eFBFmt_A4R4G4B4 = 1,
eFBFmt_X1R5G5B5 = 2,
eFBFmt_A1R5G5B5 = 3,
eFBFmt_R5G6B5 = 4,
eFBFmt_X8R8G8B8 = 5,
eFBFmt_A8R8G8B8 = 6,
eFBFmt_YUY2 = 7,
eFBFmt_UYVY = 8,
eFBFmt_INDEX8 = 9,
eFBFmt_MONOCHROME = 10,
eFBFmt_YV12 = 15,
eFBFmt_A8 = 16,
eFBFmt_NV12 = 17,
eFBFmt_NV16 = 18,
eFBFmt_RG16 = 19,
eFBFmt_R8 = 20,
eFBFmt_NV12_10BIT = 21,
eFBFmt_A2R10G10B10 = 22,
eFBFmt_NV16_10BIT = 23,
eFBFmt_INDEX1 = 24,
eFBFmt_INDEX2 = 25,
eFBFmt_INDEX4 = 26,
eFBFmt_P010 = 27,
eFBFmt_NV12_10BIT_L1 = 28,
eFBFmt_NV16_10BIT_L1 = 29
} E_FB_FMT;
typedef enum
{
eOPAQUE,
eMASK,
eKEY
} E_TRANSPARENCY_MODE;
typedef enum
{
DC_BLEND_MODE_CLEAR,
DC_BLEND_MODE_SRC,
DC_BLEND_MODE_DST,
DC_BLEND_MODE_SRC_OVER,
DC_BLEND_MODE_DST_OVER,
DC_BLEND_MODE_SRC_IN,
DC_BLEND_MODE_DST_IN,
DC_BLEND_MODE_SRC_OUT
} E_DC_BLEND_MODE;
typedef enum
{
eGloAM_NORMAL,
eGloAM_GLOBAL,
eGloAM_SCALED
} E_GLOBAL_ALPHA_MODE;
typedef enum
{
eBM_ZERO,
eBM_ONE,
eBM_NORMAL,
eBM_INVERSED,
eBM_COLOR,
eBM_COLOR_INVERSED,
eBM_SATURATED_ALPHA,
eBM_SATURATED_DEST_ALPHA
} E_BLENDING_MODE;
typedef struct
{
/*
htotal: u32HA + u32HBP + u32HFP + u32HSL
vtotal: u32VA + u32VBP + u32VFP + u32VSL
clock-frequency: htotal * vtotal * fps
*/
uint32_t u32PCF; // Pixel Clock Frequency
uint32_t u32HA; // Horizontal Active
uint32_t u32HSL; // Horizontal Sync Length
uint32_t u32HFP; // Horizontal Front Porch
uint32_t u32HBP; // Horizontal Back Porch
uint32_t u32VA; // Vertical Active
uint32_t u32VSL; // Vertical Sync Len
uint32_t u32VFP; // Vertical Front Porch
uint32_t u32VBP; // Vertical Back Porch
E_POLARITY eHSPP; // HSync Pulse Polarity
E_POLARITY eVSPP; // VSync Pulse Polarity
} DISP_LCD_TIMING;
typedef struct
{
E_DPI_DATA_FMT eDpiFmt; // DPI Data Format
E_POLARITY eDEP; // DE Polarity
E_POLARITY eDP; // DATA Polarity
E_POLARITY eCP; // CLOCK Polarity
} DISP_PANEL_CONF;
typedef struct
{
uint32_t u32ResolutionWidth;
uint32_t u32ResolutionHeight;
DISP_LCD_TIMING sLcdTiming;
DISP_PANEL_CONF sPanelConf;
} DISP_LCD_INFO;
#define DISP_ENABLE_INT() (DISP->DisplayIntrEnable |= DISP_DisplayIntrEnable_DISP0_Msk)
#define DISP_DISABLE_INT() (DISP->DisplayIntrEnable &= ~DISP_DisplayIntrEnable_DISP0_Msk)
#define DISP_GET_INTSTS() (DISP->DisplayIntr & DISP_DisplayIntr_DISP0_Msk)
const DISP_LCD_INFO *DISP_GetLCDInst(E_DISP_LCD eDispLcd);
int32_t DISP_LCDInit(const DISP_LCD_INFO *psLCDInfo);
int32_t DISP_LCDDeinit(void);
int DISP_SetFBConfig(E_DISP_LAYER eLayer, E_FB_FMT eFbFmt, uint32_t u32ResWidth, uint32_t u32ResHeight, uint32_t u32DMAFBStartAddr);
void DISP_SetPanelConf(DISP_PANEL_CONF *psPanelConf);
void DISP_SetTiming(DISP_LCD_TIMING *psLCDTiming);
int DISP_Trigger(E_DISP_LAYER eLayer, uint32_t u32Action);
int DISP_SetTransparencyMode(E_DISP_LAYER eLayer, E_TRANSPARENCY_MODE eTM);
int DISP_SetBlendOpMode(E_DC_BLEND_MODE eDCBM, E_GLOBAL_ALPHA_MODE eGloAM_Src, E_GLOBAL_ALPHA_MODE eGloAM_Dst);
void DISP_SetBlendValue(uint32_t u32GloAV_Src, uint32_t u32GloAV_Dst);
void DISP_SetColorKeyValue(uint32_t u32ColorKeyLow, uint32_t u32ColorKeyHigh);
int DISP_SetFBAddr(E_DISP_LAYER eLayer, uint32_t u32DMAFBStartAddr);
int DISP_SetFBFmt(E_DISP_LAYER eLayer, E_FB_FMT eFbFmt, uint32_t u32Pitch);
/*@}*/ /* end of group DISP_EXPORTED_FUNCTIONS */
/*@}*/ /* end of group DISP_Driver */
/*@}*/ /* end of group Standard_Driver */
#ifdef __cplusplus
}
#endif
#endif /* __NU_DISP_H__ */

630
bsp/nuvoton/libraries/ma35/StdDriver/inc/nu_eadc.h Normal file
View File

@ -0,0 +1,630 @@
/**************************************************************************//**
* @file nu_eadc.h
* @brief EADC driver header file
*
* SPDX-License-Identifier: Apache-2.0
* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __NU_EADC_H__
#define __NU_EADC_H__
#ifdef __cplusplus
extern "C"
{
#endif
/** @addtogroup Standard_Driver Standard Driver
@{
*/
/** @addtogroup EADC_Driver EADC Driver
@{
*/
/** @addtogroup EADC_EXPORTED_CONSTANTS EADC Exported Constants
@{
*/
/*---------------------------------------------------------------------------------------------------------*/
/* EADC_CTL Constant Definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define EADC_CTL_DIFFEN_SINGLE_END (0UL<<EADC_CTL_DIFFEN_Pos) /*!< Single-end input mode \hideinitializer */
#define EADC_CTL_DIFFEN_DIFFERENTIAL (1UL<<EADC_CTL_DIFFEN_Pos) /*!< Differential input mode \hideinitializer */
#define EADC_CTL_DMOF_STRAIGHT_BINARY (0UL<<EADC_CTL_DMOF_Pos) /*!< Select the straight binary format as the output format of the conversion result \hideinitializer */
#define EADC_CTL_DMOF_TWOS_COMPLEMENT (1UL<<EADC_CTL_DMOF_Pos) /*!< Select the 2's complement format as the output format of the conversion result \hideinitializer */
/*---------------------------------------------------------------------------------------------------------*/
/* EADC_SCTL Constant Definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define EADC_SCTL_CHSEL(x) ((x) << EADC_SCTL_CHSEL_Pos) /*!< A/D sample module channel selection \hideinitializer */
#define EADC_SCTL_TRGDLYDIV(x) ((x) << EADC_SCTL_TRGDLYDIV_Pos) /*!< A/D sample module start of conversion trigger delay clock divider selection \hideinitializer */
#define EADC_SCTL_TRGDLYCNT(x) ((x) << EADC_SCTL_TRGDLYCNT_Pos) /*!< A/D sample module start of conversion trigger delay time \hideinitializer */
#define EADC_SOFTWARE_TRIGGER (0UL<<EADC_SCTL_TRGSEL_Pos) /*!< Software trigger \hideinitializer */
#define EADC_FALLING_EDGE_TRIGGER (EADC_SCTL_EXTFEN_Msk | (1UL<<EADC_SCTL_TRGSEL_Pos)) /*!< STADC pin falling edge trigger \hideinitializer */
#define EADC_RISING_EDGE_TRIGGER (EADC_SCTL_EXTREN_Msk | (1UL<<EADC_SCTL_TRGSEL_Pos)) /*!< STADC pin rising edge trigger \hideinitializer */
#define EADC_FALLING_RISING_EDGE_TRIGGER (EADC_SCTL_EXTFEN_Msk | EADC_SCTL_EXTREN_Msk | (1UL<<EADC_SCTL_TRGSEL_Pos)) /*!< STADC pin both falling and rising edge trigger \hideinitializer */
#define EADC_ADINT0_TRIGGER (2UL<<EADC_SCTL_TRGSEL_Pos) /*!< ADC ADINT0 interrupt EOC pulse trigger \hideinitializer */
#define EADC_ADINT1_TRIGGER (3UL<<EADC_SCTL_TRGSEL_Pos) /*!< ADC ADINT1 interrupt EOC pulse trigger \hideinitializer */
#define EADC_TIMER0_TRIGGER (4UL<<EADC_SCTL_TRGSEL_Pos) /*!< Timer0 overflow pulse trigger \hideinitializer */
#define EADC_TIMER1_TRIGGER (5UL<<EADC_SCTL_TRGSEL_Pos) /*!< Timer1 overflow pulse trigger \hideinitializer */
#define EADC_TIMER2_TRIGGER (6UL<<EADC_SCTL_TRGSEL_Pos) /*!< Timer2 overflow pulse trigger \hideinitializer */
#define EADC_TIMER3_TRIGGER (7UL<<EADC_SCTL_TRGSEL_Pos) /*!< Timer3 overflow pulse trigger \hideinitializer */
#define EADC_TIMER4_TRIGGER (8UL<<EADC_SCTL_TRGSEL_Pos) /*!< Timer4 overflow pulse trigger \hideinitializer */
#define EADC_TIMER5_TRIGGER (9UL<<EADC_SCTL_TRGSEL_Pos) /*!< Timer5 overflow pulse trigger \hideinitializer */
#define EADC_TIMER6_TRIGGER (0xAUL<<EADC_SCTL_TRGSEL_Pos) /*!< Timer6 overflow pulse trigger \hideinitializer */
#define EADC_TIMER7_TRIGGER (0xBUL<<EADC_SCTL_TRGSEL_Pos) /*!< Timer7 overflow pulse trigger \hideinitializer */
#define EADC_TIMER8_TRIGGER (0xCUL<<EADC_SCTL_TRGSEL_Pos) /*!< Timer8 overflow pulse trigger \hideinitializer */
#define EADC_TIMER9_TRIGGER (0xDUL<<EADC_SCTL_TRGSEL_Pos) /*!< Timer9 overflow pulse trigger \hideinitializer */
#define EADC_TIMER10_TRIGGER (0xEUL<<EADC_SCTL_TRGSEL_Pos) /*!< Timer10 overflow pulse trigger \hideinitializer */
#define EADC_TIMER11_TRIGGER (0xFUL<<EADC_SCTL_TRGSEL_Pos) /*!< Timer11 overflow pulse trigger \hideinitializer */
#define EADC_EPWM0TG0_TRIGGER (0x10UL<<EADC_SCTL_TRGSEL_Pos) /*!< EPWM0TG0 trigger \hideinitializer */
#define EADC_EPWM0TG1_TRIGGER (0x11UL<<EADC_SCTL_TRGSEL_Pos) /*!< EPWM0TG1 trigger \hideinitializer */
#define EADC_EPWM0TG2_TRIGGER (0x12UL<<EADC_SCTL_TRGSEL_Pos) /*!< EPWM0TG2 trigger \hideinitializer */
#define EADC_EPWM0TG3_TRIGGER (0x13UL<<EADC_SCTL_TRGSEL_Pos) /*!< EPWM0TG3 trigger \hideinitializer */
#define EADC_EPWM0TG4_TRIGGER (0x14UL<<EADC_SCTL_TRGSEL_Pos) /*!< EPWM0TG4 trigger \hideinitializer */
#define EADC_EPWM0TG5_TRIGGER (0x15UL<<EADC_SCTL_TRGSEL_Pos) /*!< EPWM0TG5 trigger \hideinitializer */
#define EADC_EPWM1TG0_TRIGGER (0x16UL<<EADC_SCTL_TRGSEL_Pos) /*!< EPWM1TG0 trigger \hideinitializer */
#define EADC_EPWM1TG1_TRIGGER (0x17UL<<EADC_SCTL_TRGSEL_Pos) /*!< EPWM1TG1 trigger \hideinitializer */
#define EADC_EPWM1TG2_TRIGGER (0x18UL<<EADC_SCTL_TRGSEL_Pos) /*!< EPWM1TG2 trigger \hideinitializer */
#define EADC_EPWM1TG3_TRIGGER (0x19UL<<EADC_SCTL_TRGSEL_Pos) /*!< EPWM1TG3 trigger \hideinitializer */
#define EADC_EPWM1TG4_TRIGGER (0x1AUL<<EADC_SCTL_TRGSEL_Pos) /*!< EPWM1TG4 trigger \hideinitializer */
#define EADC_EPWM1TG5_TRIGGER (0x1BUL<<EADC_SCTL_TRGSEL_Pos) /*!< EPWM1TG5 trigger \hideinitializer */
#define EADC_EPWM2TG0_TRIGGER (0x1CUL<<EADC_SCTL_TRGSEL_Pos) /*!< EPWM2TG0 trigger \hideinitializer */
#define EADC_EPWM2TG1_TRIGGER (0x1DUL<<EADC_SCTL_TRGSEL_Pos) /*!< EPWM2TG1 trigger \hideinitializer */
#define EADC_EPWM2TG2_TRIGGER (0x1EUL<<EADC_SCTL_TRGSEL_Pos) /*!< EPWM2TG2 trigger \hideinitializer */
#define EADC_EPWM2TG3_TRIGGER (0x1FUL<<EADC_SCTL_TRGSEL_Pos) /*!< EPWM2TG3 trigger \hideinitializer */
#define EADC_EPWM2TG4_TRIGGER (0x20UL<<EADC_SCTL_TRGSEL_Pos) /*!< EPWM2TG4 trigger \hideinitializer */
#define EADC_EPWM2TG5_TRIGGER (0x21UL<<EADC_SCTL_TRGSEL_Pos) /*!< EPWM2TG5 trigger \hideinitializer */
#define EADC_SCTL_TRGDLYDIV_DIVIDER_1 (0<<EADC_SCTL_TRGDLYDIV_Pos) /*!< Trigger delay clock frequency is ADC_CLK/1 \hideinitializer */
#define EADC_SCTL_TRGDLYDIV_DIVIDER_2 (0x1UL<<EADC_SCTL_TRGDLYDIV_Pos) /*!< Trigger delay clock frequency is ADC_CLK/2 \hideinitializer */
#define EADC_SCTL_TRGDLYDIV_DIVIDER_4 (0x2UL<<EADC_SCTL_TRGDLYDIV_Pos) /*!< Trigger delay clock frequency is ADC_CLK/4 \hideinitializer */
#define EADC_SCTL_TRGDLYDIV_DIVIDER_16 (0x3UL<<EADC_SCTL_TRGDLYDIV_Pos) /*!< Trigger delay clock frequency is ADC_CLK/16 \hideinitializer */
/*---------------------------------------------------------------------------------------------------------*/
/* EADC_CMP Constant Definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define EADC_CMP_CMPCOND_LESS_THAN (0UL<<EADC_CMP_CMPCOND_Pos) /*!< The compare condition is "less than" \hideinitializer */
#define EADC_CMP_CMPCOND_GREATER_OR_EQUAL (1UL<<EADC_CMP_CMPCOND_Pos) /*!< The compare condition is "greater than or equal to" \hideinitializer */
#define EADC_CMP_CMPWEN_ENABLE (EADC_CMP_CMPWEN_Msk) /*!< Compare window mode enable \hideinitializer */
#define EADC_CMP_CMPWEN_DISABLE (~EADC_CMP_CMPWEN_Msk) /*!< Compare window mode disable \hideinitializer */
#define EADC_CMP_ADCMPIE_ENABLE (EADC_CMP_ADCMPIE_Msk) /*!< A/D result compare interrupt enable \hideinitializer */
#define EADC_CMP_ADCMPIE_DISABLE (~EADC_CMP_ADCMPIE_Msk) /*!< A/D result compare interrupt disable \hideinitializer */
/*@}*/ /* end of group EADC_EXPORTED_CONSTANTS */
/** @addtogroup EADC_EXPORTED_FUNCTIONS EADC Exported Functions
@{
*/
/*---------------------------------------------------------------------------------------------------------*/
/* EADC Macro Definitions */
/*---------------------------------------------------------------------------------------------------------*/
/**
* @brief A/D Converter Control Circuits Reset.
* @param[in] eadc The pointer of the specified EADC module.
* @return None
* @details ADCRST bit (EADC_CT[1]) remains 1 during ADC reset, when ADC reset end, the ADCRST bit is automatically cleared to 0.
* \hideinitializer
*/
#define EADC_CONV_RESET(eadc) ((eadc)->CTL |= EADC_CTL_ADCRST_Msk)
/**
* @brief Enable PDMA transfer.
* @param[in] eadc The pointer of the specified EADC module.
* @return None
* @details When A/D conversion is completed, the converted data is loaded into EADC_DATn (n: 0 ~ 18) register,
* user can enable this bit to generate a PDMA data transfer request.
* @note When set PDMAEN bit (EADC_CTL[11]), user must set ADINTENn (EADC_CTL[5:2], n=0~3) = 0 to disable interrupt.
* \hideinitializer
*/
#define EADC_ENABLE_PDMA(eadc) ((eadc)->CTL |= EADC_CTL_PDMAEN_Msk)
/**
* @brief Disable PDMA transfer.
* @param[in] eadc The pointer of the specified EADC module.
* @return None
* @details This macro is used to disable PDMA transfer.
* \hideinitializer
*/
#define EADC_DISABLE_PDMA(eadc) ((eadc)->CTL &= (~EADC_CTL_PDMAEN_Msk))
/**
* @brief Enable Sample Module PDMA transfer.
* @param[in] eadc The pointer of the specified EADC module.
* @param[in] u32ModuleMask the combination of sample module interrupt status bits. Each bit corresponds to a sample module interrupt status.
* This parameter decides which sample module interrupts will be disabled, valid range are between 1~0x7FFFF.
* @return None
* @details When A/D conversion is completed, the converted data is loaded into EADC_DATn (n: 0 ~ 18) register,
* user can enable this bit to generate a PDMA data transfer request.
* \hideinitializer
*/
#define EADC_ENABLE_SAMPLE_MODULE_PDMA(eadc, u32ModuleMask) ((eadc)->PDMACTL |= u32ModuleMask)
/**
* @brief Disable Sample Module PDMA transfer.
* @param[in] eadc The pointer of the specified EADC module.
* @param[in] u32ModuleMask the combination of sample module interrupt status bits. Each bit corresponds to a sample module interrupt status.
* This parameter decides which sample module interrupts will be disabled, valid range are between 1~0x7FFFF.
* @return None
* @details This macro is used to disable sample module PDMA transfer.
* \hideinitializer
*/
#define EADC_DISABLE_SAMPLE_MODULE_PDMA(eadc, u32ModuleMask) ((eadc)->PDMACTL &= (~u32ModuleMask))
/**
* @brief Enable double buffer mode.
* @param[in] eadc The pointer of the specified EADC module.
* @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 3.
* @return None
* @details The ADC controller supports a double buffer mode in sample module 0~3.
* If user enable DBMEN (EADC_SCTLn[23], n=0~3), the double buffer mode will enable.
* \hideinitializer
*/
#define EADC_ENABLE_DOUBLE_BUFFER(eadc, u32ModuleNum) ((eadc)->SCTL[(u32ModuleNum)] |= EADC_SCTL_DBMEN_Msk)
/**
* @brief Disable double buffer mode.
* @param[in] eadc The pointer of the specified EADC module.
* @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 3.
* @return None
* @details Sample has one sample result register.
* \hideinitializer
*/
#define EADC_DISABLE_DOUBLE_BUFFER(eadc, u32ModuleNum) ((eadc)->SCTL[(u32ModuleNum)] &= ~EADC_SCTL_DBMEN_Msk)
/**
* @brief Set ADIFn at A/D end of conversion.
* @param[in] eadc The pointer of the specified EADC module.
* @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 15.
* @return None
* @details The A/D converter generates ADIFn (EADC_STATUS2[3:0], n=0~3) at the start of conversion.
* \hideinitializer
*/
#define EADC_ENABLE_INT_POSITION(eadc, u32ModuleNum) ((eadc)->SCTL[(u32ModuleNum)] |= EADC_SCTL_INTPOS_Msk)
/**
* @brief Set ADIFn at A/D start of conversion.
* @param[in] eadc The pointer of the specified EADC module.
* @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 15.
* @return None
* @details The A/D converter generates ADIFn (EADC_STATUS2[3:0], n=0~3) at the end of conversion.
* \hideinitializer
*/
#define EADC_DISABLE_INT_POSITION(eadc, u32ModuleNum) ((eadc)->SCTL[(u32ModuleNum)] &= ~EADC_SCTL_INTPOS_Msk)
/**
* @brief Enable the interrupt.
* @param[in] eadc The pointer of the specified EADC module.
* @param[in] u32Mask Decides the combination of interrupt status bits. Each bit corresponds to a interrupt status.
* This parameter decides which interrupts will be enabled. Bit 0 is ADCIEN0, bit 1 is ADCIEN1..., bit 3 is ADCIEN3.
* @return None
* @details The A/D converter generates a conversion end ADIFn (EADC_STATUS2[n]) upon the end of specific sample module A/D conversion.
* If ADCIENn bit (EADC_CTL[n+2]) is set then conversion end interrupt request ADINTn is generated (n=0~3).
* \hideinitializer
*/
#define EADC_ENABLE_INT(eadc, u32Mask) ((eadc)->CTL |= ((u32Mask) << EADC_CTL_ADCIEN0_Pos))
/**
* @brief Disable the interrupt.
* @param[in] eadc The pointer of the specified EADC module.
* @param[in] u32Mask Decides the combination of interrupt status bits. Each bit corresponds to a interrupt status.
* This parameter decides which interrupts will be disabled. Bit 0 is ADCIEN0, bit 1 is ADCIEN1..., bit 3 is ADCIEN3.
* @return None
* @details Specific sample module A/D ADINT0 interrupt function Disabled.
* \hideinitializer
*/
#define EADC_DISABLE_INT(eadc, u32Mask) ((eadc)->CTL &= ~((u32Mask) << EADC_CTL_ADCIEN0_Pos))
/**
* @brief Enable the sample module interrupt.
* @param[in] eadc The pointer of the specified EADC module.
* @param[in] u32IntSel Decides which interrupt source will be used, valid value are from 0 to 3.
* @param[in] u32ModuleMask the combination of sample module interrupt status bits. Each bit corresponds to a sample module interrupt status.
* This parameter decides which sample module interrupts will be enabled, valid range are between 1~0x7FFFF.
* @return None
* @details There are 4 ADC interrupts ADINT0~3, and each of these interrupts has its own interrupt vector address.
* \hideinitializer
*/
#define EADC_ENABLE_SAMPLE_MODULE_INT(eadc, u32IntSel, u32ModuleMask) ((eadc)->INTSRC[(u32IntSel)] |= (u32ModuleMask))
/**
* @brief Disable the sample module interrupt.
* @param[in] eadc The pointer of the specified EADC module.
* @param[in] u32IntSel Decides which interrupt source will be used, valid value are from 0 to 3.
* @param[in] u32ModuleMask the combination of sample module interrupt status bits. Each bit corresponds to a sample module interrupt status.
* This parameter decides which sample module interrupts will be disabled, valid range are between 1~0x7FFFF.
* @return None
* @details There are 4 ADC interrupts ADINT0~3, and each of these interrupts has its own interrupt vector address.
* \hideinitializer
*/
#define EADC_DISABLE_SAMPLE_MODULE_INT(eadc, u32IntSel, u32ModuleMask) ((eadc)->INTSRC[(u32IntSel)] &= ~(u32ModuleMask))
/**
* @brief Set the input mode output format.
* @param[in] eadc The pointer of the specified EADC module.
* @param[in] u32Format Decides the output format. Valid values are:
* - EADC_CTL_DMOF_STRAIGHT_BINARY :Select the straight binary format as the output format of the conversion result.
* - EADC_CTL_DMOF_TWOS_COMPLEMENT :Select the 2's complement format as the output format of the conversion result.
* @return None
* @details The macro is used to set A/D input mode output format.
* \hideinitializer
*/
#define EADC_SET_DMOF(eadc, u32Format) ((eadc)->CTL = ((eadc)->CTL & ~EADC_CTL_DMOF_Msk) | (u32Format))
/**
* @brief Start the A/D conversion.
* @param[in] eadc The pointer of the specified EADC module.
* @param[in] u32ModuleMask The combination of sample module. Each bit corresponds to a sample module.
* This parameter decides which sample module will be conversion, valid range are between 1~0x7FFFF.
* Bit 0 is sample module 0, bit 1 is sample module 1..., bit 18 is sample module 18.
* @return None
* @details After write EADC_SWTRG register to start ADC conversion, the EADC_PENDSTS register will show which SAMPLE will conversion.
* \hideinitializer
*/
#define EADC_START_CONV(eadc, u32ModuleMask) ((eadc)->SWTRG = (u32ModuleMask))
/**
* @brief Cancel the conversion for sample module.
* @param[in] eadc The pointer of the specified EADC module.
* @param[in] u32ModuleMask The combination of sample module. Each bit corresponds to a sample module.
* This parameter decides which sample module will stop the conversion, valid range are between 1~0x7FFFF.
* Bit 0 is sample module 0, bit 1 is sample module 1..., bit 18 is sample module18.
* @return None
* @details If user want to disable the conversion of the sample module, user can write EADC_PENDSTS register to clear it.
* \hideinitializer
*/
#define EADC_STOP_CONV(eadc, u32ModuleMask) ((eadc)->PENDSTS = (u32ModuleMask))
/**
* @brief Get the conversion pending flag.
* @param[in] eadc The pointer of the specified EADC module.
* @return Return the conversion pending sample module.
* @details This STPFn(EADC_PENDSTS[18:0]) bit remains 1 during pending state, when the respective ADC conversion is end,
* the STPFn (n=0~18) bit is automatically cleared to 0.
* \hideinitializer
*/
#define EADC_GET_PENDING_CONV(eadc) ((eadc)->PENDSTS)
/**
* @brief Get the conversion data of the user-specified sample module.
* @param[in] eadc The pointer of the specified EADC module.
* @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 18.
* @return Return the conversion data of the user-specified sample module.
* @details This macro is used to read RESULT bit (EADC_DATn[15:0], n=0~18) field to get conversion data.
* \hideinitializer
*/
#define EADC_GET_CONV_DATA(eadc, u32ModuleNum) ((eadc)->DAT[(u32ModuleNum)] & EADC_DAT_RESULT_Msk)
/**
* @brief Get the data overrun flag of the user-specified sample module.
* @param[in] eadc The pointer of the specified EADC module.
* @param[in] u32ModuleMask The combination of data overrun status bits. Each bit corresponds to a data overrun status, valid range are between 1~0x7FFFF.
* @return Return the data overrun flag of the user-specified sample module.
* @details This macro is used to read OV bit (EADC_STATUS0[31:16], EADC_STATUS1[18:16]) field to get data overrun status.
* \hideinitializer
*/
#define EADC_GET_DATA_OVERRUN_FLAG(eadc, u32ModuleMask) ((((eadc)->STATUS0 >> EADC_STATUS0_OV_Pos) | ((eadc)->STATUS1 & EADC_STATUS1_OV_Msk)) & (u32ModuleMask))
/**
* @brief Get the data valid flag of the user-specified sample module.
* @param[in] eadc The pointer of the specified EADC module.
* @param[in] u32ModuleMask The combination of data valid status bits. Each bit corresponds to a data valid status, valid range are between 1~0x7FFFF.
* @return Return the data valid flag of the user-specified sample module.
* @details This macro is used to read VALID bit (EADC_STATUS0[15:0], EADC_STATUS1[2:0]) field to get data valid status.
* \hideinitializer
*/
#define EADC_GET_DATA_VALID_FLAG(eadc, u32ModuleMask) ((((eadc)->STATUS0 & EADC_STATUS0_VALID_Msk) | (((eadc)->STATUS1 & EADC_STATUS1_VALID_Msk) << 16)) & (u32ModuleMask))
/**
* @brief Get the double data of the user-specified sample module.
* @param[in] eadc The pointer of the specified EADC module.
* @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 18.
* @return Return the double data of the user-specified sample module.
* @details This macro is used to read RESULT bit (EADC_DDATn[15:0], n=0~3) field to get conversion data.
* \hideinitializer
*/
#define EADC_GET_DOUBLE_DATA(eadc, u32ModuleNum) ((eadc)->DDAT[(u32ModuleNum)] & EADC_DDAT0_RESULT_Msk)
/**
* @brief Get the user-specified interrupt flags.
* @param[in] eadc The pointer of the specified EADC module.
* @param[in] u32Mask The combination of interrupt status bits. Each bit corresponds to a interrupt status.
* Bit 0 is ADIF0, bit 1 is ADIF1..., bit 3 is ADIF3.
* Bit 4 is ADCMPF0, bit 5 is ADCMPF1..., bit 7 is ADCMPF3.
* @return Return the user-specified interrupt flags.
* @details This macro is used to get the user-specified interrupt flags.
* \hideinitializer
*/
#define EADC_GET_INT_FLAG(eadc, u32Mask) ((eadc)->STATUS2 & (u32Mask))
/**
* @brief Get the user-specified sample module overrun flags.
* @param[in] eadc The pointer of the specified EADC module.
* @param[in] u32ModuleMask The combination of sample module overrun status bits. Each bit corresponds to a sample module overrun status, valid range are between 1~0x7FFFF.
* @return Return the user-specified sample module overrun flags.
* @details This macro is used to get the user-specified sample module overrun flags.
* \hideinitializer
*/
#define EADC_GET_SAMPLE_MODULE_OV_FLAG(eadc, u32ModuleMask) ((eadc)->OVSTS & (u32ModuleMask))
/**
* @brief Clear the selected interrupt status bits.
* @param[in] eadc The pointer of the specified EADC module.
* @param[in] u32Mask The combination of compare interrupt status bits. Each bit corresponds to a compare interrupt status.
* Bit 0 is ADIF0, bit 1 is ADIF1..., bit 3 is ADIF3.
* Bit 4 is ADCMPF0, bit 5 is ADCMPF1..., bit 7 is ADCMPF3.
* @return None
* @details This macro is used to clear clear the selected interrupt status bits.
* \hideinitializer
*/
#define EADC_CLR_INT_FLAG(eadc, u32Mask) ((eadc)->STATUS2 = (u32Mask))
/**
* @brief Clear the selected sample module overrun status bits.
* @param[in] eadc The pointer of the specified EADC module.
* @param[in] u32ModuleMask The combination of sample module overrun status bits. Each bit corresponds to a sample module overrun status.
* Bit 0 is SPOVF0, bit 1 is SPOVF1..., bit 18 is SPOVF18.
* @return None
* @details This macro is used to clear the selected sample module overrun status bits.
* \hideinitializer
*/
#define EADC_CLR_SAMPLE_MODULE_OV_FLAG(eadc, u32ModuleMask) ((eadc)->OVSTS = (u32ModuleMask))
/**
* @brief Check all sample module A/D result data register overrun flags.
* @param[in] eadc The pointer of the specified EADC module.
* @retval 0 None of sample module data register overrun flag is set to 1.
* @retval 1 Any one of sample module data register overrun flag is set to 1.
* @details The AOV bit (EADC_STATUS2[27]) will keep 1 when any one of sample module data register overrun flag OVn (EADC_DATn[16]) is set to 1.
* \hideinitializer
*/
#define EADC_IS_DATA_OV(eadc) (((eadc)->STATUS2 & EADC_STATUS2_AOV_Msk) >> EADC_STATUS2_AOV_Pos)
/**
* @brief Check all sample module A/D result data register valid flags.
* @param[in] eadc The pointer of the specified EADC module.
* @retval 0 None of sample module data register valid flag is set to 1.
* @retval 1 Any one of sample module data register valid flag is set to 1.
* @details The AVALID bit (EADC_STATUS2[26]) will keep 1 when any one of sample module data register valid flag VALIDn (EADC_DATn[17]) is set to 1.
* \hideinitializer
*/
#define EADC_IS_DATA_VALID(eadc) (((eadc)->STATUS2 & EADC_STATUS2_AVALID_Msk) >> EADC_STATUS2_AVALID_Pos)
/**
* @brief Check all A/D sample module start of conversion overrun flags.
* @param[in] eadc The pointer of the specified EADC module.
* @retval 0 None of sample module event overrun flag is set to 1.
* @retval 1 Any one of sample module event overrun flag is set to 1.
* @details The STOVF bit (EADC_STATUS2[25]) will keep 1 when any one of sample module event overrun flag SPOVFn (EADC_OVSTS[n]) is set to 1.
* \hideinitializer
*/
#define EADC_IS_SAMPLE_MODULE_OV(eadc) (((eadc)->STATUS2 & EADC_STATUS2_STOVF_Msk) >> EADC_STATUS2_STOVF_Pos)
/**
* @brief Check all A/D interrupt flag overrun bits.
* @param[in] eadc The pointer of the specified EADC module.
* @retval 0 None of ADINT interrupt flag is overwritten to 1.
* @retval 1 Any one of ADINT interrupt flag is overwritten to 1.
* @details The ADOVIF bit (EADC_STATUS2[24]) will keep 1 when any one of ADINT interrupt flag ADOVIFn (EADC_STATUS2[11:8]) is overwritten to 1.
* \hideinitializer
*/
#define EADC_IS_INT_FLAG_OV(eadc) (((eadc)->STATUS2 & EADC_STATUS2_ADOVIF_Msk) >> EADC_STATUS2_ADOVIF_Pos)
/**
* @brief Get the busy state of EADC.
* @param[in] eadc The pointer of the specified EADC module.
* @retval 0 Idle state.
* @retval 1 Busy state.
* @details This macro is used to read BUSY bit (EADC_STATUS2[23]) to get busy state.
* \hideinitializer
*/
#define EADC_IS_BUSY(eadc) (((eadc)->STATUS2 & EADC_STATUS2_BUSY_Msk) >> EADC_STATUS2_BUSY_Pos)
/**
* @brief Configure the comparator 0 and enable it.
* @param[in] eadc The pointer of the specified EADC module.
* @param[in] u32ModuleNum specifies the compare sample module, valid value are from 0 to 18.
* @param[in] u32Condition specifies the compare condition. Valid values are:
* - \ref EADC_CMP_CMPCOND_LESS_THAN :The compare condition is "less than the compare value"
* - \ref EADC_CMP_CMPCOND_GREATER_OR_EQUAL :The compare condition is "greater than or equal to the compare value
* @param[in] u16CMPData specifies the compare value, valid range are between 0~0xFFF.
* @param[in] u32MatchCount specifies the match count setting, valid range are between 0~0xF.
* @return None
* @details For example, ADC_ENABLE_CMP0(EADC, 5, ADC_ADCMPR_CMPCOND_GREATER_OR_EQUAL, 0x800, 10, EADC_CMP_CMPWEN_DISABLE, EADC_CMP_ADCMPIE_ENABLE);
* Means EADC will assert comparator 0 flag if sample module 5 conversion result is greater or
* equal to 0x800 for 10 times continuously, and a compare interrupt request is generated.
* \hideinitializer
*/
#define EADC_ENABLE_CMP0(eadc,\
u32ModuleNum,\
u32Condition,\
u16CMPData,\
u32MatchCount) ((eadc)->CMP[0] = (((eadc)->CMP[0] & ~(EADC_CMP_CMPSPL_Msk|EADC_CMP_CMPCOND_Msk|EADC_CMP_CMPDAT_Msk|EADC_CMP_CMPMCNT_Msk))|\
(((u32ModuleNum) << EADC_CMP_CMPSPL_Pos)|\
(u32Condition) |\
((u16CMPData) << EADC_CMP_CMPDAT_Pos)| \
(((u32MatchCount) - 1) << EADC_CMP_CMPMCNT_Pos)|\
EADC_CMP_ADCMPEN_Msk)))
/**
* @brief Configure the comparator 1 and enable it.
* @param[in] eadc The pointer of the specified EADC module.
* @param[in] u32ModuleNum specifies the compare sample module, valid value are from 0 to 18.
* @param[in] u32Condition specifies the compare condition. Valid values are:
* - \ref EADC_CMP_CMPCOND_LESS_THAN :The compare condition is "less than the compare value"
* - \ref EADC_CMP_CMPCOND_GREATER_OR_EQUAL :The compare condition is "greater than or equal to the compare value
* @param[in] u16CMPData specifies the compare value, valid range are between 0~0xFFF.
* @param[in] u32MatchCount specifies the match count setting, valid range are between 0~0xF.
* @return None
* @details For example, ADC_ENABLE_CMP1(EADC, 5, ADC_ADCMPR_CMPCOND_GREATER_OR_EQUAL, 0x800, 10, EADC_CMP_ADCMPIE_ENABLE);
* Means EADC will assert comparator 1 flag if sample module 5 conversion result is greater or
* equal to 0x800 for 10 times continuously, and a compare interrupt request is generated.
* \hideinitializer
*/
#define EADC_ENABLE_CMP1(eadc,\
u32ModuleNum,\
u32Condition,\
u16CMPData,\
u32MatchCount) ((eadc)->CMP[1] = (((eadc)->CMP[1] & ~(EADC_CMP_CMPSPL_Msk|EADC_CMP_CMPCOND_Msk|EADC_CMP_CMPDAT_Msk|EADC_CMP_CMPMCNT_Msk))|\
(((u32ModuleNum) << EADC_CMP_CMPSPL_Pos)|\
(u32Condition) |\
((u16CMPData) << EADC_CMP_CMPDAT_Pos)| \
(((u32MatchCount) - 1) << EADC_CMP_CMPMCNT_Pos)|\
EADC_CMP_ADCMPEN_Msk)))
/**
* @brief Configure the comparator 2 and enable it.
* @param[in] eadc The pointer of the specified EADC module.
* @param[in] u32ModuleNum specifies the compare sample module, valid value are from 0 to 18.
* @param[in] u32Condition specifies the compare condition. Valid values are:
* - \ref EADC_CMP_CMPCOND_LESS_THAN :The compare condition is "less than the compare value"
* - \ref EADC_CMP_CMPCOND_GREATER_OR_EQUAL :The compare condition is "greater than or equal to the compare value
* @param[in] u16CMPData specifies the compare value, valid range are between 0~0xFFF.
* @param[in] u32MatchCount specifies the match count setting, valid range are between 0~0xF.
* @return None
* @details For example, ADC_ENABLE_CMP2(EADC, 5, ADC_ADCMPR_CMPCOND_GREATER_OR_EQUAL, 0x800, 10, EADC_CMP_CMPWEN_DISABLE, EADC_CMP_ADCMPIE_ENABLE);
* Means EADC will assert comparator 2 flag if sample module 5 conversion result is greater or
* equal to 0x800 for 10 times continuously, and a compare interrupt request is generated.
* \hideinitializer
*/
#define EADC_ENABLE_CMP2(eadc,\
u32ModuleNum,\
u32Condition,\
u16CMPData,\
u32MatchCount) ((eadc)->CMP[2] = (((eadc)->CMP[2] & ~(EADC_CMP_CMPSPL_Msk|EADC_CMP_CMPCOND_Msk|EADC_CMP_CMPDAT_Msk|EADC_CMP_CMPMCNT_Msk))|\
(((u32ModuleNum) << EADC_CMP_CMPSPL_Pos)|\
(u32Condition) |\
((u16CMPData) << EADC_CMP_CMPDAT_Pos)| \
(((u32MatchCount) - 1) << EADC_CMP_CMPMCNT_Pos)|\
EADC_CMP_ADCMPEN_Msk)))
/**
* @brief Configure the comparator 3 and enable it.
* @param[in] eadc The pointer of the specified EADC module.
* @param[in] u32ModuleNum specifies the compare sample module, valid value are from 0 to 18.
* @param[in] u32Condition specifies the compare condition. Valid values are:
* - \ref EADC_CMP_CMPCOND_LESS_THAN :The compare condition is "less than the compare value"
* - \ref EADC_CMP_CMPCOND_GREATER_OR_EQUAL :The compare condition is "greater than or equal to the compare value
* @param[in] u16CMPData specifies the compare value, valid range are between 0~0xFFF.
* @param[in] u32MatchCount specifies the match count setting, valid range are between 1~0xF.
* @return None
* @details For example, ADC_ENABLE_CMP3(EADC, 5, ADC_ADCMPR_CMPCOND_GREATER_OR_EQUAL, 0x800, 10, EADC_CMP_ADCMPIE_ENABLE);
* Means EADC will assert comparator 3 flag if sample module 5 conversion result is greater or
* equal to 0x800 for 10 times continuously, and a compare interrupt request is generated.
* \hideinitializer
*/
#define EADC_ENABLE_CMP3(eadc,\
u32ModuleNum,\
u32Condition,\
u16CMPData,\
u32MatchCount) ((eadc)->CMP[3] = (((eadc)->CMP[3] & ~(EADC_CMP_CMPSPL_Msk|EADC_CMP_CMPCOND_Msk|EADC_CMP_CMPDAT_Msk|EADC_CMP_CMPMCNT_Msk))|\
(((u32ModuleNum) << EADC_CMP_CMPSPL_Pos)|\
(u32Condition) |\
((u16CMPData) << EADC_CMP_CMPDAT_Pos)| \
(((u32MatchCount) - 1) << EADC_CMP_CMPMCNT_Pos)|\
EADC_CMP_ADCMPEN_Msk)))
/**
* @brief Enable the compare window mode.
* @param[in] eadc The pointer of the specified EADC module.
* @param[in] u32CMP Specifies the compare register, valid value are 0 and 2.
* @return None
* @details ADCMPF0 (EADC_STATUS2[4]) will be set when both EADC_CMP0 and EADC_CMP1 compared condition matched.
* \hideinitializer
*/
#define EADC_ENABLE_CMP_WINDOW_MODE(eadc, u32CMP) ((eadc)->CMP[(u32CMP)] |= EADC_CMP_CMPWEN_Msk)
/**
* @brief Disable the compare window mode.
* @param[in] eadc The pointer of the specified EADC module.
* @param[in] u32CMP Specifies the compare register, valid value are 0 and 2.
* @return None
* @details ADCMPF2 (EADC_STATUS2[6]) will be set when both EADC_CMP2 and EADC_CMP3 compared condition matched.
* \hideinitializer
*/
#define EADC_DISABLE_CMP_WINDOW_MODE(eadc, u32CMP) ((eadc)->CMP[(u32CMP)] &= ~EADC_CMP_CMPWEN_Msk)
/**
* @brief Enable the compare interrupt.
* @param[in] eadc The pointer of the specified EADC module.
* @param[in] u32CMP Specifies the compare register, valid value are from 0 to 3.
* @return None
* @details If the compare function is enabled and the compare condition matches the setting of CMPCOND (EADC_CMPn[2], n=0~3)
* and CMPMCNT (EADC_CMPn[11:8], n=0~3), ADCMPFn (EADC_STATUS2[7:4], n=0~3) will be asserted, in the meanwhile,
* if ADCMPIE is set to 1, a compare interrupt request is generated.
* \hideinitializer
*/
#define EADC_ENABLE_CMP_INT(eadc, u32CMP) ((eadc)->CMP[(u32CMP)] |= EADC_CMP_ADCMPIE_Msk)
/**
* @brief Disable the compare interrupt.
* @param[in] eadc The pointer of the specified EADC module.
* @param[in] u32CMP Specifies the compare register, valid value are from 0 to 3.
* @return None
* @details This macro is used to disable the compare interrupt.
* \hideinitializer
*/
#define EADC_DISABLE_CMP_INT(eadc, u32CMP) ((eadc)->CMP[(u32CMP)] &= ~EADC_CMP_ADCMPIE_Msk)
/**
* @brief Disable comparator 0.
* @param[in] eadc The pointer of the specified EADC module.
* @return None
* @details This macro is used to disable comparator 0.
* \hideinitializer
*/
#define EADC_DISABLE_CMP0(eadc) ((eadc)->CMP[0] = 0)
/**
* @brief Disable comparator 1.
* @param[in] eadc The pointer of the specified EADC module.
* @return None
* @details This macro is used to disable comparator 1.
* \hideinitializer
*/
#define EADC_DISABLE_CMP1(eadc) ((eadc)->CMP[1] = 0)
/**
* @brief Disable comparator 2.
* @param[in] eadc The pointer of the specified EADC module.
* @return None
* @details This macro is used to disable comparator 2.
* \hideinitializer
*/
#define EADC_DISABLE_CMP2(eadc) ((eadc)->CMP[2] = 0)
/**
* @brief Disable comparator 3.
* @param[in] eadc The pointer of the specified EADC module.
* @return None
* @details This macro is used to disable comparator 3.
* \hideinitializer
*/
#define EADC_DISABLE_CMP3(eadc) ((eadc)->CMP[3] = 0)
/*---------------------------------------------------------------------------------------------------------*/
/* Define EADC functions prototype */
/*---------------------------------------------------------------------------------------------------------*/
void EADC_Open(EADC_T *eadc, uint32_t u32InputMode);
void EADC_Close(EADC_T *eadc);
void EADC_ConfigSampleModule(EADC_T *eadc, uint32_t u32ModuleNum, uint32_t u32TriggerSrc, uint32_t u32Channel);
void EADC_SetTriggerDelayTime(EADC_T *eadc, uint32_t u32ModuleNum, uint32_t u32TriggerDelayTime, uint32_t u32DelayClockDivider);
void EADC_SetExtendSampleTime(EADC_T *eadc, uint32_t u32ModuleNum, uint32_t u32ExtendSampleTime);
/*@}*/ /* end of group EADC_EXPORTED_FUNCTIONS */
/*@}*/ /* end of group EADC_Driver */
/*@}*/ /* end of group Standard_Driver */
#ifdef __cplusplus
}
#endif
#endif /* __NU_EADC_H__ */

350
bsp/nuvoton/libraries/ma35/StdDriver/inc/nu_ebi.h Normal file
View File

@ -0,0 +1,350 @@
/**************************************************************************//**
* @file nu_ebi.h
* @brief External Bus Interface(EBI) driver header file
*
* SPDX-License-Identifier: Apache-2.0
* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __NU_EBI_H__
#define __NU_EBI_H__
#ifdef __cplusplus
extern "C"
{
#endif
/** @addtogroup Standard_Driver Standard Driver
@{
*/
/** @addtogroup EBI_Driver EBI Driver
@{
*/
/** @addtogroup EBI_EXPORTED_CONSTANTS EBI Exported Constants
@{
*/
/*---------------------------------------------------------------------------------------------------------*/
/* Miscellaneous Constant Definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define EBI_BANK0_BASE_ADDR 0x68000000UL /*!< EBI bank0 base address \hideinitializer */
#define EBI_BANK1_BASE_ADDR 0x68100000UL /*!< EBI bank1 base address \hideinitializer */
#define EBI_BANK2_BASE_ADDR 0x68200000UL /*!< EBI bank2 base address \hideinitializer */
#define EBI_MAX_SIZE 0x00100000UL /*!< Maximum EBI size for each bank is 1 MB \hideinitializer */
/*---------------------------------------------------------------------------------------------------------*/
/* Constants for EBI bank number */
/*---------------------------------------------------------------------------------------------------------*/
#define EBI_BANK0 0UL /*!< EBI bank 0 \hideinitializer */
#define EBI_BANK1 1UL /*!< EBI bank 1 \hideinitializer */
#define EBI_BANK2 2UL /*!< EBI bank 2 \hideinitializer */
/*---------------------------------------------------------------------------------------------------------*/
/* Constants for EBI data bus width */
/*---------------------------------------------------------------------------------------------------------*/
#define EBI_BUSWIDTH_8BIT 8UL /*!< EBI bus width is 8-bit \hideinitializer */
#define EBI_BUSWIDTH_16BIT 16UL /*!< EBI bus width is 16-bit \hideinitializer */
/*---------------------------------------------------------------------------------------------------------*/
/* Constants for EBI CS Active Level */
/*---------------------------------------------------------------------------------------------------------*/
#define EBI_CS_ACTIVE_LOW 0UL /*!< EBI CS active level is low \hideinitializer */
#define EBI_CS_ACTIVE_HIGH 1UL /*!< EBI CS active level is high \hideinitializer */
/*---------------------------------------------------------------------------------------------------------*/
/* Constants for EBI MCLK divider and Timing */
/*---------------------------------------------------------------------------------------------------------*/
#define EBI_MCLKDIV_1 0x0UL /*!< EBI output clock(MCLK) is HCLK/1 \hideinitializer */
#define EBI_MCLKDIV_2 0x1UL /*!< EBI output clock(MCLK) is HCLK/2 \hideinitializer */
#define EBI_MCLKDIV_4 0x2UL /*!< EBI output clock(MCLK) is HCLK/4 \hideinitializer */
#define EBI_MCLKDIV_8 0x3UL /*!< EBI output clock(MCLK) is HCLK/8 \hideinitializer */
#define EBI_MCLKDIV_16 0x4UL /*!< EBI output clock(MCLK) is HCLK/16 \hideinitializer */
#define EBI_MCLKDIV_32 0x5UL /*!< EBI output clock(MCLK) is HCLK/32 \hideinitializer */
#define EBI_MCLKDIV_64 0x6UL /*!< EBI output clock(MCLK) is HCLK/64 \hideinitializer */
#define EBI_MCLKDIV_128 0x7UL /*!< EBI output clock(MCLK) is HCLK/128 \hideinitializer */
#define EBI_TIMING_FASTEST 0x0UL /*!< EBI timing is the fastest \hideinitializer */
#define EBI_TIMING_VERYFAST 0x1UL /*!< EBI timing is very fast \hideinitializer */
#define EBI_TIMING_FAST 0x2UL /*!< EBI timing is fast \hideinitializer */
#define EBI_TIMING_NORMAL 0x3UL /*!< EBI timing is normal \hideinitializer */
#define EBI_TIMING_SLOW 0x4UL /*!< EBI timing is slow \hideinitializer */
#define EBI_TIMING_VERYSLOW 0x5UL /*!< EBI timing is very slow \hideinitializer */
#define EBI_TIMING_SLOWEST 0x6UL /*!< EBI timing is the slowest \hideinitializer */
#define EBI_OPMODE_NORMAL 0x0UL /*!< EBI bus operate in normal mode \hideinitializer */
#define EBI_OPMODE_CACCESS (EBI_CTL_CACCESS_Msk) /*!< EBI bus operate in Continuous Data Access mode \hideinitializer */
#define EBI_OPMODE_ADSEPARATE (EBI_CTL_ADSEPEN_Msk) /*!< EBI bus operate in AD Separate mode \hideinitializer */
/*@}*/ /* end of group EBI_EXPORTED_CONSTANTS */
/** @addtogroup EBI_EXPORTED_FUNCTIONS EBI Exported Functions
@{
*/
/**
* @brief Read 8-bit data on EBI bank0
*
* @param[in] u32Addr The data address on EBI bank0.
*
* @return 8-bit Data
*
* @details This macro is used to read 8-bit data from specify address on EBI bank0.
* \hideinitializer
*/
#define EBI0_READ_DATA8(u32Addr) (*((volatile unsigned char *)(EBI_BANK0_BASE_ADDR+(u32Addr))))
/**
* @brief Write 8-bit data to EBI bank0
*
* @param[in] u32Addr The data address on EBI bank0.
* @param[in] u32Data Specify data to be written.
*
* @return None
*
* @details This macro is used to write 8-bit data to specify address on EBI bank0.
* \hideinitializer
*/
#define EBI0_WRITE_DATA8(u32Addr, u32Data) (*((volatile unsigned char *)(EBI_BANK0_BASE_ADDR+(u32Addr))) = (u32Data))
/**
* @brief Read 16-bit data on EBI bank0
*
* @param[in] u32Addr The data address on EBI bank0.
*
* @return 16-bit Data
*
* @details This macro is used to read 16-bit data from specify address on EBI bank0.
* \hideinitializer
*/
#define EBI0_READ_DATA16(u32Addr) (*((volatile unsigned short *)(EBI_BANK0_BASE_ADDR+(u32Addr))))
/**
* @brief Write 16-bit data to EBI bank0
*
* @param[in] u32Addr The data address on EBI bank0.
* @param[in] u32Data Specify data to be written.
*
* @return None
*
* @details This macro is used to write 16-bit data to specify address on EBI bank0.
* \hideinitializer
*/
#define EBI0_WRITE_DATA16(u32Addr, u32Data) (*((volatile unsigned short *)(EBI_BANK0_BASE_ADDR+(u32Addr))) = (u32Data))
/**
* @brief Read 32-bit data on EBI bank0
*
* @param[in] u32Addr The data address on EBI bank0.
*
* @return 32-bit Data
*
* @details This macro is used to read 32-bit data from specify address on EBI bank0.
* \hideinitializer
*/
#define EBI0_READ_DATA32(u32Addr) (*((volatile unsigned int *)(EBI_BANK0_BASE_ADDR+(u32Addr))))
/**
* @brief Write 32-bit data to EBI bank0
*
* @param[in] u32Addr The data address on EBI bank0.
* @param[in] u32Data Specify data to be written.
*
* @return None
*
* @details This macro is used to write 32-bit data to specify address on EBI bank0.
* \hideinitializer
*/
#define EBI0_WRITE_DATA32(u32Addr, u32Data) (*((volatile unsigned int *)(EBI_BANK0_BASE_ADDR+(u32Addr))) = (u32Data))
/**
* @brief Read 8-bit data on EBI bank1
*
* @param[in] u32Addr The data address on EBI bank1.
*
* @return 8-bit Data
*
* @details This macro is used to read 8-bit data from specify address on EBI bank1.
* \hideinitializer
*/
#define EBI1_READ_DATA8(u32Addr) (*((volatile unsigned char *)(EBI_BANK1_BASE_ADDR+(u32Addr))))
/**
* @brief Write 8-bit data to EBI bank1
*
* @param[in] u32Addr The data address on EBI bank1.
* @param[in] u32Data Specify data to be written.
*
* @return None
*
* @details This macro is used to write 8-bit data to specify address on EBI bank1.
* \hideinitializer
*/
#define EBI1_WRITE_DATA8(u32Addr, u32Data) (*((volatile unsigned char *)(EBI_BANK1_BASE_ADDR+(u32Addr))) = (u32Data))
/**
* @brief Read 16-bit data on EBI bank1
*
* @param[in] u32Addr The data address on EBI bank1.
*
* @return 16-bit Data
*
* @details This macro is used to read 16-bit data from specify address on EBI bank1.
* \hideinitializer
*/
#define EBI1_READ_DATA16(u32Addr) (*((volatile unsigned short *)(EBI_BANK1_BASE_ADDR+(u32Addr))))
/**
* @brief Write 16-bit data to EBI bank1
*
* @param[in] u32Addr The data address on EBI bank1.
* @param[in] u32Data Specify data to be written.
*
* @return None
*
* @details This macro is used to write 16-bit data to specify address on EBI bank1.
* \hideinitializer
*/
#define EBI1_WRITE_DATA16(u32Addr, u32Data) (*((volatile unsigned short *)(EBI_BANK1_BASE_ADDR+(u32Addr))) = (u32Data))
/**
* @brief Read 32-bit data on EBI bank1
*
* @param[in] u32Addr The data address on EBI bank1.
*
* @return 32-bit Data
*
* @details This macro is used to read 32-bit data from specify address on EBI bank1.
* \hideinitializer
*/
#define EBI1_READ_DATA32(u32Addr) (*((volatile unsigned int *)(EBI_BANK1_BASE_ADDR+(u32Addr))))
/**
* @brief Write 32-bit data to EBI bank1
*
* @param[in] u32Addr The data address on EBI bank1.
* @param[in] u32Data Specify data to be written.
*
* @return None
*
* @details This macro is used to write 32-bit data to specify address on EBI bank1.
* \hideinitializer
*/
#define EBI1_WRITE_DATA32(u32Addr, u32Data) (*((volatile unsigned int *)(EBI_BANK1_BASE_ADDR+(u32Addr))) = (u32Data))
/**
* @brief Read 8-bit data on EBI bank2
*
* @param[in] u32Addr The data address on EBI bank2.
*
* @return 8-bit Data
*
* @details This macro is used to read 8-bit data from specify address on EBI bank2.
* \hideinitializer
*/
#define EBI2_READ_DATA8(u32Addr) (*((volatile unsigned char *)(EBI_BANK2_BASE_ADDR+(u32Addr))))
/**
* @brief Write 8-bit data to EBI bank2
*
* @param[in] u32Addr The data address on EBI bank2.
* @param[in] u32Data Specify data to be written.
*
* @return None
*
* @details This macro is used to write 8-bit data to specify address on EBI bank2.
* \hideinitializer
*/
#define EBI2_WRITE_DATA8(u32Addr, u32Data) (*((volatile unsigned char *)(EBI_BANK2_BASE_ADDR+(u32Addr))) = (u32Data))
/**
* @brief Read 16-bit data on EBI bank2
*
* @param[in] u32Addr The data address on EBI bank2.
*
* @return 16-bit Data
*
* @details This macro is used to read 16-bit data from specify address on EBI bank2.
* \hideinitializer
*/
#define EBI2_READ_DATA16(u32Addr) (*((volatile unsigned short *)(EBI_BANK2_BASE_ADDR+(u32Addr))))
/**
* @brief Write 16-bit data to EBI bank2
*
* @param[in] u32Addr The data address on EBI bank2.
* @param[in] u32Data Specify data to be written.
*
* @return None
*
* @details This macro is used to write 16-bit data to specify address on EBI bank2.
* \hideinitializer
*/
#define EBI2_WRITE_DATA16(u32Addr, u32Data) (*((volatile unsigned short *)(EBI_BANK2_BASE_ADDR+(u32Addr))) = (u32Data))
/**
* @brief Read 32-bit data on EBI bank2
*
* @param[in] u32Addr The data address on EBI bank2.
*
* @return 32-bit Data
*
* @details This macro is used to read 32-bit data from specify address on EBI bank2.
* \hideinitializer
*/
#define EBI2_READ_DATA32(u32Addr) (*((volatile unsigned int *)(EBI_BANK2_BASE_ADDR+(u32Addr))))
/**
* @brief Write 32-bit data to EBI bank2
*
* @param[in] u32Addr The data address on EBI bank2.
* @param[in] u32Data Specify data to be written.
*
* @return None
*
* @details This macro is used to write 32-bit data to specify address on EBI bank2.
* \hideinitializer
*/
#define EBI2_WRITE_DATA32(u32Addr, u32Data) (*((volatile unsigned int *)(EBI_BANK2_BASE_ADDR+(u32Addr))) = (u32Data))
/**
* @brief Enable EBI Write Buffer
*
* @param None
*
* @return None
*
* @details This macro is used to improve EBI write operation for all EBI banks.
* \hideinitializer
*/
#define EBI_ENABLE_WRITE_BUFFER() (EBI->CTL0 |= EBI_CTL_WBUFEN_Msk);
/**
* @brief Disable EBI Write Buffer
*
* @param None
*
* @return None
*
* @details This macro is used to disable EBI write buffer function.
* \hideinitializer
*/
#define EBI_DISABLE_WRITE_BUFFER() (EBI->CTL0 &= ~EBI_CTL_WBUFEN_Msk);
void EBI_Open(uint32_t u32Bank, uint32_t u32DataWidth, uint32_t u32TimingClass, uint32_t u32BusMode, uint32_t u32CSActiveLevel);
void EBI_Close(uint32_t u32Bank);
void EBI_SetBusTiming(uint32_t u32Bank, uint32_t u32TimingConfig, uint32_t u32MclkDiv);
/*@}*/ /* end of group EBI_EXPORTED_FUNCTIONS */
/*@}*/ /* end of group EBI_Driver */
/*@}*/ /* end of group Standard_Driver */
#ifdef __cplusplus
}
#endif
#endif

453
bsp/nuvoton/libraries/ma35/StdDriver/inc/nu_ecap.h Normal file
View File

@ -0,0 +1,453 @@
/**************************************************************************//**
* @file nu_ecap.h
* @brief EnHanced Input Capture Timer(ECAP) driver header file
*
* SPDX-License-Identifier: Apache-2.0
* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __NU_ECAP_H__
#define __NU_ECAP_H__
#ifdef __cplusplus
extern "C"
{
#endif
/** @addtogroup Standard_Driver Standard Driver
@{
*/
/** @addtogroup ECAP_Driver ECAP Driver
@{
*/
/** @addtogroup ECAP_EXPORTED_CONSTANTS ECAP Exported Constants
@{
*/
#define ECAP_IC0 (0UL) /*!< ECAP IC0 Unit \hideinitializer */
#define ECAP_IC1 (1UL) /*!< ECAP IC1 Unit \hideinitializer */
#define ECAP_IC2 (2UL) /*!< ECAP IC2 Unit \hideinitializer */
/*---------------------------------------------------------------------------------------------------------*/
/* ECAP CTL0 constant definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define ECAP_NOISE_FILTER_CLKDIV_1 (0UL<<ECAP_CTL0_NFCLKSEL_Pos) /*!< Noise filter clock divide by 1 \hideinitializer */
#define ECAP_NOISE_FILTER_CLKDIV_2 (1UL<<ECAP_CTL0_NFCLKSEL_Pos) /*!< Noise filter clock divide by 2 \hideinitializer */
#define ECAP_NOISE_FILTER_CLKDIV_4 (2UL<<ECAP_CTL0_NFCLKSEL_Pos) /*!< Noise filter clock divide by 4 \hideinitializer */
#define ECAP_NOISE_FILTER_CLKDIV_16 (3UL<<ECAP_CTL0_NFCLKSEL_Pos) /*!< Noise filter clock divide by 16 \hideinitializer */
#define ECAP_NOISE_FILTER_CLKDIV_32 (4UL<<ECAP_CTL0_NFCLKSEL_Pos) /*!< Noise filter clock divide by 32 \hideinitializer */
#define ECAP_NOISE_FILTER_CLKDIV_64 (5UL<<ECAP_CTL0_NFCLKSEL_Pos) /*!< Noise filter clock divide by 64 \hideinitializer */
#define ECAP_CAP_INPUT_SRC_FROM_IC (0UL) /*!< CAP input source from IC \hideinitializer */
#define ECAP_CAP_INPUT_SRC_FROM_CH (2UL) /*!< CAP input source from CH of QEI \hideinitializer */
#define ECAP_DISABLE_COMPARE (0UL<<ECAP_CTL0_CMPEN_Pos) /*!< Input capture compare and reload function disable \hideinitializer */
#define ECAP_COMPARE_FUNCTION (1UL<<ECAP_CTL0_CMPEN_Pos) /*!< Input capture compare function \hideinitializer */
/*---------------------------------------------------------------------------------------------------------*/
/* ECAP CTL1 constant definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define ECAP_RISING_EDGE (0UL<<ECAP_CTL1_EDGESEL0_Pos) /*!< ECAP capture rising edge selection \hideinitializer */
#define ECAP_FALLING_EDGE (1UL<<ECAP_CTL1_EDGESEL0_Pos) /*!< ECAP capture falling edge selection \hideinitializer */
#define ECAP_RISING_FALLING_EDGE (2UL<<ECAP_CTL1_EDGESEL0_Pos) /*!< ECAP capture either rising or falling edge selection \hideinitializer */
#define ECAP_CAPTURE_TIMER_CLKDIV_1 (0UL<<ECAP_CTL1_CLKSEL_Pos) /*!< ECAP capture timer clock divide by 1 \hideinitializer */
#define ECAP_CAPTURE_TIMER_CLKDIV_4 (1UL<<ECAP_CTL1_CLKSEL_Pos) /*!< ECAP capture timer clock divide by 4 \hideinitializer */
#define ECAP_CAPTURE_TIMER_CLKDIV_16 (2UL<<ECAP_CTL1_CLKSEL_Pos) /*!< ECAP capture timer clock divide by 16 \hideinitializer */
#define ECAP_CAPTURE_TIMER_CLKDIV_32 (3UL<<ECAP_CTL1_CLKSEL_Pos) /*!< ECAP capture timer clock divide by 32 \hideinitializer */
#define ECAP_CAPTURE_TIMER_CLKDIV_64 (4UL<<ECAP_CTL1_CLKSEL_Pos) /*!< ECAP capture timer clock divide by 64 \hideinitializer */
#define ECAP_CAPTURE_TIMER_CLKDIV_96 (5UL<<ECAP_CTL1_CLKSEL_Pos) /*!< ECAP capture timer clock divide by 96 \hideinitializer */
#define ECAP_CAPTURE_TIMER_CLKDIV_112 (6UL<<ECAP_CTL1_CLKSEL_Pos) /*!< ECAP capture timer clock divide by 112 \hideinitializer */
#define ECAP_CAPTURE_TIMER_CLKDIV_128 (7UL<<ECAP_CTL1_CLKSEL_Pos) /*!< ECAP capture timer clock divide by 128 \hideinitializer */
#define ECAP_CAPTURE_TIMER_CLK_SRC_CAP_CLK (0UL<<ECAP_CTL1_CNTSRCSEL_Pos) /*!< ECAP capture timer/clock source from CAP_CLK \hideinitializer */
#define ECAP_CAPTURE_TIMER_CLK_SRC_CAP0 (1UL<<ECAP_CTL1_CNTSRCSEL_Pos) /*!< ECAP capture timer/clock source from CAP0 \hideinitializer */
#define ECAP_CAPTURE_TIMER_CLK_SRC_CAP1 (2UL<<ECAP_CTL1_CNTSRCSEL_Pos) /*!< ECAP capture timer/clock source from CAP1 \hideinitializer */
#define ECAP_CAPTURE_TIMER_CLK_SRC_CAP2 (3UL<<ECAP_CTL1_CNTSRCSEL_Pos) /*!< ECAP capture timer/clock source from CAP2 \hideinitializer */
/*@}*/ /* end of group ECAP_EXPORTED_CONSTANTS */
/** @addtogroup ECAP_EXPORTED_FUNCTIONS ECAP Exported Functions
@{
*/
/**
* @brief This macro is used to select noise filter clock pre-divide number
* @param[in] ecap Specify ECAP port
* @param[in] u32ClkSel The noise filter clock divide number
* - \ref ECAP_NOISE_FILTER_CLKDIV_1
* - \ref ECAP_NOISE_FILTER_CLKDIV_2
* - \ref ECAP_NOISE_FILTER_CLKDIV_4
* - \ref ECAP_NOISE_FILTER_CLKDIV_16
* - \ref ECAP_NOISE_FILTER_CLKDIV_32
* - \ref ECAP_NOISE_FILTER_CLKDIV_64
* @return None
* @details This macro will set the sampling frequency of the noise filter cock.
* \hideinitializer
*/
#define ECAP_SET_NOISE_FILTER_CLKDIV(ecap, u32ClkSel) ((ecap)->CTL0 = ((ecap)->CTL0 & ~ECAP_CTL0_NFCLKSEL_Msk)|(u32ClkSel))
/**
* @brief This macro is used to disable noise filter
* @param[in] ecap Specify ECAP port
* @return None
* @details This macro will disable the noise filter of input capture.
* \hideinitializer
*/
#define ECAP_NOISE_FILTER_DISABLE(ecap) ((ecap)->CTL0 |= ECAP_CTL0_CAPNFDIS_Msk)
/**
* @brief This macro is used to enable noise filter
* @param[in] ecap Specify ECAP port
* @param[in] u32ClkSel Select noise filter clock divide number
* - \ref ECAP_NOISE_FILTER_CLKDIV_1
* - \ref ECAP_NOISE_FILTER_CLKDIV_2
* - \ref ECAP_NOISE_FILTER_CLKDIV_4
* - \ref ECAP_NOISE_FILTER_CLKDIV_16
* - \ref ECAP_NOISE_FILTER_CLKDIV_32
* - \ref ECAP_NOISE_FILTER_CLKDIV_64
* @return None
* @details This macro will enable the noise filter of input capture and set noise filter clock divide.
* \hideinitializer
*/
#define ECAP_NOISE_FILTER_ENABLE(ecap, u32ClkSel) ((ecap)->CTL0 = ((ecap)->CTL0 & ~(ECAP_CTL0_CAPNFDIS_Msk|ECAP_CTL0_NFCLKSEL_Msk))|(u32ClkSel))
/**
* @brief This macro is used to enable input channel unit
* @param[in] ecap Specify ECAP port
* @param[in] u32Mask The input channel mask
* - \ref ECAP_CTL0_IC0EN_Msk
* - \ref ECAP_CTL0_IC1EN_Msk
* - \ref ECAP_CTL0_IC2EN_Msk
* @return None
* @details This macro will enable the input channel_n to input capture.
* \hideinitializer
*/
#define ECAP_ENABLE_INPUT_CHANNEL(ecap, u32Mask) ((ecap)->CTL0 |= (u32Mask))
/**
* @brief This macro is used to disable input channel unit
* @param[in] ecap Specify ECAP port
* @param[in] u32Mask The input channel mask
* - \ref ECAP_CTL0_IC0EN_Msk
* - \ref ECAP_CTL0_IC1EN_Msk
* - \ref ECAP_CTL0_IC2EN_Msk
* @return None
* @details This macro will disable the input channel_n to input capture.
* \hideinitializer
*/
#define ECAP_DISABLE_INPUT_CHANNEL(ecap, u32Mask) ((ecap)->CTL0 &= ~(u32Mask))
/**
* @brief This macro is used to select input channel source
* @param[in] ecap Specify ECAP port
* @param[in] u32Index The input channel number
* - \ref ECAP_IC0
* - \ref ECAP_IC1
* - \ref ECAP_IC2
* @param[in] u32Src The input source
* - \ref ECAP_CAP_INPUT_SRC_FROM_IC
* - \ref ECAP_CAP_INPUT_SRC_FROM_CH
* @return None
* @details This macro will select the input source from ICx, CHx.
* \hideinitializer
*/
#define ECAP_SEL_INPUT_SRC(ecap, u32Index, u32Src) ((ecap)->CTL0 = ((ecap)->CTL0 & ~(ECAP_CTL0_CAPSEL0_Msk<<((u32Index)<<1)))|(((u32Src)<<ECAP_CTL0_CAPSEL0_Pos)<<((u32Index)<<1)))
/**
* @brief This macro is used to enable input channel interrupt
* @param[in] ecap Specify ECAP port
* @param[in] u32Mask The input channel mask
* - \ref ECAP_CTL0_CAPIEN0_Msk
* - \ref ECAP_CTL0_CAPIEN1_Msk
* - \ref ECAP_CTL0_CAPIEN2_Msk
* @return None
* @details This macro will enable the input channel_n interrupt.
* \hideinitializer
*/
#define ECAP_ENABLE_INT(ecap, u32Mask) ((ecap)->CTL0 |= (u32Mask))
/**
* @brief This macro is used to disable input channel interrupt
* @param[in] ecap Specify ECAP port
* @param[in] u32Mask The input channel mask
* - \ref ECAP_IC0
* - \ref ECAP_IC1
* - \ref ECAP_IC2
* @return None
* @details This macro will disable the input channel_n interrupt.
* \hideinitializer
*/
#define ECAP_DISABLE_INT(ecap, u32Mask) ((ecap)->CTL0 &= ~(u32Mask))
/**
* @brief This macro is used to enable input channel overflow interrupt
* @param[in] ecap Specify ECAP port
* @return None
* @details This macro will enable the input channel overflow interrupt.
* \hideinitializer
*/
#define ECAP_ENABLE_OVF_INT(ecap) ((ecap)->CTL0 |= ECAP_CTL0_OVIEN_Msk)
/**
* @brief This macro is used to disable input channel overflow interrupt
* @param[in] ecap Specify ECAP port
* @return None
* @details This macro will disable the input channel overflow interrupt.
* \hideinitializer
*/
#define ECAP_DISABLE_OVF_INT(ecap) ((ecap)->CTL0 &= ~ECAP_CTL0_OVIEN_Msk)
/**
* @brief This macro is used to enable input channel compare-match interrupt
* @param[in] ecap Specify ECAP port
* @return None
* @details This macro will enable the input channel compare-match interrupt.
* \hideinitializer
*/
#define ECAP_ENABLE_CMP_MATCH_INT(ecap) ((ecap)->CTL0 |= ECAP_CTL0_CMPIEN_Msk)
/**
* @brief This macro is used to disable input channel compare-match interrupt
* @param[in] ecap Specify ECAP port
* @return None
* @details This macro will disable the input channel compare-match interrupt.
* \hideinitializer
*/
#define ECAP_DISABLE_CMP_MATCH_INT(ecap) ((ecap)->CTL0 &= ~ECAP_CTL0_CMPIEN_Msk)
/**
* @brief This macro is used to start capture counter
* @param[in] ecap Specify ECAP port
* @return None
* @details This macro will start capture counter up-counting.
* \hideinitializer
*/
#define ECAP_CNT_START(ecap) ((ecap)->CTL0 |= ECAP_CTL0_CNTEN_Msk)
/**
* @brief This macro is used to stop capture counter
* @param[in] ecap Specify ECAP port
* @return None
* @details This macro will stop capture counter up-counting.
* \hideinitializer
*/
#define ECAP_CNT_STOP(ecap) ((ecap)->CTL0 &= ~ECAP_CTL0_CNTEN_Msk)
/**
* @brief This macro is used to set event to clear capture counter
* @param[in] ecap Specify ECAP port
* @param[in] u32Event The input channel number
* - \ref ECAP_CTL1_CAP0CLREN_Msk
* - \ref ECAP_CTL1_CAP1CLREN_Msk
* - \ref ECAP_CTL1_CAP2CLREN_Msk
* @return None
* @details This macro will enable and select compare or capture event that can clear capture counter.
* \hideinitializer
*/
#define ECAP_SET_CNT_CLEAR_EVENT(ecap, u32Event) do{ \
if((u32Event) & ECAP_CTL0_CMPCLREN_Msk) \
(ecap)->CTL0 |= ECAP_CTL0_CMPCLREN_Msk; \
else \
(ecap)->CTL0 &= ~ECAP_CTL0_CMPCLREN_Msk; \
(ecap)->CTL1 = ((ecap)->CTL1 &~0x700000) | ((u32Event) & 0x700000); \
}while(0);
/**
* @brief This macro is used to enable compare function
* @param[in] ecap Specify ECAP port
* @return None
* @details This macro will enable the compare function.
* \hideinitializer
*/
#define ECAP_ENABLE_CMP(ecap) ((ecap)->CTL0 |= ECAP_CTL0_CMPEN_Msk)
/**
* @brief This macro is used to disable compare function
* @param[in] ecap Specify ECAP port
* @return None
* @details This macro will disable the compare function.
* \hideinitializer
*/
#define ECAP_DISABLE_CMP(ecap) ((ecap)->CTL0 &= ~ECAP_CTL0_CMPEN_Msk)
/**
* @brief This macro is used to enable input capture function.
* @param[in] ecap Specify ECAP port
* @return None
* @details This macro will enable input capture timer/counter.
* \hideinitializer
*/
#define ECAP_ENABLE_CNT(ecap) ((ecap)->CTL0 |= ECAP_CTL0_CAPEN_Msk)
/**
* @brief This macro is used to disable input capture function.
* @param[in] ecap Specify ECAP port
* @return None
* @details This macro will disable input capture timer/counter.
* \hideinitializer
*/
#define ECAP_DISABLE_CNT(ecap) ((ecap)->CTL0 &= ~ECAP_CTL0_CAPEN_Msk)
/**
* @brief This macro is used to select input channel edge detection
* @param[in] ecap Specify ECAP port
* @param[in] u32Index The input channel number
* - \ref ECAP_IC0
* - \ref ECAP_IC1
* - \ref ECAP_IC2
* @param[in] u32Edge The input source
* - \ref ECAP_RISING_EDGE
* - \ref ECAP_FALLING_EDGE
* - \ref ECAP_RISING_FALLING_EDGE
* @return None
* @details This macro will select input capture can detect falling edge, rising edge or either rising or falling edge change.
* \hideinitializer
*/
#define ECAP_SEL_CAPTURE_EDGE(ecap, u32Index, u32Edge) ((ecap)->CTL1 = ((ecap)->CTL1 & ~(ECAP_CTL1_EDGESEL0_Msk<<((u32Index)<<1)))|((u32Edge)<<((u32Index)<<1)))
/**
* @brief This macro is used to select ECAP counter reload trigger source
* @param[in] ecap Specify ECAP port
* @param[in] u32TrigSrc The input source
* - \ref ECAP_CTL1_CAP0RLDEN_Msk
* - \ref ECAP_CTL1_CAP1RLDEN_Msk
* - \ref ECAP_CTL1_CAP2RLDEN_Msk
* - \ref ECAP_CTL1_OVRLDEN_Msk
* @return None
* @details This macro will select capture counter reload trigger source.
* \hideinitializer
*/
#define ECAP_SEL_RELOAD_TRIG_SRC(ecap, u32TrigSrc) ((ecap)->CTL1 = ((ecap)->CTL1 & ~0xF00)|(u32TrigSrc))
/**
* @brief This macro is used to select capture timer clock divide.
* @param[in] ecap Specify ECAP port
* @param[in] u32Clkdiv The input source
* - \ref ECAP_CAPTURE_TIMER_CLKDIV_1
* - \ref ECAP_CAPTURE_TIMER_CLKDIV_4
* - \ref ECAP_CAPTURE_TIMER_CLKDIV_16
* - \ref ECAP_CAPTURE_TIMER_CLKDIV_32
* - \ref ECAP_CAPTURE_TIMER_CLKDIV_64
* - \ref ECAP_CAPTURE_TIMER_CLKDIV_96
* - \ref ECAP_CAPTURE_TIMER_CLKDIV_112
* - \ref ECAP_CAPTURE_TIMER_CLKDIV_128
* @return None
* @details This macro will select capture timer clock has a pre-divider with eight divided option.
* \hideinitializer
*/
#define ECAP_SEL_TIMER_CLK_DIV(ecap, u32Clkdiv) ((ecap)->CTL1 = ((ecap)->CTL1 & ~ECAP_CTL1_CLKSEL_Msk)|(u32Clkdiv))
/**
* @brief This macro is used to select capture timer/counter clock source
* @param[in] ecap Specify ECAP port
* @param[in] u32ClkSrc The input source
* - \ref ECAP_CAPTURE_TIMER_CLK_SRC_CAP_CLK
* - \ref ECAP_CAPTURE_TIMER_CLK_SRC_CAP0
* - \ref ECAP_CAPTURE_TIMER_CLK_SRC_CAP1
* - \ref ECAP_CAPTURE_TIMER_CLK_SRC_CAP2
* @return None
* @details This macro will select capture timer/clock clock source.
* \hideinitializer
*/
#define ECAP_SEL_TIMER_CLK_SRC(ecap, u32ClkSrc) ((ecap)->CTL1 = ((ecap)->CTL1 & ~ECAP_CTL1_CNTSRCSEL_Msk)|(u32ClkSrc))
/**
* @brief This macro is used to read input capture status
* @param[in] ecap Specify ECAP port
* @return Input capture status flags
* @details This macro will get the input capture interrupt status.
* \hideinitializer
*/
#define ECAP_GET_INT_STATUS(ecap) ((ecap)->STATUS)
/**
* @brief This macro is used to get input channel interrupt flag
* @param[in] ecap Specify ECAP port
* @param[in] u32Mask The input channel mask
* - \ref ECAP_STATUS_CAPTF0_Msk
* - \ref ECAP_STATUS_CAPTF1_Msk
* - \ref ECAP_STATUS_CAPTF2_Msk
* - \ref ECAP_STATUS_CAPOVF_Msk
* - \ref ECAP_STATUS_CAPCMPF_Msk
* @return None
* @details This macro will write 1 to get the input channel_n interrupt flag.
* \hideinitializer
*/
#define ECAP_GET_CAPTURE_FLAG(ecap, u32Mask) (((ecap)->STATUS & (u32Mask))?1:0)
/**
* @brief This macro is used to clear input channel interrupt flag
* @param[in] ecap Specify ECAP port
* @param[in] u32Mask The input channel mask
* - \ref ECAP_STATUS_CAPTF0_Msk
* - \ref ECAP_STATUS_CAPTF1_Msk
* - \ref ECAP_STATUS_CAPTF2_Msk
* - \ref ECAP_STATUS_CAPOVF_Msk
* - \ref ECAP_STATUS_CAPCMPF_Msk
* @return None
* @details This macro will write 1 to clear the input channel_n interrupt flag.
* \hideinitializer
*/
#define ECAP_CLR_CAPTURE_FLAG(ecap, u32Mask) ((ecap)->STATUS = (u32Mask))
/**
* @brief This macro is used to set input capture counter value
* @param[in] ecap Specify ECAP port
* @param[in] u32Val Counter value
* @return None
* @details This macro will set a counter value of input capture.
* \hideinitializer
*/
#define ECAP_SET_CNT_VALUE(ecap, u32Val) ((ecap)->CNT = (u32Val))
/**
* @brief This macro is used to get input capture counter value
* @param[in] ecap Specify ECAP port
* @return Capture counter value
* @details This macro will get a counter value of input capture.
* \hideinitializer
*/
#define ECAP_GET_CNT_VALUE(ecap) ((ecap)->CNT)
/**
* @brief This macro is used to get input capture counter hold value
* @param[in] ecap Specify ECAP port
* @param[in] u32Index The input channel number
* - \ref ECAP_IC0
* - \ref ECAP_IC1
* - \ref ECAP_IC2
* @return Capture counter hold value
* @details This macro will get a hold value of input capture channel_n.
* \hideinitializer
*/
#define ECAP_GET_CNT_HOLD_VALUE(ecap, u32Index) (*(__IO uint32_t *) (&((ecap)->HLD0) + (u32Index)))
/**
* @brief This macro is used to set input capture counter compare value
* @param[in] ecap Specify ECAP port
* @param[in] u32Val Input capture compare value
* @return None
* @details This macro will set a compare value of input capture counter.
* \hideinitializer
*/
#define ECAP_SET_CNT_CMP(ecap, u32Val) ((ecap)->CNTCMP = (u32Val))
void ECAP_Open(ECAP_T *ecap, uint32_t u32FuncMask);
void ECAP_Close(ECAP_T *ecap);
void ECAP_EnableINT(ECAP_T *ecap, uint32_t u32Mask);
void ECAP_DisableINT(ECAP_T *ecap, uint32_t u32Mask);
/*@}*/ /* end of group ECAP_EXPORTED_FUNCTIONS */
/*@}*/ /* end of group ECAP_Driver */
/*@}*/ /* end of group Standard_Driver */
#ifdef __cplusplus
}
#endif
#endif /* __NU_ECAP_H__ */

643
bsp/nuvoton/libraries/ma35/StdDriver/inc/nu_epwm.h Normal file
View File

@ -0,0 +1,643 @@
/**************************************************************************//**
* @file nu_epwm.h
* @brief EPWM driver header file
*
* SPDX-License-Identifier: Apache-2.0
* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __NU_EPWM_H__
#define __NU_EPWM_H__
#ifdef __cplusplus
extern "C"
{
#endif
/** @addtogroup Standard_Driver Standard Driver
@{
*/
/** @addtogroup EPWM_Driver EPWM Driver
@{
*/
/** @addtogroup EPWM_EXPORTED_CONSTANTS EPWM Exported Constants
@{
*/
#define EPWM_CHANNEL_NUM (6U) /*!< EPWM channel number \hideinitializer */
#define EPWM_CH_0_MASK (0x1U) /*!< EPWM channel 0 mask \hideinitializer */
#define EPWM_CH_1_MASK (0x2U) /*!< EPWM channel 1 mask \hideinitializer */
#define EPWM_CH_2_MASK (0x4U) /*!< EPWM channel 2 mask \hideinitializer */
#define EPWM_CH_3_MASK (0x8U) /*!< EPWM channel 3 mask \hideinitializer */
#define EPWM_CH_4_MASK (0x10U) /*!< EPWM channel 4 mask \hideinitializer */
#define EPWM_CH_5_MASK (0x20U) /*!< EPWM channel 5 mask \hideinitializer */
/*---------------------------------------------------------------------------------------------------------*/
/* Counter Type Constant Definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define EPWM_UP_COUNTER (0U) /*!< Up counter type \hideinitializer */
#define EPWM_DOWN_COUNTER (1U) /*!< Down counter type \hideinitializer */
#define EPWM_UP_DOWN_COUNTER (2U) /*!< Up-Down counter type \hideinitializer */
/*---------------------------------------------------------------------------------------------------------*/
/* Aligned Type Constant Definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define EPWM_EDGE_ALIGNED (1U) /*!< EPWM working in edge aligned type(down count) \hideinitializer */
#define EPWM_CENTER_ALIGNED (2U) /*!< EPWM working in center aligned type \hideinitializer */
/*---------------------------------------------------------------------------------------------------------*/
/* Output Level Constant Definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define EPWM_OUTPUT_NOTHING (0U) /*!< EPWM output nothing \hideinitializer */
#define EPWM_OUTPUT_LOW (1U) /*!< EPWM output low \hideinitializer */
#define EPWM_OUTPUT_HIGH (2U) /*!< EPWM output high \hideinitializer */
#define EPWM_OUTPUT_TOGGLE (3U) /*!< EPWM output toggle \hideinitializer */
/*---------------------------------------------------------------------------------------------------------*/
/* Synchronous Start Function Control Constant Definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define EPWM_SSCTL_SSRC_EPWM0 (0U<<EPWM_SSCTL_SSRC_Pos) /*!< Synchronous start source comes from EPWM0 \hideinitializer */
#define EPWM_SSCTL_SSRC_EPWM1 (1U<<EPWM_SSCTL_SSRC_Pos) /*!< Synchronous start source comes from EPWM0 \hideinitializer */
#define EPWM_SSCTL_SSRC_BPWM0 (2UL<<EPWM_SSCTL_SSRC_Pos) /*!< Synchronous start source comes from BPWM0 \hideinitializer */
#define EPWM_SSCTL_SSRC_BPWM1 (3UL<<EPWM_SSCTL_SSRC_Pos) /*!< Synchronous start source comes from BPWM1 \hideinitializer */
/*---------------------------------------------------------------------------------------------------------*/
/* Trigger Source Select Constant Definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define EPWM_TRG_ADC_EVEN_ZERO (0U) /*!< EPWM trigger ADC while counter of even channel matches zero point \hideinitializer */
#define EPWM_TRG_ADC_EVEN_PERIOD (1U) /*!< EPWM trigger ADC while counter of even channel matches period point \hideinitializer */
#define EPWM_TRG_ADC_EVEN_ZERO_PERIOD (2U) /*!< EPWM trigger ADC while counter of even channel matches zero or period point \hideinitializer */
#define EPWM_TRG_ADC_EVEN_COMPARE_UP (3U) /*!< EPWM trigger ADC while counter of even channel matches up count to comparator point \hideinitializer */
#define EPWM_TRG_ADC_EVEN_COMPARE_DOWN (4U) /*!< EPWM trigger ADC while counter of even channel matches down count to comparator point \hideinitializer */
#define EPWM_TRG_ADC_ODD_ZERO (5U) /*!< EPWM trigger ADC while counter of odd channel matches zero point \hideinitializer */
#define EPWM_TRG_ADC_ODD_PERIOD (6U) /*!< EPWM trigger ADC while counter of odd channel matches period point \hideinitializer */
#define EPWM_TRG_ADC_ODD_ZERO_PERIOD (7U) /*!< EPWM trigger ADC while counter of odd channel matches zero or period point \hideinitializer */
#define EPWM_TRG_ADC_ODD_COMPARE_UP (8U) /*!< EPWM trigger ADC while counter of odd channel matches up count to comparator point \hideinitializer */
#define EPWM_TRG_ADC_ODD_COMPARE_DOWN (9U) /*!< EPWM trigger ADC while counter of odd channel matches down count to comparator point \hideinitializer */
#define EPWM_TRG_ADC_CH_0_FREE_CMP_UP (10U) /*!< EPWM trigger ADC while counter of channel 0 matches up count to free comparator point \hideinitializer */
#define EPWM_TRG_ADC_CH_0_FREE_CMP_DOWN (11U) /*!< EPWM trigger ADC while counter of channel 0 matches down count to free comparator point \hideinitializer */
#define EPWM_TRG_ADC_CH_2_FREE_CMP_UP (12U) /*!< EPWM trigger ADC while counter of channel 2 matches up count to free comparator point \hideinitializer */
#define EPWM_TRG_ADC_CH_2_FREE_CMP_DOWN (13U) /*!< EPWM trigger ADC while counter of channel 2 matches down count to free comparator point \hideinitializer */
#define EPWM_TRG_ADC_CH_4_FREE_CMP_UP (14U) /*!< EPWM trigger ADC while counter of channel 4 matches up count to free comparator point \hideinitializer */
#define EPWM_TRG_ADC_CH_4_FREE_CMP_DOWN (15U) /*!< EPWM trigger ADC while counter of channel 4 matches down count to free comparator point \hideinitializer */
#define EPWM_TRIGGER_DAC_ZERO (0x1U) /*!< EPWM trigger DAC while counter down count to 0 \hideinitializer */
#define EPWM_TRIGGER_DAC_PERIOD (0x100U) /*!< EPWM trigger DAC while counter matches (PERIOD + 1) \hideinitializer */
#define EPWM_TRIGGER_DAC_COMPARE_UP (0x10000U) /*!< EPWM trigger DAC while counter up count to CMPDAT \hideinitializer */
#define EPWM_TRIGGER_DAC_COMPARE_DOWN (0x1000000U) /*!< EPWM trigger DAC while counter down count to CMPDAT \hideinitializer */
/*---------------------------------------------------------------------------------------------------------*/
/* Fail brake Control Constant Definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define EPWM_FB_EDGE_ACMP0 (EPWM_BRKCTL0_1_CPO0EBEN_Msk) /*!< Comparator 0 as edge-detect fault brake source \hideinitializer */
#define EPWM_FB_EDGE_ACMP1 (EPWM_BRKCTL0_1_CPO1EBEN_Msk) /*!< Comparator 1 as edge-detect fault brake source \hideinitializer */
#define EPWM_FB_EDGE_BKP0 (EPWM_BRKCTL0_1_BRKP0EEN_Msk) /*!< BKP0 pin as edge-detect fault brake source \hideinitializer */
#define EPWM_FB_EDGE_BKP1 (EPWM_BRKCTL0_1_BRKP1EEN_Msk) /*!< BKP1 pin as edge-detect fault brake source \hideinitializer */
#define EPWM_FB_EDGE_ADCRM (EPWM_BRKCTL0_1_EADCEBEN_Msk) /*!< ADC Result Monitor (ADCRM) as edge-detect fault brake source \hideinitializer */
#define EPWM_FB_EDGE_SYS_CSS (EPWM_BRKCTL0_1_SYSEBEN_Msk | EPWM_FAILBRK_CSSBRKEN_Msk) /*!< System fail condition: clock security system detection as edge-detect fault brake source \hideinitializer */
#define EPWM_FB_EDGE_SYS_BOD (EPWM_BRKCTL0_1_SYSEBEN_Msk | EPWM_FAILBRK_BODBRKEN_Msk) /*!< System fail condition: brown-out detection as edge-detect fault brake source \hideinitializer */
#define EPWM_FB_EDGE_SYS_RAM (EPWM_BRKCTL0_1_SYSEBEN_Msk | EPWM_FAILBRK_RAMBRKEN_Msk) /*!< System fail condition: SRAM parity error detection as edge-detect fault brake source \hideinitializer */
#define EPWM_FB_EDGE_SYS_COR (EPWM_BRKCTL0_1_SYSEBEN_Msk | EPWM_FAILBRK_CORBRKEN_Msk) /*!< System fail condition: core lockup detection as edge-detect fault brake source \hideinitializer */
#define EPWM_FB_LEVEL_ACMP0 (EPWM_BRKCTL0_1_CPO0LBEN_Msk) /*!< Comparator 0 as level-detect fault brake source \hideinitializer */
#define EPWM_FB_LEVEL_ACMP1 (EPWM_BRKCTL0_1_CPO1LBEN_Msk) /*!< Comparator 1 as level-detect fault brake source \hideinitializer */
#define EPWM_FB_LEVEL_BKP0 (EPWM_BRKCTL0_1_BRKP0LEN_Msk) /*!< BKP0 pin as level-detect fault brake source \hideinitializer */
#define EPWM_FB_LEVEL_BKP1 (EPWM_BRKCTL0_1_BRKP1LEN_Msk) /*!< BKP1 pin as level-detect fault brake source \hideinitializer */
#define EPWM_FB_LEVEL_ADCRM (EPWM_BRKCTL0_1_EADCLBEN_Msk) /*!< ADC Result Monitor (ADCRM) as level-detect fault brake source \hideinitializer */
#define EPWM_FB_LEVEL_SYS_CSS (EPWM_BRKCTL0_1_SYSLBEN_Msk | EPWM_FAILBRK_CSSBRKEN_Msk) /*!< System fail condition: clock security system detection as level-detect fault brake source \hideinitializer */
#define EPWM_FB_LEVEL_SYS_BOD (EPWM_BRKCTL0_1_SYSLBEN_Msk | EPWM_FAILBRK_BODBRKEN_Msk) /*!< System fail condition: brown-out detection as level-detect fault brake source \hideinitializer */
#define EPWM_FB_LEVEL_SYS_RAM (EPWM_BRKCTL0_1_SYSLBEN_Msk | EPWM_FAILBRK_RAMBRKEN_Msk) /*!< System fail condition: SRAM parity error detection as level-detect fault brake source \hideinitializer */
#define EPWM_FB_LEVEL_SYS_COR (EPWM_BRKCTL0_1_SYSLBEN_Msk | EPWM_FAILBRK_CORBRKEN_Msk) /*!< System fail condition: core lockup detection as level-detect fault brake source \hideinitializer */
#define EPWM_FB_EDGE (0U) /*!< edge-detect fault brake \hideinitializer */
#define EPWM_FB_LEVEL (8U) /*!< level-detect fault brake \hideinitializer */
/*---------------------------------------------------------------------------------------------------------*/
/* Leading Edge Blanking Control Constant Definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define EPWM_LEBCTL_TRGTYPE_RISING (0U<<EPWM_LEBCTL_TRGTYPE_Pos) /*!< EPWM Leading Edge Blanking Trigger Type Is Rising Edge \hideinitializer */
#define EPWM_LEBCTL_TRGTYPE_FALLING (1U<<EPWM_LEBCTL_TRGTYPE_Pos) /*!< EPWM Leading Edge Blanking Trigger Type Is Falling Edge \hideinitializer */
#define EPWM_LEBCTL_TRGTYPE_RISING_OR_FALLING (2U<<EPWM_LEBCTL_TRGTYPE_Pos) /*!< EPWM Leading Edge Blanking Trigger Type Is Rising or Falling Edge \hideinitializer */
#define EPWM_LEBCTL_SRCEN0 (EPWM_LEBCTL_SRCEN0_Msk) /*!< EPWM Leading Edge Blanking Source From EPWMx_CH0 Enable \hideinitializer */
#define EPWM_LEBCTL_SRCEN2 (EPWM_LEBCTL_SRCEN2_Msk) /*!< EPWM Leading Edge Blanking Source From EPWMx_CH2 Enable \hideinitializer */
#define EPWM_LEBCTL_SRCEN4 (EPWM_LEBCTL_SRCEN4_Msk) /*!< EPWM Leading Edge Blanking Source From EPWMx_CH4 Enable \hideinitializer */
#define EPWM_LEBCTL_SRCEN0_2 (EPWM_LEBCTL_SRCEN0_Msk|EPWM_LEBCTL_SRCEN2_Msk) /*!< EPWM Leading Edge Blanking Source From EPWMx_CH0 and EPWMx_CH2 Enable \hideinitializer */
#define EPWM_LEBCTL_SRCEN0_4 (EPWM_LEBCTL_SRCEN0_Msk|EPWM_LEBCTL_SRCEN4_Msk) /*!< EPWM Leading Edge Blanking Source From EPWMx_CH0 and EPWMx_CH4 Enable \hideinitializer */
#define EPWM_LEBCTL_SRCEN2_4 (EPWM_LEBCTL_SRCEN2_Msk|EPWM_LEBCTL_SRCEN4_Msk) /*!< EPWM Leading Edge Blanking Source From EPWMx_CH2 and EPWMx_CH4 Enable \hideinitializer */
#define EPWM_LEBCTL_SRCEN0_2_4 (EPWM_LEBCTL_SRCEN0_Msk|EPWM_LEBCTL_SRCEN2_Msk|EPWM_LEBCTL_SRCEN4_Msk) /*!< EPWM Leading Edge Blanking Source From EPWMx_CH0, EPWMx_CH2 and EPWMx_CH4 Enable \hideinitializer */
/*---------------------------------------------------------------------------------------------------------*/
/* Capture Control Constant Definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define EPWM_CAPTURE_INT_RISING_LATCH (1U) /*!< EPWM capture interrupt if channel has rising transition \hideinitializer */
#define EPWM_CAPTURE_INT_FALLING_LATCH (0x100U) /*!< EPWM capture interrupt if channel has falling transition \hideinitializer */
#define EPWM_CAPTURE_PDMA_RISING_LATCH (0x2U) /*!< EPWM capture rising latched data transfer by PDMA \hideinitializer */
#define EPWM_CAPTURE_PDMA_FALLING_LATCH (0x4U) /*!< EPWM capture falling latched data transfer by PDMA \hideinitializer */
#define EPWM_CAPTURE_PDMA_RISING_FALLING_LATCH (0x6U) /*!< EPWM capture rising and falling latched data transfer by PDMA \hideinitializer */
/*---------------------------------------------------------------------------------------------------------*/
/* Duty Interrupt Type Constant Definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define EPWM_DUTY_INT_DOWN_COUNT_MATCH_CMP (1U << EPWM_INTEN0_CMPDIEN0_Pos) /*!< EPWM duty interrupt triggered if down count match comparator \hideinitializer */
#define EPWM_DUTY_INT_UP_COUNT_MATCH_CMP (1U << EPWM_INTEN0_CMPUIEN0_Pos) /*!< EPWM duty interrupt triggered if up down match comparator \hideinitializer */
/*---------------------------------------------------------------------------------------------------------*/
/* Interrupt Flag Accumulator Constant Definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define EPWM_IFA_ZERO_POINT (0U) /*!< EPWM counter equal to zero \hideinitializer */
#define EPWM_IFA_PERIOD_POINT (1U) /*!< EPWM counter equal to period \hideinitializer */
#define EPWM_IFA_COMPARE_UP_COUNT_POINT (2U) /*!< EPWM counter up count to comparator value \hideinitializer */
#define EPWM_IFA_COMPARE_DOWN_COUNT_POINT (3U) /*!< EPWM counter down count to comparator value \hideinitializer */
/*---------------------------------------------------------------------------------------------------------*/
/* Load Mode Constant Definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define EPWM_LOAD_MODE_IMMEDIATE (1U << EPWM_CTL0_IMMLDEN0_Pos) /*!< EPWM immediately load mode \hideinitializer */
#define EPWM_LOAD_MODE_WINDOW (1U << EPWM_CTL0_WINLDEN0_Pos) /*!< EPWM window load mode \hideinitializer */
#define EPWM_LOAD_MODE_CENTER (1U << EPWM_CTL0_CTRLD0_Pos) /*!< EPWM center load mode \hideinitializer */
/*---------------------------------------------------------------------------------------------------------*/
/* Synchronize Control Constant Definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define EPWM_SYNC_OUT_FROM_SYNCIN_SWSYNC (0U) /*!< Synchronize source from SYNC_IN or SWSYNC \hideinitializer */
#define EPWM_SYNC_OUT_FROM_COUNT_TO_ZERO (1U) /*!< Synchronize source from counter equal to 0 \hideinitializer */
#define EPWM_SYNC_OUT_FROM_COUNT_TO_COMPARATOR (2U) /*!< Synchronize source from counter equal to CMPDAT1, CMPDAT3, CMPDAT5 \hideinitializer */
#define EPWM_SYNC_OUT_DISABLE (3U) /*!< SYNC_OUT will not be generated \hideinitializer */
#define EPWM_PHS_DIR_DECREMENT (0U) /*!< EPWM counter count decrement \hideinitializer */
#define EPWM_PHS_DIR_INCREMENT (1U) /*!< EPWM counter count increment \hideinitializer */
/*---------------------------------------------------------------------------------------------------------*/
/* Noise Filter Clock Divide Select Constant Definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define EPWM_NF_CLK_DIV_1 (0U) /*!< Noise filter clock is HCLK divide by 1 \hideinitializer */
#define EPWM_NF_CLK_DIV_2 (1U) /*!< Noise filter clock is HCLK divide by 2 \hideinitializer */
#define EPWM_NF_CLK_DIV_4 (2U) /*!< Noise filter clock is HCLK divide by 4 \hideinitializer */
#define EPWM_NF_CLK_DIV_8 (3U) /*!< Noise filter clock is HCLK divide by 8 \hideinitializer */
#define EPWM_NF_CLK_DIV_16 (4U) /*!< Noise filter clock is HCLK divide by 16 \hideinitializer */
#define EPWM_NF_CLK_DIV_32 (5U) /*!< Noise filter clock is HCLK divide by 32 \hideinitializer */
#define EPWM_NF_CLK_DIV_64 (6U) /*!< Noise filter clock is HCLK divide by 64 \hideinitializer */
#define EPWM_NF_CLK_DIV_128 (7U) /*!< Noise filter clock is HCLK divide by 128 \hideinitializer */
/*---------------------------------------------------------------------------------------------------------*/
/* Clock Source Select Constant Definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define EPWM_CLKSRC_EPWM_CLK (0U) /*!< EPWM Clock source selects to EPWM0_CLK or EPWM1_CLK \hideinitializer */
#define EPWM_CLKSRC_TIMER0 (1U) /*!< EPWM Clock source selects to TIMER0 overflow \hideinitializer */
#define EPWM_CLKSRC_TIMER1 (2U) /*!< EPWM Clock source selects to TIMER1 overflow \hideinitializer */
#define EPWM_CLKSRC_TIMER2 (3U) /*!< EPWM Clock source selects to TIMER2 overflow \hideinitializer */
#define EPWM_CLKSRC_TIMER3 (4U) /*!< EPWM Clock source selects to TIMER3 overflow \hideinitializer */
/*---------------------------------------------------------------------------------------------------------*/
/* Fault Detect Clock Source Select Constant Definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define EPWM_FDCTL_FDCKSEL_CLK_DIV_1 (0UL << EPWM_FDCTL0_FDCKSEL_Pos) /*!< Fault detect clock selects to fault detect clock divided by 1 \hideinitializer */
#define EPWM_FDCTL_FDCKSEL_CLK_DIV_2 (1UL << EPWM_FDCTL0_FDCKSEL_Pos) /*!< Fault detect clock selects to fault detect clock divided by 2 \hideinitializer */
#define EPWM_FDCTL_FDCKSEL_CLK_DIV_4 (2UL << EPWM_FDCTL0_FDCKSEL_Pos) /*!< Fault detect clock selects to fault detect clock divided by 4 \hideinitializer */
#define EPWM_FDCTL_FDCKSEL_CLK_DIV_8 (3UL << EPWM_FDCTL0_FDCKSEL_Pos) /*!< Fault detect clock selects to fault detect clock divided by 8 \hideinitializer */
/*@}*/ /* end of group EPWM_EXPORTED_CONSTANTS */
/** @addtogroup EPWM_EXPORTED_FUNCTIONS EPWM Exported Functions
@{
*/
/**
* @brief This macro enable complementary mode
* @param[in] epwm The pointer of the specified EPWM module
* @return None
* @details This macro is used to enable complementary mode of EPWM module.
* \hideinitializer
*/
#define EPWM_ENABLE_COMPLEMENTARY_MODE(epwm) ((epwm)->CTL1 = (epwm)->CTL1 | (0x7ul<<EPWM_CTL1_OUTMODE0_Pos))
/**
* @brief This macro disable complementary mode, and enable independent mode.
* @param[in] epwm The pointer of the specified EPWM module
* @return None
* @details This macro is used to disable complementary mode of EPWM module.
* \hideinitializer
*/
#define EPWM_DISABLE_COMPLEMENTARY_MODE(epwm) ((epwm)->CTL1 = (epwm)->CTL1 & ~(0x7ul<<EPWM_CTL1_OUTMODE0_Pos))
/**
* @brief This macro enable group mode
* @param[in] epwm The pointer of the specified EPWM module
* @return None
* @details This macro is used to enable group mode of EPWM module.
* \hideinitializer
*/
#define EPWM_ENABLE_GROUP_MODE(epwm) ((epwm)->CTL0 = (epwm)->CTL0 | EPWM_CTL0_GROUPEN_Msk)
/**
* @brief This macro disable group mode
* @param[in] epwm The pointer of the specified EPWM module
* @return None
* @details This macro is used to disable group mode of EPWM module.
* \hideinitializer
*/
#define EPWM_DISABLE_GROUP_MODE(epwm) ((epwm)->CTL0 = (epwm)->CTL0 & ~EPWM_CTL0_GROUPEN_Msk)
/**
* @brief Enable timer synchronous start counting function of specified channel(s)
* @param[in] epwm The pointer of the specified EPWM module
* @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
* Bit 0 represents channel 0, bit 1 represents channel 1...
* @param[in] u32SyncSrc Synchronous start source selection, valid values are:
* - \ref EPWM_SSCTL_SSRC_EPWM0
* - \ref EPWM_SSCTL_SSRC_EPWM1
* - \ref EPWM_SSCTL_SSRC_BPWM0
* - \ref EPWM_SSCTL_SSRC_BPWM1
* @return None
* @details This macro is used to enable timer synchronous start counting function of specified channel(s).
* \hideinitializer
*/
#define EPWM_ENABLE_TIMER_SYNC(epwm, u32ChannelMask, u32SyncSrc) ((epwm)->SSCTL = ((epwm)->SSCTL & ~EPWM_SSCTL_SSRC_Msk) | (u32SyncSrc) | (u32ChannelMask))
/**
* @brief Disable timer synchronous start counting function of specified channel(s)
* @param[in] epwm The pointer of the specified EPWM module
* @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
* Bit 0 represents channel 0, bit 1 represents channel 1...
* @return None
* @details This macro is used to disable timer synchronous start counting function of specified channel(s).
* \hideinitializer
*/
#define EPWM_DISABLE_TIMER_SYNC(epwm, u32ChannelMask) \
do{ \
int i;\
for(i = 0; i < 6; i++) { \
if((u32ChannelMask) & (1 << i)) \
(epwm)->SSCTL &= ~(1UL << i); \
} \
}while(0)
/**
* @brief This macro enable EPWM counter synchronous start counting function.
* @param[in] epwm The pointer of the specified EPWM module
* @return None
* @details This macro is used to make selected EPWM0 and EPWM1 channel(s) start counting at the same time.
* To configure synchronous start counting channel(s) by EPWM_ENABLE_TIMER_SYNC() and EPWM_DISABLE_TIMER_SYNC().
* \hideinitializer
*/
#define EPWM_TRIGGER_SYNC_START(epwm) ((epwm)->SSTRG = EPWM_SSTRG_CNTSEN_Msk)
/**
* @brief This macro enable output inverter of specified channel(s)
* @param[in] epwm The pointer of the specified EPWM module
* @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
* Bit 0 represents channel 0, bit 1 represents channel 1...
* @return None
* @details This macro is used to enable output inverter of specified channel(s).
* \hideinitializer
*/
#define EPWM_ENABLE_OUTPUT_INVERTER(epwm, u32ChannelMask) ((epwm)->POLCTL = (u32ChannelMask))
/**
* @brief This macro get captured rising data
* @param[in] epwm The pointer of the specified EPWM module
* @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
* @return None
* @details This macro is used to get captured rising data of specified channel.
* \hideinitializer
*/
#define EPWM_GET_CAPTURE_RISING_DATA(epwm, u32ChannelNum) ((epwm)->CAPDAT[(u32ChannelNum)].RCAPDAT)
/**
* @brief This macro get captured falling data
* @param[in] epwm The pointer of the specified EPWM module
* @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
* @return None
* @details This macro is used to get captured falling data of specified channel.
* \hideinitializer
*/
#define EPWM_GET_CAPTURE_FALLING_DATA(epwm, u32ChannelNum) ((epwm)->CAPDAT[(u32ChannelNum)].FCAPDAT)
/**
* @brief This macro mask output logic to high or low
* @param[in] epwm The pointer of the specified EPWM module
* @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
* Bit 0 represents channel 0, bit 1 represents channel 1...
* @param[in] u32LevelMask Output logic to high or low
* @return None
* @details This macro is used to mask output logic to high or low of specified channel(s).
* @note If u32ChannelMask parameter is 0, then mask function will be disabled.
* \hideinitializer
*/
#define EPWM_MASK_OUTPUT(epwm, u32ChannelMask, u32LevelMask) \
{ \
(epwm)->MSKEN = (u32ChannelMask); \
(epwm)->MSK = (u32LevelMask); \
}
/**
* @brief This macro set the prescaler of the selected channel
* @param[in] epwm The pointer of the specified EPWM module
* @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
* @param[in] u32Prescaler Clock prescaler of specified channel. Valid values are between 0 ~ 0xFFF
* @return None
* @details This macro is used to set the prescaler of specified channel.
* @note Every even channel N, and channel (N + 1) share a prescaler. So if channel 0 prescaler changed, channel 1 will also be affected.
* The clock of EPWM counter is divided by (u32Prescaler + 1).
* \hideinitializer
*/
#define EPWM_SET_PRESCALER(epwm, u32ChannelNum, u32Prescaler) ((epwm)->CLKPSC[(u32ChannelNum) >> 1] = (u32Prescaler))
/**
* @brief This macro get the prescaler of the selected channel
* @param[in] epwm The pointer of the specified EPWM module
* @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
* @return Return Clock prescaler of specified channel. Valid values are between 0 ~ 0xFFF
* @details This macro is used to get the prescaler of specified channel.
* @note Every even channel N, and channel (N + 1) share a prescaler. So if channel 0 prescaler changed, channel 1 will also be affected.
* The clock of EPWM counter is divided by (u32Prescaler + 1).
* \hideinitializer
*/
#define EPWM_GET_PRESCALER(epwm, u32ChannelNum) ((epwm)->CLKPSC[(u32ChannelNum) >> 1U])
/**
* @brief This macro set the comparator of the selected channel
* @param[in] epwm The pointer of the specified EPWM module
* @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
* @param[in] u32CMR Comparator of specified channel. Valid values are between 0~0xFFFF
* @return None
* @details This macro is used to set the comparator of specified channel.
* @note This new setting will take effect on next EPWM period.
* \hideinitializer
*/
#define EPWM_SET_CMR(epwm, u32ChannelNum, u32CMR) ((epwm)->CMPDAT[(u32ChannelNum)]= (u32CMR))
/**
* @brief This macro get the comparator of the selected channel
* @param[in] epwm The pointer of the specified EPWM module
* @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
* @return Return the comparator of specified channel. Valid values are between 0~0xFFFF
* @details This macro is used to get the comparator of specified channel.
* \hideinitializer
*/
#define EPWM_GET_CMR(epwm, u32ChannelNum) ((epwm)->CMPDAT[(u32ChannelNum)])
/**
* @brief This macro set the free trigger comparator of the selected channel
* @param[in] epwm The pointer of the specified EPWM module
* @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
* @param[in] u32FTCMR Free trigger comparator of specified channel. Valid values are between 0~0xFFFF
* @return None
* @details This macro is used to set the free trigger comparator of specified channel.
* @note This new setting will take effect on next EPWM period.
* \hideinitializer
*/
#define EPWM_SET_FTCMR(epwm, u32ChannelNum, u32FTCMR) (((epwm)->FTCMPDAT[((u32ChannelNum) >> 1U)]) = (u32FTCMR))
/**
* @brief This macro set the period of the selected channel
* @param[in] epwm The pointer of the specified EPWM module
* @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
* @param[in] u32CNR Period of specified channel. Valid values are between 0~0xFFFF
* @return None
* @details This macro is used to set the period of specified channel.
* @note This new setting will take effect on next EPWM period.
* @note EPWM counter will stop if period length set to 0.
* \hideinitializer
*/
#define EPWM_SET_CNR(epwm, u32ChannelNum, u32CNR) ((epwm)->PERIOD[(u32ChannelNum)] = (u32CNR))
/**
* @brief This macro get the period of the selected channel
* @param[in] epwm The pointer of the specified EPWM module
* @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
* @return Return the period of specified channel. Valid values are between 0~0xFFFF
* @details This macro is used to get the period of specified channel.
* \hideinitializer
*/
#define EPWM_GET_CNR(epwm, u32ChannelNum) ((epwm)->PERIOD[(u32ChannelNum)])
/**
* @brief This macro set the EPWM aligned type
* @param[in] epwm The pointer of the specified EPWM module
* @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
* Bit 0 represents channel 0, bit 1 represents channel 1...
* @param[in] u32AlignedType EPWM aligned type, valid values are:
* - \ref EPWM_EDGE_ALIGNED
* - \ref EPWM_CENTER_ALIGNED
* @return None
* @details This macro is used to set the EPWM aligned type of specified channel(s).
* \hideinitializer
*/
#define EPWM_SET_ALIGNED_TYPE(epwm, u32ChannelMask, u32AlignedType) \
do{ \
int i; \
for(i = 0; i < 6; i++) { \
if((u32ChannelMask) & (1 << i)) \
(epwm)->CTL1 = (((epwm)->CTL1 & ~(3UL << (i << 1))) | ((u32AlignedType) << (i << 1))); \
} \
}while(0)
/**
* @brief Set load window of window loading mode for specified channel(s)
* @param[in] epwm The pointer of the specified EPWM module
* @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
* Bit 0 represents channel 0, bit 1 represents channel 1...
* @return None
* @details This macro is used to set load window of window loading mode for specified channel(s).
* \hideinitializer
*/
#define EPWM_SET_LOAD_WINDOW(epwm, u32ChannelMask) ((epwm)->LOAD |= (u32ChannelMask))
/**
* @brief Trigger synchronous event from specified channel(s)
* @param[in] epwm The pointer of the specified EPWM module
* @param[in] u32ChannelNum EPWM channel number. Valid values are 0, 2, 4
* Bit 0 represents channel 0, bit 1 represents channel 2 and bit 2 represents channel 4
* @return None
* @details This macro is used to trigger synchronous event from specified channel(s).
* \hideinitializer
*/
#define EPWM_TRIGGER_SYNC(epwm, u32ChannelNum) ((epwm)->SWSYNC |= (1 << ((u32ChannelNum) >> 1)))
/**
* @brief Clear counter of specified channel(s)
* @param[in] epwm The pointer of the specified EPWM module
* @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
* Bit 0 represents channel 0, bit 1 represents channel 1...
* @return None
* @details This macro is used to clear counter of specified channel(s).
* \hideinitializer
*/
#define EPWM_CLR_COUNTER(epwm, u32ChannelMask) ((epwm)->CNTCLR |= (u32ChannelMask))
/**
* @brief Set output level at zero, compare up, period(center) and compare down of specified channel(s)
* @param[in] epwm The pointer of the specified EPWM module
* @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
* Bit 0 represents channel 0, bit 1 represents channel 1...
* @param[in] u32ZeroLevel output level at zero point, valid values are:
* - \ref EPWM_OUTPUT_NOTHING
* - \ref EPWM_OUTPUT_LOW
* - \ref EPWM_OUTPUT_HIGH
* - \ref EPWM_OUTPUT_TOGGLE
* @param[in] u32CmpUpLevel output level at compare up point, valid values are:
* - \ref EPWM_OUTPUT_NOTHING
* - \ref EPWM_OUTPUT_LOW
* - \ref EPWM_OUTPUT_HIGH
* - \ref EPWM_OUTPUT_TOGGLE
* @param[in] u32PeriodLevel output level at period(center) point, valid values are:
* - \ref EPWM_OUTPUT_NOTHING
* - \ref EPWM_OUTPUT_LOW
* - \ref EPWM_OUTPUT_HIGH
* - \ref EPWM_OUTPUT_TOGGLE
* @param[in] u32CmpDownLevel output level at compare down point, valid values are:
* - \ref EPWM_OUTPUT_NOTHING
* - \ref EPWM_OUTPUT_LOW
* - \ref EPWM_OUTPUT_HIGH
* - \ref EPWM_OUTPUT_TOGGLE
* @return None
* @details This macro is used to Set output level at zero, compare up, period(center) and compare down of specified channel(s).
* \hideinitializer
*/
#define EPWM_SET_OUTPUT_LEVEL(epwm, u32ChannelMask, u32ZeroLevel, u32CmpUpLevel, u32PeriodLevel, u32CmpDownLevel) \
do{ \
int i; \
for(i = 0; i < 6; i++) { \
if((u32ChannelMask) & (1 << i)) { \
(epwm)->WGCTL0 = (((epwm)->WGCTL0 & ~(3UL << (i << 1))) | ((u32ZeroLevel) << (i << 1))); \
(epwm)->WGCTL0 = (((epwm)->WGCTL0 & ~(3UL << (EPWM_WGCTL0_PRDPCTL0_Pos + (i << 1)))) | ((u32PeriodLevel) << (EPWM_WGCTL0_PRDPCTL0_Pos + (i << 1)))); \
(epwm)->WGCTL1 = (((epwm)->WGCTL1 & ~(3UL << (i << 1))) | ((u32CmpUpLevel) << (i << 1))); \
(epwm)->WGCTL1 = (((epwm)->WGCTL1 & ~(3UL << (EPWM_WGCTL1_CMPDCTL0_Pos + (i << 1)))) | ((u32CmpDownLevel) << (EPWM_WGCTL1_CMPDCTL0_Pos + (i << 1)))); \
} \
} \
}while(0)
/**
* @brief Trigger brake event from specified channel(s)
* @param[in] epwm The pointer of the specified EPWM module
* @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
* Bit 0 represents channel 0, bit 1 represents channel 2 and bit 2 represents channel 4
* @param[in] u32BrakeType Type of brake trigger.
* - \ref EPWM_FB_EDGE
* - \ref EPWM_FB_LEVEL
* @return None
* @details This macro is used to trigger brake event from specified channel(s).
* \hideinitializer
*/
#define EPWM_TRIGGER_BRAKE(epwm, u32ChannelMask, u32BrakeType) ((epwm)->SWBRK |= ((u32ChannelMask) << (u32BrakeType)))
/**
* @brief Set Dead zone clock source
* @param[in] epwm The pointer of the specified EPWM module
* @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
* @param[in] u32AfterPrescaler Dead zone clock source is from prescaler output. Valid values are TRUE (after prescaler) or FALSE (before prescaler).
* @return None
* @details This macro is used to set Dead zone clock source. Every two channels share the same setting.
* @note The write-protection function should be disabled before using this function.
* \hideinitializer
*/
#define EPWM_SET_DEADZONE_CLK_SRC(epwm, u32ChannelNum, u32AfterPrescaler) \
((epwm)->DTCTL[(u32ChannelNum) >> 1] = (((epwm)->DTCTL[(u32ChannelNum) >> 1] & ~EPWM_DTCTL0_1_DTCKSEL_Msk) | \
((u32AfterPrescaler) << EPWM_DTCTL0_1_DTCKSEL_Pos)))
/*---------------------------------------------------------------------------------------------------------*/
/* Define EPWM functions prototype */
/*---------------------------------------------------------------------------------------------------------*/
uint32_t EPWM_ConfigCaptureChannel(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32UnitTimeNsec, uint32_t u32CaptureEdge);
uint32_t EPWM_ConfigOutputChannel(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Frequency, uint32_t u32DutyCycle);
void EPWM_Start(EPWM_T *epwm, uint32_t u32ChannelMask);
void EPWM_Stop(EPWM_T *epwm, uint32_t u32ChannelMask);
void EPWM_ForceStop(EPWM_T *epwm, uint32_t u32ChannelMask);
void EPWM_EnableADCTrigger(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Condition);
void EPWM_DisableADCTrigger(EPWM_T *epwm, uint32_t u32ChannelNum);
int32_t EPWM_EnableADCTriggerPrescale(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Prescale, uint32_t u32PrescaleCnt);
void EPWM_DisableADCTriggerPrescale(EPWM_T *epwm, uint32_t u32ChannelNum);
void EPWM_ClearADCTriggerFlag(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Condition);
uint32_t EPWM_GetADCTriggerFlag(EPWM_T *epwm, uint32_t u32ChannelNum);
void EPWM_EnableDACTrigger(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Condition);
void EPWM_DisableDACTrigger(EPWM_T *epwm, uint32_t u32ChannelNum);
void EPWM_ClearDACTriggerFlag(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Condition);
uint32_t EPWM_GetDACTriggerFlag(EPWM_T *epwm, uint32_t u32ChannelNum);
void EPWM_EnableFaultBrake(EPWM_T *epwm, uint32_t u32ChannelMask, uint32_t u32LevelMask, uint32_t u32BrakeSource);
void EPWM_EnableCapture(EPWM_T *epwm, uint32_t u32ChannelMask);
void EPWM_DisableCapture(EPWM_T *epwm, uint32_t u32ChannelMask);
void EPWM_EnableOutput(EPWM_T *epwm, uint32_t u32ChannelMask);
void EPWM_DisableOutput(EPWM_T *epwm, uint32_t u32ChannelMask);
void EPWM_EnablePDMA(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32RisingFirst, uint32_t u32Mode);
void EPWM_DisablePDMA(EPWM_T *epwm, uint32_t u32ChannelNum);
void EPWM_EnableDeadZone(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Duration);
void EPWM_DisableDeadZone(EPWM_T *epwm, uint32_t u32ChannelNum);
void EPWM_EnableCaptureInt(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Edge);
void EPWM_DisableCaptureInt(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Edge);
void EPWM_ClearCaptureIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Edge);
uint32_t EPWM_GetCaptureIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum);
void EPWM_EnableDutyInt(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32IntDutyType);
void EPWM_DisableDutyInt(EPWM_T *epwm, uint32_t u32ChannelNum);
void EPWM_ClearDutyIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum);
uint32_t EPWM_GetDutyIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum);
void EPWM_EnableFaultBrakeInt(EPWM_T *epwm, uint32_t u32BrakeSource);
void EPWM_DisableFaultBrakeInt(EPWM_T *epwm, uint32_t u32BrakeSource);
void EPWM_ClearFaultBrakeIntFlag(EPWM_T *epwm, uint32_t u32BrakeSource);
uint32_t EPWM_GetFaultBrakeIntFlag(EPWM_T *epwm, uint32_t u32BrakeSource);
void EPWM_EnablePeriodInt(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32IntPeriodType);
void EPWM_DisablePeriodInt(EPWM_T *epwm, uint32_t u32ChannelNum);
void EPWM_ClearPeriodIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum);
uint32_t EPWM_GetPeriodIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum);
void EPWM_EnableZeroInt(EPWM_T *epwm, uint32_t u32ChannelNum);
void EPWM_DisableZeroInt(EPWM_T *epwm, uint32_t u32ChannelNum);
void EPWM_ClearZeroIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum);
uint32_t EPWM_GetZeroIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum);
void EPWM_EnableAcc(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32IntFlagCnt, uint32_t u32IntAccSrc);
void EPWM_DisableAcc(EPWM_T *epwm, uint32_t u32ChannelNum);
void EPWM_EnableAccInt(EPWM_T *epwm, uint32_t u32ChannelNum);
void EPWM_DisableAccInt(EPWM_T *epwm, uint32_t u32ChannelNum);
void EPWM_ClearAccInt(EPWM_T *epwm, uint32_t u32ChannelNum);
uint32_t EPWM_GetAccInt(EPWM_T *epwm, uint32_t u32ChannelNum);
void EPWM_EnableAccPDMA(EPWM_T *epwm, uint32_t u32ChannelNum);
void EPWM_DisableAccPDMA(EPWM_T *epwm, uint32_t u32ChannelNum);
void EPWM_EnableAccStopMode(EPWM_T *epwm, uint32_t u32ChannelNum);
void EPWM_DisableAccStopMode(EPWM_T *epwm, uint32_t u32ChannelNum);
void EPWM_ClearFTDutyIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum);
uint32_t EPWM_GetFTDutyIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum);
void EPWM_EnableLoadMode(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32LoadMode);
void EPWM_DisableLoadMode(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32LoadMode);
void EPWM_ConfigSyncPhase(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32SyncSrc, uint32_t u32Direction, uint32_t u32StartPhase);
void EPWM_EnableSyncPhase(EPWM_T *epwm, uint32_t u32ChannelMask);
void EPWM_DisableSyncPhase(EPWM_T *epwm, uint32_t u32ChannelMask);
void EPWM_EnableSyncNoiseFilter(EPWM_T *epwm, uint32_t u32ClkCnt, uint32_t u32ClkDivSel);
void EPWM_DisableSyncNoiseFilter(EPWM_T *epwm);
void EPWM_EnableSyncPinInverse(EPWM_T *epwm);
void EPWM_DisableSyncPinInverse(EPWM_T *epwm);
void EPWM_SetClockSource(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32ClkSrcSel);
void EPWM_EnableBrakeNoiseFilter(EPWM_T *epwm, uint32_t u32BrakePinNum, uint32_t u32ClkCnt, uint32_t u32ClkDivSel);
void EPWM_DisableBrakeNoiseFilter(EPWM_T *epwm, uint32_t u32BrakePinNum);
void EPWM_EnableBrakePinInverse(EPWM_T *epwm, uint32_t u32BrakePinNum);
void EPWM_DisableBrakePinInverse(EPWM_T *epwm, uint32_t u32BrakePinNum);
void EPWM_SetBrakePinSource(EPWM_T *epwm, uint32_t u32BrakePinNum, uint32_t u32SelAnotherModule);
void EPWM_SetLeadingEdgeBlanking(EPWM_T *epwm, uint32_t u32TrigSrcSel, uint32_t u32TrigType, uint32_t u32BlankingCnt, uint32_t u32BlankingEnable);
uint32_t EPWM_GetWrapAroundFlag(EPWM_T *epwm, uint32_t u32ChannelNum);
void EPWM_ClearWrapAroundFlag(EPWM_T *epwm, uint32_t u32ChannelNum);
void EPWM_EnableFaultDetect(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32AfterPrescaler, uint32_t u32ClkSel);
void EPWM_DisableFaultDetect(EPWM_T *epwm, uint32_t u32ChannelNum);
void EPWM_EnableFaultDetectOutput(EPWM_T *epwm, uint32_t u32ChannelNum);
void EPWM_DisableFaultDetectOutput(EPWM_T *epwm, uint32_t u32ChannelNum);
void EPWM_EnableFaultDetectDeglitch(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32DeglitchSmpCycle);
void EPWM_DisableFaultDetectDeglitch(EPWM_T *epwm, uint32_t u32ChannelNum);
void EPWM_EnableFaultDetectMask(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32MaskCnt);
void EPWM_DisableFaultDetectMask(EPWM_T *epwm, uint32_t u32ChannelNum);
void EPWM_EnableFaultDetectInt(EPWM_T *epwm, uint32_t u32ChannelNum);
void EPWM_DisableFaultDetectInt(EPWM_T *epwm, uint32_t u32ChannelNum);
void EPWM_ClearFaultDetectInt(EPWM_T *epwm, uint32_t u32ChannelNum);
uint32_t EPWM_GetFaultDetectInt(EPWM_T *epwm, uint32_t u32ChannelNum);
/*@}*/ /* end of group EPWM_EXPORTED_FUNCTIONS */
/*@}*/ /* end of group EPWM_Driver */
/*@}*/ /* end of group Standard_Driver */
#ifdef __cplusplus
}
#endif
#endif /* __NU_EPWM_H__ */

600
bsp/nuvoton/libraries/ma35/StdDriver/inc/nu_gpio.h Normal file
View File

@ -0,0 +1,600 @@
/**************************************************************************//**
* @file GPIO.h
* @brief GPIO driver header file
*
* SPDX-License-Identifier: Apache-2.0
* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
******************************************************************************/
#ifndef __NU_GPIO_H__
#define __NU_GPIO_H__
#ifdef __cplusplus
extern "C"
{
#endif
/** @addtogroup Standard_Driver Standard Driver
@{
*/
/** @addtogroup GPIO_Driver GPIO Driver
@{
*/
/** @addtogroup GPIO_EXPORTED_CONSTANTS GPIO Exported Constants
@{
*/
#define GPIO_PIN_MAX 16UL /*!< Specify Maximum Pins of Each GPIO Port \hideinitializer */
/*---------------------------------------------------------------------------------------------------------*/
/* GPIO_MODE Constant Definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define GPIO_MODE_INPUT 0x0UL /*!< Input Mode \hideinitializer */
#define GPIO_MODE_OUTPUT 0x1UL /*!< Output Mode \hideinitializer */
#define GPIO_MODE_OPEN_DRAIN 0x2UL /*!< Open-Drain Mode \hideinitializer */
#define GPIO_MODE_QUASI 0x3UL /*!< Quasi-bidirectional Mode \hideinitializer */
/*---------------------------------------------------------------------------------------------------------*/
/* GPIO Interrupt Type Constant Definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define GPIO_INT_RISING 0x00010000UL /*!< Interrupt enable by Input Rising Edge \hideinitializer */
#define GPIO_INT_FALLING 0x00000001UL /*!< Interrupt enable by Input Falling Edge \hideinitializer */
#define GPIO_INT_BOTH_EDGE 0x00010001UL /*!< Interrupt enable by both Rising Edge and Falling Edge \hideinitializer */
#define GPIO_INT_HIGH 0x01010000UL /*!< Interrupt enable by Level-High \hideinitializer */
#define GPIO_INT_LOW 0x01000001UL /*!< Interrupt enable by Level-Level \hideinitializer */
/*---------------------------------------------------------------------------------------------------------*/
/* GPIO_INTTYPE Constant Definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define GPIO_INTTYPE_EDGE 0UL /*!< GPIO_INTTYPE Setting for Edge Trigger Mode \hideinitializer */
#define GPIO_INTTYPE_LEVEL 1UL /*!< GPIO_INTTYPE Setting for Edge Level Mode \hideinitializer */
/*---------------------------------------------------------------------------------------------------------*/
/* GPIO Slew Rate Type Constant Definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define GPIO_SLEWCTL_NORMAL 0x0UL /*!< GPIO slew setting for normal Mode \hideinitializer */
#define GPIO_SLEWCTL_HIGH 0x1UL /*!< GPIO slew setting for high Mode \hideinitializer */
#define GPIO_SLEWCTL_FAST 0x2UL /*!< GPIO slew setting for fast Mode \hideinitializer */
/*---------------------------------------------------------------------------------------------------------*/
/* GPIO Pull-up And Pull-down Type Constant Definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define GPIO_PUSEL_DISABLE 0x0UL /*!< GPIO PUSEL setting for Disable Mode \hideinitializer */
#define GPIO_PUSEL_PULL_UP 0x1UL /*!< GPIO PUSEL setting for Pull-up Mode \hideinitializer */
#define GPIO_PUSEL_PULL_DOWN 0x2UL /*!< GPIO PUSEL setting for Pull-down Mode \hideinitializer */
/*---------------------------------------------------------------------------------------------------------*/
/* GPIO_DBCTL Constant Definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define GPIO_DBCTL_ICLK_ON 0x00000020UL /*!< GPIO_DBCTL setting for all IO pins edge detection circuit is always active after reset \hideinitializer */
#define GPIO_DBCTL_ICLK_OFF 0x00000000UL /*!< GPIO_DBCTL setting for edge detection circuit is active only if IO pin corresponding GPIOx_IEN bit is set to 1 \hideinitializer */
#define GPIO_DBCTL_DBCLKSRC_LIRC 0x00000010UL /*!< GPIO_DBCTL setting for de-bounce counter clock source is the internal 10 kHz \hideinitializer */
#define GPIO_DBCTL_DBCLKSRC_HXT 0x00000000UL /*!< GPIO_DBCTL setting for de-bounce counter clock source is the HCLK \hideinitializer */
#define GPIO_DBCTL_DBCLKSEL_1 0x00000000UL /*!< GPIO_DBCTL setting for sampling cycle = 1 clocks \hideinitializer */
#define GPIO_DBCTL_DBCLKSEL_2 0x00000001UL /*!< GPIO_DBCTL setting for sampling cycle = 2 clocks \hideinitializer */
#define GPIO_DBCTL_DBCLKSEL_4 0x00000002UL /*!< GPIO_DBCTL setting for sampling cycle = 4 clocks \hideinitializer */
#define GPIO_DBCTL_DBCLKSEL_8 0x00000003UL /*!< GPIO_DBCTL setting for sampling cycle = 8 clocks \hideinitializer */
#define GPIO_DBCTL_DBCLKSEL_16 0x00000004UL /*!< GPIO_DBCTL setting for sampling cycle = 16 clocks \hideinitializer */
#define GPIO_DBCTL_DBCLKSEL_32 0x00000005UL /*!< GPIO_DBCTL setting for sampling cycle = 32 clocks \hideinitializer */
#define GPIO_DBCTL_DBCLKSEL_64 0x00000006UL /*!< GPIO_DBCTL setting for sampling cycle = 64 clocks \hideinitializer */
#define GPIO_DBCTL_DBCLKSEL_128 0x00000007UL /*!< GPIO_DBCTL setting for sampling cycle = 128 clocks \hideinitializer */
#define GPIO_DBCTL_DBCLKSEL_256 0x00000008UL /*!< GPIO_DBCTL setting for sampling cycle = 256 clocks \hideinitializer */
#define GPIO_DBCTL_DBCLKSEL_512 0x00000009UL /*!< GPIO_DBCTL setting for sampling cycle = 512 clocks \hideinitializer */
#define GPIO_DBCTL_DBCLKSEL_1024 0x0000000AUL /*!< GPIO_DBCTL setting for sampling cycle = 1024 clocks \hideinitializer */
#define GPIO_DBCTL_DBCLKSEL_2048 0x0000000BUL /*!< GPIO_DBCTL setting for sampling cycle = 2048 clocks \hideinitializer */
#define GPIO_DBCTL_DBCLKSEL_4096 0x0000000CUL /*!< GPIO_DBCTL setting for sampling cycle = 4096 clocks \hideinitializer */
#define GPIO_DBCTL_DBCLKSEL_8192 0x0000000DUL /*!< GPIO_DBCTL setting for sampling cycle = 8192 clocks \hideinitializer */
#define GPIO_DBCTL_DBCLKSEL_16384 0x0000000EUL /*!< GPIO_DBCTL setting for sampling cycle = 16384 clocks \hideinitializer */
#define GPIO_DBCTL_DBCLKSEL_32768 0x0000000FUL /*!< GPIO_DBCTL setting for sampling cycle = 32768 clocks \hideinitializer */
/* Define GPIO Pin Data Input/Output. It could be used to control each I/O pin by pin address mapping.
Example 1:
PA0 = 1;
It is used to set GPIO PA.0 to high;
Example 2:
if (PA0)
PA0 = 0;
If GPIO PA.0 pin status is high, then set GPIO PA.0 data output to low.
*/
#define GPIO_PIN_DATA(port, pin) (*((volatile uint32_t *)((GPIO_PIN_DATA_BASE+(0x40*(port))) + ((pin)<<2)))) /*!< Pin Data Input/Output \hideinitializer */
#define PA0 GPIO_PIN_DATA(0, 0 ) /*!< Specify PA.0 Pin Data Input/Output \hideinitializer */
#define PA1 GPIO_PIN_DATA(0, 1 ) /*!< Specify PA.1 Pin Data Input/Output \hideinitializer */
#define PA2 GPIO_PIN_DATA(0, 2 ) /*!< Specify PA.2 Pin Data Input/Output \hideinitializer */
#define PA3 GPIO_PIN_DATA(0, 3 ) /*!< Specify PA.3 Pin Data Input/Output \hideinitializer */
#define PA4 GPIO_PIN_DATA(0, 4 ) /*!< Specify PA.4 Pin Data Input/Output \hideinitializer */
#define PA5 GPIO_PIN_DATA(0, 5 ) /*!< Specify PA.5 Pin Data Input/Output \hideinitializer */
#define PA6 GPIO_PIN_DATA(0, 6 ) /*!< Specify PA.6 Pin Data Input/Output \hideinitializer */
#define PA7 GPIO_PIN_DATA(0, 7 ) /*!< Specify PA.7 Pin Data Input/Output \hideinitializer */
#define PA8 GPIO_PIN_DATA(0, 8 ) /*!< Specify PA.8 Pin Data Input/Output \hideinitializer */
#define PA9 GPIO_PIN_DATA(0, 9 ) /*!< Specify PA.9 Pin Data Input/Output \hideinitializer */
#define PA10 GPIO_PIN_DATA(0, 10) /*!< Specify PA.10 Pin Data Input/Output \hideinitializer */
#define PA11 GPIO_PIN_DATA(0, 11) /*!< Specify PA.11 Pin Data Input/Output \hideinitializer */
#define PA12 GPIO_PIN_DATA(0, 12) /*!< Specify PA.12 Pin Data Input/Output \hideinitializer */
#define PA13 GPIO_PIN_DATA(0, 13) /*!< Specify PA.13 Pin Data Input/Output \hideinitializer */
#define PA14 GPIO_PIN_DATA(0, 14) /*!< Specify PA.14 Pin Data Input/Output \hideinitializer */
#define PA15 GPIO_PIN_DATA(0, 15) /*!< Specify PA.15 Pin Data Input/Output \hideinitializer */
#define PB0 GPIO_PIN_DATA(1, 0 ) /*!< Specify PB.0 Pin Data Input/Output \hideinitializer */
#define PB1 GPIO_PIN_DATA(1, 1 ) /*!< Specify PB.1 Pin Data Input/Output \hideinitializer */
#define PB2 GPIO_PIN_DATA(1, 2 ) /*!< Specify PB.2 Pin Data Input/Output \hideinitializer */
#define PB3 GPIO_PIN_DATA(1, 3 ) /*!< Specify PB.3 Pin Data Input/Output \hideinitializer */
#define PB4 GPIO_PIN_DATA(1, 4 ) /*!< Specify PB.4 Pin Data Input/Output \hideinitializer */
#define PB5 GPIO_PIN_DATA(1, 5 ) /*!< Specify PB.5 Pin Data Input/Output \hideinitializer */
#define PB6 GPIO_PIN_DATA(1, 6 ) /*!< Specify PB.6 Pin Data Input/Output \hideinitializer */
#define PB7 GPIO_PIN_DATA(1, 7 ) /*!< Specify PB.7 Pin Data Input/Output \hideinitializer */
#define PB8 GPIO_PIN_DATA(1, 8 ) /*!< Specify PB.8 Pin Data Input/Output \hideinitializer */
#define PB9 GPIO_PIN_DATA(1, 9 ) /*!< Specify PB.9 Pin Data Input/Output \hideinitializer */
#define PB10 GPIO_PIN_DATA(1, 10) /*!< Specify PB.10 Pin Data Input/Output \hideinitializer */
#define PB11 GPIO_PIN_DATA(1, 11) /*!< Specify PB.11 Pin Data Input/Output \hideinitializer */
#define PB12 GPIO_PIN_DATA(1, 12) /*!< Specify PB.12 Pin Data Input/Output \hideinitializer */
#define PB13 GPIO_PIN_DATA(1, 13) /*!< Specify PB.13 Pin Data Input/Output \hideinitializer */
#define PB14 GPIO_PIN_DATA(1, 14) /*!< Specify PB.14 Pin Data Input/Output \hideinitializer */
#define PB15 GPIO_PIN_DATA(1, 15) /*!< Specify PB.15 Pin Data Input/Output \hideinitializer */
#define PC0 GPIO_PIN_DATA(2, 0 ) /*!< Specify PC.0 Pin Data Input/Output \hideinitializer */
#define PC1 GPIO_PIN_DATA(2, 1 ) /*!< Specify PC.1 Pin Data Input/Output \hideinitializer */
#define PC2 GPIO_PIN_DATA(2, 2 ) /*!< Specify PC.2 Pin Data Input/Output \hideinitializer */
#define PC3 GPIO_PIN_DATA(2, 3 ) /*!< Specify PC.3 Pin Data Input/Output \hideinitializer */
#define PC4 GPIO_PIN_DATA(2, 4 ) /*!< Specify PC.4 Pin Data Input/Output \hideinitializer */
#define PC5 GPIO_PIN_DATA(2, 5 ) /*!< Specify PC.5 Pin Data Input/Output \hideinitializer */
#define PC6 GPIO_PIN_DATA(2, 6 ) /*!< Specify PC.6 Pin Data Input/Output \hideinitializer */
#define PC7 GPIO_PIN_DATA(2, 7 ) /*!< Specify PC.7 Pin Data Input/Output \hideinitializer */
#define PC8 GPIO_PIN_DATA(2, 8 ) /*!< Specify PC.8 Pin Data Input/Output \hideinitializer */
#define PC9 GPIO_PIN_DATA(2, 9 ) /*!< Specify PC.9 Pin Data Input/Output \hideinitializer */
#define PC10 GPIO_PIN_DATA(2, 10) /*!< Specify PC.10 Pin Data Input/Output \hideinitializer */
#define PC11 GPIO_PIN_DATA(2, 11) /*!< Specify PC.11 Pin Data Input/Output \hideinitializer */
#define PC12 GPIO_PIN_DATA(2, 12) /*!< Specify PC.12 Pin Data Input/Output \hideinitializer */
#define PC13 GPIO_PIN_DATA(2, 13) /*!< Specify PC.13 Pin Data Input/Output \hideinitializer */
#define PC14 GPIO_PIN_DATA(2, 14) /*!< Specify PC.14 Pin Data Input/Output \hideinitializer */
#define PD0 GPIO_PIN_DATA(3, 0 ) /*!< Specify PD.0 Pin Data Input/Output \hideinitializer */
#define PD1 GPIO_PIN_DATA(3, 1 ) /*!< Specify PD.1 Pin Data Input/Output \hideinitializer */
#define PD2 GPIO_PIN_DATA(3, 2 ) /*!< Specify PD.2 Pin Data Input/Output \hideinitializer */
#define PD3 GPIO_PIN_DATA(3, 3 ) /*!< Specify PD.3 Pin Data Input/Output \hideinitializer */
#define PD4 GPIO_PIN_DATA(3, 4 ) /*!< Specify PD.4 Pin Data Input/Output \hideinitializer */
#define PD5 GPIO_PIN_DATA(3, 5 ) /*!< Specify PD.5 Pin Data Input/Output \hideinitializer */
#define PD6 GPIO_PIN_DATA(3, 6 ) /*!< Specify PD.6 Pin Data Input/Output \hideinitializer */
#define PD7 GPIO_PIN_DATA(3, 7 ) /*!< Specify PD.7 Pin Data Input/Output \hideinitializer */
#define PD8 GPIO_PIN_DATA(3, 8 ) /*!< Specify PD.8 Pin Data Input/Output \hideinitializer */
#define PD9 GPIO_PIN_DATA(3, 9 ) /*!< Specify PD.9 Pin Data Input/Output \hideinitializer */
#define PD10 GPIO_PIN_DATA(3, 10) /*!< Specify PD.10 Pin Data Input/Output \hideinitializer */
#define PD11 GPIO_PIN_DATA(3, 11) /*!< Specify PD.11 Pin Data Input/Output \hideinitializer */
#define PD12 GPIO_PIN_DATA(3, 12) /*!< Specify PD.12 Pin Data Input/Output \hideinitializer */
#define PD13 GPIO_PIN_DATA(3, 13) /*!< Specify PD.13 Pin Data Input/Output \hideinitializer */
#define PD14 GPIO_PIN_DATA(3, 14) /*!< Specify PD.14 Pin Data Input/Output \hideinitializer */
#define PE0 GPIO_PIN_DATA(4, 0 ) /*!< Specify PE.0 Pin Data Input/Output \hideinitializer */
#define PE1 GPIO_PIN_DATA(4, 1 ) /*!< Specify PE.1 Pin Data Input/Output \hideinitializer */
#define PE2 GPIO_PIN_DATA(4, 2 ) /*!< Specify PE.2 Pin Data Input/Output \hideinitializer */
#define PE3 GPIO_PIN_DATA(4, 3 ) /*!< Specify PE.3 Pin Data Input/Output \hideinitializer */
#define PE4 GPIO_PIN_DATA(4, 4 ) /*!< Specify PE.4 Pin Data Input/Output \hideinitializer */
#define PE5 GPIO_PIN_DATA(4, 5 ) /*!< Specify PE.5 Pin Data Input/Output \hideinitializer */
#define PE6 GPIO_PIN_DATA(4, 6 ) /*!< Specify PE.6 Pin Data Input/Output \hideinitializer */
#define PE7 GPIO_PIN_DATA(4, 7 ) /*!< Specify PE.7 Pin Data Input/Output \hideinitializer */
#define PE8 GPIO_PIN_DATA(4, 8 ) /*!< Specify PE.8 Pin Data Input/Output \hideinitializer */
#define PE9 GPIO_PIN_DATA(4, 9 ) /*!< Specify PE.9 Pin Data Input/Output \hideinitializer */
#define PE10 GPIO_PIN_DATA(4, 10) /*!< Specify PE.10 Pin Data Input/Output \hideinitializer */
#define PE11 GPIO_PIN_DATA(4, 11) /*!< Specify PE.11 Pin Data Input/Output \hideinitializer */
#define PE12 GPIO_PIN_DATA(4, 12) /*!< Specify PE.12 Pin Data Input/Output \hideinitializer */
#define PE13 GPIO_PIN_DATA(4, 13) /*!< Specify PE.13 Pin Data Input/Output \hideinitializer */
#define PE14 GPIO_PIN_DATA(4, 14) /*!< Specify PE.14 Pin Data Input/Output \hideinitializer */
#define PE15 GPIO_PIN_DATA(4, 15) /*!< Specify PE.15 Pin Data Input/Output \hideinitializer */
#define PF0 GPIO_PIN_DATA(5, 0 ) /*!< Specify PF.0 Pin Data Input/Output \hideinitializer */
#define PF1 GPIO_PIN_DATA(5, 1 ) /*!< Specify PF.1 Pin Data Input/Output \hideinitializer */
#define PF2 GPIO_PIN_DATA(5, 2 ) /*!< Specify PF.2 Pin Data Input/Output \hideinitializer */
#define PF3 GPIO_PIN_DATA(5, 3 ) /*!< Specify PF.3 Pin Data Input/Output \hideinitializer */
#define PF4 GPIO_PIN_DATA(5, 4 ) /*!< Specify PF.4 Pin Data Input/Output \hideinitializer */
#define PF5 GPIO_PIN_DATA(5, 5 ) /*!< Specify PF.5 Pin Data Input/Output \hideinitializer */
#define PF6 GPIO_PIN_DATA(5, 6 ) /*!< Specify PF.6 Pin Data Input/Output \hideinitializer */
#define PF7 GPIO_PIN_DATA(5, 7 ) /*!< Specify PF.7 Pin Data Input/Output \hideinitializer */
#define PF8 GPIO_PIN_DATA(5, 8 ) /*!< Specify PF.8 Pin Data Input/Output \hideinitializer */
#define PF9 GPIO_PIN_DATA(5, 9 ) /*!< Specify PF.9 Pin Data Input/Output \hideinitializer */
#define PF10 GPIO_PIN_DATA(5, 10) /*!< Specify PF.10 Pin Data Input/Output \hideinitializer */
#define PF11 GPIO_PIN_DATA(5, 11) /*!< Specify PF.11 Pin Data Input/Output \hideinitializer */
#define PG0 GPIO_PIN_DATA(6, 0 ) /*!< Specify PG.0 Pin Data Input/Output \hideinitializer */
#define PG1 GPIO_PIN_DATA(6, 1 ) /*!< Specify PG.1 Pin Data Input/Output \hideinitializer */
#define PG2 GPIO_PIN_DATA(6, 2 ) /*!< Specify PG.2 Pin Data Input/Output \hideinitializer */
#define PG3 GPIO_PIN_DATA(6, 3 ) /*!< Specify PG.3 Pin Data Input/Output \hideinitializer */
#define PG4 GPIO_PIN_DATA(6, 4 ) /*!< Specify PG.4 Pin Data Input/Output \hideinitializer */
#define PG5 GPIO_PIN_DATA(6, 5 ) /*!< Specify PG.5 Pin Data Input/Output \hideinitializer */
#define PG6 GPIO_PIN_DATA(6, 6 ) /*!< Specify PG.6 Pin Data Input/Output \hideinitializer */
#define PG7 GPIO_PIN_DATA(6, 7 ) /*!< Specify PG.7 Pin Data Input/Output \hideinitializer */
#define PG8 GPIO_PIN_DATA(6, 8 ) /*!< Specify PG.8 Pin Data Input/Output \hideinitializer */
#define PG9 GPIO_PIN_DATA(6, 9 ) /*!< Specify PG.9 Pin Data Input/Output \hideinitializer */
#define PG10 GPIO_PIN_DATA(6, 10) /*!< Specify PG.10 Pin Data Input/Output \hideinitializer */
#define PG11 GPIO_PIN_DATA(6, 11) /*!< Specify PG.11 Pin Data Input/Output \hideinitializer */
#define PG12 GPIO_PIN_DATA(6, 12) /*!< Specify PG.12 Pin Data Input/Output \hideinitializer */
#define PG13 GPIO_PIN_DATA(6, 13) /*!< Specify PG.13 Pin Data Input/Output \hideinitializer */
#define PG14 GPIO_PIN_DATA(6, 14) /*!< Specify PG.14 Pin Data Input/Output \hideinitializer */
#define PG15 GPIO_PIN_DATA(6, 15) /*!< Specify PG.15 Pin Data Input/Output \hideinitializer */
#define PH0 GPIO_PIN_DATA(7, 0 ) /*!< Specify PH.0 Pin Data Input/Output \hideinitializer */
#define PH1 GPIO_PIN_DATA(7, 1 ) /*!< Specify PH.1 Pin Data Input/Output \hideinitializer */
#define PH2 GPIO_PIN_DATA(7, 2 ) /*!< Specify PH.2 Pin Data Input/Output \hideinitializer */
#define PH3 GPIO_PIN_DATA(7, 3 ) /*!< Specify PH.3 Pin Data Input/Output \hideinitializer */
#define PH4 GPIO_PIN_DATA(7, 4 ) /*!< Specify PH.4 Pin Data Input/Output \hideinitializer */
#define PH5 GPIO_PIN_DATA(7, 5 ) /*!< Specify PH.5 Pin Data Input/Output \hideinitializer */
#define PH6 GPIO_PIN_DATA(7, 6 ) /*!< Specify PH.6 Pin Data Input/Output \hideinitializer */
#define PH7 GPIO_PIN_DATA(7, 7 ) /*!< Specify PH.7 Pin Data Input/Output \hideinitializer */
#define PH8 GPIO_PIN_DATA(7, 8 ) /*!< Specify PH.8 Pin Data Input/Output \hideinitializer */
#define PH9 GPIO_PIN_DATA(7, 9 ) /*!< Specify PH.9 Pin Data Input/Output \hideinitializer */
#define PH10 GPIO_PIN_DATA(7, 10) /*!< Specify PH.10 Pin Data Input/Output \hideinitializer */
#define PH11 GPIO_PIN_DATA(7, 11) /*!< Specify PH.11 Pin Data Input/Output \hideinitializer */
#define PH12 GPIO_PIN_DATA(7, 12) /*!< Specify PH.12 Pin Data Input/Output \hideinitializer */
#define PH13 GPIO_PIN_DATA(7, 13) /*!< Specify PH.13 Pin Data Input/Output \hideinitializer */
#define PH14 GPIO_PIN_DATA(7, 14) /*!< Specify PH.14 Pin Data Input/Output \hideinitializer */
#define PH15 GPIO_PIN_DATA(7, 15) /*!< Specify PH.15 Pin Data Input/Output \hideinitializer */
#define PI0 GPIO_PIN_DATA(8, 0 ) /*!< Specify PI.0 Pin Data Input/Output \hideinitializer */
#define PI1 GPIO_PIN_DATA(8, 1 ) /*!< Specify PI.1 Pin Data Input/Output \hideinitializer */
#define PI2 GPIO_PIN_DATA(8, 2 ) /*!< Specify PI.2 Pin Data Input/Output \hideinitializer */
#define PI3 GPIO_PIN_DATA(8, 3 ) /*!< Specify PI.3 Pin Data Input/Output \hideinitializer */
#define PI4 GPIO_PIN_DATA(8, 4 ) /*!< Specify PI.4 Pin Data Input/Output \hideinitializer */
#define PI5 GPIO_PIN_DATA(8, 5 ) /*!< Specify PI.5 Pin Data Input/Output \hideinitializer */
#define PI6 GPIO_PIN_DATA(8, 6 ) /*!< Specify PI.6 Pin Data Input/Output \hideinitializer */
#define PI7 GPIO_PIN_DATA(8, 7 ) /*!< Specify PI.7 Pin Data Input/Output \hideinitializer */
#define PI8 GPIO_PIN_DATA(8, 8 ) /*!< Specify PI.8 Pin Data Input/Output \hideinitializer */
#define PI9 GPIO_PIN_DATA(8, 9 ) /*!< Specify PI.9 Pin Data Input/Output \hideinitializer */
#define PI10 GPIO_PIN_DATA(8, 10) /*!< Specify PI.10 Pin Data Input/Output \hideinitializer */
#define PI11 GPIO_PIN_DATA(8, 11) /*!< Specify PI.11 Pin Data Input/Output \hideinitializer */
#define PI12 GPIO_PIN_DATA(8, 12) /*!< Specify PI.12 Pin Data Input/Output \hideinitializer */
#define PI13 GPIO_PIN_DATA(8, 13) /*!< Specify PI.13 Pin Data Input/Output \hideinitializer */
#define PI14 GPIO_PIN_DATA(8, 14) /*!< Specify PI.14 Pin Data Input/Output \hideinitializer */
#define PI15 GPIO_PIN_DATA(8, 15) /*!< Specify PI.15 Pin Data Input/Output \hideinitializer */
#define PJ0 GPIO_PIN_DATA(9, 0 ) /*!< Specify PJ.0 Pin Data Input/Output \hideinitializer */
#define PJ1 GPIO_PIN_DATA(9, 1 ) /*!< Specify PJ.1 Pin Data Input/Output \hideinitializer */
#define PJ2 GPIO_PIN_DATA(9, 2 ) /*!< Specify PJ.2 Pin Data Input/Output \hideinitializer */
#define PJ3 GPIO_PIN_DATA(9, 3 ) /*!< Specify PJ.3 Pin Data Input/Output \hideinitializer */
#define PJ4 GPIO_PIN_DATA(9, 4 ) /*!< Specify PJ.4 Pin Data Input/Output \hideinitializer */
#define PJ5 GPIO_PIN_DATA(9, 5 ) /*!< Specify PJ.5 Pin Data Input/Output \hideinitializer */
#define PJ6 GPIO_PIN_DATA(9, 6 ) /*!< Specify PJ.6 Pin Data Input/Output \hideinitializer */
#define PJ7 GPIO_PIN_DATA(9, 7 ) /*!< Specify PJ.7 Pin Data Input/Output \hideinitializer */
#define PJ8 GPIO_PIN_DATA(9, 8 ) /*!< Specify PJ.8 Pin Data Input/Output \hideinitializer */
#define PJ9 GPIO_PIN_DATA(9, 9 ) /*!< Specify PJ.9 Pin Data Input/Output \hideinitializer */
#define PJ10 GPIO_PIN_DATA(9, 10) /*!< Specify PJ.10 Pin Data Input/Output \hideinitializer */
#define PJ11 GPIO_PIN_DATA(9, 11) /*!< Specify PJ.11 Pin Data Input/Output \hideinitializer */
#define PJ12 GPIO_PIN_DATA(9, 12) /*!< Specify PJ.12 Pin Data Input/Output \hideinitializer */
#define PJ13 GPIO_PIN_DATA(9, 13) /*!< Specify PJ.13 Pin Data Input/Output \hideinitializer */
#define PJ14 GPIO_PIN_DATA(9, 14) /*!< Specify PJ.14 Pin Data Input/Output \hideinitializer */
#define PJ15 GPIO_PIN_DATA(9, 15) /*!< Specify PJ.15 Pin Data Input/Output \hideinitializer */
#define PK0 GPIO_PIN_DATA(10 , 0 ) /*!< Specify PK.0 Pin Data Input/Output \hideinitializer */
#define PK1 GPIO_PIN_DATA(10 , 1 ) /*!< Specify PK.1 Pin Data Input/Output \hideinitializer */
#define PK2 GPIO_PIN_DATA(10 , 2 ) /*!< Specify PK.2 Pin Data Input/Output \hideinitializer */
#define PK3 GPIO_PIN_DATA(10 , 3 ) /*!< Specify PK.3 Pin Data Input/Output \hideinitializer */
#define PK4 GPIO_PIN_DATA(10 , 4 ) /*!< Specify PK.4 Pin Data Input/Output \hideinitializer */
#define PK5 GPIO_PIN_DATA(10 , 5 ) /*!< Specify PK.5 Pin Data Input/Output \hideinitializer */
#define PK6 GPIO_PIN_DATA(10 , 6 ) /*!< Specify PK.6 Pin Data Input/Output \hideinitializer */
#define PK7 GPIO_PIN_DATA(10 , 7 ) /*!< Specify PK.7 Pin Data Input/Output \hideinitializer */
#define PK8 GPIO_PIN_DATA(10 , 8 ) /*!< Specify PK.8 Pin Data Input/Output \hideinitializer */
#define PK9 GPIO_PIN_DATA(10 , 9 ) /*!< Specify PK.9 Pin Data Input/Output \hideinitializer */
#define PK10 GPIO_PIN_DATA(10 , 10) /*!< Specify PK.10 Pin Data Input/Output \hideinitializer */
#define PK11 GPIO_PIN_DATA(10 , 11) /*!< Specify PK.11 Pin Data Input/Output \hideinitializer */
#define PK12 GPIO_PIN_DATA(10 , 12) /*!< Specify PK.12 Pin Data Input/Output \hideinitializer */
#define PK13 GPIO_PIN_DATA(10 , 13) /*!< Specify PK.13 Pin Data Input/Output \hideinitializer */
#define PK14 GPIO_PIN_DATA(10 , 14) /*!< Specify PK.14 Pin Data Input/Output \hideinitializer */
#define PK15 GPIO_PIN_DATA(10 , 15) /*!< Specify PK.15 Pin Data Input/Output \hideinitializer */
#define PL0 GPIO_PIN_DATA(11, 0 ) /*!< Specify PL.0 Pin Data Input/Output \hideinitializer */
#define PL1 GPIO_PIN_DATA(11, 1 ) /*!< Specify PL.1 Pin Data Input/Output \hideinitializer */
#define PL2 GPIO_PIN_DATA(11, 2 ) /*!< Specify PL.2 Pin Data Input/Output \hideinitializer */
#define PL3 GPIO_PIN_DATA(11, 3 ) /*!< Specify PL.3 Pin Data Input/Output \hideinitializer */
#define PL4 GPIO_PIN_DATA(11, 4 ) /*!< Specify PL.4 Pin Data Input/Output \hideinitializer */
#define PL5 GPIO_PIN_DATA(11, 5 ) /*!< Specify PL.5 Pin Data Input/Output \hideinitializer */
#define PL6 GPIO_PIN_DATA(11, 6 ) /*!< Specify PL.6 Pin Data Input/Output \hideinitializer */
#define PL7 GPIO_PIN_DATA(11, 7 ) /*!< Specify PL.7 Pin Data Input/Output \hideinitializer */
#define PL8 GPIO_PIN_DATA(11, 8 ) /*!< Specify PL.8 Pin Data Input/Output \hideinitializer */
#define PL9 GPIO_PIN_DATA(11, 9 ) /*!< Specify PL.9 Pin Data Input/Output \hideinitializer */
#define PL10 GPIO_PIN_DATA(11, 10) /*!< Specify PL.10 Pin Data Input/Output \hideinitializer */
#define PL11 GPIO_PIN_DATA(11, 11) /*!< Specify PL.11 Pin Data Input/Output \hideinitializer */
#define PL12 GPIO_PIN_DATA(11, 12) /*!< Specify PL.12 Pin Data Input/Output \hideinitializer */
#define PL13 GPIO_PIN_DATA(11, 13) /*!< Specify PL.13 Pin Data Input/Output \hideinitializer */
#define PL14 GPIO_PIN_DATA(11, 14) /*!< Specify PL.14 Pin Data Input/Output \hideinitializer */
#define PL15 GPIO_PIN_DATA(11, 15) /*!< Specify PL.15 Pin Data Input/Output \hideinitializer */
#define PM0 GPIO_PIN_DATA(12, 0 ) /*!< Specify PH.0 Pin Data Input/Output \hideinitializer */
#define PM1 GPIO_PIN_DATA(12, 1 ) /*!< Specify PH.1 Pin Data Input/Output \hideinitializer */
#define PM2 GPIO_PIN_DATA(12, 2 ) /*!< Specify PH.2 Pin Data Input/Output \hideinitializer */
#define PM3 GPIO_PIN_DATA(12, 3 ) /*!< Specify PH.3 Pin Data Input/Output \hideinitializer */
#define PM4 GPIO_PIN_DATA(12, 4 ) /*!< Specify PH.4 Pin Data Input/Output \hideinitializer */
#define PM5 GPIO_PIN_DATA(12, 5 ) /*!< Specify PH.5 Pin Data Input/Output \hideinitializer */
#define PM6 GPIO_PIN_DATA(12, 6 ) /*!< Specify PH.6 Pin Data Input/Output \hideinitializer */
#define PM7 GPIO_PIN_DATA(12, 7 ) /*!< Specify PH.7 Pin Data Input/Output \hideinitializer */
#define PM8 GPIO_PIN_DATA(12, 8 ) /*!< Specify PH.8 Pin Data Input/Output \hideinitializer */
#define PM9 GPIO_PIN_DATA(12, 9 ) /*!< Specify PH.9 Pin Data Input/Output \hideinitializer */
#define PM10 GPIO_PIN_DATA(12, 10) /*!< Specify PH.10 Pin Data Input/Output \hideinitializer */
#define PM11 GPIO_PIN_DATA(12, 11) /*!< Specify PH.11 Pin Data Input/Output \hideinitializer */
#define PM12 GPIO_PIN_DATA(12, 12) /*!< Specify PH.12 Pin Data Input/Output \hideinitializer */
#define PM13 GPIO_PIN_DATA(12, 13) /*!< Specify PH.13 Pin Data Input/Output \hideinitializer */
#define PM14 GPIO_PIN_DATA(12, 14) /*!< Specify PH.14 Pin Data Input/Output \hideinitializer */
#define PM15 GPIO_PIN_DATA(12, 15) /*!< Specify PH.15 Pin Data Input/Output \hideinitializer */
#define PN0 GPIO_PIN_DATA(13, 0 ) /*!< Specify PH.0 Pin Data Input/Output \hideinitializer */
#define PN1 GPIO_PIN_DATA(13, 1 ) /*!< Specify PH.1 Pin Data Input/Output \hideinitializer */
#define PN2 GPIO_PIN_DATA(13, 2 ) /*!< Specify PH.2 Pin Data Input/Output \hideinitializer */
#define PN3 GPIO_PIN_DATA(13, 3 ) /*!< Specify PH.3 Pin Data Input/Output \hideinitializer */
#define PN4 GPIO_PIN_DATA(13, 4 ) /*!< Specify PH.4 Pin Data Input/Output \hideinitializer */
#define PN5 GPIO_PIN_DATA(13, 5 ) /*!< Specify PH.5 Pin Data Input/Output \hideinitializer */
#define PN6 GPIO_PIN_DATA(13, 6 ) /*!< Specify PH.6 Pin Data Input/Output \hideinitializer */
#define PN7 GPIO_PIN_DATA(13, 7 ) /*!< Specify PH.7 Pin Data Input/Output \hideinitializer */
#define PN8 GPIO_PIN_DATA(13, 8 ) /*!< Specify PH.8 Pin Data Input/Output \hideinitializer */
#define PN9 GPIO_PIN_DATA(13, 9 ) /*!< Specify PH.9 Pin Data Input/Output \hideinitializer */
#define PN10 GPIO_PIN_DATA(13, 10) /*!< Specify PH.10 Pin Data Input/Output \hideinitializer */
#define PN11 GPIO_PIN_DATA(13, 11) /*!< Specify PH.11 Pin Data Input/Output \hideinitializer */
#define PN12 GPIO_PIN_DATA(13, 12) /*!< Specify PH.12 Pin Data Input/Output \hideinitializer */
#define PN13 GPIO_PIN_DATA(13, 13) /*!< Specify PH.13 Pin Data Input/Output \hideinitializer */
#define PN14 GPIO_PIN_DATA(13, 14) /*!< Specify PH.14 Pin Data Input/Output \hideinitializer */
#define PN15 GPIO_PIN_DATA(13, 15) /*!< Specify PH.15 Pin Data Input/Output \hideinitializer */
/*@}*/ /* end of group GPIO_EXPORTED_CONSTANTS */
/** @addtogroup GPIO_EXPORTED_FUNCTIONS GPIO Exported Functions
@{
*/
/**
* @brief Clear GPIO Pin Interrupt Flag
*
* @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF, PG, PH, PI, PJ, PK,PL, PM and PN.
* @param[in] u32PinMask The single or multiple pins of specified GPIO port.
* It could be BIT0 ~ BIT15 for PA, PB, PC, PD, PF and PH GPIO port.
* It could be BIT0 ~ BIT13 for PE GPIO port.
* It could be BIT0 ~ BIT11 for PG GPIO port.
*
* @return None
*
* @details Clear the interrupt status of specified GPIO pin.
* \hideinitializer
*/
#define GPIO_CLR_INT_FLAG(port, u32PinMask) ((port)->INTSRC = (u32PinMask))
/**
* @brief Disable Pin De-bounce Function
*
* @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF, PG, PH, PI, PJ, PK,PL, PM and PN.
* @param[in] u32PinMask The single or multiple pins of specified GPIO port.
* It could be BIT0 ~ BIT15 for PA, PB, PC, PD, PF and PH GPIO port.
* It could be BIT0 ~ BIT13 for PE GPIO port.
* It could be BIT0 ~ BIT11 for PG GPIO port.
*
* @return None
*
* @details Disable the interrupt de-bounce function of specified GPIO pin.
* \hideinitializer
*/
#define GPIO_DISABLE_DEBOUNCE(port, u32PinMask) ((port)->DBEN &= ~(u32PinMask))
/**
* @brief Enable Pin De-bounce Function
*
* @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF, PG or PH.
* @param[in] u32PinMask The single or multiple pins of specified GPIO port.
* It could be BIT0 ~ BIT15 for PA, PB, PC, PD, PF and PH GPIO port.
* It could be BIT0 ~ BIT13 for PE GPIO port.
* It could be BIT0 ~ BIT11 for PG GPIO port.
* @return None
*
* @details Enable the interrupt de-bounce function of specified GPIO pin.
* \hideinitializer
*/
#define GPIO_ENABLE_DEBOUNCE(port, u32PinMask) ((port)->DBEN |= (u32PinMask))
/**
* @brief Disable I/O Digital Input Path
*
* @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF, PG, PH, PI, PJ, PK,PL, PM and PN.
* @param[in] u32PinMask The single or multiple pins of specified GPIO port.
* It could be BIT0 ~ BIT15 for PA, PB, PC, PD, PF and PH GPIO port.
* It could be BIT0 ~ BIT13 for PE GPIO port.
* It could be BIT0 ~ BIT11 for PG GPIO port.
*
* @return None
*
* @details Disable I/O digital input path of specified GPIO pin.
* \hideinitializer
*/
#define GPIO_DISABLE_DIGITAL_PATH(port, u32PinMask) ((port)->DINOFF |= ((u32PinMask)<<16))
/**
* @brief Enable I/O Digital Input Path
*
* @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF, PG or PH.
* @param[in] u32PinMask The single or multiple pins of specified GPIO port.
* It could be BIT0 ~ BIT15 for PA, PB, PC, PD, PF and PH GPIO port.
* It could be BIT0 ~ BIT13 for PE GPIO port.
* It could be BIT0 ~ BIT11 for PG GPIO port.
*
* @return None
*
* @details Enable I/O digital input path of specified GPIO pin.
* \hideinitializer
*/
#define GPIO_ENABLE_DIGITAL_PATH(port, u32PinMask) ((port)->DINOFF &= ~((u32PinMask)<<16))
/**
* @brief Disable I/O DOUT mask
*
* @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF, PG, PH, PI, PJ, PK,PL, PM and PN.
* @param[in] u32PinMask The single or multiple pins of specified GPIO port.
* It could be BIT0 ~ BIT15 for PA, PB, PC, PD, PF and PH GPIO port.
* It could be BIT0 ~ BIT13 for PE GPIO port.
* It could be BIT0 ~ BIT11 for PG GPIO port.
*
* @return None
*
* @details Disable I/O DOUT mask of specified GPIO pin.
* \hideinitializer
*/
#define GPIO_DISABLE_DOUT_MASK(port, u32PinMask) ((port)->DATMSK &= ~(u32PinMask))
/**
* @brief Enable I/O DOUT mask
*
* @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF, PG or PH.
* @param[in] u32PinMask The single or multiple pins of specified GPIO port.
* It could be BIT0 ~ BIT15 for PA, PB, PC, PD, PF and PH GPIO port.
* It could be BIT0 ~ BIT13 for PE GPIO port.
* It could be BIT0 ~ BIT11 for PG GPIO port.
*
* @return None
*
* @details Enable I/O DOUT mask of specified GPIO pin.
* \hideinitializer
*/
#define GPIO_ENABLE_DOUT_MASK(port, u32PinMask) ((port)->DATMSK |= (u32PinMask))
/**
* @brief Get GPIO Pin Interrupt Flag
*
* @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF, PG, PH, PI, PJ, PK,PL, PM and PN.
* @param[in] u32PinMask The single or multiple pins of specified GPIO port.
* It could be BIT0 ~ BIT15 for PA, PB, PC, PD, PF and PH GPIO port.
* It could be BIT0 ~ BIT13 for PE GPIO port.
* It could be BIT0 ~ BIT11 for PG GPIO port.
*
* @retval 0 No interrupt at specified GPIO pin
* @retval 1 The specified GPIO pin generate an interrupt
*
* @details Get the interrupt status of specified GPIO pin.
* \hideinitializer
*/
#define GPIO_GET_INT_FLAG(port, u32PinMask) ((port)->INTSRC & (u32PinMask))
/**
* @brief Set De-bounce Sampling Cycle Time
*
* @param[in] u32Port GPIO port. It could be PA, PB, PC, PD, PE, PF, PG, PH, PI, PJ, PK,PL, PM and PN.
* @param[in] u32ClkSrc The de-bounce counter clock source. It could be GPIO_DBCTL_DBCLKSRC_HXT or GPIO_DBCTL_DBCLKSRC_LIRC.
* @param[in] u32ClkSel The de-bounce sampling cycle selection. It could be
* - \ref GPIO_DBCTL_DBCLKSEL_1
* - \ref GPIO_DBCTL_DBCLKSEL_2
* - \ref GPIO_DBCTL_DBCLKSEL_4
* - \ref GPIO_DBCTL_DBCLKSEL_8
* - \ref GPIO_DBCTL_DBCLKSEL_16
* - \ref GPIO_DBCTL_DBCLKSEL_32
* - \ref GPIO_DBCTL_DBCLKSEL_64
* - \ref GPIO_DBCTL_DBCLKSEL_128
* - \ref GPIO_DBCTL_DBCLKSEL_256
* - \ref GPIO_DBCTL_DBCLKSEL_512
* - \ref GPIO_DBCTL_DBCLKSEL_1024
* - \ref GPIO_DBCTL_DBCLKSEL_2048
* - \ref GPIO_DBCTL_DBCLKSEL_4096
* - \ref GPIO_DBCTL_DBCLKSEL_8192
* - \ref GPIO_DBCTL_DBCLKSEL_16384
* - \ref GPIO_DBCTL_DBCLKSEL_32768
*
* @return None
*
* @details Set the interrupt de-bounce sampling cycle time based on the debounce counter clock source. \n
* Example: _GPIO_SET_DEBOUNCE_TIME(GPIO_DBCTL_DBCLKSRC_LIRC, GPIO_DBCTL_DBCLKSEL_4). \n
* It's meaning the De-debounce counter clock source is internal 10 KHz and sampling cycle selection is 4. \n
* Then the target de-bounce sampling cycle time is (4)*(1/(10*1000)) s = 4*0.0001 s = 400 us,
* and system will sampling interrupt input once per 00 us.
* \hideinitializer
*/
#define GPIO_SET_DEBOUNCE_TIME(u32Port, u32ClkSrc, u32ClkSel) (u32Port->DBCTL = (GPIO_DBCTL_ICLKON_Msk | (u32ClkSrc) | (u32ClkSel)))
/**
* @brief Get GPIO Port IN Data
*
* @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF, PG, PH, PI, PJ, PK,PL, PM and PN.
*
* @return The specified port data
*
* @details Get the PIN register of specified GPIO port.
* \hideinitializer
*/
#define GPIO_GET_IN_DATA(port) ((port)->PIN)
/**
* @brief Set GPIO Port OUT Data
*
* @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF, PG, PH, PI, PJ, PK,PL, PM and PN.
* @param[in] u32Data GPIO port data.
*
* @return None
*
* @details Set the Data into specified GPIO port.
* \hideinitializer
*/
#define GPIO_SET_OUT_DATA(port, u32Data) ((port)->DOUT = (u32Data))
/**
* @brief Toggle Specified GPIO pin
*
* @param[in] u32Pin Pxy
*
* @return None
*
* @details Toggle the specified GPIO pint.
* \hideinitializer
*/
#define GPIO_TOGGLE(u32Pin) ((u32Pin) ^= 1)
/**
* @brief Enable External GPIO interrupt
*
* @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF, PG, PH, PI, PJ, PK,PL, PM and PN.
* @param[in] u32Pin The pin of specified GPIO port.
* It could be 0 ~ 15 for PA, PB, PC, PD, PF and PH GPIO port.
* It could be 0 ~ 13 for PE GPIO port.
* It could be 0 ~ 11 for PG GPIO port.
* @param[in] u32IntAttribs The interrupt attribute of specified GPIO pin. It could be \n
* GPIO_INT_RISING, GPIO_INT_FALLING, GPIO_INT_BOTH_EDGE, GPIO_INT_HIGH, GPIO_INT_LOW.
*
* @return None
*
* @details This function is used to enable specified GPIO pin interrupt.
* \hideinitializer
*/
#define GPIO_EnableEINT GPIO_EnableInt
/**
* @brief Disable External GPIO interrupt
*
* @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF, PG, PH, PI, PJ, PK,PL, PM and PN.
* @param[in] u32Pin The pin of specified GPIO port.
* It could be 0 ~ 15 for PA, PB, PC, PD, PF and PH GPIO port.
* It could be 0 ~ 13 for PE GPIO port.
* It could be 0 ~ 11 for PG GPIO port.
*
* @return None
*
* @details This function is used to enable specified GPIO pin interrupt.
* \hideinitializer
*/
#define GPIO_DisableEINT GPIO_DisableInt
void GPIO_SetMode(GPIO_T *port, uint32_t u32PinMask, uint32_t u32Mode);
void GPIO_EnableInt(GPIO_T *port, uint32_t u32Pin, uint32_t u32IntAttribs);
void GPIO_DisableInt(GPIO_T *port, uint32_t u32Pin);
void GPIO_SetSlewCtl(GPIO_T *port, uint32_t u32PinMask, uint32_t u32Mode);
void GPIO_SetPullCtl(GPIO_T *port, uint32_t u32PinMask, uint32_t u32Mode);
void GPIO_SetDrivingCtl(GPIO_T *port, uint32_t u32PinMask, uint32_t u32Driving);
void GPIO_SetSchmittTriggere(GPIO_T *port, uint32_t u32PinMask, uint32_t u32SchmittTrigger);
void GPIO_SetPowerMode(GPIO_T *port, uint32_t u32PinMask, uint32_t u32PowerMode);
uint32_t GPIO_GetPowerMode(GPIO_T *port, uint32_t u32PinNo);
uint32_t GPIO_GetSchmittTriggere(GPIO_T *port, uint32_t u32PinNo);
uint32_t GPIO_GetDrivingCtl(GPIO_T *port, uint32_t u32PinNo);
/*@}*/ /* end of group GPIO_EXPORTED_FUNCTIONS */
/*@}*/ /* end of group GPIO_Driver */
/*@}*/ /* end of group Standard_Driver */
#ifdef __cplusplus
}
#endif
#endif /* __GPIO_H__ */

174
bsp/nuvoton/libraries/ma35/StdDriver/inc/nu_hwsem.h Normal file
View File

@ -0,0 +1,174 @@
/**************************************************************************//**
* @file nu_hwsem.h
* @brief HWSEM driver header file
*
* SPDX-License-Identifier: Apache-2.0
* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __NU_HWSEM_H__
#define __NU_HWSEM_H__
#ifdef __cplusplus
extern "C"
{
#endif
/** @addtogroup Standard_Driver Standard Driver
@{
*/
/** @addtogroup HWSEM_Driver HWSEM Driver
@{
*/
/** @addtogroup HWSEM_EXPORTED_CONSTANTS HWSEM Exported Constants
@{
*/
#define HWSEM_CNT 8ul /*!<HWSEM count \hideinitializer */
#define HWSEM_LOCK_BY_A35 1ul /*!<Semaphore lock by A35 \hideinitializer */
#define HWSEM_LOCK_BY_M4 2ul /*!<Semaphore lock by M4 \hideinitializer */
/*@}*/ /* end of group HWSEM_EXPORTED_CONSTANTS */
/** @addtogroup HWSEM_EXPORTED_FUNCTIONS HWSEM Exported Functions
@{
*/
/**
* @brief Reset hardware semaphore
*
* @param[in] hwsem The pointer of the specified HWSEM module.
* @param[in] u32Num HWSEM number, valid values are between 0~7
* \hideinitializer
*/
#define HWSEM_RESET(hwsem, u32Num) ((hwsem)->CTL |= (HWSEM_CTL_SEM0RST_Msk << (u32Num)))
/**
* @brief
*
* @param[in] hwsem The pointer of the specified HWSEM module.
* @param[in] u32Num HWSEM number, valid values are between 0~7
*
* @retval 0 The specified semaphore is not locked.
* Otherwise The specified semaphore is locked.
* \hideinitializer
*/
#define HWSEM_IS_LOCKED(hwsem, u32Num) ((hwsem)->SEM[(u32Num)] & (HWSEM_SEM_ID_Msk))
/**
* @brief Enable specified HWSEM interrupt
*
* @param[in] hwsem The pointer of the specified HWSEM module.
* @param[in] u32Num HWSEM number, valid values are between 0~7
*
*
* \hideinitializer
*/
#define HWSEM_ENABLE_INT(hwsem, u32Num) ((hwsem)->INTENM4 |= (HWSEM_INTENM4_SEM0IEN_Msk << (u32Num)))
/**
* @brief Disable specified HWSEM interrupt
*
* @param[in] hwsem The pointer of the specified HWSEM module.
* @param[in] u32Num HWSEM number, valid values are between 0~7
*
*
* \hideinitializer
*/
#define HWSEM_DISABLE_INT(hwsem, u32Num) ((hwsem)->INTENM4 &= ~(HWSEM_INTENM4_SEM0IEN_Msk << (u32Num)))
/**
* @brief Get specified interrupt flag
*
* @param[in] hwsem The pointer of the specified HWSEM module.
* @param[in] u32Num HWSEM number, valid values are between 0~7
*
* @retval 0 The specified interrupt is not happened.
* Otherwise The specified interrupt is happened.
* \hideinitializer
*/
#define HWSEM_GET_INT_FLAG(hwsem, u32Num) ((hwsem)->INTSTSM4 & (HWSEM_INTSTSM4_SEM0IF_Msk << (u32Num)))
/**
* @brief Clear specified interrupt flag
*
* @param[in] hwsem The pointer of the specified HWSEM module.
* @param[in] u32Num HWSEM number, valid values are between 0~7
*
* \hideinitializer
*/
#define HWSEM_CLR_INT_FLAG(hwsem, u32Num) ((hwsem)->INTSTSM4 = (HWSEM_INTSTSM4_SEM0IF_Msk << (u32Num)))
/**
* @brief Unlock specified semaphore
*
* @param[in] hwsem The pointer of the specified HWSEM module.
* @param[in] u32Num HWSEM number, valid values are between 0~7
* @param[in] u8Key HWSEM channel key
*
* \hideinitializer
*/
#define HWSEM_UNLOCK(hwsem, u32Num, u8Key) ((hwsem)->SEM[(u32Num)] = ((u8Key) << HWSEM_SEM_KEY_Pos) & HWSEM_SEM_KEY_Msk)
/* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */
__STATIC_INLINE int32_t HWSEM_Try_Lock(HWSEM_T *hwsem, uint32_t u32Num, uint8_t u8Key);
__STATIC_INLINE void HWSEM_Spin_Lock(HWSEM_T *hwsem, uint32_t u32Num, uint8_t u8Key);
/**
* @brief Try to lock specified semaphore
*
* @param[in] hwsem The pointer of the specified HWSEM module.
* @param[in] u32Num HWSEM number, valid values are between 0~7
* @param[in] u8Key HWSEM channel key
* @retval 0 Successfully acquire semaphore
* @retval -1 Failed to acquire semaphore
* \hideinitializer
*/
__STATIC_INLINE int32_t HWSEM_Try_Lock(HWSEM_T *hwsem, uint32_t u32Num, uint8_t u8Key)
{
hwsem->SEM[u32Num] = (u8Key << HWSEM_SEM_KEY_Pos);
if ((hwsem->SEM[u32Num] & HWSEM_SEM_ID_Msk) == HWSEM_LOCK_BY_M4 &&
(hwsem->SEM[u32Num] & HWSEM_SEM_KEY_Msk) == (u8Key << HWSEM_SEM_KEY_Pos))
return 0;
else
return -1;
}
/**
* @brief Spin until lock specified semaphore
*
* @param[in] hwsem The pointer of the specified HWSEM module.
* @param[in] u32Num HWSEM number, valid values are between 0~7
* @param[in] u8Key HWSEM channel key
*
* \hideinitializer
*/
__STATIC_INLINE void HWSEM_Spin_Lock(HWSEM_T *hwsem, uint32_t u32Num, uint8_t u8Key)
{
while (1)
{
hwsem->SEM[u32Num] = (u8Key << HWSEM_SEM_KEY_Pos);
if ((hwsem->SEM[u32Num] & HWSEM_SEM_ID_Msk) == HWSEM_LOCK_BY_M4 &&
(hwsem->SEM[u32Num] & HWSEM_SEM_KEY_Msk) == (u8Key << HWSEM_SEM_KEY_Pos))
break;
}
}
/*@}*/ /* end of group HWSEM_EXPORTED_FUNCTIONS */
/*@}*/ /* end of group HWSEM_Driver */
/*@}*/ /* end of group Standard_Driver */
#ifdef __cplusplus
}
#endif
#endif

296
bsp/nuvoton/libraries/ma35/StdDriver/inc/nu_i2c.h Normal file
View File

@ -0,0 +1,296 @@
/****************************************************************************//**
* @file nu_i2c.h
* @brief I2C driver header file
*
* SPDX-License-Identifier: Apache-2.0
* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __NU_I2C_H__
#define __NU_I2C_H__
#ifdef __cplusplus
extern "C"
{
#endif
/** @addtogroup Standard_Driver Standard Driver
@{
*/
/** @addtogroup I2C_Driver I2C Driver
@{
*/
/** @addtogroup I2C_EXPORTED_CONSTANTS I2C Exported Constants
@{
*/
/*---------------------------------------------------------------------------------------------------------*/
/* I2C_CTL constant definitions. */
/*---------------------------------------------------------------------------------------------------------*/
#define I2C_CTL_STA_SI 0x28UL /*!< I2C_CTL setting for I2C control bits. It would set STA and SI bits \hideinitializer */
#define I2C_CTL_STA_SI_AA 0x2CUL /*!< I2C_CTL setting for I2C control bits. It would set STA, SI and AA bits \hideinitializer */
#define I2C_CTL_STO_SI 0x18UL /*!< I2C_CTL setting for I2C control bits. It would set STO and SI bits \hideinitializer */
#define I2C_CTL_STO_SI_AA 0x1CUL /*!< I2C_CTL setting for I2C control bits. It would set STO, SI and AA bits \hideinitializer */
#define I2C_CTL_SI 0x08UL /*!< I2C_CTL setting for I2C control bits. It would set SI bit \hideinitializer */
#define I2C_CTL_SI_AA 0x0CUL /*!< I2C_CTL setting for I2C control bits. It would set SI and AA bits \hideinitializer */
#define I2C_CTL_STA 0x20UL /*!< I2C_CTL setting for I2C control bits. It would set STA bit \hideinitializer */
#define I2C_CTL_STO 0x10UL /*!< I2C_CTL setting for I2C control bits. It would set STO bit \hideinitializer */
#define I2C_CTL_AA 0x04UL /*!< I2C_CTL setting for I2C control bits. It would set AA bit \hideinitializer */
/*---------------------------------------------------------------------------------------------------------*/
/* I2C GCMode constant definitions. */
/*---------------------------------------------------------------------------------------------------------*/
#define I2C_GCMODE_ENABLE 1 /*!< Enable I2C GC Mode \hideinitializer */
#define I2C_GCMODE_DISABLE 0 /*!< Disable I2C GC Mode \hideinitializer */
/*@}*/ /* end of group I2C_EXPORTED_CONSTANTS */
/** @addtogroup I2C_EXPORTED_FUNCTIONS I2C Exported Functions
@{
*/
/**
* @brief The macro is used to set I2C bus condition at One Time
*
* @param[in] i2c Specify I2C port
* @param[in] u8Ctrl A byte writes to I2C control register
*
* @return None
*
* @details Set I2C_CTL register to control I2C bus conditions of START, STOP, SI, ACK.
* \hideinitializer
*/
#define I2C_SET_CONTROL_REG(i2c, u8Ctrl) ((i2c)->CTL0 = ((i2c)->CTL0 & ~0x3c) | (u8Ctrl))
/**
* @brief The macro is used to set START condition of I2C Bus
*
* @param[in] i2c Specify I2C port
*
* @return None
*
* @details Set the I2C bus START condition in I2C_CTL register.
* \hideinitializer
*/
#define I2C_START(i2c) ((i2c)->CTL0 = ((i2c)->CTL0 & ~I2C_CTL0_SI_Msk) | I2C_CTL0_STA_Msk)
/**
* @brief The macro is used to wait I2C bus status get ready
*
* @param[in] i2c Specify I2C port
*
* @return None
*
* @details When a new status is presented of I2C bus, the SI flag will be set in I2C_CTL register.
* \hideinitializer
*/
#define I2C_WAIT_READY(i2c) while(!((i2c)->CTL0 & I2C_CTL0_SI_Msk))
/**
* @brief The macro is used to Read I2C Bus Data Register
*
* @param[in] i2c Specify I2C port
*
* @return A byte of I2C data register
*
* @details I2C controller read data from bus and save it in I2CDAT register.
* \hideinitializer
*/
#define I2C_GET_DATA(i2c) ((i2c)->DAT)
/**
* @brief Write a Data to I2C Data Register
*
* @param[in] i2c Specify I2C port
* @param[in] u8Data A byte that writes to data register
*
* @return None
*
* @details When write a data to I2C_DAT register, the I2C controller will shift it to I2C bus.
* \hideinitializer
*/
#define I2C_SET_DATA(i2c, u8Data) ((i2c)->DAT = (u8Data))
/**
* @brief Get I2C Bus status code
*
* @param[in] i2c Specify I2C port
*
* @return I2C status code
*
* @details To get this status code to monitor I2C bus event.
* \hideinitializer
*/
#define I2C_GET_STATUS(i2c) ((i2c)->STATUS0)
/**
* @brief Get Time-out flag from I2C Bus
*
* @param[in] i2c Specify I2C port
*
* @retval 0 I2C Bus time-out is not happened
* @retval 1 I2C Bus time-out is happened
*
* @details When I2C bus occurs time-out event, the time-out flag will be set.
* \hideinitializer
*/
#define I2C_GET_TIMEOUT_FLAG(i2c) ( ((i2c)->TOCTL & I2C_TOCTL_TOIF_Msk) == I2C_TOCTL_TOIF_Msk ? 1:0 )
/**
* @brief To get wake-up flag from I2C Bus
*
* @param[in] i2c Specify I2C port
*
* @retval 0 Chip is not woken-up from power-down mode
* @retval 1 Chip is woken-up from power-down mode
*
* @details I2C bus occurs wake-up event, wake-up flag will be set.
* \hideinitializer
*/
#define I2C_GET_WAKEUP_FLAG(i2c) ( ((i2c)->WKSTS & I2C_WKSTS_WKIF_Msk) == I2C_WKSTS_WKIF_Msk ? 1:0 )
/**
* @brief To clear wake-up flag
*
* @param[in] i2c Specify I2C port
*
* @return None
*
* @details If wake-up flag is set, use this macro to clear it.
* \hideinitializer
*/
#define I2C_CLEAR_WAKEUP_FLAG(i2c) ((i2c)->WKSTS = I2C_WKSTS_WKIF_Msk)
/**
* @brief Enable RX PDMA function.
* @param[in] i2c The pointer of the specified I2C module.
* @return None.
* @details Set RXPDMAEN bit of I2C_CTL1 register to enable RX PDMA transfer function.
* \hideinitializer
*/
#define I2C_ENABLE_RX_PDMA(i2c) ((i2c)->CTL1 |= I2C_CTL1_RXPDMAEN_Msk)
/**
* @brief Enable TX PDMA function.
* @param[in] i2c The pointer of the specified I2C module.
* @return None.
* @details Set TXPDMAEN bit of I2C_CTL1 register to enable TX PDMA transfer function.
* \hideinitializer
*/
#define I2C_ENABLE_TX_PDMA(i2c) ((i2c)->CTL1 |= I2C_CTL1_TXPDMAEN_Msk)
/**
* @brief Disable RX PDMA transfer.
* @param[in] i2c The pointer of the specified I2C module.
* @return None.
* @details Clear RXPDMAEN bit of I2C_CTL1 register to disable RX PDMA transfer function.
* \hideinitializer
*/
#define I2C_DISABLE_RX_PDMA(i2c) ((i2c)->CTL1 &= ~I2C_CTL1_RXPDMAEN_Msk)
/**
* @brief Disable TX PDMA transfer.
* @param[in] i2c The pointer of the specified I2C module.
* @return None.
* @details Clear TXPDMAEN bit of I2C_CTL1 register to disable TX PDMA transfer function.
* \hideinitializer
*/
#define I2C_DISABLE_TX_PDMA(i2c) ((i2c)->CTL1 &= ~I2C_CTL1_TXPDMAEN_Msk)
/**
* @brief Enable PDMA stretch function.
* @param[in] i2c The pointer of the specified I2C module.
* @return None.
* @details Enable this function is to stretch bus by hardware after PDMA transfer is done if SI is not cleared.
* \hideinitializer
*/
#define I2C_ENABLE_PDMA_STRETCH(i2c) ((i2c)->CTL1 |= I2C_CTL1_PDMASTR_Msk)
/**
* @brief Disable PDMA stretch function.
* @param[in] i2c The pointer of the specified I2C module.
* @return None.
* @details I2C will send STOP after PDMA transfers done automatically.
* \hideinitializer
*/
#define I2C_DISABLE_PDMA_STRETCH(i2c) ((i2c)->CTL1 &= ~I2C_CTL1_PDMASTR_Msk)
/**
* @brief Reset PDMA function.
* @param[in] i2c The pointer of the specified I2C module.
* @return None.
* @details I2C PDMA engine will be reset after this function is called.
* \hideinitializer
*/
#define I2C_DISABLE_RST_PDMA(i2c) ((i2c)->CTL1 |= I2C_CTL1_PDMARST_Msk)
/*---------------------------------------------------------------------------------------------------------*/
/* inline functions */
/*---------------------------------------------------------------------------------------------------------*/
/* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */
__STATIC_INLINE void I2C_STOP(I2C_T *i2c);
/**
* @brief The macro is used to set STOP condition of I2C Bus
*
* @param[in] i2c Specify I2C port
*
* @return None
*
* @details Set the I2C bus STOP condition in I2C_CTL register.
*/
__STATIC_INLINE void I2C_STOP(I2C_T *i2c)
{
(i2c)->CTL0 |= (I2C_CTL0_SI_Msk | I2C_CTL0_STO_Msk);
while (i2c->CTL0 & I2C_CTL0_STO_Msk)
{
}
}
void I2C_ClearTimeoutFlag(I2C_T *i2c);
void I2C_Close(I2C_T *i2c);
void I2C_Trigger(I2C_T *i2c, uint8_t u8Start, uint8_t u8Stop, uint8_t u8Si, uint8_t u8Ack);
void I2C_DisableInt(I2C_T *i2c);
void I2C_EnableInt(I2C_T *i2c);
uint32_t I2C_GetBusClockFreq(I2C_T *i2c);
uint32_t I2C_GetIntFlag(I2C_T *i2c);
uint32_t I2C_GetStatus(I2C_T *i2c);
uint32_t I2C_Open(I2C_T *i2c, uint32_t u32BusClock);
uint8_t I2C_GetData(I2C_T *i2c);
void I2C_SetSlaveAddr(I2C_T *i2c, uint8_t u8SlaveNo, uint8_t u8SlaveAddr, uint8_t u8GCMode);
void I2C_SetSlaveAddrMask(I2C_T *i2c, uint8_t u8SlaveNo, uint8_t u8SlaveAddrMask);
uint32_t I2C_SetBusClockFreq(I2C_T *i2c, uint32_t u32BusClock);
void I2C_EnableTimeout(I2C_T *i2c, uint8_t u8LongTimeout);
void I2C_DisableTimeout(I2C_T *i2c);
void I2C_EnableWakeup(I2C_T *i2c);
void I2C_DisableWakeup(I2C_T *i2c);
void I2C_SetData(I2C_T *i2c, uint8_t u8Data);
uint8_t I2C_WriteByte(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t data);
uint32_t I2C_WriteMultiBytes(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t data[], uint32_t u32wLen);
uint8_t I2C_WriteByteOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t data);
uint32_t I2C_WriteMultiBytesOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t data[], uint32_t u32wLen);
uint8_t I2C_WriteByteTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t data);
uint32_t I2C_WriteMultiBytesTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t data[], uint32_t u32wLen);
uint8_t I2C_ReadByte(I2C_T *i2c, uint8_t u8SlaveAddr);
uint32_t I2C_ReadMultiBytes(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t rdata[], uint32_t u32rLen);
uint8_t I2C_ReadByteOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr);
uint32_t I2C_ReadMultiBytesOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t rdata[], uint32_t u32rLen);
uint8_t I2C_ReadByteTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr);
uint32_t I2C_ReadMultiBytesTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t rdata[], uint32_t u32rLen);
/*@}*/ /* end of group I2C_EXPORTED_FUNCTIONS */
/*@}*/ /* end of group I2C_Driver */
/*@}*/ /* end of group Standard_Driver */
#ifdef __cplusplus
}
#endif
#endif

351
bsp/nuvoton/libraries/ma35/StdDriver/inc/nu_i2s.h Normal file
View File

@ -0,0 +1,351 @@
/****************************************************************************//**
* @file nu_i2s.h
* @brief I2S driver header file
*
* SPDX-License-Identifier: Apache-2.0
* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __NU_I2S_H__
#define __NU_I2S_H__
#ifdef __cplusplus
extern "C"
{
#endif
/** @addtogroup Standard_Driver Standard Driver
@{
*/
/** @addtogroup I2S_Driver I2S Driver
@{
*/
/** @addtogroup I2S_EXPORTED_CONSTANTS I2S Exported Constants
@{
*/
#define I2S_DATABIT_8 (0U << I2S_CTL0_DATWIDTH_Pos) /*!< I2S data width is 8-bit \hideinitializer */
#define I2S_DATABIT_16 (1U << I2S_CTL0_DATWIDTH_Pos) /*!< I2S data width is 16-bit \hideinitializer */
#define I2S_DATABIT_24 (2U << I2S_CTL0_DATWIDTH_Pos) /*!< I2S data width is 24-bit \hideinitializer */
#define I2S_DATABIT_32 (3U << I2S_CTL0_DATWIDTH_Pos) /*!< I2S data width is 32-bit \hideinitializer */
/* Audio Format */
#define I2S_ENABLE_MONO I2S_CTL0_MONO_Msk /*!< Mono channel \hideinitializer */
#define I2S_DISABLE_MONO (0U) /*!< Stereo channel \hideinitializer */
/* I2S Data Format */
#define I2S_FORMAT_I2S (0U << I2S_CTL0_FORMAT_Pos) /*!< I2S data format \hideinitializer */
#define I2S_FORMAT_I2S_MSB (1U << I2S_CTL0_FORMAT_Pos) /*!< I2S MSB data format \hideinitializer */
#define I2S_FORMAT_I2S_LSB (2U << I2S_CTL0_FORMAT_Pos) /*!< I2S LSB data format \hideinitializer */
#define I2S_FORMAT_PCM (4U << I2S_CTL0_FORMAT_Pos) /*!< PCM data format \hideinitializer */
#define I2S_FORMAT_PCM_MSB (5U << I2S_CTL0_FORMAT_Pos) /*!< PCM MSB data format \hideinitializer */
#define I2S_FORMAT_PCM_LSB (6U << I2S_CTL0_FORMAT_Pos) /*!< PCM LSB data format \hideinitializer */
/* I2S Data Format */
#define I2S_ORDER_AT_MSB (0U) /*!< Channel data is at MSB \hideinitializer */
#define I2S_ORDER_AT_LSB I2S_CTL0_ORDER_Msk /*!< Channel data is at LSB \hideinitializer */
/* I2S TDM Channel Number */
#define I2S_TDM_2CH 0U /*!< Use TDM 2 channel \hideinitializer */
#define I2S_TDM_4CH 1U /*!< Use TDM 4 channel \hideinitializer */
#define I2S_TDM_6CH 2U /*!< Use TDM 6 channel \hideinitializer */
#define I2S_TDM_8CH 3U /*!< Use TDM 8 channel \hideinitializer */
/* I2S TDM Channel Width */
#define I2S_TDM_WIDTH_8BIT 0U /*!< TDM channel witch is 8-bit \hideinitializer */
#define I2S_TDM_WIDTH_16BIT 1U /*!< TDM channel witch is 16-bit \hideinitializer */
#define I2S_TDM_WIDTH_24BIT 2U /*!< TDM channel witch is 24-bit \hideinitializer */
#define I2S_TDM_WIDTH_32BIT 3U /*!< TDM channel witch is 32-bit \hideinitializer */
/* I2S TDM Sync Width */
#define I2S_TDM_SYNC_ONE_BCLK 0U /*!< TDM sync widht is one BLCK period \hideinitializer */
#define I2S_TDM_SYNC_ONE_CHANNEL 1U /*!< TDM sync widht is one channel period \hideinitializer */
/* I2S Operation mode */
#define I2S_MODE_SLAVE I2S_CTL0_SLAVE_Msk /*!< As slave mode \hideinitializer */
#define I2S_MODE_MASTER (0u) /*!< As master mode \hideinitializer */
/* I2S FIFO Threshold */
#define I2S_FIFO_TX_LEVEL_WORD_0 (0U) /*!< TX threshold is 0 word \hideinitializer */
#define I2S_FIFO_TX_LEVEL_WORD_1 (1U << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 1 word \hideinitializer */
#define I2S_FIFO_TX_LEVEL_WORD_2 (2U << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 2 words \hideinitializer */
#define I2S_FIFO_TX_LEVEL_WORD_3 (3U << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 3 words \hideinitializer */
#define I2S_FIFO_TX_LEVEL_WORD_4 (4U << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 4 words \hideinitializer */
#define I2S_FIFO_TX_LEVEL_WORD_5 (5U << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 5 words \hideinitializer */
#define I2S_FIFO_TX_LEVEL_WORD_6 (6U << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 6 words \hideinitializer */
#define I2S_FIFO_TX_LEVEL_WORD_7 (7U << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 7 words \hideinitializer */
#define I2S_FIFO_TX_LEVEL_WORD_8 (8U << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 8 words \hideinitializer */
#define I2S_FIFO_TX_LEVEL_WORD_9 (9U << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 9 words \hideinitializer */
#define I2S_FIFO_TX_LEVEL_WORD_10 (10U << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 10 words \hideinitializer */
#define I2S_FIFO_TX_LEVEL_WORD_11 (11U << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 11 words \hideinitializer */
#define I2S_FIFO_TX_LEVEL_WORD_12 (12U << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 12 words \hideinitializer */
#define I2S_FIFO_TX_LEVEL_WORD_13 (13U << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 13 words \hideinitializer */
#define I2S_FIFO_TX_LEVEL_WORD_14 (14U << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 14 words \hideinitializer */
#define I2S_FIFO_TX_LEVEL_WORD_15 (15U << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 15 words \hideinitializer */
#define I2S_FIFO_RX_LEVEL_WORD_1 (0U) /*!< RX threshold is 1 word \hideinitializer */
#define I2S_FIFO_RX_LEVEL_WORD_2 (1U << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 2 words \hideinitializer */
#define I2S_FIFO_RX_LEVEL_WORD_3 (2U << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 3 words \hideinitializer */
#define I2S_FIFO_RX_LEVEL_WORD_4 (3U << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 4 words \hideinitializer */
#define I2S_FIFO_RX_LEVEL_WORD_5 (4U << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 5 words \hideinitializer */
#define I2S_FIFO_RX_LEVEL_WORD_6 (5U << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 6 words \hideinitializer */
#define I2S_FIFO_RX_LEVEL_WORD_7 (6U << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 7 words \hideinitializer */
#define I2S_FIFO_RX_LEVEL_WORD_8 (7U << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 8 words \hideinitializer */
#define I2S_FIFO_RX_LEVEL_WORD_9 (8U << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 9 words \hideinitializer */
#define I2S_FIFO_RX_LEVEL_WORD_10 (9U << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 10 words \hideinitializer */
#define I2S_FIFO_RX_LEVEL_WORD_11 (10U << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 11 words \hideinitializer */
#define I2S_FIFO_RX_LEVEL_WORD_12 (11U << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 12 words \hideinitializer */
#define I2S_FIFO_RX_LEVEL_WORD_13 (12U << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 13 words \hideinitializer */
#define I2S_FIFO_RX_LEVEL_WORD_14 (13U << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 14 words \hideinitializer */
#define I2S_FIFO_RX_LEVEL_WORD_15 (14U << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 15 words \hideinitializer */
#define I2S_FIFO_RX_LEVEL_WORD_16 (15U << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 16 words \hideinitializer */
/* I2S Record Channel */
#define I2S_MONO_RIGHT (0U) /*!< Record mono right channel \hideinitializer */
#define I2S_MONO_LEFT I2S_CTL0_RXLCH_Msk /*!< Record mono left channel \hideinitializer */
/* I2S Channel */
#define I2S_RIGHT (0U) /*!< Select right channel \hideinitializer */
#define I2S_LEFT (1U) /*!< Select left channel \hideinitializer */
/*@}*/ /* end of group I2S_EXPORTED_CONSTANTS */
/** @addtogroup I2S_EXPORTED_FUNCTIONS I2S Exported Functions
@{
*/
/*---------------------------------------------------------------------------------------------------------*/
/* inline functions */
/*---------------------------------------------------------------------------------------------------------*/
/**
* @brief Enable zero cross detect function.
* @param[in] i2s is the base address of I2S module.
* @param[in] u32ChMask is the mask for channel number (valid value is from (1~8).
* @return none
* \hideinitializer
*/
__STATIC_INLINE void I2S_ENABLE_TX_ZCD(I2S_T *i2s, uint32_t u32ChMask)
{
if ((u32ChMask > 0U) && (u32ChMask < 9U))
{
i2s->CTL1 |= ((uint32_t)1U << (u32ChMask - 1U));
}
}
/**
* @brief Disable zero cross detect function.
* @param[in] i2s is the base address of I2S module.
* @param[in] u32ChMask is the mask for channel number (valid value is from (1~8).
* @return none
* \hideinitializer
*/
__STATIC_INLINE void I2S_DISABLE_TX_ZCD(I2S_T *i2s, uint32_t u32ChMask)
{
if ((u32ChMask > 0U) && (u32ChMask < 9U))
{
i2s->CTL1 &= ~((uint32_t)1U << (u32ChMask - 1U));
}
}
/**
* @brief Enable I2S Tx DMA function. I2S requests DMA to transfer data to Tx FIFO.
* @param[in] i2s is the base address of I2S module.
* @return none
* \hideinitializer
*/
#define I2S_ENABLE_TXDMA(i2s) ( (i2s)->CTL0 |= I2S_CTL0_TXPDMAEN_Msk )
/**
* @brief Disable I2S Tx DMA function. I2S requests DMA to transfer data to Tx FIFO.
* @param[in] i2s is the base address of I2S module.
* @return none
* \hideinitializer
*/
#define I2S_DISABLE_TXDMA(i2s) ( (i2s)->CTL0 &= ~I2S_CTL0_TXPDMAEN_Msk )
/**
* @brief Enable I2S Rx DMA function. I2S requests DMA to transfer data from Rx FIFO.
* @param[in] i2s is the base address of I2S module.
* @return none
* \hideinitializer
*/
#define I2S_ENABLE_RXDMA(i2s) ( (i2s)->CTL0 |= I2S_CTL0_RXPDMAEN_Msk )
/**
* @brief Disable I2S Rx DMA function. I2S requests DMA to transfer data from Rx FIFO.
* @param[in] i2s is the base address of I2S module.
* @return none
* \hideinitializer
*/
#define I2S_DISABLE_RXDMA(i2s) ( (i2s)->CTL0 &= ~I2S_CTL0_RXPDMAEN_Msk )
/**
* @brief Enable I2S Tx function .
* @param[in] i2s is the base address of I2S module.
* @return none
* \hideinitializer
*/
#define I2S_ENABLE_TX(i2s) ( (i2s)->CTL0 |= I2S_CTL0_TXEN_Msk )
/**
* @brief Disable I2S Tx function .
* @param[in] i2s is the base address of I2S module.
* @return none
* \hideinitializer
*/
#define I2S_DISABLE_TX(i2s) ( (i2s)->CTL0 &= ~I2S_CTL0_TXEN_Msk )
/**
* @brief Enable I2S Rx function .
* @param[in] i2s is the base address of I2S module.
* @return none
* \hideinitializer
*/
#define I2S_ENABLE_RX(i2s) ( (i2s)->CTL0 |= I2S_CTL0_RXEN_Msk )
/**
* @brief Disable I2S Rx function .
* @param[in] i2s is the base address of I2S module.
* @return none
* \hideinitializer
*/
#define I2S_DISABLE_RX(i2s) ( (i2s)->CTL0 &= ~I2S_CTL0_RXEN_Msk )
/**
* @brief Enable Tx Mute function .
* @param[in] i2s is the base address of I2S module.
* @return none
* \hideinitializer
*/
#define I2S_ENABLE_TX_MUTE(i2s) ( (i2s)->CTL0 |= I2S_CTL0_MUTE_Msk )
/**
* @brief Disable Tx Mute function .
* @param[in] i2s is the base address of I2S module.
* @return none
* \hideinitializer
*/
#define I2S_DISABLE_TX_MUTE(i2s) ( (i2s)->CTL0 &= ~I2S_CTL0_MUTE_Msk )
/**
* @brief Clear Tx FIFO. Internal pointer is reset to FIFO start point.
* @param[in] i2s is the base address of I2S module.
* @return none
* \hideinitializer
*/
#define I2S_CLR_TX_FIFO(i2s) ( (i2s)->CTL0 |= I2S_CTL0_TXFBCLR_Msk )
/**
* @brief Clear Rx FIFO. Internal pointer is reset to FIFO start point.
* @param[in] i2s is the base address of I2S module.
* @return none
* \hideinitializer
*/
#define I2S_CLR_RX_FIFO(i2s) ( (i2s)->CTL0 |= I2S_CTL0_RXFBCLR_Msk )
/**
* @brief This function sets the recording source channel when mono mode is used.
* @param[in] i2s is the base address of I2S module.
* @param[in] u32Ch left or right channel. Valid values are:
* - \ref I2S_MONO_LEFT
* - \ref I2S_MONO_RIGHT
* @return none
* \hideinitializer
*/
__STATIC_INLINE void I2S_SET_MONO_RX_CHANNEL(I2S_T *i2s, uint32_t u32Ch)
{
u32Ch == I2S_MONO_LEFT ?
(i2s->CTL0 |= I2S_CTL0_RXLCH_Msk) :
(i2s->CTL0 &= ~I2S_CTL0_RXLCH_Msk);
}
/**
* @brief Write data to I2S Tx FIFO.
* @param[in] i2s is the base address of I2S module.
* @param[in] u32Data: The data written to FIFO.
* @return none
* \hideinitializer
*/
#define I2S_WRITE_TX_FIFO(i2s, u32Data) ( (i2s)->TXFIFO = (u32Data) )
/**
* @brief Read Rx FIFO.
* @param[in] i2s is the base address of I2S module.
* @return Data in Rx FIFO.
* \hideinitializer
*/
#define I2S_READ_RX_FIFO(i2s) ( (i2s)->RXFIFO )
/**
* @brief This function gets the interrupt flag according to the mask parameter.
* @param[in] i2s is the base address of I2S module.
* @param[in] u32Mask is the mask for the all interrupt flags.
* @return The masked bit value of interrupt flag.
* \hideinitializer
*/
#define I2S_GET_INT_FLAG(i2s, u32Mask) ( (i2s)->STATUS0 & (u32Mask) )
/**
* @brief This function clears the interrupt flag according to the mask parameter.
* @param[in] i2s is the base address of I2S module.
* @param[in] u32Mask is the mask for the all interrupt flags.
* @return none
* \hideinitializer
*/
#define I2S_CLR_INT_FLAG(i2s, u32Mask) ( (i2s)->STATUS0 |= (u32Mask) )
/**
* @brief This function gets the zero crossing interrupt flag according to the mask parameter.
* @param[in] i2s is the base address of I2S module.
* @param[in] u32Mask is the mask for the all interrupt flags.
* @return The masked bit value of interrupt flag.
* \hideinitializer
*/
#define I2S_GET_ZC_INT_FLAG(i2s, u32Mask) ( (i2s)->STATUS1 & (u32Mask) )
/**
* @brief This function clears the zero crossing interrupt flag according to the mask parameter.
* @param[in] i2s is the base address of I2S module.
* @param[in] u32Mask is the mask for the all interrupt flags.
* @return none
* \hideinitializer
*/
#define I2S_CLR_ZC_INT_FLAG(i2s, u32Mask) ( (i2s)->STATUS1 |= (u32Mask) )
/**
* @brief Get transmit FIFO level
* @param[in] i2s is the base address of I2S module.
* @return FIFO level
* \hideinitializer
*/
#define I2S_GET_TX_FIFO_LEVEL(i2s) ( (((i2s)->STATUS1 & I2S_STATUS1_TXCNT_Msk) >> I2S_STATUS1_TXCNT_Pos) & 0xF )
/**
* @brief Get receive FIFO level
* @param[in] i2s is the base address of I2S module.
* @return FIFO level
* \hideinitializer
*/
#define I2S_GET_RX_FIFO_LEVEL(i2s) ( (((i2s)->STATUS1 & I2S_STATUS1_RXCNT_Msk) >> I2S_STATUS1_RXCNT_Pos) & 0xF )
void I2S_Close(I2S_T *i2s);
void I2S_EnableInt(I2S_T *i2s, uint32_t u32Mask);
void I2S_DisableInt(I2S_T *i2s, uint32_t u32Mask);
uint32_t I2S_EnableMCLK(I2S_T *i2s, uint32_t u32BusClock);
void I2S_DisableMCLK(I2S_T *i2s);
void I2S_SetFIFO(I2S_T *i2s, uint32_t u32TxThreshold, uint32_t u32RxThreshold);
void I2S_ConfigureTDM(I2S_T *i2s, uint32_t u32ChannelWidth, uint32_t u32ChannelNum, uint32_t u32SyncWidth);
uint32_t I2S_Open(I2S_T *i2s, uint32_t u32MasterSlave, uint32_t u32SampleRate, uint32_t u32WordWidth, uint32_t u32MonoData, uint32_t u32DataFormat);
/*@}*/ /* end of group I2S_EXPORTED_FUNCTIONS */
/*@}*/ /* end of group I2S_Driver */
/*@}*/ /* end of group Standard_Driver */
#ifdef __cplusplus
}
#endif
#endif

169
bsp/nuvoton/libraries/ma35/StdDriver/inc/nu_kpi.h Normal file
View File

@ -0,0 +1,169 @@
/**************************************************************************//**
* @file nu_kpi.h
* @brief KPI driver header file
*
* SPDX-License-Identifier: Apache-2.0
* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __NU_KPI_H__
#define __NU_KPI_H__
#ifdef __cplusplus
extern "C"
{
#endif
/** @addtogroup Standard_Driver Standard Driver
@{
*/
/** @addtogroup KPI_Driver KPI Driver
@{
*/
/** @addtogroup KPI_EXPORTED_CONSTANTS KPI Exported Constants
@{
*/
#define KPI_ROW_SCAN_DELAY4CLK (0x0 << KPI_KPICONF_SCANROWD_Pos) /*!< Delay cycle when row change */
#define KPI_ROW_SCAN_DELAY8CLK (0x1 << KPI_KPICONF_SCANROWD_Pos) /*!< Delay cycle when row change */
#define KPI_ROW_SCAN_DELAY16CLK (0x2 << KPI_KPICONF_SCANROWD_Pos) /*!< Delay cycle when row change */
#define KPI_ROW_SCAN_DELAY32CLK (0x3 << KPI_KPICONF_SCANROWD_Pos) /*!< Delay cycle when row change */
#define KPI_KEY00 (KPI_KPIKEST0_KEST00_Msk) /*!< Press / Release Key Indicator */
#define KPI_KEY01 (KPI_KPIKEST0_KEST01_Msk) /*!< Press / Release Key Indicator */
#define KPI_KEY02 (KPI_KPIKEST0_KEST02_Msk) /*!< Press / Release Key Indicator */
#define KPI_KEY03 (KPI_KPIKEST0_KEST03_Msk) /*!< Press / Release Key Indicator */
#define KPI_KEY04 (KPI_KPIKEST0_KEST04_Msk) /*!< Press / Release Key Indicator */
#define KPI_KEY05 (KPI_KPIKEST0_KEST05_Msk) /*!< Press / Release Key Indicator */
#define KPI_KEY06 (KPI_KPIKEST0_KEST06_Msk) /*!< Press / Release Key Indicator */
#define KPI_KEY07 (KPI_KPIKEST0_KEST07_Msk) /*!< Press / Release Key Indicator */
#define KPI_KEY10 (KPI_KPIKEST0_KEST10_Msk) /*!< Press / Release Key Indicator */
#define KPI_KEY11 (KPI_KPIKEST0_KEST11_Msk) /*!< Press / Release Key Indicator */
#define KPI_KEY12 (KPI_KPIKEST0_KEST12_Msk) /*!< Press / Release Key Indicator */
#define KPI_KEY13 (KPI_KPIKEST0_KEST13_Msk) /*!< Press / Release Key Indicator */
#define KPI_KEY14 (KPI_KPIKEST0_KEST14_Msk) /*!< Press / Release Key Indicator */
#define KPI_KEY15 (KPI_KPIKEST0_KEST15_Msk) /*!< Press / Release Key Indicator */
#define KPI_KEY16 (KPI_KPIKEST0_KEST16_Msk) /*!< Press / Release Key Indicator */
#define KPI_KEY17 (KPI_KPIKEST0_KEST17_Msk) /*!< Press / Release Key Indicator */
#define KPI_KEY20 (KPI_KPIKEST0_KEST20_Msk) /*!< Press / Release Key Indicator */
#define KPI_KEY21 (KPI_KPIKEST0_KEST21_Msk) /*!< Press / Release Key Indicator */
#define KPI_KEY22 (KPI_KPIKEST0_KEST22_Msk) /*!< Press / Release Key Indicator */
#define KPI_KEY23 (KPI_KPIKEST0_KEST23_Msk) /*!< Press / Release Key Indicator */
#define KPI_KEY24 (KPI_KPIKEST0_KEST24_Msk) /*!< Press / Release Key Indicator */
#define KPI_KEY25 (KPI_KPIKEST0_KEST25_Msk) /*!< Press / Release Key Indicator */
#define KPI_KEY26 (KPI_KPIKEST0_KEST26_Msk) /*!< Press / Release Key Indicator */
#define KPI_KEY27 (KPI_KPIKEST0_KEST27_Msk) /*!< Press / Release Key Indicator */
#define KPI_KEY30 (KPI_KPIKEST0_KEST30_Msk) /*!< Press / Release Key Indicator */
#define KPI_KEY31 (KPI_KPIKEST0_KEST31_Msk) /*!< Press / Release Key Indicator */
#define KPI_KEY32 (KPI_KPIKEST0_KEST32_Msk) /*!< Press / Release Key Indicator */
#define KPI_KEY33 (KPI_KPIKEST0_KEST33_Msk) /*!< Press / Release Key Indicator */
#define KPI_KEY34 (KPI_KPIKEST0_KEST34_Msk) /*!< Press / Release Key Indicator */
#define KPI_KEY35 (KPI_KPIKEST0_KEST35_Msk) /*!< Press / Release Key Indicator */
#define KPI_KEY36 (KPI_KPIKEST0_KEST36_Msk) /*!< Press / Release Key Indicator */
#define KPI_KEY37 (KPI_KPIKEST0_KEST37_Msk) /*!< Press / Release Key Indicator */
#define KPI_KEY40 (KPI_KPIKEST0_KEST40_Msk) /*!< Press / Release Key Indicator */
#define KPI_KEY41 (KPI_KPIKEST0_KEST41_Msk) /*!< Press / Release Key Indicator */
#define KPI_KEY42 (KPI_KPIKEST0_KEST42_Msk) /*!< Press / Release Key Indicator */
#define KPI_KEY43 (KPI_KPIKEST0_KEST43_Msk) /*!< Press / Release Key Indicator */
#define KPI_KEY44 (KPI_KPIKEST0_KEST44_Msk) /*!< Press / Release Key Indicator */
#define KPI_KEY45 (KPI_KPIKEST0_KEST45_Msk) /*!< Press / Release Key Indicator */
#define KPI_KEY46 (KPI_KPIKEST0_KEST46_Msk) /*!< Press / Release Key Indicator */
#define KPI_KEY47 (KPI_KPIKEST0_KEST47_Msk) /*!< Press / Release Key Indicator */
#define KPI_KEY50 (KPI_KPIKEST0_KEST50_Msk) /*!< Press / Release Key Indicator */
#define KPI_KEY51 (KPI_KPIKEST0_KEST51_Msk) /*!< Press / Release Key Indicator */
#define KPI_KEY52 (KPI_KPIKEST0_KEST52_Msk) /*!< Press / Release Key Indicator */
#define KPI_KEY53 (KPI_KPIKEST0_KEST53_Msk) /*!< Press / Release Key Indicator */
#define KPI_KEY54 (KPI_KPIKEST0_KEST54_Msk) /*!< Press / Release Key Indicator */
#define KPI_KEY55 (KPI_KPIKEST0_KEST55_Msk) /*!< Press / Release Key Indicator */
#define KPI_KEY56 (KPI_KPIKEST0_KEST56_Msk) /*!< Press / Release Key Indicator */
#define KPI_KEY57 (KPI_KPIKEST0_KEST57_Msk) /*!< Press / Release Key Indicator */
#define KPI_GET_KEY_STA_REG0(kpi) (kpi->KPIKEST0) /*!< Get Keypad State Register 0 */
#define KPI_GET_KEY_STA_REG1(kpi) (kpi->KPIKEST1) /*!< Get Keypad State Register 1 */
#define KPI_GET_PRESS_KEY_REG0(kpi) (kpi->KPIKPE0) /*!< Get Lower 32 Key Press Event Indicator */
#define KPI_GET_PRESS_KEY_REG1(kpi) (kpi->KPIKPE1) /*!< Get Upper 32 Key Press Event Indicator */
#define KPI_GET_RELEASE_KEY_REG0(kpi) (kpi->KPIKRE0) /*!< Get Lower 32 Key Release Event Indicator */
#define KPI_GET_RELEASE_KEY_REG1(kpi) (kpi->KPIKRE1) /*!< Get Upper 32 Key Release Event Indicator */
#define KPI_EN_WAKEUP(kpi) (kpi->KPICONF |= KPI_KPICONF_WAKEUP_Msk) /*!< Enable Lower Power Wakeup */
#define KPI_DIS_WAKEUP(kpi) (kpi->KPICONF &= ~KPI_KPICONF_WAKEUP_Msk) /*!< Disable Lower Power Wakeup */
/**
* @brief Enable KPI specified interrupt
*
* @param[in] u32InterruptFlag The specified interrupt of KPI module.
* - \ref KPI_KPICONF_PKINTEN_Msk : Press Key Interrupt Enable
* - \ref KPI_KPICONF_RKINTEN_Msk : Release Key Interrupt
* - \ref KPI_KPICONF_INTEN_Msk : Key Interrupt Enable
*
* @return None
*
* @details The function is used to enable KPI specified interrupt.
* \hideinitializer
*/
#define KPI_ENABLE_INT(kpi,u32InterruptFlag) (kpi->KPICONF |= u32InterruptFlag)
/**
* @brief Disable KPI specified interrupt
*
* @param[in] u32InterruptFlag The specified interrupt of KPI module.
* - \ref KPI_KPICONF_PKINTEN_Msk : Press Key Interrupt Enable
* - \ref KPI_KPICONF_RKINTEN_Msk : Release Key Interrupt
* - \ref KPI_KPICONF_INTEN_Msk : Key Interrupt Enable
*
* @return None
*
* @details The function is used to enable KPI specified interrupt.
* \hideinitializer
*/
#define KPI_DISABLE_INT(kpi,u32InterruptFlag) (kpi->KPICONF &= ~u32IntSel)
/**
* @brief Disable 3Key Reset
*
* @return None
*
* @details The function is used to disable 3key Reset.
* \hideinitializer
*/
#define KPI_DISABLE_3KEY_RESET(kpi) (kpi->KPI3KCONF &= ~KPI_KPI3KCONF_EN3KYRST_Msk)
/**
* @brief Get interrupt flag
*
* @return \ref KPI_KPISTATUS_PDWAKE_Msk
* \ref KPI_KPISTATUS_RST3KEY_Msk
* \ref KPI_KPISTATUS_KEYINT_Msk
* \ref KPI_KPISTATUS_RKEYINT_Msk
* \ref KPI_KPISTATUS_PKEYINT_Msk
*
* @details The function is used to disable 3key Reset.
* \hideinitializer
*/
#define KPI_GET_INT_FLAG(kpi) (kpi->KPISTATUS)
void KPI_Open(KPI_T *kpi, uint32_t u32Row, uint32_t u32Col);
void KPI_Close(KPI_T *kpi);
void KPI_ConfigKeyScanTiming(KPI_T *kpi, uint32_t u32PreScale, uint32_t u32Debounce, uint32_t u32ScanDelay);
void KPI_Set3KeyReset(KPI_T *kpi, uint32_t u32Key1, uint32_t u32Key2, uint32_t u32Key3, uint32_t u32RstCnt);
/*@}*/ /* end of group KPI_EXPORTED_FUNCTIONS */
/*@}*/ /* end of group KPI_Driver */
/*@}*/ /* end of group Standard_Driver */
#ifdef __cplusplus
}
#endif
#endif /*__NU_KPI_H__*/

421
bsp/nuvoton/libraries/ma35/StdDriver/inc/nu_pdma.h Normal file
View File

@ -0,0 +1,421 @@
/**************************************************************************//**
* @file nu_pdma.h
* @brief PDMA driver header file
*
* SPDX-License-Identifier: Apache-2.0
* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __NU_PDMA_H__
#define __NU_PDMA_H__
#ifdef __cplusplus
extern "C"
{
#endif
/** @addtogroup Standard_Driver Standard Driver
@{
*/
/** @addtogroup PDMA_Driver PDMA Driver
@{
*/
/** @addtogroup PDMA_EXPORTED_CONSTANTS PDMA Exported Constants
@{
*/
/*---------------------------------------------------------------------------------------------------------*/
/* Operation Mode Constant Definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define PDMA_OP_STOP 0x00000000UL /*!<DMA Stop Mode \hideinitializer */
#define PDMA_OP_BASIC 0x00000001UL /*!<DMA Basic Mode \hideinitializer */
#define PDMA_OP_SCATTER 0x00000002UL /*!<DMA Scatter-gather Mode \hideinitializer */
/*---------------------------------------------------------------------------------------------------------*/
/* Data Width Constant Definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define PDMA_WIDTH_8 0x00000000UL /*!<DMA Transfer Width 8-bit \hideinitializer */
#define PDMA_WIDTH_16 0x00001000UL /*!<DMA Transfer Width 16-bit \hideinitializer */
#define PDMA_WIDTH_32 0x00002000UL /*!<DMA Transfer Width 32-bit \hideinitializer */
/*---------------------------------------------------------------------------------------------------------*/
/* Address Attribute Constant Definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define PDMA_SAR_INC 0x00000000UL /*!<DMA SAR increment \hideinitializer */
#define PDMA_SAR_FIX 0x00000300UL /*!<DMA SAR fix address \hideinitializer */
#define PDMA_DAR_INC 0x00000000UL /*!<DMA DAR increment \hideinitializer */
#define PDMA_DAR_FIX 0x00000C00UL /*!<DMA DAR fix address \hideinitializer */
/*---------------------------------------------------------------------------------------------------------*/
/* Burst Mode Constant Definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define PDMA_REQ_SINGLE 0x00000004UL /*!<DMA Single Request \hideinitializer */
#define PDMA_REQ_BURST 0x00000000UL /*!<DMA Burst Request \hideinitializer */
#define PDMA_BURST_128 0x00000000UL /*!<DMA Burst 128 Transfers \hideinitializer */
#define PDMA_BURST_64 0x00000010UL /*!<DMA Burst 64 Transfers \hideinitializer */
#define PDMA_BURST_32 0x00000020UL /*!<DMA Burst 32 Transfers \hideinitializer */
#define PDMA_BURST_16 0x00000030UL /*!<DMA Burst 16 Transfers \hideinitializer */
#define PDMA_BURST_8 0x00000040UL /*!<DMA Burst 8 Transfers \hideinitializer */
#define PDMA_BURST_4 0x00000050UL /*!<DMA Burst 4 Transfers \hideinitializer */
#define PDMA_BURST_2 0x00000060UL /*!<DMA Burst 2 Transfers \hideinitializer */
#define PDMA_BURST_1 0x00000070UL /*!<DMA Burst 1 Transfers \hideinitializer */
/*---------------------------------------------------------------------------------------------------------*/
/* Table Interrupt Disable Constant Definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define PDMA_TBINTDIS_ENABLE (0x0UL<<PDMA_DSCT_CTL_TBINTDIS_Pos) /*!<DMA Table Interrupt Enabled \hideinitializer */
#define PDMA_TBINTDIS_DISABLE (0x1UL<<PDMA_DSCT_CTL_TBINTDIS_Pos) /*!<DMA Table Interrupt Disabled \hideinitializer */
/*---------------------------------------------------------------------------------------------------------*/
/* Peripheral Transfer Mode Constant Definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define PDMA_MEM 0UL /*!<DMA Connect to Memory \hideinitializer */
#define PDMA_UART0_TX 4UL /*!<DMA Connect to UART0_TX \hideinitializer */
#define PDMA_UART0_RX 5UL /*!<DMA Connect to UART0_RX \hideinitializer */
#define PDMA_UART1_TX 6UL /*!<DMA Connect to UART1_TX \hideinitializer */
#define PDMA_UART1_RX 7UL /*!<DMA Connect to UART1_RX \hideinitializer */
#define PDMA_UART2_TX 8UL /*!<DMA Connect to UART2_TX \hideinitializer */
#define PDMA_UART2_RX 9UL /*!<DMA Connect to UART2_RX \hideinitializer */
#define PDMA_UART3_TX 10UL /*!<DMA Connect to UART3_TX \hideinitializer */
#define PDMA_UART3_RX 11UL /*!<DMA Connect to UART3_RX \hideinitializer */
#define PDMA_UART4_TX 12UL /*!<DMA Connect to UART4_TX \hideinitializer */
#define PDMA_UART4_RX 13UL /*!<DMA Connect to UART4_RX \hideinitializer */
#define PDMA_UART5_TX 14UL /*!<DMA Connect to UART5_TX \hideinitializer */
#define PDMA_UART5_RX 15UL /*!<DMA Connect to UART5_RX \hideinitializer */
#define PDMA_UART6_TX 16UL /*!<DMA Connect to UART6_TX \hideinitializer */
#define PDMA_UART6_RX 17UL /*!<DMA Connect to UART6_RX \hideinitializer */
#define PDMA_UART7_TX 18UL /*!<DMA Connect to UART7_TX \hideinitializer */
#define PDMA_UART7_RX 19UL /*!<DMA Connect to UART7_RX \hideinitializer */
#define PDMA_UART8_TX 20UL /*!<DMA Connect to UART8_TX \hideinitializer */
#define PDMA_UART8_RX 21UL /*!<DMA Connect to UART8_RX \hideinitializer */
#define PDMA_UART9_TX 22UL /*!<DMA Connect to UART9_TX \hideinitializer */
#define PDMA_UART9_RX 23UL /*!<DMA Connect to UART9_RX \hideinitializer */
#define PDMA_UART10_TX 24UL /*!<DMA Connect to UART10_TX \hideinitializer */
#define PDMA_UART10_RX 25UL /*!<DMA Connect to UART10_RX \hideinitializer */
#define PDMA_UART11_TX 26UL /*!<DMA Connect to UART11_TX \hideinitializer */
#define PDMA_UART11_RX 27UL /*!<DMA Connect to UART11_RX \hideinitializer */
#define PDMA_UART12_TX 28UL /*!<DMA Connect to UART12_TX \hideinitializer */
#define PDMA_UART12_RX 29UL /*!<DMA Connect to UART12_RX \hideinitializer */
#define PDMA_UART13_TX 30UL /*!<DMA Connect to UART13_TX \hideinitializer */
#define PDMA_UART13_RX 31UL /*!<DMA Connect to UART13_RX \hideinitializer */
#define PDMA_UART14_TX 32UL /*!<DMA Connect to UART14_TX \hideinitializer */
#define PDMA_UART14_RX 33UL /*!<DMA Connect to UART14_RX \hideinitializer */
#define PDMA_UART15_TX 34UL /*!<DMA Connect to UART15_TX \hideinitializer */
#define PDMA_UART15_RX 35UL /*!<DMA Connect to UART15_RX \hideinitializer */
#define PDMA_UART16_TX 36UL /*!<DMA Connect to UART16_TX \hideinitializer */
#define PDMA_UART16_RX 37UL /*!<DMA Connect to UART16_RX \hideinitializer */
#define PDMA_QSPI0_TX 54UL /*!<DMA Connect to QSPI0_TX \hideinitializer */
#define PDMA_QSPI0_RX 55UL /*!<DMA Connect to QSPI0_RX \hideinitializer */
#define PDMA_QSPI1_TX 56UL /*!<DMA Connect to QSPI1_TX \hideinitializer */
#define PDMA_QSPI1_RX 57UL /*!<DMA Connect to QSPI1_RX \hideinitializer */
#define PDMA_SPI0_TX 60UL /*!<DMA Connect to SPI0_TX \hideinitializer */
#define PDMA_SPI0_RX 61UL /*!<DMA Connect to SPI0_RX \hideinitializer */
#define PDMA_SPI1_TX 62UL /*!<DMA Connect to SPI1_TX \hideinitializer */
#define PDMA_SPI1_RX 63UL /*!<DMA Connect to SPI1_RX \hideinitializer */
#define PDMA_SPI2_TX 64UL /*!<DMA Connect to SPI2_TX \hideinitializer */
#define PDMA_SPI2_RX 65UL /*!<DMA Connect to SPI2_RX \hideinitializer */
#define PDMA_SPI3_TX 66UL /*!<DMA Connect to SPI3_TX \hideinitializer */
#define PDMA_SPI3_RX 67UL /*!<DMA Connect to SPI3_RX \hideinitializer */
#define PDMA_I2C0_TX 70UL /*!<DMA Connect to I2C0_TX \hideinitializer */
#define PDMA_I2C0_RX 71UL /*!<DMA Connect to I2C0_RX \hideinitializer */
#define PDMA_I2C1_TX 72UL /*!<DMA Connect to I2C1_TX \hideinitializer */
#define PDMA_I2C1_RX 73UL /*!<DMA Connect to I2C1_RX \hideinitializer */
#define PDMA_I2C2_TX 74UL /*!<DMA Connect to I2C2_TX \hideinitializer */
#define PDMA_I2C2_RX 75UL /*!<DMA Connect to I2C2_RX \hideinitializer */
#define PDMA_I2C3_TX 76UL /*!<DMA Connect to I2C3_TX \hideinitializer */
#define PDMA_I2C3_RX 77UL /*!<DMA Connect to I2C3_RX \hideinitializer */
#define PDMA_I2C4_TX 78UL /*!<DMA Connect to I2C4_TX \hideinitializer */
#define PDMA_I2C4_RX 79UL /*!<DMA Connect to I2C4_RX \hideinitializer */
#define PDMA_I2C5_TX 80UL /*!<DMA Connect to I2C5_TX \hideinitializer */
#define PDMA_I2C5_RX 81UL /*!<DMA Connect to I2C5_RX \hideinitializer */
#define PDMA_I2S0_TX 86UL /*!<DMA Connect to I2S0_TX \hideinitializer */
#define PDMA_I2S0_RX 87UL /*!<DMA Connect to I2S0_RX \hideinitializer */
#define PDMA_I2S1_TX 88UL /*!<DMA Connect to I2S1_TX \ideinitializer */
#define PDMA_I2S1_RX 89UL /*!<DMA Connect to I2S1_RX \ideinitializer */
#define PDMA_TMR0 94UL /*!<DMA Connect to TMR0 \hideinitializer */
#define PDMA_TMR1 95UL /*!<DMA Connect to TMR1 \hideinitializer */
#define PDMA_TMR2 96UL /*!<DMA Connect to TMR2 \hideinitializer */
#define PDMA_TMR3 97UL /*!<DMA Connect to TMR3 \hideinitializer */
#define PDMA_TMR4 98UL /*!<DMA Connect to TMR4 \hideinitializer */
#define PDMA_TMR5 99UL /*!<DMA Connect to TMR5 \hideinitializer */
#define PDMA_TMR6 100UL /*!<DMA Connect to TMR6 \hideinitializer */
#define PDMA_TMR7 101UL /*!<DMA Connect to TMR7 \hideinitializer */
#define PDMA_TMR8 102UL /*!<DMA Connect to TMR8 \hideinitializer */
#define PDMA_TMR9 103UL /*!<DMA Connect to TMR9 \hideinitializer */
#define PDMA_TMR10 104UL /*!<DMA Connect to TMR10 \hideinitializer */
#define PDMA_TMR11 105UL /*!<DMA Connect to TMR11 \hideinitializer */
#define PDMA_EPWM0_P1_RX 110UL /*!<DMA Connect to EPWM0_P1_RX \hideinitializer */
#define PDMA_EPWM0_P2_RX 111UL /*!<DMA Connect to EPWM0_P2_RX \hideinitializer */
#define PDMA_EPWM0_P3_RX 112UL /*!<DMA Connect to EPWM0_P3_RX \hideinitializer */
#define PDMA_EPWM1_P1_RX 113UL /*!<DMA Connect to EPWM1_P1_RX \hideinitializer */
#define PDMA_EPWM1_P2_RX 114UL /*!<DMA Connect to EPWM1_P2_RX \hideinitializer */
#define PDMA_EPWM1_P3_RX 115UL /*!<DMA Connect to EPWM1_P3_RX \hideinitializer */
#define PDMA_EPWM2_P1_RX 116UL /*!<DMA Connect to EPWM2_P1_RX \hideinitializer */
#define PDMA_EPWM2_P2_RX 117UL /*!<DMA Connect to EPWM2_P2_RX \hideinitializer */
#define PDMA_EPWM2_P3_RX 118UL /*!<DMA Connect to EPWM2_P3_RX \hideinitializer */
#define PDMA_EPWM0_CH0_TX 122UL /*!<DMA Connect to EPWM0_CH0_TX \hideinitializer */
#define PDMA_EPWM0_CH1_TX 123UL /*!<DMA Connect to EPWM0_CH1_TX \hideinitializer */
#define PDMA_EPWM0_CH2_TX 124UL /*!<DMA Connect to EPWM0_CH2_TX \hideinitializer */
#define PDMA_EPWM0_CH3_TX 125UL /*!<DMA Connect to EPWM0_CH3_TX \hideinitializer */
#define PDMA_EPWM0_CH4_TX 126UL /*!<DMA Connect to EPWM0_CH4_TX \hideinitializer */
#define PDMA_EPWM0_CH5_TX 127UL /*!<DMA Connect to EPWM0_CH5_TX \hideinitializer */
#define PDMA_EPWM1_CH0_TX 128UL /*!<DMA Connect to EPWM1_CH0_TX \hideinitializer */
#define PDMA_EPWM1_CH1_TX 129UL /*!<DMA Connect to EPWM1_CH1_TX \hideinitializer */
#define PDMA_EPWM1_CH2_TX 130UL /*!<DMA Connect to EPWM1_CH2_TX \hideinitializer */
#define PDMA_EPWM1_CH3_TX 131UL /*!<DMA Connect to EPWM1_CH3_TX \hideinitializer */
#define PDMA_EPWM1_CH4_TX 132UL /*!<DMA Connect to EPWM1_CH4_TX \hideinitializer */
#define PDMA_EPWM1_CH5_TX 133UL /*!<DMA Connect to EPWM1_CH5_TX \hideinitializer */
#define PDMA_EPWM2_CH0_TX 134UL /*!<DMA Connect to EPWM2_CH0_TX \hideinitializer */
#define PDMA_EPWM2_CH1_TX 135UL /*!<DMA Connect to EPWM2_CH1_TX \hideinitializer */
#define PDMA_EPWM2_CH2_TX 136UL /*!<DMA Connect to EPWM2_CH2_TX \hideinitializer */
#define PDMA_EPWM2_CH3_TX 137UL /*!<DMA Connect to EPWM2_CH3_TX \hideinitializer */
#define PDMA_EPWM2_CH4_TX 138UL /*!<DMA Connect to EPWM2_CH4_TX \hideinitializer */
#define PDMA_EPWM2_CH5_TX 139UL /*!<DMA Connect to EPWM2_CH5_TX \hideinitializer */
#define PDMA_EADC0_RX 146UL /*!<DMA Connect to EADC0_RX \hideinitializer */
/*---------------------------------------------------------------------------------------------------------*/
/* Interrupt Type Constant Definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define PDMA_INT_TRANS_DONE 0x00000000UL /*!<Transfer Done Interrupt \hideinitializer */
#define PDMA_INT_TEMPTY 0x00000001UL /*!<Table Empty Interrupt \hideinitializer */
#define PDMA_INT_TIMEOUT 0x00000002UL /*!<Timeout Interrupt \hideinitializer */
/*@}*/ /* end of group PDMA_EXPORTED_CONSTANTS */
/** @addtogroup PDMA_EXPORTED_FUNCTIONS PDMA Exported Functions
@{
*/
/**
* @brief Get PDMA Interrupt Status
*
* @param[in] pdma The pointer of the specified PDMA module
*
* @return None
*
* @details This macro gets the interrupt status.
* \hideinitializer
*/
#define PDMA_GET_INT_STATUS(pdma) ((uint32_t)(pdma->INTSTS))
/**
* @brief Get Transfer Done Interrupt Status
*
* @param[in] pdma The pointer of the specified PDMA module
*
* @return None
*
* @details Get the transfer done Interrupt status.
* \hideinitializer
*/
#define PDMA_GET_TD_STS(pdma) ((uint32_t)(pdma->TDSTS))
/**
* @brief Clear Transfer Done Interrupt Status
*
* @param[in] pdma The pointer of the specified PDMA module
*
* @param[in] u32Mask The channel mask
*
* @return None
*
* @details Clear the transfer done Interrupt status.
* \hideinitializer
*/
#define PDMA_CLR_TD_FLAG(pdma,u32Mask) ((uint32_t)(pdma->TDSTS = (u32Mask)))
/**
* @brief Get Target Abort Interrupt Status
*
* @param[in] pdma The pointer of the specified PDMA module
*
* @return None
*
* @details Get the target abort Interrupt status.
* \hideinitializer
*/
#define PDMA_GET_ABORT_STS(pdma) ((uint32_t)(pdma->ABTSTS))
/**
* @brief Clear Target Abort Interrupt Status
*
* @param[in] pdma The pointer of the specified PDMA module
*
* @param[in] u32Mask The channel mask
*
* @return None
*
* @details Clear the target abort Interrupt status.
* \hideinitializer
*/
#define PDMA_CLR_ABORT_FLAG(pdma,u32Mask) ((uint32_t)(pdma->ABTSTS = (u32Mask)))
/**
* @brief Get Alignment Interrupt Status
*
* @param[in] pdma The pointer of the specified PDMA module
*
* @return None
*
* @details Get Alignment Interrupt status.
* \hideinitializer
*/
#define PDMA_GET_ALIGN_STS(pdma) ((uint32_t)(PDMA->ALIGN))
/**
* @brief Clear Alignment Interrupt Status
*
* @param[in] pdma The pointer of the specified PDMA module
* @param[in] u32Mask The channel mask
*
* @return None
*
* @details Clear the Alignment Interrupt status.
* \hideinitializer
*/
#define PDMA_CLR_ALIGN_FLAG(pdma,u32Mask) ((uint32_t)(pdma->ALIGN = (u32Mask)))
/**
* @brief Clear Timeout Interrupt Status
*
* @param[in] pdma The pointer of the specified PDMA module
* @param[in] u32Ch The selected channel
*
* @return None
*
* @details Clear the selected channel timeout interrupt status.
* \hideinitializer
*/
#define PDMA_CLR_TMOUT_FLAG(pdma,u32Ch) ((uint32_t)(pdma->INTSTS = (1 << ((u32Ch) + 8))))
/**
* @brief Check Channel Status
*
* @param[in] pdma The pointer of the specified PDMA module
* @param[in] u32Ch The selected channel
*
* @retval 0 Idle state
* @retval 1 Busy state
*
* @details Check the selected channel is busy or not.
* \hideinitializer
*/
#define PDMA_IS_CH_BUSY(pdma,u32Ch) ((uint32_t)(pdma->TRGSTS & (1 << (u32Ch)))? 1 : 0)
/**
* @brief Set Source Address
*
* @param[in] pdma The pointer of the specified PDMA module
* @param[in] u32Ch The selected channel
* @param[in] u32Addr The selected address
*
* @return None
*
* @details This macro set the selected channel source address.
* \hideinitializer
*/
#define PDMA_SET_SRC_ADDR(pdma,u32Ch, u32Addr) ((uint32_t)(pdma->DSCT[(u32Ch)].SA = (u32Addr)))
/**
* @brief Set Destination Address
*
* @param[in] pdma The pointer of the specified PDMA module
* @param[in] u32Ch The selected channel
* @param[in] u32Addr The selected address
*
* @return None
*
* @details This macro set the selected channel destination address.
* \hideinitializer
*/
#define PDMA_SET_DST_ADDR(pdma,u32Ch, u32Addr) ((uint32_t)(pdma->DSCT[(u32Ch)].DA = (u32Addr)))
/**
* @brief Set Transfer Count
*
* @param[in] pdma The pointer of the specified PDMA module
* @param[in] u32Ch The selected channel
* @param[in] u32TransCount Transfer Count
*
* @return None
*
* @details This macro set the selected channel transfer count.
* \hideinitializer
*/
#define PDMA_SET_TRANS_CNT(pdma,u32Ch, u32TransCount) ((uint32_t)(pdma->DSCT[(u32Ch)].CTL=(pdma->DSCT[(u32Ch)].CTL&~PDMA_DSCT_CTL_TXCNT_Msk)|(((u32TransCount)-1) << PDMA_DSCT_CTL_TXCNT_Pos)))
/**
* @brief Set Scatter-gather descriptor Address
*
* @param[in] pdma The pointer of the specified PDMA module
* @param[in] u32Ch The selected channel
* @param[in] u32Addr The descriptor address
*
* @return None
*
* @details This macro set the selected channel scatter-gather descriptor address.
* \hideinitializer
*/
#define PDMA_SET_SCATTER_DESC(pdma,u32Ch, u32Addr) ((uint32_t)(pdma->DSCT[(u32Ch)].NEXT = (u32Addr) - (pdma->SCATBA)))
/**
* @brief Stop the channel
*
* @param[in] pdma The pointer of the specified PDMA module
*
* @param[in] u32Ch The selected channel
*
* @return None
*
* @details This macro stop the selected channel.
* \hideinitializer
*/
#define PDMA_STOP(pdma,u32Ch) ((uint32_t)(pdma->PAUSE = (1 << (u32Ch))))
/**
* @brief Pause the channel
*
* @param[in] pdma The pointer of the specified PDMA module
*
* @param[in] u32Ch The selected channel
*
* @return None
*
* @details This macro pause the selected channel.
* \hideinitializer
*/
#define PDMA_PAUSE(pdma,u32Ch) ((uint32_t)(pdma->PAUSE = (1 << (u32Ch))))
/*---------------------------------------------------------------------------------------------------------*/
/* Define PDMA functions prototype */
/*---------------------------------------------------------------------------------------------------------*/
void PDMA_Open(PDMA_T *pdma, uint32_t u32Mask);
void PDMA_Close(PDMA_T *pdma);
void PDMA_SetTransferCnt(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32Width, uint32_t u32TransCount);
void PDMA_SetTransferAddr(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32SrcAddr, uint32_t u32SrcCtrl, uint32_t u32DstAddr, uint32_t u32DstCtrl);
void PDMA_SetTransferMode(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32Peripheral, uint32_t u32ScatterEn, uint32_t u32DescAddr);
void PDMA_SetBurstType(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32BurstType, uint32_t u32BurstSize);
void PDMA_EnableTimeout(PDMA_T *pdma, uint32_t u32Mask);
void PDMA_DisableTimeout(PDMA_T *pdma, uint32_t u32Mask);
void PDMA_SetTimeOut(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32OnOff, uint32_t u32TimeOutCnt);
void PDMA_Trigger(PDMA_T *pdma, uint32_t u32Ch);
void PDMA_EnableInt(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32Mask);
void PDMA_DisableInt(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32Mask);
void PDMA_SetStride(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32DestLen, uint32_t u32SrcLen, uint32_t u32TransCount);
void PDMA_SetRepeat(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32DestInterval, uint32_t u32SrcInterval, uint32_t u32RepeatCount);
/*@}*/ /* end of group PDMA_EXPORTED_FUNCTIONS */
/*@}*/ /* end of group PDMA_Driver */
/*@}*/ /* end of group Standard_Driver */
#ifdef __cplusplus
}
#endif
#endif /* __PDMA_H__ */

388
bsp/nuvoton/libraries/ma35/StdDriver/inc/nu_qei.h Normal file
View File

@ -0,0 +1,388 @@
/**************************************************************************//**
* @file nu_qei.h
* @brief Quadrature Encoder Interface (QEI) driver header file
*
* SPDX-License-Identifier: Apache-2.0
* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __NU_QEI_H__
#define __NU_QEI_H__
#ifdef __cplusplus
extern "C"
{
#endif
/** @addtogroup Standard_Driver Standard Driver
@{
*/
/** @addtogroup QEI_Driver QEI Driver
@{
*/
/** @addtogroup QEI_EXPORTED_CONSTANTS QEI Exported Constants
@{
*/
/*---------------------------------------------------------------------------------------------------------*/
/* QEI counting mode selection constants definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define QEI_CTL_X4_FREE_COUNTING_MODE (0x0<<QEI_CTL_MODE_Pos) /*!< QEI operate in X4 free-counting mode \hideinitializer */
#define QEI_CTL_X2_FREE_COUNTING_MODE (0x1<<QEI_CTL_MODE_Pos) /*!< QEI operate in X2 free-counting mode \hideinitializer */
#define QEI_CTL_X4_COMPARE_COUNTING_MODE (0x2<<QEI_CTL_MODE_Pos) /*!< QEI operate in X4 compare-counting mode \hideinitializer */
#define QEI_CTL_X2_COMPARE_COUNTING_MODE (0x3<<QEI_CTL_MODE_Pos) /*!< QEI operate in X2 compare-counting mode \hideinitializer */
/*---------------------------------------------------------------------------------------------------------*/
/* QEI noise filter clock pre-divide selection constants definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define QEI_CTL_NFCLKSEL_DIV1 (0x0<<QEI_CTL_NFCLKSEL_Pos) /*!< The sampling frequency of the noise filter is QEI_CLK \hideinitializer */
#define QEI_CTL_NFCLKSEL_DIV2 (0x1<<QEI_CTL_NFCLKSEL_Pos) /*!< The sampling frequency of the noise filter is QEI_CLK/2 \hideinitializer */
#define QEI_CTL_NFCLKSEL_DIV4 (0x2<<QEI_CTL_NFCLKSEL_Pos) /*!< The sampling frequency of the noise filter is QEI_CLK/4 \hideinitializer */
#define QEI_CTL_NFCLKSEL_DIV16 (0x3<<QEI_CTL_NFCLKSEL_Pos) /*!< The sampling frequency of the noise filter is QEI_CLK/16 \hideinitializer */
#define QEI_CTL_NFCLKSEL_DIV32 (0x4<<QEI_CTL_NFCLKSEL_Pos) /*!< The sampling frequency of the noise filter is QEI_CLK/32 \hideinitializer */
#define QEI_CTL_NFCLKSEL_DIV64 (0x5<<QEI_CTL_NFCLKSEL_Pos) /*!< The sampling frequency of the noise filter is QEI_CLK/64 \hideinitializer */
/*@}*/ /* end of group QEI_EXPORTED_CONSTANTS */
/** @addtogroup QEI_EXPORTED_FUNCTIONS QEI Exported Functions
@{
*/
/**
* @brief Disable QEI compare function
* @param[in] qei The pointer of the specified QEI module.
* @return None
* @details This macro disable QEI counter compare function.
* \hideinitializer
*/
#define QEI_DISABLE_CNT_CMP(qei) ((qei)->CTL &= (~QEI_CTL_CMPEN_Msk))
/**
* @brief Enable QEI compare function
* @param[in] qei The pointer of the specified QEI module.
* @return None
* @details This macro enable QEI counter compare function.
* \hideinitializer
*/
#define QEI_ENABLE_CNT_CMP(qei) ((qei)->CTL |= QEI_CTL_CMPEN_Msk)
/**
* @brief Disable QEI index latch function
* @param[in] qei The pointer of the specified QEI module.
* @return None
* @details This macro disable QEI index trigger counter latch function.
* \hideinitializer
*/
#define QEI_DISABLE_INDEX_LATCH(qei) ((qei)->CTL &= (~QEI_CTL_IDXLATEN_Msk))
/**
* @brief Enable QEI index latch function
* @param[in] qei The pointer of the specified QEI module.
* @return None
* @details This macro enable QEI index trigger counter latch function.
* \hideinitializer
*/
#define QEI_ENABLE_INDEX_LATCH(qei) ((qei)->CTL |= QEI_CTL_IDXLATEN_Msk)
/**
* @brief Disable QEI index reload function
* @param[in] qei The pointer of the specified QEI module.
* @return None
* @details This macro disable QEI index trigger counter reload function.
* \hideinitializer
*/
#define QEI_DISABLE_INDEX_RELOAD(qei) ((qei)->CTL &= (~QEI_CTL_IDXRLDEN_Msk))
/**
* @brief Enable QEI index reload function
* @param[in] qei The pointer of the specified QEI module.
* @return None
* @details This macro enable QEI index trigger counter reload function.
* \hideinitializer
*/
#define QEI_ENABLE_INDEX_RELOAD(qei) ((qei)->CTL |= QEI_CTL_IDXRLDEN_Msk)
/**
* @brief Disable QEI input
* @param[in] qei The pointer of the specified QEI module.
* @param[in] u32InputType Input signal type.
* - \ref QEI_CTL_CHAEN_Msk : QEA input
* - \ref QEI_CTL_CHAEN_Msk : QEB input
* - \ref QEI_CTL_IDXEN_Msk : IDX input
* @return None
* @details This macro disable specified QEI signal input.
* \hideinitializer
*/
#define QEI_DISABLE_INPUT(qei, u32InputType) ((qei)->CTL &= ~(u32InputType))
/**
* @brief Enable QEI input
* @param[in] qei The pointer of the specified QEI module.
* @param[in] u32InputType Input signal type .
* - \ref QEI_CTL_CHAEN_Msk : QEA input
* - \ref QEI_CTL_CHBEN_Msk : QEB input
* - \ref QEI_CTL_IDXEN_Msk : IDX input
* @return None
* @details This macro enable specified QEI signal input.
* \hideinitializer
*/
#define QEI_ENABLE_INPUT(qei, u32InputType) ((qei)->CTL |= (u32InputType))
/**
* @brief Disable inverted input polarity
* @param[in] qei The pointer of the specified QEI module.
* @param[in] u32InputType Input signal type .
* - \ref QEI_CTL_CHAINV_Msk : QEA Input
* - \ref QEI_CTL_CHBINV_Msk : QEB Input
* - \ref QEI_CTL_IDXINV_Msk : IDX Input
* @return None
* @details This macro disable specified QEI signal inverted input polarity.
* \hideinitializer
*/
#define QEI_DISABLE_INPUT_INV(qei, u32InputType) ((qei)->CTL &= ~(u32InputType))
/**
* @brief Enable inverted input polarity
* @param[in] qei The pointer of the specified QEI module.
* @param[in] u32InputType Input signal type.
* - \ref QEI_CTL_CHAINV_Msk : QEA Input
* - \ref QEI_CTL_CHBINV_Msk : QEB Input
* - \ref QEI_CTL_IDXINV_Msk : IDX Input
* @return None
* @details This macro inverse specified QEI signal input polarity.
* \hideinitializer
*/
#define QEI_ENABLE_INPUT_INV(qei, u32InputType) ((qei)->CTL |= (u32InputType))
/**
* @brief Disable QEI interrupt
* @param[in] qei The pointer of the specified QEI module.
* @param[in] u32IntSel Interrupt type selection.
* - \ref QEI_CTL_DIRIEN_Msk : Direction change interrupt
* - \ref QEI_CTL_OVUNIEN_Msk : Counter overflow or underflow interrupt
* - \ref QEI_CTL_CMPIEN_Msk : Compare-match interrupt
* - \ref QEI_CTL_IDXIEN_Msk : Index detected interrupt
* @return None
* @details This macro disable specified QEI interrupt.
* \hideinitializer
*/
#define QEI_DISABLE_INT(qei, u32IntSel) ((qei)->CTL &= ~(u32IntSel))
/**
* @brief Enable QEI interrupt
* @param[in] qei The pointer of the specified QEI module.
* @param[in] u32IntSel Interrupt type selection.
* - \ref QEI_CTL_DIRIEN_Msk : Direction change interrupt
* - \ref QEI_CTL_OVUNIEN_Msk : Counter overflow or underflow interrupt
* - \ref QEI_CTL_CMPIEN_Msk : Compare-match interrupt
* - \ref QEI_CTL_IDXIEN_Msk : Index detected interrupt
* @return None
* @details This macro enable specified QEI interrupt.
* \hideinitializer
*/
#define QEI_ENABLE_INT(qei, u32IntSel) ((qei)->CTL |= (u32IntSel))
/**
* @brief Disable QEI noise filter
* @param[in] qei The pointer of the specified QEI module.
* @return None
* @details This macro disable QEI noise filter function.
* \hideinitializer
*/
#define QEI_DISABLE_NOISE_FILTER(qei) ((qei)->CTL |= QEI_CTL_NFDIS_Msk)
/**
* @brief Enable QEI noise filter
* @param[in] qei The pointer of the specified QEI module.
* @param[in] u32ClkSel The sampling frequency of the noise filter clock.
* - \ref QEI_CTL_NFCLKSEL_DIV1
* - \ref QEI_CTL_NFCLKSEL_DIV2
* - \ref QEI_CTL_NFCLKSEL_DIV4
* - \ref QEI_CTL_NFCLKSEL_DIV16
* - \ref QEI_CTL_NFCLKSEL_DIV32
* - \ref QEI_CTL_NFCLKSEL_DIV64
* @return None
* @details This macro enable QEI noise filter function and select noise filter clock.
* \hideinitializer
*/
#define QEI_ENABLE_NOISE_FILTER(qei, u32ClkSel) ((qei)->CTL = ((qei)->CTL & (~(QEI_CTL_NFDIS_Msk|QEI_CTL_NFCLKSEL_Msk))) | (u32ClkSel))
/**
* @brief Get QEI counter value
* @param[in] qei The pointer of the specified QEI module.
* @return QEI pulse counter register value.
* @details This macro get QEI pulse counter value.
* \hideinitializer
*/
#define QEI_GET_CNT_VALUE(qei) ((qei)->CNT)
/**
* @brief Get QEI counting direction
* @param[in] qei The pointer of the specified QEI module.
* @retval 0 QEI counter is in down-counting.
* @retval 1 QEI counter is in up-counting.
* @details This macro get QEI counting direction.
* \hideinitializer
*/
#define QEI_GET_DIR(qei) (((qei)->STATUS & (QEI_STATUS_DIRF_Msk))?1:0)
/**
* @brief Get QEI counter hold value
* @param[in] qei The pointer of the specified QEI module.
* @return QEI pulse counter hold register value.
* @details This macro get QEI pulse counter hold value, which is updated with counter value in hold counter value control.
* \hideinitializer
*/
#define QEI_GET_HOLD_VALUE(qei) ((qei)->CNTHOLD)
/**
* @brief Get QEI counter index latch value
* @param[in] qei The pointer of the specified QEI module.
* @return QEI pulse counter index latch value
* @details This macro get QEI pulse counter index latch value, which is updated with counter value when the index is detected.
* \hideinitializer
*/
#define QEI_GET_INDEX_LATCH_VALUE(qei) ((qei)->CNTLATCH)
/**
* @brief Set QEI counter index latch value
* @param[in] qei The pointer of the specified QEI module.
* @param[in] u32Val The latch value.
* @return QEI pulse counter index latch value
* @details This macro set QEI pulse counter index latch value, which is updated with counter value when the index is detected.
* \hideinitializer
*/
#define QEI_SET_INDEX_LATCH_VALUE(qei,u32Val) ((qei)->CNTLATCH = (u32Val))
/**
* @brief Get QEI interrupt flag status
* @param[in] qei The pointer of the specified QEI module.
* @param[in] u32IntSel Interrupt type selection.
* - \ref QEI_STATUS_DIRF_Msk : Counting direction flag
* - \ref QEI_STATUS_DIRCHGF_Msk : Direction change flag
* - \ref QEI_STATUS_OVUNF_Msk : Counter overflow or underflow flag
* - \ref QEI_STATUS_CMPF_Msk : Compare-match flag
* - \ref QEI_STATUS_IDXF_Msk : Index detected flag
* @retval 0 QEI specified interrupt flag is not set.
* @retval 1 QEI specified interrupt flag is set.
* @details This macro get QEI specified interrupt flag status.
* \hideinitializer
*/
#define QEI_GET_INT_FLAG(qei, u32IntSel) (((qei)->STATUS & (u32IntSel))?1:0)
/**
* @brief Clear QEI interrupt flag
* @param[in] qei The pointer of the specified QEI module.
* @param[in] u32IntSel Interrupt type selection.
* - \ref QEI_STATUS_DIRCHGF_Msk : Direction change flag
* - \ref QEI_STATUS_OVUNF_Msk : Counter overflow or underflow flag
* - \ref QEI_STATUS_CMPF_Msk : Compare-match flag
* - \ref QEI_STATUS_IDXF_Msk : Index detected flag
* @return None
* @details This macro clear QEI specified interrupt flag.
* \hideinitializer
*/
#define QEI_CLR_INT_FLAG(qei, u32IntSel) ((qei)->STATUS = (u32IntSel))
/**
* @brief Set QEI counter compare value
* @param[in] qei The pointer of the specified QEI module.
* @param[in] u32Value The counter compare value.
* @return None
* @details This macro set QEI pulse counter compare value.
* \hideinitializer
*/
#define QEI_SET_CNT_CMP(qei, u32Value) ((qei)->CNTCMP = (u32Value))
/**
* @brief Set QEI counter value
* @param[in] qei The pointer of the specified QEI module.
* @param[in] u32Value The counter compare value.
* @return None
* @details This macro set QEI pulse counter value.
* \hideinitializer
*/
#define QEI_SET_CNT_VALUE(qei, u32Value) ((qei)->CNT = (u32Value))
/**
* @brief Enable QEI counter hold mode
* @param[in] qei The pointer of the specified QEI module.
* @param[in] u32Type The triggered type.
* - \ref QEI_CTL_HOLDCNT_Msk : Hold QEI_CNT control
* - \ref QEI_CTL_HOLDTMR0_Msk : Hold QEI_CNT by Timer0
* - \ref QEI_CTL_HOLDTMR1_Msk : Hold QEI_CNT by Timer1
* - \ref QEI_CTL_HOLDTMR2_Msk : Hold QEI_CNT by Timer2
* - \ref QEI_CTL_HOLDTMR3_Msk : Hold QEI_CNT by Timer3
* @return None
* @details This macro enable QEI counter hold mode.
* \hideinitializer
*/
#define QEI_ENABLE_HOLD_TRG_SRC(qei, u32Type) ((qei)->CTL |= (u32Type))
/**
* @brief Disable QEI counter hold mode
* @param[in] qei The pointer of the specified QEI module.
* @param[in] u32Type The triggered type.
* - \ref QEI_CTL_HOLDCNT_Msk : Hold QEI_CNT control
* - \ref QEI_CTL_HOLDTMR0_Msk : Hold QEI_CNT by Timer0
* - \ref QEI_CTL_HOLDTMR1_Msk : Hold QEI_CNT by Timer1
* - \ref QEI_CTL_HOLDTMR2_Msk : Hold QEI_CNT by Timer2
* - \ref QEI_CTL_HOLDTMR3_Msk : Hold QEI_CNT by Timer3
* @return None
* @details This macro disable QEI counter hold mode.
* \hideinitializer
*/
#define QEI_DISABLE_HOLD_TRG_SRC(qei, u32Type) ((qei)->CTL &= ~(u32Type))
/**
* @brief Set QEI maximum count value
* @param[in] qei The pointer of the specified QEI module.
* @param[in] u32Value The counter maximum value.
* @return QEI maximum count value
* @details This macro set QEI maximum count value.
* \hideinitializer
*/
#define QEI_SET_CNT_MAX(qei, u32Value) ((qei)->CNTMAX = (u32Value))
/**
* @brief Set QEI counting mode
* @param[in] qei The pointer of the specified QEI module.
* @param[in] u32Mode QEI counting mode.
* - \ref QEI_CTL_X4_FREE_COUNTING_MODE
* - \ref QEI_CTL_X2_FREE_COUNTING_MODE
* - \ref QEI_CTL_X4_COMPARE_COUNTING_MODE
* - \ref QEI_CTL_X2_COMPARE_COUNTING_MODE
* @return None
* @details This macro set QEI counting mode.
* \hideinitializer
*/
#define QEI_SET_CNT_MODE(qei, u32Mode) ((qei)->CTL = ((qei)->CTL & (~QEI_CTL_MODE_Msk)) | (u32Mode))
void QEI_Close(QEI_T *qei);
void QEI_DisableInt(QEI_T *qei, uint32_t u32IntSel);
void QEI_EnableInt(QEI_T *qei, uint32_t u32IntSel);
void QEI_Open(QEI_T *qei, uint32_t u32Mode, uint32_t u32Value);
void QEI_Start(QEI_T *qei);
void QEI_Stop(QEI_T *qei);
/*@}*/ /* end of group QEI_EXPORTED_FUNCTIONS */
/*@}*/ /* end of group QEI_Driver */
/*@}*/ /* end of group Standard_Driver */
#ifdef __cplusplus
}
#endif
#endif /* __NU_QEI_H__ */

379
bsp/nuvoton/libraries/ma35/StdDriver/inc/nu_qspi.h Normal file
View File

@ -0,0 +1,379 @@
/**************************************************************************//**
* @file nu_qspi.h
* @brief QSPI driver header file
*
* SPDX-License-Identifier: Apache-2.0
* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __NU_QSPI_H__
#define __NU_QSPI_H__
#ifdef __cplusplus
extern "C"
{
#endif
/** @addtogroup Standard_Driver Standard Driver
@{
*/
/** @addtogroup QSPI_Driver QSPI Driver
@{
*/
/** @addtogroup QSPI_EXPORTED_CONSTANTS QSPI Exported Constants
@{
*/
#define QSPI_MODE_0 (QSPI_CTL_TXNEG_Msk) /*!< CLKPOL=0; RXNEG=0; TXNEG=1 \hideinitializer */
#define QSPI_MODE_1 (QSPI_CTL_RXNEG_Msk) /*!< CLKPOL=0; RXNEG=1; TXNEG=0 \hideinitializer */
#define QSPI_MODE_2 (QSPI_CTL_CLKPOL_Msk | QSPI_CTL_RXNEG_Msk) /*!< CLKPOL=1; RXNEG=1; TXNEG=0 \hideinitializer */
#define QSPI_MODE_3 (QSPI_CTL_CLKPOL_Msk | QSPI_CTL_TXNEG_Msk) /*!< CLKPOL=1; RXNEG=0; TXNEG=1 \hideinitializer */
#define QSPI_SLAVE (QSPI_CTL_SLAVE_Msk) /*!< Set as slave \hideinitializer */
#define QSPI_MASTER (0x0U) /*!< Set as master \hideinitializer */
#define QSPI_SS (QSPI_SSCTL_SS_Msk) /*!< Set SS \hideinitializer */
#define QSPI_SS_ACTIVE_HIGH (QSPI_SSCTL_SSACTPOL_Msk) /*!< SS active high \hideinitializer */
#define QSPI_SS_ACTIVE_LOW (0x0U) /*!< SS active low \hideinitializer */
/* QSPI Interrupt Mask */
#define QSPI_UNIT_INT_MASK (0x001U) /*!< Unit transfer interrupt mask \hideinitializer */
#define QSPI_SSACT_INT_MASK (0x002U) /*!< Slave selection signal active interrupt mask \hideinitializer */
#define QSPI_SSINACT_INT_MASK (0x004U) /*!< Slave selection signal inactive interrupt mask \hideinitializer */
#define QSPI_SLVUR_INT_MASK (0x008U) /*!< Slave under run interrupt mask \hideinitializer */
#define QSPI_SLVBE_INT_MASK (0x010U) /*!< Slave bit count error interrupt mask \hideinitializer */
#define QSPI_TXUF_INT_MASK (0x040U) /*!< Slave TX underflow interrupt mask \hideinitializer */
#define QSPI_FIFO_TXTH_INT_MASK (0x080U) /*!< FIFO TX threshold interrupt mask \hideinitializer */
#define QSPI_FIFO_RXTH_INT_MASK (0x100U) /*!< FIFO RX threshold interrupt mask \hideinitializer */
#define QSPI_FIFO_RXOV_INT_MASK (0x200U) /*!< FIFO RX overrun interrupt mask \hideinitializer */
#define QSPI_FIFO_RXTO_INT_MASK (0x400U) /*!< FIFO RX time-out interrupt mask \hideinitializer */
/* QSPI Status Mask */
#define QSPI_BUSY_MASK (0x01U) /*!< Busy status mask \hideinitializer */
#define QSPI_RX_EMPTY_MASK (0x02U) /*!< RX empty status mask \hideinitializer */
#define QSPI_RX_FULL_MASK (0x04U) /*!< RX full status mask \hideinitializer */
#define QSPI_TX_EMPTY_MASK (0x08U) /*!< TX empty status mask \hideinitializer */
#define QSPI_TX_FULL_MASK (0x10U) /*!< TX full status mask \hideinitializer */
#define QSPI_TXRX_RESET_MASK (0x20U) /*!< TX or RX reset status mask \hideinitializer */
#define QSPI_QSPIEN_STS_MASK (0x40U) /*!< QSPIEN status mask \hideinitializer */
#define QSPI_SSLINE_STS_MASK (0x80U) /*!< QSPIx_SS line status mask \hideinitializer */
/*@}*/ /* end of group QSPI_EXPORTED_CONSTANTS */
/** @addtogroup QSPI_EXPORTED_FUNCTIONS QSPI Exported Functions
@{
*/
/**
* @brief Clear the unit transfer interrupt flag.
* @param[in] qspi The pointer of the specified QSPI module.
* @return None.
* @details Write 1 to UNITIF bit of QSPI_STATUS register to clear the unit transfer interrupt flag.
* \hideinitializer
*/
#define QSPI_CLR_UNIT_TRANS_INT_FLAG(qspi) ((qspi)->STATUS = QSPI_STATUS_UNITIF_Msk)
/**
* @brief Trigger RX PDMA function.
* @param[in] qspi The pointer of the specified QSPI module.
* @return None.
* @details Set RXPDMAEN bit of QSPI_PDMACTL register to enable RX PDMA transfer function.
* \hideinitializer
*/
#define QSPI_TRIGGER_RX_PDMA(qspi) ((qspi)->PDMACTL |= QSPI_PDMACTL_RXPDMAEN_Msk)
/**
* @brief Trigger TX PDMA function.
* @param[in] qspi The pointer of the specified QSPI module.
* @return None.
* @details Set TXPDMAEN bit of QSPI_PDMACTL register to enable TX PDMA transfer function.
* \hideinitializer
*/
#define QSPI_TRIGGER_TX_PDMA(qspi) ((qspi)->PDMACTL |= QSPI_PDMACTL_TXPDMAEN_Msk)
/**
* @brief Trigger TX and RX PDMA function.
* @param[in] qspi The pointer of the specified QSPI module.
* @return None.
* @details Set TXPDMAEN bit and RXPDMAEN bit of QSPI_PDMACTL register to enable TX and RX PDMA transfer function.
* \hideinitializer
*/
#define QSPI_TRIGGER_TX_RX_PDMA(qspi) ((qspi)->PDMACTL |= (QSPI_PDMACTL_TXPDMAEN_Msk | QSPI_PDMACTL_RXPDMAEN_Msk))
/**
* @brief Disable RX PDMA transfer.
* @param[in] qspi The pointer of the specified QSPI module.
* @return None.
* @details Clear RXPDMAEN bit of QSPI_PDMACTL register to disable RX PDMA transfer function.
* \hideinitializer
*/
#define QSPI_DISABLE_RX_PDMA(qspi) ( (qspi)->PDMACTL &= ~QSPI_PDMACTL_RXPDMAEN_Msk )
/**
* @brief Disable TX PDMA transfer.
* @param[in] qspi The pointer of the specified QSPI module.
* @return None.
* @details Clear TXPDMAEN bit of QSPI_PDMACTL register to disable TX PDMA transfer function.
* \hideinitializer
*/
#define QSPI_DISABLE_TX_PDMA(qspi) ( (qspi)->PDMACTL &= ~QSPI_PDMACTL_TXPDMAEN_Msk )
/**
* @brief Disable TX and RX PDMA transfer.
* @param[in] qspi The pointer of the specified QSPI module.
* @return None.
* @details Clear TXPDMAEN bit and RXPDMAEN bit of QSPI_PDMACTL register to disable TX and RX PDMA transfer function.
* \hideinitializer
*/
#define QSPI_DISABLE_TX_RX_PDMA(qspi) ( (qspi)->PDMACTL &= ~(QSPI_PDMACTL_TXPDMAEN_Msk | QSPI_PDMACTL_RXPDMAEN_Msk) )
/**
* @brief Get the count of available data in RX FIFO.
* @param[in] qspi The pointer of the specified QSPI module.
* @return The count of available data in RX FIFO.
* @details Read RXCNT (QSPI_STATUS[27:24]) to get the count of available data in RX FIFO.
* \hideinitializer
*/
#define QSPI_GET_RX_FIFO_COUNT(qspi) (((qspi)->STATUS & QSPI_STATUS_RXCNT_Msk) >> QSPI_STATUS_RXCNT_Pos)
/**
* @brief Get the RX FIFO empty flag.
* @param[in] qspi The pointer of the specified QSPI module.
* @retval 0 RX FIFO is not empty.
* @retval 1 RX FIFO is empty.
* @details Read RXEMPTY bit of QSPI_STATUS register to get the RX FIFO empty flag.
* \hideinitializer
*/
#define QSPI_GET_RX_FIFO_EMPTY_FLAG(qspi) (((qspi)->STATUS & QSPI_STATUS_RXEMPTY_Msk)>>QSPI_STATUS_RXEMPTY_Pos)
/**
* @brief Get the TX FIFO empty flag.
* @param[in] qspi The pointer of the specified QSPI module.
* @retval 0 TX FIFO is not empty.
* @retval 1 TX FIFO is empty.
* @details Read TXEMPTY bit of QSPI_STATUS register to get the TX FIFO empty flag.
* \hideinitializer
*/
#define QSPI_GET_TX_FIFO_EMPTY_FLAG(qspi) (((qspi)->STATUS & QSPI_STATUS_TXEMPTY_Msk)>>QSPI_STATUS_TXEMPTY_Pos)
/**
* @brief Get the TX FIFO full flag.
* @param[in] qspi The pointer of the specified QSPI module.
* @retval 0 TX FIFO is not full.
* @retval 1 TX FIFO is full.
* @details Read TXFULL bit of QSPI_STATUS register to get the TX FIFO full flag.
* \hideinitializer
*/
#define QSPI_GET_TX_FIFO_FULL_FLAG(qspi) (((qspi)->STATUS & QSPI_STATUS_TXFULL_Msk)>>QSPI_STATUS_TXFULL_Pos)
/**
* @brief Get the datum read from RX register.
* @param[in] qspi The pointer of the specified QSPI module.
* @return Data in RX register.
* @details Read QSPI_RX register to get the received datum.
* \hideinitializer
*/
#define QSPI_READ_RX(qspi) ((qspi)->RX)
/**
* @brief Write datum to TX register.
* @param[in] qspi The pointer of the specified QSPI module.
* @param[in] u32TxData The datum which user attempt to transfer through QSPI bus.
* @return None.
* @details Write u32TxData to QSPI_TX register.
* \hideinitializer
*/
#define QSPI_WRITE_TX(qspi, u32TxData) ((qspi)->TX = (u32TxData))
/**
* @brief Set QSPIx_SS pin to high state.
* @param[in] qspi The pointer of the specified QSPI module.
* @return None.
* @details Disable automatic slave selection function and set QSPIx_SS pin to high state.
* \hideinitializer
*/
#define QSPI_SET_SS_HIGH(qspi) ((qspi)->SSCTL = ((qspi)->SSCTL & (~QSPI_SSCTL_AUTOSS_Msk)) | (QSPI_SSCTL_SSACTPOL_Msk | QSPI_SSCTL_SS_Msk))
/**
* @brief Set QSPIx_SS pin to low state.
* @param[in] qspi The pointer of the specified QSPI module.
* @return None.
* @details Disable automatic slave selection function and set QSPIx_SS pin to low state.
* \hideinitializer
*/
#define QSPI_SET_SS_LOW(qspi) ((qspi)->SSCTL = ((qspi)->SSCTL & (~(QSPI_SSCTL_AUTOSS_Msk | QSPI_SSCTL_SSACTPOL_Msk))) | QSPI_SSCTL_SS_Msk)
/**
* @brief Enable Byte Reorder function.
* @param[in] qspi The pointer of the specified QSPI module.
* @return None.
* @details Enable Byte Reorder function. The suspend interval depends on the setting of SUSPITV (QSPI_CTL[7:4]).
* \hideinitializer
*/
#define QSPI_ENABLE_BYTE_REORDER(qspi) ((qspi)->CTL |= QSPI_CTL_REORDER_Msk)
/**
* @brief Disable Byte Reorder function.
* @param[in] qspi The pointer of the specified QSPI module.
* @return None.
* @details Clear REORDER bit field of QSPI_CTL register to disable Byte Reorder function.
* \hideinitializer
*/
#define QSPI_DISABLE_BYTE_REORDER(qspi) ((qspi)->CTL &= ~QSPI_CTL_REORDER_Msk)
/**
* @brief Set the length of suspend interval.
* @param[in] qspi The pointer of the specified QSPI module.
* @param[in] u32SuspCycle Decides the length of suspend interval. It could be 0 ~ 15.
* @return None.
* @details Set the length of suspend interval according to u32SuspCycle.
* The length of suspend interval is ((u32SuspCycle + 0.5) * the length of one QSPI bus clock cycle).
* \hideinitializer
*/
#define QSPI_SET_SUSPEND_CYCLE(qspi, u32SuspCycle) ((qspi)->CTL = ((qspi)->CTL & ~QSPI_CTL_SUSPITV_Msk) | ((u32SuspCycle) << QSPI_CTL_SUSPITV_Pos))
/**
* @brief Set the QSPI transfer sequence with LSB first.
* @param[in] qspi The pointer of the specified QSPI module.
* @return None.
* @details Set LSB bit of QSPI_CTL register to set the QSPI transfer sequence with LSB first.
* \hideinitializer
*/
#define QSPI_SET_LSB_FIRST(qspi) ((qspi)->CTL |= QSPI_CTL_LSB_Msk)
/**
* @brief Set the QSPI transfer sequence with MSB first.
* @param[in] qspi The pointer of the specified SPI module.
* @return None.
* @details Clear LSB bit of QSPI_CTL register to set the QSPI transfer sequence with MSB first.
* \hideinitializer
*/
#define QSPI_SET_MSB_FIRST(qspi) ((qspi)->CTL &= ~QSPI_CTL_LSB_Msk)
/**
* @brief Set the data width of a QSPI transaction.
* @param[in] qspi The pointer of the specified QSPI module.
* @param[in] u32Width The bit width of one transaction.
* @return None.
* @details The data width can be 8 ~ 32 bits.
* \hideinitializer
*/
#define QSPI_SET_DATA_WIDTH(qspi, u32Width) ((qspi)->CTL = ((qspi)->CTL & ~QSPI_CTL_DWIDTH_Msk) | (((u32Width)&0x1F) << QSPI_CTL_DWIDTH_Pos))
/**
* @brief Get the QSPI busy state.
* @param[in] qspi The pointer of the specified QSPI module.
* @retval 0 QSPI controller is not busy.
* @retval 1 QSPI controller is busy.
* @details This macro will return the busy state of QSPI controller.
* \hideinitializer
*/
#define QSPI_IS_BUSY(qspi) ( ((qspi)->STATUS & QSPI_STATUS_BUSY_Msk)>>QSPI_STATUS_BUSY_Pos )
/**
* @brief Enable QSPI controller.
* @param[in] qspi The pointer of the specified QSPI module.
* @return None.
* @details Set QSPIEN (QSPI_CTL[0]) to enable QSPI controller.
* \hideinitializer
*/
#define QSPI_ENABLE(qspi) ((qspi)->CTL |= QSPI_CTL_QSPIEN_Msk)
/**
* @brief Disable QSPI controller.
* @param[in] qspi The pointer of the specified QSPI module.
* @return None.
* @details Clear QSPIEN (QSPI_CTL[0]) to disable QSPI controller.
* \hideinitializer
*/
#define QSPI_DISABLE(qspi) ((qspi)->CTL &= ~QSPI_CTL_QSPIEN_Msk)
/**
* @brief Disable QSPI Dual IO function.
* @param[in] qspi is the base address of QSPI module.
* @return none
* \hideinitializer
*/
#define QSPI_DISABLE_DUAL_MODE(qspi) ( (qspi)->CTL &= ~QSPI_CTL_DUALIOEN_Msk )
/**
* @brief Enable Dual IO function and set QSPI Dual IO direction to input.
* @param[in] qspi is the base address of QSPI module.
* @return none
* \hideinitializer
*/
#define QSPI_ENABLE_DUAL_INPUT_MODE(qspi) ( (qspi)->CTL = ((qspi)->CTL & ~QSPI_CTL_DATDIR_Msk) | QSPI_CTL_DUALIOEN_Msk )
/**
* @brief Enable Dual IO function and set QSPI Dual IO direction to output.
* @param[in] qspi is the base address of QSPI module.
* @return none
* \hideinitializer
*/
#define QSPI_ENABLE_DUAL_OUTPUT_MODE(qspi) ( (qspi)->CTL |= QSPI_CTL_DATDIR_Msk | QSPI_CTL_DUALIOEN_Msk )
/**
* @brief Disable QSPI Dual IO function.
* @param[in] qspi is the base address of QSPI module.
* @return none
* \hideinitializer
*/
#define QSPI_DISABLE_QUAD_MODE(qspi) ( (qspi)->CTL &= ~QSPI_CTL_QUADIOEN_Msk )
/**
* @brief Set QSPI Quad IO direction to input.
* @param[in] qspi is the base address of QSPI module.
* @return none
* \hideinitializer
*/
#define QSPI_ENABLE_QUAD_INPUT_MODE(qspi) ( (qspi)->CTL = ((qspi)->CTL & ~QSPI_CTL_DATDIR_Msk) | QSPI_CTL_QUADIOEN_Msk )
/**
* @brief Set QSPI Quad IO direction to output.
* @param[in] qspi is the base address of QSPI module.
* @return none
* \hideinitializer
*/
#define QSPI_ENABLE_QUAD_OUTPUT_MODE(qspi) ( (qspi)->CTL |= QSPI_CTL_DATDIR_Msk | QSPI_CTL_QUADIOEN_Msk )
/**
* @brief Set QSPI Master Receive Phase.
* @param[in] qspi is the base address of QSPI module.
* @param[in] rxdly is the clock cycle of delay for rx phase.
* @return none
* \hideinitializer
*/
#define QSPI_SET_MRXPHASE(qspi, rxdly) ( (qspi)->INTERNAL = ((qspi)->INTERNAL & ~QSPI_INTERNAL_MRXPHASE_Msk) | (rxdly<<QSPI_INTERNAL_MRXPHASE_Pos) )
/* Function prototype declaration */
uint32_t QSPI_Open(QSPI_T *qspi, uint32_t u32MasterSlave, uint32_t u32QSPIMode, uint32_t u32DataWidth, uint32_t u32BusClock);
void QSPI_Close(QSPI_T *qspi);
void QSPI_ClearRxFIFO(QSPI_T *qspi);
void QSPI_ClearTxFIFO(QSPI_T *qspi);
void QSPI_DisableAutoSS(QSPI_T *qspi);
void QSPI_EnableAutoSS(QSPI_T *qspi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel);
uint32_t QSPI_SetBusClock(QSPI_T *qspi, uint32_t u32BusClock);
void QSPI_SetFIFO(QSPI_T *qspi, uint32_t u32TxThreshold, uint32_t u32RxThreshold);
uint32_t QSPI_GetBusClock(QSPI_T *qspi);
void QSPI_EnableInt(QSPI_T *qspi, uint32_t u32Mask);
void QSPI_DisableInt(QSPI_T *qspi, uint32_t u32Mask);
uint32_t QSPI_GetIntFlag(QSPI_T *qspi, uint32_t u32Mask);
void QSPI_ClearIntFlag(QSPI_T *qspi, uint32_t u32Mask);
uint32_t QSPI_GetStatus(QSPI_T *qspi, uint32_t u32Mask);
/*@}*/ /* end of group QSPI_EXPORTED_FUNCTIONS */
/*@}*/ /* end of group QSPI_Driver */
/*@}*/ /* end of group Standard_Driver */
#ifdef __cplusplus
}
#endif
#endif

224
bsp/nuvoton/libraries/ma35/StdDriver/inc/nu_rtc.h Normal file
View File

@ -0,0 +1,224 @@
/**************************************************************************//**
* @file nu_rtc.h
* @brief RTC driver header file
*
* SPDX-License-Identifier: Apache-2.0
* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __NU_RTC_H__
#define __NU_RTC_H__
#ifdef __cplusplus
extern "C"
{
#endif
#include "NuMicro.h"
#if defined(USE_MA35D1_SUBM)
#define REG_RTC_TALM RTC->TALM_M
#define REG_RTC_CALM RTC->CALM_M
#define REG_RTC_INTEN RTC->INTEN_M
#define REG_RTC_INTSTS RTC->INTSTS_M
#define REG_RTC_TICK RTC->TICK_M
#define REG_RTC_TAMSK RTC->TAMSK_M
#define REG_RTC_CAMSK RTC->CAMSK_M
#else
#define REG_RTC_TALM RTC->TALM
#define REG_RTC_CALM RTC->CALM
#define REG_RTC_INTEN RTC->INTEN
#define REG_RTC_INTSTS RTC->INTSTS
#define REG_RTC_TICK RTC->TICK
#define REG_RTC_TAMSK RTC->TAMSK
#define REG_RTC_CAMSK RTC->CAMSK
#endif
/** @addtogroup Standard_Driver Standard Driver
@{
*/
/** @addtogroup RTC_Driver RTC Driver
@{
*/
/** @addtogroup RTC_EXPORTED_CONSTANTS RTC Exported Constants
@{
*/
/*---------------------------------------------------------------------------------------------------------*/
/* RTC Initial Keyword Constant Definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define RTC_INIT_KEY 0xA5EB1357UL /*!< RTC Initiation Key to make RTC leaving reset state \hideinitializer */
/*---------------------------------------------------------------------------------------------------------*/
/* RTC Time Attribute Constant Definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define RTC_CLOCK_12 0UL /*!< RTC as 12-hour time scale with AM and PM indication \hideinitializer */
#define RTC_CLOCK_24 1UL /*!< RTC as 24-hour time scale \hideinitializer */
#define RTC_AM 1UL /*!< RTC as AM indication \hideinitializer */
#define RTC_PM 2UL /*!< RTC as PM indication \hideinitializer */
/*---------------------------------------------------------------------------------------------------------*/
/* RTC Tick Period Constant Definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define RTC_TICK_1_SEC 0x0UL /*!< RTC time tick period is 1 second \hideinitializer */
#define RTC_TICK_1_2_SEC 0x1UL /*!< RTC time tick period is 1/2 second \hideinitializer */
#define RTC_TICK_1_4_SEC 0x2UL /*!< RTC time tick period is 1/4 second \hideinitializer */
#define RTC_TICK_1_8_SEC 0x3UL /*!< RTC time tick period is 1/8 second \hideinitializer */
#define RTC_TICK_1_16_SEC 0x4UL /*!< RTC time tick period is 1/16 second \hideinitializer */
#define RTC_TICK_1_32_SEC 0x5UL /*!< RTC time tick period is 1/32 second \hideinitializer */
#define RTC_TICK_1_64_SEC 0x6UL /*!< RTC time tick period is 1/64 second \hideinitializer */
#define RTC_TICK_1_128_SEC 0x7UL /*!< RTC time tick period is 1/128 second \hideinitializer */
/*---------------------------------------------------------------------------------------------------------*/
/* RTC Day of Week Constant Definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define RTC_SUNDAY 0x0UL /*!< Day of the Week is Sunday \hideinitializer */
#define RTC_MONDAY 0x1UL /*!< Day of the Week is Monday \hideinitializer */
#define RTC_TUESDAY 0x2UL /*!< Day of the Week is Tuesday \hideinitializer */
#define RTC_WEDNESDAY 0x3UL /*!< Day of the Week is Wednesday \hideinitializer */
#define RTC_THURSDAY 0x4UL /*!< Day of the Week is Thursday \hideinitializer */
#define RTC_FRIDAY 0x5UL /*!< Day of the Week is Friday \hideinitializer */
#define RTC_SATURDAY 0x6UL /*!< Day of the Week is Saturday \hideinitializer */
/*---------------------------------------------------------------------------------------------------------*/
/* RTC Miscellaneous Constant Definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define RTC_WAIT_COUNT 0xFFFFFFFFUL /*!< Initial Time-out Value \hideinitializer */
#define RTC_YEAR2000 2000UL /*!< RTC Reference for compute year data \hideinitializer */
/*@}*/ /* end of group RTC_EXPORTED_CONSTANTS */
/** @addtogroup RTC_EXPORTED_STRUCTS RTC Exported Structs
@{
*/
/**
* @details RTC define Time Data Struct
*/
typedef struct
{
uint32_t u32Year; /*!< Year value */
uint32_t u32Month; /*!< Month value */
uint32_t u32Day; /*!< Day value */
uint32_t u32DayOfWeek; /*!< Day of week value */
uint32_t u32Hour; /*!< Hour value */
uint32_t u32Minute; /*!< Minute value */
uint32_t u32Second; /*!< Second value */
uint32_t u32TimeScale; /*!< 12-Hour, 24-Hour */
uint32_t u32AmPm; /*!< Only Time Scale select 12-hr used */
} S_RTC_TIME_DATA_T;
/*@}*/ /* end of group RTC_EXPORTED_STRUCTS */
/** @addtogroup RTC_EXPORTED_FUNCTIONS RTC Exported Functions
@{
*/
/**
* @brief Indicate is Leap Year or not
*
* @param None
*
* @retval 0 This year is not a leap year
* @retval 1 This year is a leap year
*
* @details According to current date, return this year is leap year or not.
* \hideinitializer
*/
#define RTC_IS_LEAP_YEAR() (RTC->LEAPYEAR & RTC_LEAPYEAR_LEAPYEAR_Msk ? 1:0)
/**
* @brief Clear RTC Alarm Interrupt Flag
*
* @param None
*
* @return None
*
* @details This macro is used to clear RTC alarm interrupt flag.
* \hideinitializer
*/
#define RTC_CLEAR_ALARM_INT_FLAG() (REG_RTC_INTSTS = RTC_INTSTS_ALMIF_Msk)
/**
* @brief Clear RTC Tick Interrupt Flag
*
* @param None
*
* @return None
*
* @details This macro is used to clear RTC tick interrupt flag.
* \hideinitializer
*/
#define RTC_CLEAR_TICK_INT_FLAG() (REG_RTC_INTSTS = RTC_INTSTS_TICKIF_Msk)
/**
* @brief Get RTC Alarm Interrupt Flag
*
* @param None
*
* @retval 0 RTC alarm interrupt did not occur
* @retval 1 RTC alarm interrupt occurred
*
* @details This macro indicates RTC alarm interrupt occurred or not.
* \hideinitializer
*/
#define RTC_GET_ALARM_INT_FLAG() ((REG_RTC_INTSTS & RTC_INTSTS_ALMIF_Msk)? 1:0)
/**
* @brief Get RTC Time Tick Interrupt Flag
*
* @param None
*
* @retval 0 RTC time tick interrupt did not occur
* @retval 1 RTC time tick interrupt occurred
*
* @details This macro indicates RTC time tick interrupt occurred or not.
* \hideinitializer
*/
#define RTC_GET_TICK_INT_FLAG() ((REG_RTC_INTSTS & RTC_INTSTS_TICKIF_Msk)? 1:0)
/**
* @brief Read Spare Register
*
* @param[in] u32RegNum The spare register number, 0~19.
*
* @return Spare register content
*
* @details Read the specify spare register content.
* @note The returned value is valid only when SPRRDY(SPRCTL[7] SPR Register Ready) bit is set. \n
* And its controlled by RTC Access Enable Register.
* \hideinitializer
*/
#define RTC_READ_SPARE_REGISTER(u32RegNum) (RTC->SPR[(u32RegNum)])
int32_t RTC_Open(S_RTC_TIME_DATA_T *sPt);
void RTC_Close(void);
void RTC_GetDateAndTime(S_RTC_TIME_DATA_T *sPt);
void RTC_GetAlarmDateAndTime(S_RTC_TIME_DATA_T *sPt);
void RTC_SetDateAndTime(S_RTC_TIME_DATA_T *sPt);
void RTC_SetAlarmDateAndTime(S_RTC_TIME_DATA_T *sPt);
void RTC_SetDate(uint32_t u32Year, uint32_t u32Month, uint32_t u32Day, uint32_t u32DayOfWeek);
void RTC_SetTime(uint32_t u32Hour, uint32_t u32Minute, uint32_t u32Second, uint32_t u32TimeMode, uint32_t u32AmPm);
void RTC_SetAlarmDate(uint32_t u32Year, uint32_t u32Month, uint32_t u32Day);
void RTC_SetAlarmTime(uint32_t u32Hour, uint32_t u32Minute, uint32_t u32Second, uint32_t u32TimeMode, uint32_t u32AmPm);
void RTC_SetAlarmDateMask(uint8_t u8IsTenYMsk, uint8_t u8IsYMsk, uint8_t u8IsTenMMsk, uint8_t u8IsMMsk, uint8_t u8IsTenDMsk, uint8_t u8IsDMsk);
void RTC_SetAlarmTimeMask(uint8_t u8IsTenHMsk, uint8_t u8IsHMsk, uint8_t u8IsTenMMsk, uint8_t u8IsMMsk, uint8_t u8IsTenSMsk, uint8_t u8IsSMsk);
uint32_t RTC_GetDayOfWeek(void);
void RTC_SetTickPeriod(uint32_t u32TickSelection);
void RTC_EnableInt(uint32_t u32IntFlagMask);
void RTC_DisableInt(uint32_t u32IntFlagMask);
/*@}*/ /* end of group RTC_EXPORTED_FUNCTIONS */
/*@}*/ /* end of group RTC_Driver */
/*@}*/ /* end of group Standard_Driver */
#ifdef __cplusplus
}
#endif
#endif /* __NU_RTC_H__ */

266
bsp/nuvoton/libraries/ma35/StdDriver/inc/nu_sc.h Normal file
View File

@ -0,0 +1,266 @@
/**************************************************************************//**
* @file nu_sc.h
* @brief Smartcard (SC) driver header file
*
* SPDX-License-Identifier: Apache-2.0
* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __NU_SC_H__
#define __NU_SC_H__
#ifdef __cplusplus
extern "C"
{
#endif
/** @addtogroup Standard_Driver Standard Driver
@{
*/
/** @addtogroup SC_Driver SC Driver
@{
*/
/** @addtogroup SC_EXPORTED_CONSTANTS SC Exported Constants
@{
*/
#define SC_INTERFACE_NUM 2 /*!< Smartcard interface numbers \hideinitializer */
#define SC_PIN_STATE_HIGH 1 /*!< Smartcard pin status high \hideinitializer */
#define SC_PIN_STATE_LOW 0 /*!< Smartcard pin status low \hideinitializer */
#define SC_PIN_STATE_IGNORE 0xFFFFFFFF /*!< Ignore pin status \hideinitializer */
#define SC_CLK_ON 1 /*!< Smartcard clock on \hideinitializer */
#define SC_CLK_OFF 0 /*!< Smartcard clock off \hideinitializer */
#define SC_TMR_MODE_0 (0ul << SC_TMRCTL0_OPMODE_Pos) /*!<Timer Operation Mode 0, down count \hideinitializer */
#define SC_TMR_MODE_1 (1ul << SC_TMRCTL0_OPMODE_Pos) /*!<Timer Operation Mode 1, down count, start after detect start bit \hideinitializer */
#define SC_TMR_MODE_2 (2ul << SC_TMRCTL0_OPMODE_Pos) /*!<Timer Operation Mode 2, down count, start after receive start bit \hideinitializer */
#define SC_TMR_MODE_3 (3ul << SC_TMRCTL0_OPMODE_Pos) /*!<Timer Operation Mode 3, down count, use for activation, only timer 0 support this mode \hideinitializer */
#define SC_TMR_MODE_4 (4ul << SC_TMRCTL0_OPMODE_Pos) /*!<Timer Operation Mode 4, down count with reload after timeout \hideinitializer */
#define SC_TMR_MODE_5 (5ul << SC_TMRCTL0_OPMODE_Pos) /*!<Timer Operation Mode 5, down count, start after detect start bit, reload after timeout \hideinitializer */
#define SC_TMR_MODE_6 (6ul << SC_TMRCTL0_OPMODE_Pos) /*!<Timer Operation Mode 6, down count, start after receive start bit, reload after timeout \hideinitializer */
#define SC_TMR_MODE_7 (7ul << SC_TMRCTL0_OPMODE_Pos) /*!<Timer Operation Mode 7, down count, start and reload after detect start bit \hideinitializer */
#define SC_TMR_MODE_8 (8ul << SC_TMRCTL0_OPMODE_Pos) /*!<Timer Operation Mode 8, up count \hideinitializer */
#define SC_TMR_MODE_F (0xF << SC_TMRCTL0_OPMODE_Pos) /*!<Timer Operation Mode 15, down count, reload after detect start bit \hideinitializer */
/*@}*/ /* end of group SC_EXPORTED_CONSTANTS */
/** @addtogroup SC_EXPORTED_FUNCTIONS SC Exported Functions
@{
*/
/**
* @brief This macro enable smartcard interrupt
* @param[in] sc Base address of smartcard module
* @param[in] u32Mask Interrupt mask to be enabled. A combination of
* - \ref SC_INTEN_ACERRIEN_Msk
* - \ref SC_INTEN_RXTOIEN_Msk
* - \ref SC_INTEN_INITIEN_Msk
* - \ref SC_INTEN_CDIEN_Msk
* - \ref SC_INTEN_BGTIEN_Msk
* - \ref SC_INTEN_TMR2IEN_Msk
* - \ref SC_INTEN_TMR1IEN_Msk
* - \ref SC_INTEN_TMR0IEN_Msk
* - \ref SC_INTEN_TERRIEN_Msk
* - \ref SC_INTEN_TBEIEN_Msk
* - \ref SC_INTEN_RDAIEN_Msk
* @return None
* \hideinitializer
*/
#define SC_ENABLE_INT(sc, u32Mask) ((sc)->INTEN |= (u32Mask))
/**
* @brief This macro disable smartcard interrupt
* @param[in] sc Base address of smartcard module
* @param[in] u32Mask Interrupt mask to be disabled. A combination of
* - \ref SC_INTEN_ACERRIEN_Msk
* - \ref SC_INTEN_RXTOIEN_Msk
* - \ref SC_INTEN_INITIEN_Msk
* - \ref SC_INTEN_CDIEN_Msk
* - \ref SC_INTEN_BGTIEN_Msk
* - \ref SC_INTEN_TMR2IEN_Msk
* - \ref SC_INTEN_TMR1IEN_Msk
* - \ref SC_INTEN_TMR0IEN_Msk
* - \ref SC_INTEN_TERRIEN_Msk
* - \ref SC_INTEN_TBEIEN_Msk
* - \ref SC_INTEN_RDAIEN_Msk
* @return None
* \hideinitializer
*/
#define SC_DISABLE_INT(sc, u32Mask) ((sc)->INTEN &= ~(u32Mask))
/**
* @brief This macro set VCC pin state of smartcard interface
* @param[in] sc Base address of smartcard module
* @param[in] u32State Pin state of VCC pin, valid parameters are \ref SC_PIN_STATE_HIGH and \ref SC_PIN_STATE_LOW
* @return None
* \hideinitializer
*/
#define SC_SET_VCC_PIN(sc, u32State) \
do {\
while((sc)->PINCTL & SC_PINCTL_SYNC_Msk);\
if(u32State)\
(sc)->PINCTL |= SC_PINCTL_PWREN_Msk;\
else\
(sc)->PINCTL &= ~SC_PINCTL_PWREN_Msk;\
}while(0)
/**
* @brief This macro turns CLK output on or off
* @param[in] sc Base address of smartcard module
* @param[in] u32OnOff Clock on or off for selected smartcard module, valid values are \ref SC_CLK_ON and \ref SC_CLK_OFF
* @return None
* \hideinitializer
*/
#define SC_SET_CLK_PIN(sc, u32OnOff)\
do {\
while((sc)->PINCTL & SC_PINCTL_SYNC_Msk);\
if(u32OnOff)\
(sc)->PINCTL |= SC_PINCTL_CLKKEEP_Msk;\
else\
(sc)->PINCTL &= ~(SC_PINCTL_CLKKEEP_Msk);\
}while(0)
/**
* @brief This macro set I/O pin state of smartcard interface
* @param[in] sc Base address of smartcard module
* @param[in] u32State Pin state of I/O pin, valid parameters are \ref SC_PIN_STATE_HIGH and \ref SC_PIN_STATE_LOW
* @return None
* \hideinitializer
*/
#define SC_SET_IO_PIN(sc, u32State)\
do {\
while((sc)->PINCTL & SC_PINCTL_SYNC_Msk);\
if(u32State)\
(sc)->PINCTL |= SC_PINCTL_SCDATA_Msk;\
else\
(sc)->PINCTL &= ~SC_PINCTL_SCDATA_Msk;\
}while(0)
/**
* @brief This macro set RST pin state of smartcard interface
* @param[in] sc Base address of smartcard module
* @param[in] u32State Pin state of RST pin, valid parameters are \ref SC_PIN_STATE_HIGH and \ref SC_PIN_STATE_LOW
* @return None
* \hideinitializer
*/
#define SC_SET_RST_PIN(sc, u32State)\
do {\
while((sc)->PINCTL & SC_PINCTL_SYNC_Msk);\
if(u32State)\
(sc)->PINCTL |= SC_PINCTL_RSTEN_Msk;\
else\
(sc)->PINCTL &= ~SC_PINCTL_RSTEN_Msk;\
}while(0)
/**
* @brief This macro read one byte from smartcard module receive FIFO
* @param[in] sc Base address of smartcard module
* @return One byte read from receive FIFO
* \hideinitializer
*/
#define SC_READ(sc) ((char)((sc)->DAT))
/**
* @brief This macro write one byte to smartcard module transmit FIFO
* @param[in] sc Base address of smartcard module
* @param[in] u8Data Data to write to transmit FIFO
* @return None
* \hideinitializer
*/
#define SC_WRITE(sc, u8Data) ((sc)->DAT = (u8Data))
/**
* @brief This macro set smartcard stop bit length
* @param[in] sc Base address of smartcard module
* @param[in] u32Len Stop bit length, ether 1 or 2.
* @return None
* @details Stop bit length must be 1 for T = 1 protocol and 2 for T = 0 protocol.
* \hideinitializer
*/
#define SC_SET_STOP_BIT_LEN(sc, u32Len) ((sc)->CTL = ((sc)->CTL & ~SC_CTL_NSB_Msk) | ((u32Len) == 1 ? SC_CTL_NSB_Msk : 0))
/* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */
__STATIC_INLINE void SC_SetTxRetry(SC_T *sc, uint32_t u32Count);
__STATIC_INLINE void SC_SetRxRetry(SC_T *sc, uint32_t u32Count);
/**
* @brief Enable/Disable Tx error retry, and set Tx error retry count
* @param[in] sc Base address of smartcard module
* @param[in] u32Count The number of times of Tx error retry count, between 0~8. 0 means disable Tx error retry
* @return None
*/
__STATIC_INLINE void SC_SetTxRetry(SC_T *sc, uint32_t u32Count)
{
while ((sc)->CTL & SC_CTL_SYNC_Msk)
{
;
}
/* Retry count must set while enable bit disabled, so disable it first */
(sc)->CTL &= ~(SC_CTL_TXRTY_Msk | SC_CTL_TXRTYEN_Msk);
if ((u32Count) != 0UL)
{
while ((sc)->CTL & SC_CTL_SYNC_Msk)
{
;
}
(sc)->CTL |= (((u32Count) - 1UL) << SC_CTL_TXRTY_Pos) | SC_CTL_TXRTYEN_Msk;
}
}
/**
* @brief Enable/Disable Rx error retry, and set Rx error retry count
* @param[in] sc Base address of smartcard module
* @param[in] u32Count The number of times of Rx error retry count, between 0~8. 0 means disable Rx error retry
* @return None
*/
__STATIC_INLINE void SC_SetRxRetry(SC_T *sc, uint32_t u32Count)
{
while ((sc)->CTL & SC_CTL_SYNC_Msk)
{
;
}
/* Retry count must set while enable bit disabled, so disable it first */
(sc)->CTL &= ~(SC_CTL_RXRTY_Msk | SC_CTL_RXRTYEN_Msk);
if ((u32Count) != 0UL)
{
while ((sc)->CTL & SC_CTL_SYNC_Msk)
{
;
}
(sc)->CTL |= (((u32Count) - 1UL) << SC_CTL_RXRTY_Pos) | SC_CTL_RXRTYEN_Msk;
}
}
uint32_t SC_IsCardInserted(SC_T *sc);
void SC_ClearFIFO(SC_T *sc);
void SC_Close(SC_T *sc);
void SC_Open(SC_T *sc, uint32_t u32CardDet, uint32_t u32PWR);
void SC_ResetReader(SC_T *sc);
void SC_SetBlockGuardTime(SC_T *sc, uint32_t u32BGT);
void SC_SetCharGuardTime(SC_T *sc, uint32_t u32CGT);
void SC_StopAllTimer(SC_T *sc);
void SC_StartTimer(SC_T *sc, uint32_t u32TimerNum, uint32_t u32Mode, uint32_t u32ETUCount);
void SC_StopTimer(SC_T *sc, uint32_t u32TimerNum);
uint32_t SC_GetInterfaceClock(SC_T *sc);
/*@}*/ /* end of group SC_EXPORTED_FUNCTIONS */
/*@}*/ /* end of group SC_Driver */
/*@}*/ /* end of group Standard_Driver */
#ifdef __cplusplus
}
#endif
#endif /* __NU_SC_H__ */

265
bsp/nuvoton/libraries/ma35/StdDriver/inc/nu_scuart.h Normal file
View File

@ -0,0 +1,265 @@
/**************************************************************************//**
* @file nu_scuart.h
* @brief Smartcard UART mode (SCUART) driver header file
*
* SPDX-License-Identifier: Apache-2.0
* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __NU_SCUART_H__
#define __NU_SCUART_H__
#ifdef __cplusplus
extern "C"
{
#endif
/** @addtogroup Standard_Driver Standard Driver
@{
*/
/** @addtogroup SCUART_Driver SCUART Driver
@{
*/
/** @addtogroup SCUART_EXPORTED_CONSTANTS SCUART Exported Constants
@{
*/
#define SCUART_CHAR_LEN_5 (0x3ul << SC_UARTCTL_WLS_Pos) /*!< Set SCUART word length to 5 bits \hideinitializer */
#define SCUART_CHAR_LEN_6 (0x2ul << SC_UARTCTL_WLS_Pos) /*!< Set SCUART word length to 6 bits \hideinitializer */
#define SCUART_CHAR_LEN_7 (0x1ul << SC_UARTCTL_WLS_Pos) /*!< Set SCUART word length to 7 bits \hideinitializer */
#define SCUART_CHAR_LEN_8 (0UL) /*!< Set SCUART word length to 8 bits \hideinitializer */
#define SCUART_PARITY_NONE (SC_UARTCTL_PBOFF_Msk) /*!< Set SCUART transfer with no parity \hideinitializer */
#define SCUART_PARITY_ODD (SC_UARTCTL_OPE_Msk) /*!< Set SCUART transfer with odd parity \hideinitializer */
#define SCUART_PARITY_EVEN (0UL) /*!< Set SCUART transfer with even parity \hideinitializer */
#define SCUART_STOP_BIT_1 (SC_CTL_NSB_Msk) /*!< Set SCUART transfer with one stop bit \hideinitializer */
#define SCUART_STOP_BIT_2 (0UL) /*!< Set SCUART transfer with two stop bits \hideinitializer */
/*@}*/ /* end of group SCUART_EXPORTED_CONSTANTS */
/** @addtogroup SCUART_EXPORTED_FUNCTIONS SCUART Exported Functions
@{
*/
/* TX Macros */
/**
* @brief Write Data to Tx data register
* @param[in] sc The base address of smartcard module.
* @param[in] u8Data Data byte to transmit
* @return None
* \hideinitializer
*/
#define SCUART_WRITE(sc, u8Data) ((sc)->DAT = (u8Data))
/**
* @brief Get TX FIFO empty flag status from register
* @param[in] sc The base address of smartcard module
* @return Transmit FIFO empty status
* @retval 0 Transmit FIFO is not empty
* @retval SC_STATUS_TXEMPTY_Msk Transmit FIFO is empty
* \hideinitializer
*/
#define SCUART_GET_TX_EMPTY(sc) ((sc)->STATUS & SC_STATUS_TXEMPTY_Msk)
/**
* @brief Get TX FIFO full flag status from register
* @param[in] sc The base address of smartcard module
* @return Transmit FIFO full status
* @retval 0 Transmit FIFO is not full
* @retval SC_STATUS_TXFULL_Msk Transmit FIFO is full
* \hideinitializer
*/
#define SCUART_GET_TX_FULL(sc) ((sc)->STATUS & SC_STATUS_TXFULL_Msk)
/**
* @brief Wait specified smartcard port transmission complete
* @param[in] sc The base address of smartcard module
* @return None
* @note This Macro blocks until transmit complete.
* \hideinitializer
*/
#define SCUART_WAIT_TX_EMPTY(sc) while((sc)->STATUS & SC_STATUS_TXACT_Msk)
/**
* @brief Check specified smartcard port transmit FIFO is full or not
* @param[in] sc The base address of smartcard module
* @return Transmit FIFO full status
* @retval 0 Transmit FIFO is not full
* @retval 1 Transmit FIFO is full
* \hideinitializer
*/
#define SCUART_IS_TX_FULL(sc) ((sc)->STATUS & SC_STATUS_TXFULL_Msk ? 1 : 0)
/**
* @brief Check specified smartcard port transmission is over
* @param[in] sc The base address of smartcard module
* @return Transmit complete status
* @retval 0 Transmit is not complete
* @retval 1 Transmit complete
* \hideinitializer
*/
#define SCUART_IS_TX_EMPTY(sc) ((sc)->STATUS & SC_STATUS_TXACT_Msk ? 0 : 1)
/**
* @brief Check specified Smartcard port Transmission Status
* @param[in] sc The pointer of smartcard module.
* @retval 0 Transmit is completed
* @retval 1 Transmit is active
* @details TXACT (SC_STATUS[31]) is set by hardware when Tx transfer is in active and the STOP bit of the last byte has been transmitted.
* \hideinitializer
*/
#define SCUART_IS_TX_ACTIVE(sc) (((sc)->STATUS & SC_STATUS_TXACT_Msk)? 1 : 0)
/* RX Macros */
/**
* @brief Read Rx data register
* @param[in] sc The base address of smartcard module
* @return The oldest data byte in RX FIFO
* \hideinitializer
*/
#define SCUART_READ(sc) ((sc)->DAT)
/**
* @brief Get RX FIFO empty flag status from register
* @param[in] sc The base address of smartcard module
* @return Receive FIFO empty status
* @retval 0 Receive FIFO is not empty
* @retval SC_STATUS_RXEMPTY_Msk Receive FIFO is empty
* \hideinitializer
*/
#define SCUART_GET_RX_EMPTY(sc) ((sc)->STATUS & SC_STATUS_RXEMPTY_Msk)
/**
* @brief Get RX FIFO full flag status from register
* @param[in] sc The base address of smartcard module
* @return Receive FIFO full status
* @retval 0 Receive FIFO is not full
* @retval SC_STATUS_RXFULLF_Msk Receive FIFO is full
* \hideinitializer
*/
#define SCUART_GET_RX_FULL(sc) ((sc)->STATUS & SC_STATUS_RXFULL_Msk)
/**
* @brief Check if receive data number in FIFO reach FIFO trigger level or not
* @param[in] sc The base address of smartcard module
* @return Receive FIFO data status
* @retval 0 The number of bytes in receive FIFO is less than trigger level
* @retval 1 The number of bytes in receive FIFO equals or larger than trigger level
* @note If receive trigger level is \b not 1 byte, this macro return 0 does not necessary indicates there is \b no data in FIFO
* \hideinitializer
*/
#define SCUART_IS_RX_READY(sc) ((sc)->INTSTS & SC_INTSTS_RDAIF_Msk ? 1 : 0)
/**
* @brief Check specified smartcard port receive FIFO is full or not
* @param[in] sc The base address of smartcard module
* @return Receive FIFO full status
* @retval 0 Receive FIFO is not full
* @retval 1 Receive FIFO is full
* \hideinitializer
*/
#define SCUART_IS_RX_FULL(sc) ((sc)->STATUS & SC_STATUS_RXFULL_Msk ? 1 : 0)
/* Interrupt Macros */
/**
* @brief Enable specified interrupts
* @param[in] sc The base address of smartcard module
* @param[in] u32Mask Interrupt masks to enable, a combination of following bits
* - \ref SC_INTEN_RXTOIEN_Msk
* - \ref SC_INTEN_TERRIEN_Msk
* - \ref SC_INTEN_TBEIEN_Msk
* - \ref SC_INTEN_RDAIEN_Msk
* @return None
* \hideinitializer
*/
#define SCUART_ENABLE_INT(sc, u32Mask) ((sc)->INTEN |= (u32Mask))
/**
* @brief Disable specified interrupts
* @param[in] sc The base address of smartcard module
* @param[in] u32Mask Interrupt masks to disable, a combination of following bits
* - \ref SC_INTEN_RXTOIEN_Msk
* - \ref SC_INTEN_TERRIEN_Msk
* - \ref SC_INTEN_TBEIEN_Msk
* - \ref SC_INTEN_RDAIEN_Msk
* @return None
* \hideinitializer
*/
#define SCUART_DISABLE_INT(sc, u32Mask) ((sc)->INTEN &= ~(u32Mask))
/**
* @brief Get specified interrupt flag/status
* @param[in] sc The base address of smartcard module
* @param[in] u32Type Interrupt flag/status to check, could be one of following value
* - \ref SC_INTSTS_RXTOIF_Msk
* - \ref SC_INTSTS_TERRIF_Msk
* - \ref SC_INTSTS_TBEIF_Msk
* - \ref SC_INTSTS_RDAIF_Msk
* @return The status of specified interrupt
* @retval 0 Specified interrupt does not happened
* @retval 1 Specified interrupt happened
* \hideinitializer
*/
#define SCUART_GET_INT_FLAG(sc, u32Type) ((sc)->INTSTS & (u32Type) ? 1 : 0)
/**
* @brief Clear specified interrupt flag/status
* @param[in] sc The base address of smartcard module
* @param[in] u32Type Interrupt flag/status to clear, could be the combination of following values
* - \ref SC_INTSTS_RXTOIF_Msk
* - \ref SC_INTSTS_TERRIF_Msk
* - \ref SC_INTSTS_TBEIF_Msk
* @return None
* \hideinitializer
*/
#define SCUART_CLR_INT_FLAG(sc, u32Type) ((sc)->INTSTS = (u32Type))
/**
* @brief Get receive error flag/status
* @param[in] sc The base address of smartcard module
* @return Current receive error status, could one of following errors:
* @retval SC_STATUS_PEF_Msk Parity error
* @retval SC_STATUS_FEF_Msk Frame error
* @retval SC_STATUS_BEF_Msk Break error
* \hideinitializer
*/
#define SCUART_GET_ERR_FLAG(sc) ((sc)->STATUS & (SC_STATUS_PEF_Msk | SC_STATUS_FEF_Msk | SC_STATUS_BEF_Msk))
/**
* @brief Clear specified receive error flag/status
* @param[in] sc The base address of smartcard module
* @param[in] u32Mask Receive error flag/status to clear, combination following values
* - \ref SC_STATUS_PEF_Msk
* - \ref SC_STATUS_FEF_Msk
* - \ref SC_STATUS_BEF_Msk
* @return None
* \hideinitializer
*/
#define SCUART_CLR_ERR_FLAG(sc, u32Mask) ((sc)->STATUS = (u32Mask))
void SCUART_Close(SC_T *sc);
uint32_t SCUART_Open(SC_T *sc, uint32_t u32baudrate);
uint32_t SCUART_Read(SC_T *sc, uint8_t pu8RxBuf[], uint32_t u32ReadBytes);
uint32_t SCUART_SetLineConfig(SC_T *sc, uint32_t u32Baudrate, uint32_t u32DataWidth, uint32_t u32Parity, uint32_t u32StopBits);
void SCUART_SetTimeoutCnt(SC_T *sc, uint32_t u32TOC);
void SCUART_Write(SC_T *sc, uint8_t pu8TxBuf[], uint32_t u32WriteBytes);
/*@}*/ /* end of group SCUART_EXPORTED_FUNCTIONS */
/*@}*/ /* end of group SCUART_Driver */
/*@}*/ /* end of group Standard_Driver */
#ifdef __cplusplus
}
#endif
#endif /* __NU_SCUART_H__ */

121
bsp/nuvoton/libraries/ma35/StdDriver/inc/nu_sdh.h Normal file
View File

@ -0,0 +1,121 @@
/****************************************************************************//**
* @file nu_sdh.h
* @brief SDH driver header file
*
* SPDX-License-Identifier: Apache-2.0
* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __NU_SDH_H__
#define __NU_SDH_H__
#ifdef __cplusplus
extern "C"
{
#endif
/** @addtogroup Standard_Driver Standard Driver
@{
*/
/** @addtogroup SDH_Driver SDH Driver
@{
*/
/** @addtogroup SDH_EXPORTED_CONSTANTS SDH Exported Constants
@{
*/
#define SDH_POWER_ON 0x01
#define SDH_POWER_180 0x0A
#define SDH_POWER_300 0x0C
#define SDH_POWER_330 0x0E
#define SDH_RESET_ALL 0x01
#define SDH_RESET_CMD 0x02
#define SDH_RESET_DATA 0x04
#define SDH_CMD_RESP_MASK 0x03
#define SDH_CMD_CRC 0x08
#define SDH_CMD_INDEX 0x10
#define SDH_CMD_DATA 0x20
#define SDH_CMD_ABORTCMD 0xC0
#define SDH_CMD_RESP_NONE 0x00
#define SDH_CMD_RESP_LONG 0x01
#define SDH_CMD_RESP_SHORT 0x02
#define SDH_CMD_RESP_SHORT_BUSY 0x03
/* MMC command */
#define MMC_CMD_STOP_TRANSMISSION 12
/* MMC response */
#define MMC_RSP_PRESENT (1 << 0)
#define MMC_RSP_136 (1 << 1) /* 136 bit response */
#define MMC_RSP_CRC (1 << 2) /* expect valid crc */
#define MMC_RSP_BUSY (1 << 3) /* card may send busy */
#define MMC_RSP_OPCODE (1 << 4) /* response contains opcode */
#define MMC_RSP_NONE (0)
#define MMC_RSP_R1 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
#define MMC_RSP_R1b (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE|MMC_RSP_BUSY)
#define MMC_RSP_R2 (MMC_RSP_PRESENT|MMC_RSP_136|MMC_RSP_CRC)
#define MMC_RSP_R3 (MMC_RSP_PRESENT)
#define MMC_RSP_R4 (MMC_RSP_PRESENT)
#define MMC_RSP_R5 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
#define MMC_RSP_R6 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
#define MMC_RSP_R7 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
#define MMC_DATA_READ 1
#define MMC_DATA_WRITE 2
#define SDH_BLOCK_SIZE 512ul
struct mmc_cmd
{
unsigned short cmdidx;
unsigned int resp_type;
unsigned int cmdarg;
unsigned int response[4];
};
struct mmc_data
{
union
{
char *dest;
const char *src; /* src buffers don't get written to */
};
unsigned int flags;
unsigned int blocks;
unsigned int blocksize;
};
#define SDH_ISCARDINSERTED(SDH) (SDH->S_PSTATE.CARD_INSERTED && SDH->S_PSTATE.CARD_STABLE)
/*@}*/ /* end of group SDH_EXPORTED_CONSTANTS */
/** @addtogroup SDH_EXPORTED_FUNCTIONS SDH Exported Functions
@{
*/
void SDH_DumpReg(SDH_T *sdh);
void SDH_Reset(SDH_T *sdh, uint8_t u8Mask);
int SDH_SetBusWidth(SDH_T *sdh, uint32_t u32BusWidth);
uint32_t SDH_SetClock(SDH_T *sdh, uint32_t u32SrcFreqInHz, uint32_t u32ExceptedFreqInHz);
int SD_GetBusStatus(SDH_T *sdh, uint32_t cmdidx);
void SDH_SetPower(SDH_T *sdh, uint32_t u32OnOff);
/*@}*/ /* end of group SDH_EXPORTED_FUNCTIONS */
/*@}*/ /* end of group SDH_Driver */
/*@}*/ /* end of group Standard_Driver */
#ifdef __cplusplus
}
#endif
#endif

607
bsp/nuvoton/libraries/ma35/StdDriver/inc/nu_spi.h Normal file
View File

@ -0,0 +1,607 @@
/**************************************************************************//**
* @file nu_spi.h
* @brief SPI driver header file
*
* SPDX-License-Identifier: Apache-2.0
* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __NU_SPI_H__
#define __NU_SPI_H__
#ifdef __cplusplus
extern "C"
{
#endif
/** @addtogroup Standard_Driver Standard Driver
@{
*/
/** @addtogroup SPI_Driver SPI Driver
@{
*/
/** @addtogroup SPI_EXPORTED_CONSTANTS SPI Exported Constants
@{
*/
#define SPI_MODE_0 (SPI_CTL_TXNEG_Msk) /*!< CLKPOL=0; RXNEG=0; TXNEG=1 \hideinitializer */
#define SPI_MODE_1 (SPI_CTL_RXNEG_Msk) /*!< CLKPOL=0; RXNEG=1; TXNEG=0 \hideinitializer */
#define SPI_MODE_2 (SPI_CTL_CLKPOL_Msk | SPI_CTL_RXNEG_Msk) /*!< CLKPOL=1; RXNEG=1; TXNEG=0 \hideinitializer */
#define SPI_MODE_3 (SPI_CTL_CLKPOL_Msk | SPI_CTL_TXNEG_Msk) /*!< CLKPOL=1; RXNEG=0; TXNEG=1 \hideinitializer */
#define SPI_SLAVE (SPI_CTL_SLAVE_Msk) /*!< Set as slave \hideinitializer */
#define SPI_MASTER (0x0U) /*!< Set as master \hideinitializer */
#define SPI_SS (SPI_SSCTL_SS_Msk) /*!< Set SS \hideinitializer */
#define SPI_SS_ACTIVE_HIGH (SPI_SSCTL_SSACTPOL_Msk) /*!< SS active high \hideinitializer */
#define SPI_SS_ACTIVE_LOW (0x0U) /*!< SS active low \hideinitializer */
/* SPI Interrupt Mask */
#define SPI_UNIT_INT_MASK (0x001U) /*!< Unit transfer interrupt mask \hideinitializer */
#define SPI_SSACT_INT_MASK (0x002U) /*!< Slave selection signal active interrupt mask \hideinitializer */
#define SPI_SSINACT_INT_MASK (0x004U) /*!< Slave selection signal inactive interrupt mask \hideinitializer */
#define SPI_SLVUR_INT_MASK (0x008U) /*!< Slave under run interrupt mask \hideinitializer */
#define SPI_SLVBE_INT_MASK (0x010U) /*!< Slave bit count error interrupt mask \hideinitializer */
#define SPI_TXUF_INT_MASK (0x040U) /*!< Slave TX underflow interrupt mask \hideinitializer */
#define SPI_FIFO_TXTH_INT_MASK (0x080U) /*!< FIFO TX threshold interrupt mask \hideinitializer */
#define SPI_FIFO_RXTH_INT_MASK (0x100U) /*!< FIFO RX threshold interrupt mask \hideinitializer */
#define SPI_FIFO_RXOV_INT_MASK (0x200U) /*!< FIFO RX overrun interrupt mask \hideinitializer */
#define SPI_FIFO_RXTO_INT_MASK (0x400U) /*!< FIFO RX time-out interrupt mask \hideinitializer */
/* SPI Status Mask */
#define SPI_BUSY_MASK (0x01U) /*!< Busy status mask \hideinitializer */
#define SPI_RX_EMPTY_MASK (0x02U) /*!< RX empty status mask \hideinitializer */
#define SPI_RX_FULL_MASK (0x04U) /*!< RX full status mask \hideinitializer */
#define SPI_TX_EMPTY_MASK (0x08U) /*!< TX empty status mask \hideinitializer */
#define SPI_TX_FULL_MASK (0x10U) /*!< TX full status mask \hideinitializer */
#define SPI_TXRX_RESET_MASK (0x20U) /*!< TX or RX reset status mask \hideinitializer */
#define SPI_SPIEN_STS_MASK (0x40U) /*!< SPIEN status mask \hideinitializer */
#define SPI_SSLINE_STS_MASK (0x80U) /*!< SPIx_SS line status mask \hideinitializer */
/* I2S Data Width */
#define SPII2S_DATABIT_8 (0U << SPI_I2SCTL_WDWIDTH_Pos) /*!< I2S data width is 8-bit \hideinitializer */
#define SPII2S_DATABIT_16 (1U << SPI_I2SCTL_WDWIDTH_Pos) /*!< I2S data width is 16-bit \hideinitializer */
#define SPII2S_DATABIT_24 (2U << SPI_I2SCTL_WDWIDTH_Pos) /*!< I2S data width is 24-bit \hideinitializer */
#define SPII2S_DATABIT_32 (3U << SPI_I2SCTL_WDWIDTH_Pos) /*!< I2S data width is 32-bit \hideinitializer */
/* I2S Audio Format */
#define SPII2S_MONO SPI_I2SCTL_MONO_Msk /*!< Monaural channel \hideinitializer */
#define SPII2S_STEREO (0U) /*!< Stereo channel \hideinitializer */
/* I2S Data Format */
#define SPII2S_FORMAT_I2S (0U<<SPI_I2SCTL_FORMAT_Pos) /*!< I2S data format \hideinitializer */
#define SPII2S_FORMAT_MSB (1U<<SPI_I2SCTL_FORMAT_Pos) /*!< MSB justified data format \hideinitializer */
#define SPII2S_FORMAT_PCMA (2U<<SPI_I2SCTL_FORMAT_Pos) /*!< PCM mode A data format \hideinitializer */
#define SPII2S_FORMAT_PCMB (3U<<SPI_I2SCTL_FORMAT_Pos) /*!< PCM mode B data format \hideinitializer */
/* I2S Operation mode */
#define SPII2S_MODE_SLAVE SPI_I2SCTL_SLAVE_Msk /*!< As slave mode \hideinitializer */
#define SPII2S_MODE_MASTER (0U) /*!< As master mode \hideinitializer */
/* I2S Record Channel */
#define SPII2S_MONO_RIGHT (0U) /*!< Record mono right channel \hideinitializer */
#define SPII2S_MONO_LEFT SPI_I2SCTL_RXLCH_Msk /*!< Record mono left channel \hideinitializer */
/* I2S Channel */
#define SPII2S_RIGHT (0U) /*!< Select right channel \hideinitializer */
#define SPII2S_LEFT (1U) /*!< Select left channel \hideinitializer */
/* I2S Interrupt Mask */
#define SPII2S_FIFO_TXTH_INT_MASK (0x01U) /*!< TX FIFO threshold interrupt mask \hideinitializer */
#define SPII2S_FIFO_RXTH_INT_MASK (0x02U) /*!< RX FIFO threshold interrupt mask \hideinitializer */
#define SPII2S_FIFO_RXOV_INT_MASK (0x04U) /*!< RX FIFO overrun interrupt mask \hideinitializer */
#define SPII2S_FIFO_RXTO_INT_MASK (0x08U) /*!< RX FIFO time-out interrupt mask \hideinitializer */
#define SPII2S_TXUF_INT_MASK (0x10U) /*!< TX FIFO underflow interrupt mask \hideinitializer */
#define SPII2S_RIGHT_ZC_INT_MASK (0x20U) /*!< Right channel zero cross interrupt mask \hideinitializer */
#define SPII2S_LEFT_ZC_INT_MASK (0x40U) /*!< Left channel zero cross interrupt mask \hideinitializer */
/*@}*/ /* end of group SPI_EXPORTED_CONSTANTS */
/** @addtogroup SPI_EXPORTED_FUNCTIONS SPI Exported Functions
@{
*/
/**
* @brief Clear the unit transfer interrupt flag.
* @param[in] spi The pointer of the specified SPI module.
* @return None.
* @details Write 1 to UNITIF bit of SPI_STATUS register to clear the unit transfer interrupt flag.
* \hideinitializer
*/
#define SPI_CLR_UNIT_TRANS_INT_FLAG(spi) ((spi)->STATUS = SPI_STATUS_UNITIF_Msk)
/**
* @brief Trigger RX PDMA function.
* @param[in] spi The pointer of the specified SPI module.
* @return None.
* @details Set RXPDMAEN bit of SPI_PDMACTL register to enable RX PDMA transfer function.
* \hideinitializer
*/
#define SPI_TRIGGER_RX_PDMA(spi) ((spi)->PDMACTL |= SPI_PDMACTL_RXPDMAEN_Msk)
/**
* @brief Trigger TX PDMA function.
* @param[in] spi The pointer of the specified SPI module.
* @return None.
* @details Set TXPDMAEN bit of SPI_PDMACTL register to enable TX PDMA transfer function.
* \hideinitializer
*/
#define SPI_TRIGGER_TX_PDMA(spi) ((spi)->PDMACTL |= SPI_PDMACTL_TXPDMAEN_Msk)
/**
* @brief Trigger TX and RX PDMA function.
* @param[in] spi The pointer of the specified SPI module.
* @return None.
* @details Set TXPDMAEN bit and RXPDMAEN bit of SPI_PDMACTL register to enable TX and RX PDMA transfer function.
* \hideinitializer
*/
#define SPI_TRIGGER_TX_RX_PDMA(spi) ((spi)->PDMACTL |= (SPI_PDMACTL_TXPDMAEN_Msk | SPI_PDMACTL_RXPDMAEN_Msk))
/**
* @brief Disable RX PDMA transfer.
* @param[in] spi The pointer of the specified SPI module.
* @return None.
* @details Clear RXPDMAEN bit of SPI_PDMACTL register to disable RX PDMA transfer function.
* \hideinitializer
*/
#define SPI_DISABLE_RX_PDMA(spi) ( (spi)->PDMACTL &= ~SPI_PDMACTL_RXPDMAEN_Msk )
/**
* @brief Disable TX PDMA transfer.
* @param[in] spi The pointer of the specified SPI module.
* @return None.
* @details Clear TXPDMAEN bit of SPI_PDMACTL register to disable TX PDMA transfer function.
* \hideinitializer
*/
#define SPI_DISABLE_TX_PDMA(spi) ( (spi)->PDMACTL &= ~SPI_PDMACTL_TXPDMAEN_Msk )
/**
* @brief Disable TX and RX PDMA transfer.
* @param[in] spi The pointer of the specified SPI module.
* @return None.
* @details Clear TXPDMAEN bit and RXPDMAEN bit of SPI_PDMACTL register to disable TX and RX PDMA transfer function.
* \hideinitializer
*/
#define SPI_DISABLE_TX_RX_PDMA(spi) ( (spi)->PDMACTL &= ~(SPI_PDMACTL_TXPDMAEN_Msk | SPI_PDMACTL_RXPDMAEN_Msk) )
/**
* @brief Get the count of available data in RX FIFO.
* @param[in] spi The pointer of the specified SPI module.
* @return The count of available data in RX FIFO.
* @details Read RXCNT (SPI_STATUS[27:24]) to get the count of available data in RX FIFO.
* \hideinitializer
*/
#define SPI_GET_RX_FIFO_COUNT(spi) (((spi)->STATUS & SPI_STATUS_RXCNT_Msk) >> SPI_STATUS_RXCNT_Pos)
/**
* @brief Get the RX FIFO empty flag.
* @param[in] spi The pointer of the specified SPI module.
* @retval 0 RX FIFO is not empty.
* @retval 1 RX FIFO is empty.
* @details Read RXEMPTY bit of SPI_STATUS register to get the RX FIFO empty flag.
* \hideinitializer
*/
#define SPI_GET_RX_FIFO_EMPTY_FLAG(spi) (((spi)->STATUS & SPI_STATUS_RXEMPTY_Msk)>>SPI_STATUS_RXEMPTY_Pos)
/**
* @brief Get the TX FIFO empty flag.
* @param[in] spi The pointer of the specified SPI module.
* @retval 0 TX FIFO is not empty.
* @retval 1 TX FIFO is empty.
* @details Read TXEMPTY bit of SPI_STATUS register to get the TX FIFO empty flag.
* \hideinitializer
*/
#define SPI_GET_TX_FIFO_EMPTY_FLAG(spi) (((spi)->STATUS & SPI_STATUS_TXEMPTY_Msk)>>SPI_STATUS_TXEMPTY_Pos)
/**
* @brief Get the TX FIFO full flag.
* @param[in] spi The pointer of the specified SPI module.
* @retval 0 TX FIFO is not full.
* @retval 1 TX FIFO is full.
* @details Read TXFULL bit of SPI_STATUS register to get the TX FIFO full flag.
* \hideinitializer
*/
#define SPI_GET_TX_FIFO_FULL_FLAG(spi) (((spi)->STATUS & SPI_STATUS_TXFULL_Msk)>>SPI_STATUS_TXFULL_Pos)
/**
* @brief Get the datum read from RX register.
* @param[in] spi The pointer of the specified SPI module.
* @return Data in RX register.
* @details Read SPI_RX register to get the received datum.
* \hideinitializer
*/
#define SPI_READ_RX(spi) ((spi)->RX)
/**
* @brief Write datum to TX register.
* @param[in] spi The pointer of the specified SPI module.
* @param[in] u32TxData The datum which user attempt to transfer through SPI bus.
* @return None.
* @details Write u32TxData to SPI_TX register.
* \hideinitializer
*/
#define SPI_WRITE_TX(spi, u32TxData) ((spi)->TX = (u32TxData))
/**
* @brief Set SPIx_SS pin to high state.
* @param[in] spi The pointer of the specified SPI module.
* @return None.
* @details Disable automatic slave selection function and set SPIx_SS pin to high state.
* \hideinitializer
*/
#define SPI_SET_SS_HIGH(spi) ((spi)->SSCTL = ((spi)->SSCTL & (~SPI_SSCTL_AUTOSS_Msk)) | (SPI_SSCTL_SSACTPOL_Msk | SPI_SSCTL_SS_Msk))
/**
* @brief Set SPIx_SS pin to low state.
* @param[in] spi The pointer of the specified SPI module.
* @return None.
* @details Disable automatic slave selection function and set SPIx_SS pin to low state.
* \hideinitializer
*/
#define SPI_SET_SS_LOW(spi) ((spi)->SSCTL = ((spi)->SSCTL & (~(SPI_SSCTL_AUTOSS_Msk | SPI_SSCTL_SSACTPOL_Msk))) | SPI_SSCTL_SS_Msk)
/**
* @brief Enable Byte Reorder function.
* @param[in] spi The pointer of the specified SPI module.
* @return None.
* @details Enable Byte Reorder function. The suspend interval depends on the setting of SUSPITV (SPI_CTL[7:4]).
* \hideinitializer
*/
#define SPI_ENABLE_BYTE_REORDER(spi) ((spi)->CTL |= SPI_CTL_REORDER_Msk)
/**
* @brief Disable Byte Reorder function.
* @param[in] spi The pointer of the specified SPI module.
* @return None.
* @details Clear REORDER bit field of SPI_CTL register to disable Byte Reorder function.
* \hideinitializer
*/
#define SPI_DISABLE_BYTE_REORDER(spi) ((spi)->CTL &= ~SPI_CTL_REORDER_Msk)
/**
* @brief Set the length of suspend interval.
* @param[in] spi The pointer of the specified SPI module.
* @param[in] u32SuspCycle Decides the length of suspend interval. It could be 0 ~ 15.
* @return None.
* @details Set the length of suspend interval according to u32SuspCycle.
* The length of suspend interval is ((u32SuspCycle + 0.5) * the length of one SPI bus clock cycle).
* \hideinitializer
*/
#define SPI_SET_SUSPEND_CYCLE(spi, u32SuspCycle) ((spi)->CTL = ((spi)->CTL & ~SPI_CTL_SUSPITV_Msk) | ((u32SuspCycle) << SPI_CTL_SUSPITV_Pos))
/**
* @brief Set the SPI transfer sequence with LSB first.
* @param[in] spi The pointer of the specified SPI module.
* @return None.
* @details Set LSB bit of SPI_CTL register to set the SPI transfer sequence with LSB first.
* \hideinitializer
*/
#define SPI_SET_LSB_FIRST(spi) ((spi)->CTL |= SPI_CTL_LSB_Msk)
/**
* @brief Set the SPI transfer sequence with MSB first.
* @param[in] spi The pointer of the specified SPI module.
* @return None.
* @details Clear LSB bit of SPI_CTL register to set the SPI transfer sequence with MSB first.
* \hideinitializer
*/
#define SPI_SET_MSB_FIRST(spi) ((spi)->CTL &= ~SPI_CTL_LSB_Msk)
/**
* @brief Set the data width of a SPI transaction.
* @param[in] spi The pointer of the specified SPI module.
* @param[in] u32Width The bit width of one transaction.
* @return None.
* @details The data width can be 8 ~ 32 bits.
* \hideinitializer
*/
#define SPI_SET_DATA_WIDTH(spi, u32Width) ((spi)->CTL = ((spi)->CTL & ~SPI_CTL_DWIDTH_Msk) | (((u32Width)&0x1F) << SPI_CTL_DWIDTH_Pos))
/**
* @brief Get the SPI busy state.
* @param[in] spi The pointer of the specified SPI module.
* @retval 0 SPI controller is not busy.
* @retval 1 SPI controller is busy.
* @details This macro will return the busy state of SPI controller.
* \hideinitializer
*/
#define SPI_IS_BUSY(spi) ( ((spi)->STATUS & SPI_STATUS_BUSY_Msk)>>SPI_STATUS_BUSY_Pos )
/**
* @brief Enable SPI controller.
* @param[in] spi The pointer of the specified SPI module.
* @return None.
* @details Set SPIEN (SPI_CTL[0]) to enable SPI controller.
* \hideinitializer
*/
#define SPI_ENABLE(spi) ((spi)->CTL |= SPI_CTL_SPIEN_Msk)
/**
* @brief Disable SPI controller.
* @param[in] spi The pointer of the specified SPI module.
* @return None.
* @details Clear SPIEN (SPI_CTL[0]) to disable SPI controller.
* \hideinitializer
*/
#define SPI_DISABLE(spi) ((spi)->CTL &= ~SPI_CTL_SPIEN_Msk)
/* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */
__STATIC_INLINE void SPII2S_ENABLE_TX_ZCD(SPI_T *i2s, uint32_t u32ChMask);
__STATIC_INLINE void SPII2S_DISABLE_TX_ZCD(SPI_T *i2s, uint32_t u32ChMask);
__STATIC_INLINE void SPII2S_SET_MONO_RX_CHANNEL(SPI_T *i2s, uint32_t u32Ch);
/**
* @brief Enable zero cross detection function.
* @param[in] i2s The pointer of the specified I2S module.
* @param[in] u32ChMask The mask for left or right channel. Valid values are:
* - \ref SPII2S_RIGHT
* - \ref SPII2S_LEFT
* @return None
* @details This function will set RZCEN or LZCEN bit of SPI_I2SCTL register to enable zero cross detection function.
*/
__STATIC_INLINE void SPII2S_ENABLE_TX_ZCD(SPI_T *i2s, uint32_t u32ChMask)
{
if (u32ChMask == SPII2S_RIGHT)
{
i2s->I2SCTL |= SPI_I2SCTL_RZCEN_Msk;
}
else
{
i2s->I2SCTL |= SPI_I2SCTL_LZCEN_Msk;
}
}
/**
* @brief Disable zero cross detection function.
* @param[in] i2s The pointer of the specified I2S module.
* @param[in] u32ChMask The mask for left or right channel. Valid values are:
* - \ref SPII2S_RIGHT
* - \ref SPII2S_LEFT
* @return None
* @details This function will clear RZCEN or LZCEN bit of SPI_I2SCTL register to disable zero cross detection function.
*/
__STATIC_INLINE void SPII2S_DISABLE_TX_ZCD(SPI_T *i2s, uint32_t u32ChMask)
{
if (u32ChMask == SPII2S_RIGHT)
{
i2s->I2SCTL &= ~SPI_I2SCTL_RZCEN_Msk;
}
else
{
i2s->I2SCTL &= ~SPI_I2SCTL_LZCEN_Msk;
}
}
/**
* @brief Enable I2S TX DMA function.
* @param[in] i2s The pointer of the specified I2S module.
* @return None
* @details This macro will set TXPDMAEN bit of SPI_PDMACTL register to transmit data with PDMA.
* \hideinitializer
*/
#define SPII2S_ENABLE_TXDMA(i2s) ( (i2s)->PDMACTL |= SPI_PDMACTL_TXPDMAEN_Msk )
/**
* @brief Disable I2S TX DMA function.
* @param[in] i2s The pointer of the specified I2S module.
* @return None
* @details This macro will clear TXPDMAEN bit of SPI_PDMACTL register to disable TX DMA function.
* \hideinitializer
*/
#define SPII2S_DISABLE_TXDMA(i2s) ( (i2s)->PDMACTL &= ~SPI_PDMACTL_TXPDMAEN_Msk )
/**
* @brief Enable I2S RX DMA function.
* @param[in] i2s The pointer of the specified I2S module.
* @return None
* @details This macro will set RXPDMAEN bit of SPI_PDMACTL register to receive data with PDMA.
* \hideinitializer
*/
#define SPII2S_ENABLE_RXDMA(i2s) ( (i2s)->PDMACTL |= SPI_PDMACTL_RXPDMAEN_Msk )
/**
* @brief Disable I2S RX DMA function.
* @param[in] i2s The pointer of the specified I2S module.
* @return None
* @details This macro will clear RXPDMAEN bit of SPI_PDMACTL register to disable RX DMA function.
* \hideinitializer
*/
#define SPII2S_DISABLE_RXDMA(i2s) ( (i2s)->PDMACTL &= ~SPI_PDMACTL_RXPDMAEN_Msk )
/**
* @brief Enable I2S TX function.
* @param[in] i2s The pointer of the specified I2S module.
* @return None
* @details This macro will set TXEN bit of SPI_I2SCTL register to enable I2S TX function.
* \hideinitializer
*/
#define SPII2S_ENABLE_TX(i2s) ( (i2s)->I2SCTL |= SPI_I2SCTL_TXEN_Msk )
/**
* @brief Disable I2S TX function.
* @param[in] i2s The pointer of the specified I2S module.
* @return None
* @details This macro will clear TXEN bit of SPI_I2SCTL register to disable I2S TX function.
* \hideinitializer
*/
#define SPII2S_DISABLE_TX(i2s) ( (i2s)->I2SCTL &= ~SPI_I2SCTL_TXEN_Msk )
/**
* @brief Enable I2S RX function.
* @param[in] i2s The pointer of the specified I2S module.
* @return None
* @details This macro will set RXEN bit of SPI_I2SCTL register to enable I2S RX function.
* \hideinitializer
*/
#define SPII2S_ENABLE_RX(i2s) ( (i2s)->I2SCTL |= SPI_I2SCTL_RXEN_Msk )
/**
* @brief Disable I2S RX function.
* @param[in] i2s The pointer of the specified I2S module.
* @return None
* @details This macro will clear RXEN bit of SPI_I2SCTL register to disable I2S RX function.
* \hideinitializer
*/
#define SPII2S_DISABLE_RX(i2s) ( (i2s)->I2SCTL &= ~SPI_I2SCTL_RXEN_Msk )
/**
* @brief Enable TX Mute function.
* @param[in] i2s The pointer of the specified I2S module.
* @return None
* @details This macro will set MUTE bit of SPI_I2SCTL register to enable I2S TX mute function.
* \hideinitializer
*/
#define SPII2S_ENABLE_TX_MUTE(i2s) ( (i2s)->I2SCTL |= SPI_I2SCTL_MUTE_Msk )
/**
* @brief Disable TX Mute function.
* @param[in] i2s The pointer of the specified I2S module.
* @return None
* @details This macro will clear MUTE bit of SPI_I2SCTL register to disable I2S TX mute function.
* \hideinitializer
*/
#define SPII2S_DISABLE_TX_MUTE(i2s) ( (i2s)->I2SCTL &= ~SPI_I2SCTL_MUTE_Msk )
/**
* @brief Clear TX FIFO.
* @param[in] i2s The pointer of the specified I2S module.
* @return None
* @details This macro will clear TX FIFO. The internal TX FIFO pointer will be reset to FIFO start point.
* \hideinitializer
*/
#define SPII2S_CLR_TX_FIFO(i2s) ( (i2s)->FIFOCTL |= SPI_FIFOCTL_TXFBCLR_Msk )
/**
* @brief Clear RX FIFO.
* @param[in] i2s The pointer of the specified I2S module.
* @return None
* @details This macro will clear RX FIFO. The internal RX FIFO pointer will be reset to FIFO start point.
* \hideinitializer
*/
#define SPII2S_CLR_RX_FIFO(i2s) ( (i2s)->FIFOCTL |= SPI_FIFOCTL_RXFBCLR_Msk )
/**
* @brief This function sets the recording source channel when mono mode is used.
* @param[in] i2s The pointer of the specified I2S module.
* @param[in] u32Ch left or right channel. Valid values are:
* - \ref SPII2S_MONO_LEFT
* - \ref SPII2S_MONO_RIGHT
* @return None
* @details This function selects the recording source channel of monaural mode.
* \hideinitializer
*/
__STATIC_INLINE void SPII2S_SET_MONO_RX_CHANNEL(SPI_T *i2s, uint32_t u32Ch)
{
u32Ch == SPII2S_MONO_LEFT ?
(i2s->I2SCTL |= SPI_I2SCTL_RXLCH_Msk) :
(i2s->I2SCTL &= ~SPI_I2SCTL_RXLCH_Msk);
}
/**
* @brief Write data to I2S TX FIFO.
* @param[in] i2s The pointer of the specified I2S module.
* @param[in] u32Data The value written to TX FIFO.
* @return None
* @details This macro will write a value to TX FIFO.
* \hideinitializer
*/
#define SPII2S_WRITE_TX_FIFO(i2s, u32Data) ( (i2s)->TX = (u32Data) )
/**
* @brief Read RX FIFO.
* @param[in] i2s The pointer of the specified I2S module.
* @return The value read from RX FIFO.
* @details This function will return a value read from RX FIFO.
* \hideinitializer
*/
#define SPII2S_READ_RX_FIFO(i2s) ( (i2s)->RX )
/**
* @brief Get the interrupt flag.
* @param[in] i2s The pointer of the specified I2S module.
* @param[in] u32Mask The mask value for all interrupt flags.
* @return The interrupt flags specified by the u32mask parameter.
* @details This macro will return the combination interrupt flags of SPI_I2SSTS register. The flags are specified by the u32mask parameter.
* \hideinitializer
*/
#define SPII2S_GET_INT_FLAG(i2s, u32Mask) ( (i2s)->I2SSTS & (u32Mask) )
/**
* @brief Clear the interrupt flag.
* @param[in] i2s The pointer of the specified I2S module.
* @param[in] u32Mask The mask value for all interrupt flags.
* @return None
* @details This macro will clear the interrupt flags specified by the u32mask parameter.
* @note Except TX and RX FIFO threshold interrupt flags, the other interrupt flags can be cleared by writing 1 to itself.
* \hideinitializer
*/
#define SPII2S_CLR_INT_FLAG(i2s, u32Mask) ( (i2s)->I2SSTS = (u32Mask) )
/**
* @brief Get transmit FIFO level
* @param[in] i2s The pointer of the specified I2S module.
* @return TX FIFO level
* @details This macro will return the number of available words in TX FIFO.
* \hideinitializer
*/
#define SPII2S_GET_TX_FIFO_LEVEL(i2s) ( ((i2s)->I2SSTS & SPI_I2SSTS_TXCNT_Msk) >> SPI_I2SSTS_TXCNT_Pos )
/**
* @brief Get receive FIFO level
* @param[in] i2s The pointer of the specified I2S module.
* @return RX FIFO level
* @details This macro will return the number of available words in RX FIFO.
* \hideinitializer
*/
#define SPII2S_GET_RX_FIFO_LEVEL(i2s) ( ((i2s)->I2SSTS & SPI_I2SSTS_RXCNT_Msk) >> SPI_I2SSTS_RXCNT_Pos )
/**
* @brief Set SPI Master Receive Phase.
* @param[in] spi is the base address of SPI module.
* @param[in] rxdly is the clock cycle of delay for rx phase.
* @return none
* \hideinitializer
*/
#define SPI_SET_MRXPHASE(spi, rxdly) ( (spi)->INTERNAL = ((spi)->INTERNAL & ~SPI_INTERNAL_MRXPHASE_Msk) | (rxdly<<SPI_INTERNAL_MRXPHASE_Pos) )
/* Function prototype declaration */
uint32_t SPI_Open(SPI_T *spi, uint32_t u32MasterSlave, uint32_t u32SPIMode, uint32_t u32DataWidth, uint32_t u32BusClock);
void SPI_Close(SPI_T *spi);
void SPI_ClearRxFIFO(SPI_T *spi);
void SPI_ClearTxFIFO(SPI_T *spi);
void SPI_DisableAutoSS(SPI_T *spi);
void SPI_EnableAutoSS(SPI_T *spi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel);
uint32_t SPI_SetBusClock(SPI_T *spi, uint32_t u32BusClock);
void SPI_SetFIFO(SPI_T *spi, uint32_t u32TxThreshold, uint32_t u32RxThreshold);
uint32_t SPI_GetBusClock(SPI_T *spi);
void SPI_EnableInt(SPI_T *spi, uint32_t u32Mask);
void SPI_DisableInt(SPI_T *spi, uint32_t u32Mask);
uint32_t SPI_GetIntFlag(SPI_T *spi, uint32_t u32Mask);
void SPI_ClearIntFlag(SPI_T *spi, uint32_t u32Mask);
uint32_t SPI_GetStatus(SPI_T *spi, uint32_t u32Mask);
uint32_t SPII2S_Open(SPI_T *i2s, uint32_t u32MasterSlave, uint32_t u32SampleRate, uint32_t u32WordWidth, uint32_t u32Channels, uint32_t u32DataFormat);
void SPII2S_Close(SPI_T *i2s);
void SPII2S_EnableInt(SPI_T *i2s, uint32_t u32Mask);
void SPII2S_DisableInt(SPI_T *i2s, uint32_t u32Mask);
uint32_t SPII2S_EnableMCLK(SPI_T *i2s, uint32_t u32BusClock);
void SPII2S_DisableMCLK(SPI_T *i2s);
void SPII2S_SetFIFO(SPI_T *i2s, uint32_t u32TxThreshold, uint32_t u32RxThreshold);
/*@}*/ /* end of group SPI_EXPORTED_FUNCTIONS */
/*@}*/ /* end of group SPI_Driver */
/*@}*/ /* end of group Standard_Driver */
#ifdef __cplusplus
}
#endif
#endif

Some files were not shown because too many files have changed in this diff Show More