mirror of https://github.com/RT-Thread/rt-thread
bsp/stm32: Separate STM32WB HAL drivers (#10223)
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@ -111,6 +111,7 @@ config SOC_SERIES_STM32WB
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bool
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select ARCH_ARM_CORTEX_M4
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select SOC_FAMILY_STM32
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select PKG_USING_STM32WB_HAL_DRIVER
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config BOARD_SERIES_STM32_NUCLEO_32
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bool
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@ -1,233 +0,0 @@
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/**
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******************************************************************************
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* @file stm32wbxx.h
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* @author MCD Application Team
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* @brief CMSIS STM32WBxx Device Peripheral Access Layer Header File.
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*
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* The file is the unique include file that the application programmer
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* is using in the C source code, usually in main.c. This file contains:
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* - Configuration section that allows to select:
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* - The STM32WBxx device used in the target application
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* - To use or not the peripheral's drivers in application code(i.e.
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* code will be based on direct access to peripheral's registers
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* rather than drivers API), this option is controlled by
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* "#define USE_HAL_DRIVER"
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*
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******************************************************************************
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* @attention
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*
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* Copyright (c) 2019-2021 STMicroelectronics.
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* All rights reserved.
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*
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* This software is licensed under terms that can be found in the LICENSE file
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* in the root directory of this software component.
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* If no LICENSE file comes with this software, it is provided AS-IS.
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*
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******************************************************************************
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*/
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/** @addtogroup CMSIS
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* @{
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*/
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/** @addtogroup stm32wbxx
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* @{
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*/
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#ifndef __STM32WBxx_H
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#define __STM32WBxx_H
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#ifdef __cplusplus
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extern "C" {
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#endif /* __cplusplus */
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/** @addtogroup Library_configuration_section
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* @{
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*/
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/**
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* @brief STM32 Family
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*/
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#if !defined (STM32WB)
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#define STM32WB
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#endif /* STM32WB */
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/* Tip: To avoid modifying this file each time you need to switch between these
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devices, you can define the device in your toolchain compiler preprocessor.
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*/
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#if !defined (USE_HAL_DRIVER)
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/**
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* @brief Comment the line below if you will not use the peripherals drivers.
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In this case, these drivers will not be included and the application code will
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be based on direct access to peripherals registers
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*/
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/*#define USE_HAL_DRIVER */
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#endif /* USE_HAL_DRIVER */
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/**
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* @brief CMSIS Device version number
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*/
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#define __STM32WBxx_CMSIS_VERSION_MAIN (0x01U) /*!< [31:24] main version */
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#define __STM32WBxx_CMSIS_VERSION_SUB1 (0x09U) /*!< [23:16] sub1 version */
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#define __STM32WBxx_CMSIS_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */
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#define __STM32WBxx_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */
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#define __STM32WBxx_CMSIS_DEVICE_VERSION ((__STM32WBxx_CMSIS_VERSION_MAIN << 24)\
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|(__STM32WBxx_CMSIS_VERSION_SUB1 << 16)\
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|(__STM32WBxx_CMSIS_VERSION_SUB2 << 8 )\
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|(__STM32WBxx_CMSIS_VERSION_RC))
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/**
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* @}
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*/
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/** @addtogroup Device_Included
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* @{
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*/
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#if defined(STM32WB55xx)
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#include "stm32wb55xx.h"
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#elif defined(STM32WB5Mxx)
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#include "stm32wb5mxx.h"
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#elif defined(STM32WB50xx)
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#include "stm32wb50xx.h"
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#elif defined(STM32WB35xx)
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#include "stm32wb35xx.h"
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#elif defined(STM32WB30xx)
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#include "stm32wb30xx.h"
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#elif defined(STM32WB15xx)
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#include "stm32wb15xx.h"
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#elif defined(STM32WB10xx)
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#include "stm32wb10xx.h"
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#else
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#error "Please select first the target STM32WBxx device used in your application, for instance xxx (in stm32wbxx.h file)"
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#endif
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/**
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* @}
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*/
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/** @addtogroup Exported_types
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* @{
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*/
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typedef enum
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{
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RESET = 0,
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SET = !RESET
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} FlagStatus, ITStatus;
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typedef enum
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{
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DISABLE = 0,
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ENABLE = !DISABLE
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} FunctionalState;
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#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
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typedef enum
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{
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SUCCESS = 0,
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ERROR = !SUCCESS
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} ErrorStatus;
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/**
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* @}
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*/
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/** @addtogroup Exported_macros
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* @{
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*/
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#define SET_BIT(REG, BIT) ((REG) |= (BIT))
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#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
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#define READ_BIT(REG, BIT) ((REG) & (BIT))
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#define CLEAR_REG(REG) ((REG) = (0x0))
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#define WRITE_REG(REG, VAL) ((REG) = (VAL))
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#define READ_REG(REG) ((REG))
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#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
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/* Use of CMSIS compiler intrinsics for register exclusive access */
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/* Atomic 32-bit register access macro to set one or several bits */
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#define ATOMIC_SET_BIT(REG, BIT) \
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do { \
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uint32_t val; \
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do { \
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val = __LDREXW((__IO uint32_t *)&(REG)) | (BIT); \
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} while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \
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} while(0)
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/* Atomic 32-bit register access macro to clear one or several bits */
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#define ATOMIC_CLEAR_BIT(REG, BIT) \
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do { \
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uint32_t val; \
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do { \
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val = __LDREXW((__IO uint32_t *)&(REG)) & ~(BIT); \
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} while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \
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} while(0)
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/* Atomic 32-bit register access macro to clear and set one or several bits */
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#define ATOMIC_MODIFY_REG(REG, CLEARMSK, SETMASK) \
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do { \
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uint32_t val; \
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do { \
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val = (__LDREXW((__IO uint32_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \
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} while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \
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} while(0)
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/* Atomic 16-bit register access macro to set one or several bits */
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#define ATOMIC_SETH_BIT(REG, BIT) \
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do { \
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uint16_t val; \
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do { \
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val = __LDREXH((__IO uint16_t *)&(REG)) | (BIT); \
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} while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \
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} while(0)
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/* Atomic 16-bit register access macro to clear one or several bits */
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#define ATOMIC_CLEARH_BIT(REG, BIT) \
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do { \
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uint16_t val; \
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do { \
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val = __LDREXH((__IO uint16_t *)&(REG)) & ~(BIT); \
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} while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \
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} while(0)
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/* Atomic 16-bit register access macro to clear and set one or several bits */
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#define ATOMIC_MODIFYH_REG(REG, CLEARMSK, SETMASK) \
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do { \
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uint16_t val; \
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do { \
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val = (__LDREXH((__IO uint16_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \
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} while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \
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} while(0)
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#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))
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/**
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* @}
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*/
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#if defined (USE_HAL_DRIVER)
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#include "stm32wbxx_hal.h"
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#endif /* USE_HAL_DRIVER */
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#ifdef __cplusplus
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}
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#endif /* __cplusplus */
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#endif /* __STM32WBxx_H */
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/**
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* @}
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*/
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/**
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* @}
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*/
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/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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@ -1,112 +0,0 @@
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/**
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******************************************************************************
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* @file system_stm32wbxx.h
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* @author MCD Application Team
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* @brief CMSIS Cortex Device System Source File for STM32WBxx devices.
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******************************************************************************
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* @attention
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*
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* Copyright (c) 2019-2021 STMicroelectronics.
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* All rights reserved.
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*
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* This software is licensed under terms that can be found in the LICENSE file
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* in the root directory of this software component.
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* If no LICENSE file comes with this software, it is provided AS-IS.
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*
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******************************************************************************
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*/
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/** @addtogroup CMSIS
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* @{
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*/
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/** @addtogroup stm32wbxx_system
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* @{
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*/
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/**
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* @brief Define to prevent recursive inclusion
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*/
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#ifndef __SYSTEM_STM32WBXX_H
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#define __SYSTEM_STM32WBXX_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <stdint.h>
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/** @addtogroup STM32WBxx_System_Includes
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* @{
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*/
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/**
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* @}
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*/
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/** @addtogroup STM32WBxx_System_Exported_types
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* @{
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*/
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/* The SystemCoreClock variable is updated in three ways:
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1) by calling CMSIS function SystemCoreClockUpdate()
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2) by calling HAL API function HAL_RCC_GetSysClockFreq()
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3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
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Note: If you use this function to configure the system clock; then there
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is no need to call the 2 first functions listed above, since SystemCoreClock
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variable is updated automatically.
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*/
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extern uint32_t SystemCoreClock; /*!< System Clock Frequency */
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extern const uint32_t AHBPrescTable[16]; /*!< AHB prescalers table values */
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extern const uint32_t APBPrescTable[8]; /*!< APB prescalers table values */
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extern const uint32_t MSIRangeTable[16]; /*!< MSI ranges table values */
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#if defined(STM32WB55xx) || defined(STM32WB5Mxx) || defined(STM32WB35xx) || defined (STM32WB15xx) || defined (STM32WB10xx)
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extern const uint32_t SmpsPrescalerTable[4][6]; /*!< SMPS factor ranges table values */
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#endif
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/**
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* @}
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*/
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/** @addtogroup STM32WBxx_System_Exported_Constants
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* @{
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*/
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/**
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* @}
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*/
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/** @addtogroup STM32WBxx_System_Exported_Macros
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* @{
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*/
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/**
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* @}
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*/
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/** @addtogroup STM32WBxx_System_Exported_Functions
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* @{
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*/
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extern void SystemInit(void);
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extern void SystemCoreClockUpdate(void);
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/**
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* @}
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*/
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#ifdef __cplusplus
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}
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#endif
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#endif /*__SYSTEM_STM32WBXX_H */
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/**
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* @}
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*/
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/**
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* @}
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*/
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/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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@ -1,345 +0,0 @@
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<!DOCTYPE html>
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<html xmlns="http://www.w3.org/1999/xhtml" lang="en" xml:lang="en">
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<head>
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<meta charset="utf-8" />
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<meta name="generator" content="pandoc" />
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<meta name="viewport" content="width=device-width, initial-scale=1.0, user-scalable=yes" />
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<title>Release Notes for STM32WBxx CMSIS</title>
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<style type="text/css">
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code{white-space: pre-wrap;}
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span.smallcaps{font-variant: small-caps;}
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span.underline{text-decoration: underline;}
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div.column{display: inline-block; vertical-align: top; width: 50%;}
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</style>
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<link rel="stylesheet" href="_htmresc/mini-st_2020.css" />
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<!--[if lt IE 9]>
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<script src="//cdnjs.cloudflare.com/ajax/libs/html5shiv/3.7.3/html5shiv-printshiv.min.js"></script>
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<![endif]-->
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<link rel="icon" type="image/x-icon" href="_htmresc/favicon.png" />
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</head>
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<body>
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<div class="row">
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<div class="col-sm-12 col-lg-4">
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<center>
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<h1 id="release-notes-for">Release Notes for</h1>
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<h1 id="stm32wbxx-cmsis"><mark>STM32WBxx CMSIS</mark></h1>
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<p>Copyright © 2019 STMicroelectronics<br />
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</p>
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<a href="https://www.st.com" class="logo"><img src="_htmresc/st_logo_2020.png" alt="ST logo" /></a>
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</center>
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<h1 id="purpose">Purpose</h1>
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<p>This driver provides the CMSIS device for the stm32wbxx products. This covers</p>
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<ul>
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<li>STM32WB55xx devices</li>
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<li>STM32WB5Mxx devices</li>
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<li>STM32WB50xx devices</li>
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<li>STM32WB35xx devices</li>
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<li>STM32WB30xx devices</li>
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<li>STM32WB15xx devices</li>
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<li>STM32WB10xx devices</li>
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</ul>
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<p>This driver is composed of the descriptions of the registers under “Include” directory.</p>
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<p>Various template file are provided to easily build an application. They can be adapted to fit applications requirements.</p>
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<ul>
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<li>Templates/system_stm32wbxx.c contains the initialization code referred as SystemInit.</li>
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<li>Startup files are provided as example for IAR©, KEIL© and SW4STM32©.</li>
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<li>Linker files are provided as example for IAR©, KEIL© and SW4STM32©.</li>
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</ul>
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<h1 id="specific-consideration-for-available-flash-size-inside-linker-file">Specific consideration for available FLASH size inside linker file</h1>
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<p>The available flash size depends on the wireless binary used inside the STM32WB device.</p>
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<p>The linker files templates for IAR, KEIL and GCC provide example of implementation which can be tuned.</p>
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<p>You can refer to the below chapters to optimize the usage of the flash on your device.</p>
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<h2 id="stm32wb55xx-stm32wb50xx-and-stm32wb5m">STM32WB55xx, STM32WB50xx and STM32WB5M</h2>
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<p>The default linker file provided in “/Drivers/CMSIS/DeviceST/STM32WBxx/Source/Templates” allows the application to use 512KB of flash.</p>
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<p>The maximum flash memory that can be used by the application is up to the Secure Flash Start Address (SFSA) that can be read from the option byte.</p>
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<p>The __ICFEDIT_region_ROM_end__ in the linker can be modified with a value up to : (0x08000000 + (SFSA << 12)) - 1.</p>
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<p>Example:</p>
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<ul>
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<li>When the SFSA option byte is set to 0xA0, the maximum value to be used for __ICFEDIT_region_ROM_end is 0x0809FFFF which is 640KB of flash.</li>
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</ul>
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<p>Note:</p>
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<ul>
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<li>The SFSA option byte can only be set by the CPU2. The user cannot modify that value.</li>
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</ul>
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<h2 id="stm32wb35xx-and-stm32wb30xx">STM32WB35xx and STM32WB30xx</h2>
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<p>The default linker file provided in "/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates allows the application to use 120KB of flash.</p>
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<p>The maximum flash memory that can be used by the application is up to the Secure Flash Start Address (SFSA) that can be read from the option byte.</p>
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<p>The __ICFEDIT_region_ROM_end__ in the linker can be modified with a value up to : (0x08000000 + (SFSA << 12)) - 1.</p>
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<p>Example:</p>
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<ul>
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<li>When the SFSA option byte is set to 0x32, the maximum value to be used for __ICFEDIT_region_ROM_end is 0x08031FFF – which is 200KB of flash</li>
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</ul>
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<p>Note:</p>
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<ul>
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<li>The SFSA option byte can only be set by the CPU2. The user cannot modify that value.</li>
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</ul>
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<h2 id="stm32wb15xx-and-stm32wb10xx">STM32WB15xx and STM32WB10xx</h2>
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<p>The default linker file provided in "/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates allows the application to use 110KB of flash.</p>
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<p>The maximum flash memory that can be used by the application is up to the Secure Flash Start Address (SFSA) that can be read from the option byte.</p>
|
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<p>The __ICFEDIT_region_ROM_end__ in the linker can be modified with a value up to : (0x08000000 + (SFSA << 11)) - 1 considering minimum CPU secure area size is one sector (2kBytes).</p>
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<p>Example:</p>
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<ul>
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<li>When the SFSA option byte is set to 0x37, the maximum value to be used for __ICFEDIT_region_ROM_end is 0x0801B800 – which is 110kB of flash</li>
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</ul>
|
||||
<p>Note:</p>
|
||||
<ul>
|
||||
<li>The SFSA option byte can only be set by the CPU2. The user cannot modify that value.</li>
|
||||
</ul>
|
||||
</div>
|
||||
<div class="col-sm-12 col-lg-8">
|
||||
<h1 id="update-history">Update History</h1>
|
||||
<div class="collapse">
|
||||
<input type="checkbox" id="collapse-section9" checked aria-hidden="true"> <label for="collapse-section9" aria-hidden="true">V1.9.0 / 24-June-2021</label>
|
||||
<div>
|
||||
<h2 id="main-changes">Main Changes</h2>
|
||||
<ul>
|
||||
<li>Add atomic register access services:
|
||||
<ul>
|
||||
<li>32-bit register access: ATOMIC_SET_BIT(), ATOMIC_CLEAR_BIT(), ATOMIC_MODIFY_REG()</li>
|
||||
<li>16-bit register access: ATOMIC_SETH_BIT(), ATOMIC_CLEARH_BIT(), ATOMIC_MODIFYH_BIT()</li>
|
||||
</ul></li>
|
||||
<li>Update linker files templates for all IDE (.icf/.sct/.ld)
|
||||
<ul>
|
||||
<li>RAM start address has been updated from 0x20000000/0x20000004 to 0x20000008 to be aligned on a 8 byte boundary, and be compatible with ARM Compiler 6 (Keil MDK-ARM)</li>
|
||||
</ul></li>
|
||||
<li>Add define LSI_STARTUP_TIME used in default IWDG timeout calculation (HAL_IWDG_DEFAULT_TIMEOUT)</li>
|
||||
<li>Add define FLASH_ECCR_CPUID bits for new macro __HAL_FLASH_ECC_CPUID() macro</li>
|
||||
</ul>
|
||||
<h2 id="supported-devices-and-boards">Supported Devices and boards</h2>
|
||||
<ul>
|
||||
<li>STM32WB55xx, STM32WB5Mxx, STM32WB50xx, STM32WB35xx, STM32WB30xx, STM32WB15xx and STM32WB10xx devices.</li>
|
||||
</ul>
|
||||
</div>
|
||||
</div>
|
||||
<div class="collapse">
|
||||
<input type="checkbox" id="collapse-section8" aria-hidden="true"> <label for="collapse-section8" aria-hidden="true">V1.8.0 / 09-February-2021</label>
|
||||
<div>
|
||||
<h2 id="main-changes-1">Main Changes</h2>
|
||||
<h3 id="add-support-for-stm32wb15xx-and-stm32wb10xx">Add support for STM32WB15xx and STM32WB10xx</h3>
|
||||
<ul>
|
||||
<li>Change how to adapt VTOR for user</li>
|
||||
</ul>
|
||||
<h2 id="development-toolchains-and-compilers">Development Toolchains and Compilers</h2>
|
||||
<ul>
|
||||
<li>IAR Embedded Workbench for ARM (EWARM) toolchain V8.20.2</li>
|
||||
<li>RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.25</li>
|
||||
<li>System Workbench STM32 (SW4STM32) toolchain V2.7</li>
|
||||
</ul>
|
||||
<h2 id="supported-devices-and-boards-1">Supported Devices and boards</h2>
|
||||
<ul>
|
||||
<li>STM32WB55xx, STM32WB5Mxx, STM32WB50xx, STM32WB35xx, STM32WB30xx, STM32WB15xx and STM32WB10xx devices.</li>
|
||||
</ul>
|
||||
</div>
|
||||
</div>
|
||||
<div class="collapse">
|
||||
<input type="checkbox" id="collapse-section7" aria-hidden="true"> <label for="collapse-section7" aria-hidden="true">V1.7.0 / 30-October-2020</label>
|
||||
<div>
|
||||
<h2 id="main-changes-2">Main Changes</h2>
|
||||
<h3 id="maintenance-release">Maintenance release</h3>
|
||||
<p>Maintenance release for <strong>STM32WBxx</strong> devices (stm32wb55xx, stm32wb50xx, stm32wb35xx and stm32wb30xx devices)</p>
|
||||
<table>
|
||||
<thead>
|
||||
<tr class="header">
|
||||
<th style="text-align: left;">Fixed bugs headline</th>
|
||||
</tr>
|
||||
</thead>
|
||||
<tbody>
|
||||
<tr class="odd">
|
||||
<td style="text-align: left;">[STM32WB35] Remove EXTI_C2IMR2_IM43 and EXTI_IMR2_IM43</td>
|
||||
</tr>
|
||||
<tr class="even">
|
||||
<td style="text-align: left;">[STM32WB50] Remove RCC_CR_HSEBYP</td>
|
||||
</tr>
|
||||
<tr class="odd">
|
||||
<td style="text-align: left;">[STM32WB55] Remove RCC_CR_HSEBYP</td>
|
||||
</tr>
|
||||
<tr class="even">
|
||||
<td style="text-align: left;">[STM32WB5M] Remove RCC_CR_HSEBYP</td>
|
||||
</tr>
|
||||
</tbody>
|
||||
</table>
|
||||
<h2 id="development-toolchains-and-compilers-1">Development Toolchains and Compilers</h2>
|
||||
<ul>
|
||||
<li>IAR Embedded Workbench for ARM (EWARM) toolchain V8.20.2</li>
|
||||
<li>RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.25</li>
|
||||
<li>System Workbench STM32 (SW4STM32) toolchain V2.7</li>
|
||||
</ul>
|
||||
<h2 id="supported-devices-and-boards-2">Supported Devices and boards</h2>
|
||||
<ul>
|
||||
<li>STM32WB55xx, STM32WB5Mxx, STM32WB50xx, STM32WB35xx and STM32WB30xx devices.</li>
|
||||
</ul>
|
||||
</div>
|
||||
</div>
|
||||
<div class="collapse">
|
||||
<input type="checkbox" id="collapse-section6" aria-hidden="true"> <label for="collapse-section6" aria-hidden="true">v1.6.0 / 05-June-2020</label>
|
||||
<div>
|
||||
<h2 id="main-changes-3">Main Changes</h2>
|
||||
<h3 id="maintenance-release-1">Maintenance release</h3>
|
||||
<p>Maintenance release for <strong>STM32WBxx</strong> devices (stm32wb55xx, stm32wb50xx, stm32wb35xx and stm32wb30xx devices)</p>
|
||||
<table>
|
||||
<thead>
|
||||
<tr class="header">
|
||||
<th style="text-align: left;">Fixed bugs headline</th>
|
||||
</tr>
|
||||
</thead>
|
||||
<tbody>
|
||||
<tr class="odd">
|
||||
<td style="text-align: left;">[All devices] Correct DMAMUX_CxCR_DMAREQ_ID_Msk</td>
|
||||
</tr>
|
||||
<tr class="even">
|
||||
<td style="text-align: left;">[All devices] Remove DMAMUX_CxCR_DMAREQ_ID_[6-7]</td>
|
||||
</tr>
|
||||
<tr class="odd">
|
||||
<td style="text-align: left;">[All devices] Call SystemInit first in startup/Reset_Handler, so GCC code is similar to IAR/Keil</td>
|
||||
</tr>
|
||||
<tr class="even">
|
||||
<td style="text-align: left;">[STM32WB50xx and STM32WB30xx] Remove OR register from LPTIM_TypeDef</td>
|
||||
</tr>
|
||||
<tr class="odd">
|
||||
<td style="text-align: left;">[STM32WB50xx and STM32WB30xx] Remove DMAMUX_CSR_SOF[7-13] and DMAMUX_CFR_SOF[7-13]</td>
|
||||
</tr>
|
||||
<tr class="even">
|
||||
<td style="text-align: left;">[STM32WB50xx and STM32WB30xx] Remove EXTI_RTSR1_RTxx_Pos [20, 21 and 31]</td>
|
||||
</tr>
|
||||
<tr class="odd">
|
||||
<td style="text-align: left;">[STM32WB50xx and STM32WB30xx] Remove TIM2_OR_TI4_RMP, TIM2_OR_ITR1_RMP and LPTIM_OR_OR</td>
|
||||
</tr>
|
||||
</tbody>
|
||||
</table>
|
||||
<h2 id="development-toolchains-and-compilers-2">Development Toolchains and Compilers</h2>
|
||||
<ul>
|
||||
<li>IAR Embedded Workbench for ARM (EWARM) toolchain V8.20.2</li>
|
||||
<li>RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.25</li>
|
||||
<li>System Workbench STM32 (SW4STM32) toolchain V2.7</li>
|
||||
</ul>
|
||||
<h2 id="supported-devices-and-boards-3">Supported Devices and boards</h2>
|
||||
<ul>
|
||||
<li>STM32WB55xx, STM32WB5Mxx, STM32WB50xx, STM32WB35xx and STM32WB30xx devices.</li>
|
||||
</ul>
|
||||
</div>
|
||||
</div>
|
||||
<div class="collapse">
|
||||
<input type="checkbox" id="collapse-section5" aria-hidden="true"> <label for="collapse-section5" aria-hidden="true">V1.4.0 / 12-February-2020</label>
|
||||
<div>
|
||||
<h2 id="main-changes-4">Main Changes</h2>
|
||||
<h3 id="introduction-of-stm32wb35xx-stm32wb30xx-and-stm32wb5mxx-product">Introduction of STM32WB35xx, STM32WB30xx and STM32WB5Mxx product</h3>
|
||||
<p>This release introduce the support of STM32WB5Mxx, STM32WB35xx product and its value line STM32WB30xx.</p>
|
||||
<p>Added features:</p>
|
||||
<ul>
|
||||
<li>Templates/system_stm32wbxx.c contains the initialization code referred as SystemInit.</li>
|
||||
<li>Startup files are provided as example for IAR©, KEIL© and SW4STM32©.</li>
|
||||
<li>Linker files are provided as example for IAR©, KEIL© and SW4STM32©.</li>
|
||||
<li>The product STM32WB5Mxx is supported by enabling inside your project the define “STM32WB5Mxx”.</li>
|
||||
<li>The product STM32WB35xx is supported by enabling inside your project the define “STM32WB35xx”.</li>
|
||||
<li>The product STM32WB30xx is supported by enabling inside your project the define “STM32WB30xx”.</li>
|
||||
</ul>
|
||||
<h2 id="development-toolchains-and-compilers-3">Development Toolchains and Compilers</h2>
|
||||
<ul>
|
||||
<li>IAR Embedded Workbench for ARM (EWARM) toolchain V8.20.2</li>
|
||||
<li>RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.25</li>
|
||||
<li>System Workbench STM32 (SW4STM32) toolchain V2.7</li>
|
||||
</ul>
|
||||
<h2 id="supported-devices-and-boards-4">Supported Devices and boards</h2>
|
||||
<ul>
|
||||
<li>STM32WB55xx, STM32WB5Mxx, STM32WB50xx, STM32WB35xx and STM32WB30xx devices.</li>
|
||||
</ul>
|
||||
</div>
|
||||
</div>
|
||||
<div class="collapse">
|
||||
<input type="checkbox" id="collapse-section4" aria-hidden="true"> <label for="collapse-section4" aria-hidden="true">V1.3.0 / 11-September-2019</label>
|
||||
<div>
|
||||
<h2 id="main-changes-5">Main Changes</h2>
|
||||
<p>Maintenance release for <strong>STM32WBxx</strong> devices (stm32wb55xx and stm32wb50xx devices)</p>
|
||||
<table>
|
||||
<thead>
|
||||
<tr class="header">
|
||||
<th style="text-align: left;">Fixed bugs headline</th>
|
||||
</tr>
|
||||
</thead>
|
||||
<tbody>
|
||||
<tr class="odd">
|
||||
<td style="text-align: left;">Remove IS_TIM_SYNCHRO_INSTANCE macro from CMSIS</td>
|
||||
</tr>
|
||||
<tr class="even">
|
||||
<td style="text-align: left;">Move FLASH_SIZE define from hal flash. h to cmsis device file</td>
|
||||
</tr>
|
||||
<tr class="odd">
|
||||
<td style="text-align: left;">Correct size of .bin files generated by SW4STM32</td>
|
||||
</tr>
|
||||
<tr class="even">
|
||||
<td style="text-align: left;">Remove RCC_PLLSAI_SUPPORT for STM32WB50</td>
|
||||
</tr>
|
||||
</tbody>
|
||||
</table>
|
||||
<h2 id="development-toolchains-and-compilers-4">Development Toolchains and Compilers</h2>
|
||||
<ul>
|
||||
<li>IAR Embedded Workbench for ARM (EWARM) toolchain V8.20.2</li>
|
||||
<li>RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.25</li>
|
||||
<li>System Workbench STM32 (SW4STM32) toolchain V2.7</li>
|
||||
</ul>
|
||||
<h2 id="supported-devices-and-boards-5">Supported Devices and boards</h2>
|
||||
<ul>
|
||||
<li>STM32WB55xx, STM32WB50xx devices</li>
|
||||
</ul>
|
||||
</div>
|
||||
</div>
|
||||
<div class="collapse">
|
||||
<input type="checkbox" id="collapse-section3" aria-hidden="true"> <label for="collapse-section3" aria-hidden="true">V1.2.0 / 26-June-2019</label>
|
||||
<div>
|
||||
<h2 id="main-changes-6">Main Changes</h2>
|
||||
<h3 id="introduction-of-stm32wb50xx-device">Introduction of STM32WB50xx device</h3>
|
||||
<p>First release for STM32WBxx CMSIS introducing <strong>stm32wb50xx</strong> devices.</p>
|
||||
<h2 id="contents">Contents</h2>
|
||||
<p>CMSIS devices files for stm32wb55xx, stm32wb50xx devices.</p>
|
||||
<h2 id="development-toolchains-and-compilers-5">Development Toolchains and Compilers</h2>
|
||||
<ul>
|
||||
<li>IAR Embedded Workbench for ARM (EWARM) toolchain V8.20.2</li>
|
||||
<li>RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.25</li>
|
||||
<li>System Workbench STM32 (SW4STM32) toolchain V2.7</li>
|
||||
</ul>
|
||||
<h2 id="supported-devices-and-boards-6">Supported Devices and boards</h2>
|
||||
<ul>
|
||||
<li>STM32WB55xx and STM32WB50xx devices</li>
|
||||
</ul>
|
||||
</div>
|
||||
</div>
|
||||
<div class="collapse">
|
||||
<input type="checkbox" id="collapse-section2" aria-hidden="true"> <label for="collapse-section2" aria-hidden="true">V1.1.0 / 05-April-2019</label>
|
||||
<div>
|
||||
<h2 id="main-changes-7">Main Changes</h2>
|
||||
<h3 id="maintenance-release-2">Maintenance release</h3>
|
||||
<p>Maintenance release for <strong>STM32WBxx</strong> devices (stm32wb55xx devices)</p>
|
||||
<table>
|
||||
<caption>Fixed bugs list</caption>
|
||||
<thead>
|
||||
<tr class="header">
|
||||
<th>Headline</th>
|
||||
</tr>
|
||||
</thead>
|
||||
<tbody>
|
||||
<tr class="odd">
|
||||
<td>Correct GCC linker file: Set available size of RAM1 to 192K - 4 instead of 191K.</td>
|
||||
</tr>
|
||||
<tr class="even">
|
||||
<td>Set FLASH_ACR_LATENCY_x as uint32_t (UL instead of U).</td>
|
||||
</tr>
|
||||
</tbody>
|
||||
</table>
|
||||
</div>
|
||||
</div>
|
||||
<div class="collapse">
|
||||
<input type="checkbox" id="collapse-section1" aria-hidden="true"> <label for="collapse-section1" aria-hidden="true">V1.0.0 / 06-February-2019</label>
|
||||
<div>
|
||||
<h2 id="main-changes-8">Main Changes</h2>
|
||||
<h3 id="first-release">First release</h3>
|
||||
<p>Add support of STM32WB55xx.</p>
|
||||
</div>
|
||||
</div>
|
||||
</div>
|
||||
</div>
|
||||
<footer class="sticky">
|
||||
<p>For complete documentation on STM32WBxx, visit: [<a href="http://www.st.com/stm32wb">www.st.com/stm32wb</a>]</p>
|
||||
<em>This release note uses up to date web standards and, for this reason, should not be opened with Internet Explorer but preferably with popular browsers such as Google Chrome, Mozilla Firefox, Opera or Microsoft Edge.</em>
|
||||
</footer>
|
||||
</body>
|
||||
</html>
|
||||
|
|
@ -1,21 +0,0 @@
|
|||
; *************************************************************
|
||||
; *** Scatter-Loading Description File generated by uVision ***
|
||||
; *************************************************************
|
||||
|
||||
LR_IROM1 0x08000000 0x0001B800 { ; load region size_region
|
||||
ER_IROM1 0x08000000 0x0001B800 { ; load address = execution address
|
||||
*.o (RESET, +First)
|
||||
*(InRoot$$Sections)
|
||||
.ANY (+RO)
|
||||
}
|
||||
RW_IRAM1 0x20000008 0x2FF8 { ; RW data
|
||||
.ANY (+RW +ZI)
|
||||
}
|
||||
RW_RAM_SHARED 0x20030000 0x2800 { ; RW data
|
||||
*(MAPPING_TABLE)
|
||||
*(MB_MEM1)
|
||||
*(MB_MEM2)
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -1,21 +0,0 @@
|
|||
; *************************************************************
|
||||
; *** Scatter-Loading Description File generated by uVision ***
|
||||
; *************************************************************
|
||||
|
||||
LR_IROM1 0x08000000 0x0001B800 { ; load region size_region
|
||||
ER_IROM1 0x08000000 0x0001B800 { ; load address = execution address
|
||||
*.o (RESET, +First)
|
||||
*(InRoot$$Sections)
|
||||
.ANY (+RO)
|
||||
}
|
||||
RW_IRAM1 0x20000008 0x2FF8 { ; RW data
|
||||
.ANY (+RW +ZI)
|
||||
}
|
||||
RW_RAM_SHARED 0x20030000 0x2800 { ; RW data
|
||||
*(MAPPING_TABLE)
|
||||
*(MB_MEM1)
|
||||
*(MB_MEM2)
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -1,21 +0,0 @@
|
|||
; *************************************************************
|
||||
; *** Scatter-Loading Description File generated by uVision ***
|
||||
; *************************************************************
|
||||
|
||||
LR_IROM1 0x08000000 0x00040000 { ; load region size_region
|
||||
ER_IROM1 0x08000000 0x00040000 { ; load address = execution address
|
||||
*.o (RESET, +First)
|
||||
*(InRoot$$Sections)
|
||||
.ANY (+RO)
|
||||
}
|
||||
RW_IRAM1 0x20000008 0x7FF8 { ; RW data
|
||||
.ANY (+RW +ZI)
|
||||
}
|
||||
RW_RAM_SHARED 0x20030000 0x2800 { ; RW data
|
||||
*(MAPPING_TABLE)
|
||||
*(MB_MEM1)
|
||||
*(MB_MEM2)
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -1,21 +0,0 @@
|
|||
; *************************************************************
|
||||
; *** Scatter-Loading Description File generated by uVision ***
|
||||
; *************************************************************
|
||||
|
||||
LR_IROM1 0x08000000 0x00040000 { ; load region size_region
|
||||
ER_IROM1 0x08000000 0x00040000 { ; load address = execution address
|
||||
*.o (RESET, +First)
|
||||
*(InRoot$$Sections)
|
||||
.ANY (+RO)
|
||||
}
|
||||
RW_IRAM1 0x20000008 0x7FF8 { ; RW data
|
||||
.ANY (+RW +ZI)
|
||||
}
|
||||
RW_RAM_SHARED 0x20030000 0x2800 { ; RW data
|
||||
*(MAPPING_TABLE)
|
||||
*(MB_MEM1)
|
||||
*(MB_MEM2)
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -1,21 +0,0 @@
|
|||
; *************************************************************
|
||||
; *** Scatter-Loading Description File generated by uVision ***
|
||||
; *************************************************************
|
||||
|
||||
LR_IROM1 0x08000000 0x00080000 { ; load region size_region
|
||||
ER_IROM1 0x08000000 0x00080000 { ; load address = execution address
|
||||
*.o (RESET, +First)
|
||||
*(InRoot$$Sections)
|
||||
.ANY (+RO)
|
||||
}
|
||||
RW_IRAM1 0x20000008 0xFFF8 { ; RW data
|
||||
.ANY (+RW +ZI)
|
||||
}
|
||||
RW_RAM_SHARED 0x20030000 0x2800 { ; RW data
|
||||
*(MAPPING_TABLE)
|
||||
*(MB_MEM1)
|
||||
*(MB_MEM2)
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -1,21 +0,0 @@
|
|||
; *************************************************************
|
||||
; *** Scatter-Loading Description File generated by uVision ***
|
||||
; *************************************************************
|
||||
|
||||
LR_IROM1 0x08000000 0x00080000 { ; load region size_region
|
||||
ER_IROM1 0x08000000 0x00080000 { ; load address = execution address
|
||||
*.o (RESET, +First)
|
||||
*(InRoot$$Sections)
|
||||
.ANY (+RO)
|
||||
}
|
||||
RW_IRAM1 0x20000008 0x2FFF8 { ; RW data
|
||||
.ANY (+RW +ZI)
|
||||
}
|
||||
RW_RAM_SHARED 0x20030000 0x2800 { ; RW data
|
||||
*(MAPPING_TABLE)
|
||||
*(MB_MEM1)
|
||||
*(MB_MEM2)
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -1,21 +0,0 @@
|
|||
; *************************************************************
|
||||
; *** Scatter-Loading Description File generated by uVision ***
|
||||
; *************************************************************
|
||||
|
||||
LR_IROM1 0x08000000 0x00080000 { ; load region size_region
|
||||
ER_IROM1 0x08000000 0x00080000 { ; load address = execution address
|
||||
*.o (RESET, +First)
|
||||
*(InRoot$$Sections)
|
||||
.ANY (+RO)
|
||||
}
|
||||
RW_IRAM1 0x20000008 0x2FFF8 { ; RW data
|
||||
.ANY (+RW +ZI)
|
||||
}
|
||||
RW_RAM_SHARED 0x20030000 0x2800 { ; RW data
|
||||
*(MAPPING_TABLE)
|
||||
*(MB_MEM1)
|
||||
*(MB_MEM2)
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -1,332 +0,0 @@
|
|||
;******************************************************************************
|
||||
;* File Name : startup_stm32wb10xx_cm4.s
|
||||
;* Author : MCD Application Team
|
||||
;* Description : STM32WB10xx devices vector table for MDK-ARM toolchain.
|
||||
;* This module performs:
|
||||
;* - Set the initial SP
|
||||
;* - Set the initial PC == Reset_Handler
|
||||
;* - Set the vector table entries with the exceptions ISR address
|
||||
;* - Branches to __main in the C library (which eventually
|
||||
;* calls main()).
|
||||
;* After Reset the CortexM4 processor is in Thread mode,
|
||||
;* priority is Privileged, and the Stack is set to Main.
|
||||
;* <<< Use Configuration Wizard in Context Menu >>>
|
||||
;******************************************************************************
|
||||
;* @attention
|
||||
;*
|
||||
;* Copyright (c) 2019-2021 STMicroelectronics.
|
||||
;* All rights reserved.
|
||||
;*
|
||||
;* This software is licensed under terms that can be found in the LICENSE file
|
||||
;* in the root directory of this software component.
|
||||
;* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
;*
|
||||
;******************************************************************************
|
||||
|
||||
; Amount of memory (in bytes) allocated for Stack
|
||||
; Tailor this value to your application needs
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00000400
|
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
||||
Stack_Mem SPACE Stack_Size
|
||||
__initial_sp
|
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000000
|
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||
__heap_base
|
||||
Heap_Mem SPACE Heap_Size
|
||||
__heap_limit
|
||||
|
||||
PRESERVE8
|
||||
THUMB
|
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
AREA RESET, DATA, READONLY
|
||||
EXPORT __Vectors
|
||||
EXPORT __Vectors_End
|
||||
EXPORT __Vectors_Size
|
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WWDG_IRQHandler ; Window WatchDog
|
||||
DCD PVD_PVM_IRQHandler ; PVD and PVM detector
|
||||
DCD TAMP_STAMP_LSECSS_IRQHandler ; RTC Tamper and TimeStamp Interrupts and LSECSS Interrupts
|
||||
DCD RTC_WKUP_IRQHandler ; RTC Wakeup Interrupt
|
||||
DCD FLASH_IRQHandler ; FLASH global Interrupt
|
||||
DCD RCC_IRQHandler ; RCC Interrupt
|
||||
DCD EXTI0_IRQHandler ; EXTI Line 0 Interrupt
|
||||
DCD EXTI1_IRQHandler ; EXTI Line 1 Interrupt
|
||||
DCD EXTI2_IRQHandler ; EXTI Line 2 Interrupt
|
||||
DCD EXTI3_IRQHandler ; EXTI Line 3 Interrup
|
||||
DCD EXTI4_IRQHandler ; EXTI Line 4 Interrupt
|
||||
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 Interrupt
|
||||
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 Interrupt
|
||||
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 Interrupt
|
||||
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 Interrupt
|
||||
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 Interrupt
|
||||
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 Interrupt
|
||||
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 Interrupt
|
||||
DCD ADC1_IRQHandler ; ADC1 Interrupt
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD C2SEV_PWR_C2H_IRQHandler ; CPU M0+ SEV Interrupt
|
||||
DCD 0 ; Reserved
|
||||
DCD EXTI9_5_IRQHandler ; EXTI Lines [9:5] Interrupt
|
||||
DCD TIM1_BRK_IRQHandler ; TIM1 Break Interrupt
|
||||
DCD TIM1_UP_IRQHandler ; TIM1 Update Interrupt
|
||||
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Communication Interrupts
|
||||
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare Interrupt
|
||||
DCD TIM2_IRQHandler ; TIM2 Global Interrupt
|
||||
DCD PKA_IRQHandler ; PKA Interrupt
|
||||
DCD I2C1_EV_IRQHandler ; I2C1 Event Interrupt
|
||||
DCD I2C1_ER_IRQHandler ; I2C1 Error Interrupt
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SPI1_IRQHandler ; SPI1 Interrupt
|
||||
DCD 0 ; Reserved
|
||||
DCD USART1_IRQHandler ; USART1 Interrupt
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD TSC_IRQHandler ; TSC Interrupt
|
||||
DCD EXTI15_10_IRQHandler ; EXTI Lines1[15:10 ]Interrupts
|
||||
DCD RTC_Alarm_IRQHandler ; RTC Alarms (A and B) Interrupt
|
||||
DCD 0 ; Reserved
|
||||
DCD PWR_SOTF_BLEACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
|
||||
DCD IPCC_C1_RX_IRQHandler ; IPCC CPU1 RX occupied interrupt
|
||||
DCD IPCC_C1_TX_IRQHandler ; IPCC CPU1 RX free interrupt
|
||||
DCD HSEM_IRQHandler ; HSEM0 Interrupt
|
||||
DCD LPTIM1_IRQHandler ; LPTIM1 Interrupt
|
||||
DCD LPTIM2_IRQHandler ; LPTIM2 Interrupt
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD AES2_IRQHandler ; AES2 Interrupt
|
||||
DCD RNG_IRQHandler ; RNG1 Interrupt
|
||||
DCD FPU_IRQHandler ; FPU Interrupt
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD DMAMUX1_OVR_IRQHandler ; DMAMUX overrun Interrupt
|
||||
|
||||
__Vectors_End
|
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
AREA |.text|, CODE, READONLY
|
||||
|
||||
; Reset handler
|
||||
Reset_Handler PROC
|
||||
EXPORT Reset_Handler [WEAK]
|
||||
IMPORT SystemInit
|
||||
IMPORT __main
|
||||
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__main
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC
|
||||
EXPORT NMI_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
HardFault_Handler\
|
||||
PROC
|
||||
EXPORT HardFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
MemManage_Handler\
|
||||
PROC
|
||||
EXPORT MemManage_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
BusFault_Handler\
|
||||
PROC
|
||||
EXPORT BusFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
UsageFault_Handler\
|
||||
PROC
|
||||
EXPORT UsageFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SVC_Handler PROC
|
||||
EXPORT SVC_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
DebugMon_Handler\
|
||||
PROC
|
||||
EXPORT DebugMon_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
PendSV_Handler PROC
|
||||
EXPORT PendSV_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SysTick_Handler PROC
|
||||
EXPORT SysTick_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
Default_Handler PROC
|
||||
|
||||
EXPORT WWDG_IRQHandler [WEAK]
|
||||
EXPORT PVD_PVM_IRQHandler [WEAK]
|
||||
EXPORT TAMP_STAMP_LSECSS_IRQHandler [WEAK]
|
||||
EXPORT RTC_WKUP_IRQHandler [WEAK]
|
||||
EXPORT FLASH_IRQHandler [WEAK]
|
||||
EXPORT RCC_IRQHandler [WEAK]
|
||||
EXPORT EXTI0_IRQHandler [WEAK]
|
||||
EXPORT EXTI1_IRQHandler [WEAK]
|
||||
EXPORT EXTI2_IRQHandler [WEAK]
|
||||
EXPORT EXTI3_IRQHandler [WEAK]
|
||||
EXPORT EXTI4_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel1_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel2_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel3_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel4_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel5_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel6_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel7_IRQHandler [WEAK]
|
||||
EXPORT ADC1_IRQHandler [WEAK]
|
||||
EXPORT C2SEV_PWR_C2H_IRQHandler [WEAK]
|
||||
EXPORT EXTI9_5_IRQHandler [WEAK]
|
||||
EXPORT TIM1_BRK_IRQHandler [WEAK]
|
||||
EXPORT TIM1_UP_IRQHandler [WEAK]
|
||||
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
|
||||
EXPORT TIM1_CC_IRQHandler [WEAK]
|
||||
EXPORT TIM2_IRQHandler [WEAK]
|
||||
EXPORT PKA_IRQHandler [WEAK]
|
||||
EXPORT I2C1_EV_IRQHandler [WEAK]
|
||||
EXPORT I2C1_ER_IRQHandler [WEAK]
|
||||
EXPORT SPI1_IRQHandler [WEAK]
|
||||
EXPORT USART1_IRQHandler [WEAK]
|
||||
EXPORT TSC_IRQHandler [WEAK]
|
||||
EXPORT EXTI15_10_IRQHandler [WEAK]
|
||||
EXPORT RTC_Alarm_IRQHandler [WEAK]
|
||||
EXPORT PWR_SOTF_BLEACT_RFPHASE_IRQHandler [WEAK]
|
||||
EXPORT IPCC_C1_RX_IRQHandler [WEAK]
|
||||
EXPORT IPCC_C1_TX_IRQHandler [WEAK]
|
||||
EXPORT HSEM_IRQHandler [WEAK]
|
||||
EXPORT LPTIM1_IRQHandler [WEAK]
|
||||
EXPORT LPTIM2_IRQHandler [WEAK]
|
||||
EXPORT AES1_IRQHandler [WEAK]
|
||||
EXPORT AES2_IRQHandler [WEAK]
|
||||
EXPORT RNG_IRQHandler [WEAK]
|
||||
EXPORT FPU_IRQHandler [WEAK]
|
||||
EXPORT DMAMUX1_OVR_IRQHandler [WEAK]
|
||||
|
||||
WWDG_IRQHandler
|
||||
PVD_PVM_IRQHandler
|
||||
TAMP_STAMP_LSECSS_IRQHandler
|
||||
RTC_WKUP_IRQHandler
|
||||
FLASH_IRQHandler
|
||||
RCC_IRQHandler
|
||||
EXTI0_IRQHandler
|
||||
EXTI1_IRQHandler
|
||||
EXTI2_IRQHandler
|
||||
EXTI3_IRQHandler
|
||||
EXTI4_IRQHandler
|
||||
DMA1_Channel1_IRQHandler
|
||||
DMA1_Channel2_IRQHandler
|
||||
DMA1_Channel3_IRQHandler
|
||||
DMA1_Channel4_IRQHandler
|
||||
DMA1_Channel5_IRQHandler
|
||||
DMA1_Channel6_IRQHandler
|
||||
DMA1_Channel7_IRQHandler
|
||||
ADC1_IRQHandler
|
||||
C2SEV_PWR_C2H_IRQHandler
|
||||
EXTI9_5_IRQHandler
|
||||
TIM1_BRK_IRQHandler
|
||||
TIM1_UP_IRQHandler
|
||||
TIM1_TRG_COM_IRQHandler
|
||||
TIM1_CC_IRQHandler
|
||||
TIM2_IRQHandler
|
||||
PKA_IRQHandler
|
||||
I2C1_EV_IRQHandler
|
||||
I2C1_ER_IRQHandler
|
||||
SPI1_IRQHandler
|
||||
USART1_IRQHandler
|
||||
TSC_IRQHandler
|
||||
EXTI15_10_IRQHandler
|
||||
RTC_Alarm_IRQHandler
|
||||
PWR_SOTF_BLEACT_RFPHASE_IRQHandler
|
||||
IPCC_C1_RX_IRQHandler
|
||||
IPCC_C1_TX_IRQHandler
|
||||
HSEM_IRQHandler
|
||||
LPTIM1_IRQHandler
|
||||
LPTIM2_IRQHandler
|
||||
AES1_IRQHandler
|
||||
AES2_IRQHandler
|
||||
RNG_IRQHandler
|
||||
FPU_IRQHandler
|
||||
DMAMUX1_OVR_IRQHandler
|
||||
|
||||
B .
|
||||
|
||||
ENDP
|
||||
|
||||
ALIGN
|
||||
|
||||
;*******************************************************************************
|
||||
; User Stack and Heap initialization
|
||||
;*******************************************************************************
|
||||
IF :DEF:__MICROLIB
|
||||
|
||||
EXPORT __initial_sp
|
||||
EXPORT __heap_base
|
||||
EXPORT __heap_limit
|
||||
|
||||
ELSE
|
||||
|
||||
IMPORT __use_two_region_memory
|
||||
EXPORT __user_initial_stackheap
|
||||
|
||||
__user_initial_stackheap
|
||||
|
||||
LDR R0, = Heap_Mem
|
||||
LDR R1, =(Stack_Mem + Stack_Size)
|
||||
LDR R2, = (Heap_Mem + Heap_Size)
|
||||
LDR R3, = Stack_Mem
|
||||
BX LR
|
||||
|
||||
ALIGN
|
||||
|
||||
ENDIF
|
||||
|
||||
END
|
||||
|
||||
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
||||
|
|
@ -1,336 +0,0 @@
|
|||
;******************************************************************************
|
||||
;* File Name : startup_stm32wb15xx_cm4.s
|
||||
;* Author : MCD Application Team
|
||||
;* Description : STM32WB15xx devices vector table for MDK-ARM toolchain.
|
||||
;* This module performs:
|
||||
;* - Set the initial SP
|
||||
;* - Set the initial PC == Reset_Handler
|
||||
;* - Set the vector table entries with the exceptions ISR address
|
||||
;* - Branches to __main in the C library (which eventually
|
||||
;* calls main()).
|
||||
;* After Reset the CortexM4 processor is in Thread mode,
|
||||
;* priority is Privileged, and the Stack is set to Main.
|
||||
;* <<< Use Configuration Wizard in Context Menu >>>
|
||||
;******************************************************************************
|
||||
;* @attention
|
||||
;*
|
||||
;* Copyright (c) 2019-2021 STMicroelectronics.
|
||||
;* All rights reserved.
|
||||
;*
|
||||
;* This software is licensed under terms that can be found in the LICENSE file
|
||||
;* in the root directory of this software component.
|
||||
;* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
;*
|
||||
;******************************************************************************
|
||||
|
||||
; Amount of memory (in bytes) allocated for Stack
|
||||
; Tailor this value to your application needs
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00000400
|
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
||||
Stack_Mem SPACE Stack_Size
|
||||
__initial_sp
|
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000000
|
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||
__heap_base
|
||||
Heap_Mem SPACE Heap_Size
|
||||
__heap_limit
|
||||
|
||||
PRESERVE8
|
||||
THUMB
|
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
AREA RESET, DATA, READONLY
|
||||
EXPORT __Vectors
|
||||
EXPORT __Vectors_End
|
||||
EXPORT __Vectors_Size
|
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WWDG_IRQHandler ; Window WatchDog
|
||||
DCD PVD_PVM_IRQHandler ; PVD and PVM detector
|
||||
DCD TAMP_STAMP_LSECSS_IRQHandler ; RTC Tamper and TimeStamp Interrupts and LSECSS Interrupts
|
||||
DCD RTC_WKUP_IRQHandler ; RTC Wakeup Interrupt
|
||||
DCD FLASH_IRQHandler ; FLASH global Interrupt
|
||||
DCD RCC_IRQHandler ; RCC Interrupt
|
||||
DCD EXTI0_IRQHandler ; EXTI Line 0 Interrupt
|
||||
DCD EXTI1_IRQHandler ; EXTI Line 1 Interrupt
|
||||
DCD EXTI2_IRQHandler ; EXTI Line 2 Interrupt
|
||||
DCD EXTI3_IRQHandler ; EXTI Line 3 Interrup
|
||||
DCD EXTI4_IRQHandler ; EXTI Line 4 Interrupt
|
||||
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 Interrupt
|
||||
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 Interrupt
|
||||
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 Interrupt
|
||||
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 Interrupt
|
||||
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 Interrupt
|
||||
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 Interrupt
|
||||
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 Interrupt
|
||||
DCD ADC1_IRQHandler ; ADC1 Interrupt
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD C2SEV_PWR_C2H_IRQHandler ; CPU M0+ SEV Interrupt
|
||||
DCD COMP_IRQHandler ; COMP1 Interrupts
|
||||
DCD EXTI9_5_IRQHandler ; EXTI Lines [9:5] Interrupt
|
||||
DCD TIM1_BRK_IRQHandler ; TIM1 Break Interrupt
|
||||
DCD TIM1_UP_IRQHandler ; TIM1 Update Interrupt
|
||||
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Communication Interrupts
|
||||
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare Interrupt
|
||||
DCD TIM2_IRQHandler ; TIM2 Global Interrupt
|
||||
DCD PKA_IRQHandler ; PKA Interrupt
|
||||
DCD I2C1_EV_IRQHandler ; I2C1 Event Interrupt
|
||||
DCD I2C1_ER_IRQHandler ; I2C1 Error Interrupt
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SPI1_IRQHandler ; SPI1 Interrupt
|
||||
DCD 0 ; Reserved
|
||||
DCD USART1_IRQHandler ; USART1 Interrupt
|
||||
DCD LPUART1_IRQHandler ; LPUART1 Interrupt
|
||||
DCD 0 ; Reserved
|
||||
DCD TSC_IRQHandler ; TSC Interrupt
|
||||
DCD EXTI15_10_IRQHandler ; EXTI Lines1[15:10 ]Interrupts
|
||||
DCD RTC_Alarm_IRQHandler ; RTC Alarms (A and B) Interrupt
|
||||
DCD 0 ; Reserved
|
||||
DCD PWR_SOTF_BLEACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
|
||||
DCD IPCC_C1_RX_IRQHandler ; IPCC CPU1 RX occupied interrupt
|
||||
DCD IPCC_C1_TX_IRQHandler ; IPCC CPU1 RX free interrupt
|
||||
DCD HSEM_IRQHandler ; HSEM0 Interrupt
|
||||
DCD LPTIM1_IRQHandler ; LPTIM1 Interrupt
|
||||
DCD LPTIM2_IRQHandler ; LPTIM2 Interrupt
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD AES2_IRQHandler ; AES2 Interrupt
|
||||
DCD RNG_IRQHandler ; RNG1 Interrupt
|
||||
DCD FPU_IRQHandler ; FPU Interrupt
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD DMAMUX1_OVR_IRQHandler ; DMAMUX overrun Interrupt
|
||||
|
||||
__Vectors_End
|
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
AREA |.text|, CODE, READONLY
|
||||
|
||||
; Reset handler
|
||||
Reset_Handler PROC
|
||||
EXPORT Reset_Handler [WEAK]
|
||||
IMPORT SystemInit
|
||||
IMPORT __main
|
||||
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__main
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC
|
||||
EXPORT NMI_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
HardFault_Handler\
|
||||
PROC
|
||||
EXPORT HardFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
MemManage_Handler\
|
||||
PROC
|
||||
EXPORT MemManage_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
BusFault_Handler\
|
||||
PROC
|
||||
EXPORT BusFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
UsageFault_Handler\
|
||||
PROC
|
||||
EXPORT UsageFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SVC_Handler PROC
|
||||
EXPORT SVC_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
DebugMon_Handler\
|
||||
PROC
|
||||
EXPORT DebugMon_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
PendSV_Handler PROC
|
||||
EXPORT PendSV_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SysTick_Handler PROC
|
||||
EXPORT SysTick_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
Default_Handler PROC
|
||||
|
||||
EXPORT WWDG_IRQHandler [WEAK]
|
||||
EXPORT PVD_PVM_IRQHandler [WEAK]
|
||||
EXPORT TAMP_STAMP_LSECSS_IRQHandler [WEAK]
|
||||
EXPORT RTC_WKUP_IRQHandler [WEAK]
|
||||
EXPORT FLASH_IRQHandler [WEAK]
|
||||
EXPORT RCC_IRQHandler [WEAK]
|
||||
EXPORT EXTI0_IRQHandler [WEAK]
|
||||
EXPORT EXTI1_IRQHandler [WEAK]
|
||||
EXPORT EXTI2_IRQHandler [WEAK]
|
||||
EXPORT EXTI3_IRQHandler [WEAK]
|
||||
EXPORT EXTI4_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel1_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel2_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel3_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel4_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel5_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel6_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel7_IRQHandler [WEAK]
|
||||
EXPORT ADC1_IRQHandler [WEAK]
|
||||
EXPORT C2SEV_PWR_C2H_IRQHandler [WEAK]
|
||||
EXPORT COMP_IRQHandler [WEAK]
|
||||
EXPORT EXTI9_5_IRQHandler [WEAK]
|
||||
EXPORT TIM1_BRK_IRQHandler [WEAK]
|
||||
EXPORT TIM1_UP_IRQHandler [WEAK]
|
||||
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
|
||||
EXPORT TIM1_CC_IRQHandler [WEAK]
|
||||
EXPORT TIM2_IRQHandler [WEAK]
|
||||
EXPORT PKA_IRQHandler [WEAK]
|
||||
EXPORT I2C1_EV_IRQHandler [WEAK]
|
||||
EXPORT I2C1_ER_IRQHandler [WEAK]
|
||||
EXPORT SPI1_IRQHandler [WEAK]
|
||||
EXPORT USART1_IRQHandler [WEAK]
|
||||
EXPORT LPUART1_IRQHandler [WEAK]
|
||||
EXPORT TSC_IRQHandler [WEAK]
|
||||
EXPORT EXTI15_10_IRQHandler [WEAK]
|
||||
EXPORT RTC_Alarm_IRQHandler [WEAK]
|
||||
EXPORT PWR_SOTF_BLEACT_RFPHASE_IRQHandler [WEAK]
|
||||
EXPORT IPCC_C1_RX_IRQHandler [WEAK]
|
||||
EXPORT IPCC_C1_TX_IRQHandler [WEAK]
|
||||
EXPORT HSEM_IRQHandler [WEAK]
|
||||
EXPORT LPTIM1_IRQHandler [WEAK]
|
||||
EXPORT LPTIM2_IRQHandler [WEAK]
|
||||
EXPORT AES1_IRQHandler [WEAK]
|
||||
EXPORT AES2_IRQHandler [WEAK]
|
||||
EXPORT RNG_IRQHandler [WEAK]
|
||||
EXPORT FPU_IRQHandler [WEAK]
|
||||
EXPORT DMAMUX1_OVR_IRQHandler [WEAK]
|
||||
|
||||
WWDG_IRQHandler
|
||||
PVD_PVM_IRQHandler
|
||||
TAMP_STAMP_LSECSS_IRQHandler
|
||||
RTC_WKUP_IRQHandler
|
||||
FLASH_IRQHandler
|
||||
RCC_IRQHandler
|
||||
EXTI0_IRQHandler
|
||||
EXTI1_IRQHandler
|
||||
EXTI2_IRQHandler
|
||||
EXTI3_IRQHandler
|
||||
EXTI4_IRQHandler
|
||||
DMA1_Channel1_IRQHandler
|
||||
DMA1_Channel2_IRQHandler
|
||||
DMA1_Channel3_IRQHandler
|
||||
DMA1_Channel4_IRQHandler
|
||||
DMA1_Channel5_IRQHandler
|
||||
DMA1_Channel6_IRQHandler
|
||||
DMA1_Channel7_IRQHandler
|
||||
ADC1_IRQHandler
|
||||
C2SEV_PWR_C2H_IRQHandler
|
||||
COMP_IRQHandler
|
||||
EXTI9_5_IRQHandler
|
||||
TIM1_BRK_IRQHandler
|
||||
TIM1_UP_IRQHandler
|
||||
TIM1_TRG_COM_IRQHandler
|
||||
TIM1_CC_IRQHandler
|
||||
TIM2_IRQHandler
|
||||
PKA_IRQHandler
|
||||
I2C1_EV_IRQHandler
|
||||
I2C1_ER_IRQHandler
|
||||
SPI1_IRQHandler
|
||||
USART1_IRQHandler
|
||||
LPUART1_IRQHandler
|
||||
TSC_IRQHandler
|
||||
EXTI15_10_IRQHandler
|
||||
RTC_Alarm_IRQHandler
|
||||
PWR_SOTF_BLEACT_RFPHASE_IRQHandler
|
||||
IPCC_C1_RX_IRQHandler
|
||||
IPCC_C1_TX_IRQHandler
|
||||
HSEM_IRQHandler
|
||||
LPTIM1_IRQHandler
|
||||
LPTIM2_IRQHandler
|
||||
AES1_IRQHandler
|
||||
AES2_IRQHandler
|
||||
RNG_IRQHandler
|
||||
FPU_IRQHandler
|
||||
DMAMUX1_OVR_IRQHandler
|
||||
|
||||
B .
|
||||
|
||||
ENDP
|
||||
|
||||
ALIGN
|
||||
|
||||
;*******************************************************************************
|
||||
; User Stack and Heap initialization
|
||||
;*******************************************************************************
|
||||
IF :DEF:__MICROLIB
|
||||
|
||||
EXPORT __initial_sp
|
||||
EXPORT __heap_base
|
||||
EXPORT __heap_limit
|
||||
|
||||
ELSE
|
||||
|
||||
IMPORT __use_two_region_memory
|
||||
EXPORT __user_initial_stackheap
|
||||
|
||||
__user_initial_stackheap
|
||||
|
||||
LDR R0, = Heap_Mem
|
||||
LDR R1, =(Stack_Mem + Stack_Size)
|
||||
LDR R2, = (Heap_Mem + Heap_Size)
|
||||
LDR R3, = Stack_Mem
|
||||
BX LR
|
||||
|
||||
ALIGN
|
||||
|
||||
ENDIF
|
||||
|
||||
END
|
||||
|
||||
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
||||
|
|
@ -1,328 +0,0 @@
|
|||
;******************************************************************************
|
||||
;* File Name : startup_stm32wb30xx_cm4.s
|
||||
;* Author : MCD Application Team
|
||||
;* Description : STM32WB30xx devices vector table for MDK-ARM toolchain.
|
||||
;* This module performs:
|
||||
;* - Set the initial SP
|
||||
;* - Set the initial PC == Reset_Handler
|
||||
;* - Set the vector table entries with the exceptions ISR address
|
||||
;* - Branches to __main in the C library (which eventually
|
||||
;* calls main()).
|
||||
;* After Reset the CortexM4 processor is in Thread mode,
|
||||
;* priority is Privileged, and the Stack is set to Main.
|
||||
;* <<< Use Configuration Wizard in Context Menu >>>
|
||||
;******************************************************************************
|
||||
;* @attention
|
||||
;*
|
||||
;* Copyright (c) 2019-2021 STMicroelectronics.
|
||||
;* All rights reserved.
|
||||
;*
|
||||
;* This software is licensed under terms that can be found in the LICENSE file
|
||||
;* in the root directory of this software component.
|
||||
;* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
;*
|
||||
;******************************************************************************
|
||||
|
||||
; Amount of memory (in bytes) allocated for Stack
|
||||
; Tailor this value to your application needs
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00000400
|
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
||||
Stack_Mem SPACE Stack_Size
|
||||
__initial_sp
|
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000000
|
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||
__heap_base
|
||||
Heap_Mem SPACE Heap_Size
|
||||
__heap_limit
|
||||
|
||||
PRESERVE8
|
||||
THUMB
|
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
AREA RESET, DATA, READONLY
|
||||
EXPORT __Vectors
|
||||
EXPORT __Vectors_End
|
||||
EXPORT __Vectors_Size
|
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WWDG_IRQHandler ; Window WatchDog
|
||||
DCD PVD_PVM_IRQHandler ; PVD and PVM detector
|
||||
DCD TAMP_STAMP_LSECSS_IRQHandler ; RTC Tamper and TimeStamp Interrupts and LSECSS Interrupts
|
||||
DCD RTC_WKUP_IRQHandler ; RTC Wakeup Interrupt
|
||||
DCD FLASH_IRQHandler ; FLASH global Interrupt
|
||||
DCD RCC_IRQHandler ; RCC Interrupt
|
||||
DCD EXTI0_IRQHandler ; EXTI Line 0 Interrupt
|
||||
DCD EXTI1_IRQHandler ; EXTI Line 1 Interrupt
|
||||
DCD EXTI2_IRQHandler ; EXTI Line 2 Interrupt
|
||||
DCD EXTI3_IRQHandler ; EXTI Line 3 Interrup
|
||||
DCD EXTI4_IRQHandler ; EXTI Line 4 Interrupt
|
||||
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 Interrupt
|
||||
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 Interrupt
|
||||
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 Interrupt
|
||||
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 Interrupt
|
||||
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 Interrupt
|
||||
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 Interrupt
|
||||
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 Interrupt
|
||||
DCD ADC1_IRQHandler ; ADC1 Interrupt
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD C2SEV_PWR_C2H_IRQHandler ; CPU M0+ SEV Interrupt
|
||||
DCD 0 ; Reserved
|
||||
DCD EXTI9_5_IRQHandler ; EXTI Lines [9:5] Interrupt
|
||||
DCD TIM1_BRK_IRQHandler ; TIM1 Break Interrupt
|
||||
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16 global Interrupts
|
||||
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Communication and TIM17 global Interrupts
|
||||
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare Interrupt
|
||||
DCD TIM2_IRQHandler ; TIM2 Global Interrupt
|
||||
DCD PKA_IRQHandler ; PKA Interrupt
|
||||
DCD I2C1_EV_IRQHandler ; I2C1 Event Interrupt
|
||||
DCD I2C1_ER_IRQHandler ; I2C1 Error Interrupt
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SPI1_IRQHandler ; SPI1 Interrupt
|
||||
DCD 0 ; Reserved
|
||||
DCD USART1_IRQHandler ; USART1 Interrupt
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD EXTI15_10_IRQHandler ; EXTI Lines1[15:10 ]Interrupts
|
||||
DCD RTC_Alarm_IRQHandler ; RTC Alarms (A and B) Interrupt
|
||||
DCD 0 ; Reserved
|
||||
DCD PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
|
||||
DCD IPCC_C1_RX_IRQHandler ; IPCC CPU1 RX occupied interrupt
|
||||
DCD IPCC_C1_TX_IRQHandler ; IPCC CPU1 RX free interrupt
|
||||
DCD HSEM_IRQHandler ; HSEM0 Interrupt
|
||||
DCD LPTIM1_IRQHandler ; LPTIM1 Interrupt
|
||||
DCD LPTIM2_IRQHandler ; LPTIM2 Interrupt
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD AES2_IRQHandler ; AES2 Interrupt
|
||||
DCD RNG_IRQHandler ; RNG1 Interrupt
|
||||
DCD FPU_IRQHandler ; FPU Interrupt
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD DMAMUX1_OVR_IRQHandler ; DMAMUX overrun Interrupt
|
||||
|
||||
__Vectors_End
|
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
AREA |.text|, CODE, READONLY
|
||||
|
||||
; Reset handler
|
||||
Reset_Handler PROC
|
||||
EXPORT Reset_Handler [WEAK]
|
||||
IMPORT SystemInit
|
||||
IMPORT __main
|
||||
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__main
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC
|
||||
EXPORT NMI_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
HardFault_Handler\
|
||||
PROC
|
||||
EXPORT HardFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
MemManage_Handler\
|
||||
PROC
|
||||
EXPORT MemManage_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
BusFault_Handler\
|
||||
PROC
|
||||
EXPORT BusFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
UsageFault_Handler\
|
||||
PROC
|
||||
EXPORT UsageFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SVC_Handler PROC
|
||||
EXPORT SVC_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
DebugMon_Handler\
|
||||
PROC
|
||||
EXPORT DebugMon_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
PendSV_Handler PROC
|
||||
EXPORT PendSV_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SysTick_Handler PROC
|
||||
EXPORT SysTick_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
Default_Handler PROC
|
||||
|
||||
EXPORT WWDG_IRQHandler [WEAK]
|
||||
EXPORT PVD_PVM_IRQHandler [WEAK]
|
||||
EXPORT TAMP_STAMP_LSECSS_IRQHandler [WEAK]
|
||||
EXPORT RTC_WKUP_IRQHandler [WEAK]
|
||||
EXPORT FLASH_IRQHandler [WEAK]
|
||||
EXPORT RCC_IRQHandler [WEAK]
|
||||
EXPORT EXTI0_IRQHandler [WEAK]
|
||||
EXPORT EXTI1_IRQHandler [WEAK]
|
||||
EXPORT EXTI2_IRQHandler [WEAK]
|
||||
EXPORT EXTI3_IRQHandler [WEAK]
|
||||
EXPORT EXTI4_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel1_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel2_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel3_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel4_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel5_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel6_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel7_IRQHandler [WEAK]
|
||||
EXPORT ADC1_IRQHandler [WEAK]
|
||||
EXPORT C2SEV_PWR_C2H_IRQHandler [WEAK]
|
||||
EXPORT EXTI9_5_IRQHandler [WEAK]
|
||||
EXPORT TIM1_BRK_IRQHandler [WEAK]
|
||||
EXPORT TIM1_UP_TIM16_IRQHandler [WEAK]
|
||||
EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK]
|
||||
EXPORT TIM1_CC_IRQHandler [WEAK]
|
||||
EXPORT TIM2_IRQHandler [WEAK]
|
||||
EXPORT PKA_IRQHandler [WEAK]
|
||||
EXPORT I2C1_EV_IRQHandler [WEAK]
|
||||
EXPORT I2C1_ER_IRQHandler [WEAK]
|
||||
EXPORT SPI1_IRQHandler [WEAK]
|
||||
EXPORT USART1_IRQHandler [WEAK]
|
||||
EXPORT EXTI15_10_IRQHandler [WEAK]
|
||||
EXPORT RTC_Alarm_IRQHandler [WEAK]
|
||||
EXPORT PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler [WEAK]
|
||||
EXPORT IPCC_C1_RX_IRQHandler [WEAK]
|
||||
EXPORT IPCC_C1_TX_IRQHandler [WEAK]
|
||||
EXPORT HSEM_IRQHandler [WEAK]
|
||||
EXPORT LPTIM1_IRQHandler [WEAK]
|
||||
EXPORT LPTIM2_IRQHandler [WEAK]
|
||||
EXPORT AES2_IRQHandler [WEAK]
|
||||
EXPORT RNG_IRQHandler [WEAK]
|
||||
EXPORT FPU_IRQHandler [WEAK]
|
||||
EXPORT DMAMUX1_OVR_IRQHandler [WEAK]
|
||||
|
||||
WWDG_IRQHandler
|
||||
PVD_PVM_IRQHandler
|
||||
TAMP_STAMP_LSECSS_IRQHandler
|
||||
RTC_WKUP_IRQHandler
|
||||
FLASH_IRQHandler
|
||||
RCC_IRQHandler
|
||||
EXTI0_IRQHandler
|
||||
EXTI1_IRQHandler
|
||||
EXTI2_IRQHandler
|
||||
EXTI3_IRQHandler
|
||||
EXTI4_IRQHandler
|
||||
DMA1_Channel1_IRQHandler
|
||||
DMA1_Channel2_IRQHandler
|
||||
DMA1_Channel3_IRQHandler
|
||||
DMA1_Channel4_IRQHandler
|
||||
DMA1_Channel5_IRQHandler
|
||||
DMA1_Channel6_IRQHandler
|
||||
DMA1_Channel7_IRQHandler
|
||||
ADC1_IRQHandler
|
||||
C2SEV_PWR_C2H_IRQHandler
|
||||
EXTI9_5_IRQHandler
|
||||
TIM1_BRK_IRQHandler
|
||||
TIM1_UP_TIM16_IRQHandler
|
||||
TIM1_TRG_COM_TIM17_IRQHandler
|
||||
TIM1_CC_IRQHandler
|
||||
TIM2_IRQHandler
|
||||
PKA_IRQHandler
|
||||
I2C1_EV_IRQHandler
|
||||
I2C1_ER_IRQHandler
|
||||
SPI1_IRQHandler
|
||||
USART1_IRQHandler
|
||||
EXTI15_10_IRQHandler
|
||||
RTC_Alarm_IRQHandler
|
||||
PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
|
||||
IPCC_C1_RX_IRQHandler
|
||||
IPCC_C1_TX_IRQHandler
|
||||
HSEM_IRQHandler
|
||||
LPTIM1_IRQHandler
|
||||
LPTIM2_IRQHandler
|
||||
AES2_IRQHandler
|
||||
RNG_IRQHandler
|
||||
FPU_IRQHandler
|
||||
DMAMUX1_OVR_IRQHandler
|
||||
|
||||
B .
|
||||
|
||||
ENDP
|
||||
|
||||
ALIGN
|
||||
|
||||
;*******************************************************************************
|
||||
; User Stack and Heap initialization
|
||||
;*******************************************************************************
|
||||
IF :DEF:__MICROLIB
|
||||
|
||||
EXPORT __initial_sp
|
||||
EXPORT __heap_base
|
||||
EXPORT __heap_limit
|
||||
|
||||
ELSE
|
||||
|
||||
IMPORT __use_two_region_memory
|
||||
EXPORT __user_initial_stackheap
|
||||
|
||||
__user_initial_stackheap
|
||||
|
||||
LDR R0, = Heap_Mem
|
||||
LDR R1, =(Stack_Mem + Stack_Size)
|
||||
LDR R2, = (Heap_Mem + Heap_Size)
|
||||
LDR R3, = Stack_Mem
|
||||
BX LR
|
||||
|
||||
ALIGN
|
||||
|
||||
ENDIF
|
||||
|
||||
END
|
||||
|
||||
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
||||
|
|
@ -1,360 +0,0 @@
|
|||
;******************************************************************************
|
||||
;* File Name : startup_stm32wb35xx_cm4.s
|
||||
;* Author : MCD Application Team
|
||||
;* Description : STM32WB35xx devices vector table for MDK-ARM toolchain.
|
||||
;* This module performs:
|
||||
;* - Set the initial SP
|
||||
;* - Set the initial PC == Reset_Handler
|
||||
;* - Set the vector table entries with the exceptions ISR address
|
||||
;* - Branches to __main in the C library (which eventually
|
||||
;* calls main()).
|
||||
;* After Reset the CortexM4 processor is in Thread mode,
|
||||
;* priority is Privileged, and the Stack is set to Main.
|
||||
;* <<< Use Configuration Wizard in Context Menu >>>
|
||||
;******************************************************************************
|
||||
;* @attention
|
||||
;*
|
||||
;* Copyright (c) 2019-2021 STMicroelectronics.
|
||||
;* All rights reserved.
|
||||
;*
|
||||
;* This software is licensed under terms that can be found in the LICENSE file
|
||||
;* in the root directory of this software component.
|
||||
;* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
;*
|
||||
;******************************************************************************
|
||||
|
||||
; Amount of memory (in bytes) allocated for Stack
|
||||
; Tailor this value to your application needs
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00000400
|
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
||||
Stack_Mem SPACE Stack_Size
|
||||
__initial_sp
|
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000000
|
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||
__heap_base
|
||||
Heap_Mem SPACE Heap_Size
|
||||
__heap_limit
|
||||
|
||||
PRESERVE8
|
||||
THUMB
|
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
AREA RESET, DATA, READONLY
|
||||
EXPORT __Vectors
|
||||
EXPORT __Vectors_End
|
||||
EXPORT __Vectors_Size
|
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WWDG_IRQHandler ; Window WatchDog
|
||||
DCD PVD_PVM_IRQHandler ; PVD and PVM detector
|
||||
DCD TAMP_STAMP_LSECSS_IRQHandler ; RTC Tamper and TimeStamp Interrupts and LSECSS Interrupts
|
||||
DCD RTC_WKUP_IRQHandler ; RTC Wakeup Interrupt
|
||||
DCD FLASH_IRQHandler ; FLASH global Interrupt
|
||||
DCD RCC_IRQHandler ; RCC Interrupt
|
||||
DCD EXTI0_IRQHandler ; EXTI Line 0 Interrupt
|
||||
DCD EXTI1_IRQHandler ; EXTI Line 1 Interrupt
|
||||
DCD EXTI2_IRQHandler ; EXTI Line 2 Interrupt
|
||||
DCD EXTI3_IRQHandler ; EXTI Line 3 Interrup
|
||||
DCD EXTI4_IRQHandler ; EXTI Line 4 Interrupt
|
||||
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 Interrupt
|
||||
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 Interrupt
|
||||
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 Interrupt
|
||||
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 Interrupt
|
||||
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 Interrupt
|
||||
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 Interrupt
|
||||
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 Interrupt
|
||||
DCD ADC1_IRQHandler ; ADC1 Interrupt
|
||||
DCD USB_HP_IRQHandler ; USB High Priority Interrupt
|
||||
DCD USB_LP_IRQHandler ; USB Low Priority Interrupt
|
||||
DCD C2SEV_PWR_C2H_IRQHandler ; CPU M0+ SEV Interrupt
|
||||
DCD COMP_IRQHandler ; COMP1 and COMP2 Interrupts
|
||||
DCD EXTI9_5_IRQHandler ; EXTI Lines [9:5] Interrupt
|
||||
DCD TIM1_BRK_IRQHandler ; TIM1 Break Interrupt
|
||||
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16 global Interrupts
|
||||
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Communication and TIM17 global Interrupts
|
||||
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare Interrupt
|
||||
DCD TIM2_IRQHandler ; TIM2 Global Interrupt
|
||||
DCD PKA_IRQHandler ; PKA Interrupt
|
||||
DCD I2C1_EV_IRQHandler ; I2C1 Event Interrupt
|
||||
DCD I2C1_ER_IRQHandler ; I2C1 Error Interrupt
|
||||
DCD I2C3_EV_IRQHandler ; I2C3 Event Interrupt
|
||||
DCD I2C3_ER_IRQHandler ; I2C3 Error Interrupt
|
||||
DCD SPI1_IRQHandler ; SPI1 Interrupt
|
||||
DCD 0 ; Reserved
|
||||
DCD USART1_IRQHandler ; USART1 Interrupt
|
||||
DCD LPUART1_IRQHandler ; LPUART1 Interrupt
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD EXTI15_10_IRQHandler ; EXTI Lines1[15:10 ]Interrupts
|
||||
DCD RTC_Alarm_IRQHandler ; RTC Alarms (A and B) Interrupt
|
||||
DCD CRS_IRQHandler ; CRS interrupt
|
||||
DCD PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
|
||||
DCD IPCC_C1_RX_IRQHandler ; IPCC CPU1 RX occupied interrupt
|
||||
DCD IPCC_C1_TX_IRQHandler ; IPCC CPU1 RX free interrupt
|
||||
DCD HSEM_IRQHandler ; HSEM0 Interrupt
|
||||
DCD LPTIM1_IRQHandler ; LPTIM1 Interrupt
|
||||
DCD LPTIM2_IRQHandler ; LPTIM2 Interrupt
|
||||
DCD 0 ; Reserved
|
||||
DCD QUADSPI_IRQHandler ; QUADSPI Interrupt
|
||||
DCD AES1_IRQHandler ; AES1 Interrupt
|
||||
DCD AES2_IRQHandler ; AES2 Interrupt
|
||||
DCD RNG_IRQHandler ; RNG1 Interrupt
|
||||
DCD FPU_IRQHandler ; FPU Interrupt
|
||||
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 Interrupt
|
||||
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 Interrupt
|
||||
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 Interrupt
|
||||
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 Interrupt
|
||||
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 Interrupt
|
||||
DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6 Interrupt
|
||||
DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7 Interrupt
|
||||
DCD DMAMUX1_OVR_IRQHandler ; DMAMUX overrun Interrupt
|
||||
|
||||
__Vectors_End
|
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
AREA |.text|, CODE, READONLY
|
||||
|
||||
; Reset handler
|
||||
Reset_Handler PROC
|
||||
EXPORT Reset_Handler [WEAK]
|
||||
IMPORT SystemInit
|
||||
IMPORT __main
|
||||
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__main
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC
|
||||
EXPORT NMI_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
HardFault_Handler\
|
||||
PROC
|
||||
EXPORT HardFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
MemManage_Handler\
|
||||
PROC
|
||||
EXPORT MemManage_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
BusFault_Handler\
|
||||
PROC
|
||||
EXPORT BusFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
UsageFault_Handler\
|
||||
PROC
|
||||
EXPORT UsageFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SVC_Handler PROC
|
||||
EXPORT SVC_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
DebugMon_Handler\
|
||||
PROC
|
||||
EXPORT DebugMon_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
PendSV_Handler PROC
|
||||
EXPORT PendSV_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SysTick_Handler PROC
|
||||
EXPORT SysTick_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
Default_Handler PROC
|
||||
|
||||
EXPORT WWDG_IRQHandler [WEAK]
|
||||
EXPORT PVD_PVM_IRQHandler [WEAK]
|
||||
EXPORT TAMP_STAMP_LSECSS_IRQHandler [WEAK]
|
||||
EXPORT RTC_WKUP_IRQHandler [WEAK]
|
||||
EXPORT FLASH_IRQHandler [WEAK]
|
||||
EXPORT RCC_IRQHandler [WEAK]
|
||||
EXPORT EXTI0_IRQHandler [WEAK]
|
||||
EXPORT EXTI1_IRQHandler [WEAK]
|
||||
EXPORT EXTI2_IRQHandler [WEAK]
|
||||
EXPORT EXTI3_IRQHandler [WEAK]
|
||||
EXPORT EXTI4_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel1_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel2_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel3_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel4_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel5_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel6_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel7_IRQHandler [WEAK]
|
||||
EXPORT ADC1_IRQHandler [WEAK]
|
||||
EXPORT USB_HP_IRQHandler [WEAK]
|
||||
EXPORT USB_LP_IRQHandler [WEAK]
|
||||
EXPORT C2SEV_PWR_C2H_IRQHandler [WEAK]
|
||||
EXPORT COMP_IRQHandler [WEAK]
|
||||
EXPORT EXTI9_5_IRQHandler [WEAK]
|
||||
EXPORT TIM1_BRK_IRQHandler [WEAK]
|
||||
EXPORT TIM1_UP_TIM16_IRQHandler [WEAK]
|
||||
EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK]
|
||||
EXPORT TIM1_CC_IRQHandler [WEAK]
|
||||
EXPORT TIM2_IRQHandler [WEAK]
|
||||
EXPORT PKA_IRQHandler [WEAK]
|
||||
EXPORT I2C1_EV_IRQHandler [WEAK]
|
||||
EXPORT I2C1_ER_IRQHandler [WEAK]
|
||||
EXPORT I2C3_EV_IRQHandler [WEAK]
|
||||
EXPORT I2C3_ER_IRQHandler [WEAK]
|
||||
EXPORT SPI1_IRQHandler [WEAK]
|
||||
EXPORT USART1_IRQHandler [WEAK]
|
||||
EXPORT LPUART1_IRQHandler [WEAK]
|
||||
EXPORT EXTI15_10_IRQHandler [WEAK]
|
||||
EXPORT RTC_Alarm_IRQHandler [WEAK]
|
||||
EXPORT CRS_IRQHandler [WEAK]
|
||||
EXPORT PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler [WEAK]
|
||||
EXPORT IPCC_C1_RX_IRQHandler [WEAK]
|
||||
EXPORT IPCC_C1_TX_IRQHandler [WEAK]
|
||||
EXPORT HSEM_IRQHandler [WEAK]
|
||||
EXPORT LPTIM1_IRQHandler [WEAK]
|
||||
EXPORT LPTIM2_IRQHandler [WEAK]
|
||||
EXPORT QUADSPI_IRQHandler [WEAK]
|
||||
EXPORT AES1_IRQHandler [WEAK]
|
||||
EXPORT AES2_IRQHandler [WEAK]
|
||||
EXPORT RNG_IRQHandler [WEAK]
|
||||
EXPORT FPU_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Channel1_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Channel2_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Channel3_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Channel4_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Channel5_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Channel6_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Channel7_IRQHandler [WEAK]
|
||||
EXPORT DMAMUX1_OVR_IRQHandler [WEAK]
|
||||
|
||||
WWDG_IRQHandler
|
||||
PVD_PVM_IRQHandler
|
||||
TAMP_STAMP_LSECSS_IRQHandler
|
||||
RTC_WKUP_IRQHandler
|
||||
FLASH_IRQHandler
|
||||
RCC_IRQHandler
|
||||
EXTI0_IRQHandler
|
||||
EXTI1_IRQHandler
|
||||
EXTI2_IRQHandler
|
||||
EXTI3_IRQHandler
|
||||
EXTI4_IRQHandler
|
||||
DMA1_Channel1_IRQHandler
|
||||
DMA1_Channel2_IRQHandler
|
||||
DMA1_Channel3_IRQHandler
|
||||
DMA1_Channel4_IRQHandler
|
||||
DMA1_Channel5_IRQHandler
|
||||
DMA1_Channel6_IRQHandler
|
||||
DMA1_Channel7_IRQHandler
|
||||
ADC1_IRQHandler
|
||||
USB_HP_IRQHandler
|
||||
USB_LP_IRQHandler
|
||||
C2SEV_PWR_C2H_IRQHandler
|
||||
COMP_IRQHandler
|
||||
EXTI9_5_IRQHandler
|
||||
TIM1_BRK_IRQHandler
|
||||
TIM1_UP_TIM16_IRQHandler
|
||||
TIM1_TRG_COM_TIM17_IRQHandler
|
||||
TIM1_CC_IRQHandler
|
||||
TIM2_IRQHandler
|
||||
PKA_IRQHandler
|
||||
I2C1_EV_IRQHandler
|
||||
I2C1_ER_IRQHandler
|
||||
I2C3_EV_IRQHandler
|
||||
I2C3_ER_IRQHandler
|
||||
SPI1_IRQHandler
|
||||
USART1_IRQHandler
|
||||
LPUART1_IRQHandler
|
||||
EXTI15_10_IRQHandler
|
||||
RTC_Alarm_IRQHandler
|
||||
CRS_IRQHandler
|
||||
PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
|
||||
IPCC_C1_RX_IRQHandler
|
||||
IPCC_C1_TX_IRQHandler
|
||||
HSEM_IRQHandler
|
||||
LPTIM1_IRQHandler
|
||||
LPTIM2_IRQHandler
|
||||
QUADSPI_IRQHandler
|
||||
AES1_IRQHandler
|
||||
AES2_IRQHandler
|
||||
RNG_IRQHandler
|
||||
FPU_IRQHandler
|
||||
DMA2_Channel1_IRQHandler
|
||||
DMA2_Channel2_IRQHandler
|
||||
DMA2_Channel3_IRQHandler
|
||||
DMA2_Channel4_IRQHandler
|
||||
DMA2_Channel5_IRQHandler
|
||||
DMA2_Channel6_IRQHandler
|
||||
DMA2_Channel7_IRQHandler
|
||||
DMAMUX1_OVR_IRQHandler
|
||||
|
||||
B .
|
||||
|
||||
ENDP
|
||||
|
||||
ALIGN
|
||||
|
||||
;*******************************************************************************
|
||||
; User Stack and Heap initialization
|
||||
;*******************************************************************************
|
||||
IF :DEF:__MICROLIB
|
||||
|
||||
EXPORT __initial_sp
|
||||
EXPORT __heap_base
|
||||
EXPORT __heap_limit
|
||||
|
||||
ELSE
|
||||
|
||||
IMPORT __use_two_region_memory
|
||||
EXPORT __user_initial_stackheap
|
||||
|
||||
__user_initial_stackheap
|
||||
|
||||
LDR R0, = Heap_Mem
|
||||
LDR R1, =(Stack_Mem + Stack_Size)
|
||||
LDR R2, = (Heap_Mem + Heap_Size)
|
||||
LDR R3, = Stack_Mem
|
||||
BX LR
|
||||
|
||||
ALIGN
|
||||
|
||||
ENDIF
|
||||
|
||||
END
|
||||
|
||||
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
||||
|
|
@ -1,328 +0,0 @@
|
|||
;******************************************************************************
|
||||
;* File Name : startup_stm32wb50xx_cm4.s
|
||||
;* Author : MCD Application Team
|
||||
;* Description : STM32WB50xx devices vector table for MDK-ARM toolchain.
|
||||
;* This module performs:
|
||||
;* - Set the initial SP
|
||||
;* - Set the initial PC == Reset_Handler
|
||||
;* - Set the vector table entries with the exceptions ISR address
|
||||
;* - Branches to __main in the C library (which eventually
|
||||
;* calls main()).
|
||||
;* After Reset the CortexM4 processor is in Thread mode,
|
||||
;* priority is Privileged, and the Stack is set to Main.
|
||||
;* <<< Use Configuration Wizard in Context Menu >>>
|
||||
;******************************************************************************
|
||||
;* @attention
|
||||
;*
|
||||
;* Copyright (c) 2019-2021 STMicroelectronics.
|
||||
;* All rights reserved.
|
||||
;*
|
||||
;* This software is licensed under terms that can be found in the LICENSE file
|
||||
;* in the root directory of this software component.
|
||||
;* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
;*
|
||||
;******************************************************************************
|
||||
|
||||
; Amount of memory (in bytes) allocated for Stack
|
||||
; Tailor this value to your application needs
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00000400
|
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
||||
Stack_Mem SPACE Stack_Size
|
||||
__initial_sp
|
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000000
|
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||
__heap_base
|
||||
Heap_Mem SPACE Heap_Size
|
||||
__heap_limit
|
||||
|
||||
PRESERVE8
|
||||
THUMB
|
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
AREA RESET, DATA, READONLY
|
||||
EXPORT __Vectors
|
||||
EXPORT __Vectors_End
|
||||
EXPORT __Vectors_Size
|
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WWDG_IRQHandler ; Window WatchDog
|
||||
DCD PVD_PVM_IRQHandler ; PVD and PVM detector
|
||||
DCD TAMP_STAMP_LSECSS_IRQHandler ; RTC Tamper and TimeStamp Interrupts and LSECSS Interrupts
|
||||
DCD RTC_WKUP_IRQHandler ; RTC Wakeup Interrupt
|
||||
DCD FLASH_IRQHandler ; FLASH global Interrupt
|
||||
DCD RCC_IRQHandler ; RCC Interrupt
|
||||
DCD EXTI0_IRQHandler ; EXTI Line 0 Interrupt
|
||||
DCD EXTI1_IRQHandler ; EXTI Line 1 Interrupt
|
||||
DCD EXTI2_IRQHandler ; EXTI Line 2 Interrupt
|
||||
DCD EXTI3_IRQHandler ; EXTI Line 3 Interrup
|
||||
DCD EXTI4_IRQHandler ; EXTI Line 4 Interrupt
|
||||
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 Interrupt
|
||||
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 Interrupt
|
||||
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 Interrupt
|
||||
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 Interrupt
|
||||
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 Interrupt
|
||||
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 Interrupt
|
||||
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 Interrupt
|
||||
DCD ADC1_IRQHandler ; ADC1 Interrupt
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD C2SEV_PWR_C2H_IRQHandler ; CPU M0+ SEV Interrupt
|
||||
DCD 0 ; Reserved
|
||||
DCD EXTI9_5_IRQHandler ; EXTI Lines [9:5] Interrupt
|
||||
DCD TIM1_BRK_IRQHandler ; TIM1 Break Interrupt
|
||||
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16 global Interrupts
|
||||
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Communication and TIM17 global Interrupts
|
||||
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare Interrupt
|
||||
DCD TIM2_IRQHandler ; TIM2 Global Interrupt
|
||||
DCD PKA_IRQHandler ; PKA Interrupt
|
||||
DCD I2C1_EV_IRQHandler ; I2C1 Event Interrupt
|
||||
DCD I2C1_ER_IRQHandler ; I2C1 Error Interrupt
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SPI1_IRQHandler ; SPI1 Interrupt
|
||||
DCD 0 ; Reserved
|
||||
DCD USART1_IRQHandler ; USART1 Interrupt
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD EXTI15_10_IRQHandler ; EXTI Lines1[15:10 ]Interrupts
|
||||
DCD RTC_Alarm_IRQHandler ; RTC Alarms (A and B) Interrupt
|
||||
DCD 0 ; Reserved
|
||||
DCD PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
|
||||
DCD IPCC_C1_RX_IRQHandler ; IPCC CPU1 RX occupied interrupt
|
||||
DCD IPCC_C1_TX_IRQHandler ; IPCC CPU1 RX free interrupt
|
||||
DCD HSEM_IRQHandler ; HSEM0 Interrupt
|
||||
DCD LPTIM1_IRQHandler ; LPTIM1 Interrupt
|
||||
DCD LPTIM2_IRQHandler ; LPTIM2 Interrupt
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD AES2_IRQHandler ; AES2 Interrupt
|
||||
DCD RNG_IRQHandler ; RNG1 Interrupt
|
||||
DCD FPU_IRQHandler ; FPU Interrupt
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD DMAMUX1_OVR_IRQHandler ; DMAMUX overrun Interrupt
|
||||
|
||||
__Vectors_End
|
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
AREA |.text|, CODE, READONLY
|
||||
|
||||
; Reset handler
|
||||
Reset_Handler PROC
|
||||
EXPORT Reset_Handler [WEAK]
|
||||
IMPORT SystemInit
|
||||
IMPORT __main
|
||||
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__main
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC
|
||||
EXPORT NMI_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
HardFault_Handler\
|
||||
PROC
|
||||
EXPORT HardFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
MemManage_Handler\
|
||||
PROC
|
||||
EXPORT MemManage_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
BusFault_Handler\
|
||||
PROC
|
||||
EXPORT BusFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
UsageFault_Handler\
|
||||
PROC
|
||||
EXPORT UsageFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SVC_Handler PROC
|
||||
EXPORT SVC_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
DebugMon_Handler\
|
||||
PROC
|
||||
EXPORT DebugMon_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
PendSV_Handler PROC
|
||||
EXPORT PendSV_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SysTick_Handler PROC
|
||||
EXPORT SysTick_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
Default_Handler PROC
|
||||
|
||||
EXPORT WWDG_IRQHandler [WEAK]
|
||||
EXPORT PVD_PVM_IRQHandler [WEAK]
|
||||
EXPORT TAMP_STAMP_LSECSS_IRQHandler [WEAK]
|
||||
EXPORT RTC_WKUP_IRQHandler [WEAK]
|
||||
EXPORT FLASH_IRQHandler [WEAK]
|
||||
EXPORT RCC_IRQHandler [WEAK]
|
||||
EXPORT EXTI0_IRQHandler [WEAK]
|
||||
EXPORT EXTI1_IRQHandler [WEAK]
|
||||
EXPORT EXTI2_IRQHandler [WEAK]
|
||||
EXPORT EXTI3_IRQHandler [WEAK]
|
||||
EXPORT EXTI4_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel1_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel2_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel3_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel4_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel5_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel6_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel7_IRQHandler [WEAK]
|
||||
EXPORT ADC1_IRQHandler [WEAK]
|
||||
EXPORT C2SEV_PWR_C2H_IRQHandler [WEAK]
|
||||
EXPORT EXTI9_5_IRQHandler [WEAK]
|
||||
EXPORT TIM1_BRK_IRQHandler [WEAK]
|
||||
EXPORT TIM1_UP_TIM16_IRQHandler [WEAK]
|
||||
EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK]
|
||||
EXPORT TIM1_CC_IRQHandler [WEAK]
|
||||
EXPORT TIM2_IRQHandler [WEAK]
|
||||
EXPORT PKA_IRQHandler [WEAK]
|
||||
EXPORT I2C1_EV_IRQHandler [WEAK]
|
||||
EXPORT I2C1_ER_IRQHandler [WEAK]
|
||||
EXPORT SPI1_IRQHandler [WEAK]
|
||||
EXPORT USART1_IRQHandler [WEAK]
|
||||
EXPORT EXTI15_10_IRQHandler [WEAK]
|
||||
EXPORT RTC_Alarm_IRQHandler [WEAK]
|
||||
EXPORT PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler [WEAK]
|
||||
EXPORT IPCC_C1_RX_IRQHandler [WEAK]
|
||||
EXPORT IPCC_C1_TX_IRQHandler [WEAK]
|
||||
EXPORT HSEM_IRQHandler [WEAK]
|
||||
EXPORT LPTIM1_IRQHandler [WEAK]
|
||||
EXPORT LPTIM2_IRQHandler [WEAK]
|
||||
EXPORT AES2_IRQHandler [WEAK]
|
||||
EXPORT RNG_IRQHandler [WEAK]
|
||||
EXPORT FPU_IRQHandler [WEAK]
|
||||
EXPORT DMAMUX1_OVR_IRQHandler [WEAK]
|
||||
|
||||
WWDG_IRQHandler
|
||||
PVD_PVM_IRQHandler
|
||||
TAMP_STAMP_LSECSS_IRQHandler
|
||||
RTC_WKUP_IRQHandler
|
||||
FLASH_IRQHandler
|
||||
RCC_IRQHandler
|
||||
EXTI0_IRQHandler
|
||||
EXTI1_IRQHandler
|
||||
EXTI2_IRQHandler
|
||||
EXTI3_IRQHandler
|
||||
EXTI4_IRQHandler
|
||||
DMA1_Channel1_IRQHandler
|
||||
DMA1_Channel2_IRQHandler
|
||||
DMA1_Channel3_IRQHandler
|
||||
DMA1_Channel4_IRQHandler
|
||||
DMA1_Channel5_IRQHandler
|
||||
DMA1_Channel6_IRQHandler
|
||||
DMA1_Channel7_IRQHandler
|
||||
ADC1_IRQHandler
|
||||
C2SEV_PWR_C2H_IRQHandler
|
||||
EXTI9_5_IRQHandler
|
||||
TIM1_BRK_IRQHandler
|
||||
TIM1_UP_TIM16_IRQHandler
|
||||
TIM1_TRG_COM_TIM17_IRQHandler
|
||||
TIM1_CC_IRQHandler
|
||||
TIM2_IRQHandler
|
||||
PKA_IRQHandler
|
||||
I2C1_EV_IRQHandler
|
||||
I2C1_ER_IRQHandler
|
||||
SPI1_IRQHandler
|
||||
USART1_IRQHandler
|
||||
EXTI15_10_IRQHandler
|
||||
RTC_Alarm_IRQHandler
|
||||
PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
|
||||
IPCC_C1_RX_IRQHandler
|
||||
IPCC_C1_TX_IRQHandler
|
||||
HSEM_IRQHandler
|
||||
LPTIM1_IRQHandler
|
||||
LPTIM2_IRQHandler
|
||||
AES2_IRQHandler
|
||||
RNG_IRQHandler
|
||||
FPU_IRQHandler
|
||||
DMAMUX1_OVR_IRQHandler
|
||||
|
||||
B .
|
||||
|
||||
ENDP
|
||||
|
||||
ALIGN
|
||||
|
||||
;*******************************************************************************
|
||||
; User Stack and Heap initialization
|
||||
;*******************************************************************************
|
||||
IF :DEF:__MICROLIB
|
||||
|
||||
EXPORT __initial_sp
|
||||
EXPORT __heap_base
|
||||
EXPORT __heap_limit
|
||||
|
||||
ELSE
|
||||
|
||||
IMPORT __use_two_region_memory
|
||||
EXPORT __user_initial_stackheap
|
||||
|
||||
__user_initial_stackheap
|
||||
|
||||
LDR R0, = Heap_Mem
|
||||
LDR R1, =(Stack_Mem + Stack_Size)
|
||||
LDR R2, = (Heap_Mem + Heap_Size)
|
||||
LDR R3, = Stack_Mem
|
||||
BX LR
|
||||
|
||||
ALIGN
|
||||
|
||||
ENDIF
|
||||
|
||||
END
|
||||
|
||||
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
||||
|
|
@ -1,368 +0,0 @@
|
|||
;******************************************************************************
|
||||
;* File Name : startup_stm32wb55xx_cm4.s
|
||||
;* Author : MCD Application Team
|
||||
;* Description : STM32WB55xx devices vector table for MDK-ARM toolchain.
|
||||
;* This module performs:
|
||||
;* - Set the initial SP
|
||||
;* - Set the initial PC == Reset_Handler
|
||||
;* - Set the vector table entries with the exceptions ISR address
|
||||
;* - Branches to __main in the C library (which eventually
|
||||
;* calls main()).
|
||||
;* After Reset the CortexM4 processor is in Thread mode,
|
||||
;* priority is Privileged, and the Stack is set to Main.
|
||||
;* <<< Use Configuration Wizard in Context Menu >>>
|
||||
;******************************************************************************
|
||||
;* @attention
|
||||
;*
|
||||
;* Copyright (c) 2019-2021 STMicroelectronics.
|
||||
;* All rights reserved.
|
||||
;*
|
||||
;* This software is licensed under terms that can be found in the LICENSE file
|
||||
;* in the root directory of this software component.
|
||||
;* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
;*
|
||||
;******************************************************************************
|
||||
|
||||
; Amount of memory (in bytes) allocated for Stack
|
||||
; Tailor this value to your application needs
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00000400
|
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
||||
Stack_Mem SPACE Stack_Size
|
||||
__initial_sp
|
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000000
|
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||
__heap_base
|
||||
Heap_Mem SPACE Heap_Size
|
||||
__heap_limit
|
||||
|
||||
PRESERVE8
|
||||
THUMB
|
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
AREA RESET, DATA, READONLY
|
||||
EXPORT __Vectors
|
||||
EXPORT __Vectors_End
|
||||
EXPORT __Vectors_Size
|
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WWDG_IRQHandler ; Window WatchDog
|
||||
DCD PVD_PVM_IRQHandler ; PVD and PVM detector
|
||||
DCD TAMP_STAMP_LSECSS_IRQHandler ; RTC Tamper and TimeStamp Interrupts and LSECSS Interrupts
|
||||
DCD RTC_WKUP_IRQHandler ; RTC Wakeup Interrupt
|
||||
DCD FLASH_IRQHandler ; FLASH global Interrupt
|
||||
DCD RCC_IRQHandler ; RCC Interrupt
|
||||
DCD EXTI0_IRQHandler ; EXTI Line 0 Interrupt
|
||||
DCD EXTI1_IRQHandler ; EXTI Line 1 Interrupt
|
||||
DCD EXTI2_IRQHandler ; EXTI Line 2 Interrupt
|
||||
DCD EXTI3_IRQHandler ; EXTI Line 3 Interrup
|
||||
DCD EXTI4_IRQHandler ; EXTI Line 4 Interrupt
|
||||
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 Interrupt
|
||||
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 Interrupt
|
||||
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 Interrupt
|
||||
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 Interrupt
|
||||
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 Interrupt
|
||||
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 Interrupt
|
||||
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 Interrupt
|
||||
DCD ADC1_IRQHandler ; ADC1 Interrupt
|
||||
DCD USB_HP_IRQHandler ; USB High Priority Interrupt
|
||||
DCD USB_LP_IRQHandler ; USB Low Priority Interrupt
|
||||
DCD C2SEV_PWR_C2H_IRQHandler ; CPU M0+ SEV Interrupt
|
||||
DCD COMP_IRQHandler ; COMP1 and COMP2 Interrupts
|
||||
DCD EXTI9_5_IRQHandler ; EXTI Lines [9:5] Interrupt
|
||||
DCD TIM1_BRK_IRQHandler ; TIM1 Break Interrupt
|
||||
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16 global Interrupts
|
||||
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Communication and TIM17 global Interrupts
|
||||
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare Interrupt
|
||||
DCD TIM2_IRQHandler ; TIM2 Global Interrupt
|
||||
DCD PKA_IRQHandler ; PKA Interrupt
|
||||
DCD I2C1_EV_IRQHandler ; I2C1 Event Interrupt
|
||||
DCD I2C1_ER_IRQHandler ; I2C1 Error Interrupt
|
||||
DCD I2C3_EV_IRQHandler ; I2C3 Event Interrupt
|
||||
DCD I2C3_ER_IRQHandler ; I2C3 Error Interrupt
|
||||
DCD SPI1_IRQHandler ; SPI1 Interrupt
|
||||
DCD SPI2_IRQHandler ; SPI2 Interrupt
|
||||
DCD USART1_IRQHandler ; USART1 Interrupt
|
||||
DCD LPUART1_IRQHandler ; LPUART1 Interrupt
|
||||
DCD SAI1_IRQHandler ; SAI Interrupt
|
||||
DCD TSC_IRQHandler ; TSC Interrupt
|
||||
DCD EXTI15_10_IRQHandler ; EXTI Lines1[15:10 ]Interrupts
|
||||
DCD RTC_Alarm_IRQHandler ; RTC Alarms (A and B) Interrupt
|
||||
DCD CRS_IRQHandler ; CRS interrupt
|
||||
DCD PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
|
||||
DCD IPCC_C1_RX_IRQHandler ; IPCC CPU1 RX occupied interrupt
|
||||
DCD IPCC_C1_TX_IRQHandler ; IPCC CPU1 RX free interrupt
|
||||
DCD HSEM_IRQHandler ; HSEM0 Interrupt
|
||||
DCD LPTIM1_IRQHandler ; LPTIM1 Interrupt
|
||||
DCD LPTIM2_IRQHandler ; LPTIM2 Interrupt
|
||||
DCD LCD_IRQHandler ; LCD Interrupt
|
||||
DCD QUADSPI_IRQHandler ; QUADSPI Interrupt
|
||||
DCD AES1_IRQHandler ; AES1 Interrupt
|
||||
DCD AES2_IRQHandler ; AES2 Interrupt
|
||||
DCD RNG_IRQHandler ; RNG1 Interrupt
|
||||
DCD FPU_IRQHandler ; FPU Interrupt
|
||||
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 Interrupt
|
||||
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 Interrupt
|
||||
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 Interrupt
|
||||
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 Interrupt
|
||||
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 Interrupt
|
||||
DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6 Interrupt
|
||||
DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7 Interrupt
|
||||
DCD DMAMUX1_OVR_IRQHandler ; DMAMUX overrun Interrupt
|
||||
|
||||
__Vectors_End
|
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
AREA |.text|, CODE, READONLY
|
||||
|
||||
; Reset handler
|
||||
Reset_Handler PROC
|
||||
EXPORT Reset_Handler [WEAK]
|
||||
IMPORT SystemInit
|
||||
IMPORT __main
|
||||
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__main
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC
|
||||
EXPORT NMI_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
HardFault_Handler\
|
||||
PROC
|
||||
EXPORT HardFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
MemManage_Handler\
|
||||
PROC
|
||||
EXPORT MemManage_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
BusFault_Handler\
|
||||
PROC
|
||||
EXPORT BusFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
UsageFault_Handler\
|
||||
PROC
|
||||
EXPORT UsageFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SVC_Handler PROC
|
||||
EXPORT SVC_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
DebugMon_Handler\
|
||||
PROC
|
||||
EXPORT DebugMon_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
PendSV_Handler PROC
|
||||
EXPORT PendSV_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SysTick_Handler PROC
|
||||
EXPORT SysTick_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
Default_Handler PROC
|
||||
|
||||
EXPORT WWDG_IRQHandler [WEAK]
|
||||
EXPORT PVD_PVM_IRQHandler [WEAK]
|
||||
EXPORT TAMP_STAMP_LSECSS_IRQHandler [WEAK]
|
||||
EXPORT RTC_WKUP_IRQHandler [WEAK]
|
||||
EXPORT FLASH_IRQHandler [WEAK]
|
||||
EXPORT RCC_IRQHandler [WEAK]
|
||||
EXPORT EXTI0_IRQHandler [WEAK]
|
||||
EXPORT EXTI1_IRQHandler [WEAK]
|
||||
EXPORT EXTI2_IRQHandler [WEAK]
|
||||
EXPORT EXTI3_IRQHandler [WEAK]
|
||||
EXPORT EXTI4_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel1_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel2_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel3_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel4_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel5_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel6_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel7_IRQHandler [WEAK]
|
||||
EXPORT ADC1_IRQHandler [WEAK]
|
||||
EXPORT USB_HP_IRQHandler [WEAK]
|
||||
EXPORT USB_LP_IRQHandler [WEAK]
|
||||
EXPORT C2SEV_PWR_C2H_IRQHandler [WEAK]
|
||||
EXPORT COMP_IRQHandler [WEAK]
|
||||
EXPORT EXTI9_5_IRQHandler [WEAK]
|
||||
EXPORT TIM1_BRK_IRQHandler [WEAK]
|
||||
EXPORT TIM1_UP_TIM16_IRQHandler [WEAK]
|
||||
EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK]
|
||||
EXPORT TIM1_CC_IRQHandler [WEAK]
|
||||
EXPORT TIM2_IRQHandler [WEAK]
|
||||
EXPORT PKA_IRQHandler [WEAK]
|
||||
EXPORT I2C1_EV_IRQHandler [WEAK]
|
||||
EXPORT I2C1_ER_IRQHandler [WEAK]
|
||||
EXPORT I2C3_EV_IRQHandler [WEAK]
|
||||
EXPORT I2C3_ER_IRQHandler [WEAK]
|
||||
EXPORT SPI1_IRQHandler [WEAK]
|
||||
EXPORT SPI2_IRQHandler [WEAK]
|
||||
EXPORT USART1_IRQHandler [WEAK]
|
||||
EXPORT LPUART1_IRQHandler [WEAK]
|
||||
EXPORT SAI1_IRQHandler [WEAK]
|
||||
EXPORT TSC_IRQHandler [WEAK]
|
||||
EXPORT EXTI15_10_IRQHandler [WEAK]
|
||||
EXPORT RTC_Alarm_IRQHandler [WEAK]
|
||||
EXPORT CRS_IRQHandler [WEAK]
|
||||
EXPORT PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler [WEAK]
|
||||
EXPORT IPCC_C1_RX_IRQHandler [WEAK]
|
||||
EXPORT IPCC_C1_TX_IRQHandler [WEAK]
|
||||
EXPORT HSEM_IRQHandler [WEAK]
|
||||
EXPORT LPTIM1_IRQHandler [WEAK]
|
||||
EXPORT LPTIM2_IRQHandler [WEAK]
|
||||
EXPORT LCD_IRQHandler [WEAK]
|
||||
EXPORT QUADSPI_IRQHandler [WEAK]
|
||||
EXPORT AES1_IRQHandler [WEAK]
|
||||
EXPORT AES2_IRQHandler [WEAK]
|
||||
EXPORT RNG_IRQHandler [WEAK]
|
||||
EXPORT FPU_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Channel1_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Channel2_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Channel3_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Channel4_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Channel5_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Channel6_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Channel7_IRQHandler [WEAK]
|
||||
EXPORT DMAMUX1_OVR_IRQHandler [WEAK]
|
||||
|
||||
WWDG_IRQHandler
|
||||
PVD_PVM_IRQHandler
|
||||
TAMP_STAMP_LSECSS_IRQHandler
|
||||
RTC_WKUP_IRQHandler
|
||||
FLASH_IRQHandler
|
||||
RCC_IRQHandler
|
||||
EXTI0_IRQHandler
|
||||
EXTI1_IRQHandler
|
||||
EXTI2_IRQHandler
|
||||
EXTI3_IRQHandler
|
||||
EXTI4_IRQHandler
|
||||
DMA1_Channel1_IRQHandler
|
||||
DMA1_Channel2_IRQHandler
|
||||
DMA1_Channel3_IRQHandler
|
||||
DMA1_Channel4_IRQHandler
|
||||
DMA1_Channel5_IRQHandler
|
||||
DMA1_Channel6_IRQHandler
|
||||
DMA1_Channel7_IRQHandler
|
||||
ADC1_IRQHandler
|
||||
USB_HP_IRQHandler
|
||||
USB_LP_IRQHandler
|
||||
C2SEV_PWR_C2H_IRQHandler
|
||||
COMP_IRQHandler
|
||||
EXTI9_5_IRQHandler
|
||||
TIM1_BRK_IRQHandler
|
||||
TIM1_UP_TIM16_IRQHandler
|
||||
TIM1_TRG_COM_TIM17_IRQHandler
|
||||
TIM1_CC_IRQHandler
|
||||
TIM2_IRQHandler
|
||||
PKA_IRQHandler
|
||||
I2C1_EV_IRQHandler
|
||||
I2C1_ER_IRQHandler
|
||||
I2C3_EV_IRQHandler
|
||||
I2C3_ER_IRQHandler
|
||||
SPI1_IRQHandler
|
||||
SPI2_IRQHandler
|
||||
USART1_IRQHandler
|
||||
LPUART1_IRQHandler
|
||||
SAI1_IRQHandler
|
||||
TSC_IRQHandler
|
||||
EXTI15_10_IRQHandler
|
||||
RTC_Alarm_IRQHandler
|
||||
CRS_IRQHandler
|
||||
PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
|
||||
IPCC_C1_RX_IRQHandler
|
||||
IPCC_C1_TX_IRQHandler
|
||||
HSEM_IRQHandler
|
||||
LPTIM1_IRQHandler
|
||||
LPTIM2_IRQHandler
|
||||
LCD_IRQHandler
|
||||
QUADSPI_IRQHandler
|
||||
AES1_IRQHandler
|
||||
AES2_IRQHandler
|
||||
RNG_IRQHandler
|
||||
FPU_IRQHandler
|
||||
DMA2_Channel1_IRQHandler
|
||||
DMA2_Channel2_IRQHandler
|
||||
DMA2_Channel3_IRQHandler
|
||||
DMA2_Channel4_IRQHandler
|
||||
DMA2_Channel5_IRQHandler
|
||||
DMA2_Channel6_IRQHandler
|
||||
DMA2_Channel7_IRQHandler
|
||||
DMAMUX1_OVR_IRQHandler
|
||||
|
||||
B .
|
||||
|
||||
ENDP
|
||||
|
||||
ALIGN
|
||||
|
||||
;*******************************************************************************
|
||||
; User Stack and Heap initialization
|
||||
;*******************************************************************************
|
||||
IF :DEF:__MICROLIB
|
||||
|
||||
EXPORT __initial_sp
|
||||
EXPORT __heap_base
|
||||
EXPORT __heap_limit
|
||||
|
||||
ELSE
|
||||
|
||||
IMPORT __use_two_region_memory
|
||||
EXPORT __user_initial_stackheap
|
||||
|
||||
__user_initial_stackheap
|
||||
|
||||
LDR R0, = Heap_Mem
|
||||
LDR R1, =(Stack_Mem + Stack_Size)
|
||||
LDR R2, = (Heap_Mem + Heap_Size)
|
||||
LDR R3, = Stack_Mem
|
||||
BX LR
|
||||
|
||||
ALIGN
|
||||
|
||||
ENDIF
|
||||
|
||||
END
|
||||
|
||||
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
||||
|
|
@ -1,368 +0,0 @@
|
|||
;******************************************************************************
|
||||
;* File Name : startup_stm32wb5mxx_cm4.s
|
||||
;* Author : MCD Application Team
|
||||
;* Description : STM32WB5Mxx devices vector table for MDK-ARM toolchain.
|
||||
;* This module performs:
|
||||
;* - Set the initial SP
|
||||
;* - Set the initial PC == Reset_Handler
|
||||
;* - Set the vector table entries with the exceptions ISR address
|
||||
;* - Branches to __main in the C library (which eventually
|
||||
;* calls main()).
|
||||
;* After Reset the CortexM4 processor is in Thread mode,
|
||||
;* priority is Privileged, and the Stack is set to Main.
|
||||
;* <<< Use Configuration Wizard in Context Menu >>>
|
||||
;******************************************************************************
|
||||
;* @attention
|
||||
;*
|
||||
;* Copyright (c) 2019-2021 STMicroelectronics.
|
||||
;* All rights reserved.
|
||||
;*
|
||||
;* This software is licensed under terms that can be found in the LICENSE file
|
||||
;* in the root directory of this software component.
|
||||
;* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
;*
|
||||
;******************************************************************************
|
||||
|
||||
; Amount of memory (in bytes) allocated for Stack
|
||||
; Tailor this value to your application needs
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00000400
|
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
||||
Stack_Mem SPACE Stack_Size
|
||||
__initial_sp
|
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000000
|
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||
__heap_base
|
||||
Heap_Mem SPACE Heap_Size
|
||||
__heap_limit
|
||||
|
||||
PRESERVE8
|
||||
THUMB
|
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
AREA RESET, DATA, READONLY
|
||||
EXPORT __Vectors
|
||||
EXPORT __Vectors_End
|
||||
EXPORT __Vectors_Size
|
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WWDG_IRQHandler ; Window WatchDog
|
||||
DCD PVD_PVM_IRQHandler ; PVD and PVM detector
|
||||
DCD TAMP_STAMP_LSECSS_IRQHandler ; RTC Tamper and TimeStamp Interrupts and LSECSS Interrupts
|
||||
DCD RTC_WKUP_IRQHandler ; RTC Wakeup Interrupt
|
||||
DCD FLASH_IRQHandler ; FLASH global Interrupt
|
||||
DCD RCC_IRQHandler ; RCC Interrupt
|
||||
DCD EXTI0_IRQHandler ; EXTI Line 0 Interrupt
|
||||
DCD EXTI1_IRQHandler ; EXTI Line 1 Interrupt
|
||||
DCD EXTI2_IRQHandler ; EXTI Line 2 Interrupt
|
||||
DCD EXTI3_IRQHandler ; EXTI Line 3 Interrup
|
||||
DCD EXTI4_IRQHandler ; EXTI Line 4 Interrupt
|
||||
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 Interrupt
|
||||
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 Interrupt
|
||||
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 Interrupt
|
||||
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 Interrupt
|
||||
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 Interrupt
|
||||
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 Interrupt
|
||||
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 Interrupt
|
||||
DCD ADC1_IRQHandler ; ADC1 Interrupt
|
||||
DCD USB_HP_IRQHandler ; USB High Priority Interrupt
|
||||
DCD USB_LP_IRQHandler ; USB Low Priority Interrupt
|
||||
DCD C2SEV_PWR_C2H_IRQHandler ; CPU M0+ SEV Interrupt
|
||||
DCD COMP_IRQHandler ; COMP1 and COMP2 Interrupts
|
||||
DCD EXTI9_5_IRQHandler ; EXTI Lines [9:5] Interrupt
|
||||
DCD TIM1_BRK_IRQHandler ; TIM1 Break Interrupt
|
||||
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16 global Interrupts
|
||||
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Communication and TIM17 global Interrupts
|
||||
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare Interrupt
|
||||
DCD TIM2_IRQHandler ; TIM2 Global Interrupt
|
||||
DCD PKA_IRQHandler ; PKA Interrupt
|
||||
DCD I2C1_EV_IRQHandler ; I2C1 Event Interrupt
|
||||
DCD I2C1_ER_IRQHandler ; I2C1 Error Interrupt
|
||||
DCD I2C3_EV_IRQHandler ; I2C3 Event Interrupt
|
||||
DCD I2C3_ER_IRQHandler ; I2C3 Error Interrupt
|
||||
DCD SPI1_IRQHandler ; SPI1 Interrupt
|
||||
DCD SPI2_IRQHandler ; SPI2 Interrupt
|
||||
DCD USART1_IRQHandler ; USART1 Interrupt
|
||||
DCD LPUART1_IRQHandler ; LPUART1 Interrupt
|
||||
DCD SAI1_IRQHandler ; SAI Interrupt
|
||||
DCD TSC_IRQHandler ; TSC Interrupt
|
||||
DCD EXTI15_10_IRQHandler ; EXTI Lines1[15:10 ]Interrupts
|
||||
DCD RTC_Alarm_IRQHandler ; RTC Alarms (A and B) Interrupt
|
||||
DCD CRS_IRQHandler ; CRS interrupt
|
||||
DCD PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
|
||||
DCD IPCC_C1_RX_IRQHandler ; IPCC CPU1 RX occupied interrupt
|
||||
DCD IPCC_C1_TX_IRQHandler ; IPCC CPU1 RX free interrupt
|
||||
DCD HSEM_IRQHandler ; HSEM0 Interrupt
|
||||
DCD LPTIM1_IRQHandler ; LPTIM1 Interrupt
|
||||
DCD LPTIM2_IRQHandler ; LPTIM2 Interrupt
|
||||
DCD LCD_IRQHandler ; LCD Interrupt
|
||||
DCD QUADSPI_IRQHandler ; QUADSPI Interrupt
|
||||
DCD AES1_IRQHandler ; AES1 Interrupt
|
||||
DCD AES2_IRQHandler ; AES2 Interrupt
|
||||
DCD RNG_IRQHandler ; RNG1 Interrupt
|
||||
DCD FPU_IRQHandler ; FPU Interrupt
|
||||
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 Interrupt
|
||||
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 Interrupt
|
||||
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 Interrupt
|
||||
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 Interrupt
|
||||
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 Interrupt
|
||||
DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6 Interrupt
|
||||
DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7 Interrupt
|
||||
DCD DMAMUX1_OVR_IRQHandler ; DMAMUX overrun Interrupt
|
||||
|
||||
__Vectors_End
|
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
AREA |.text|, CODE, READONLY
|
||||
|
||||
; Reset handler
|
||||
Reset_Handler PROC
|
||||
EXPORT Reset_Handler [WEAK]
|
||||
IMPORT SystemInit
|
||||
IMPORT __main
|
||||
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__main
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC
|
||||
EXPORT NMI_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
HardFault_Handler\
|
||||
PROC
|
||||
EXPORT HardFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
MemManage_Handler\
|
||||
PROC
|
||||
EXPORT MemManage_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
BusFault_Handler\
|
||||
PROC
|
||||
EXPORT BusFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
UsageFault_Handler\
|
||||
PROC
|
||||
EXPORT UsageFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SVC_Handler PROC
|
||||
EXPORT SVC_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
DebugMon_Handler\
|
||||
PROC
|
||||
EXPORT DebugMon_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
PendSV_Handler PROC
|
||||
EXPORT PendSV_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SysTick_Handler PROC
|
||||
EXPORT SysTick_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
Default_Handler PROC
|
||||
|
||||
EXPORT WWDG_IRQHandler [WEAK]
|
||||
EXPORT PVD_PVM_IRQHandler [WEAK]
|
||||
EXPORT TAMP_STAMP_LSECSS_IRQHandler [WEAK]
|
||||
EXPORT RTC_WKUP_IRQHandler [WEAK]
|
||||
EXPORT FLASH_IRQHandler [WEAK]
|
||||
EXPORT RCC_IRQHandler [WEAK]
|
||||
EXPORT EXTI0_IRQHandler [WEAK]
|
||||
EXPORT EXTI1_IRQHandler [WEAK]
|
||||
EXPORT EXTI2_IRQHandler [WEAK]
|
||||
EXPORT EXTI3_IRQHandler [WEAK]
|
||||
EXPORT EXTI4_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel1_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel2_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel3_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel4_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel5_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel6_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel7_IRQHandler [WEAK]
|
||||
EXPORT ADC1_IRQHandler [WEAK]
|
||||
EXPORT USB_HP_IRQHandler [WEAK]
|
||||
EXPORT USB_LP_IRQHandler [WEAK]
|
||||
EXPORT C2SEV_PWR_C2H_IRQHandler [WEAK]
|
||||
EXPORT COMP_IRQHandler [WEAK]
|
||||
EXPORT EXTI9_5_IRQHandler [WEAK]
|
||||
EXPORT TIM1_BRK_IRQHandler [WEAK]
|
||||
EXPORT TIM1_UP_TIM16_IRQHandler [WEAK]
|
||||
EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK]
|
||||
EXPORT TIM1_CC_IRQHandler [WEAK]
|
||||
EXPORT TIM2_IRQHandler [WEAK]
|
||||
EXPORT PKA_IRQHandler [WEAK]
|
||||
EXPORT I2C1_EV_IRQHandler [WEAK]
|
||||
EXPORT I2C1_ER_IRQHandler [WEAK]
|
||||
EXPORT I2C3_EV_IRQHandler [WEAK]
|
||||
EXPORT I2C3_ER_IRQHandler [WEAK]
|
||||
EXPORT SPI1_IRQHandler [WEAK]
|
||||
EXPORT SPI2_IRQHandler [WEAK]
|
||||
EXPORT USART1_IRQHandler [WEAK]
|
||||
EXPORT LPUART1_IRQHandler [WEAK]
|
||||
EXPORT SAI1_IRQHandler [WEAK]
|
||||
EXPORT TSC_IRQHandler [WEAK]
|
||||
EXPORT EXTI15_10_IRQHandler [WEAK]
|
||||
EXPORT RTC_Alarm_IRQHandler [WEAK]
|
||||
EXPORT CRS_IRQHandler [WEAK]
|
||||
EXPORT PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler [WEAK]
|
||||
EXPORT IPCC_C1_RX_IRQHandler [WEAK]
|
||||
EXPORT IPCC_C1_TX_IRQHandler [WEAK]
|
||||
EXPORT HSEM_IRQHandler [WEAK]
|
||||
EXPORT LPTIM1_IRQHandler [WEAK]
|
||||
EXPORT LPTIM2_IRQHandler [WEAK]
|
||||
EXPORT LCD_IRQHandler [WEAK]
|
||||
EXPORT QUADSPI_IRQHandler [WEAK]
|
||||
EXPORT AES1_IRQHandler [WEAK]
|
||||
EXPORT AES2_IRQHandler [WEAK]
|
||||
EXPORT RNG_IRQHandler [WEAK]
|
||||
EXPORT FPU_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Channel1_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Channel2_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Channel3_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Channel4_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Channel5_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Channel6_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Channel7_IRQHandler [WEAK]
|
||||
EXPORT DMAMUX1_OVR_IRQHandler [WEAK]
|
||||
|
||||
WWDG_IRQHandler
|
||||
PVD_PVM_IRQHandler
|
||||
TAMP_STAMP_LSECSS_IRQHandler
|
||||
RTC_WKUP_IRQHandler
|
||||
FLASH_IRQHandler
|
||||
RCC_IRQHandler
|
||||
EXTI0_IRQHandler
|
||||
EXTI1_IRQHandler
|
||||
EXTI2_IRQHandler
|
||||
EXTI3_IRQHandler
|
||||
EXTI4_IRQHandler
|
||||
DMA1_Channel1_IRQHandler
|
||||
DMA1_Channel2_IRQHandler
|
||||
DMA1_Channel3_IRQHandler
|
||||
DMA1_Channel4_IRQHandler
|
||||
DMA1_Channel5_IRQHandler
|
||||
DMA1_Channel6_IRQHandler
|
||||
DMA1_Channel7_IRQHandler
|
||||
ADC1_IRQHandler
|
||||
USB_HP_IRQHandler
|
||||
USB_LP_IRQHandler
|
||||
C2SEV_PWR_C2H_IRQHandler
|
||||
COMP_IRQHandler
|
||||
EXTI9_5_IRQHandler
|
||||
TIM1_BRK_IRQHandler
|
||||
TIM1_UP_TIM16_IRQHandler
|
||||
TIM1_TRG_COM_TIM17_IRQHandler
|
||||
TIM1_CC_IRQHandler
|
||||
TIM2_IRQHandler
|
||||
PKA_IRQHandler
|
||||
I2C1_EV_IRQHandler
|
||||
I2C1_ER_IRQHandler
|
||||
I2C3_EV_IRQHandler
|
||||
I2C3_ER_IRQHandler
|
||||
SPI1_IRQHandler
|
||||
SPI2_IRQHandler
|
||||
USART1_IRQHandler
|
||||
LPUART1_IRQHandler
|
||||
SAI1_IRQHandler
|
||||
TSC_IRQHandler
|
||||
EXTI15_10_IRQHandler
|
||||
RTC_Alarm_IRQHandler
|
||||
CRS_IRQHandler
|
||||
PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
|
||||
IPCC_C1_RX_IRQHandler
|
||||
IPCC_C1_TX_IRQHandler
|
||||
HSEM_IRQHandler
|
||||
LPTIM1_IRQHandler
|
||||
LPTIM2_IRQHandler
|
||||
LCD_IRQHandler
|
||||
QUADSPI_IRQHandler
|
||||
AES1_IRQHandler
|
||||
AES2_IRQHandler
|
||||
RNG_IRQHandler
|
||||
FPU_IRQHandler
|
||||
DMA2_Channel1_IRQHandler
|
||||
DMA2_Channel2_IRQHandler
|
||||
DMA2_Channel3_IRQHandler
|
||||
DMA2_Channel4_IRQHandler
|
||||
DMA2_Channel5_IRQHandler
|
||||
DMA2_Channel6_IRQHandler
|
||||
DMA2_Channel7_IRQHandler
|
||||
DMAMUX1_OVR_IRQHandler
|
||||
|
||||
B .
|
||||
|
||||
ENDP
|
||||
|
||||
ALIGN
|
||||
|
||||
;*******************************************************************************
|
||||
; User Stack and Heap initialization
|
||||
;*******************************************************************************
|
||||
IF :DEF:__MICROLIB
|
||||
|
||||
EXPORT __initial_sp
|
||||
EXPORT __heap_base
|
||||
EXPORT __heap_limit
|
||||
|
||||
ELSE
|
||||
|
||||
IMPORT __use_two_region_memory
|
||||
EXPORT __user_initial_stackheap
|
||||
|
||||
__user_initial_stackheap
|
||||
|
||||
LDR R0, = Heap_Mem
|
||||
LDR R1, =(Stack_Mem + Stack_Size)
|
||||
LDR R2, = (Heap_Mem + Heap_Size)
|
||||
LDR R3, = Stack_Mem
|
||||
BX LR
|
||||
|
||||
ALIGN
|
||||
|
||||
ENDIF
|
||||
|
||||
END
|
||||
|
||||
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
||||
|
|
@ -1,179 +0,0 @@
|
|||
/*
|
||||
******************************************************************************
|
||||
**
|
||||
** File : LinkerScript.ld
|
||||
**
|
||||
** Author : STM32CubeIDE
|
||||
**
|
||||
** Abstract : Linker script for STM32WB15xC Device
|
||||
** 320Kbytes FLASH
|
||||
** 48Kbytes RAM
|
||||
**
|
||||
** Set heap size, stack size and stack location according
|
||||
** to application requirements.
|
||||
**
|
||||
** Set memory bank area and size if external memory is used.
|
||||
**
|
||||
** Target : STMicroelectronics STM32
|
||||
**
|
||||
** Distribution: The file is distributed as is without any warranty
|
||||
** of any kind.
|
||||
**
|
||||
*****************************************************************************
|
||||
** @attention
|
||||
**
|
||||
** <h2><center>© Copyright (c) 2020 STMicroelectronics.
|
||||
** All rights reserved.</center></h2>
|
||||
**
|
||||
** This software component is licensed by ST under BSD 3-Clause license,
|
||||
** the "License"; You may not use this file except in compliance with the
|
||||
** License. You may obtain a copy of the License at:
|
||||
** opensource.org/licenses/BSD-3-Clause
|
||||
**
|
||||
*****************************************************************************
|
||||
*/
|
||||
|
||||
/* Entry Point */
|
||||
ENTRY(Reset_Handler)
|
||||
|
||||
/* Highest address of the user mode stack */
|
||||
_estack = 0x20003000; /* end of RAM */
|
||||
/* Generate a link error if heap and stack don't fit into RAM */
|
||||
_Min_Heap_Size = 0x400 ; /* required amount of heap */
|
||||
_Min_Stack_Size = 0x1000 ; /* required amount of stack */
|
||||
|
||||
/* Specify the memory areas */
|
||||
MEMORY
|
||||
{
|
||||
FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 110K
|
||||
RAM1 (xrw) : ORIGIN = 0x20000008, LENGTH = 0x2FF8
|
||||
RAM_SHARED (xrw) : ORIGIN = 0x20030000, LENGTH = 10K
|
||||
}
|
||||
|
||||
/* Define output sections */
|
||||
SECTIONS
|
||||
{
|
||||
/* The startup code goes first into FLASH */
|
||||
.isr_vector :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.isr_vector)) /* Startup code */
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
/* The program code and other data goes into FLASH */
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.text) /* .text sections (code) */
|
||||
*(.text*) /* .text* sections (code) */
|
||||
*(.glue_7) /* glue arm to thumb code */
|
||||
*(.glue_7t) /* glue thumb to arm code */
|
||||
*(.eh_frame)
|
||||
|
||||
KEEP (*(.init))
|
||||
KEEP (*(.fini))
|
||||
|
||||
. = ALIGN(4);
|
||||
_etext = .; /* define a global symbols at end of code */
|
||||
} >FLASH
|
||||
|
||||
/* Constant data goes into FLASH */
|
||||
.rodata :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.rodata) /* .rodata sections (constants, strings, etc.) */
|
||||
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
.ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
|
||||
.ARM : {
|
||||
__exidx_start = .;
|
||||
*(.ARM.exidx*)
|
||||
__exidx_end = .;
|
||||
} >FLASH
|
||||
|
||||
.preinit_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP (*(.preinit_array*))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
} >FLASH
|
||||
.init_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array*))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
} >FLASH
|
||||
.fini_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP (*(SORT(.fini_array.*)))
|
||||
KEEP (*(.fini_array*))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
} >FLASH
|
||||
|
||||
/* used by the startup to initialize data */
|
||||
_sidata = LOADADDR(.data);
|
||||
|
||||
/* Initialized data sections goes into RAM, load LMA copy after code */
|
||||
.data :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sdata = .; /* create a global symbol at data start */
|
||||
*(.data) /* .data sections */
|
||||
*(.data*) /* .data* sections */
|
||||
*(.RamFunc) /* .RamFunc sections */
|
||||
*(.RamFunc*) /* .RamFunc* sections */
|
||||
|
||||
. = ALIGN(4);
|
||||
_edata = .; /* define a global symbol at data end */
|
||||
} >RAM1 AT> FLASH
|
||||
|
||||
|
||||
/* Uninitialized data section */
|
||||
. = ALIGN(4);
|
||||
.bss :
|
||||
{
|
||||
/* This is used by the startup in order to initialize the .bss secion */
|
||||
_sbss = .; /* define a global symbol at bss start */
|
||||
__bss_start__ = _sbss;
|
||||
*(.bss)
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
|
||||
. = ALIGN(4);
|
||||
_ebss = .; /* define a global symbol at bss end */
|
||||
__bss_end__ = _ebss;
|
||||
} >RAM1
|
||||
|
||||
/* User_heap_stack section, used to check that there is enough RAM left */
|
||||
._user_heap_stack :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
PROVIDE ( end = . );
|
||||
PROVIDE ( _end = . );
|
||||
. = . + _Min_Heap_Size;
|
||||
. = . + _Min_Stack_Size;
|
||||
. = ALIGN(8);
|
||||
} >RAM1
|
||||
|
||||
|
||||
|
||||
/* Remove information from the standard libraries */
|
||||
/DISCARD/ :
|
||||
{
|
||||
libc.a ( * )
|
||||
libm.a ( * )
|
||||
libgcc.a ( * )
|
||||
}
|
||||
|
||||
.ARM.attributes 0 : { *(.ARM.attributes) }
|
||||
MAPPING_TABLE (NOLOAD) : { *(MAPPING_TABLE) } >RAM_SHARED
|
||||
MB_MEM1 (NOLOAD) : { *(MB_MEM1) } >RAM_SHARED
|
||||
MB_MEM2 (NOLOAD) : { _sMB_MEM2 = . ; *(MB_MEM2) ; _eMB_MEM2 = . ; } >RAM_SHARED
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -1,179 +0,0 @@
|
|||
/*
|
||||
******************************************************************************
|
||||
**
|
||||
** File : LinkerScript.ld
|
||||
**
|
||||
** Author : STM32CubeIDE
|
||||
**
|
||||
** Abstract : Linker script for STM32WB15xC Device
|
||||
** 320Kbytes FLASH
|
||||
** 48Kbytes RAM
|
||||
**
|
||||
** Set heap size, stack size and stack location according
|
||||
** to application requirements.
|
||||
**
|
||||
** Set memory bank area and size if external memory is used.
|
||||
**
|
||||
** Target : STMicroelectronics STM32
|
||||
**
|
||||
** Distribution: The file is distributed as is without any warranty
|
||||
** of any kind.
|
||||
**
|
||||
*****************************************************************************
|
||||
** @attention
|
||||
**
|
||||
** <h2><center>© Copyright (c) 2020 STMicroelectronics.
|
||||
** All rights reserved.</center></h2>
|
||||
**
|
||||
** This software component is licensed by ST under BSD 3-Clause license,
|
||||
** the "License"; You may not use this file except in compliance with the
|
||||
** License. You may obtain a copy of the License at:
|
||||
** opensource.org/licenses/BSD-3-Clause
|
||||
**
|
||||
*****************************************************************************
|
||||
*/
|
||||
|
||||
/* Entry Point */
|
||||
ENTRY(Reset_Handler)
|
||||
|
||||
/* Highest address of the user mode stack */
|
||||
_estack = 0x20003000; /* end of RAM */
|
||||
/* Generate a link error if heap and stack don't fit into RAM */
|
||||
_Min_Heap_Size = 0x400 ; /* required amount of heap */
|
||||
_Min_Stack_Size = 0x1000 ; /* required amount of stack */
|
||||
|
||||
/* Specify the memory areas */
|
||||
MEMORY
|
||||
{
|
||||
FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 110K
|
||||
RAM1 (xrw) : ORIGIN = 0x20000008, LENGTH = 0x2FF8
|
||||
RAM_SHARED (xrw) : ORIGIN = 0x20030000, LENGTH = 10K
|
||||
}
|
||||
|
||||
/* Define output sections */
|
||||
SECTIONS
|
||||
{
|
||||
/* The startup code goes first into FLASH */
|
||||
.isr_vector :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.isr_vector)) /* Startup code */
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
/* The program code and other data goes into FLASH */
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.text) /* .text sections (code) */
|
||||
*(.text*) /* .text* sections (code) */
|
||||
*(.glue_7) /* glue arm to thumb code */
|
||||
*(.glue_7t) /* glue thumb to arm code */
|
||||
*(.eh_frame)
|
||||
|
||||
KEEP (*(.init))
|
||||
KEEP (*(.fini))
|
||||
|
||||
. = ALIGN(4);
|
||||
_etext = .; /* define a global symbols at end of code */
|
||||
} >FLASH
|
||||
|
||||
/* Constant data goes into FLASH */
|
||||
.rodata :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.rodata) /* .rodata sections (constants, strings, etc.) */
|
||||
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
.ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
|
||||
.ARM : {
|
||||
__exidx_start = .;
|
||||
*(.ARM.exidx*)
|
||||
__exidx_end = .;
|
||||
} >FLASH
|
||||
|
||||
.preinit_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP (*(.preinit_array*))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
} >FLASH
|
||||
.init_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array*))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
} >FLASH
|
||||
.fini_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP (*(SORT(.fini_array.*)))
|
||||
KEEP (*(.fini_array*))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
} >FLASH
|
||||
|
||||
/* used by the startup to initialize data */
|
||||
_sidata = LOADADDR(.data);
|
||||
|
||||
/* Initialized data sections goes into RAM, load LMA copy after code */
|
||||
.data :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sdata = .; /* create a global symbol at data start */
|
||||
*(.data) /* .data sections */
|
||||
*(.data*) /* .data* sections */
|
||||
*(.RamFunc) /* .RamFunc sections */
|
||||
*(.RamFunc*) /* .RamFunc* sections */
|
||||
|
||||
. = ALIGN(4);
|
||||
_edata = .; /* define a global symbol at data end */
|
||||
} >RAM1 AT> FLASH
|
||||
|
||||
|
||||
/* Uninitialized data section */
|
||||
. = ALIGN(4);
|
||||
.bss :
|
||||
{
|
||||
/* This is used by the startup in order to initialize the .bss secion */
|
||||
_sbss = .; /* define a global symbol at bss start */
|
||||
__bss_start__ = _sbss;
|
||||
*(.bss)
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
|
||||
. = ALIGN(4);
|
||||
_ebss = .; /* define a global symbol at bss end */
|
||||
__bss_end__ = _ebss;
|
||||
} >RAM1
|
||||
|
||||
/* User_heap_stack section, used to check that there is enough RAM left */
|
||||
._user_heap_stack :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
PROVIDE ( end = . );
|
||||
PROVIDE ( _end = . );
|
||||
. = . + _Min_Heap_Size;
|
||||
. = . + _Min_Stack_Size;
|
||||
. = ALIGN(8);
|
||||
} >RAM1
|
||||
|
||||
|
||||
|
||||
/* Remove information from the standard libraries */
|
||||
/DISCARD/ :
|
||||
{
|
||||
libc.a ( * )
|
||||
libm.a ( * )
|
||||
libgcc.a ( * )
|
||||
}
|
||||
|
||||
.ARM.attributes 0 : { *(.ARM.attributes) }
|
||||
MAPPING_TABLE (NOLOAD) : { *(MAPPING_TABLE) } >RAM_SHARED
|
||||
MB_MEM1 (NOLOAD) : { *(MB_MEM1) } >RAM_SHARED
|
||||
MB_MEM2 (NOLOAD) : { _sMB_MEM2 = . ; *(MB_MEM2) ; _eMB_MEM2 = . ; } >RAM_SHARED
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -1,187 +0,0 @@
|
|||
/**
|
||||
*****************************************************************************
|
||||
**
|
||||
** File : stm32wb30xx_flash_cm4.ld
|
||||
**
|
||||
** Abstract : System Workbench Minimal System calls file
|
||||
**
|
||||
** For more information about which c-functions
|
||||
** need which of these lowlevel functions
|
||||
** please consult the Newlib libc-manual
|
||||
**
|
||||
** Environment : System Workbench for MCU
|
||||
**
|
||||
** Distribution: The file is distributed “as is,” without any warranty
|
||||
** of any kind.
|
||||
**
|
||||
*****************************************************************************
|
||||
**
|
||||
** <h2><center>© COPYRIGHT(c) 2019 Ac6</center></h2>
|
||||
**
|
||||
** Redistribution and use in source and binary forms, with or without modification,
|
||||
** are permitted provided that the following conditions are met:
|
||||
** 1. Redistributions of source code must retain the above copyright notice,
|
||||
** this list of conditions and the following disclaimer.
|
||||
** 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
** this list of conditions and the following disclaimer in the documentation
|
||||
** and/or other materials provided with the distribution.
|
||||
** 3. Neither the name of Ac6 nor the names of its contributors
|
||||
** may be used to endorse or promote products derived from this software
|
||||
** without specific prior written permission.
|
||||
**
|
||||
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
**
|
||||
*****************************************************************************
|
||||
*/
|
||||
|
||||
/* Entry Point */
|
||||
ENTRY(Reset_Handler)
|
||||
|
||||
/* Highest address of the user mode stack */
|
||||
_estack = 0x20008000; /* end of RAM */
|
||||
/* Generate a link error if heap and stack don't fit into RAM */
|
||||
_Min_Heap_Size = 0x400; /* required amount of heap */
|
||||
_Min_Stack_Size = 0x1000; /* required amount of stack */
|
||||
|
||||
/* Specify the memory areas */
|
||||
MEMORY
|
||||
{
|
||||
FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 256K
|
||||
RAM1 (xrw) : ORIGIN = 0x20000008, LENGTH = 0x7FF8
|
||||
RAM_SHARED (xrw) : ORIGIN = 0x20030000, LENGTH = 10K
|
||||
}
|
||||
|
||||
/* Define output sections */
|
||||
SECTIONS
|
||||
{
|
||||
/* The startup code goes first into FLASH */
|
||||
.isr_vector :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.isr_vector)) /* Startup code */
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
/* The program code and other data goes into FLASH */
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.text) /* .text sections (code) */
|
||||
*(.text*) /* .text* sections (code) */
|
||||
*(.glue_7) /* glue arm to thumb code */
|
||||
*(.glue_7t) /* glue thumb to arm code */
|
||||
*(.eh_frame)
|
||||
|
||||
KEEP (*(.init))
|
||||
KEEP (*(.fini))
|
||||
|
||||
. = ALIGN(4);
|
||||
_etext = .; /* define a global symbols at end of code */
|
||||
} >FLASH
|
||||
|
||||
/* Constant data goes into FLASH */
|
||||
.rodata :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.rodata) /* .rodata sections (constants, strings, etc.) */
|
||||
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
.ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
|
||||
.ARM : {
|
||||
__exidx_start = .;
|
||||
*(.ARM.exidx*)
|
||||
__exidx_end = .;
|
||||
} >FLASH
|
||||
|
||||
.preinit_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP (*(.preinit_array*))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
} >FLASH
|
||||
.init_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array*))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
} >FLASH
|
||||
.fini_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP (*(SORT(.fini_array.*)))
|
||||
KEEP (*(.fini_array*))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
} >FLASH
|
||||
|
||||
/* used by the startup to initialize data */
|
||||
_sidata = LOADADDR(.data);
|
||||
|
||||
/* Initialized data sections goes into RAM, load LMA copy after code */
|
||||
.data :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sdata = .; /* create a global symbol at data start */
|
||||
*(.data) /* .data sections */
|
||||
*(.data*) /* .data* sections */
|
||||
|
||||
. = ALIGN(4);
|
||||
_edata = .; /* define a global symbol at data end */
|
||||
} >RAM1 AT> FLASH
|
||||
|
||||
|
||||
/* Uninitialized data section */
|
||||
. = ALIGN(4);
|
||||
.bss :
|
||||
{
|
||||
/* This is used by the startup in order to initialize the .bss secion */
|
||||
_sbss = .; /* define a global symbol at bss start */
|
||||
__bss_start__ = _sbss;
|
||||
*(.bss)
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
|
||||
. = ALIGN(4);
|
||||
_ebss = .; /* define a global symbol at bss end */
|
||||
__bss_end__ = _ebss;
|
||||
} >RAM1
|
||||
|
||||
/* User_heap_stack section, used to check that there is enough RAM left */
|
||||
._user_heap_stack :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
PROVIDE ( end = . );
|
||||
PROVIDE ( _end = . );
|
||||
. = . + _Min_Heap_Size;
|
||||
. = . + _Min_Stack_Size;
|
||||
. = ALIGN(8);
|
||||
} >RAM1
|
||||
|
||||
|
||||
|
||||
/* Remove information from the standard libraries */
|
||||
/DISCARD/ :
|
||||
{
|
||||
libc.a ( * )
|
||||
libm.a ( * )
|
||||
libgcc.a ( * )
|
||||
}
|
||||
|
||||
.ARM.attributes 0 : { *(.ARM.attributes) }
|
||||
MAPPING_TABLE (NOLOAD) : { *(MAPPING_TABLE) } >RAM_SHARED
|
||||
MB_MEM1 (NOLOAD) : { *(MB_MEM1) } >RAM_SHARED
|
||||
MB_MEM2 (NOLOAD) : { _sMB_MEM2 = . ; *(MB_MEM2) ; _eMB_MEM2 = . ; } >RAM_SHARED
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -1,187 +0,0 @@
|
|||
/**
|
||||
*****************************************************************************
|
||||
**
|
||||
** File : stm32wb35xx_flash_cm4.ld
|
||||
**
|
||||
** Abstract : System Workbench Minimal System calls file
|
||||
**
|
||||
** For more information about which c-functions
|
||||
** need which of these lowlevel functions
|
||||
** please consult the Newlib libc-manual
|
||||
**
|
||||
** Environment : System Workbench for MCU
|
||||
**
|
||||
** Distribution: The file is distributed “as is,” without any warranty
|
||||
** of any kind.
|
||||
**
|
||||
*****************************************************************************
|
||||
**
|
||||
** <h2><center>© COPYRIGHT(c) 2019 Ac6</center></h2>
|
||||
**
|
||||
** Redistribution and use in source and binary forms, with or without modification,
|
||||
** are permitted provided that the following conditions are met:
|
||||
** 1. Redistributions of source code must retain the above copyright notice,
|
||||
** this list of conditions and the following disclaimer.
|
||||
** 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
** this list of conditions and the following disclaimer in the documentation
|
||||
** and/or other materials provided with the distribution.
|
||||
** 3. Neither the name of Ac6 nor the names of its contributors
|
||||
** may be used to endorse or promote products derived from this software
|
||||
** without specific prior written permission.
|
||||
**
|
||||
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
**
|
||||
*****************************************************************************
|
||||
*/
|
||||
|
||||
/* Entry Point */
|
||||
ENTRY(Reset_Handler)
|
||||
|
||||
/* Highest address of the user mode stack */
|
||||
_estack = 0x20008000; /* end of RAM */
|
||||
/* Generate a link error if heap and stack don't fit into RAM */
|
||||
_Min_Heap_Size = 0x400; /* required amount of heap */
|
||||
_Min_Stack_Size = 0x1000; /* required amount of stack */
|
||||
|
||||
/* Specify the memory areas */
|
||||
MEMORY
|
||||
{
|
||||
FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 256K
|
||||
RAM1 (xrw) : ORIGIN = 0x20000008, LENGTH = 0x7FF8
|
||||
RAM_SHARED (xrw) : ORIGIN = 0x20030000, LENGTH = 10K
|
||||
}
|
||||
|
||||
/* Define output sections */
|
||||
SECTIONS
|
||||
{
|
||||
/* The startup code goes first into FLASH */
|
||||
.isr_vector :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.isr_vector)) /* Startup code */
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
/* The program code and other data goes into FLASH */
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.text) /* .text sections (code) */
|
||||
*(.text*) /* .text* sections (code) */
|
||||
*(.glue_7) /* glue arm to thumb code */
|
||||
*(.glue_7t) /* glue thumb to arm code */
|
||||
*(.eh_frame)
|
||||
|
||||
KEEP (*(.init))
|
||||
KEEP (*(.fini))
|
||||
|
||||
. = ALIGN(4);
|
||||
_etext = .; /* define a global symbols at end of code */
|
||||
} >FLASH
|
||||
|
||||
/* Constant data goes into FLASH */
|
||||
.rodata :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.rodata) /* .rodata sections (constants, strings, etc.) */
|
||||
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
.ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
|
||||
.ARM : {
|
||||
__exidx_start = .;
|
||||
*(.ARM.exidx*)
|
||||
__exidx_end = .;
|
||||
} >FLASH
|
||||
|
||||
.preinit_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP (*(.preinit_array*))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
} >FLASH
|
||||
.init_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array*))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
} >FLASH
|
||||
.fini_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP (*(SORT(.fini_array.*)))
|
||||
KEEP (*(.fini_array*))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
} >FLASH
|
||||
|
||||
/* used by the startup to initialize data */
|
||||
_sidata = LOADADDR(.data);
|
||||
|
||||
/* Initialized data sections goes into RAM, load LMA copy after code */
|
||||
.data :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sdata = .; /* create a global symbol at data start */
|
||||
*(.data) /* .data sections */
|
||||
*(.data*) /* .data* sections */
|
||||
|
||||
. = ALIGN(4);
|
||||
_edata = .; /* define a global symbol at data end */
|
||||
} >RAM1 AT> FLASH
|
||||
|
||||
|
||||
/* Uninitialized data section */
|
||||
. = ALIGN(4);
|
||||
.bss :
|
||||
{
|
||||
/* This is used by the startup in order to initialize the .bss secion */
|
||||
_sbss = .; /* define a global symbol at bss start */
|
||||
__bss_start__ = _sbss;
|
||||
*(.bss)
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
|
||||
. = ALIGN(4);
|
||||
_ebss = .; /* define a global symbol at bss end */
|
||||
__bss_end__ = _ebss;
|
||||
} >RAM1
|
||||
|
||||
/* User_heap_stack section, used to check that there is enough RAM left */
|
||||
._user_heap_stack :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
PROVIDE ( end = . );
|
||||
PROVIDE ( _end = . );
|
||||
. = . + _Min_Heap_Size;
|
||||
. = . + _Min_Stack_Size;
|
||||
. = ALIGN(8);
|
||||
} >RAM1
|
||||
|
||||
|
||||
|
||||
/* Remove information from the standard libraries */
|
||||
/DISCARD/ :
|
||||
{
|
||||
libc.a ( * )
|
||||
libm.a ( * )
|
||||
libgcc.a ( * )
|
||||
}
|
||||
|
||||
.ARM.attributes 0 : { *(.ARM.attributes) }
|
||||
MAPPING_TABLE (NOLOAD) : { *(MAPPING_TABLE) } >RAM_SHARED
|
||||
MB_MEM1 (NOLOAD) : { *(MB_MEM1) } >RAM_SHARED
|
||||
MB_MEM2 (NOLOAD) : { _sMB_MEM2 = . ; *(MB_MEM2) ; _eMB_MEM2 = . ; } >RAM_SHARED
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -1,187 +0,0 @@
|
|||
/**
|
||||
*****************************************************************************
|
||||
**
|
||||
** File : stm32wb50xx_flash_cm4.ld
|
||||
**
|
||||
** Abstract : System Workbench Minimal System calls file
|
||||
**
|
||||
** For more information about which c-functions
|
||||
** need which of these lowlevel functions
|
||||
** please consult the Newlib libc-manual
|
||||
**
|
||||
** Environment : System Workbench for MCU
|
||||
**
|
||||
** Distribution: The file is distributed “as is,” without any warranty
|
||||
** of any kind.
|
||||
**
|
||||
*****************************************************************************
|
||||
**
|
||||
** <h2><center>© COPYRIGHT(c) 2019 Ac6</center></h2>
|
||||
**
|
||||
** Redistribution and use in source and binary forms, with or without modification,
|
||||
** are permitted provided that the following conditions are met:
|
||||
** 1. Redistributions of source code must retain the above copyright notice,
|
||||
** this list of conditions and the following disclaimer.
|
||||
** 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
** this list of conditions and the following disclaimer in the documentation
|
||||
** and/or other materials provided with the distribution.
|
||||
** 3. Neither the name of Ac6 nor the names of its contributors
|
||||
** may be used to endorse or promote products derived from this software
|
||||
** without specific prior written permission.
|
||||
**
|
||||
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
**
|
||||
*****************************************************************************
|
||||
*/
|
||||
|
||||
/* Entry Point */
|
||||
ENTRY(Reset_Handler)
|
||||
|
||||
/* Highest address of the user mode stack */
|
||||
_estack = 0x20010000; /* end of RAM */
|
||||
/* Generate a link error if heap and stack don't fit into RAM */
|
||||
_Min_Heap_Size = 0x400; /* required amount of heap */
|
||||
_Min_Stack_Size = 0x1000; /* required amount of stack */
|
||||
|
||||
/* Specify the memory areas */
|
||||
MEMORY
|
||||
{
|
||||
FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 512K
|
||||
RAM1 (xrw) : ORIGIN = 0x20000008, LENGTH = 0xFFF8
|
||||
RAM_SHARED (xrw) : ORIGIN = 0x20030000, LENGTH = 10K
|
||||
}
|
||||
|
||||
/* Define output sections */
|
||||
SECTIONS
|
||||
{
|
||||
/* The startup code goes first into FLASH */
|
||||
.isr_vector :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.isr_vector)) /* Startup code */
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
/* The program code and other data goes into FLASH */
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.text) /* .text sections (code) */
|
||||
*(.text*) /* .text* sections (code) */
|
||||
*(.glue_7) /* glue arm to thumb code */
|
||||
*(.glue_7t) /* glue thumb to arm code */
|
||||
*(.eh_frame)
|
||||
|
||||
KEEP (*(.init))
|
||||
KEEP (*(.fini))
|
||||
|
||||
. = ALIGN(4);
|
||||
_etext = .; /* define a global symbols at end of code */
|
||||
} >FLASH
|
||||
|
||||
/* Constant data goes into FLASH */
|
||||
.rodata :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.rodata) /* .rodata sections (constants, strings, etc.) */
|
||||
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
.ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
|
||||
.ARM : {
|
||||
__exidx_start = .;
|
||||
*(.ARM.exidx*)
|
||||
__exidx_end = .;
|
||||
} >FLASH
|
||||
|
||||
.preinit_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP (*(.preinit_array*))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
} >FLASH
|
||||
.init_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array*))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
} >FLASH
|
||||
.fini_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP (*(SORT(.fini_array.*)))
|
||||
KEEP (*(.fini_array*))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
} >FLASH
|
||||
|
||||
/* used by the startup to initialize data */
|
||||
_sidata = LOADADDR(.data);
|
||||
|
||||
/* Initialized data sections goes into RAM, load LMA copy after code */
|
||||
.data :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sdata = .; /* create a global symbol at data start */
|
||||
*(.data) /* .data sections */
|
||||
*(.data*) /* .data* sections */
|
||||
|
||||
. = ALIGN(4);
|
||||
_edata = .; /* define a global symbol at data end */
|
||||
} >RAM1 AT> FLASH
|
||||
|
||||
|
||||
/* Uninitialized data section */
|
||||
. = ALIGN(4);
|
||||
.bss :
|
||||
{
|
||||
/* This is used by the startup in order to initialize the .bss secion */
|
||||
_sbss = .; /* define a global symbol at bss start */
|
||||
__bss_start__ = _sbss;
|
||||
*(.bss)
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
|
||||
. = ALIGN(4);
|
||||
_ebss = .; /* define a global symbol at bss end */
|
||||
__bss_end__ = _ebss;
|
||||
} >RAM1
|
||||
|
||||
/* User_heap_stack section, used to check that there is enough RAM left */
|
||||
._user_heap_stack :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
PROVIDE ( end = . );
|
||||
PROVIDE ( _end = . );
|
||||
. = . + _Min_Heap_Size;
|
||||
. = . + _Min_Stack_Size;
|
||||
. = ALIGN(8);
|
||||
} >RAM1
|
||||
|
||||
|
||||
|
||||
/* Remove information from the standard libraries */
|
||||
/DISCARD/ :
|
||||
{
|
||||
libc.a ( * )
|
||||
libm.a ( * )
|
||||
libgcc.a ( * )
|
||||
}
|
||||
|
||||
.ARM.attributes 0 : { *(.ARM.attributes) }
|
||||
MAPPING_TABLE (NOLOAD) : { *(MAPPING_TABLE) } >RAM_SHARED
|
||||
MB_MEM1 (NOLOAD) : { *(MB_MEM1) } >RAM_SHARED
|
||||
MB_MEM2 (NOLOAD) : { _sMB_MEM2 = . ; *(MB_MEM2) ; _eMB_MEM2 = . ; } >RAM_SHARED
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -1,187 +0,0 @@
|
|||
/**
|
||||
*****************************************************************************
|
||||
**
|
||||
** File : stm32wb55xx_flash_cm4.ld
|
||||
**
|
||||
** Abstract : System Workbench Minimal System calls file
|
||||
**
|
||||
** For more information about which c-functions
|
||||
** need which of these lowlevel functions
|
||||
** please consult the Newlib libc-manual
|
||||
**
|
||||
** Environment : System Workbench for MCU
|
||||
**
|
||||
** Distribution: The file is distributed “as is,” without any warranty
|
||||
** of any kind.
|
||||
**
|
||||
*****************************************************************************
|
||||
**
|
||||
** <h2><center>© COPYRIGHT(c) 2019 Ac6</center></h2>
|
||||
**
|
||||
** Redistribution and use in source and binary forms, with or without modification,
|
||||
** are permitted provided that the following conditions are met:
|
||||
** 1. Redistributions of source code must retain the above copyright notice,
|
||||
** this list of conditions and the following disclaimer.
|
||||
** 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
** this list of conditions and the following disclaimer in the documentation
|
||||
** and/or other materials provided with the distribution.
|
||||
** 3. Neither the name of Ac6 nor the names of its contributors
|
||||
** may be used to endorse or promote products derived from this software
|
||||
** without specific prior written permission.
|
||||
**
|
||||
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
**
|
||||
*****************************************************************************
|
||||
*/
|
||||
|
||||
/* Entry Point */
|
||||
ENTRY(Reset_Handler)
|
||||
|
||||
/* Highest address of the user mode stack */
|
||||
_estack = 0x20030000; /* end of RAM */
|
||||
/* Generate a link error if heap and stack don't fit into RAM */
|
||||
_Min_Heap_Size = 0x400; /* required amount of heap */
|
||||
_Min_Stack_Size = 0x1000; /* required amount of stack */
|
||||
|
||||
/* Specify the memory areas */
|
||||
MEMORY
|
||||
{
|
||||
FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 512K
|
||||
RAM1 (xrw) : ORIGIN = 0x20000008, LENGTH = 0x2FFF8
|
||||
RAM_SHARED (xrw) : ORIGIN = 0x20030000, LENGTH = 10K
|
||||
}
|
||||
|
||||
/* Define output sections */
|
||||
SECTIONS
|
||||
{
|
||||
/* The startup code goes first into FLASH */
|
||||
.isr_vector :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.isr_vector)) /* Startup code */
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
/* The program code and other data goes into FLASH */
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.text) /* .text sections (code) */
|
||||
*(.text*) /* .text* sections (code) */
|
||||
*(.glue_7) /* glue arm to thumb code */
|
||||
*(.glue_7t) /* glue thumb to arm code */
|
||||
*(.eh_frame)
|
||||
|
||||
KEEP (*(.init))
|
||||
KEEP (*(.fini))
|
||||
|
||||
. = ALIGN(4);
|
||||
_etext = .; /* define a global symbols at end of code */
|
||||
} >FLASH
|
||||
|
||||
/* Constant data goes into FLASH */
|
||||
.rodata :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.rodata) /* .rodata sections (constants, strings, etc.) */
|
||||
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
.ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
|
||||
.ARM : {
|
||||
__exidx_start = .;
|
||||
*(.ARM.exidx*)
|
||||
__exidx_end = .;
|
||||
} >FLASH
|
||||
|
||||
.preinit_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP (*(.preinit_array*))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
} >FLASH
|
||||
.init_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array*))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
} >FLASH
|
||||
.fini_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP (*(SORT(.fini_array.*)))
|
||||
KEEP (*(.fini_array*))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
} >FLASH
|
||||
|
||||
/* used by the startup to initialize data */
|
||||
_sidata = LOADADDR(.data);
|
||||
|
||||
/* Initialized data sections goes into RAM, load LMA copy after code */
|
||||
.data :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sdata = .; /* create a global symbol at data start */
|
||||
*(.data) /* .data sections */
|
||||
*(.data*) /* .data* sections */
|
||||
|
||||
. = ALIGN(4);
|
||||
_edata = .; /* define a global symbol at data end */
|
||||
} >RAM1 AT> FLASH
|
||||
|
||||
|
||||
/* Uninitialized data section */
|
||||
. = ALIGN(4);
|
||||
.bss :
|
||||
{
|
||||
/* This is used by the startup in order to initialize the .bss secion */
|
||||
_sbss = .; /* define a global symbol at bss start */
|
||||
__bss_start__ = _sbss;
|
||||
*(.bss)
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
|
||||
. = ALIGN(4);
|
||||
_ebss = .; /* define a global symbol at bss end */
|
||||
__bss_end__ = _ebss;
|
||||
} >RAM1
|
||||
|
||||
/* User_heap_stack section, used to check that there is enough RAM left */
|
||||
._user_heap_stack :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
PROVIDE ( end = . );
|
||||
PROVIDE ( _end = . );
|
||||
. = . + _Min_Heap_Size;
|
||||
. = . + _Min_Stack_Size;
|
||||
. = ALIGN(8);
|
||||
} >RAM1
|
||||
|
||||
|
||||
|
||||
/* Remove information from the standard libraries */
|
||||
/DISCARD/ :
|
||||
{
|
||||
libc.a ( * )
|
||||
libm.a ( * )
|
||||
libgcc.a ( * )
|
||||
}
|
||||
|
||||
.ARM.attributes 0 : { *(.ARM.attributes) }
|
||||
MAPPING_TABLE (NOLOAD) : { *(MAPPING_TABLE) } >RAM_SHARED
|
||||
MB_MEM1 (NOLOAD) : { *(MB_MEM1) } >RAM_SHARED
|
||||
MB_MEM2 (NOLOAD) : { _sMB_MEM2 = . ; *(MB_MEM2) ; _eMB_MEM2 = . ; } >RAM_SHARED
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -1,187 +0,0 @@
|
|||
/**
|
||||
*****************************************************************************
|
||||
**
|
||||
** File : stm32wb5mxx_flash_cm4.ld
|
||||
**
|
||||
** Abstract : System Workbench Minimal System calls file
|
||||
**
|
||||
** For more information about which c-functions
|
||||
** need which of these lowlevel functions
|
||||
** please consult the Newlib libc-manual
|
||||
**
|
||||
** Environment : System Workbench for MCU
|
||||
**
|
||||
** Distribution: The file is distributed “as is,” without any warranty
|
||||
** of any kind.
|
||||
**
|
||||
*****************************************************************************
|
||||
**
|
||||
** <h2><center>© COPYRIGHT(c) 2019 Ac6</center></h2>
|
||||
**
|
||||
** Redistribution and use in source and binary forms, with or without modification,
|
||||
** are permitted provided that the following conditions are met:
|
||||
** 1. Redistributions of source code must retain the above copyright notice,
|
||||
** this list of conditions and the following disclaimer.
|
||||
** 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
** this list of conditions and the following disclaimer in the documentation
|
||||
** and/or other materials provided with the distribution.
|
||||
** 3. Neither the name of Ac6 nor the names of its contributors
|
||||
** may be used to endorse or promote products derived from this software
|
||||
** without specific prior written permission.
|
||||
**
|
||||
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
**
|
||||
*****************************************************************************
|
||||
*/
|
||||
|
||||
/* Entry Point */
|
||||
ENTRY(Reset_Handler)
|
||||
|
||||
/* Highest address of the user mode stack */
|
||||
_estack = 0x20030000; /* end of RAM */
|
||||
/* Generate a link error if heap and stack don't fit into RAM */
|
||||
_Min_Heap_Size = 0x400; /* required amount of heap */
|
||||
_Min_Stack_Size = 0x1000; /* required amount of stack */
|
||||
|
||||
/* Specify the memory areas */
|
||||
MEMORY
|
||||
{
|
||||
FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 512K
|
||||
RAM1 (xrw) : ORIGIN = 0x20000008, LENGTH = 0x2FFF8
|
||||
RAM_SHARED (xrw) : ORIGIN = 0x20030000, LENGTH = 10K
|
||||
}
|
||||
|
||||
/* Define output sections */
|
||||
SECTIONS
|
||||
{
|
||||
/* The startup code goes first into FLASH */
|
||||
.isr_vector :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.isr_vector)) /* Startup code */
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
/* The program code and other data goes into FLASH */
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.text) /* .text sections (code) */
|
||||
*(.text*) /* .text* sections (code) */
|
||||
*(.glue_7) /* glue arm to thumb code */
|
||||
*(.glue_7t) /* glue thumb to arm code */
|
||||
*(.eh_frame)
|
||||
|
||||
KEEP (*(.init))
|
||||
KEEP (*(.fini))
|
||||
|
||||
. = ALIGN(4);
|
||||
_etext = .; /* define a global symbols at end of code */
|
||||
} >FLASH
|
||||
|
||||
/* Constant data goes into FLASH */
|
||||
.rodata :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.rodata) /* .rodata sections (constants, strings, etc.) */
|
||||
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
.ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
|
||||
.ARM : {
|
||||
__exidx_start = .;
|
||||
*(.ARM.exidx*)
|
||||
__exidx_end = .;
|
||||
} >FLASH
|
||||
|
||||
.preinit_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP (*(.preinit_array*))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
} >FLASH
|
||||
.init_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array*))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
} >FLASH
|
||||
.fini_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP (*(SORT(.fini_array.*)))
|
||||
KEEP (*(.fini_array*))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
} >FLASH
|
||||
|
||||
/* used by the startup to initialize data */
|
||||
_sidata = LOADADDR(.data);
|
||||
|
||||
/* Initialized data sections goes into RAM, load LMA copy after code */
|
||||
.data :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sdata = .; /* create a global symbol at data start */
|
||||
*(.data) /* .data sections */
|
||||
*(.data*) /* .data* sections */
|
||||
|
||||
. = ALIGN(4);
|
||||
_edata = .; /* define a global symbol at data end */
|
||||
} >RAM1 AT> FLASH
|
||||
|
||||
|
||||
/* Uninitialized data section */
|
||||
. = ALIGN(4);
|
||||
.bss :
|
||||
{
|
||||
/* This is used by the startup in order to initialize the .bss secion */
|
||||
_sbss = .; /* define a global symbol at bss start */
|
||||
__bss_start__ = _sbss;
|
||||
*(.bss)
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
|
||||
. = ALIGN(4);
|
||||
_ebss = .; /* define a global symbol at bss end */
|
||||
__bss_end__ = _ebss;
|
||||
} >RAM1
|
||||
|
||||
/* User_heap_stack section, used to check that there is enough RAM left */
|
||||
._user_heap_stack :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
PROVIDE ( end = . );
|
||||
PROVIDE ( _end = . );
|
||||
. = . + _Min_Heap_Size;
|
||||
. = . + _Min_Stack_Size;
|
||||
. = ALIGN(8);
|
||||
} >RAM1
|
||||
|
||||
|
||||
|
||||
/* Remove information from the standard libraries */
|
||||
/DISCARD/ :
|
||||
{
|
||||
libc.a ( * )
|
||||
libm.a ( * )
|
||||
libgcc.a ( * )
|
||||
}
|
||||
|
||||
.ARM.attributes 0 : { *(.ARM.attributes) }
|
||||
MAPPING_TABLE (NOLOAD) : { *(MAPPING_TABLE) } >RAM_SHARED
|
||||
MB_MEM1 (NOLOAD) : { *(MB_MEM1) } >RAM_SHARED
|
||||
MB_MEM2 (NOLOAD) : { _sMB_MEM2 = . ; *(MB_MEM2) ; _eMB_MEM2 = . ; } >RAM_SHARED
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -1,387 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file startup_stm32wb10xx_cm4.s
|
||||
* @author MCD Application Team
|
||||
* @brief STM32WB10xx devices vector table GCC toolchain.
|
||||
* This module performs:
|
||||
* - Set the initial SP
|
||||
* - Set the initial PC == Reset_Handler,
|
||||
* - Set the vector table entries with the exceptions ISR address
|
||||
* - Branches to main in the C library (which eventually
|
||||
* calls main()).
|
||||
* After Reset the Cortex-M4 processor is in Thread mode,
|
||||
* priority is Privileged, and the Stack is set to Main.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2019-2021 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
.syntax unified
|
||||
.cpu cortex-m4
|
||||
.fpu softvfp
|
||||
.thumb
|
||||
|
||||
.global g_pfnVectors
|
||||
.global Default_Handler
|
||||
|
||||
/* start address for the initialization values of the .data section.
|
||||
defined in linker script */
|
||||
.word _sidata
|
||||
/* start address for the .data section. defined in linker script */
|
||||
.word _sdata
|
||||
/* end address for the .data section. defined in linker script */
|
||||
.word _edata
|
||||
/* start address for the .bss section. defined in linker script */
|
||||
.word _sbss
|
||||
/* end address for the .bss section. defined in linker script */
|
||||
.word _ebss
|
||||
/* start address for the .MB_MEM2 section. defined in linker script */
|
||||
.word _sMB_MEM2
|
||||
/* end address for the .MB_MEM2 section. defined in linker script */
|
||||
.word _eMB_MEM2
|
||||
|
||||
/* INIT_BSS macro is used to fill the specified region [start : end] with zeros */
|
||||
.macro INIT_BSS start, end
|
||||
ldr r0, =\start
|
||||
ldr r1, =\end
|
||||
movs r3, #0
|
||||
bl LoopFillZerobss
|
||||
.endm
|
||||
|
||||
/* INIT_DATA macro is used to copy data in the region [start : end] starting from 'src' */
|
||||
.macro INIT_DATA start, end, src
|
||||
ldr r0, =\start
|
||||
ldr r1, =\end
|
||||
ldr r2, =\src
|
||||
movs r3, #0
|
||||
bl LoopCopyDataInit
|
||||
.endm
|
||||
|
||||
.section .text.data_initializers
|
||||
CopyDataInit:
|
||||
ldr r4, [r2, r3]
|
||||
str r4, [r0, r3]
|
||||
adds r3, r3, #4
|
||||
|
||||
LoopCopyDataInit:
|
||||
adds r4, r0, r3
|
||||
cmp r4, r1
|
||||
bcc CopyDataInit
|
||||
bx lr
|
||||
|
||||
FillZerobss:
|
||||
str r3, [r0]
|
||||
adds r0, r0, #4
|
||||
|
||||
LoopFillZerobss:
|
||||
cmp r0, r1
|
||||
bcc FillZerobss
|
||||
bx lr
|
||||
|
||||
.section .text.Reset_Handler
|
||||
.weak Reset_Handler
|
||||
.type Reset_Handler, %function
|
||||
Reset_Handler:
|
||||
ldr r0, =_estack
|
||||
mov sp, r0 /* set stack pointer */
|
||||
/* Call the clock system intitialization function.*/
|
||||
bl SystemInit
|
||||
|
||||
/* Copy the data segment initializers from flash to SRAM */
|
||||
INIT_DATA _sdata, _edata, _sidata
|
||||
|
||||
/* Zero fill the bss segments. */
|
||||
INIT_BSS _sbss, _ebss
|
||||
INIT_BSS _sMB_MEM2, _eMB_MEM2
|
||||
|
||||
/* Call static constructors */
|
||||
bl __libc_init_array
|
||||
/* Call the application s entry point.*/
|
||||
bl entry
|
||||
|
||||
LoopForever:
|
||||
b LoopForever
|
||||
|
||||
.size Reset_Handler, .-Reset_Handler
|
||||
|
||||
/**
|
||||
* @brief This is the code that gets called when the processor receives an
|
||||
* unexpected interrupt. This simply enters an infinite loop, preserving
|
||||
* the system state for examination by a debugger.
|
||||
*
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
.section .text.Default_Handler,"ax",%progbits
|
||||
Default_Handler:
|
||||
Infinite_Loop:
|
||||
b Infinite_Loop
|
||||
.size Default_Handler, .-Default_Handler
|
||||
/******************************************************************************
|
||||
*
|
||||
* The minimal vector table for a Cortex-M4. Note that the proper constructs
|
||||
* must be placed on this to ensure that it ends up at physical address
|
||||
* 0x0000.0000.
|
||||
*
|
||||
******************************************************************************/
|
||||
.section .isr_vector,"a",%progbits
|
||||
.type g_pfnVectors, %object
|
||||
.size g_pfnVectors, .-g_pfnVectors
|
||||
|
||||
|
||||
g_pfnVectors:
|
||||
.word _estack
|
||||
.word Reset_Handler
|
||||
.word NMI_Handler
|
||||
.word HardFault_Handler
|
||||
.word MemManage_Handler
|
||||
.word BusFault_Handler
|
||||
.word UsageFault_Handler
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word SVC_Handler
|
||||
.word DebugMon_Handler
|
||||
.word 0
|
||||
.word PendSV_Handler
|
||||
.word SysTick_Handler
|
||||
.word WWDG_IRQHandler
|
||||
.word PVD_PVM_IRQHandler
|
||||
.word TAMP_STAMP_LSECSS_IRQHandler
|
||||
.word RTC_WKUP_IRQHandler
|
||||
.word FLASH_IRQHandler
|
||||
.word RCC_IRQHandler
|
||||
.word EXTI0_IRQHandler
|
||||
.word EXTI1_IRQHandler
|
||||
.word EXTI2_IRQHandler
|
||||
.word EXTI3_IRQHandler
|
||||
.word EXTI4_IRQHandler
|
||||
.word DMA1_Channel1_IRQHandler
|
||||
.word DMA1_Channel2_IRQHandler
|
||||
.word DMA1_Channel3_IRQHandler
|
||||
.word DMA1_Channel4_IRQHandler
|
||||
.word DMA1_Channel5_IRQHandler
|
||||
.word DMA1_Channel6_IRQHandler
|
||||
.word DMA1_Channel7_IRQHandler
|
||||
.word ADC1_IRQHandler
|
||||
.word 0
|
||||
.word 0
|
||||
.word C2SEV_PWR_C2H_IRQHandler
|
||||
.word 0
|
||||
.word EXTI9_5_IRQHandler
|
||||
.word TIM1_BRK_IRQHandler
|
||||
.word TIM1_UP_IRQHandler
|
||||
.word TIM1_TRG_COM_IRQHandler
|
||||
.word TIM1_CC_IRQHandler
|
||||
.word TIM2_IRQHandler
|
||||
.word PKA_IRQHandler
|
||||
.word I2C1_EV_IRQHandler
|
||||
.word I2C1_ER_IRQHandler
|
||||
.word 0
|
||||
.word 0
|
||||
.word SPI1_IRQHandler
|
||||
.word 0
|
||||
.word USART1_IRQHandler
|
||||
.word 0
|
||||
.word 0
|
||||
.word TSC_IRQHandler
|
||||
.word EXTI15_10_IRQHandler
|
||||
.word RTC_Alarm_IRQHandler
|
||||
.word 0
|
||||
.word PWR_SOTF_BLEACT_RFPHASE_IRQHandler
|
||||
.word IPCC_C1_RX_IRQHandler
|
||||
.word IPCC_C1_TX_IRQHandler
|
||||
.word HSEM_IRQHandler
|
||||
.word LPTIM1_IRQHandler
|
||||
.word LPTIM2_IRQHandler
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word AES2_IRQHandler
|
||||
.word RNG_IRQHandler
|
||||
.word FPU_IRQHandler
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word DMAMUX1_OVR_IRQHandler
|
||||
|
||||
/*******************************************************************************
|
||||
*
|
||||
* Provide weak aliases for each Exception handler to the Default_Handler.
|
||||
* As they are weak aliases, any function with the same name will override
|
||||
* this definition.
|
||||
*
|
||||
*******************************************************************************/
|
||||
.weak NMI_Handler
|
||||
.thumb_set NMI_Handler,Default_Handler
|
||||
|
||||
.weak HardFault_Handler
|
||||
.thumb_set HardFault_Handler,Default_Handler
|
||||
|
||||
.weak MemManage_Handler
|
||||
.thumb_set MemManage_Handler,Default_Handler
|
||||
|
||||
.weak BusFault_Handler
|
||||
.thumb_set BusFault_Handler,Default_Handler
|
||||
|
||||
.weak UsageFault_Handler
|
||||
.thumb_set UsageFault_Handler,Default_Handler
|
||||
|
||||
.weak SVC_Handler
|
||||
.thumb_set SVC_Handler,Default_Handler
|
||||
|
||||
.weak DebugMon_Handler
|
||||
.thumb_set DebugMon_Handler,Default_Handler
|
||||
|
||||
.weak PendSV_Handler
|
||||
.thumb_set PendSV_Handler,Default_Handler
|
||||
|
||||
.weak SysTick_Handler
|
||||
.thumb_set SysTick_Handler,Default_Handler
|
||||
|
||||
.weak WWDG_IRQHandler
|
||||
.thumb_set WWDG_IRQHandler,Default_Handler
|
||||
|
||||
.weak PVD_PVM_IRQHandler
|
||||
.thumb_set PVD_PVM_IRQHandler,Default_Handler
|
||||
|
||||
.weak TAMP_STAMP_LSECSS_IRQHandler
|
||||
.thumb_set TAMP_STAMP_LSECSS_IRQHandler,Default_Handler
|
||||
|
||||
.weak RTC_WKUP_IRQHandler
|
||||
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
|
||||
|
||||
.weak FLASH_IRQHandler
|
||||
.thumb_set FLASH_IRQHandler,Default_Handler
|
||||
|
||||
.weak RCC_IRQHandler
|
||||
.thumb_set RCC_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI0_IRQHandler
|
||||
.thumb_set EXTI0_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI1_IRQHandler
|
||||
.thumb_set EXTI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI2_IRQHandler
|
||||
.thumb_set EXTI2_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI3_IRQHandler
|
||||
.thumb_set EXTI3_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI4_IRQHandler
|
||||
.thumb_set EXTI4_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel1_IRQHandler
|
||||
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel2_IRQHandler
|
||||
.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel3_IRQHandler
|
||||
.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel4_IRQHandler
|
||||
.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel5_IRQHandler
|
||||
.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel6_IRQHandler
|
||||
.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel7_IRQHandler
|
||||
.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
|
||||
|
||||
.weak ADC1_IRQHandler
|
||||
.thumb_set ADC1_IRQHandler,Default_Handler
|
||||
|
||||
.weak C2SEV_PWR_C2H_IRQHandler
|
||||
.thumb_set C2SEV_PWR_C2H_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI9_5_IRQHandler
|
||||
.thumb_set EXTI9_5_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_BRK_IRQHandler
|
||||
.thumb_set TIM1_BRK_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_UP_IRQHandler
|
||||
.thumb_set TIM1_UP_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_TRG_COM_IRQHandler
|
||||
.thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_CC_IRQHandler
|
||||
.thumb_set TIM1_CC_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM2_IRQHandler
|
||||
.thumb_set TIM2_IRQHandler,Default_Handler
|
||||
|
||||
.weak PKA_IRQHandler
|
||||
.thumb_set PKA_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C1_EV_IRQHandler
|
||||
.thumb_set I2C1_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C1_ER_IRQHandler
|
||||
.thumb_set I2C1_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI1_IRQHandler
|
||||
.thumb_set SPI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART1_IRQHandler
|
||||
.thumb_set USART1_IRQHandler,Default_Handler
|
||||
|
||||
.weak TSC_IRQHandler
|
||||
.thumb_set TSC_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI15_10_IRQHandler
|
||||
.thumb_set EXTI15_10_IRQHandler,Default_Handler
|
||||
|
||||
.weak RTC_Alarm_IRQHandler
|
||||
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
|
||||
|
||||
.weak PWR_SOTF_BLEACT_RFPHASE_IRQHandler
|
||||
.thumb_set PWR_SOTF_BLEACT_RFPHASE_IRQHandler,Default_Handler
|
||||
|
||||
.weak IPCC_C1_RX_IRQHandler
|
||||
.thumb_set IPCC_C1_RX_IRQHandler,Default_Handler
|
||||
|
||||
.weak IPCC_C1_TX_IRQHandler
|
||||
.thumb_set IPCC_C1_TX_IRQHandler,Default_Handler
|
||||
|
||||
.weak HSEM_IRQHandler
|
||||
.thumb_set HSEM_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPTIM1_IRQHandler
|
||||
.thumb_set LPTIM1_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPTIM2_IRQHandler
|
||||
.thumb_set LPTIM2_IRQHandler,Default_Handler
|
||||
|
||||
.weak AES2_IRQHandler
|
||||
.thumb_set AES2_IRQHandler,Default_Handler
|
||||
|
||||
.weak RNG_IRQHandler
|
||||
.thumb_set RNG_IRQHandler,Default_Handler
|
||||
|
||||
.weak FPU_IRQHandler
|
||||
.thumb_set FPU_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMAMUX1_OVR_IRQHandler
|
||||
.thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -1,393 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file startup_stm32wb15xx_cm4.s
|
||||
* @author MCD Application Team
|
||||
* @brief STM32WB15xx devices vector table GCC toolchain.
|
||||
* This module performs:
|
||||
* - Set the initial SP
|
||||
* - Set the initial PC == Reset_Handler,
|
||||
* - Set the vector table entries with the exceptions ISR address
|
||||
* - Branches to main in the C library (which eventually
|
||||
* calls main()).
|
||||
* After Reset the Cortex-M4 processor is in Thread mode,
|
||||
* priority is Privileged, and the Stack is set to Main.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2019-2021 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
.syntax unified
|
||||
.cpu cortex-m4
|
||||
.fpu softvfp
|
||||
.thumb
|
||||
|
||||
.global g_pfnVectors
|
||||
.global Default_Handler
|
||||
|
||||
/* start address for the initialization values of the .data section.
|
||||
defined in linker script */
|
||||
.word _sidata
|
||||
/* start address for the .data section. defined in linker script */
|
||||
.word _sdata
|
||||
/* end address for the .data section. defined in linker script */
|
||||
.word _edata
|
||||
/* start address for the .bss section. defined in linker script */
|
||||
.word _sbss
|
||||
/* end address for the .bss section. defined in linker script */
|
||||
.word _ebss
|
||||
/* start address for the .MB_MEM2 section. defined in linker script */
|
||||
.word _sMB_MEM2
|
||||
/* end address for the .MB_MEM2 section. defined in linker script */
|
||||
.word _eMB_MEM2
|
||||
|
||||
/* INIT_BSS macro is used to fill the specified region [start : end] with zeros */
|
||||
.macro INIT_BSS start, end
|
||||
ldr r0, =\start
|
||||
ldr r1, =\end
|
||||
movs r3, #0
|
||||
bl LoopFillZerobss
|
||||
.endm
|
||||
|
||||
/* INIT_DATA macro is used to copy data in the region [start : end] starting from 'src' */
|
||||
.macro INIT_DATA start, end, src
|
||||
ldr r0, =\start
|
||||
ldr r1, =\end
|
||||
ldr r2, =\src
|
||||
movs r3, #0
|
||||
bl LoopCopyDataInit
|
||||
.endm
|
||||
|
||||
.section .text.data_initializers
|
||||
CopyDataInit:
|
||||
ldr r4, [r2, r3]
|
||||
str r4, [r0, r3]
|
||||
adds r3, r3, #4
|
||||
|
||||
LoopCopyDataInit:
|
||||
adds r4, r0, r3
|
||||
cmp r4, r1
|
||||
bcc CopyDataInit
|
||||
bx lr
|
||||
|
||||
FillZerobss:
|
||||
str r3, [r0]
|
||||
adds r0, r0, #4
|
||||
|
||||
LoopFillZerobss:
|
||||
cmp r0, r1
|
||||
bcc FillZerobss
|
||||
bx lr
|
||||
|
||||
.section .text.Reset_Handler
|
||||
.weak Reset_Handler
|
||||
.type Reset_Handler, %function
|
||||
Reset_Handler:
|
||||
ldr r0, =_estack
|
||||
mov sp, r0 /* set stack pointer */
|
||||
/* Call the clock system intitialization function.*/
|
||||
bl SystemInit
|
||||
|
||||
/* Copy the data segment initializers from flash to SRAM */
|
||||
INIT_DATA _sdata, _edata, _sidata
|
||||
|
||||
/* Zero fill the bss segments. */
|
||||
INIT_BSS _sbss, _ebss
|
||||
INIT_BSS _sMB_MEM2, _eMB_MEM2
|
||||
|
||||
/* Call static constructors */
|
||||
bl __libc_init_array
|
||||
/* Call the application s entry point.*/
|
||||
bl entry
|
||||
|
||||
LoopForever:
|
||||
b LoopForever
|
||||
|
||||
.size Reset_Handler, .-Reset_Handler
|
||||
|
||||
/**
|
||||
* @brief This is the code that gets called when the processor receives an
|
||||
* unexpected interrupt. This simply enters an infinite loop, preserving
|
||||
* the system state for examination by a debugger.
|
||||
*
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
.section .text.Default_Handler,"ax",%progbits
|
||||
Default_Handler:
|
||||
Infinite_Loop:
|
||||
b Infinite_Loop
|
||||
.size Default_Handler, .-Default_Handler
|
||||
/******************************************************************************
|
||||
*
|
||||
* The minimal vector table for a Cortex-M4. Note that the proper constructs
|
||||
* must be placed on this to ensure that it ends up at physical address
|
||||
* 0x0000.0000.
|
||||
*
|
||||
******************************************************************************/
|
||||
.section .isr_vector,"a",%progbits
|
||||
.type g_pfnVectors, %object
|
||||
.size g_pfnVectors, .-g_pfnVectors
|
||||
|
||||
|
||||
g_pfnVectors:
|
||||
.word _estack
|
||||
.word Reset_Handler
|
||||
.word NMI_Handler
|
||||
.word HardFault_Handler
|
||||
.word MemManage_Handler
|
||||
.word BusFault_Handler
|
||||
.word UsageFault_Handler
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word SVC_Handler
|
||||
.word DebugMon_Handler
|
||||
.word 0
|
||||
.word PendSV_Handler
|
||||
.word SysTick_Handler
|
||||
.word WWDG_IRQHandler
|
||||
.word PVD_PVM_IRQHandler
|
||||
.word TAMP_STAMP_LSECSS_IRQHandler
|
||||
.word RTC_WKUP_IRQHandler
|
||||
.word FLASH_IRQHandler
|
||||
.word RCC_IRQHandler
|
||||
.word EXTI0_IRQHandler
|
||||
.word EXTI1_IRQHandler
|
||||
.word EXTI2_IRQHandler
|
||||
.word EXTI3_IRQHandler
|
||||
.word EXTI4_IRQHandler
|
||||
.word DMA1_Channel1_IRQHandler
|
||||
.word DMA1_Channel2_IRQHandler
|
||||
.word DMA1_Channel3_IRQHandler
|
||||
.word DMA1_Channel4_IRQHandler
|
||||
.word DMA1_Channel5_IRQHandler
|
||||
.word DMA1_Channel6_IRQHandler
|
||||
.word DMA1_Channel7_IRQHandler
|
||||
.word ADC1_IRQHandler
|
||||
.word 0
|
||||
.word 0
|
||||
.word C2SEV_PWR_C2H_IRQHandler
|
||||
.word COMP_IRQHandler
|
||||
.word EXTI9_5_IRQHandler
|
||||
.word TIM1_BRK_IRQHandler
|
||||
.word TIM1_UP_IRQHandler
|
||||
.word TIM1_TRG_COM_IRQHandler
|
||||
.word TIM1_CC_IRQHandler
|
||||
.word TIM2_IRQHandler
|
||||
.word PKA_IRQHandler
|
||||
.word I2C1_EV_IRQHandler
|
||||
.word I2C1_ER_IRQHandler
|
||||
.word 0
|
||||
.word 0
|
||||
.word SPI1_IRQHandler
|
||||
.word 0
|
||||
.word USART1_IRQHandler
|
||||
.word LPUART1_IRQHandler
|
||||
.word 0
|
||||
.word TSC_IRQHandler
|
||||
.word EXTI15_10_IRQHandler
|
||||
.word RTC_Alarm_IRQHandler
|
||||
.word 0
|
||||
.word PWR_SOTF_BLEACT_RFPHASE_IRQHandler
|
||||
.word IPCC_C1_RX_IRQHandler
|
||||
.word IPCC_C1_TX_IRQHandler
|
||||
.word HSEM_IRQHandler
|
||||
.word LPTIM1_IRQHandler
|
||||
.word LPTIM2_IRQHandler
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word AES2_IRQHandler
|
||||
.word RNG_IRQHandler
|
||||
.word FPU_IRQHandler
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word DMAMUX1_OVR_IRQHandler
|
||||
|
||||
/*******************************************************************************
|
||||
*
|
||||
* Provide weak aliases for each Exception handler to the Default_Handler.
|
||||
* As they are weak aliases, any function with the same name will override
|
||||
* this definition.
|
||||
*
|
||||
*******************************************************************************/
|
||||
.weak NMI_Handler
|
||||
.thumb_set NMI_Handler,Default_Handler
|
||||
|
||||
.weak HardFault_Handler
|
||||
.thumb_set HardFault_Handler,Default_Handler
|
||||
|
||||
.weak MemManage_Handler
|
||||
.thumb_set MemManage_Handler,Default_Handler
|
||||
|
||||
.weak BusFault_Handler
|
||||
.thumb_set BusFault_Handler,Default_Handler
|
||||
|
||||
.weak UsageFault_Handler
|
||||
.thumb_set UsageFault_Handler,Default_Handler
|
||||
|
||||
.weak SVC_Handler
|
||||
.thumb_set SVC_Handler,Default_Handler
|
||||
|
||||
.weak DebugMon_Handler
|
||||
.thumb_set DebugMon_Handler,Default_Handler
|
||||
|
||||
.weak PendSV_Handler
|
||||
.thumb_set PendSV_Handler,Default_Handler
|
||||
|
||||
.weak SysTick_Handler
|
||||
.thumb_set SysTick_Handler,Default_Handler
|
||||
|
||||
.weak WWDG_IRQHandler
|
||||
.thumb_set WWDG_IRQHandler,Default_Handler
|
||||
|
||||
.weak PVD_PVM_IRQHandler
|
||||
.thumb_set PVD_PVM_IRQHandler,Default_Handler
|
||||
|
||||
.weak TAMP_STAMP_LSECSS_IRQHandler
|
||||
.thumb_set TAMP_STAMP_LSECSS_IRQHandler,Default_Handler
|
||||
|
||||
.weak RTC_WKUP_IRQHandler
|
||||
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
|
||||
|
||||
.weak FLASH_IRQHandler
|
||||
.thumb_set FLASH_IRQHandler,Default_Handler
|
||||
|
||||
.weak RCC_IRQHandler
|
||||
.thumb_set RCC_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI0_IRQHandler
|
||||
.thumb_set EXTI0_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI1_IRQHandler
|
||||
.thumb_set EXTI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI2_IRQHandler
|
||||
.thumb_set EXTI2_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI3_IRQHandler
|
||||
.thumb_set EXTI3_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI4_IRQHandler
|
||||
.thumb_set EXTI4_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel1_IRQHandler
|
||||
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel2_IRQHandler
|
||||
.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel3_IRQHandler
|
||||
.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel4_IRQHandler
|
||||
.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel5_IRQHandler
|
||||
.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel6_IRQHandler
|
||||
.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel7_IRQHandler
|
||||
.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
|
||||
|
||||
.weak ADC1_IRQHandler
|
||||
.thumb_set ADC1_IRQHandler,Default_Handler
|
||||
|
||||
.weak C2SEV_PWR_C2H_IRQHandler
|
||||
.thumb_set C2SEV_PWR_C2H_IRQHandler,Default_Handler
|
||||
|
||||
.weak COMP_IRQHandler
|
||||
.thumb_set COMP_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI9_5_IRQHandler
|
||||
.thumb_set EXTI9_5_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_BRK_IRQHandler
|
||||
.thumb_set TIM1_BRK_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_UP_IRQHandler
|
||||
.thumb_set TIM1_UP_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_TRG_COM_IRQHandler
|
||||
.thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_CC_IRQHandler
|
||||
.thumb_set TIM1_CC_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM2_IRQHandler
|
||||
.thumb_set TIM2_IRQHandler,Default_Handler
|
||||
|
||||
.weak PKA_IRQHandler
|
||||
.thumb_set PKA_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C1_EV_IRQHandler
|
||||
.thumb_set I2C1_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C1_ER_IRQHandler
|
||||
.thumb_set I2C1_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI1_IRQHandler
|
||||
.thumb_set SPI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART1_IRQHandler
|
||||
.thumb_set USART1_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPUART1_IRQHandler
|
||||
.thumb_set LPUART1_IRQHandler,Default_Handler
|
||||
|
||||
.weak TSC_IRQHandler
|
||||
.thumb_set TSC_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI15_10_IRQHandler
|
||||
.thumb_set EXTI15_10_IRQHandler,Default_Handler
|
||||
|
||||
.weak RTC_Alarm_IRQHandler
|
||||
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
|
||||
|
||||
.weak PWR_SOTF_BLEACT_RFPHASE_IRQHandler
|
||||
.thumb_set PWR_SOTF_BLEACT_RFPHASE_IRQHandler,Default_Handler
|
||||
|
||||
.weak IPCC_C1_RX_IRQHandler
|
||||
.thumb_set IPCC_C1_RX_IRQHandler,Default_Handler
|
||||
|
||||
.weak IPCC_C1_TX_IRQHandler
|
||||
.thumb_set IPCC_C1_TX_IRQHandler,Default_Handler
|
||||
|
||||
.weak HSEM_IRQHandler
|
||||
.thumb_set HSEM_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPTIM1_IRQHandler
|
||||
.thumb_set LPTIM1_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPTIM2_IRQHandler
|
||||
.thumb_set LPTIM2_IRQHandler,Default_Handler
|
||||
|
||||
.weak AES2_IRQHandler
|
||||
.thumb_set AES2_IRQHandler,Default_Handler
|
||||
|
||||
.weak RNG_IRQHandler
|
||||
.thumb_set RNG_IRQHandler,Default_Handler
|
||||
|
||||
.weak FPU_IRQHandler
|
||||
.thumb_set FPU_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMAMUX1_OVR_IRQHandler
|
||||
.thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -1,384 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file startup_stm32wb30xx_cm4.s
|
||||
* @author MCD Application Team
|
||||
* @brief STM32WB30xx devices vector table GCC toolchain.
|
||||
* This module performs:
|
||||
* - Set the initial SP
|
||||
* - Set the initial PC == Reset_Handler,
|
||||
* - Set the vector table entries with the exceptions ISR address
|
||||
* - Branches to main in the C library (which eventually
|
||||
* calls main()).
|
||||
* After Reset the Cortex-M4 processor is in Thread mode,
|
||||
* priority is Privileged, and the Stack is set to Main.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2019-2021 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
.syntax unified
|
||||
.cpu cortex-m4
|
||||
.fpu softvfp
|
||||
.thumb
|
||||
|
||||
.global g_pfnVectors
|
||||
.global Default_Handler
|
||||
|
||||
/* start address for the initialization values of the .data section.
|
||||
defined in linker script */
|
||||
.word _sidata
|
||||
/* start address for the .data section. defined in linker script */
|
||||
.word _sdata
|
||||
/* end address for the .data section. defined in linker script */
|
||||
.word _edata
|
||||
/* start address for the .bss section. defined in linker script */
|
||||
.word _sbss
|
||||
/* end address for the .bss section. defined in linker script */
|
||||
.word _ebss
|
||||
/* start address for the .MB_MEM2 section. defined in linker script */
|
||||
.word _sMB_MEM2
|
||||
/* end address for the .MB_MEM2 section. defined in linker script */
|
||||
.word _eMB_MEM2
|
||||
|
||||
/* INIT_BSS macro is used to fill the specified region [start : end] with zeros */
|
||||
.macro INIT_BSS start, end
|
||||
ldr r0, =\start
|
||||
ldr r1, =\end
|
||||
movs r3, #0
|
||||
bl LoopFillZerobss
|
||||
.endm
|
||||
|
||||
/* INIT_DATA macro is used to copy data in the region [start : end] starting from 'src' */
|
||||
.macro INIT_DATA start, end, src
|
||||
ldr r0, =\start
|
||||
ldr r1, =\end
|
||||
ldr r2, =\src
|
||||
movs r3, #0
|
||||
bl LoopCopyDataInit
|
||||
.endm
|
||||
|
||||
.section .text.data_initializers
|
||||
CopyDataInit:
|
||||
ldr r4, [r2, r3]
|
||||
str r4, [r0, r3]
|
||||
adds r3, r3, #4
|
||||
|
||||
LoopCopyDataInit:
|
||||
adds r4, r0, r3
|
||||
cmp r4, r1
|
||||
bcc CopyDataInit
|
||||
bx lr
|
||||
|
||||
FillZerobss:
|
||||
str r3, [r0]
|
||||
adds r0, r0, #4
|
||||
|
||||
LoopFillZerobss:
|
||||
cmp r0, r1
|
||||
bcc FillZerobss
|
||||
bx lr
|
||||
|
||||
.section .text.Reset_Handler
|
||||
.weak Reset_Handler
|
||||
.type Reset_Handler, %function
|
||||
Reset_Handler:
|
||||
ldr r0, =_estack
|
||||
mov sp, r0 /* set stack pointer */
|
||||
/* Call the clock system intitialization function.*/
|
||||
bl SystemInit
|
||||
|
||||
/* Copy the data segment initializers from flash to SRAM */
|
||||
INIT_DATA _sdata, _edata, _sidata
|
||||
|
||||
/* Zero fill the bss segments. */
|
||||
INIT_BSS _sbss, _ebss
|
||||
INIT_BSS _sMB_MEM2, _eMB_MEM2
|
||||
|
||||
/* Call static constructors */
|
||||
bl __libc_init_array
|
||||
/* Call the application s entry point.*/
|
||||
bl entry
|
||||
|
||||
LoopForever:
|
||||
b LoopForever
|
||||
|
||||
.size Reset_Handler, .-Reset_Handler
|
||||
|
||||
/**
|
||||
* @brief This is the code that gets called when the processor receives an
|
||||
* unexpected interrupt. This simply enters an infinite loop, preserving
|
||||
* the system state for examination by a debugger.
|
||||
*
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
.section .text.Default_Handler,"ax",%progbits
|
||||
Default_Handler:
|
||||
Infinite_Loop:
|
||||
b Infinite_Loop
|
||||
.size Default_Handler, .-Default_Handler
|
||||
/******************************************************************************
|
||||
*
|
||||
* The minimal vector table for a Cortex-M4. Note that the proper constructs
|
||||
* must be placed on this to ensure that it ends up at physical address
|
||||
* 0x0000.0000.
|
||||
*
|
||||
******************************************************************************/
|
||||
.section .isr_vector,"a",%progbits
|
||||
.type g_pfnVectors, %object
|
||||
.size g_pfnVectors, .-g_pfnVectors
|
||||
|
||||
|
||||
g_pfnVectors:
|
||||
.word _estack
|
||||
.word Reset_Handler
|
||||
.word NMI_Handler
|
||||
.word HardFault_Handler
|
||||
.word MemManage_Handler
|
||||
.word BusFault_Handler
|
||||
.word UsageFault_Handler
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word SVC_Handler
|
||||
.word DebugMon_Handler
|
||||
.word 0
|
||||
.word PendSV_Handler
|
||||
.word SysTick_Handler
|
||||
.word WWDG_IRQHandler
|
||||
.word PVD_PVM_IRQHandler
|
||||
.word TAMP_STAMP_LSECSS_IRQHandler
|
||||
.word RTC_WKUP_IRQHandler
|
||||
.word FLASH_IRQHandler
|
||||
.word RCC_IRQHandler
|
||||
.word EXTI0_IRQHandler
|
||||
.word EXTI1_IRQHandler
|
||||
.word EXTI2_IRQHandler
|
||||
.word EXTI3_IRQHandler
|
||||
.word EXTI4_IRQHandler
|
||||
.word DMA1_Channel1_IRQHandler
|
||||
.word DMA1_Channel2_IRQHandler
|
||||
.word DMA1_Channel3_IRQHandler
|
||||
.word DMA1_Channel4_IRQHandler
|
||||
.word DMA1_Channel5_IRQHandler
|
||||
.word DMA1_Channel6_IRQHandler
|
||||
.word DMA1_Channel7_IRQHandler
|
||||
.word ADC1_IRQHandler
|
||||
.word 0
|
||||
.word 0
|
||||
.word C2SEV_PWR_C2H_IRQHandler
|
||||
.word 0
|
||||
.word EXTI9_5_IRQHandler
|
||||
.word TIM1_BRK_IRQHandler
|
||||
.word TIM1_UP_TIM16_IRQHandler
|
||||
.word TIM1_TRG_COM_TIM17_IRQHandler
|
||||
.word TIM1_CC_IRQHandler
|
||||
.word TIM2_IRQHandler
|
||||
.word PKA_IRQHandler
|
||||
.word I2C1_EV_IRQHandler
|
||||
.word I2C1_ER_IRQHandler
|
||||
.word 0
|
||||
.word 0
|
||||
.word SPI1_IRQHandler
|
||||
.word 0
|
||||
.word USART1_IRQHandler
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word EXTI15_10_IRQHandler
|
||||
.word RTC_Alarm_IRQHandler
|
||||
.word 0
|
||||
.word PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
|
||||
.word IPCC_C1_RX_IRQHandler
|
||||
.word IPCC_C1_TX_IRQHandler
|
||||
.word HSEM_IRQHandler
|
||||
.word LPTIM1_IRQHandler
|
||||
.word LPTIM2_IRQHandler
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word AES2_IRQHandler
|
||||
.word RNG_IRQHandler
|
||||
.word FPU_IRQHandler
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word DMAMUX1_OVR_IRQHandler
|
||||
|
||||
/*******************************************************************************
|
||||
*
|
||||
* Provide weak aliases for each Exception handler to the Default_Handler.
|
||||
* As they are weak aliases, any function with the same name will override
|
||||
* this definition.
|
||||
*
|
||||
*******************************************************************************/
|
||||
.weak NMI_Handler
|
||||
.thumb_set NMI_Handler,Default_Handler
|
||||
|
||||
.weak HardFault_Handler
|
||||
.thumb_set HardFault_Handler,Default_Handler
|
||||
|
||||
.weak MemManage_Handler
|
||||
.thumb_set MemManage_Handler,Default_Handler
|
||||
|
||||
.weak BusFault_Handler
|
||||
.thumb_set BusFault_Handler,Default_Handler
|
||||
|
||||
.weak UsageFault_Handler
|
||||
.thumb_set UsageFault_Handler,Default_Handler
|
||||
|
||||
.weak SVC_Handler
|
||||
.thumb_set SVC_Handler,Default_Handler
|
||||
|
||||
.weak DebugMon_Handler
|
||||
.thumb_set DebugMon_Handler,Default_Handler
|
||||
|
||||
.weak PendSV_Handler
|
||||
.thumb_set PendSV_Handler,Default_Handler
|
||||
|
||||
.weak SysTick_Handler
|
||||
.thumb_set SysTick_Handler,Default_Handler
|
||||
|
||||
.weak WWDG_IRQHandler
|
||||
.thumb_set WWDG_IRQHandler,Default_Handler
|
||||
|
||||
.weak PVD_PVM_IRQHandler
|
||||
.thumb_set PVD_PVM_IRQHandler,Default_Handler
|
||||
|
||||
.weak TAMP_STAMP_LSECSS_IRQHandler
|
||||
.thumb_set TAMP_STAMP_LSECSS_IRQHandler,Default_Handler
|
||||
|
||||
.weak RTC_WKUP_IRQHandler
|
||||
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
|
||||
|
||||
.weak FLASH_IRQHandler
|
||||
.thumb_set FLASH_IRQHandler,Default_Handler
|
||||
|
||||
.weak RCC_IRQHandler
|
||||
.thumb_set RCC_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI0_IRQHandler
|
||||
.thumb_set EXTI0_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI1_IRQHandler
|
||||
.thumb_set EXTI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI2_IRQHandler
|
||||
.thumb_set EXTI2_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI3_IRQHandler
|
||||
.thumb_set EXTI3_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI4_IRQHandler
|
||||
.thumb_set EXTI4_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel1_IRQHandler
|
||||
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel2_IRQHandler
|
||||
.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel3_IRQHandler
|
||||
.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel4_IRQHandler
|
||||
.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel5_IRQHandler
|
||||
.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel6_IRQHandler
|
||||
.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel7_IRQHandler
|
||||
.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
|
||||
|
||||
.weak ADC1_IRQHandler
|
||||
.thumb_set ADC1_IRQHandler,Default_Handler
|
||||
|
||||
.weak C2SEV_PWR_C2H_IRQHandler
|
||||
.thumb_set C2SEV_PWR_C2H_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI9_5_IRQHandler
|
||||
.thumb_set EXTI9_5_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_BRK_IRQHandler
|
||||
.thumb_set TIM1_BRK_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_UP_TIM16_IRQHandler
|
||||
.thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_TRG_COM_TIM17_IRQHandler
|
||||
.thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_CC_IRQHandler
|
||||
.thumb_set TIM1_CC_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM2_IRQHandler
|
||||
.thumb_set TIM2_IRQHandler,Default_Handler
|
||||
|
||||
.weak PKA_IRQHandler
|
||||
.thumb_set PKA_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C1_EV_IRQHandler
|
||||
.thumb_set I2C1_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C1_ER_IRQHandler
|
||||
.thumb_set I2C1_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI1_IRQHandler
|
||||
.thumb_set SPI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART1_IRQHandler
|
||||
.thumb_set USART1_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI15_10_IRQHandler
|
||||
.thumb_set EXTI15_10_IRQHandler,Default_Handler
|
||||
|
||||
.weak RTC_Alarm_IRQHandler
|
||||
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
|
||||
|
||||
.weak PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
|
||||
.thumb_set PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler,Default_Handler
|
||||
|
||||
.weak IPCC_C1_RX_IRQHandler
|
||||
.thumb_set IPCC_C1_RX_IRQHandler,Default_Handler
|
||||
|
||||
.weak IPCC_C1_TX_IRQHandler
|
||||
.thumb_set IPCC_C1_TX_IRQHandler,Default_Handler
|
||||
|
||||
.weak HSEM_IRQHandler
|
||||
.thumb_set HSEM_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPTIM1_IRQHandler
|
||||
.thumb_set LPTIM1_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPTIM2_IRQHandler
|
||||
.thumb_set LPTIM2_IRQHandler,Default_Handler
|
||||
|
||||
.weak AES2_IRQHandler
|
||||
.thumb_set AES2_IRQHandler,Default_Handler
|
||||
|
||||
.weak RNG_IRQHandler
|
||||
.thumb_set RNG_IRQHandler,Default_Handler
|
||||
|
||||
.weak FPU_IRQHandler
|
||||
.thumb_set FPU_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMAMUX1_OVR_IRQHandler
|
||||
.thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -1,432 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file startup_stm32wb35xx_cm4.s
|
||||
* @author MCD Application Team
|
||||
* @brief STM32WB35xx devices vector table GCC toolchain.
|
||||
* This module performs:
|
||||
* - Set the initial SP
|
||||
* - Set the initial PC == Reset_Handler,
|
||||
* - Set the vector table entries with the exceptions ISR address
|
||||
* - Branches to main in the C library (which eventually
|
||||
* calls main()).
|
||||
* After Reset the Cortex-M4 processor is in Thread mode,
|
||||
* priority is Privileged, and the Stack is set to Main.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2019-2021 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
.syntax unified
|
||||
.cpu cortex-m4
|
||||
.fpu softvfp
|
||||
.thumb
|
||||
|
||||
.global g_pfnVectors
|
||||
.global Default_Handler
|
||||
|
||||
/* start address for the initialization values of the .data section.
|
||||
defined in linker script */
|
||||
.word _sidata
|
||||
/* start address for the .data section. defined in linker script */
|
||||
.word _sdata
|
||||
/* end address for the .data section. defined in linker script */
|
||||
.word _edata
|
||||
/* start address for the .bss section. defined in linker script */
|
||||
.word _sbss
|
||||
/* end address for the .bss section. defined in linker script */
|
||||
.word _ebss
|
||||
/* start address for the .MB_MEM2 section. defined in linker script */
|
||||
.word _sMB_MEM2
|
||||
/* end address for the .MB_MEM2 section. defined in linker script */
|
||||
.word _eMB_MEM2
|
||||
|
||||
/* INIT_BSS macro is used to fill the specified region [start : end] with zeros */
|
||||
.macro INIT_BSS start, end
|
||||
ldr r0, =\start
|
||||
ldr r1, =\end
|
||||
movs r3, #0
|
||||
bl LoopFillZerobss
|
||||
.endm
|
||||
|
||||
/* INIT_DATA macro is used to copy data in the region [start : end] starting from 'src' */
|
||||
.macro INIT_DATA start, end, src
|
||||
ldr r0, =\start
|
||||
ldr r1, =\end
|
||||
ldr r2, =\src
|
||||
movs r3, #0
|
||||
bl LoopCopyDataInit
|
||||
.endm
|
||||
|
||||
.section .text.data_initializers
|
||||
CopyDataInit:
|
||||
ldr r4, [r2, r3]
|
||||
str r4, [r0, r3]
|
||||
adds r3, r3, #4
|
||||
|
||||
LoopCopyDataInit:
|
||||
adds r4, r0, r3
|
||||
cmp r4, r1
|
||||
bcc CopyDataInit
|
||||
bx lr
|
||||
|
||||
FillZerobss:
|
||||
str r3, [r0]
|
||||
adds r0, r0, #4
|
||||
|
||||
LoopFillZerobss:
|
||||
cmp r0, r1
|
||||
bcc FillZerobss
|
||||
bx lr
|
||||
|
||||
.section .text.Reset_Handler
|
||||
.weak Reset_Handler
|
||||
.type Reset_Handler, %function
|
||||
Reset_Handler:
|
||||
ldr r0, =_estack
|
||||
mov sp, r0 /* set stack pointer */
|
||||
/* Call the clock system intitialization function.*/
|
||||
bl SystemInit
|
||||
|
||||
/* Copy the data segment initializers from flash to SRAM */
|
||||
INIT_DATA _sdata, _edata, _sidata
|
||||
|
||||
/* Zero fill the bss segments. */
|
||||
INIT_BSS _sbss, _ebss
|
||||
INIT_BSS _sMB_MEM2, _eMB_MEM2
|
||||
|
||||
/* Call static constructors */
|
||||
bl __libc_init_array
|
||||
/* Call the application s entry point.*/
|
||||
bl entry
|
||||
|
||||
LoopForever:
|
||||
b LoopForever
|
||||
|
||||
.size Reset_Handler, .-Reset_Handler
|
||||
|
||||
/**
|
||||
* @brief This is the code that gets called when the processor receives an
|
||||
* unexpected interrupt. This simply enters an infinite loop, preserving
|
||||
* the system state for examination by a debugger.
|
||||
*
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
.section .text.Default_Handler,"ax",%progbits
|
||||
Default_Handler:
|
||||
Infinite_Loop:
|
||||
b Infinite_Loop
|
||||
.size Default_Handler, .-Default_Handler
|
||||
/******************************************************************************
|
||||
*
|
||||
* The minimal vector table for a Cortex-M4. Note that the proper constructs
|
||||
* must be placed on this to ensure that it ends up at physical address
|
||||
* 0x0000.0000.
|
||||
*
|
||||
******************************************************************************/
|
||||
.section .isr_vector,"a",%progbits
|
||||
.type g_pfnVectors, %object
|
||||
.size g_pfnVectors, .-g_pfnVectors
|
||||
|
||||
|
||||
g_pfnVectors:
|
||||
.word _estack
|
||||
.word Reset_Handler
|
||||
.word NMI_Handler
|
||||
.word HardFault_Handler
|
||||
.word MemManage_Handler
|
||||
.word BusFault_Handler
|
||||
.word UsageFault_Handler
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word SVC_Handler
|
||||
.word DebugMon_Handler
|
||||
.word 0
|
||||
.word PendSV_Handler
|
||||
.word SysTick_Handler
|
||||
.word WWDG_IRQHandler
|
||||
.word PVD_PVM_IRQHandler
|
||||
.word TAMP_STAMP_LSECSS_IRQHandler
|
||||
.word RTC_WKUP_IRQHandler
|
||||
.word FLASH_IRQHandler
|
||||
.word RCC_IRQHandler
|
||||
.word EXTI0_IRQHandler
|
||||
.word EXTI1_IRQHandler
|
||||
.word EXTI2_IRQHandler
|
||||
.word EXTI3_IRQHandler
|
||||
.word EXTI4_IRQHandler
|
||||
.word DMA1_Channel1_IRQHandler
|
||||
.word DMA1_Channel2_IRQHandler
|
||||
.word DMA1_Channel3_IRQHandler
|
||||
.word DMA1_Channel4_IRQHandler
|
||||
.word DMA1_Channel5_IRQHandler
|
||||
.word DMA1_Channel6_IRQHandler
|
||||
.word DMA1_Channel7_IRQHandler
|
||||
.word ADC1_IRQHandler
|
||||
.word USB_HP_IRQHandler
|
||||
.word USB_LP_IRQHandler
|
||||
.word C2SEV_PWR_C2H_IRQHandler
|
||||
.word COMP_IRQHandler
|
||||
.word EXTI9_5_IRQHandler
|
||||
.word TIM1_BRK_IRQHandler
|
||||
.word TIM1_UP_TIM16_IRQHandler
|
||||
.word TIM1_TRG_COM_TIM17_IRQHandler
|
||||
.word TIM1_CC_IRQHandler
|
||||
.word TIM2_IRQHandler
|
||||
.word PKA_IRQHandler
|
||||
.word I2C1_EV_IRQHandler
|
||||
.word I2C1_ER_IRQHandler
|
||||
.word I2C3_EV_IRQHandler
|
||||
.word I2C3_ER_IRQHandler
|
||||
.word SPI1_IRQHandler
|
||||
.word 0
|
||||
.word USART1_IRQHandler
|
||||
.word LPUART1_IRQHandler
|
||||
.word 0
|
||||
.word 0
|
||||
.word EXTI15_10_IRQHandler
|
||||
.word RTC_Alarm_IRQHandler
|
||||
.word CRS_IRQHandler
|
||||
.word PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
|
||||
.word IPCC_C1_RX_IRQHandler
|
||||
.word IPCC_C1_TX_IRQHandler
|
||||
.word HSEM_IRQHandler
|
||||
.word LPTIM1_IRQHandler
|
||||
.word LPTIM2_IRQHandler
|
||||
.word 0
|
||||
.word QUADSPI_IRQHandler
|
||||
.word AES1_IRQHandler
|
||||
.word AES2_IRQHandler
|
||||
.word RNG_IRQHandler
|
||||
.word FPU_IRQHandler
|
||||
.word DMA2_Channel1_IRQHandler
|
||||
.word DMA2_Channel2_IRQHandler
|
||||
.word DMA2_Channel3_IRQHandler
|
||||
.word DMA2_Channel4_IRQHandler
|
||||
.word DMA2_Channel5_IRQHandler
|
||||
.word DMA2_Channel6_IRQHandler
|
||||
.word DMA2_Channel7_IRQHandler
|
||||
.word DMAMUX1_OVR_IRQHandler
|
||||
|
||||
/*******************************************************************************
|
||||
*
|
||||
* Provide weak aliases for each Exception handler to the Default_Handler.
|
||||
* As they are weak aliases, any function with the same name will override
|
||||
* this definition.
|
||||
*
|
||||
*******************************************************************************/
|
||||
.weak NMI_Handler
|
||||
.thumb_set NMI_Handler,Default_Handler
|
||||
|
||||
.weak HardFault_Handler
|
||||
.thumb_set HardFault_Handler,Default_Handler
|
||||
|
||||
.weak MemManage_Handler
|
||||
.thumb_set MemManage_Handler,Default_Handler
|
||||
|
||||
.weak BusFault_Handler
|
||||
.thumb_set BusFault_Handler,Default_Handler
|
||||
|
||||
.weak UsageFault_Handler
|
||||
.thumb_set UsageFault_Handler,Default_Handler
|
||||
|
||||
.weak SVC_Handler
|
||||
.thumb_set SVC_Handler,Default_Handler
|
||||
|
||||
.weak DebugMon_Handler
|
||||
.thumb_set DebugMon_Handler,Default_Handler
|
||||
|
||||
.weak PendSV_Handler
|
||||
.thumb_set PendSV_Handler,Default_Handler
|
||||
|
||||
.weak SysTick_Handler
|
||||
.thumb_set SysTick_Handler,Default_Handler
|
||||
|
||||
.weak WWDG_IRQHandler
|
||||
.thumb_set WWDG_IRQHandler,Default_Handler
|
||||
|
||||
.weak PVD_PVM_IRQHandler
|
||||
.thumb_set PVD_PVM_IRQHandler,Default_Handler
|
||||
|
||||
.weak TAMP_STAMP_LSECSS_IRQHandler
|
||||
.thumb_set TAMP_STAMP_LSECSS_IRQHandler,Default_Handler
|
||||
|
||||
.weak RTC_WKUP_IRQHandler
|
||||
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
|
||||
|
||||
.weak FLASH_IRQHandler
|
||||
.thumb_set FLASH_IRQHandler,Default_Handler
|
||||
|
||||
.weak RCC_IRQHandler
|
||||
.thumb_set RCC_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI0_IRQHandler
|
||||
.thumb_set EXTI0_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI1_IRQHandler
|
||||
.thumb_set EXTI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI2_IRQHandler
|
||||
.thumb_set EXTI2_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI3_IRQHandler
|
||||
.thumb_set EXTI3_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI4_IRQHandler
|
||||
.thumb_set EXTI4_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel1_IRQHandler
|
||||
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel2_IRQHandler
|
||||
.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel3_IRQHandler
|
||||
.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel4_IRQHandler
|
||||
.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel5_IRQHandler
|
||||
.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel6_IRQHandler
|
||||
.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel7_IRQHandler
|
||||
.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
|
||||
|
||||
.weak ADC1_IRQHandler
|
||||
.thumb_set ADC1_IRQHandler,Default_Handler
|
||||
|
||||
.weak USB_HP_IRQHandler
|
||||
.thumb_set USB_HP_IRQHandler,Default_Handler
|
||||
|
||||
.weak USB_LP_IRQHandler
|
||||
.thumb_set USB_LP_IRQHandler,Default_Handler
|
||||
|
||||
.weak C2SEV_PWR_C2H_IRQHandler
|
||||
.thumb_set C2SEV_PWR_C2H_IRQHandler,Default_Handler
|
||||
|
||||
.weak COMP_IRQHandler
|
||||
.thumb_set COMP_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI9_5_IRQHandler
|
||||
.thumb_set EXTI9_5_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_BRK_IRQHandler
|
||||
.thumb_set TIM1_BRK_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_UP_TIM16_IRQHandler
|
||||
.thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_TRG_COM_TIM17_IRQHandler
|
||||
.thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_CC_IRQHandler
|
||||
.thumb_set TIM1_CC_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM2_IRQHandler
|
||||
.thumb_set TIM2_IRQHandler,Default_Handler
|
||||
|
||||
.weak PKA_IRQHandler
|
||||
.thumb_set PKA_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C1_EV_IRQHandler
|
||||
.thumb_set I2C1_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C1_ER_IRQHandler
|
||||
.thumb_set I2C1_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C3_EV_IRQHandler
|
||||
.thumb_set I2C3_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C3_ER_IRQHandler
|
||||
.thumb_set I2C3_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI1_IRQHandler
|
||||
.thumb_set SPI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART1_IRQHandler
|
||||
.thumb_set USART1_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPUART1_IRQHandler
|
||||
.thumb_set LPUART1_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI15_10_IRQHandler
|
||||
.thumb_set EXTI15_10_IRQHandler,Default_Handler
|
||||
|
||||
.weak RTC_Alarm_IRQHandler
|
||||
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
|
||||
|
||||
.weak CRS_IRQHandler
|
||||
.thumb_set CRS_IRQHandler,Default_Handler
|
||||
|
||||
.weak PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
|
||||
.thumb_set PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler,Default_Handler
|
||||
|
||||
.weak IPCC_C1_RX_IRQHandler
|
||||
.thumb_set IPCC_C1_RX_IRQHandler,Default_Handler
|
||||
|
||||
.weak IPCC_C1_TX_IRQHandler
|
||||
.thumb_set IPCC_C1_TX_IRQHandler,Default_Handler
|
||||
|
||||
.weak HSEM_IRQHandler
|
||||
.thumb_set HSEM_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPTIM1_IRQHandler
|
||||
.thumb_set LPTIM1_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPTIM2_IRQHandler
|
||||
.thumb_set LPTIM2_IRQHandler,Default_Handler
|
||||
|
||||
.weak QUADSPI_IRQHandler
|
||||
.thumb_set QUADSPI_IRQHandler,Default_Handler
|
||||
|
||||
.weak AES1_IRQHandler
|
||||
.thumb_set AES1_IRQHandler,Default_Handler
|
||||
|
||||
.weak AES2_IRQHandler
|
||||
.thumb_set AES2_IRQHandler,Default_Handler
|
||||
|
||||
.weak RNG_IRQHandler
|
||||
.thumb_set RNG_IRQHandler,Default_Handler
|
||||
|
||||
.weak FPU_IRQHandler
|
||||
.thumb_set FPU_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Channel1_IRQHandler
|
||||
.thumb_set DMA2_Channel1_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Channel2_IRQHandler
|
||||
.thumb_set DMA2_Channel2_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Channel3_IRQHandler
|
||||
.thumb_set DMA2_Channel3_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Channel4_IRQHandler
|
||||
.thumb_set DMA2_Channel4_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Channel5_IRQHandler
|
||||
.thumb_set DMA2_Channel5_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Channel6_IRQHandler
|
||||
.thumb_set DMA2_Channel6_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Channel7_IRQHandler
|
||||
.thumb_set DMA2_Channel7_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMAMUX1_OVR_IRQHandler
|
||||
.thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -1,387 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file startup_stm32wb50xx_cm4.s
|
||||
* @author MCD Application Team
|
||||
* @brief STM32WB50xx devices vector table GCC toolchain.
|
||||
* This module performs:
|
||||
* - Set the initial SP
|
||||
* - Set the initial PC == Reset_Handler,
|
||||
* - Set the vector table entries with the exceptions ISR address
|
||||
* - Branches to main in the C library (which eventually
|
||||
* calls main()).
|
||||
* After Reset the Cortex-M4 processor is in Thread mode,
|
||||
* priority is Privileged, and the Stack is set to Main.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2019-2021 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
.syntax unified
|
||||
.cpu cortex-m4
|
||||
.fpu softvfp
|
||||
.thumb
|
||||
|
||||
.global g_pfnVectors
|
||||
.global Default_Handler
|
||||
|
||||
/* start address for the initialization values of the .data section.
|
||||
defined in linker script */
|
||||
.word _sidata
|
||||
/* start address for the .data section. defined in linker script */
|
||||
.word _sdata
|
||||
/* end address for the .data section. defined in linker script */
|
||||
.word _edata
|
||||
/* start address for the .bss section. defined in linker script */
|
||||
.word _sbss
|
||||
/* end address for the .bss section. defined in linker script */
|
||||
.word _ebss
|
||||
/* start address for the .MB_MEM2 section. defined in linker script */
|
||||
.word _sMB_MEM2
|
||||
/* end address for the .MB_MEM2 section. defined in linker script */
|
||||
.word _eMB_MEM2
|
||||
|
||||
/* INIT_BSS macro is used to fill the specified region [start : end] with zeros */
|
||||
.macro INIT_BSS start, end
|
||||
ldr r0, =\start
|
||||
ldr r1, =\end
|
||||
movs r3, #0
|
||||
bl LoopFillZerobss
|
||||
.endm
|
||||
|
||||
/* INIT_DATA macro is used to copy data in the region [start : end] starting from 'src' */
|
||||
.macro INIT_DATA start, end, src
|
||||
ldr r0, =\start
|
||||
ldr r1, =\end
|
||||
ldr r2, =\src
|
||||
movs r3, #0
|
||||
bl LoopCopyDataInit
|
||||
.endm
|
||||
|
||||
.section .text.data_initializers
|
||||
CopyDataInit:
|
||||
ldr r4, [r2, r3]
|
||||
str r4, [r0, r3]
|
||||
adds r3, r3, #4
|
||||
|
||||
LoopCopyDataInit:
|
||||
adds r4, r0, r3
|
||||
cmp r4, r1
|
||||
bcc CopyDataInit
|
||||
bx lr
|
||||
|
||||
FillZerobss:
|
||||
str r3, [r0]
|
||||
adds r0, r0, #4
|
||||
|
||||
LoopFillZerobss:
|
||||
cmp r0, r1
|
||||
bcc FillZerobss
|
||||
bx lr
|
||||
|
||||
.section .text.Reset_Handler
|
||||
.weak Reset_Handler
|
||||
.type Reset_Handler, %function
|
||||
Reset_Handler:
|
||||
ldr r0, =_estack
|
||||
mov sp, r0 /* set stack pointer */
|
||||
/* Call the clock system intitialization function.*/
|
||||
bl SystemInit
|
||||
|
||||
/* Copy the data segment initializers from flash to SRAM */
|
||||
INIT_DATA _sdata, _edata, _sidata
|
||||
|
||||
/* Zero fill the bss segments. */
|
||||
INIT_BSS _sbss, _ebss
|
||||
INIT_BSS _sMB_MEM2, _eMB_MEM2
|
||||
|
||||
/* Call static constructors */
|
||||
bl __libc_init_array
|
||||
/* Call the application s entry point.*/
|
||||
bl entry
|
||||
|
||||
LoopForever:
|
||||
b LoopForever
|
||||
|
||||
.size Reset_Handler, .-Reset_Handler
|
||||
|
||||
/**
|
||||
* @brief This is the code that gets called when the processor receives an
|
||||
* unexpected interrupt. This simply enters an infinite loop, preserving
|
||||
* the system state for examination by a debugger.
|
||||
*
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
.section .text.Default_Handler,"ax",%progbits
|
||||
Default_Handler:
|
||||
Infinite_Loop:
|
||||
b Infinite_Loop
|
||||
.size Default_Handler, .-Default_Handler
|
||||
/******************************************************************************
|
||||
*
|
||||
* The minimal vector table for a Cortex-M4. Note that the proper constructs
|
||||
* must be placed on this to ensure that it ends up at physical address
|
||||
* 0x0000.0000.
|
||||
*
|
||||
******************************************************************************/
|
||||
.section .isr_vector,"a",%progbits
|
||||
.type g_pfnVectors, %object
|
||||
.size g_pfnVectors, .-g_pfnVectors
|
||||
|
||||
|
||||
g_pfnVectors:
|
||||
.word _estack
|
||||
.word Reset_Handler
|
||||
.word NMI_Handler
|
||||
.word HardFault_Handler
|
||||
.word MemManage_Handler
|
||||
.word BusFault_Handler
|
||||
.word UsageFault_Handler
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word SVC_Handler
|
||||
.word DebugMon_Handler
|
||||
.word 0
|
||||
.word PendSV_Handler
|
||||
.word SysTick_Handler
|
||||
.word WWDG_IRQHandler
|
||||
.word PVD_PVM_IRQHandler
|
||||
.word TAMP_STAMP_LSECSS_IRQHandler
|
||||
.word RTC_WKUP_IRQHandler
|
||||
.word FLASH_IRQHandler
|
||||
.word RCC_IRQHandler
|
||||
.word EXTI0_IRQHandler
|
||||
.word EXTI1_IRQHandler
|
||||
.word EXTI2_IRQHandler
|
||||
.word EXTI3_IRQHandler
|
||||
.word EXTI4_IRQHandler
|
||||
.word DMA1_Channel1_IRQHandler
|
||||
.word DMA1_Channel2_IRQHandler
|
||||
.word DMA1_Channel3_IRQHandler
|
||||
.word DMA1_Channel4_IRQHandler
|
||||
.word DMA1_Channel5_IRQHandler
|
||||
.word DMA1_Channel6_IRQHandler
|
||||
.word DMA1_Channel7_IRQHandler
|
||||
.word ADC1_IRQHandler
|
||||
.word 0
|
||||
.word 0
|
||||
.word C2SEV_PWR_C2H_IRQHandler
|
||||
.word 0
|
||||
.word EXTI9_5_IRQHandler
|
||||
.word TIM1_BRK_IRQHandler
|
||||
.word TIM1_UP_TIM16_IRQHandler
|
||||
.word TIM1_TRG_COM_TIM17_IRQHandler
|
||||
.word TIM1_CC_IRQHandler
|
||||
.word TIM2_IRQHandler
|
||||
.word PKA_IRQHandler
|
||||
.word I2C1_EV_IRQHandler
|
||||
.word I2C1_ER_IRQHandler
|
||||
.word 0
|
||||
.word 0
|
||||
.word SPI1_IRQHandler
|
||||
.word 0
|
||||
.word USART1_IRQHandler
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word EXTI15_10_IRQHandler
|
||||
.word RTC_Alarm_IRQHandler
|
||||
.word 0
|
||||
.word PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
|
||||
.word IPCC_C1_RX_IRQHandler
|
||||
.word IPCC_C1_TX_IRQHandler
|
||||
.word HSEM_IRQHandler
|
||||
.word LPTIM1_IRQHandler
|
||||
.word LPTIM2_IRQHandler
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word AES2_IRQHandler
|
||||
.word RNG_IRQHandler
|
||||
.word FPU_IRQHandler
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word DMAMUX1_OVR_IRQHandler
|
||||
|
||||
/*******************************************************************************
|
||||
*
|
||||
* Provide weak aliases for each Exception handler to the Default_Handler.
|
||||
* As they are weak aliases, any function with the same name will override
|
||||
* this definition.
|
||||
*
|
||||
*******************************************************************************/
|
||||
.weak NMI_Handler
|
||||
.thumb_set NMI_Handler,Default_Handler
|
||||
|
||||
.weak HardFault_Handler
|
||||
.thumb_set HardFault_Handler,Default_Handler
|
||||
|
||||
.weak MemManage_Handler
|
||||
.thumb_set MemManage_Handler,Default_Handler
|
||||
|
||||
.weak BusFault_Handler
|
||||
.thumb_set BusFault_Handler,Default_Handler
|
||||
|
||||
.weak UsageFault_Handler
|
||||
.thumb_set UsageFault_Handler,Default_Handler
|
||||
|
||||
.weak SVC_Handler
|
||||
.thumb_set SVC_Handler,Default_Handler
|
||||
|
||||
.weak DebugMon_Handler
|
||||
.thumb_set DebugMon_Handler,Default_Handler
|
||||
|
||||
.weak PendSV_Handler
|
||||
.thumb_set PendSV_Handler,Default_Handler
|
||||
|
||||
.weak SysTick_Handler
|
||||
.thumb_set SysTick_Handler,Default_Handler
|
||||
|
||||
.weak WWDG_IRQHandler
|
||||
.thumb_set WWDG_IRQHandler,Default_Handler
|
||||
|
||||
.weak PVD_PVM_IRQHandler
|
||||
.thumb_set PVD_PVM_IRQHandler,Default_Handler
|
||||
|
||||
.weak TAMP_STAMP_LSECSS_IRQHandler
|
||||
.thumb_set TAMP_STAMP_LSECSS_IRQHandler,Default_Handler
|
||||
|
||||
.weak RTC_WKUP_IRQHandler
|
||||
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
|
||||
|
||||
.weak FLASH_IRQHandler
|
||||
.thumb_set FLASH_IRQHandler,Default_Handler
|
||||
|
||||
.weak RCC_IRQHandler
|
||||
.thumb_set RCC_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI0_IRQHandler
|
||||
.thumb_set EXTI0_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI1_IRQHandler
|
||||
.thumb_set EXTI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI2_IRQHandler
|
||||
.thumb_set EXTI2_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI3_IRQHandler
|
||||
.thumb_set EXTI3_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI4_IRQHandler
|
||||
.thumb_set EXTI4_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel1_IRQHandler
|
||||
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel2_IRQHandler
|
||||
.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel3_IRQHandler
|
||||
.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel4_IRQHandler
|
||||
.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel5_IRQHandler
|
||||
.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel6_IRQHandler
|
||||
.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel7_IRQHandler
|
||||
.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
|
||||
|
||||
.weak ADC1_IRQHandler
|
||||
.thumb_set ADC1_IRQHandler,Default_Handler
|
||||
|
||||
.weak C2SEV_PWR_C2H_IRQHandler
|
||||
.thumb_set C2SEV_PWR_C2H_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI9_5_IRQHandler
|
||||
.thumb_set EXTI9_5_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_BRK_IRQHandler
|
||||
.thumb_set TIM1_BRK_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_UP_TIM16_IRQHandler
|
||||
.thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_TRG_COM_TIM17_IRQHandler
|
||||
.thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_CC_IRQHandler
|
||||
.thumb_set TIM1_CC_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM2_IRQHandler
|
||||
.thumb_set TIM2_IRQHandler,Default_Handler
|
||||
|
||||
.weak PKA_IRQHandler
|
||||
.thumb_set PKA_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C1_EV_IRQHandler
|
||||
.thumb_set I2C1_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C1_ER_IRQHandler
|
||||
.thumb_set I2C1_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI1_IRQHandler
|
||||
.thumb_set SPI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART1_IRQHandler
|
||||
.thumb_set USART1_IRQHandler,Default_Handler
|
||||
|
||||
.weak TSC_IRQHandler
|
||||
.thumb_set TSC_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI15_10_IRQHandler
|
||||
.thumb_set EXTI15_10_IRQHandler,Default_Handler
|
||||
|
||||
.weak RTC_Alarm_IRQHandler
|
||||
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
|
||||
|
||||
.weak PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
|
||||
.thumb_set PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler,Default_Handler
|
||||
|
||||
.weak IPCC_C1_RX_IRQHandler
|
||||
.thumb_set IPCC_C1_RX_IRQHandler,Default_Handler
|
||||
|
||||
.weak IPCC_C1_TX_IRQHandler
|
||||
.thumb_set IPCC_C1_TX_IRQHandler,Default_Handler
|
||||
|
||||
.weak HSEM_IRQHandler
|
||||
.thumb_set HSEM_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPTIM1_IRQHandler
|
||||
.thumb_set LPTIM1_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPTIM2_IRQHandler
|
||||
.thumb_set LPTIM2_IRQHandler,Default_Handler
|
||||
|
||||
.weak AES2_IRQHandler
|
||||
.thumb_set AES2_IRQHandler,Default_Handler
|
||||
|
||||
.weak RNG_IRQHandler
|
||||
.thumb_set RNG_IRQHandler,Default_Handler
|
||||
|
||||
.weak FPU_IRQHandler
|
||||
.thumb_set FPU_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMAMUX1_OVR_IRQHandler
|
||||
.thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -1,444 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file startup_stm32wb55xx_cm4.s
|
||||
* @author MCD Application Team
|
||||
* @brief STM32WB55xx devices vector table GCC toolchain.
|
||||
* This module performs:
|
||||
* - Set the initial SP
|
||||
* - Set the initial PC == Reset_Handler,
|
||||
* - Set the vector table entries with the exceptions ISR address
|
||||
* - Branches to main in the C library (which eventually
|
||||
* calls main()).
|
||||
* After Reset the Cortex-M4 processor is in Thread mode,
|
||||
* priority is Privileged, and the Stack is set to Main.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2019-2021 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
.syntax unified
|
||||
.cpu cortex-m4
|
||||
.fpu softvfp
|
||||
.thumb
|
||||
|
||||
.global g_pfnVectors
|
||||
.global Default_Handler
|
||||
|
||||
/* start address for the initialization values of the .data section.
|
||||
defined in linker script */
|
||||
.word _sidata
|
||||
/* start address for the .data section. defined in linker script */
|
||||
.word _sdata
|
||||
/* end address for the .data section. defined in linker script */
|
||||
.word _edata
|
||||
/* start address for the .bss section. defined in linker script */
|
||||
.word _sbss
|
||||
/* end address for the .bss section. defined in linker script */
|
||||
.word _ebss
|
||||
/* start address for the .MB_MEM2 section. defined in linker script */
|
||||
.word _sMB_MEM2
|
||||
/* end address for the .MB_MEM2 section. defined in linker script */
|
||||
.word _eMB_MEM2
|
||||
|
||||
/* INIT_BSS macro is used to fill the specified region [start : end] with zeros */
|
||||
.macro INIT_BSS start, end
|
||||
ldr r0, =\start
|
||||
ldr r1, =\end
|
||||
movs r3, #0
|
||||
bl LoopFillZerobss
|
||||
.endm
|
||||
|
||||
/* INIT_DATA macro is used to copy data in the region [start : end] starting from 'src' */
|
||||
.macro INIT_DATA start, end, src
|
||||
ldr r0, =\start
|
||||
ldr r1, =\end
|
||||
ldr r2, =\src
|
||||
movs r3, #0
|
||||
bl LoopCopyDataInit
|
||||
.endm
|
||||
|
||||
.section .text.data_initializers
|
||||
CopyDataInit:
|
||||
ldr r4, [r2, r3]
|
||||
str r4, [r0, r3]
|
||||
adds r3, r3, #4
|
||||
|
||||
LoopCopyDataInit:
|
||||
adds r4, r0, r3
|
||||
cmp r4, r1
|
||||
bcc CopyDataInit
|
||||
bx lr
|
||||
|
||||
FillZerobss:
|
||||
str r3, [r0]
|
||||
adds r0, r0, #4
|
||||
|
||||
LoopFillZerobss:
|
||||
cmp r0, r1
|
||||
bcc FillZerobss
|
||||
bx lr
|
||||
|
||||
.section .text.Reset_Handler
|
||||
.weak Reset_Handler
|
||||
.type Reset_Handler, %function
|
||||
Reset_Handler:
|
||||
ldr r0, =_estack
|
||||
mov sp, r0 /* set stack pointer */
|
||||
/* Call the clock system intitialization function.*/
|
||||
bl SystemInit
|
||||
|
||||
/* Copy the data segment initializers from flash to SRAM */
|
||||
INIT_DATA _sdata, _edata, _sidata
|
||||
|
||||
/* Zero fill the bss segments. */
|
||||
INIT_BSS _sbss, _ebss
|
||||
INIT_BSS _sMB_MEM2, _eMB_MEM2
|
||||
|
||||
/* Call static constructors */
|
||||
bl __libc_init_array
|
||||
/* Call the application s entry point.*/
|
||||
bl entry
|
||||
|
||||
LoopForever:
|
||||
b LoopForever
|
||||
|
||||
.size Reset_Handler, .-Reset_Handler
|
||||
|
||||
/**
|
||||
* @brief This is the code that gets called when the processor receives an
|
||||
* unexpected interrupt. This simply enters an infinite loop, preserving
|
||||
* the system state for examination by a debugger.
|
||||
*
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
.section .text.Default_Handler,"ax",%progbits
|
||||
Default_Handler:
|
||||
Infinite_Loop:
|
||||
b Infinite_Loop
|
||||
.size Default_Handler, .-Default_Handler
|
||||
/******************************************************************************
|
||||
*
|
||||
* The minimal vector table for a Cortex-M4. Note that the proper constructs
|
||||
* must be placed on this to ensure that it ends up at physical address
|
||||
* 0x0000.0000.
|
||||
*
|
||||
******************************************************************************/
|
||||
.section .isr_vector,"a",%progbits
|
||||
.type g_pfnVectors, %object
|
||||
.size g_pfnVectors, .-g_pfnVectors
|
||||
|
||||
|
||||
g_pfnVectors:
|
||||
.word _estack
|
||||
.word Reset_Handler
|
||||
.word NMI_Handler
|
||||
.word HardFault_Handler
|
||||
.word MemManage_Handler
|
||||
.word BusFault_Handler
|
||||
.word UsageFault_Handler
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word SVC_Handler
|
||||
.word DebugMon_Handler
|
||||
.word 0
|
||||
.word PendSV_Handler
|
||||
.word SysTick_Handler
|
||||
.word WWDG_IRQHandler
|
||||
.word PVD_PVM_IRQHandler
|
||||
.word TAMP_STAMP_LSECSS_IRQHandler
|
||||
.word RTC_WKUP_IRQHandler
|
||||
.word FLASH_IRQHandler
|
||||
.word RCC_IRQHandler
|
||||
.word EXTI0_IRQHandler
|
||||
.word EXTI1_IRQHandler
|
||||
.word EXTI2_IRQHandler
|
||||
.word EXTI3_IRQHandler
|
||||
.word EXTI4_IRQHandler
|
||||
.word DMA1_Channel1_IRQHandler
|
||||
.word DMA1_Channel2_IRQHandler
|
||||
.word DMA1_Channel3_IRQHandler
|
||||
.word DMA1_Channel4_IRQHandler
|
||||
.word DMA1_Channel5_IRQHandler
|
||||
.word DMA1_Channel6_IRQHandler
|
||||
.word DMA1_Channel7_IRQHandler
|
||||
.word ADC1_IRQHandler
|
||||
.word USB_HP_IRQHandler
|
||||
.word USB_LP_IRQHandler
|
||||
.word C2SEV_PWR_C2H_IRQHandler
|
||||
.word COMP_IRQHandler
|
||||
.word EXTI9_5_IRQHandler
|
||||
.word TIM1_BRK_IRQHandler
|
||||
.word TIM1_UP_TIM16_IRQHandler
|
||||
.word TIM1_TRG_COM_TIM17_IRQHandler
|
||||
.word TIM1_CC_IRQHandler
|
||||
.word TIM2_IRQHandler
|
||||
.word PKA_IRQHandler
|
||||
.word I2C1_EV_IRQHandler
|
||||
.word I2C1_ER_IRQHandler
|
||||
.word I2C3_EV_IRQHandler
|
||||
.word I2C3_ER_IRQHandler
|
||||
.word SPI1_IRQHandler
|
||||
.word SPI2_IRQHandler
|
||||
.word USART1_IRQHandler
|
||||
.word LPUART1_IRQHandler
|
||||
.word SAI1_IRQHandler
|
||||
.word TSC_IRQHandler
|
||||
.word EXTI15_10_IRQHandler
|
||||
.word RTC_Alarm_IRQHandler
|
||||
.word CRS_IRQHandler
|
||||
.word PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
|
||||
.word IPCC_C1_RX_IRQHandler
|
||||
.word IPCC_C1_TX_IRQHandler
|
||||
.word HSEM_IRQHandler
|
||||
.word LPTIM1_IRQHandler
|
||||
.word LPTIM2_IRQHandler
|
||||
.word LCD_IRQHandler
|
||||
.word QUADSPI_IRQHandler
|
||||
.word AES1_IRQHandler
|
||||
.word AES2_IRQHandler
|
||||
.word RNG_IRQHandler
|
||||
.word FPU_IRQHandler
|
||||
.word DMA2_Channel1_IRQHandler
|
||||
.word DMA2_Channel2_IRQHandler
|
||||
.word DMA2_Channel3_IRQHandler
|
||||
.word DMA2_Channel4_IRQHandler
|
||||
.word DMA2_Channel5_IRQHandler
|
||||
.word DMA2_Channel6_IRQHandler
|
||||
.word DMA2_Channel7_IRQHandler
|
||||
.word DMAMUX1_OVR_IRQHandler
|
||||
|
||||
/*******************************************************************************
|
||||
*
|
||||
* Provide weak aliases for each Exception handler to the Default_Handler.
|
||||
* As they are weak aliases, any function with the same name will override
|
||||
* this definition.
|
||||
*
|
||||
*******************************************************************************/
|
||||
.weak NMI_Handler
|
||||
.thumb_set NMI_Handler,Default_Handler
|
||||
|
||||
.weak HardFault_Handler
|
||||
.thumb_set HardFault_Handler,Default_Handler
|
||||
|
||||
.weak MemManage_Handler
|
||||
.thumb_set MemManage_Handler,Default_Handler
|
||||
|
||||
.weak BusFault_Handler
|
||||
.thumb_set BusFault_Handler,Default_Handler
|
||||
|
||||
.weak UsageFault_Handler
|
||||
.thumb_set UsageFault_Handler,Default_Handler
|
||||
|
||||
.weak SVC_Handler
|
||||
.thumb_set SVC_Handler,Default_Handler
|
||||
|
||||
.weak DebugMon_Handler
|
||||
.thumb_set DebugMon_Handler,Default_Handler
|
||||
|
||||
.weak PendSV_Handler
|
||||
.thumb_set PendSV_Handler,Default_Handler
|
||||
|
||||
.weak SysTick_Handler
|
||||
.thumb_set SysTick_Handler,Default_Handler
|
||||
|
||||
.weak WWDG_IRQHandler
|
||||
.thumb_set WWDG_IRQHandler,Default_Handler
|
||||
|
||||
.weak PVD_PVM_IRQHandler
|
||||
.thumb_set PVD_PVM_IRQHandler,Default_Handler
|
||||
|
||||
.weak TAMP_STAMP_LSECSS_IRQHandler
|
||||
.thumb_set TAMP_STAMP_LSECSS_IRQHandler,Default_Handler
|
||||
|
||||
.weak RTC_WKUP_IRQHandler
|
||||
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
|
||||
|
||||
.weak FLASH_IRQHandler
|
||||
.thumb_set FLASH_IRQHandler,Default_Handler
|
||||
|
||||
.weak RCC_IRQHandler
|
||||
.thumb_set RCC_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI0_IRQHandler
|
||||
.thumb_set EXTI0_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI1_IRQHandler
|
||||
.thumb_set EXTI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI2_IRQHandler
|
||||
.thumb_set EXTI2_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI3_IRQHandler
|
||||
.thumb_set EXTI3_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI4_IRQHandler
|
||||
.thumb_set EXTI4_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel1_IRQHandler
|
||||
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel2_IRQHandler
|
||||
.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel3_IRQHandler
|
||||
.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel4_IRQHandler
|
||||
.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel5_IRQHandler
|
||||
.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel6_IRQHandler
|
||||
.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel7_IRQHandler
|
||||
.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
|
||||
|
||||
.weak ADC1_IRQHandler
|
||||
.thumb_set ADC1_IRQHandler,Default_Handler
|
||||
|
||||
.weak USB_HP_IRQHandler
|
||||
.thumb_set USB_HP_IRQHandler,Default_Handler
|
||||
|
||||
.weak USB_LP_IRQHandler
|
||||
.thumb_set USB_LP_IRQHandler,Default_Handler
|
||||
|
||||
.weak C2SEV_PWR_C2H_IRQHandler
|
||||
.thumb_set C2SEV_PWR_C2H_IRQHandler,Default_Handler
|
||||
|
||||
.weak COMP_IRQHandler
|
||||
.thumb_set COMP_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI9_5_IRQHandler
|
||||
.thumb_set EXTI9_5_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_BRK_IRQHandler
|
||||
.thumb_set TIM1_BRK_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_UP_TIM16_IRQHandler
|
||||
.thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_TRG_COM_TIM17_IRQHandler
|
||||
.thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_CC_IRQHandler
|
||||
.thumb_set TIM1_CC_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM2_IRQHandler
|
||||
.thumb_set TIM2_IRQHandler,Default_Handler
|
||||
|
||||
.weak PKA_IRQHandler
|
||||
.thumb_set PKA_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C1_EV_IRQHandler
|
||||
.thumb_set I2C1_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C1_ER_IRQHandler
|
||||
.thumb_set I2C1_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C3_EV_IRQHandler
|
||||
.thumb_set I2C3_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C3_ER_IRQHandler
|
||||
.thumb_set I2C3_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI1_IRQHandler
|
||||
.thumb_set SPI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI2_IRQHandler
|
||||
.thumb_set SPI2_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART1_IRQHandler
|
||||
.thumb_set USART1_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPUART1_IRQHandler
|
||||
.thumb_set LPUART1_IRQHandler,Default_Handler
|
||||
|
||||
.weak SAI1_IRQHandler
|
||||
.thumb_set SAI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak TSC_IRQHandler
|
||||
.thumb_set TSC_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI15_10_IRQHandler
|
||||
.thumb_set EXTI15_10_IRQHandler,Default_Handler
|
||||
|
||||
.weak RTC_Alarm_IRQHandler
|
||||
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
|
||||
|
||||
.weak CRS_IRQHandler
|
||||
.thumb_set CRS_IRQHandler,Default_Handler
|
||||
|
||||
.weak PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
|
||||
.thumb_set PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler,Default_Handler
|
||||
|
||||
.weak IPCC_C1_RX_IRQHandler
|
||||
.thumb_set IPCC_C1_RX_IRQHandler,Default_Handler
|
||||
|
||||
.weak IPCC_C1_TX_IRQHandler
|
||||
.thumb_set IPCC_C1_TX_IRQHandler,Default_Handler
|
||||
|
||||
.weak HSEM_IRQHandler
|
||||
.thumb_set HSEM_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPTIM1_IRQHandler
|
||||
.thumb_set LPTIM1_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPTIM2_IRQHandler
|
||||
.thumb_set LPTIM2_IRQHandler,Default_Handler
|
||||
|
||||
.weak LCD_IRQHandler
|
||||
.thumb_set LCD_IRQHandler,Default_Handler
|
||||
|
||||
.weak QUADSPI_IRQHandler
|
||||
.thumb_set QUADSPI_IRQHandler,Default_Handler
|
||||
|
||||
.weak AES1_IRQHandler
|
||||
.thumb_set AES1_IRQHandler,Default_Handler
|
||||
|
||||
.weak AES2_IRQHandler
|
||||
.thumb_set AES2_IRQHandler,Default_Handler
|
||||
|
||||
.weak RNG_IRQHandler
|
||||
.thumb_set RNG_IRQHandler,Default_Handler
|
||||
|
||||
.weak FPU_IRQHandler
|
||||
.thumb_set FPU_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Channel1_IRQHandler
|
||||
.thumb_set DMA2_Channel1_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Channel2_IRQHandler
|
||||
.thumb_set DMA2_Channel2_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Channel3_IRQHandler
|
||||
.thumb_set DMA2_Channel3_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Channel4_IRQHandler
|
||||
.thumb_set DMA2_Channel4_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Channel5_IRQHandler
|
||||
.thumb_set DMA2_Channel5_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Channel6_IRQHandler
|
||||
.thumb_set DMA2_Channel6_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Channel7_IRQHandler
|
||||
.thumb_set DMA2_Channel7_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMAMUX1_OVR_IRQHandler
|
||||
.thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -1,444 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file startup_stm32wb5mxx_cm4.s
|
||||
* @author MCD Application Team
|
||||
* @brief STM32WB5Mxx devices vector table GCC toolchain.
|
||||
* This module performs:
|
||||
* - Set the initial SP
|
||||
* - Set the initial PC == Reset_Handler,
|
||||
* - Set the vector table entries with the exceptions ISR address
|
||||
* - Branches to main in the C library (which eventually
|
||||
* calls main()).
|
||||
* After Reset the Cortex-M4 processor is in Thread mode,
|
||||
* priority is Privileged, and the Stack is set to Main.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2019-2021 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
.syntax unified
|
||||
.cpu cortex-m4
|
||||
.fpu softvfp
|
||||
.thumb
|
||||
|
||||
.global g_pfnVectors
|
||||
.global Default_Handler
|
||||
|
||||
/* start address for the initialization values of the .data section.
|
||||
defined in linker script */
|
||||
.word _sidata
|
||||
/* start address for the .data section. defined in linker script */
|
||||
.word _sdata
|
||||
/* end address for the .data section. defined in linker script */
|
||||
.word _edata
|
||||
/* start address for the .bss section. defined in linker script */
|
||||
.word _sbss
|
||||
/* end address for the .bss section. defined in linker script */
|
||||
.word _ebss
|
||||
/* start address for the .MB_MEM2 section. defined in linker script */
|
||||
.word _sMB_MEM2
|
||||
/* end address for the .MB_MEM2 section. defined in linker script */
|
||||
.word _eMB_MEM2
|
||||
|
||||
/* INIT_BSS macro is used to fill the specified region [start : end] with zeros */
|
||||
.macro INIT_BSS start, end
|
||||
ldr r0, =\start
|
||||
ldr r1, =\end
|
||||
movs r3, #0
|
||||
bl LoopFillZerobss
|
||||
.endm
|
||||
|
||||
/* INIT_DATA macro is used to copy data in the region [start : end] starting from 'src' */
|
||||
.macro INIT_DATA start, end, src
|
||||
ldr r0, =\start
|
||||
ldr r1, =\end
|
||||
ldr r2, =\src
|
||||
movs r3, #0
|
||||
bl LoopCopyDataInit
|
||||
.endm
|
||||
|
||||
.section .text.data_initializers
|
||||
CopyDataInit:
|
||||
ldr r4, [r2, r3]
|
||||
str r4, [r0, r3]
|
||||
adds r3, r3, #4
|
||||
|
||||
LoopCopyDataInit:
|
||||
adds r4, r0, r3
|
||||
cmp r4, r1
|
||||
bcc CopyDataInit
|
||||
bx lr
|
||||
|
||||
FillZerobss:
|
||||
str r3, [r0]
|
||||
adds r0, r0, #4
|
||||
|
||||
LoopFillZerobss:
|
||||
cmp r0, r1
|
||||
bcc FillZerobss
|
||||
bx lr
|
||||
|
||||
.section .text.Reset_Handler
|
||||
.weak Reset_Handler
|
||||
.type Reset_Handler, %function
|
||||
Reset_Handler:
|
||||
ldr r0, =_estack
|
||||
mov sp, r0 /* set stack pointer */
|
||||
/* Call the clock system intitialization function.*/
|
||||
bl SystemInit
|
||||
|
||||
/* Copy the data segment initializers from flash to SRAM */
|
||||
INIT_DATA _sdata, _edata, _sidata
|
||||
|
||||
/* Zero fill the bss segments. */
|
||||
INIT_BSS _sbss, _ebss
|
||||
INIT_BSS _sMB_MEM2, _eMB_MEM2
|
||||
|
||||
/* Call static constructors */
|
||||
bl __libc_init_array
|
||||
/* Call the application s entry point.*/
|
||||
bl entry
|
||||
|
||||
LoopForever:
|
||||
b LoopForever
|
||||
|
||||
.size Reset_Handler, .-Reset_Handler
|
||||
|
||||
/**
|
||||
* @brief This is the code that gets called when the processor receives an
|
||||
* unexpected interrupt. This simply enters an infinite loop, preserving
|
||||
* the system state for examination by a debugger.
|
||||
*
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
.section .text.Default_Handler,"ax",%progbits
|
||||
Default_Handler:
|
||||
Infinite_Loop:
|
||||
b Infinite_Loop
|
||||
.size Default_Handler, .-Default_Handler
|
||||
/******************************************************************************
|
||||
*
|
||||
* The minimal vector table for a Cortex-M4. Note that the proper constructs
|
||||
* must be placed on this to ensure that it ends up at physical address
|
||||
* 0x0000.0000.
|
||||
*
|
||||
******************************************************************************/
|
||||
.section .isr_vector,"a",%progbits
|
||||
.type g_pfnVectors, %object
|
||||
.size g_pfnVectors, .-g_pfnVectors
|
||||
|
||||
|
||||
g_pfnVectors:
|
||||
.word _estack
|
||||
.word Reset_Handler
|
||||
.word NMI_Handler
|
||||
.word HardFault_Handler
|
||||
.word MemManage_Handler
|
||||
.word BusFault_Handler
|
||||
.word UsageFault_Handler
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word SVC_Handler
|
||||
.word DebugMon_Handler
|
||||
.word 0
|
||||
.word PendSV_Handler
|
||||
.word SysTick_Handler
|
||||
.word WWDG_IRQHandler
|
||||
.word PVD_PVM_IRQHandler
|
||||
.word TAMP_STAMP_LSECSS_IRQHandler
|
||||
.word RTC_WKUP_IRQHandler
|
||||
.word FLASH_IRQHandler
|
||||
.word RCC_IRQHandler
|
||||
.word EXTI0_IRQHandler
|
||||
.word EXTI1_IRQHandler
|
||||
.word EXTI2_IRQHandler
|
||||
.word EXTI3_IRQHandler
|
||||
.word EXTI4_IRQHandler
|
||||
.word DMA1_Channel1_IRQHandler
|
||||
.word DMA1_Channel2_IRQHandler
|
||||
.word DMA1_Channel3_IRQHandler
|
||||
.word DMA1_Channel4_IRQHandler
|
||||
.word DMA1_Channel5_IRQHandler
|
||||
.word DMA1_Channel6_IRQHandler
|
||||
.word DMA1_Channel7_IRQHandler
|
||||
.word ADC1_IRQHandler
|
||||
.word USB_HP_IRQHandler
|
||||
.word USB_LP_IRQHandler
|
||||
.word C2SEV_PWR_C2H_IRQHandler
|
||||
.word COMP_IRQHandler
|
||||
.word EXTI9_5_IRQHandler
|
||||
.word TIM1_BRK_IRQHandler
|
||||
.word TIM1_UP_TIM16_IRQHandler
|
||||
.word TIM1_TRG_COM_TIM17_IRQHandler
|
||||
.word TIM1_CC_IRQHandler
|
||||
.word TIM2_IRQHandler
|
||||
.word PKA_IRQHandler
|
||||
.word I2C1_EV_IRQHandler
|
||||
.word I2C1_ER_IRQHandler
|
||||
.word I2C3_EV_IRQHandler
|
||||
.word I2C3_ER_IRQHandler
|
||||
.word SPI1_IRQHandler
|
||||
.word SPI2_IRQHandler
|
||||
.word USART1_IRQHandler
|
||||
.word LPUART1_IRQHandler
|
||||
.word SAI1_IRQHandler
|
||||
.word TSC_IRQHandler
|
||||
.word EXTI15_10_IRQHandler
|
||||
.word RTC_Alarm_IRQHandler
|
||||
.word CRS_IRQHandler
|
||||
.word PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
|
||||
.word IPCC_C1_RX_IRQHandler
|
||||
.word IPCC_C1_TX_IRQHandler
|
||||
.word HSEM_IRQHandler
|
||||
.word LPTIM1_IRQHandler
|
||||
.word LPTIM2_IRQHandler
|
||||
.word LCD_IRQHandler
|
||||
.word QUADSPI_IRQHandler
|
||||
.word AES1_IRQHandler
|
||||
.word AES2_IRQHandler
|
||||
.word RNG_IRQHandler
|
||||
.word FPU_IRQHandler
|
||||
.word DMA2_Channel1_IRQHandler
|
||||
.word DMA2_Channel2_IRQHandler
|
||||
.word DMA2_Channel3_IRQHandler
|
||||
.word DMA2_Channel4_IRQHandler
|
||||
.word DMA2_Channel5_IRQHandler
|
||||
.word DMA2_Channel6_IRQHandler
|
||||
.word DMA2_Channel7_IRQHandler
|
||||
.word DMAMUX1_OVR_IRQHandler
|
||||
|
||||
/*******************************************************************************
|
||||
*
|
||||
* Provide weak aliases for each Exception handler to the Default_Handler.
|
||||
* As they are weak aliases, any function with the same name will override
|
||||
* this definition.
|
||||
*
|
||||
*******************************************************************************/
|
||||
.weak NMI_Handler
|
||||
.thumb_set NMI_Handler,Default_Handler
|
||||
|
||||
.weak HardFault_Handler
|
||||
.thumb_set HardFault_Handler,Default_Handler
|
||||
|
||||
.weak MemManage_Handler
|
||||
.thumb_set MemManage_Handler,Default_Handler
|
||||
|
||||
.weak BusFault_Handler
|
||||
.thumb_set BusFault_Handler,Default_Handler
|
||||
|
||||
.weak UsageFault_Handler
|
||||
.thumb_set UsageFault_Handler,Default_Handler
|
||||
|
||||
.weak SVC_Handler
|
||||
.thumb_set SVC_Handler,Default_Handler
|
||||
|
||||
.weak DebugMon_Handler
|
||||
.thumb_set DebugMon_Handler,Default_Handler
|
||||
|
||||
.weak PendSV_Handler
|
||||
.thumb_set PendSV_Handler,Default_Handler
|
||||
|
||||
.weak SysTick_Handler
|
||||
.thumb_set SysTick_Handler,Default_Handler
|
||||
|
||||
.weak WWDG_IRQHandler
|
||||
.thumb_set WWDG_IRQHandler,Default_Handler
|
||||
|
||||
.weak PVD_PVM_IRQHandler
|
||||
.thumb_set PVD_PVM_IRQHandler,Default_Handler
|
||||
|
||||
.weak TAMP_STAMP_LSECSS_IRQHandler
|
||||
.thumb_set TAMP_STAMP_LSECSS_IRQHandler,Default_Handler
|
||||
|
||||
.weak RTC_WKUP_IRQHandler
|
||||
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
|
||||
|
||||
.weak FLASH_IRQHandler
|
||||
.thumb_set FLASH_IRQHandler,Default_Handler
|
||||
|
||||
.weak RCC_IRQHandler
|
||||
.thumb_set RCC_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI0_IRQHandler
|
||||
.thumb_set EXTI0_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI1_IRQHandler
|
||||
.thumb_set EXTI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI2_IRQHandler
|
||||
.thumb_set EXTI2_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI3_IRQHandler
|
||||
.thumb_set EXTI3_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI4_IRQHandler
|
||||
.thumb_set EXTI4_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel1_IRQHandler
|
||||
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel2_IRQHandler
|
||||
.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel3_IRQHandler
|
||||
.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel4_IRQHandler
|
||||
.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel5_IRQHandler
|
||||
.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel6_IRQHandler
|
||||
.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel7_IRQHandler
|
||||
.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
|
||||
|
||||
.weak ADC1_IRQHandler
|
||||
.thumb_set ADC1_IRQHandler,Default_Handler
|
||||
|
||||
.weak USB_HP_IRQHandler
|
||||
.thumb_set USB_HP_IRQHandler,Default_Handler
|
||||
|
||||
.weak USB_LP_IRQHandler
|
||||
.thumb_set USB_LP_IRQHandler,Default_Handler
|
||||
|
||||
.weak C2SEV_PWR_C2H_IRQHandler
|
||||
.thumb_set C2SEV_PWR_C2H_IRQHandler,Default_Handler
|
||||
|
||||
.weak COMP_IRQHandler
|
||||
.thumb_set COMP_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI9_5_IRQHandler
|
||||
.thumb_set EXTI9_5_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_BRK_IRQHandler
|
||||
.thumb_set TIM1_BRK_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_UP_TIM16_IRQHandler
|
||||
.thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_TRG_COM_TIM17_IRQHandler
|
||||
.thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_CC_IRQHandler
|
||||
.thumb_set TIM1_CC_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM2_IRQHandler
|
||||
.thumb_set TIM2_IRQHandler,Default_Handler
|
||||
|
||||
.weak PKA_IRQHandler
|
||||
.thumb_set PKA_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C1_EV_IRQHandler
|
||||
.thumb_set I2C1_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C1_ER_IRQHandler
|
||||
.thumb_set I2C1_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C3_EV_IRQHandler
|
||||
.thumb_set I2C3_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C3_ER_IRQHandler
|
||||
.thumb_set I2C3_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI1_IRQHandler
|
||||
.thumb_set SPI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI2_IRQHandler
|
||||
.thumb_set SPI2_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART1_IRQHandler
|
||||
.thumb_set USART1_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPUART1_IRQHandler
|
||||
.thumb_set LPUART1_IRQHandler,Default_Handler
|
||||
|
||||
.weak SAI1_IRQHandler
|
||||
.thumb_set SAI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak TSC_IRQHandler
|
||||
.thumb_set TSC_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI15_10_IRQHandler
|
||||
.thumb_set EXTI15_10_IRQHandler,Default_Handler
|
||||
|
||||
.weak RTC_Alarm_IRQHandler
|
||||
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
|
||||
|
||||
.weak CRS_IRQHandler
|
||||
.thumb_set CRS_IRQHandler,Default_Handler
|
||||
|
||||
.weak PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
|
||||
.thumb_set PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler,Default_Handler
|
||||
|
||||
.weak IPCC_C1_RX_IRQHandler
|
||||
.thumb_set IPCC_C1_RX_IRQHandler,Default_Handler
|
||||
|
||||
.weak IPCC_C1_TX_IRQHandler
|
||||
.thumb_set IPCC_C1_TX_IRQHandler,Default_Handler
|
||||
|
||||
.weak HSEM_IRQHandler
|
||||
.thumb_set HSEM_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPTIM1_IRQHandler
|
||||
.thumb_set LPTIM1_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPTIM2_IRQHandler
|
||||
.thumb_set LPTIM2_IRQHandler,Default_Handler
|
||||
|
||||
.weak LCD_IRQHandler
|
||||
.thumb_set LCD_IRQHandler,Default_Handler
|
||||
|
||||
.weak QUADSPI_IRQHandler
|
||||
.thumb_set QUADSPI_IRQHandler,Default_Handler
|
||||
|
||||
.weak AES1_IRQHandler
|
||||
.thumb_set AES1_IRQHandler,Default_Handler
|
||||
|
||||
.weak AES2_IRQHandler
|
||||
.thumb_set AES2_IRQHandler,Default_Handler
|
||||
|
||||
.weak RNG_IRQHandler
|
||||
.thumb_set RNG_IRQHandler,Default_Handler
|
||||
|
||||
.weak FPU_IRQHandler
|
||||
.thumb_set FPU_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Channel1_IRQHandler
|
||||
.thumb_set DMA2_Channel1_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Channel2_IRQHandler
|
||||
.thumb_set DMA2_Channel2_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Channel3_IRQHandler
|
||||
.thumb_set DMA2_Channel3_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Channel4_IRQHandler
|
||||
.thumb_set DMA2_Channel4_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Channel5_IRQHandler
|
||||
.thumb_set DMA2_Channel5_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Channel6_IRQHandler
|
||||
.thumb_set DMA2_Channel6_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Channel7_IRQHandler
|
||||
.thumb_set DMA2_Channel7_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMAMUX1_OVR_IRQHandler
|
||||
.thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -1,40 +0,0 @@
|
|||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x08000000;
|
||||
/*-Memory Regions-*/
|
||||
/***** FLASH Part dedicated to M4 *****/
|
||||
define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
|
||||
define symbol __ICFEDIT_region_ROM_end__ = 0x0801B7FF;
|
||||
define symbol __ICFEDIT_region_RAM_start__ = 0x20000008;
|
||||
define symbol __ICFEDIT_region_RAM_end__ = 0x20002FFF;
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x1000;
|
||||
define symbol __ICFEDIT_size_heap__ = 0x000;
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
define symbol __ICFEDIT_region_RAM_SHARED_start__ = 0x20030000;
|
||||
define symbol __ICFEDIT_region_RAM_SHARED_end__ = 0x200327FF;
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||
define region RAM_SHARED_region = mem:[from __ICFEDIT_region_RAM_SHARED_start__ to __ICFEDIT_region_RAM_SHARED_end__];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
/* MB_MEM1 and MB_MEM2 are sections reserved to mailbox communication. It is placed in the shared memory */
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit,
|
||||
section MAPPING_TABLE,
|
||||
section MB_MEM1 };
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
|
||||
place in ROM_region { readonly };
|
||||
place in RAM_region { readwrite, block CSTACK, block HEAP };
|
||||
place in RAM_SHARED_region { first section MAPPING_TABLE};
|
||||
place in RAM_SHARED_region { section MB_MEM1};
|
||||
place in RAM_SHARED_region { section MB_MEM2};
|
||||
|
|
@ -1,39 +0,0 @@
|
|||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x20000000;
|
||||
/*-Memory Regions-*/
|
||||
/***** RAM dedicated to M4 *****/
|
||||
define symbol __ICFEDIT_region_ROM_start__ = 0x20000000;
|
||||
define symbol __ICFEDIT_region_ROM_end__ = 0x20002AFF;
|
||||
|
||||
define symbol __ICFEDIT_region_RAM_start__ = 0x20002B00;
|
||||
define symbol __ICFEDIT_region_RAM_end__ = 0x2000AFFF;
|
||||
|
||||
/***** RAM2a *****/
|
||||
define symbol __ICFEDIT_region_RAM_SHARED_start__ = 0x20030000;
|
||||
define symbol __ICFEDIT_region_RAM_SHARED_end__ = 0x2000AFFF;
|
||||
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x400;
|
||||
define symbol __ICFEDIT_size_heap__ = 0x000;
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit };
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
|
||||
place in ROM_region { readonly };
|
||||
place in RAM_region { readwrite,
|
||||
block CSTACK, block HEAP };
|
||||
|
|
@ -1,40 +0,0 @@
|
|||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x08000000;
|
||||
/*-Memory Regions-*/
|
||||
/***** FLASH Part dedicated to M4 *****/
|
||||
define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
|
||||
define symbol __ICFEDIT_region_ROM_end__ = 0x0801B7FF;
|
||||
define symbol __ICFEDIT_region_RAM_start__ = 0x20000008;
|
||||
define symbol __ICFEDIT_region_RAM_end__ = 0x20002FFF;
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x1000;
|
||||
define symbol __ICFEDIT_size_heap__ = 0x000;
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
define symbol __ICFEDIT_region_RAM_SHARED_start__ = 0x20030000;
|
||||
define symbol __ICFEDIT_region_RAM_SHARED_end__ = 0x200327FF;
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||
define region RAM_SHARED_region = mem:[from __ICFEDIT_region_RAM_SHARED_start__ to __ICFEDIT_region_RAM_SHARED_end__];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
/* MB_MEM1 and MB_MEM2 are sections reserved to mailbox communication. It is placed in the shared memory */
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit,
|
||||
section MAPPING_TABLE,
|
||||
section MB_MEM1 };
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
|
||||
place in ROM_region { readonly };
|
||||
place in RAM_region { readwrite, block CSTACK, block HEAP };
|
||||
place in RAM_SHARED_region { first section MAPPING_TABLE};
|
||||
place in RAM_SHARED_region { section MB_MEM1};
|
||||
place in RAM_SHARED_region { section MB_MEM2};
|
||||
|
|
@ -1,39 +0,0 @@
|
|||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x20000000;
|
||||
/*-Memory Regions-*/
|
||||
/***** RAM dedicated to M4 *****/
|
||||
define symbol __ICFEDIT_region_ROM_start__ = 0x20000000;
|
||||
define symbol __ICFEDIT_region_ROM_end__ = 0x20002AFF;
|
||||
|
||||
define symbol __ICFEDIT_region_RAM_start__ = 0x20002B00;
|
||||
define symbol __ICFEDIT_region_RAM_end__ = 0x2000AFFF;
|
||||
|
||||
/***** RAM2a *****/
|
||||
define symbol __ICFEDIT_region_RAM_SHARED_start__ = 0x20030000;
|
||||
define symbol __ICFEDIT_region_RAM_SHARED_end__ = 0x2000AFFF;
|
||||
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x400;
|
||||
define symbol __ICFEDIT_size_heap__ = 0x000;
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit };
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
|
||||
place in ROM_region { readonly };
|
||||
place in RAM_region { readwrite,
|
||||
block CSTACK, block HEAP };
|
||||
|
|
@ -1,40 +0,0 @@
|
|||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x08000000;
|
||||
/*-Memory Regions-*/
|
||||
/***** FLASH Part dedicated to M4 *****/
|
||||
define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
|
||||
define symbol __ICFEDIT_region_ROM_end__ = 0x0803FFFF;
|
||||
define symbol __ICFEDIT_region_RAM_start__ = 0x20000008;
|
||||
define symbol __ICFEDIT_region_RAM_end__ = 0x20007FFF;
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x1000;
|
||||
define symbol __ICFEDIT_size_heap__ = 0x000;
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
define symbol __ICFEDIT_region_RAM_SHARED_start__ = 0x20030000;
|
||||
define symbol __ICFEDIT_region_RAM_SHARED_end__ = 0x200327FF;
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||
define region RAM_SHARED_region = mem:[from __ICFEDIT_region_RAM_SHARED_start__ to __ICFEDIT_region_RAM_SHARED_end__];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
/* MB_MEM1 and MB_MEM2 are sections reserved to mailbox communication. It is placed in the shared memory */
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit,
|
||||
section MAPPING_TABLE,
|
||||
section MB_MEM1 };
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
|
||||
place in ROM_region { readonly };
|
||||
place in RAM_region { readwrite,block CSTACK, block HEAP };
|
||||
place in RAM_SHARED_region { first section MAPPING_TABLE};
|
||||
place in RAM_SHARED_region { section MB_MEM1};
|
||||
place in RAM_SHARED_region { section MB_MEM2};
|
||||
|
|
@ -1,39 +0,0 @@
|
|||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x20000000;
|
||||
/*-Memory Regions-*/
|
||||
/***** RAM dedicated to M4 *****/
|
||||
define symbol __ICFEDIT_region_ROM_start__ = 0x20000000;
|
||||
define symbol __ICFEDIT_region_ROM_end__ = 0x20003FFF;
|
||||
|
||||
define symbol __ICFEDIT_region_RAM_start__ = 0x20004000 ;
|
||||
define symbol __ICFEDIT_region_RAM_end__ = 0x20007FFF ;
|
||||
|
||||
/***** RAM2a *****/
|
||||
define symbol __ICFEDIT_region_RAM_SHARED_start__ = 0x20038000 ;
|
||||
define symbol __ICFEDIT_region_RAM_SHARED_end__ = 0x2003A7FF ;
|
||||
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x400;
|
||||
define symbol __ICFEDIT_size_heap__ = 0x000;
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit };
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
|
||||
place in ROM_region { readonly };
|
||||
place in RAM_region { readwrite,
|
||||
block CSTACK, block HEAP };
|
||||
|
|
@ -1,40 +0,0 @@
|
|||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x08000000;
|
||||
/*-Memory Regions-*/
|
||||
/***** FLASH Part dedicated to M4 *****/
|
||||
define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
|
||||
define symbol __ICFEDIT_region_ROM_end__ = 0x0803FFFF;
|
||||
define symbol __ICFEDIT_region_RAM_start__ = 0x20000008;
|
||||
define symbol __ICFEDIT_region_RAM_end__ = 0x20007FFF;
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x1000;
|
||||
define symbol __ICFEDIT_size_heap__ = 0x000;
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
define symbol __ICFEDIT_region_RAM_SHARED_start__ = 0x20030000;
|
||||
define symbol __ICFEDIT_region_RAM_SHARED_end__ = 0x200327FF;
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||
define region RAM_SHARED_region = mem:[from __ICFEDIT_region_RAM_SHARED_start__ to __ICFEDIT_region_RAM_SHARED_end__];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
/* MB_MEM1 and MB_MEM2 are sections reserved to mailbox communication. It is placed in the shared memory */
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit,
|
||||
section MAPPING_TABLE,
|
||||
section MB_MEM1 };
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
|
||||
place in ROM_region { readonly };
|
||||
place in RAM_region { readwrite,block CSTACK, block HEAP };
|
||||
place in RAM_SHARED_region { first section MAPPING_TABLE};
|
||||
place in RAM_SHARED_region { section MB_MEM1};
|
||||
place in RAM_SHARED_region { section MB_MEM2};
|
||||
|
|
@ -1,39 +0,0 @@
|
|||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x20000000;
|
||||
/*-Memory Regions-*/
|
||||
/***** RAM dedicated to M4 *****/
|
||||
define symbol __ICFEDIT_region_ROM_start__ = 0x20000000;
|
||||
define symbol __ICFEDIT_region_ROM_end__ = 0x20003FFF;
|
||||
|
||||
define symbol __ICFEDIT_region_RAM_start__ = 0x20004000 ;
|
||||
define symbol __ICFEDIT_region_RAM_end__ = 0x20007FFF ;
|
||||
|
||||
/***** RAM2a *****/
|
||||
define symbol __ICFEDIT_region_RAM_SHARED_start__ = 0x20038000 ;
|
||||
define symbol __ICFEDIT_region_RAM_SHARED_end__ = 0x2003A7FF ;
|
||||
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x400;
|
||||
define symbol __ICFEDIT_size_heap__ = 0x000;
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit };
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
|
||||
place in ROM_region { readonly };
|
||||
place in RAM_region { readwrite,
|
||||
block CSTACK, block HEAP };
|
||||
|
|
@ -1,40 +0,0 @@
|
|||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x08000000;
|
||||
/*-Memory Regions-*/
|
||||
/***** FLASH Part dedicated to M4 *****/
|
||||
define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
|
||||
define symbol __ICFEDIT_region_ROM_end__ = 0x0807FFFF;
|
||||
define symbol __ICFEDIT_region_RAM_start__ = 0x20000008;
|
||||
define symbol __ICFEDIT_region_RAM_end__ = 0x2000FFFF;
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x1000;
|
||||
define symbol __ICFEDIT_size_heap__ = 0x000;
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
define symbol __ICFEDIT_region_RAM_SHARED_start__ = 0x20030000;
|
||||
define symbol __ICFEDIT_region_RAM_SHARED_end__ = 0x200327FF;
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||
define region RAM_SHARED_region = mem:[from __ICFEDIT_region_RAM_SHARED_start__ to __ICFEDIT_region_RAM_SHARED_end__];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
/* MB_MEM1 and MB_MEM2 are sections reserved to mailbox communication. It is placed in the shared memory */
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit,
|
||||
section MAPPING_TABLE,
|
||||
section MB_MEM1 };
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
|
||||
place in ROM_region { readonly };
|
||||
place in RAM_region { readwrite,block CSTACK, block HEAP };
|
||||
place in RAM_SHARED_region { first section MAPPING_TABLE};
|
||||
place in RAM_SHARED_region { section MB_MEM1};
|
||||
place in RAM_SHARED_region { section MB_MEM2};
|
||||
|
|
@ -1,39 +0,0 @@
|
|||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x20000000;
|
||||
/*-Memory Regions-*/
|
||||
/***** RAM dedicated to M4 *****/
|
||||
define symbol __ICFEDIT_region_ROM_start__ = 0x20000000;
|
||||
define symbol __ICFEDIT_region_ROM_end__ = 0x20007FFF;
|
||||
|
||||
define symbol __ICFEDIT_region_RAM_start__ = 0x20008000 ;
|
||||
define symbol __ICFEDIT_region_RAM_end__ = 0x2000FFFF ;
|
||||
|
||||
/***** RAM2a *****/
|
||||
define symbol __ICFEDIT_region_RAM_SHARED_start__ = 0x20030000 ;
|
||||
define symbol __ICFEDIT_region_RAM_SHARED_end__ = 0x20037FFF ;
|
||||
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x400;
|
||||
define symbol __ICFEDIT_size_heap__ = 0x000;
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit };
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
|
||||
place in ROM_region { readonly };
|
||||
place in RAM_region { readwrite,
|
||||
block CSTACK, block HEAP };
|
||||
|
|
@ -1,40 +0,0 @@
|
|||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x08000000;
|
||||
/*-Memory Regions-*/
|
||||
/***** FLASH Part dedicated to M4 *****/
|
||||
define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
|
||||
define symbol __ICFEDIT_region_ROM_end__ = 0x0807FFFF;
|
||||
define symbol __ICFEDIT_region_RAM_start__ = 0x20000008;
|
||||
define symbol __ICFEDIT_region_RAM_end__ = 0x2002FFFF;
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x1000;
|
||||
define symbol __ICFEDIT_size_heap__ = 0x000;
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
define symbol __ICFEDIT_region_RAM_SHARED_start__ = 0x20030000;
|
||||
define symbol __ICFEDIT_region_RAM_SHARED_end__ = 0x200327FF;
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||
define region RAM_SHARED_region = mem:[from __ICFEDIT_region_RAM_SHARED_start__ to __ICFEDIT_region_RAM_SHARED_end__];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
/* MB_MEM1 and MB_MEM2 are sections reserved to mailbox communication. It is placed in the shared memory */
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit,
|
||||
section MAPPING_TABLE,
|
||||
section MB_MEM1 };
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
|
||||
place in ROM_region { readonly };
|
||||
place in RAM_region { readwrite,block CSTACK, block HEAP };
|
||||
place in RAM_SHARED_region { first section MAPPING_TABLE};
|
||||
place in RAM_SHARED_region { section MB_MEM1};
|
||||
place in RAM_SHARED_region { section MB_MEM2};
|
||||
|
|
@ -1,39 +0,0 @@
|
|||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x20000000;
|
||||
/*-Memory Regions-*/
|
||||
/***** RAM dedicated to M4 *****/
|
||||
define symbol __ICFEDIT_region_ROM_start__ = 0x20000000;
|
||||
define symbol __ICFEDIT_region_ROM_end__ = 0x20017FFF;
|
||||
|
||||
define symbol __ICFEDIT_region_RAM_start__ = 0x20018000 ;
|
||||
define symbol __ICFEDIT_region_RAM_end__ = 0x2002FFFF ;
|
||||
|
||||
/***** RAM2a *****/
|
||||
define symbol __ICFEDIT_region_RAM_SHARED_start__ = 0x20030000 ;
|
||||
define symbol __ICFEDIT_region_RAM_SHARED_end__ = 0x20037FFF ;
|
||||
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x400;
|
||||
define symbol __ICFEDIT_size_heap__ = 0x000;
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit };
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
|
||||
place in ROM_region { readonly };
|
||||
place in RAM_region { readwrite,
|
||||
block CSTACK, block HEAP };
|
||||
|
|
@ -1,40 +0,0 @@
|
|||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x08000000;
|
||||
/*-Memory Regions-*/
|
||||
/***** FLASH Part dedicated to M4 *****/
|
||||
define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
|
||||
define symbol __ICFEDIT_region_ROM_end__ = 0x0807FFFF;
|
||||
define symbol __ICFEDIT_region_RAM_start__ = 0x20000008;
|
||||
define symbol __ICFEDIT_region_RAM_end__ = 0x2002FFFF;
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x1000;
|
||||
define symbol __ICFEDIT_size_heap__ = 0x000;
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
define symbol __ICFEDIT_region_RAM_SHARED_start__ = 0x20030000;
|
||||
define symbol __ICFEDIT_region_RAM_SHARED_end__ = 0x200327FF;
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||
define region RAM_SHARED_region = mem:[from __ICFEDIT_region_RAM_SHARED_start__ to __ICFEDIT_region_RAM_SHARED_end__];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
/* MB_MEM1 and MB_MEM2 are sections reserved to mailbox communication. It is placed in the shared memory */
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit,
|
||||
section MAPPING_TABLE,
|
||||
section MB_MEM1 };
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
|
||||
place in ROM_region { readonly };
|
||||
place in RAM_region { readwrite,block CSTACK, block HEAP };
|
||||
place in RAM_SHARED_region { first section MAPPING_TABLE};
|
||||
place in RAM_SHARED_region { section MB_MEM1};
|
||||
place in RAM_SHARED_region { section MB_MEM2};
|
||||
|
|
@ -1,39 +0,0 @@
|
|||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x20000000;
|
||||
/*-Memory Regions-*/
|
||||
/***** RAM dedicated to M4 *****/
|
||||
define symbol __ICFEDIT_region_ROM_start__ = 0x20000000;
|
||||
define symbol __ICFEDIT_region_ROM_end__ = 0x20017FFF;
|
||||
|
||||
define symbol __ICFEDIT_region_RAM_start__ = 0x20018000 ;
|
||||
define symbol __ICFEDIT_region_RAM_end__ = 0x2002FFFF ;
|
||||
|
||||
/***** RAM2a *****/
|
||||
define symbol __ICFEDIT_region_RAM_SHARED_start__ = 0x20030000 ;
|
||||
define symbol __ICFEDIT_region_RAM_SHARED_end__ = 0x20037FFF ;
|
||||
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x400;
|
||||
define symbol __ICFEDIT_size_heap__ = 0x000;
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit };
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
|
||||
place in ROM_region { readonly };
|
||||
place in RAM_region { readwrite,
|
||||
block CSTACK, block HEAP };
|
||||
|
|
@ -1,421 +0,0 @@
|
|||
;******************************************************************************
|
||||
;* File Name : startup_stm32wb10xx_cm4.s
|
||||
;* Author : MCD Application Team
|
||||
;* Description : M4 core vector table of the STM32WB10xx devices for the
|
||||
;* IAR (EWARM) toolchain.
|
||||
;*
|
||||
;* This module performs:
|
||||
;* - Set the initial SP
|
||||
;* - Set the initial PC == _iar_program_start,
|
||||
;* - Set the vector table entries with the exceptions ISR
|
||||
;* address.
|
||||
;* - Branches to main in the C library (which eventually
|
||||
;* calls main()).
|
||||
;* After Reset the Cortex-M4 processor is in Thread mode,
|
||||
;* priority is Privileged, and the Stack is set to Main.
|
||||
;******************************************************************************
|
||||
;* @attention
|
||||
;*
|
||||
;* Copyright (c) 2019-2021 STMicroelectronics.
|
||||
;* All rights reserved.
|
||||
;*
|
||||
;* This software is licensed under terms that can be found in the LICENSE file
|
||||
;* in the root directory of this software component.
|
||||
;* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
;*
|
||||
;******************************************************************************
|
||||
;
|
||||
;
|
||||
; The modules in this file are included in the libraries, and may be replaced
|
||||
; by any user-defined modules that define the PUBLIC symbol _program_start or
|
||||
; a user defined start symbol.
|
||||
; To override the cstartup defined in the library, simply add your modified
|
||||
; version to the workbench project.
|
||||
;
|
||||
; The vector table is normally located at address 0.
|
||||
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
|
||||
; The name "__vector_table" has special meaning for C-SPY:
|
||||
; it is where the SP start value is found, and the NVIC vector
|
||||
; table register (VTOR) is initialized to this address if != 0.
|
||||
;
|
||||
; Cortex-M version
|
||||
;
|
||||
|
||||
MODULE ?cstartup
|
||||
|
||||
;; Forward declaration of sections.
|
||||
SECTION CSTACK:DATA:NOROOT(3)
|
||||
|
||||
SECTION .intvec:CODE:NOROOT(2)
|
||||
|
||||
EXTERN __iar_program_start
|
||||
EXTERN SystemInit
|
||||
PUBLIC __vector_table
|
||||
|
||||
DATA
|
||||
__vector_table
|
||||
DCD sfe(CSTACK)
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WWDG_IRQHandler ; Window WatchDog
|
||||
DCD PVD_PVM_IRQHandler ; PVD and PVM Interrupt
|
||||
DCD TAMP_STAMP_LSECSS_IRQHandler ; RTC Tamper, TimeStamp Interrupts and LSECSS Interrupts
|
||||
DCD RTC_WKUP_IRQHandler ; RTC Wakeup Interrupt
|
||||
DCD FLASH_IRQHandler ; FLASH global Interrupt
|
||||
DCD RCC_IRQHandler ; RCC Interrupt
|
||||
DCD EXTI0_IRQHandler ; EXTI Line 0 Interrupt
|
||||
DCD EXTI1_IRQHandler ; EXTI Line 1 Interrupt
|
||||
DCD EXTI2_IRQHandler ; EXTI Line 2 Interrupt
|
||||
DCD EXTI3_IRQHandler ; EXTI Line 3 Interrup
|
||||
DCD EXTI4_IRQHandler ; EXTI Line 4 Interrupt
|
||||
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 Interrupt
|
||||
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 Interrupt
|
||||
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 Interrupt
|
||||
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 Interrupt
|
||||
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 Interrupt
|
||||
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 Interrupt
|
||||
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 Interrupt
|
||||
DCD ADC1_IRQHandler ; ADC1 Interrupt
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD C2SEV_PWR_C2H_IRQHandler ; CPU M0+ SEV Interrupt
|
||||
DCD 0 ; Reserved
|
||||
DCD EXTI9_5_IRQHandler ; EXTI Lines [9:5] Interrupt
|
||||
DCD TIM1_BRK_IRQHandler ; TIM1 Break Interrupt
|
||||
DCD TIM1_UP_IRQHandler ; TIM1 Update Interrupt
|
||||
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Communication Interrupts
|
||||
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare Interrupt
|
||||
DCD TIM2_IRQHandler ; TIM2 Global Interrupt
|
||||
DCD PKA_IRQHandler ; PKA Interrupt
|
||||
DCD I2C1_EV_IRQHandler ; I2C1 Event Interrupt
|
||||
DCD I2C1_ER_IRQHandler ; I2C1 Error Interrupt
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SPI1_IRQHandler ; SPI1 Interrupt
|
||||
DCD 0 ; Reserved
|
||||
DCD USART1_IRQHandler ; USART1 Interrupt
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD TSC_IRQHandler ; TSC Interrupt
|
||||
DCD EXTI15_10_IRQHandler ; EXTI Lines1[15:10 ]Interrupts
|
||||
DCD RTC_Alarm_IRQHandler ; RTC Alarms (A and B) Interrupt
|
||||
DCD 0 ; Reserved
|
||||
DCD PWR_SOTF_BLEACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
|
||||
DCD IPCC_C1_RX_IRQHandler ; IPCC CPU1 RX occupied interrupt
|
||||
DCD IPCC_C1_TX_IRQHandler ; IPCC CPU1 RX free interrupt
|
||||
DCD HSEM_IRQHandler ; HSEM0 Interrupt
|
||||
DCD LPTIM1_IRQHandler ; LPTIM1 Interrupt
|
||||
DCD LPTIM2_IRQHandler ; LPTIM2 Interrupt
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD AES2_IRQHandler ; AES2 Interrupt
|
||||
DCD RNG_IRQHandler ; RNG1 Interrupt
|
||||
DCD FPU_IRQHandler ; FPU Interrupt
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD DMAMUX1_OVR_IRQHandler ; DMAMUX overrun Interrupt
|
||||
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
;;
|
||||
;; Default interrupt handlers.
|
||||
;;
|
||||
THUMB
|
||||
|
||||
PUBWEAK Reset_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(2)
|
||||
Reset_Handler
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__iar_program_start
|
||||
BX R0
|
||||
|
||||
PUBWEAK NMI_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
NMI_Handler
|
||||
B NMI_Handler
|
||||
|
||||
PUBWEAK HardFault_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
HardFault_Handler
|
||||
B HardFault_Handler
|
||||
|
||||
PUBWEAK MemManage_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
MemManage_Handler
|
||||
B MemManage_Handler
|
||||
|
||||
PUBWEAK BusFault_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
BusFault_Handler
|
||||
B BusFault_Handler
|
||||
|
||||
PUBWEAK UsageFault_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
UsageFault_Handler
|
||||
B UsageFault_Handler
|
||||
|
||||
PUBWEAK SVC_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SVC_Handler
|
||||
B SVC_Handler
|
||||
|
||||
PUBWEAK DebugMon_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DebugMon_Handler
|
||||
B DebugMon_Handler
|
||||
|
||||
PUBWEAK PendSV_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
PendSV_Handler
|
||||
B PendSV_Handler
|
||||
|
||||
PUBWEAK SysTick_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SysTick_Handler
|
||||
B SysTick_Handler
|
||||
|
||||
PUBWEAK WWDG_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
WWDG_IRQHandler
|
||||
B WWDG_IRQHandler
|
||||
|
||||
PUBWEAK PVD_PVM_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
PVD_PVM_IRQHandler
|
||||
B PVD_PVM_IRQHandler
|
||||
|
||||
PUBWEAK TAMP_STAMP_LSECSS_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TAMP_STAMP_LSECSS_IRQHandler
|
||||
B TAMP_STAMP_LSECSS_IRQHandler
|
||||
|
||||
PUBWEAK RTC_WKUP_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
RTC_WKUP_IRQHandler
|
||||
B RTC_WKUP_IRQHandler
|
||||
|
||||
PUBWEAK FLASH_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
FLASH_IRQHandler
|
||||
B FLASH_IRQHandler
|
||||
|
||||
PUBWEAK RCC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
RCC_IRQHandler
|
||||
B RCC_IRQHandler
|
||||
|
||||
PUBWEAK EXTI0_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI0_IRQHandler
|
||||
B EXTI0_IRQHandler
|
||||
|
||||
PUBWEAK EXTI1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI1_IRQHandler
|
||||
B EXTI1_IRQHandler
|
||||
|
||||
PUBWEAK EXTI2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI2_IRQHandler
|
||||
B EXTI2_IRQHandler
|
||||
|
||||
PUBWEAK EXTI3_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI3_IRQHandler
|
||||
B EXTI3_IRQHandler
|
||||
|
||||
PUBWEAK EXTI4_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI4_IRQHandler
|
||||
B EXTI4_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel1_IRQHandler
|
||||
B DMA1_Channel1_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel2_IRQHandler
|
||||
B DMA1_Channel2_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel3_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel3_IRQHandler
|
||||
B DMA1_Channel3_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel4_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel4_IRQHandler
|
||||
B DMA1_Channel4_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel5_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel5_IRQHandler
|
||||
B DMA1_Channel5_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel6_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel6_IRQHandler
|
||||
B DMA1_Channel6_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel7_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel7_IRQHandler
|
||||
B DMA1_Channel7_IRQHandler
|
||||
|
||||
PUBWEAK ADC1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
ADC1_IRQHandler
|
||||
B ADC1_IRQHandler
|
||||
|
||||
PUBWEAK C2SEV_PWR_C2H_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
C2SEV_PWR_C2H_IRQHandler
|
||||
B C2SEV_PWR_C2H_IRQHandler
|
||||
|
||||
PUBWEAK EXTI9_5_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI9_5_IRQHandler
|
||||
B EXTI9_5_IRQHandler
|
||||
|
||||
PUBWEAK TIM1_BRK_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM1_BRK_IRQHandler
|
||||
B TIM1_BRK_IRQHandler
|
||||
|
||||
PUBWEAK TIM1_UP_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM1_UP_IRQHandler
|
||||
B TIM1_UP_IRQHandler
|
||||
|
||||
PUBWEAK TIM1_TRG_COM_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM1_TRG_COM_IRQHandler
|
||||
B TIM1_TRG_COM_IRQHandler
|
||||
|
||||
PUBWEAK TIM1_CC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM1_CC_IRQHandler
|
||||
B TIM1_CC_IRQHandler
|
||||
|
||||
PUBWEAK TIM2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM2_IRQHandler
|
||||
B TIM2_IRQHandler
|
||||
|
||||
PUBWEAK PKA_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
PKA_IRQHandler
|
||||
B PKA_IRQHandler
|
||||
|
||||
PUBWEAK I2C1_EV_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C1_EV_IRQHandler
|
||||
B I2C1_EV_IRQHandler
|
||||
|
||||
PUBWEAK I2C1_ER_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C1_ER_IRQHandler
|
||||
B I2C1_ER_IRQHandler
|
||||
|
||||
PUBWEAK SPI1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SPI1_IRQHandler
|
||||
B SPI1_IRQHandler
|
||||
|
||||
PUBWEAK USART1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
USART1_IRQHandler
|
||||
B USART1_IRQHandler
|
||||
|
||||
PUBWEAK TSC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TSC_IRQHandler
|
||||
B TSC_IRQHandler
|
||||
|
||||
PUBWEAK EXTI15_10_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI15_10_IRQHandler
|
||||
B EXTI15_10_IRQHandler
|
||||
|
||||
PUBWEAK RTC_Alarm_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
RTC_Alarm_IRQHandler
|
||||
B RTC_Alarm_IRQHandler
|
||||
|
||||
PUBWEAK PWR_SOTF_BLEACT_RFPHASE_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
PWR_SOTF_BLEACT_RFPHASE_IRQHandler
|
||||
B PWR_SOTF_BLEACT_RFPHASE_IRQHandler
|
||||
|
||||
PUBWEAK IPCC_C1_RX_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IPCC_C1_RX_IRQHandler
|
||||
B IPCC_C1_RX_IRQHandler
|
||||
|
||||
PUBWEAK IPCC_C1_TX_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IPCC_C1_TX_IRQHandler
|
||||
B IPCC_C1_TX_IRQHandler
|
||||
|
||||
PUBWEAK HSEM_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
HSEM_IRQHandler
|
||||
B HSEM_IRQHandler
|
||||
|
||||
PUBWEAK LPTIM1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
LPTIM1_IRQHandler
|
||||
B LPTIM1_IRQHandler
|
||||
|
||||
PUBWEAK LPTIM2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
LPTIM2_IRQHandler
|
||||
B LPTIM2_IRQHandler
|
||||
|
||||
PUBWEAK AES2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
AES2_IRQHandler
|
||||
B AES2_IRQHandler
|
||||
|
||||
PUBWEAK RNG_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
RNG_IRQHandler
|
||||
B RNG_IRQHandler
|
||||
|
||||
PUBWEAK FPU_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
FPU_IRQHandler
|
||||
B FPU_IRQHandler
|
||||
|
||||
PUBWEAK DMAMUX1_OVR_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMAMUX1_OVR_IRQHandler
|
||||
B DMAMUX1_OVR_IRQHandler
|
||||
|
||||
END
|
||||
|
||||
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
||||
|
|
@ -1,431 +0,0 @@
|
|||
;******************************************************************************
|
||||
;* File Name : startup_stm32wb15xx_cm4.s
|
||||
;* Author : MCD Application Team
|
||||
;* Description : M4 core vector table of the STM32WB15xx devices for the
|
||||
;* IAR (EWARM) toolchain.
|
||||
;*
|
||||
;* This module performs:
|
||||
;* - Set the initial SP
|
||||
;* - Set the initial PC == _iar_program_start,
|
||||
;* - Set the vector table entries with the exceptions ISR
|
||||
;* address.
|
||||
;* - Branches to main in the C library (which eventually
|
||||
;* calls main()).
|
||||
;* After Reset the Cortex-M4 processor is in Thread mode,
|
||||
;* priority is Privileged, and the Stack is set to Main.
|
||||
;******************************************************************************
|
||||
;* @attention
|
||||
;*
|
||||
;* Copyright (c) 2019-2021 STMicroelectronics.
|
||||
;* All rights reserved.
|
||||
;*
|
||||
;* This software is licensed under terms that can be found in the LICENSE file
|
||||
;* in the root directory of this software component.
|
||||
;* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
;*
|
||||
;******************************************************************************
|
||||
;
|
||||
;
|
||||
; The modules in this file are included in the libraries, and may be replaced
|
||||
; by any user-defined modules that define the PUBLIC symbol _program_start or
|
||||
; a user defined start symbol.
|
||||
; To override the cstartup defined in the library, simply add your modified
|
||||
; version to the workbench project.
|
||||
;
|
||||
; The vector table is normally located at address 0.
|
||||
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
|
||||
; The name "__vector_table" has special meaning for C-SPY:
|
||||
; it is where the SP start value is found, and the NVIC vector
|
||||
; table register (VTOR) is initialized to this address if != 0.
|
||||
;
|
||||
; Cortex-M version
|
||||
;
|
||||
|
||||
MODULE ?cstartup
|
||||
|
||||
;; Forward declaration of sections.
|
||||
SECTION CSTACK:DATA:NOROOT(3)
|
||||
|
||||
SECTION .intvec:CODE:NOROOT(2)
|
||||
|
||||
EXTERN __iar_program_start
|
||||
EXTERN SystemInit
|
||||
PUBLIC __vector_table
|
||||
|
||||
DATA
|
||||
__vector_table
|
||||
DCD sfe(CSTACK)
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WWDG_IRQHandler ; Window WatchDog
|
||||
DCD PVD_PVM_IRQHandler ; PVD and PVM Interrupt
|
||||
DCD TAMP_STAMP_LSECSS_IRQHandler ; RTC Tamper, TimeStamp Interrupts and LSECSS Interrupts
|
||||
DCD RTC_WKUP_IRQHandler ; RTC Wakeup Interrupt
|
||||
DCD FLASH_IRQHandler ; FLASH global Interrupt
|
||||
DCD RCC_IRQHandler ; RCC Interrupt
|
||||
DCD EXTI0_IRQHandler ; EXTI Line 0 Interrupt
|
||||
DCD EXTI1_IRQHandler ; EXTI Line 1 Interrupt
|
||||
DCD EXTI2_IRQHandler ; EXTI Line 2 Interrupt
|
||||
DCD EXTI3_IRQHandler ; EXTI Line 3 Interrup
|
||||
DCD EXTI4_IRQHandler ; EXTI Line 4 Interrupt
|
||||
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 Interrupt
|
||||
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 Interrupt
|
||||
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 Interrupt
|
||||
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 Interrupt
|
||||
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 Interrupt
|
||||
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 Interrupt
|
||||
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 Interrupt
|
||||
DCD ADC1_IRQHandler ; ADC1 Interrupt
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD C2SEV_PWR_C2H_IRQHandler ; CPU M0+ SEV Interrupt
|
||||
DCD COMP_IRQHandler ; COMP1 Interrupts
|
||||
DCD EXTI9_5_IRQHandler ; EXTI Lines [9:5] Interrupt
|
||||
DCD TIM1_BRK_IRQHandler ; TIM1 Break Interrupt
|
||||
DCD TIM1_UP_IRQHandler ; TIM1 Update Interrupt
|
||||
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Communication Interrupts
|
||||
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare Interrupt
|
||||
DCD TIM2_IRQHandler ; TIM2 Global Interrupt
|
||||
DCD PKA_IRQHandler ; PKA Interrupt
|
||||
DCD I2C1_EV_IRQHandler ; I2C1 Event Interrupt
|
||||
DCD I2C1_ER_IRQHandler ; I2C1 Error Interrupt
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SPI1_IRQHandler ; SPI1 Interrupt
|
||||
DCD 0 ; Reserved
|
||||
DCD USART1_IRQHandler ; USART1 Interrupt
|
||||
DCD LPUART1_IRQHandler ; LPUART1 Interrupt
|
||||
DCD 0 ; Reserved
|
||||
DCD TSC_IRQHandler ; TSC Interrupt
|
||||
DCD EXTI15_10_IRQHandler ; EXTI Lines1[15:10 ]Interrupts
|
||||
DCD RTC_Alarm_IRQHandler ; RTC Alarms (A and B) Interrupt
|
||||
DCD 0 ; Reserved
|
||||
DCD PWR_SOTF_BLEACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
|
||||
DCD IPCC_C1_RX_IRQHandler ; IPCC CPU1 RX occupied interrupt
|
||||
DCD IPCC_C1_TX_IRQHandler ; IPCC CPU1 RX free interrupt
|
||||
DCD HSEM_IRQHandler ; HSEM0 Interrupt
|
||||
DCD LPTIM1_IRQHandler ; LPTIM1 Interrupt
|
||||
DCD LPTIM2_IRQHandler ; LPTIM2 Interrupt
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD AES2_IRQHandler ; AES2 Interrupt
|
||||
DCD RNG_IRQHandler ; RNG1 Interrupt
|
||||
DCD FPU_IRQHandler ; FPU Interrupt
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD DMAMUX1_OVR_IRQHandler ; DMAMUX overrun Interrupt
|
||||
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
;;
|
||||
;; Default interrupt handlers.
|
||||
;;
|
||||
THUMB
|
||||
|
||||
PUBWEAK Reset_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(2)
|
||||
Reset_Handler
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__iar_program_start
|
||||
BX R0
|
||||
|
||||
PUBWEAK NMI_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
NMI_Handler
|
||||
B NMI_Handler
|
||||
|
||||
PUBWEAK HardFault_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
HardFault_Handler
|
||||
B HardFault_Handler
|
||||
|
||||
PUBWEAK MemManage_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
MemManage_Handler
|
||||
B MemManage_Handler
|
||||
|
||||
PUBWEAK BusFault_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
BusFault_Handler
|
||||
B BusFault_Handler
|
||||
|
||||
PUBWEAK UsageFault_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
UsageFault_Handler
|
||||
B UsageFault_Handler
|
||||
|
||||
PUBWEAK SVC_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SVC_Handler
|
||||
B SVC_Handler
|
||||
|
||||
PUBWEAK DebugMon_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DebugMon_Handler
|
||||
B DebugMon_Handler
|
||||
|
||||
PUBWEAK PendSV_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
PendSV_Handler
|
||||
B PendSV_Handler
|
||||
|
||||
PUBWEAK SysTick_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SysTick_Handler
|
||||
B SysTick_Handler
|
||||
|
||||
PUBWEAK WWDG_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
WWDG_IRQHandler
|
||||
B WWDG_IRQHandler
|
||||
|
||||
PUBWEAK PVD_PVM_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
PVD_PVM_IRQHandler
|
||||
B PVD_PVM_IRQHandler
|
||||
|
||||
PUBWEAK TAMP_STAMP_LSECSS_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TAMP_STAMP_LSECSS_IRQHandler
|
||||
B TAMP_STAMP_LSECSS_IRQHandler
|
||||
|
||||
PUBWEAK RTC_WKUP_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
RTC_WKUP_IRQHandler
|
||||
B RTC_WKUP_IRQHandler
|
||||
|
||||
PUBWEAK FLASH_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
FLASH_IRQHandler
|
||||
B FLASH_IRQHandler
|
||||
|
||||
PUBWEAK RCC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
RCC_IRQHandler
|
||||
B RCC_IRQHandler
|
||||
|
||||
PUBWEAK EXTI0_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI0_IRQHandler
|
||||
B EXTI0_IRQHandler
|
||||
|
||||
PUBWEAK EXTI1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI1_IRQHandler
|
||||
B EXTI1_IRQHandler
|
||||
|
||||
PUBWEAK EXTI2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI2_IRQHandler
|
||||
B EXTI2_IRQHandler
|
||||
|
||||
PUBWEAK EXTI3_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI3_IRQHandler
|
||||
B EXTI3_IRQHandler
|
||||
|
||||
PUBWEAK EXTI4_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI4_IRQHandler
|
||||
B EXTI4_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel1_IRQHandler
|
||||
B DMA1_Channel1_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel2_IRQHandler
|
||||
B DMA1_Channel2_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel3_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel3_IRQHandler
|
||||
B DMA1_Channel3_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel4_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel4_IRQHandler
|
||||
B DMA1_Channel4_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel5_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel5_IRQHandler
|
||||
B DMA1_Channel5_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel6_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel6_IRQHandler
|
||||
B DMA1_Channel6_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel7_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel7_IRQHandler
|
||||
B DMA1_Channel7_IRQHandler
|
||||
|
||||
PUBWEAK ADC1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
ADC1_IRQHandler
|
||||
B ADC1_IRQHandler
|
||||
|
||||
PUBWEAK C2SEV_PWR_C2H_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
C2SEV_PWR_C2H_IRQHandler
|
||||
B C2SEV_PWR_C2H_IRQHandler
|
||||
|
||||
PUBWEAK COMP_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
COMP_IRQHandler
|
||||
B COMP_IRQHandler
|
||||
|
||||
PUBWEAK EXTI9_5_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI9_5_IRQHandler
|
||||
B EXTI9_5_IRQHandler
|
||||
|
||||
PUBWEAK TIM1_BRK_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM1_BRK_IRQHandler
|
||||
B TIM1_BRK_IRQHandler
|
||||
|
||||
PUBWEAK TIM1_UP_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM1_UP_IRQHandler
|
||||
B TIM1_UP_IRQHandler
|
||||
|
||||
PUBWEAK TIM1_TRG_COM_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM1_TRG_COM_IRQHandler
|
||||
B TIM1_TRG_COM_IRQHandler
|
||||
|
||||
PUBWEAK TIM1_CC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM1_CC_IRQHandler
|
||||
B TIM1_CC_IRQHandler
|
||||
|
||||
PUBWEAK TIM2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM2_IRQHandler
|
||||
B TIM2_IRQHandler
|
||||
|
||||
PUBWEAK PKA_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
PKA_IRQHandler
|
||||
B PKA_IRQHandler
|
||||
|
||||
PUBWEAK I2C1_EV_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C1_EV_IRQHandler
|
||||
B I2C1_EV_IRQHandler
|
||||
|
||||
PUBWEAK I2C1_ER_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C1_ER_IRQHandler
|
||||
B I2C1_ER_IRQHandler
|
||||
|
||||
PUBWEAK SPI1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SPI1_IRQHandler
|
||||
B SPI1_IRQHandler
|
||||
|
||||
PUBWEAK USART1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
USART1_IRQHandler
|
||||
B USART1_IRQHandler
|
||||
|
||||
PUBWEAK LPUART1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
LPUART1_IRQHandler
|
||||
B LPUART1_IRQHandler
|
||||
|
||||
PUBWEAK TSC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TSC_IRQHandler
|
||||
B TSC_IRQHandler
|
||||
|
||||
PUBWEAK EXTI15_10_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI15_10_IRQHandler
|
||||
B EXTI15_10_IRQHandler
|
||||
|
||||
PUBWEAK RTC_Alarm_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
RTC_Alarm_IRQHandler
|
||||
B RTC_Alarm_IRQHandler
|
||||
|
||||
PUBWEAK PWR_SOTF_BLEACT_RFPHASE_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
PWR_SOTF_BLEACT_RFPHASE_IRQHandler
|
||||
B PWR_SOTF_BLEACT_RFPHASE_IRQHandler
|
||||
|
||||
PUBWEAK IPCC_C1_RX_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IPCC_C1_RX_IRQHandler
|
||||
B IPCC_C1_RX_IRQHandler
|
||||
|
||||
PUBWEAK IPCC_C1_TX_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IPCC_C1_TX_IRQHandler
|
||||
B IPCC_C1_TX_IRQHandler
|
||||
|
||||
PUBWEAK HSEM_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
HSEM_IRQHandler
|
||||
B HSEM_IRQHandler
|
||||
|
||||
PUBWEAK LPTIM1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
LPTIM1_IRQHandler
|
||||
B LPTIM1_IRQHandler
|
||||
|
||||
PUBWEAK LPTIM2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
LPTIM2_IRQHandler
|
||||
B LPTIM2_IRQHandler
|
||||
|
||||
PUBWEAK AES2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
AES2_IRQHandler
|
||||
B AES2_IRQHandler
|
||||
|
||||
PUBWEAK RNG_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
RNG_IRQHandler
|
||||
B RNG_IRQHandler
|
||||
|
||||
PUBWEAK FPU_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
FPU_IRQHandler
|
||||
B FPU_IRQHandler
|
||||
|
||||
PUBWEAK DMAMUX1_OVR_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMAMUX1_OVR_IRQHandler
|
||||
B DMAMUX1_OVR_IRQHandler
|
||||
|
||||
END
|
||||
|
||||
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
||||
|
|
@ -1,416 +0,0 @@
|
|||
;******************************************************************************
|
||||
;* File Name : startup_stm32wb30xx_cm4.s
|
||||
;* Author : MCD Application Team
|
||||
;* Description : M4 core vector table of the STM32WB30xx devices for the
|
||||
;* IAR (EWARM) toolchain.
|
||||
;*
|
||||
;* This module performs:
|
||||
;* - Set the initial SP
|
||||
;* - Set the initial PC == _iar_program_start,
|
||||
;* - Set the vector table entries with the exceptions ISR
|
||||
;* address.
|
||||
;* - Branches to main in the C library (which eventually
|
||||
;* calls main()).
|
||||
;* After Reset the Cortex-M4 processor is in Thread mode,
|
||||
;* priority is Privileged, and the Stack is set to Main.
|
||||
;******************************************************************************
|
||||
;* @attention
|
||||
;*
|
||||
;* Copyright (c) 2019-2021 STMicroelectronics.
|
||||
;* All rights reserved.
|
||||
;*
|
||||
;* This software is licensed under terms that can be found in the LICENSE file
|
||||
;* in the root directory of this software component.
|
||||
;* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
;*
|
||||
;******************************************************************************
|
||||
;
|
||||
;
|
||||
; The modules in this file are included in the libraries, and may be replaced
|
||||
; by any user-defined modules that define the PUBLIC symbol _program_start or
|
||||
; a user defined start symbol.
|
||||
; To override the cstartup defined in the library, simply add your modified
|
||||
; version to the workbench project.
|
||||
;
|
||||
; The vector table is normally located at address 0.
|
||||
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
|
||||
; The name "__vector_table" has special meaning for C-SPY:
|
||||
; it is where the SP start value is found, and the NVIC vector
|
||||
; table register (VTOR) is initialized to this address if != 0.
|
||||
;
|
||||
; Cortex-M version
|
||||
;
|
||||
|
||||
MODULE ?cstartup
|
||||
|
||||
;; Forward declaration of sections.
|
||||
SECTION CSTACK:DATA:NOROOT(3)
|
||||
|
||||
SECTION .intvec:CODE:NOROOT(2)
|
||||
|
||||
EXTERN __iar_program_start
|
||||
EXTERN SystemInit
|
||||
PUBLIC __vector_table
|
||||
|
||||
DATA
|
||||
__vector_table
|
||||
DCD sfe(CSTACK)
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WWDG_IRQHandler ; Window WatchDog
|
||||
DCD PVD_PVM_IRQHandler ; PVD and PVM Interrupt
|
||||
DCD TAMP_STAMP_LSECSS_IRQHandler ; RTC Tamper, TimeStamp Interrupts and LSECSS Interrupts
|
||||
DCD RTC_WKUP_IRQHandler ; RTC Wakeup Interrupt
|
||||
DCD FLASH_IRQHandler ; FLASH global Interrupt
|
||||
DCD RCC_IRQHandler ; RCC Interrupt
|
||||
DCD EXTI0_IRQHandler ; EXTI Line 0 Interrupt
|
||||
DCD EXTI1_IRQHandler ; EXTI Line 1 Interrupt
|
||||
DCD EXTI2_IRQHandler ; EXTI Line 2 Interrupt
|
||||
DCD EXTI3_IRQHandler ; EXTI Line 3 Interrup
|
||||
DCD EXTI4_IRQHandler ; EXTI Line 4 Interrupt
|
||||
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 Interrupt
|
||||
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 Interrupt
|
||||
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 Interrupt
|
||||
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 Interrupt
|
||||
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 Interrupt
|
||||
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 Interrupt
|
||||
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 Interrupt
|
||||
DCD ADC1_IRQHandler ; ADC1 Interrupt
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD C2SEV_PWR_C2H_IRQHandler ; CPU M0+ SEV Interrupt
|
||||
DCD 0 ; Reserved
|
||||
DCD EXTI9_5_IRQHandler ; EXTI Lines [9:5] Interrupt
|
||||
DCD TIM1_BRK_IRQHandler ; TIM1 Break Interrupt
|
||||
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16 global Interrupts
|
||||
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Communication and TIM17 global Interrupts
|
||||
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare Interrupt
|
||||
DCD TIM2_IRQHandler ; TIM2 Global Interrupt
|
||||
DCD PKA_IRQHandler ; PKA Interrupt
|
||||
DCD I2C1_EV_IRQHandler ; I2C1 Event Interrupt
|
||||
DCD I2C1_ER_IRQHandler ; I2C1 Error Interrupt
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SPI1_IRQHandler ; SPI1 Interrupt
|
||||
DCD 0 ; Reserved
|
||||
DCD USART1_IRQHandler ; USART1 Interrupt
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD EXTI15_10_IRQHandler ; EXTI Lines1[15:10 ]Interrupts
|
||||
DCD RTC_Alarm_IRQHandler ; RTC Alarms (A and B) Interrupt
|
||||
DCD 0 ; Reserved
|
||||
DCD PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
|
||||
DCD IPCC_C1_RX_IRQHandler ; IPCC CPU1 RX occupied interrupt
|
||||
DCD IPCC_C1_TX_IRQHandler ; IPCC CPU1 RX free interrupt
|
||||
DCD HSEM_IRQHandler ; HSEM0 Interrupt
|
||||
DCD LPTIM1_IRQHandler ; LPTIM1 Interrupt
|
||||
DCD LPTIM2_IRQHandler ; LPTIM2 Interrupt
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD AES2_IRQHandler ; AES2 Interrupt
|
||||
DCD RNG_IRQHandler ; RNG1 Interrupt
|
||||
DCD FPU_IRQHandler ; FPU Interrupt
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD DMAMUX1_OVR_IRQHandler ; DMAMUX overrun Interrupt
|
||||
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
;;
|
||||
;; Default interrupt handlers.
|
||||
;;
|
||||
THUMB
|
||||
|
||||
PUBWEAK Reset_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(2)
|
||||
Reset_Handler
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__iar_program_start
|
||||
BX R0
|
||||
|
||||
PUBWEAK NMI_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
NMI_Handler
|
||||
B NMI_Handler
|
||||
|
||||
PUBWEAK HardFault_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
HardFault_Handler
|
||||
B HardFault_Handler
|
||||
|
||||
PUBWEAK MemManage_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
MemManage_Handler
|
||||
B MemManage_Handler
|
||||
|
||||
PUBWEAK BusFault_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
BusFault_Handler
|
||||
B BusFault_Handler
|
||||
|
||||
PUBWEAK UsageFault_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
UsageFault_Handler
|
||||
B UsageFault_Handler
|
||||
|
||||
PUBWEAK SVC_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SVC_Handler
|
||||
B SVC_Handler
|
||||
|
||||
PUBWEAK DebugMon_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DebugMon_Handler
|
||||
B DebugMon_Handler
|
||||
|
||||
PUBWEAK PendSV_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
PendSV_Handler
|
||||
B PendSV_Handler
|
||||
|
||||
PUBWEAK SysTick_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SysTick_Handler
|
||||
B SysTick_Handler
|
||||
|
||||
PUBWEAK WWDG_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
WWDG_IRQHandler
|
||||
B WWDG_IRQHandler
|
||||
|
||||
PUBWEAK PVD_PVM_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
PVD_PVM_IRQHandler
|
||||
B PVD_PVM_IRQHandler
|
||||
|
||||
PUBWEAK TAMP_STAMP_LSECSS_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TAMP_STAMP_LSECSS_IRQHandler
|
||||
B TAMP_STAMP_LSECSS_IRQHandler
|
||||
|
||||
PUBWEAK RTC_WKUP_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
RTC_WKUP_IRQHandler
|
||||
B RTC_WKUP_IRQHandler
|
||||
|
||||
PUBWEAK FLASH_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
FLASH_IRQHandler
|
||||
B FLASH_IRQHandler
|
||||
|
||||
PUBWEAK RCC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
RCC_IRQHandler
|
||||
B RCC_IRQHandler
|
||||
|
||||
PUBWEAK EXTI0_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI0_IRQHandler
|
||||
B EXTI0_IRQHandler
|
||||
|
||||
PUBWEAK EXTI1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI1_IRQHandler
|
||||
B EXTI1_IRQHandler
|
||||
|
||||
PUBWEAK EXTI2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI2_IRQHandler
|
||||
B EXTI2_IRQHandler
|
||||
|
||||
PUBWEAK EXTI3_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI3_IRQHandler
|
||||
B EXTI3_IRQHandler
|
||||
|
||||
PUBWEAK EXTI4_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI4_IRQHandler
|
||||
B EXTI4_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel1_IRQHandler
|
||||
B DMA1_Channel1_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel2_IRQHandler
|
||||
B DMA1_Channel2_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel3_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel3_IRQHandler
|
||||
B DMA1_Channel3_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel4_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel4_IRQHandler
|
||||
B DMA1_Channel4_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel5_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel5_IRQHandler
|
||||
B DMA1_Channel5_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel6_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel6_IRQHandler
|
||||
B DMA1_Channel6_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel7_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel7_IRQHandler
|
||||
B DMA1_Channel7_IRQHandler
|
||||
|
||||
PUBWEAK ADC1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
ADC1_IRQHandler
|
||||
B ADC1_IRQHandler
|
||||
|
||||
PUBWEAK C2SEV_PWR_C2H_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
C2SEV_PWR_C2H_IRQHandler
|
||||
B C2SEV_PWR_C2H_IRQHandler
|
||||
|
||||
PUBWEAK EXTI9_5_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI9_5_IRQHandler
|
||||
B EXTI9_5_IRQHandler
|
||||
|
||||
PUBWEAK TIM1_BRK_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM1_BRK_IRQHandler
|
||||
B TIM1_BRK_IRQHandler
|
||||
|
||||
PUBWEAK TIM1_UP_TIM16_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM1_UP_TIM16_IRQHandler
|
||||
B TIM1_UP_TIM16_IRQHandler
|
||||
|
||||
PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM1_TRG_COM_TIM17_IRQHandler
|
||||
B TIM1_TRG_COM_TIM17_IRQHandler
|
||||
|
||||
PUBWEAK TIM1_CC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM1_CC_IRQHandler
|
||||
B TIM1_CC_IRQHandler
|
||||
|
||||
PUBWEAK TIM2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM2_IRQHandler
|
||||
B TIM2_IRQHandler
|
||||
|
||||
PUBWEAK PKA_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
PKA_IRQHandler
|
||||
B PKA_IRQHandler
|
||||
|
||||
PUBWEAK I2C1_EV_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C1_EV_IRQHandler
|
||||
B I2C1_EV_IRQHandler
|
||||
|
||||
PUBWEAK I2C1_ER_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C1_ER_IRQHandler
|
||||
B I2C1_ER_IRQHandler
|
||||
|
||||
PUBWEAK SPI1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SPI1_IRQHandler
|
||||
B SPI1_IRQHandler
|
||||
|
||||
PUBWEAK USART1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
USART1_IRQHandler
|
||||
B USART1_IRQHandler
|
||||
|
||||
PUBWEAK EXTI15_10_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI15_10_IRQHandler
|
||||
B EXTI15_10_IRQHandler
|
||||
|
||||
PUBWEAK RTC_Alarm_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
RTC_Alarm_IRQHandler
|
||||
B RTC_Alarm_IRQHandler
|
||||
|
||||
PUBWEAK PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
|
||||
B PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
|
||||
|
||||
PUBWEAK IPCC_C1_RX_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IPCC_C1_RX_IRQHandler
|
||||
B IPCC_C1_RX_IRQHandler
|
||||
|
||||
PUBWEAK IPCC_C1_TX_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IPCC_C1_TX_IRQHandler
|
||||
B IPCC_C1_TX_IRQHandler
|
||||
|
||||
PUBWEAK HSEM_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
HSEM_IRQHandler
|
||||
B HSEM_IRQHandler
|
||||
|
||||
PUBWEAK LPTIM1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
LPTIM1_IRQHandler
|
||||
B LPTIM1_IRQHandler
|
||||
|
||||
PUBWEAK LPTIM2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
LPTIM2_IRQHandler
|
||||
B LPTIM2_IRQHandler
|
||||
|
||||
PUBWEAK AES2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
AES2_IRQHandler
|
||||
B AES2_IRQHandler
|
||||
|
||||
PUBWEAK RNG_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
RNG_IRQHandler
|
||||
B RNG_IRQHandler
|
||||
|
||||
PUBWEAK FPU_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
FPU_IRQHandler
|
||||
B FPU_IRQHandler
|
||||
|
||||
PUBWEAK DMAMUX1_OVR_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMAMUX1_OVR_IRQHandler
|
||||
B DMAMUX1_OVR_IRQHandler
|
||||
|
||||
END
|
||||
|
||||
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
||||
|
|
@ -1,496 +0,0 @@
|
|||
;******************************************************************************
|
||||
;* File Name : startup_stm32wb35xx_cm4.s
|
||||
;* Author : MCD Application Team
|
||||
;* Description : M4 core vector table of the STM32WB35xx devices for the
|
||||
;* IAR (EWARM) toolchain.
|
||||
;*
|
||||
;* This module performs:
|
||||
;* - Set the initial SP
|
||||
;* - Set the initial PC == _iar_program_start,
|
||||
;* - Set the vector table entries with the exceptions ISR
|
||||
;* address.
|
||||
;* - Branches to main in the C library (which eventually
|
||||
;* calls main()).
|
||||
;* After Reset the Cortex-M4 processor is in Thread mode,
|
||||
;* priority is Privileged, and the Stack is set to Main.
|
||||
;******************************************************************************
|
||||
;* @attention
|
||||
;*
|
||||
;* Copyright (c) 2019-2021 STMicroelectronics.
|
||||
;* All rights reserved.
|
||||
;*
|
||||
;* This software is licensed under terms that can be found in the LICENSE file
|
||||
;* in the root directory of this software component.
|
||||
;* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
;*
|
||||
;******************************************************************************
|
||||
;
|
||||
;
|
||||
; The modules in this file are included in the libraries, and may be replaced
|
||||
; by any user-defined modules that define the PUBLIC symbol _program_start or
|
||||
; a user defined start symbol.
|
||||
; To override the cstartup defined in the library, simply add your modified
|
||||
; version to the workbench project.
|
||||
;
|
||||
; The vector table is normally located at address 0.
|
||||
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
|
||||
; The name "__vector_table" has special meaning for C-SPY:
|
||||
; it is where the SP start value is found, and the NVIC vector
|
||||
; table register (VTOR) is initialized to this address if != 0.
|
||||
;
|
||||
; Cortex-M version
|
||||
;
|
||||
|
||||
MODULE ?cstartup
|
||||
|
||||
;; Forward declaration of sections.
|
||||
SECTION CSTACK:DATA:NOROOT(3)
|
||||
|
||||
SECTION .intvec:CODE:NOROOT(2)
|
||||
|
||||
EXTERN __iar_program_start
|
||||
EXTERN SystemInit
|
||||
PUBLIC __vector_table
|
||||
|
||||
DATA
|
||||
__vector_table
|
||||
DCD sfe(CSTACK)
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WWDG_IRQHandler ; Window WatchDog
|
||||
DCD PVD_PVM_IRQHandler ; PVD and PVM Interrupt
|
||||
DCD TAMP_STAMP_LSECSS_IRQHandler ; RTC Tamper, TimeStamp Interrupts and LSECSS Interrupts
|
||||
DCD RTC_WKUP_IRQHandler ; RTC Wakeup Interrupt
|
||||
DCD FLASH_IRQHandler ; FLASH global Interrupt
|
||||
DCD RCC_IRQHandler ; RCC Interrupt
|
||||
DCD EXTI0_IRQHandler ; EXTI Line 0 Interrupt
|
||||
DCD EXTI1_IRQHandler ; EXTI Line 1 Interrupt
|
||||
DCD EXTI2_IRQHandler ; EXTI Line 2 Interrupt
|
||||
DCD EXTI3_IRQHandler ; EXTI Line 3 Interrup
|
||||
DCD EXTI4_IRQHandler ; EXTI Line 4 Interrupt
|
||||
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 Interrupt
|
||||
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 Interrupt
|
||||
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 Interrupt
|
||||
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 Interrupt
|
||||
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 Interrupt
|
||||
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 Interrupt
|
||||
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 Interrupt
|
||||
DCD ADC1_IRQHandler ; ADC1 Interrupt
|
||||
DCD USB_HP_IRQHandler ; USB High Priority Interrupt
|
||||
DCD USB_LP_IRQHandler ; USB Low Priority Interrupt
|
||||
DCD C2SEV_PWR_C2H_IRQHandler ; CPU M0+ SEV Interrupt
|
||||
DCD COMP_IRQHandler ; COMP1 and COMP2 Interrupts
|
||||
DCD EXTI9_5_IRQHandler ; EXTI Lines [9:5] Interrupt
|
||||
DCD TIM1_BRK_IRQHandler ; TIM1 Break Interrupt
|
||||
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16 global Interrupts
|
||||
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Communication and TIM17 global Interrupts
|
||||
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare Interrupt
|
||||
DCD TIM2_IRQHandler ; TIM2 Global Interrupt
|
||||
DCD PKA_IRQHandler ; PKA Interrupt
|
||||
DCD I2C1_EV_IRQHandler ; I2C1 Event Interrupt
|
||||
DCD I2C1_ER_IRQHandler ; I2C1 Error Interrupt
|
||||
DCD I2C3_EV_IRQHandler ; I2C3 Event Interrupt
|
||||
DCD I2C3_ER_IRQHandler ; I2C3 Error Interrupt
|
||||
DCD SPI1_IRQHandler ; SPI1 Interrupt
|
||||
DCD 0 ; Reserved
|
||||
DCD USART1_IRQHandler ; USART1 Interrupt
|
||||
DCD LPUART1_IRQHandler ; LPUART1 Interrupt
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD EXTI15_10_IRQHandler ; EXTI Lines1[15:10 ]Interrupts
|
||||
DCD RTC_Alarm_IRQHandler ; RTC Alarms (A and B) Interrupt
|
||||
DCD CRS_IRQHandler ; CRS interrupt
|
||||
DCD PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
|
||||
DCD IPCC_C1_RX_IRQHandler ; IPCC CPU1 RX occupied interrupt
|
||||
DCD IPCC_C1_TX_IRQHandler ; IPCC CPU1 RX free interrupt
|
||||
DCD HSEM_IRQHandler ; HSEM0 Interrupt
|
||||
DCD LPTIM1_IRQHandler ; LPTIM1 Interrupt
|
||||
DCD LPTIM2_IRQHandler ; LPTIM2 Interrupt
|
||||
DCD 0 ; Reserved
|
||||
DCD QUADSPI_IRQHandler ; QUADSPI Interrupt
|
||||
DCD AES1_IRQHandler ; AES1 Interrupt
|
||||
DCD AES2_IRQHandler ; AES2 Interrupt
|
||||
DCD RNG_IRQHandler ; RNG1 Interrupt
|
||||
DCD FPU_IRQHandler ; FPU Interrupt
|
||||
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 Interrupt
|
||||
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 Interrupt
|
||||
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 Interrupt
|
||||
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 Interrupt
|
||||
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 Interrupt
|
||||
DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6 Interrupt
|
||||
DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7 Interrupt
|
||||
DCD DMAMUX1_OVR_IRQHandler ; DMAMUX overrun Interrupt
|
||||
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
;;
|
||||
;; Default interrupt handlers.
|
||||
;;
|
||||
THUMB
|
||||
|
||||
PUBWEAK Reset_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(2)
|
||||
Reset_Handler
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__iar_program_start
|
||||
BX R0
|
||||
|
||||
PUBWEAK NMI_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
NMI_Handler
|
||||
B NMI_Handler
|
||||
|
||||
PUBWEAK HardFault_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
HardFault_Handler
|
||||
B HardFault_Handler
|
||||
|
||||
PUBWEAK MemManage_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
MemManage_Handler
|
||||
B MemManage_Handler
|
||||
|
||||
PUBWEAK BusFault_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
BusFault_Handler
|
||||
B BusFault_Handler
|
||||
|
||||
PUBWEAK UsageFault_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
UsageFault_Handler
|
||||
B UsageFault_Handler
|
||||
|
||||
PUBWEAK SVC_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SVC_Handler
|
||||
B SVC_Handler
|
||||
|
||||
PUBWEAK DebugMon_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DebugMon_Handler
|
||||
B DebugMon_Handler
|
||||
|
||||
PUBWEAK PendSV_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
PendSV_Handler
|
||||
B PendSV_Handler
|
||||
|
||||
PUBWEAK SysTick_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SysTick_Handler
|
||||
B SysTick_Handler
|
||||
|
||||
PUBWEAK WWDG_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
WWDG_IRQHandler
|
||||
B WWDG_IRQHandler
|
||||
|
||||
PUBWEAK PVD_PVM_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
PVD_PVM_IRQHandler
|
||||
B PVD_PVM_IRQHandler
|
||||
|
||||
PUBWEAK TAMP_STAMP_LSECSS_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TAMP_STAMP_LSECSS_IRQHandler
|
||||
B TAMP_STAMP_LSECSS_IRQHandler
|
||||
|
||||
PUBWEAK RTC_WKUP_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
RTC_WKUP_IRQHandler
|
||||
B RTC_WKUP_IRQHandler
|
||||
|
||||
PUBWEAK FLASH_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
FLASH_IRQHandler
|
||||
B FLASH_IRQHandler
|
||||
|
||||
PUBWEAK RCC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
RCC_IRQHandler
|
||||
B RCC_IRQHandler
|
||||
|
||||
PUBWEAK EXTI0_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI0_IRQHandler
|
||||
B EXTI0_IRQHandler
|
||||
|
||||
PUBWEAK EXTI1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI1_IRQHandler
|
||||
B EXTI1_IRQHandler
|
||||
|
||||
PUBWEAK EXTI2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI2_IRQHandler
|
||||
B EXTI2_IRQHandler
|
||||
|
||||
PUBWEAK EXTI3_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI3_IRQHandler
|
||||
B EXTI3_IRQHandler
|
||||
|
||||
PUBWEAK EXTI4_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI4_IRQHandler
|
||||
B EXTI4_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel1_IRQHandler
|
||||
B DMA1_Channel1_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel2_IRQHandler
|
||||
B DMA1_Channel2_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel3_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel3_IRQHandler
|
||||
B DMA1_Channel3_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel4_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel4_IRQHandler
|
||||
B DMA1_Channel4_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel5_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel5_IRQHandler
|
||||
B DMA1_Channel5_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel6_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel6_IRQHandler
|
||||
B DMA1_Channel6_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel7_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel7_IRQHandler
|
||||
B DMA1_Channel7_IRQHandler
|
||||
|
||||
PUBWEAK ADC1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
ADC1_IRQHandler
|
||||
B ADC1_IRQHandler
|
||||
|
||||
PUBWEAK USB_HP_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
USB_HP_IRQHandler
|
||||
B USB_HP_IRQHandler
|
||||
|
||||
PUBWEAK USB_LP_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
USB_LP_IRQHandler
|
||||
B USB_LP_IRQHandler
|
||||
|
||||
PUBWEAK C2SEV_PWR_C2H_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
C2SEV_PWR_C2H_IRQHandler
|
||||
B C2SEV_PWR_C2H_IRQHandler
|
||||
|
||||
PUBWEAK COMP_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
COMP_IRQHandler
|
||||
B COMP_IRQHandler
|
||||
|
||||
PUBWEAK EXTI9_5_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI9_5_IRQHandler
|
||||
B EXTI9_5_IRQHandler
|
||||
|
||||
PUBWEAK TIM1_BRK_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM1_BRK_IRQHandler
|
||||
B TIM1_BRK_IRQHandler
|
||||
|
||||
PUBWEAK TIM1_UP_TIM16_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM1_UP_TIM16_IRQHandler
|
||||
B TIM1_UP_TIM16_IRQHandler
|
||||
|
||||
PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM1_TRG_COM_TIM17_IRQHandler
|
||||
B TIM1_TRG_COM_TIM17_IRQHandler
|
||||
|
||||
PUBWEAK TIM1_CC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM1_CC_IRQHandler
|
||||
B TIM1_CC_IRQHandler
|
||||
|
||||
PUBWEAK TIM2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM2_IRQHandler
|
||||
B TIM2_IRQHandler
|
||||
|
||||
PUBWEAK PKA_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
PKA_IRQHandler
|
||||
B PKA_IRQHandler
|
||||
|
||||
PUBWEAK I2C1_EV_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C1_EV_IRQHandler
|
||||
B I2C1_EV_IRQHandler
|
||||
|
||||
PUBWEAK I2C1_ER_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C1_ER_IRQHandler
|
||||
B I2C1_ER_IRQHandler
|
||||
|
||||
PUBWEAK I2C3_EV_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C3_EV_IRQHandler
|
||||
B I2C3_EV_IRQHandler
|
||||
|
||||
PUBWEAK I2C3_ER_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C3_ER_IRQHandler
|
||||
B I2C3_ER_IRQHandler
|
||||
|
||||
PUBWEAK SPI1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SPI1_IRQHandler
|
||||
B SPI1_IRQHandler
|
||||
|
||||
PUBWEAK USART1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
USART1_IRQHandler
|
||||
B USART1_IRQHandler
|
||||
|
||||
PUBWEAK LPUART1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
LPUART1_IRQHandler
|
||||
B LPUART1_IRQHandler
|
||||
|
||||
PUBWEAK EXTI15_10_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI15_10_IRQHandler
|
||||
B EXTI15_10_IRQHandler
|
||||
|
||||
PUBWEAK RTC_Alarm_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
RTC_Alarm_IRQHandler
|
||||
B RTC_Alarm_IRQHandler
|
||||
|
||||
PUBWEAK CRS_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
CRS_IRQHandler
|
||||
B CRS_IRQHandler
|
||||
|
||||
PUBWEAK PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
|
||||
B PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
|
||||
|
||||
PUBWEAK IPCC_C1_RX_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IPCC_C1_RX_IRQHandler
|
||||
B IPCC_C1_RX_IRQHandler
|
||||
|
||||
PUBWEAK IPCC_C1_TX_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IPCC_C1_TX_IRQHandler
|
||||
B IPCC_C1_TX_IRQHandler
|
||||
|
||||
PUBWEAK HSEM_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
HSEM_IRQHandler
|
||||
B HSEM_IRQHandler
|
||||
|
||||
PUBWEAK LPTIM1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
LPTIM1_IRQHandler
|
||||
B LPTIM1_IRQHandler
|
||||
|
||||
PUBWEAK LPTIM2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
LPTIM2_IRQHandler
|
||||
B LPTIM2_IRQHandler
|
||||
|
||||
PUBWEAK QUADSPI_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
QUADSPI_IRQHandler
|
||||
B QUADSPI_IRQHandler
|
||||
|
||||
PUBWEAK AES1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
AES1_IRQHandler
|
||||
B AES1_IRQHandler
|
||||
|
||||
PUBWEAK AES2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
AES2_IRQHandler
|
||||
B AES2_IRQHandler
|
||||
|
||||
PUBWEAK RNG_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
RNG_IRQHandler
|
||||
B RNG_IRQHandler
|
||||
|
||||
PUBWEAK FPU_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
FPU_IRQHandler
|
||||
B FPU_IRQHandler
|
||||
|
||||
PUBWEAK DMA2_Channel1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA2_Channel1_IRQHandler
|
||||
B DMA2_Channel1_IRQHandler
|
||||
|
||||
PUBWEAK DMA2_Channel2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA2_Channel2_IRQHandler
|
||||
B DMA2_Channel2_IRQHandler
|
||||
|
||||
PUBWEAK DMA2_Channel3_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA2_Channel3_IRQHandler
|
||||
B DMA2_Channel3_IRQHandler
|
||||
|
||||
PUBWEAK DMA2_Channel4_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA2_Channel4_IRQHandler
|
||||
B DMA2_Channel4_IRQHandler
|
||||
|
||||
PUBWEAK DMA2_Channel5_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA2_Channel5_IRQHandler
|
||||
B DMA2_Channel5_IRQHandler
|
||||
|
||||
PUBWEAK DMA2_Channel6_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA2_Channel6_IRQHandler
|
||||
B DMA2_Channel6_IRQHandler
|
||||
|
||||
PUBWEAK DMA2_Channel7_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA2_Channel7_IRQHandler
|
||||
B DMA2_Channel7_IRQHandler
|
||||
|
||||
PUBWEAK DMAMUX1_OVR_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMAMUX1_OVR_IRQHandler
|
||||
B DMAMUX1_OVR_IRQHandler
|
||||
|
||||
END
|
||||
|
||||
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
||||
|
|
@ -1,416 +0,0 @@
|
|||
;******************************************************************************
|
||||
;* File Name : startup_stm32wb50xx_cm4.s
|
||||
;* Author : MCD Application Team
|
||||
;* Description : M4 core vector table of the STM32WB50xx devices for the
|
||||
;* IAR (EWARM) toolchain.
|
||||
;*
|
||||
;* This module performs:
|
||||
;* - Set the initial SP
|
||||
;* - Set the initial PC == _iar_program_start,
|
||||
;* - Set the vector table entries with the exceptions ISR
|
||||
;* address.
|
||||
;* - Branches to main in the C library (which eventually
|
||||
;* calls main()).
|
||||
;* After Reset the Cortex-M4 processor is in Thread mode,
|
||||
;* priority is Privileged, and the Stack is set to Main.
|
||||
;******************************************************************************
|
||||
;* @attention
|
||||
;*
|
||||
;* Copyright (c) 2019-2021 STMicroelectronics.
|
||||
;* All rights reserved.
|
||||
;*
|
||||
;* This software is licensed under terms that can be found in the LICENSE file
|
||||
;* in the root directory of this software component.
|
||||
;* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
;*
|
||||
;******************************************************************************
|
||||
;
|
||||
;
|
||||
; The modules in this file are included in the libraries, and may be replaced
|
||||
; by any user-defined modules that define the PUBLIC symbol _program_start or
|
||||
; a user defined start symbol.
|
||||
; To override the cstartup defined in the library, simply add your modified
|
||||
; version to the workbench project.
|
||||
;
|
||||
; The vector table is normally located at address 0.
|
||||
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
|
||||
; The name "__vector_table" has special meaning for C-SPY:
|
||||
; it is where the SP start value is found, and the NVIC vector
|
||||
; table register (VTOR) is initialized to this address if != 0.
|
||||
;
|
||||
; Cortex-M version
|
||||
;
|
||||
|
||||
MODULE ?cstartup
|
||||
|
||||
;; Forward declaration of sections.
|
||||
SECTION CSTACK:DATA:NOROOT(3)
|
||||
|
||||
SECTION .intvec:CODE:NOROOT(2)
|
||||
|
||||
EXTERN __iar_program_start
|
||||
EXTERN SystemInit
|
||||
PUBLIC __vector_table
|
||||
|
||||
DATA
|
||||
__vector_table
|
||||
DCD sfe(CSTACK)
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WWDG_IRQHandler ; Window WatchDog
|
||||
DCD PVD_PVM_IRQHandler ; PVD and PVM Interrupt
|
||||
DCD TAMP_STAMP_LSECSS_IRQHandler ; RTC Tamper, TimeStamp Interrupts and LSECSS Interrupts
|
||||
DCD RTC_WKUP_IRQHandler ; RTC Wakeup Interrupt
|
||||
DCD FLASH_IRQHandler ; FLASH global Interrupt
|
||||
DCD RCC_IRQHandler ; RCC Interrupt
|
||||
DCD EXTI0_IRQHandler ; EXTI Line 0 Interrupt
|
||||
DCD EXTI1_IRQHandler ; EXTI Line 1 Interrupt
|
||||
DCD EXTI2_IRQHandler ; EXTI Line 2 Interrupt
|
||||
DCD EXTI3_IRQHandler ; EXTI Line 3 Interrup
|
||||
DCD EXTI4_IRQHandler ; EXTI Line 4 Interrupt
|
||||
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 Interrupt
|
||||
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 Interrupt
|
||||
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 Interrupt
|
||||
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 Interrupt
|
||||
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 Interrupt
|
||||
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 Interrupt
|
||||
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 Interrupt
|
||||
DCD ADC1_IRQHandler ; ADC1 Interrupt
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD C2SEV_PWR_C2H_IRQHandler ; CPU M0+ SEV Interrupt
|
||||
DCD 0 ; Reserved
|
||||
DCD EXTI9_5_IRQHandler ; EXTI Lines [9:5] Interrupt
|
||||
DCD TIM1_BRK_IRQHandler ; TIM1 Break Interrupt
|
||||
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16 global Interrupts
|
||||
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Communication and TIM17 global Interrupts
|
||||
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare Interrupt
|
||||
DCD TIM2_IRQHandler ; TIM2 Global Interrupt
|
||||
DCD PKA_IRQHandler ; PKA Interrupt
|
||||
DCD I2C1_EV_IRQHandler ; I2C1 Event Interrupt
|
||||
DCD I2C1_ER_IRQHandler ; I2C1 Error Interrupt
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SPI1_IRQHandler ; SPI1 Interrupt
|
||||
DCD 0 ; Reserved
|
||||
DCD USART1_IRQHandler ; USART1 Interrupt
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD EXTI15_10_IRQHandler ; EXTI Lines1[15:10 ]Interrupts
|
||||
DCD RTC_Alarm_IRQHandler ; RTC Alarms (A and B) Interrupt
|
||||
DCD 0 ; Reserved
|
||||
DCD PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
|
||||
DCD IPCC_C1_RX_IRQHandler ; IPCC CPU1 RX occupied interrupt
|
||||
DCD IPCC_C1_TX_IRQHandler ; IPCC CPU1 RX free interrupt
|
||||
DCD HSEM_IRQHandler ; HSEM0 Interrupt
|
||||
DCD LPTIM1_IRQHandler ; LPTIM1 Interrupt
|
||||
DCD LPTIM2_IRQHandler ; LPTIM2 Interrupt
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD AES2_IRQHandler ; AES2 Interrupt
|
||||
DCD RNG_IRQHandler ; RNG1 Interrupt
|
||||
DCD FPU_IRQHandler ; FPU Interrupt
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD DMAMUX1_OVR_IRQHandler ; DMAMUX overrun Interrupt
|
||||
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
;;
|
||||
;; Default interrupt handlers.
|
||||
;;
|
||||
THUMB
|
||||
|
||||
PUBWEAK Reset_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(2)
|
||||
Reset_Handler
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__iar_program_start
|
||||
BX R0
|
||||
|
||||
PUBWEAK NMI_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
NMI_Handler
|
||||
B NMI_Handler
|
||||
|
||||
PUBWEAK HardFault_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
HardFault_Handler
|
||||
B HardFault_Handler
|
||||
|
||||
PUBWEAK MemManage_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
MemManage_Handler
|
||||
B MemManage_Handler
|
||||
|
||||
PUBWEAK BusFault_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
BusFault_Handler
|
||||
B BusFault_Handler
|
||||
|
||||
PUBWEAK UsageFault_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
UsageFault_Handler
|
||||
B UsageFault_Handler
|
||||
|
||||
PUBWEAK SVC_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SVC_Handler
|
||||
B SVC_Handler
|
||||
|
||||
PUBWEAK DebugMon_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DebugMon_Handler
|
||||
B DebugMon_Handler
|
||||
|
||||
PUBWEAK PendSV_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
PendSV_Handler
|
||||
B PendSV_Handler
|
||||
|
||||
PUBWEAK SysTick_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SysTick_Handler
|
||||
B SysTick_Handler
|
||||
|
||||
PUBWEAK WWDG_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
WWDG_IRQHandler
|
||||
B WWDG_IRQHandler
|
||||
|
||||
PUBWEAK PVD_PVM_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
PVD_PVM_IRQHandler
|
||||
B PVD_PVM_IRQHandler
|
||||
|
||||
PUBWEAK TAMP_STAMP_LSECSS_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TAMP_STAMP_LSECSS_IRQHandler
|
||||
B TAMP_STAMP_LSECSS_IRQHandler
|
||||
|
||||
PUBWEAK RTC_WKUP_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
RTC_WKUP_IRQHandler
|
||||
B RTC_WKUP_IRQHandler
|
||||
|
||||
PUBWEAK FLASH_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
FLASH_IRQHandler
|
||||
B FLASH_IRQHandler
|
||||
|
||||
PUBWEAK RCC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
RCC_IRQHandler
|
||||
B RCC_IRQHandler
|
||||
|
||||
PUBWEAK EXTI0_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI0_IRQHandler
|
||||
B EXTI0_IRQHandler
|
||||
|
||||
PUBWEAK EXTI1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI1_IRQHandler
|
||||
B EXTI1_IRQHandler
|
||||
|
||||
PUBWEAK EXTI2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI2_IRQHandler
|
||||
B EXTI2_IRQHandler
|
||||
|
||||
PUBWEAK EXTI3_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI3_IRQHandler
|
||||
B EXTI3_IRQHandler
|
||||
|
||||
PUBWEAK EXTI4_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI4_IRQHandler
|
||||
B EXTI4_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel1_IRQHandler
|
||||
B DMA1_Channel1_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel2_IRQHandler
|
||||
B DMA1_Channel2_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel3_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel3_IRQHandler
|
||||
B DMA1_Channel3_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel4_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel4_IRQHandler
|
||||
B DMA1_Channel4_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel5_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel5_IRQHandler
|
||||
B DMA1_Channel5_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel6_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel6_IRQHandler
|
||||
B DMA1_Channel6_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel7_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel7_IRQHandler
|
||||
B DMA1_Channel7_IRQHandler
|
||||
|
||||
PUBWEAK ADC1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
ADC1_IRQHandler
|
||||
B ADC1_IRQHandler
|
||||
|
||||
PUBWEAK C2SEV_PWR_C2H_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
C2SEV_PWR_C2H_IRQHandler
|
||||
B C2SEV_PWR_C2H_IRQHandler
|
||||
|
||||
PUBWEAK EXTI9_5_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI9_5_IRQHandler
|
||||
B EXTI9_5_IRQHandler
|
||||
|
||||
PUBWEAK TIM1_BRK_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM1_BRK_IRQHandler
|
||||
B TIM1_BRK_IRQHandler
|
||||
|
||||
PUBWEAK TIM1_UP_TIM16_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM1_UP_TIM16_IRQHandler
|
||||
B TIM1_UP_TIM16_IRQHandler
|
||||
|
||||
PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM1_TRG_COM_TIM17_IRQHandler
|
||||
B TIM1_TRG_COM_TIM17_IRQHandler
|
||||
|
||||
PUBWEAK TIM1_CC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM1_CC_IRQHandler
|
||||
B TIM1_CC_IRQHandler
|
||||
|
||||
PUBWEAK TIM2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM2_IRQHandler
|
||||
B TIM2_IRQHandler
|
||||
|
||||
PUBWEAK PKA_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
PKA_IRQHandler
|
||||
B PKA_IRQHandler
|
||||
|
||||
PUBWEAK I2C1_EV_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C1_EV_IRQHandler
|
||||
B I2C1_EV_IRQHandler
|
||||
|
||||
PUBWEAK I2C1_ER_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C1_ER_IRQHandler
|
||||
B I2C1_ER_IRQHandler
|
||||
|
||||
PUBWEAK SPI1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SPI1_IRQHandler
|
||||
B SPI1_IRQHandler
|
||||
|
||||
PUBWEAK USART1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
USART1_IRQHandler
|
||||
B USART1_IRQHandler
|
||||
|
||||
PUBWEAK EXTI15_10_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI15_10_IRQHandler
|
||||
B EXTI15_10_IRQHandler
|
||||
|
||||
PUBWEAK RTC_Alarm_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
RTC_Alarm_IRQHandler
|
||||
B RTC_Alarm_IRQHandler
|
||||
|
||||
PUBWEAK PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
|
||||
B PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
|
||||
|
||||
PUBWEAK IPCC_C1_RX_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IPCC_C1_RX_IRQHandler
|
||||
B IPCC_C1_RX_IRQHandler
|
||||
|
||||
PUBWEAK IPCC_C1_TX_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IPCC_C1_TX_IRQHandler
|
||||
B IPCC_C1_TX_IRQHandler
|
||||
|
||||
PUBWEAK HSEM_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
HSEM_IRQHandler
|
||||
B HSEM_IRQHandler
|
||||
|
||||
PUBWEAK LPTIM1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
LPTIM1_IRQHandler
|
||||
B LPTIM1_IRQHandler
|
||||
|
||||
PUBWEAK LPTIM2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
LPTIM2_IRQHandler
|
||||
B LPTIM2_IRQHandler
|
||||
|
||||
PUBWEAK AES2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
AES2_IRQHandler
|
||||
B AES2_IRQHandler
|
||||
|
||||
PUBWEAK RNG_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
RNG_IRQHandler
|
||||
B RNG_IRQHandler
|
||||
|
||||
PUBWEAK FPU_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
FPU_IRQHandler
|
||||
B FPU_IRQHandler
|
||||
|
||||
PUBWEAK DMAMUX1_OVR_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMAMUX1_OVR_IRQHandler
|
||||
B DMAMUX1_OVR_IRQHandler
|
||||
|
||||
END
|
||||
|
||||
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
||||
|
|
@ -1,516 +0,0 @@
|
|||
;******************************************************************************
|
||||
;* File Name : startup_stm32wb55xx_cm4.s
|
||||
;* Author : MCD Application Team
|
||||
;* Description : M4 core vector table of the STM32WB55xx devices for the
|
||||
;* IAR (EWARM) toolchain.
|
||||
;*
|
||||
;* This module performs:
|
||||
;* - Set the initial SP
|
||||
;* - Set the initial PC == _iar_program_start,
|
||||
;* - Set the vector table entries with the exceptions ISR
|
||||
;* address.
|
||||
;* - Branches to main in the C library (which eventually
|
||||
;* calls main()).
|
||||
;* After Reset the Cortex-M4 processor is in Thread mode,
|
||||
;* priority is Privileged, and the Stack is set to Main.
|
||||
;******************************************************************************
|
||||
;* @attention
|
||||
;*
|
||||
;* Copyright (c) 2019-2021 STMicroelectronics.
|
||||
;* All rights reserved.
|
||||
;*
|
||||
;* This software is licensed under terms that can be found in the LICENSE file
|
||||
;* in the root directory of this software component.
|
||||
;* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
;*
|
||||
;******************************************************************************
|
||||
;
|
||||
;
|
||||
; The modules in this file are included in the libraries, and may be replaced
|
||||
; by any user-defined modules that define the PUBLIC symbol _program_start or
|
||||
; a user defined start symbol.
|
||||
; To override the cstartup defined in the library, simply add your modified
|
||||
; version to the workbench project.
|
||||
;
|
||||
; The vector table is normally located at address 0.
|
||||
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
|
||||
; The name "__vector_table" has special meaning for C-SPY:
|
||||
; it is where the SP start value is found, and the NVIC vector
|
||||
; table register (VTOR) is initialized to this address if != 0.
|
||||
;
|
||||
; Cortex-M version
|
||||
;
|
||||
|
||||
MODULE ?cstartup
|
||||
|
||||
;; Forward declaration of sections.
|
||||
SECTION CSTACK:DATA:NOROOT(3)
|
||||
|
||||
SECTION .intvec:CODE:NOROOT(2)
|
||||
|
||||
EXTERN __iar_program_start
|
||||
EXTERN SystemInit
|
||||
PUBLIC __vector_table
|
||||
|
||||
DATA
|
||||
__vector_table
|
||||
DCD sfe(CSTACK)
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WWDG_IRQHandler ; Window WatchDog
|
||||
DCD PVD_PVM_IRQHandler ; PVD and PVM Interrupt
|
||||
DCD TAMP_STAMP_LSECSS_IRQHandler ; RTC Tamper, TimeStamp Interrupts and LSECSS Interrupts
|
||||
DCD RTC_WKUP_IRQHandler ; RTC Wakeup Interrupt
|
||||
DCD FLASH_IRQHandler ; FLASH global Interrupt
|
||||
DCD RCC_IRQHandler ; RCC Interrupt
|
||||
DCD EXTI0_IRQHandler ; EXTI Line 0 Interrupt
|
||||
DCD EXTI1_IRQHandler ; EXTI Line 1 Interrupt
|
||||
DCD EXTI2_IRQHandler ; EXTI Line 2 Interrupt
|
||||
DCD EXTI3_IRQHandler ; EXTI Line 3 Interrup
|
||||
DCD EXTI4_IRQHandler ; EXTI Line 4 Interrupt
|
||||
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 Interrupt
|
||||
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 Interrupt
|
||||
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 Interrupt
|
||||
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 Interrupt
|
||||
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 Interrupt
|
||||
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 Interrupt
|
||||
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 Interrupt
|
||||
DCD ADC1_IRQHandler ; ADC1 Interrupt
|
||||
DCD USB_HP_IRQHandler ; USB High Priority Interrupt
|
||||
DCD USB_LP_IRQHandler ; USB Low Priority Interrupt
|
||||
DCD C2SEV_PWR_C2H_IRQHandler ; CPU M0+ SEV Interrupt
|
||||
DCD COMP_IRQHandler ; COMP1 and COMP2 Interrupts
|
||||
DCD EXTI9_5_IRQHandler ; EXTI Lines [9:5] Interrupt
|
||||
DCD TIM1_BRK_IRQHandler ; TIM1 Break Interrupt
|
||||
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16 global Interrupts
|
||||
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Communication and TIM17 global Interrupts
|
||||
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare Interrupt
|
||||
DCD TIM2_IRQHandler ; TIM2 Global Interrupt
|
||||
DCD PKA_IRQHandler ; PKA Interrupt
|
||||
DCD I2C1_EV_IRQHandler ; I2C1 Event Interrupt
|
||||
DCD I2C1_ER_IRQHandler ; I2C1 Error Interrupt
|
||||
DCD I2C3_EV_IRQHandler ; I2C3 Event Interrupt
|
||||
DCD I2C3_ER_IRQHandler ; I2C3 Error Interrupt
|
||||
DCD SPI1_IRQHandler ; SPI1 Interrupt
|
||||
DCD SPI2_IRQHandler ; SPI2 Interrupt
|
||||
DCD USART1_IRQHandler ; USART1 Interrupt
|
||||
DCD LPUART1_IRQHandler ; LPUART1 Interrupt
|
||||
DCD SAI1_IRQHandler ; SAI Interrupt
|
||||
DCD TSC_IRQHandler ; TSC Interrupt
|
||||
DCD EXTI15_10_IRQHandler ; EXTI Lines1[15:10 ]Interrupts
|
||||
DCD RTC_Alarm_IRQHandler ; RTC Alarms (A and B) Interrupt
|
||||
DCD CRS_IRQHandler ; CRS interrupt
|
||||
DCD PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
|
||||
DCD IPCC_C1_RX_IRQHandler ; IPCC CPU1 RX occupied interrupt
|
||||
DCD IPCC_C1_TX_IRQHandler ; IPCC CPU1 RX free interrupt
|
||||
DCD HSEM_IRQHandler ; HSEM0 Interrupt
|
||||
DCD LPTIM1_IRQHandler ; LPTIM1 Interrupt
|
||||
DCD LPTIM2_IRQHandler ; LPTIM2 Interrupt
|
||||
DCD LCD_IRQHandler ; LCD Interrupt
|
||||
DCD QUADSPI_IRQHandler ; QUADSPI Interrupt
|
||||
DCD AES1_IRQHandler ; AES1 Interrupt
|
||||
DCD AES2_IRQHandler ; AES2 Interrupt
|
||||
DCD RNG_IRQHandler ; RNG1 Interrupt
|
||||
DCD FPU_IRQHandler ; FPU Interrupt
|
||||
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 Interrupt
|
||||
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 Interrupt
|
||||
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 Interrupt
|
||||
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 Interrupt
|
||||
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 Interrupt
|
||||
DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6 Interrupt
|
||||
DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7 Interrupt
|
||||
DCD DMAMUX1_OVR_IRQHandler ; DMAMUX overrun Interrupt
|
||||
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
;;
|
||||
;; Default interrupt handlers.
|
||||
;;
|
||||
THUMB
|
||||
|
||||
PUBWEAK Reset_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(2)
|
||||
Reset_Handler
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__iar_program_start
|
||||
BX R0
|
||||
|
||||
PUBWEAK NMI_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
NMI_Handler
|
||||
B NMI_Handler
|
||||
|
||||
PUBWEAK HardFault_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
HardFault_Handler
|
||||
B HardFault_Handler
|
||||
|
||||
PUBWEAK MemManage_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
MemManage_Handler
|
||||
B MemManage_Handler
|
||||
|
||||
PUBWEAK BusFault_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
BusFault_Handler
|
||||
B BusFault_Handler
|
||||
|
||||
PUBWEAK UsageFault_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
UsageFault_Handler
|
||||
B UsageFault_Handler
|
||||
|
||||
PUBWEAK SVC_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SVC_Handler
|
||||
B SVC_Handler
|
||||
|
||||
PUBWEAK DebugMon_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DebugMon_Handler
|
||||
B DebugMon_Handler
|
||||
|
||||
PUBWEAK PendSV_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
PendSV_Handler
|
||||
B PendSV_Handler
|
||||
|
||||
PUBWEAK SysTick_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SysTick_Handler
|
||||
B SysTick_Handler
|
||||
|
||||
PUBWEAK WWDG_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
WWDG_IRQHandler
|
||||
B WWDG_IRQHandler
|
||||
|
||||
PUBWEAK PVD_PVM_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
PVD_PVM_IRQHandler
|
||||
B PVD_PVM_IRQHandler
|
||||
|
||||
PUBWEAK TAMP_STAMP_LSECSS_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TAMP_STAMP_LSECSS_IRQHandler
|
||||
B TAMP_STAMP_LSECSS_IRQHandler
|
||||
|
||||
PUBWEAK RTC_WKUP_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
RTC_WKUP_IRQHandler
|
||||
B RTC_WKUP_IRQHandler
|
||||
|
||||
PUBWEAK FLASH_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
FLASH_IRQHandler
|
||||
B FLASH_IRQHandler
|
||||
|
||||
PUBWEAK RCC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
RCC_IRQHandler
|
||||
B RCC_IRQHandler
|
||||
|
||||
PUBWEAK EXTI0_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI0_IRQHandler
|
||||
B EXTI0_IRQHandler
|
||||
|
||||
PUBWEAK EXTI1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI1_IRQHandler
|
||||
B EXTI1_IRQHandler
|
||||
|
||||
PUBWEAK EXTI2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI2_IRQHandler
|
||||
B EXTI2_IRQHandler
|
||||
|
||||
PUBWEAK EXTI3_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI3_IRQHandler
|
||||
B EXTI3_IRQHandler
|
||||
|
||||
PUBWEAK EXTI4_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI4_IRQHandler
|
||||
B EXTI4_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel1_IRQHandler
|
||||
B DMA1_Channel1_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel2_IRQHandler
|
||||
B DMA1_Channel2_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel3_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel3_IRQHandler
|
||||
B DMA1_Channel3_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel4_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel4_IRQHandler
|
||||
B DMA1_Channel4_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel5_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel5_IRQHandler
|
||||
B DMA1_Channel5_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel6_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel6_IRQHandler
|
||||
B DMA1_Channel6_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel7_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel7_IRQHandler
|
||||
B DMA1_Channel7_IRQHandler
|
||||
|
||||
PUBWEAK ADC1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
ADC1_IRQHandler
|
||||
B ADC1_IRQHandler
|
||||
|
||||
PUBWEAK USB_HP_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
USB_HP_IRQHandler
|
||||
B USB_HP_IRQHandler
|
||||
|
||||
PUBWEAK USB_LP_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
USB_LP_IRQHandler
|
||||
B USB_LP_IRQHandler
|
||||
|
||||
PUBWEAK C2SEV_PWR_C2H_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
C2SEV_PWR_C2H_IRQHandler
|
||||
B C2SEV_PWR_C2H_IRQHandler
|
||||
|
||||
PUBWEAK COMP_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
COMP_IRQHandler
|
||||
B COMP_IRQHandler
|
||||
|
||||
PUBWEAK EXTI9_5_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI9_5_IRQHandler
|
||||
B EXTI9_5_IRQHandler
|
||||
|
||||
PUBWEAK TIM1_BRK_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM1_BRK_IRQHandler
|
||||
B TIM1_BRK_IRQHandler
|
||||
|
||||
PUBWEAK TIM1_UP_TIM16_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM1_UP_TIM16_IRQHandler
|
||||
B TIM1_UP_TIM16_IRQHandler
|
||||
|
||||
PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM1_TRG_COM_TIM17_IRQHandler
|
||||
B TIM1_TRG_COM_TIM17_IRQHandler
|
||||
|
||||
PUBWEAK TIM1_CC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM1_CC_IRQHandler
|
||||
B TIM1_CC_IRQHandler
|
||||
|
||||
PUBWEAK TIM2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM2_IRQHandler
|
||||
B TIM2_IRQHandler
|
||||
|
||||
PUBWEAK PKA_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
PKA_IRQHandler
|
||||
B PKA_IRQHandler
|
||||
|
||||
PUBWEAK I2C1_EV_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C1_EV_IRQHandler
|
||||
B I2C1_EV_IRQHandler
|
||||
|
||||
PUBWEAK I2C1_ER_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C1_ER_IRQHandler
|
||||
B I2C1_ER_IRQHandler
|
||||
|
||||
PUBWEAK I2C3_EV_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C3_EV_IRQHandler
|
||||
B I2C3_EV_IRQHandler
|
||||
|
||||
PUBWEAK I2C3_ER_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C3_ER_IRQHandler
|
||||
B I2C3_ER_IRQHandler
|
||||
|
||||
PUBWEAK SPI1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SPI1_IRQHandler
|
||||
B SPI1_IRQHandler
|
||||
|
||||
PUBWEAK SPI2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SPI2_IRQHandler
|
||||
B SPI2_IRQHandler
|
||||
|
||||
PUBWEAK USART1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
USART1_IRQHandler
|
||||
B USART1_IRQHandler
|
||||
|
||||
PUBWEAK LPUART1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
LPUART1_IRQHandler
|
||||
B LPUART1_IRQHandler
|
||||
|
||||
PUBWEAK SAI1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SAI1_IRQHandler
|
||||
B SAI1_IRQHandler
|
||||
|
||||
PUBWEAK TSC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TSC_IRQHandler
|
||||
B TSC_IRQHandler
|
||||
|
||||
PUBWEAK EXTI15_10_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI15_10_IRQHandler
|
||||
B EXTI15_10_IRQHandler
|
||||
|
||||
PUBWEAK RTC_Alarm_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
RTC_Alarm_IRQHandler
|
||||
B RTC_Alarm_IRQHandler
|
||||
|
||||
PUBWEAK CRS_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
CRS_IRQHandler
|
||||
B CRS_IRQHandler
|
||||
|
||||
PUBWEAK PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
|
||||
B PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
|
||||
|
||||
PUBWEAK IPCC_C1_RX_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IPCC_C1_RX_IRQHandler
|
||||
B IPCC_C1_RX_IRQHandler
|
||||
|
||||
PUBWEAK IPCC_C1_TX_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IPCC_C1_TX_IRQHandler
|
||||
B IPCC_C1_TX_IRQHandler
|
||||
|
||||
PUBWEAK HSEM_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
HSEM_IRQHandler
|
||||
B HSEM_IRQHandler
|
||||
|
||||
PUBWEAK LPTIM1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
LPTIM1_IRQHandler
|
||||
B LPTIM1_IRQHandler
|
||||
|
||||
PUBWEAK LPTIM2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
LPTIM2_IRQHandler
|
||||
B LPTIM2_IRQHandler
|
||||
|
||||
PUBWEAK LCD_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
LCD_IRQHandler
|
||||
B LCD_IRQHandler
|
||||
|
||||
PUBWEAK QUADSPI_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
QUADSPI_IRQHandler
|
||||
B QUADSPI_IRQHandler
|
||||
|
||||
PUBWEAK AES1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
AES1_IRQHandler
|
||||
B AES1_IRQHandler
|
||||
|
||||
PUBWEAK AES2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
AES2_IRQHandler
|
||||
B AES2_IRQHandler
|
||||
|
||||
PUBWEAK RNG_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
RNG_IRQHandler
|
||||
B RNG_IRQHandler
|
||||
|
||||
PUBWEAK FPU_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
FPU_IRQHandler
|
||||
B FPU_IRQHandler
|
||||
|
||||
PUBWEAK DMA2_Channel1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA2_Channel1_IRQHandler
|
||||
B DMA2_Channel1_IRQHandler
|
||||
|
||||
PUBWEAK DMA2_Channel2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA2_Channel2_IRQHandler
|
||||
B DMA2_Channel2_IRQHandler
|
||||
|
||||
PUBWEAK DMA2_Channel3_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA2_Channel3_IRQHandler
|
||||
B DMA2_Channel3_IRQHandler
|
||||
|
||||
PUBWEAK DMA2_Channel4_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA2_Channel4_IRQHandler
|
||||
B DMA2_Channel4_IRQHandler
|
||||
|
||||
PUBWEAK DMA2_Channel5_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA2_Channel5_IRQHandler
|
||||
B DMA2_Channel5_IRQHandler
|
||||
|
||||
PUBWEAK DMA2_Channel6_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA2_Channel6_IRQHandler
|
||||
B DMA2_Channel6_IRQHandler
|
||||
|
||||
PUBWEAK DMA2_Channel7_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA2_Channel7_IRQHandler
|
||||
B DMA2_Channel7_IRQHandler
|
||||
|
||||
PUBWEAK DMAMUX1_OVR_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMAMUX1_OVR_IRQHandler
|
||||
B DMAMUX1_OVR_IRQHandler
|
||||
|
||||
END
|
||||
|
||||
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
||||
|
|
@ -1,516 +0,0 @@
|
|||
;******************************************************************************
|
||||
;* File Name : startup_stm32wb5mxx_cm4.s
|
||||
;* Author : MCD Application Team
|
||||
;* Description : M4 core vector table of the STM32WB5Mxx devices for the
|
||||
;* IAR (EWARM) toolchain.
|
||||
;*
|
||||
;* This module performs:
|
||||
;* - Set the initial SP
|
||||
;* - Set the initial PC == _iar_program_start,
|
||||
;* - Set the vector table entries with the exceptions ISR
|
||||
;* address.
|
||||
;* - Branches to main in the C library (which eventually
|
||||
;* calls main()).
|
||||
;* After Reset the Cortex-M4 processor is in Thread mode,
|
||||
;* priority is Privileged, and the Stack is set to Main.
|
||||
;******************************************************************************
|
||||
;* @attention
|
||||
;*
|
||||
;* Copyright (c) 2019-2021 STMicroelectronics.
|
||||
;* All rights reserved.
|
||||
;*
|
||||
;* This software is licensed under terms that can be found in the LICENSE file
|
||||
;* in the root directory of this software component.
|
||||
;* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
;*
|
||||
;******************************************************************************
|
||||
;
|
||||
;
|
||||
; The modules in this file are included in the libraries, and may be replaced
|
||||
; by any user-defined modules that define the PUBLIC symbol _program_start or
|
||||
; a user defined start symbol.
|
||||
; To override the cstartup defined in the library, simply add your modified
|
||||
; version to the workbench project.
|
||||
;
|
||||
; The vector table is normally located at address 0.
|
||||
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
|
||||
; The name "__vector_table" has special meaning for C-SPY:
|
||||
; it is where the SP start value is found, and the NVIC vector
|
||||
; table register (VTOR) is initialized to this address if != 0.
|
||||
;
|
||||
; Cortex-M version
|
||||
;
|
||||
|
||||
MODULE ?cstartup
|
||||
|
||||
;; Forward declaration of sections.
|
||||
SECTION CSTACK:DATA:NOROOT(3)
|
||||
|
||||
SECTION .intvec:CODE:NOROOT(2)
|
||||
|
||||
EXTERN __iar_program_start
|
||||
EXTERN SystemInit
|
||||
PUBLIC __vector_table
|
||||
|
||||
DATA
|
||||
__vector_table
|
||||
DCD sfe(CSTACK)
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WWDG_IRQHandler ; Window WatchDog
|
||||
DCD PVD_PVM_IRQHandler ; PVD and PVM Interrupt
|
||||
DCD TAMP_STAMP_LSECSS_IRQHandler ; RTC Tamper, TimeStamp Interrupts and LSECSS Interrupts
|
||||
DCD RTC_WKUP_IRQHandler ; RTC Wakeup Interrupt
|
||||
DCD FLASH_IRQHandler ; FLASH global Interrupt
|
||||
DCD RCC_IRQHandler ; RCC Interrupt
|
||||
DCD EXTI0_IRQHandler ; EXTI Line 0 Interrupt
|
||||
DCD EXTI1_IRQHandler ; EXTI Line 1 Interrupt
|
||||
DCD EXTI2_IRQHandler ; EXTI Line 2 Interrupt
|
||||
DCD EXTI3_IRQHandler ; EXTI Line 3 Interrup
|
||||
DCD EXTI4_IRQHandler ; EXTI Line 4 Interrupt
|
||||
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 Interrupt
|
||||
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 Interrupt
|
||||
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 Interrupt
|
||||
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 Interrupt
|
||||
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 Interrupt
|
||||
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 Interrupt
|
||||
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 Interrupt
|
||||
DCD ADC1_IRQHandler ; ADC1 Interrupt
|
||||
DCD USB_HP_IRQHandler ; USB High Priority Interrupt
|
||||
DCD USB_LP_IRQHandler ; USB Low Priority Interrupt
|
||||
DCD C2SEV_PWR_C2H_IRQHandler ; CPU M0+ SEV Interrupt
|
||||
DCD COMP_IRQHandler ; COMP1 and COMP2 Interrupts
|
||||
DCD EXTI9_5_IRQHandler ; EXTI Lines [9:5] Interrupt
|
||||
DCD TIM1_BRK_IRQHandler ; TIM1 Break Interrupt
|
||||
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16 global Interrupts
|
||||
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Communication and TIM17 global Interrupts
|
||||
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare Interrupt
|
||||
DCD TIM2_IRQHandler ; TIM2 Global Interrupt
|
||||
DCD PKA_IRQHandler ; PKA Interrupt
|
||||
DCD I2C1_EV_IRQHandler ; I2C1 Event Interrupt
|
||||
DCD I2C1_ER_IRQHandler ; I2C1 Error Interrupt
|
||||
DCD I2C3_EV_IRQHandler ; I2C3 Event Interrupt
|
||||
DCD I2C3_ER_IRQHandler ; I2C3 Error Interrupt
|
||||
DCD SPI1_IRQHandler ; SPI1 Interrupt
|
||||
DCD SPI2_IRQHandler ; SPI2 Interrupt
|
||||
DCD USART1_IRQHandler ; USART1 Interrupt
|
||||
DCD LPUART1_IRQHandler ; LPUART1 Interrupt
|
||||
DCD SAI1_IRQHandler ; SAI Interrupt
|
||||
DCD TSC_IRQHandler ; TSC Interrupt
|
||||
DCD EXTI15_10_IRQHandler ; EXTI Lines1[15:10 ]Interrupts
|
||||
DCD RTC_Alarm_IRQHandler ; RTC Alarms (A and B) Interrupt
|
||||
DCD CRS_IRQHandler ; CRS interrupt
|
||||
DCD PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
|
||||
DCD IPCC_C1_RX_IRQHandler ; IPCC CPU1 RX occupied interrupt
|
||||
DCD IPCC_C1_TX_IRQHandler ; IPCC CPU1 RX free interrupt
|
||||
DCD HSEM_IRQHandler ; HSEM0 Interrupt
|
||||
DCD LPTIM1_IRQHandler ; LPTIM1 Interrupt
|
||||
DCD LPTIM2_IRQHandler ; LPTIM2 Interrupt
|
||||
DCD LCD_IRQHandler ; LCD Interrupt
|
||||
DCD QUADSPI_IRQHandler ; QUADSPI Interrupt
|
||||
DCD AES1_IRQHandler ; AES1 Interrupt
|
||||
DCD AES2_IRQHandler ; AES2 Interrupt
|
||||
DCD RNG_IRQHandler ; RNG1 Interrupt
|
||||
DCD FPU_IRQHandler ; FPU Interrupt
|
||||
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 Interrupt
|
||||
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 Interrupt
|
||||
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 Interrupt
|
||||
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 Interrupt
|
||||
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 Interrupt
|
||||
DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6 Interrupt
|
||||
DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7 Interrupt
|
||||
DCD DMAMUX1_OVR_IRQHandler ; DMAMUX overrun Interrupt
|
||||
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
;;
|
||||
;; Default interrupt handlers.
|
||||
;;
|
||||
THUMB
|
||||
|
||||
PUBWEAK Reset_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(2)
|
||||
Reset_Handler
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__iar_program_start
|
||||
BX R0
|
||||
|
||||
PUBWEAK NMI_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
NMI_Handler
|
||||
B NMI_Handler
|
||||
|
||||
PUBWEAK HardFault_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
HardFault_Handler
|
||||
B HardFault_Handler
|
||||
|
||||
PUBWEAK MemManage_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
MemManage_Handler
|
||||
B MemManage_Handler
|
||||
|
||||
PUBWEAK BusFault_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
BusFault_Handler
|
||||
B BusFault_Handler
|
||||
|
||||
PUBWEAK UsageFault_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
UsageFault_Handler
|
||||
B UsageFault_Handler
|
||||
|
||||
PUBWEAK SVC_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SVC_Handler
|
||||
B SVC_Handler
|
||||
|
||||
PUBWEAK DebugMon_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DebugMon_Handler
|
||||
B DebugMon_Handler
|
||||
|
||||
PUBWEAK PendSV_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
PendSV_Handler
|
||||
B PendSV_Handler
|
||||
|
||||
PUBWEAK SysTick_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SysTick_Handler
|
||||
B SysTick_Handler
|
||||
|
||||
PUBWEAK WWDG_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
WWDG_IRQHandler
|
||||
B WWDG_IRQHandler
|
||||
|
||||
PUBWEAK PVD_PVM_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
PVD_PVM_IRQHandler
|
||||
B PVD_PVM_IRQHandler
|
||||
|
||||
PUBWEAK TAMP_STAMP_LSECSS_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TAMP_STAMP_LSECSS_IRQHandler
|
||||
B TAMP_STAMP_LSECSS_IRQHandler
|
||||
|
||||
PUBWEAK RTC_WKUP_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
RTC_WKUP_IRQHandler
|
||||
B RTC_WKUP_IRQHandler
|
||||
|
||||
PUBWEAK FLASH_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
FLASH_IRQHandler
|
||||
B FLASH_IRQHandler
|
||||
|
||||
PUBWEAK RCC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
RCC_IRQHandler
|
||||
B RCC_IRQHandler
|
||||
|
||||
PUBWEAK EXTI0_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI0_IRQHandler
|
||||
B EXTI0_IRQHandler
|
||||
|
||||
PUBWEAK EXTI1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI1_IRQHandler
|
||||
B EXTI1_IRQHandler
|
||||
|
||||
PUBWEAK EXTI2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI2_IRQHandler
|
||||
B EXTI2_IRQHandler
|
||||
|
||||
PUBWEAK EXTI3_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI3_IRQHandler
|
||||
B EXTI3_IRQHandler
|
||||
|
||||
PUBWEAK EXTI4_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI4_IRQHandler
|
||||
B EXTI4_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel1_IRQHandler
|
||||
B DMA1_Channel1_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel2_IRQHandler
|
||||
B DMA1_Channel2_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel3_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel3_IRQHandler
|
||||
B DMA1_Channel3_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel4_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel4_IRQHandler
|
||||
B DMA1_Channel4_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel5_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel5_IRQHandler
|
||||
B DMA1_Channel5_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel6_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel6_IRQHandler
|
||||
B DMA1_Channel6_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel7_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel7_IRQHandler
|
||||
B DMA1_Channel7_IRQHandler
|
||||
|
||||
PUBWEAK ADC1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
ADC1_IRQHandler
|
||||
B ADC1_IRQHandler
|
||||
|
||||
PUBWEAK USB_HP_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
USB_HP_IRQHandler
|
||||
B USB_HP_IRQHandler
|
||||
|
||||
PUBWEAK USB_LP_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
USB_LP_IRQHandler
|
||||
B USB_LP_IRQHandler
|
||||
|
||||
PUBWEAK C2SEV_PWR_C2H_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
C2SEV_PWR_C2H_IRQHandler
|
||||
B C2SEV_PWR_C2H_IRQHandler
|
||||
|
||||
PUBWEAK COMP_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
COMP_IRQHandler
|
||||
B COMP_IRQHandler
|
||||
|
||||
PUBWEAK EXTI9_5_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI9_5_IRQHandler
|
||||
B EXTI9_5_IRQHandler
|
||||
|
||||
PUBWEAK TIM1_BRK_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM1_BRK_IRQHandler
|
||||
B TIM1_BRK_IRQHandler
|
||||
|
||||
PUBWEAK TIM1_UP_TIM16_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM1_UP_TIM16_IRQHandler
|
||||
B TIM1_UP_TIM16_IRQHandler
|
||||
|
||||
PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM1_TRG_COM_TIM17_IRQHandler
|
||||
B TIM1_TRG_COM_TIM17_IRQHandler
|
||||
|
||||
PUBWEAK TIM1_CC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM1_CC_IRQHandler
|
||||
B TIM1_CC_IRQHandler
|
||||
|
||||
PUBWEAK TIM2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM2_IRQHandler
|
||||
B TIM2_IRQHandler
|
||||
|
||||
PUBWEAK PKA_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
PKA_IRQHandler
|
||||
B PKA_IRQHandler
|
||||
|
||||
PUBWEAK I2C1_EV_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C1_EV_IRQHandler
|
||||
B I2C1_EV_IRQHandler
|
||||
|
||||
PUBWEAK I2C1_ER_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C1_ER_IRQHandler
|
||||
B I2C1_ER_IRQHandler
|
||||
|
||||
PUBWEAK I2C3_EV_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C3_EV_IRQHandler
|
||||
B I2C3_EV_IRQHandler
|
||||
|
||||
PUBWEAK I2C3_ER_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C3_ER_IRQHandler
|
||||
B I2C3_ER_IRQHandler
|
||||
|
||||
PUBWEAK SPI1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SPI1_IRQHandler
|
||||
B SPI1_IRQHandler
|
||||
|
||||
PUBWEAK SPI2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SPI2_IRQHandler
|
||||
B SPI2_IRQHandler
|
||||
|
||||
PUBWEAK USART1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
USART1_IRQHandler
|
||||
B USART1_IRQHandler
|
||||
|
||||
PUBWEAK LPUART1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
LPUART1_IRQHandler
|
||||
B LPUART1_IRQHandler
|
||||
|
||||
PUBWEAK SAI1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SAI1_IRQHandler
|
||||
B SAI1_IRQHandler
|
||||
|
||||
PUBWEAK TSC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TSC_IRQHandler
|
||||
B TSC_IRQHandler
|
||||
|
||||
PUBWEAK EXTI15_10_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI15_10_IRQHandler
|
||||
B EXTI15_10_IRQHandler
|
||||
|
||||
PUBWEAK RTC_Alarm_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
RTC_Alarm_IRQHandler
|
||||
B RTC_Alarm_IRQHandler
|
||||
|
||||
PUBWEAK CRS_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
CRS_IRQHandler
|
||||
B CRS_IRQHandler
|
||||
|
||||
PUBWEAK PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
|
||||
B PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
|
||||
|
||||
PUBWEAK IPCC_C1_RX_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IPCC_C1_RX_IRQHandler
|
||||
B IPCC_C1_RX_IRQHandler
|
||||
|
||||
PUBWEAK IPCC_C1_TX_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IPCC_C1_TX_IRQHandler
|
||||
B IPCC_C1_TX_IRQHandler
|
||||
|
||||
PUBWEAK HSEM_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
HSEM_IRQHandler
|
||||
B HSEM_IRQHandler
|
||||
|
||||
PUBWEAK LPTIM1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
LPTIM1_IRQHandler
|
||||
B LPTIM1_IRQHandler
|
||||
|
||||
PUBWEAK LPTIM2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
LPTIM2_IRQHandler
|
||||
B LPTIM2_IRQHandler
|
||||
|
||||
PUBWEAK LCD_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
LCD_IRQHandler
|
||||
B LCD_IRQHandler
|
||||
|
||||
PUBWEAK QUADSPI_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
QUADSPI_IRQHandler
|
||||
B QUADSPI_IRQHandler
|
||||
|
||||
PUBWEAK AES1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
AES1_IRQHandler
|
||||
B AES1_IRQHandler
|
||||
|
||||
PUBWEAK AES2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
AES2_IRQHandler
|
||||
B AES2_IRQHandler
|
||||
|
||||
PUBWEAK RNG_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
RNG_IRQHandler
|
||||
B RNG_IRQHandler
|
||||
|
||||
PUBWEAK FPU_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
FPU_IRQHandler
|
||||
B FPU_IRQHandler
|
||||
|
||||
PUBWEAK DMA2_Channel1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA2_Channel1_IRQHandler
|
||||
B DMA2_Channel1_IRQHandler
|
||||
|
||||
PUBWEAK DMA2_Channel2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA2_Channel2_IRQHandler
|
||||
B DMA2_Channel2_IRQHandler
|
||||
|
||||
PUBWEAK DMA2_Channel3_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA2_Channel3_IRQHandler
|
||||
B DMA2_Channel3_IRQHandler
|
||||
|
||||
PUBWEAK DMA2_Channel4_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA2_Channel4_IRQHandler
|
||||
B DMA2_Channel4_IRQHandler
|
||||
|
||||
PUBWEAK DMA2_Channel5_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA2_Channel5_IRQHandler
|
||||
B DMA2_Channel5_IRQHandler
|
||||
|
||||
PUBWEAK DMA2_Channel6_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA2_Channel6_IRQHandler
|
||||
B DMA2_Channel6_IRQHandler
|
||||
|
||||
PUBWEAK DMA2_Channel7_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA2_Channel7_IRQHandler
|
||||
B DMA2_Channel7_IRQHandler
|
||||
|
||||
PUBWEAK DMAMUX1_OVR_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMAMUX1_OVR_IRQHandler
|
||||
B DMAMUX1_OVR_IRQHandler
|
||||
|
||||
END
|
||||
|
||||
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
||||
|
|
@ -1,368 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file system_stm32wbxx.c
|
||||
* @author MCD Application Team
|
||||
* @brief CMSIS Cortex Device Peripheral Access Layer System Source File
|
||||
*
|
||||
* This file provides two functions and one global variable to be called from
|
||||
* user application:
|
||||
* - SystemInit(): This function is called at startup just after reset and
|
||||
* before branch to main program. This call is made inside
|
||||
* the "startup_stm32wbxx.s" file.
|
||||
*
|
||||
* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
|
||||
* by the user application to setup the SysTick
|
||||
* timer or configure other parameters.
|
||||
*
|
||||
* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
|
||||
* be called whenever the core clock is changed
|
||||
* during program execution.
|
||||
*
|
||||
* After each device reset the MSI (4 MHz) is used as system clock source.
|
||||
* Then SystemInit() function is called, in "startup_stm32wbxx.s" file, to
|
||||
* configure the system clock before to branch to main program.
|
||||
*
|
||||
* This file configures the system clock as follows:
|
||||
*=============================================================================
|
||||
*-----------------------------------------------------------------------------
|
||||
* System Clock source | MSI
|
||||
*-----------------------------------------------------------------------------
|
||||
* SYSCLK(Hz) | 4000000
|
||||
*-----------------------------------------------------------------------------
|
||||
* HCLK(Hz) | 4000000
|
||||
*-----------------------------------------------------------------------------
|
||||
* AHB Prescaler | 1
|
||||
*-----------------------------------------------------------------------------
|
||||
* APB1 Prescaler | 1
|
||||
*-----------------------------------------------------------------------------
|
||||
* APB2 Prescaler | 1
|
||||
*-----------------------------------------------------------------------------
|
||||
* PLL_M | 1
|
||||
*-----------------------------------------------------------------------------
|
||||
* PLL_N | 8
|
||||
*-----------------------------------------------------------------------------
|
||||
* PLL_P | 7
|
||||
*-----------------------------------------------------------------------------
|
||||
* PLL_Q | 2
|
||||
*-----------------------------------------------------------------------------
|
||||
* PLL_R | 2
|
||||
*-----------------------------------------------------------------------------
|
||||
* PLLSAI1_P | NA
|
||||
*-----------------------------------------------------------------------------
|
||||
* PLLSAI1_Q | NA
|
||||
*-----------------------------------------------------------------------------
|
||||
* PLLSAI1_R | NA
|
||||
*-----------------------------------------------------------------------------
|
||||
* Require 48MHz for USB OTG FS, | Disabled
|
||||
* SDIO and RNG clock |
|
||||
*-----------------------------------------------------------------------------
|
||||
*=============================================================================
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2019-2021 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/** @addtogroup CMSIS
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup stm32WBxx_system
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup stm32WBxx_System_Private_Includes
|
||||
* @{
|
||||
*/
|
||||
|
||||
#include "stm32wbxx.h"
|
||||
|
||||
#if !defined (HSE_VALUE)
|
||||
#define HSE_VALUE (32000000UL) /*!< Value of the External oscillator in Hz */
|
||||
#endif /* HSE_VALUE */
|
||||
|
||||
#if !defined (MSI_VALUE)
|
||||
#define MSI_VALUE (4000000UL) /*!< Value of the Internal oscillator in Hz*/
|
||||
#endif /* MSI_VALUE */
|
||||
|
||||
#if !defined (HSI_VALUE)
|
||||
#define HSI_VALUE (16000000UL) /*!< Value of the Internal oscillator in Hz*/
|
||||
#endif /* HSI_VALUE */
|
||||
|
||||
#if !defined (LSI_VALUE)
|
||||
#define LSI_VALUE (32000UL) /*!< Value of LSI in Hz*/
|
||||
#endif /* LSI_VALUE */
|
||||
|
||||
#if !defined (LSE_VALUE)
|
||||
#define LSE_VALUE (32768UL) /*!< Value of LSE in Hz*/
|
||||
#endif /* LSE_VALUE */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32WBxx_System_Private_TypesDefinitions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32WBxx_System_Private_Defines
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Note: Following vector table addresses must be defined in line with linker
|
||||
configuration. */
|
||||
/*!< Uncomment the following line if you need to relocate CPU1 CM4 and/or CPU2
|
||||
CM0+ vector table anywhere in Sram or Flash. Else vector table will be kept
|
||||
at address 0x00 which correspond to automatic remap of boot address selected */
|
||||
/* #define USER_VECT_TAB_ADDRESS */
|
||||
#if defined(USER_VECT_TAB_ADDRESS)
|
||||
/*!< Uncomment this line for user vector table remap in Sram else user remap
|
||||
will be done in Flash. */
|
||||
/* #define VECT_TAB_SRAM */
|
||||
#if defined(VECT_TAB_SRAM)
|
||||
#define VECT_TAB_BASE_ADDRESS SRAM1_BASE /*!< Vector Table base address field.
|
||||
This value must be a multiple of 0x200. */
|
||||
#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
|
||||
This value must be a multiple of 0x200. */
|
||||
#else
|
||||
#define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field.
|
||||
This value must be a multiple of 0x200. */
|
||||
#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
|
||||
This value must be a multiple of 0x200. */
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32WBxx_System_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32WBxx_System_Private_Variables
|
||||
* @{
|
||||
*/
|
||||
/* The SystemCoreClock variable is updated in three ways:
|
||||
1) by calling CMSIS function SystemCoreClockUpdate()
|
||||
2) by calling HAL API function HAL_RCC_GetHCLKFreq()
|
||||
3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
|
||||
Note: If you use this function to configure the system clock; then there
|
||||
is no need to call the 2 first functions listed above, since SystemCoreClock
|
||||
variable is updated automatically.
|
||||
*/
|
||||
uint32_t SystemCoreClock = 4000000UL ; /*CPU1: M4 on MSI clock after startup (4MHz)*/
|
||||
|
||||
const uint32_t AHBPrescTable[16UL] = {1UL, 3UL, 5UL, 1UL, 1UL, 6UL, 10UL, 32UL, 2UL, 4UL, 8UL, 16UL, 64UL, 128UL, 256UL, 512UL};
|
||||
|
||||
const uint32_t APBPrescTable[8UL] = {0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL};
|
||||
|
||||
const uint32_t MSIRangeTable[16UL] = {100000UL, 200000UL, 400000UL, 800000UL, 1000000UL, 2000000UL, \
|
||||
4000000UL, 8000000UL, 16000000UL, 24000000UL, 32000000UL, 48000000UL, 0UL, 0UL, 0UL, 0UL}; /* 0UL values are incorrect cases */
|
||||
|
||||
#if defined(STM32WB55xx) || defined(STM32WB5Mxx) || defined(STM32WB35xx) || defined (STM32WB15xx) || defined (STM32WB10xx)
|
||||
const uint32_t SmpsPrescalerTable[4UL][6UL]={{1UL,3UL,2UL,2UL,1UL,2UL}, \
|
||||
{2UL,6UL,4UL,3UL,2UL,4UL}, \
|
||||
{4UL,12UL,8UL,6UL,4UL,8UL}, \
|
||||
{4UL,12UL,8UL,6UL,4UL,8UL}};
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32WBxx_System_Private_FunctionPrototypes
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32WBxx_System_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Setup the microcontroller system.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void SystemInit(void)
|
||||
{
|
||||
#if defined(USER_VECT_TAB_ADDRESS)
|
||||
/* Configure the Vector Table location add offset address ------------------*/
|
||||
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;
|
||||
#endif
|
||||
|
||||
/* FPU settings ------------------------------------------------------------*/
|
||||
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
|
||||
SCB->CPACR |= ((3UL << (10UL*2UL))|(3UL << (11UL*2UL))); /* set CP10 and CP11 Full Access */
|
||||
#endif
|
||||
|
||||
/* Reset the RCC clock configuration to the default reset state ------------*/
|
||||
/* Set MSION bit */
|
||||
RCC->CR |= RCC_CR_MSION;
|
||||
|
||||
/* Reset CFGR register */
|
||||
RCC->CFGR = 0x00070000U;
|
||||
|
||||
/* Reset PLLSAI1ON, PLLON, HSECSSON, HSEON, HSION, and MSIPLLON bits */
|
||||
RCC->CR &= (uint32_t)0xFAF6FEFBU;
|
||||
|
||||
/*!< Reset LSI1 and LSI2 bits */
|
||||
RCC->CSR &= (uint32_t)0xFFFFFFFAU;
|
||||
|
||||
/*!< Reset HSI48ON bit */
|
||||
RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
|
||||
|
||||
/* Reset PLLCFGR register */
|
||||
RCC->PLLCFGR = 0x22041000U;
|
||||
|
||||
#if defined(STM32WB55xx) || defined(STM32WB5Mxx)
|
||||
/* Reset PLLSAI1CFGR register */
|
||||
RCC->PLLSAI1CFGR = 0x22041000U;
|
||||
#endif
|
||||
|
||||
/* Reset HSEBYP bit */
|
||||
RCC->CR &= 0xFFFBFFFFU;
|
||||
|
||||
/* Disable all interrupts */
|
||||
RCC->CIER = 0x00000000;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Update SystemCoreClock variable according to Clock Register Values.
|
||||
* The SystemCoreClock variable contains the core clock (HCLK), it can
|
||||
* be used by the user application to setup the SysTick timer or configure
|
||||
* other parameters.
|
||||
*
|
||||
* @note Each time the core clock (HCLK) changes, this function must be called
|
||||
* to update SystemCoreClock variable value. Otherwise, any configuration
|
||||
* based on this variable will be incorrect.
|
||||
*
|
||||
* @note - The system frequency computed by this function is not the real
|
||||
* frequency in the chip. It is calculated based on the predefined
|
||||
* constant and the selected clock source:
|
||||
*
|
||||
* - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
|
||||
*
|
||||
* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
|
||||
*
|
||||
* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
|
||||
*
|
||||
* - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
|
||||
* or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
|
||||
*
|
||||
* (*) MSI_VALUE is a constant defined in stm32wbxx_hal.h file (default value
|
||||
* 4 MHz) but the real value may vary depending on the variations
|
||||
* in voltage and temperature.
|
||||
*
|
||||
* (**) HSI_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
|
||||
* 16 MHz) but the real value may vary depending on the variations
|
||||
* in voltage and temperature.
|
||||
*
|
||||
* (***) HSE_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
|
||||
* 32 MHz), user has to ensure that HSE_VALUE is same as the real
|
||||
* frequency of the crystal used. Otherwise, this function may
|
||||
* have wrong result.
|
||||
*
|
||||
* - The result of this function could be not correct when using fractional
|
||||
* value for HSE crystal.
|
||||
*
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void SystemCoreClockUpdate(void)
|
||||
{
|
||||
uint32_t tmp, msirange, pllvco, pllr, pllsource , pllm;
|
||||
|
||||
/* Get MSI Range frequency--------------------------------------------------*/
|
||||
|
||||
/*MSI frequency range in Hz*/
|
||||
msirange = MSIRangeTable[(RCC->CR & RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos];
|
||||
|
||||
/* Get SYSCLK source -------------------------------------------------------*/
|
||||
switch (RCC->CFGR & RCC_CFGR_SWS)
|
||||
{
|
||||
case 0x00: /* MSI used as system clock source */
|
||||
SystemCoreClock = msirange;
|
||||
break;
|
||||
|
||||
case 0x04: /* HSI used as system clock source */
|
||||
/* HSI used as system clock source */
|
||||
SystemCoreClock = HSI_VALUE;
|
||||
break;
|
||||
|
||||
case 0x08: /* HSE used as system clock source */
|
||||
SystemCoreClock = HSE_VALUE;
|
||||
break;
|
||||
|
||||
case 0x0C: /* PLL used as system clock source */
|
||||
/* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
|
||||
SYSCLK = PLL_VCO / PLLR
|
||||
*/
|
||||
pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
|
||||
pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1UL ;
|
||||
|
||||
if(pllsource == 0x02UL) /* HSI used as PLL clock source */
|
||||
{
|
||||
pllvco = (HSI_VALUE / pllm);
|
||||
}
|
||||
else if(pllsource == 0x03UL) /* HSE used as PLL clock source */
|
||||
{
|
||||
pllvco = (HSE_VALUE / pllm);
|
||||
}
|
||||
else /* MSI used as PLL clock source */
|
||||
{
|
||||
pllvco = (msirange / pllm);
|
||||
}
|
||||
|
||||
pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
|
||||
pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1UL);
|
||||
|
||||
SystemCoreClock = pllvco/pllr;
|
||||
break;
|
||||
|
||||
default:
|
||||
SystemCoreClock = msirange;
|
||||
break;
|
||||
}
|
||||
|
||||
/* Compute HCLK clock frequency --------------------------------------------*/
|
||||
/* Get HCLK1 prescaler */
|
||||
tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
|
||||
/* HCLK clock frequency */
|
||||
SystemCoreClock = SystemCoreClock / tmp;
|
||||
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -1,86 +0,0 @@
|
|||
import rtconfig
|
||||
from building import *
|
||||
|
||||
# get current directory
|
||||
cwd = GetCurrentDir()
|
||||
|
||||
# The set of source files associated with this SConscript file.
|
||||
|
||||
src = Split('''
|
||||
CMSIS/Device/ST/STM32WBxx/Source/Templates/system_stm32wbxx.c
|
||||
STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
|
||||
STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_comp.c
|
||||
STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c
|
||||
STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_crc.c
|
||||
STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_crc_ex.c
|
||||
STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cryp.c
|
||||
STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cryp_ex.c
|
||||
STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c
|
||||
STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c
|
||||
STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c
|
||||
STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
|
||||
STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
|
||||
STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
|
||||
STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
|
||||
STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rng.c
|
||||
STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
|
||||
STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
|
||||
''')
|
||||
|
||||
if GetDepend(['RT_USING_SERIAL']) or GetDepend(['RT_USING_NANO', 'RT_USING_CONSOLE']):
|
||||
src += ['STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_uart.c']
|
||||
src += ['STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_uart_ex.c']
|
||||
src += ['STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_usart.c']
|
||||
src += ['STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_usart_ex.c']
|
||||
|
||||
if GetDepend(['RT_USING_I2C']):
|
||||
src += ['STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_i2c.c']
|
||||
src += ['STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_i2c_ex.c']
|
||||
|
||||
if GetDepend(['RT_USING_SPI']):
|
||||
src += ['STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_spi.c']
|
||||
src += ['STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_spi_ex.c']
|
||||
src += ['STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_qspi.c']
|
||||
|
||||
if GetDepend(['RT_USING_USB']):
|
||||
# src += ['STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hcd.c']
|
||||
src += ['STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pcd.c']
|
||||
src += ['STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pcd_ex.c']
|
||||
# src += ['STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_usb.c']
|
||||
|
||||
if GetDepend(['RT_USING_HWTIMER']) or GetDepend(['RT_USING_PWM']):
|
||||
src += ['STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_lptim.c']
|
||||
src += ['STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c']
|
||||
src += ['STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c']
|
||||
|
||||
if GetDepend(['RT_USING_ADC']):
|
||||
src += ['STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_adc.c']
|
||||
src += ['STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_adc_ex.c']
|
||||
|
||||
if GetDepend(['RT_USING_RTC']):
|
||||
src += ['STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rtc.c']
|
||||
src += ['STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rtc_ex.c']
|
||||
|
||||
if GetDepend(['RT_USING_WDT']):
|
||||
src += ['STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_iwdg.c']
|
||||
src += ['STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_wwdg.c']
|
||||
|
||||
if GetDepend(['RT_USING_AUDIO']):
|
||||
src += ['STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_sai.c']
|
||||
src += ['STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_sai_ex.c']
|
||||
|
||||
if GetDepend(['RT_USING_PM']):
|
||||
src += ['STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_lptim.c']
|
||||
|
||||
if GetDepend(['BSP_USING_ON_CHIP_FLASH']):
|
||||
src += ['STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c']
|
||||
src += ['STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c']
|
||||
# src += ['STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ramfunc.c']
|
||||
|
||||
path = [cwd + '/STM32WBxx_HAL_Driver/Inc',
|
||||
cwd + '/CMSIS/Device/ST/STM32WBxx/Include']
|
||||
|
||||
CPPDEFINES = ['USE_HAL_DRIVER']
|
||||
group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
|
||||
|
||||
Return('group')
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,57 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32_assert.h
|
||||
* @author MCD Application Team
|
||||
* @brief STM32 assert template file.
|
||||
* This file should be copied to the application folder and renamed
|
||||
* to stm32_assert.h.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32_ASSERT_H
|
||||
#define STM32_ASSERT_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
#ifdef USE_FULL_ASSERT
|
||||
/**
|
||||
* @brief The assert_param macro is used for function's parameters check.
|
||||
* @param expr If expr is false, it calls assert_failed function
|
||||
* which reports the name of the source file and the source
|
||||
* line number of the call that failed.
|
||||
* If expr is true, it returns no value.
|
||||
* @retval None
|
||||
*/
|
||||
#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
void assert_failed(uint8_t* file, uint32_t line);
|
||||
#else
|
||||
#define assert_param(expr) ((void)0U)
|
||||
#endif /* USE_FULL_ASSERT */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32_ASSERT_H */
|
||||
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -1,699 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32wbxx_hal.h
|
||||
* @author MCD Application Team
|
||||
* @brief This file contains all the functions prototypes for the HAL
|
||||
* module driver.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32WBxx_HAL_H
|
||||
#define STM32WBxx_HAL_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32wbxx_hal_conf.h"
|
||||
#include "stm32wbxx_ll_system.h"
|
||||
|
||||
/** @addtogroup STM32WBxx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup HAL HAL
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_TICK_FREQ Tick Frequency
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_TICK_FREQ_10HZ = 100U,
|
||||
HAL_TICK_FREQ_100HZ = 10U,
|
||||
HAL_TICK_FREQ_1KHZ = 1U,
|
||||
HAL_TICK_FREQ_DEFAULT = HAL_TICK_FREQ_1KHZ
|
||||
} HAL_TickFreqTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup HAL_Exported_Constants HAL Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup SYSCFG_Exported_Constants SYSCFG Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup SYSCFG_BootMode BOOT Mode
|
||||
* @{
|
||||
*/
|
||||
#define SYSCFG_BOOT_MAINFLASH LL_SYSCFG_REMAP_FLASH /*!< Main Flash memory mapped at 0x00000000 */
|
||||
#define SYSCFG_BOOT_SYSTEMFLASH LL_SYSCFG_REMAP_SYSTEMFLASH /*!< System Flash memory mapped at 0x00000000 */
|
||||
#define SYSCFG_BOOT_SRAM LL_SYSCFG_REMAP_SRAM /*!< SRAM1 mapped at 0x00000000 */
|
||||
#if defined(LL_SYSCFG_REMAP_QUADSPI)
|
||||
#define SYSCFG_BOOT_QUADSPI LL_SYSCFG_REMAP_QUADSPI /*!< QUADSPI memory mapped at 0x00000000 */
|
||||
#endif
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SYSCFG_FPU_Interrupts FPU Interrupts
|
||||
* @{
|
||||
*/
|
||||
#define SYSCFG_IT_FPU_IOC SYSCFG_CFGR1_FPU_IE_0 /*!< Floating Point Unit Invalid operation Interrupt */
|
||||
#define SYSCFG_IT_FPU_DZC SYSCFG_CFGR1_FPU_IE_1 /*!< Floating Point Unit Divide-by-zero Interrupt */
|
||||
#define SYSCFG_IT_FPU_UFC SYSCFG_CFGR1_FPU_IE_2 /*!< Floating Point Unit Underflow Interrupt */
|
||||
#define SYSCFG_IT_FPU_OFC SYSCFG_CFGR1_FPU_IE_3 /*!< Floating Point Unit Overflow Interrupt */
|
||||
#define SYSCFG_IT_FPU_IDC SYSCFG_CFGR1_FPU_IE_4 /*!< Floating Point Unit Input denormal Interrupt */
|
||||
#define SYSCFG_IT_FPU_IXC SYSCFG_CFGR1_FPU_IE_5 /*!< Floating Point Unit Inexact Interrupt */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SYSCFG_SRAM2WRP SRAM2 Page Write protection (0 to 31)
|
||||
* @{
|
||||
*/
|
||||
#define SYSCFG_SRAM2WRP_PAGE0 LL_SYSCFG_SRAM2WRP_PAGE0 /*!< SRAM2A Write protection page 0 */
|
||||
#define SYSCFG_SRAM2WRP_PAGE1 LL_SYSCFG_SRAM2WRP_PAGE1 /*!< SRAM2A Write protection page 1 */
|
||||
#define SYSCFG_SRAM2WRP_PAGE2 LL_SYSCFG_SRAM2WRP_PAGE2 /*!< SRAM2A Write protection page 2 */
|
||||
#define SYSCFG_SRAM2WRP_PAGE3 LL_SYSCFG_SRAM2WRP_PAGE3 /*!< SRAM2A Write protection page 3 */
|
||||
#define SYSCFG_SRAM2WRP_PAGE4 LL_SYSCFG_SRAM2WRP_PAGE4 /*!< SRAM2A Write protection page 4 */
|
||||
#define SYSCFG_SRAM2WRP_PAGE5 LL_SYSCFG_SRAM2WRP_PAGE5 /*!< SRAM2A Write protection page 5 */
|
||||
#define SYSCFG_SRAM2WRP_PAGE6 LL_SYSCFG_SRAM2WRP_PAGE6 /*!< SRAM2A Write protection page 6 */
|
||||
#define SYSCFG_SRAM2WRP_PAGE7 LL_SYSCFG_SRAM2WRP_PAGE7 /*!< SRAM2A Write protection page 7 */
|
||||
#define SYSCFG_SRAM2WRP_PAGE8 LL_SYSCFG_SRAM2WRP_PAGE8 /*!< SRAM2A Write protection page 8 */
|
||||
#define SYSCFG_SRAM2WRP_PAGE9 LL_SYSCFG_SRAM2WRP_PAGE9 /*!< SRAM2A Write protection page 9 */
|
||||
#define SYSCFG_SRAM2WRP_PAGE10 LL_SYSCFG_SRAM2WRP_PAGE10 /*!< SRAM2A Write protection page 10 */
|
||||
#define SYSCFG_SRAM2WRP_PAGE11 LL_SYSCFG_SRAM2WRP_PAGE11 /*!< SRAM2A Write protection page 11 */
|
||||
#define SYSCFG_SRAM2WRP_PAGE12 LL_SYSCFG_SRAM2WRP_PAGE12 /*!< SRAM2A Write protection page 12 */
|
||||
#define SYSCFG_SRAM2WRP_PAGE13 LL_SYSCFG_SRAM2WRP_PAGE13 /*!< SRAM2A Write protection page 13 */
|
||||
#define SYSCFG_SRAM2WRP_PAGE14 LL_SYSCFG_SRAM2WRP_PAGE14 /*!< SRAM2A Write protection page 14 */
|
||||
#define SYSCFG_SRAM2WRP_PAGE15 LL_SYSCFG_SRAM2WRP_PAGE15 /*!< SRAM2A Write protection page 15 */
|
||||
#define SYSCFG_SRAM2WRP_PAGE16 LL_SYSCFG_SRAM2WRP_PAGE16 /*!< SRAM2A Write protection page 16 */
|
||||
#define SYSCFG_SRAM2WRP_PAGE17 LL_SYSCFG_SRAM2WRP_PAGE17 /*!< SRAM2A Write protection page 17 */
|
||||
#define SYSCFG_SRAM2WRP_PAGE18 LL_SYSCFG_SRAM2WRP_PAGE18 /*!< SRAM2A Write protection page 18 */
|
||||
#define SYSCFG_SRAM2WRP_PAGE19 LL_SYSCFG_SRAM2WRP_PAGE19 /*!< SRAM2A Write protection page 19 */
|
||||
#define SYSCFG_SRAM2WRP_PAGE20 LL_SYSCFG_SRAM2WRP_PAGE20 /*!< SRAM2A Write protection page 20 */
|
||||
#define SYSCFG_SRAM2WRP_PAGE21 LL_SYSCFG_SRAM2WRP_PAGE21 /*!< SRAM2A Write protection page 21 */
|
||||
#define SYSCFG_SRAM2WRP_PAGE22 LL_SYSCFG_SRAM2WRP_PAGE22 /*!< SRAM2A Write protection page 22 */
|
||||
#define SYSCFG_SRAM2WRP_PAGE23 LL_SYSCFG_SRAM2WRP_PAGE23 /*!< SRAM2A Write protection page 23 */
|
||||
#define SYSCFG_SRAM2WRP_PAGE24 LL_SYSCFG_SRAM2WRP_PAGE24 /*!< SRAM2A Write protection page 24 */
|
||||
#define SYSCFG_SRAM2WRP_PAGE25 LL_SYSCFG_SRAM2WRP_PAGE25 /*!< SRAM2A Write protection page 25 */
|
||||
#define SYSCFG_SRAM2WRP_PAGE26 LL_SYSCFG_SRAM2WRP_PAGE26 /*!< SRAM2A Write protection page 26 */
|
||||
#define SYSCFG_SRAM2WRP_PAGE27 LL_SYSCFG_SRAM2WRP_PAGE27 /*!< SRAM2A Write protection page 27 */
|
||||
#define SYSCFG_SRAM2WRP_PAGE28 LL_SYSCFG_SRAM2WRP_PAGE28 /*!< SRAM2A Write protection page 28 */
|
||||
#define SYSCFG_SRAM2WRP_PAGE29 LL_SYSCFG_SRAM2WRP_PAGE29 /*!< SRAM2A Write protection page 29 */
|
||||
#define SYSCFG_SRAM2WRP_PAGE30 LL_SYSCFG_SRAM2WRP_PAGE30 /*!< SRAM2A Write protection page 30 */
|
||||
#define SYSCFG_SRAM2WRP_PAGE31 LL_SYSCFG_SRAM2WRP_PAGE31 /*!< SRAM2A Write protection page 31 */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SYSCFG_SRAM2WRP_32_63 SRAM2 Page Write protection (32 to 63)
|
||||
* @{
|
||||
*/
|
||||
#define SYSCFG_SRAM2WRP_PAGE32 LL_SYSCFG_SRAM2WRP_PAGE32 /*!< SRAM2B Write protection page 32 */
|
||||
#define SYSCFG_SRAM2WRP_PAGE33 LL_SYSCFG_SRAM2WRP_PAGE33 /*!< SRAM2B Write protection page 33 */
|
||||
#define SYSCFG_SRAM2WRP_PAGE34 LL_SYSCFG_SRAM2WRP_PAGE34 /*!< SRAM2B Write protection page 34 */
|
||||
#define SYSCFG_SRAM2WRP_PAGE35 LL_SYSCFG_SRAM2WRP_PAGE35 /*!< SRAM2B Write protection page 35 */
|
||||
#if defined(LL_SYSCFG_SRAM2WRP_PAGE36)
|
||||
#define SYSCFG_SRAM2WRP_PAGE36 LL_SYSCFG_SRAM2WRP_PAGE36 /*!< SRAM2B Write protection page 36 */
|
||||
#define SYSCFG_SRAM2WRP_PAGE37 LL_SYSCFG_SRAM2WRP_PAGE37 /*!< SRAM2B Write protection page 37 */
|
||||
#define SYSCFG_SRAM2WRP_PAGE38 LL_SYSCFG_SRAM2WRP_PAGE38 /*!< SRAM2B Write protection page 38 */
|
||||
#define SYSCFG_SRAM2WRP_PAGE39 LL_SYSCFG_SRAM2WRP_PAGE39 /*!< SRAM2B Write protection page 39 */
|
||||
#define SYSCFG_SRAM2WRP_PAGE40 LL_SYSCFG_SRAM2WRP_PAGE40 /*!< SRAM2B Write protection page 40 */
|
||||
#define SYSCFG_SRAM2WRP_PAGE41 LL_SYSCFG_SRAM2WRP_PAGE41 /*!< SRAM2B Write protection page 41 */
|
||||
#define SYSCFG_SRAM2WRP_PAGE42 LL_SYSCFG_SRAM2WRP_PAGE42 /*!< SRAM2B Write protection page 42 */
|
||||
#define SYSCFG_SRAM2WRP_PAGE43 LL_SYSCFG_SRAM2WRP_PAGE43 /*!< SRAM2B Write protection page 43 */
|
||||
#define SYSCFG_SRAM2WRP_PAGE44 LL_SYSCFG_SRAM2WRP_PAGE44 /*!< SRAM2B Write protection page 44 */
|
||||
#define SYSCFG_SRAM2WRP_PAGE45 LL_SYSCFG_SRAM2WRP_PAGE45 /*!< SRAM2B Write protection page 45 */
|
||||
#define SYSCFG_SRAM2WRP_PAGE46 LL_SYSCFG_SRAM2WRP_PAGE46 /*!< SRAM2B Write protection page 46 */
|
||||
#define SYSCFG_SRAM2WRP_PAGE47 LL_SYSCFG_SRAM2WRP_PAGE47 /*!< SRAM2B Write protection page 47 */
|
||||
#define SYSCFG_SRAM2WRP_PAGE48 LL_SYSCFG_SRAM2WRP_PAGE48 /*!< SRAM2B Write protection page 48 */
|
||||
#define SYSCFG_SRAM2WRP_PAGE49 LL_SYSCFG_SRAM2WRP_PAGE49 /*!< SRAM2B Write protection page 49 */
|
||||
#define SYSCFG_SRAM2WRP_PAGE50 LL_SYSCFG_SRAM2WRP_PAGE50 /*!< SRAM2B Write protection page 50 */
|
||||
#define SYSCFG_SRAM2WRP_PAGE51 LL_SYSCFG_SRAM2WRP_PAGE51 /*!< SRAM2B Write protection page 51 */
|
||||
#define SYSCFG_SRAM2WRP_PAGE52 LL_SYSCFG_SRAM2WRP_PAGE52 /*!< SRAM2B Write protection page 52 */
|
||||
#define SYSCFG_SRAM2WRP_PAGE53 LL_SYSCFG_SRAM2WRP_PAGE53 /*!< SRAM2B Write protection page 53 */
|
||||
#define SYSCFG_SRAM2WRP_PAGE54 LL_SYSCFG_SRAM2WRP_PAGE54 /*!< SRAM2B Write protection page 54 */
|
||||
#define SYSCFG_SRAM2WRP_PAGE55 LL_SYSCFG_SRAM2WRP_PAGE55 /*!< SRAM2B Write protection page 55 */
|
||||
#define SYSCFG_SRAM2WRP_PAGE56 LL_SYSCFG_SRAM2WRP_PAGE56 /*!< SRAM2B Write protection page 56 */
|
||||
#define SYSCFG_SRAM2WRP_PAGE57 LL_SYSCFG_SRAM2WRP_PAGE57 /*!< SRAM2B Write protection page 57 */
|
||||
#define SYSCFG_SRAM2WRP_PAGE58 LL_SYSCFG_SRAM2WRP_PAGE58 /*!< SRAM2B Write protection page 58 */
|
||||
#define SYSCFG_SRAM2WRP_PAGE59 LL_SYSCFG_SRAM2WRP_PAGE59 /*!< SRAM2B Write protection page 59 */
|
||||
#define SYSCFG_SRAM2WRP_PAGE60 LL_SYSCFG_SRAM2WRP_PAGE60 /*!< SRAM2B Write protection page 60 */
|
||||
#define SYSCFG_SRAM2WRP_PAGE61 LL_SYSCFG_SRAM2WRP_PAGE61 /*!< SRAM2B Write protection page 61 */
|
||||
#define SYSCFG_SRAM2WRP_PAGE62 LL_SYSCFG_SRAM2WRP_PAGE62 /*!< SRAM2B Write protection page 62 */
|
||||
#define SYSCFG_SRAM2WRP_PAGE63 LL_SYSCFG_SRAM2WRP_PAGE63 /*!< SRAM2B Write protection page 63 */
|
||||
#endif /* LL_SYSCFG_SRAM2WRP_PAGE36 */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if defined(VREFBUF)
|
||||
/** @defgroup SYSCFG_VREFBUF_VoltageScale VREFBUF Voltage Scale
|
||||
* @{
|
||||
*/
|
||||
#define SYSCFG_VREFBUF_VOLTAGE_SCALE0 LL_VREFBUF_VOLTAGE_SCALE0 /*!< Voltage reference scale 0 (VREF_OUT1) */
|
||||
#define SYSCFG_VREFBUF_VOLTAGE_SCALE1 LL_VREFBUF_VOLTAGE_SCALE1 /*!< Voltage reference scale 1 (VREF_OUT2) */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SYSCFG_VREFBUF_HighImpedance VREFBUF High Impedance
|
||||
* @{
|
||||
*/
|
||||
#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE 0x00000000U /*!< VREF_plus pin is internally connected to Voltage reference buffer output */
|
||||
#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE VREFBUF_CSR_HIZ /*!< VREF_plus pin is high impedance */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* VREFBUF */
|
||||
|
||||
/** @defgroup SYSCFG_SRAM_flags_definition SRAM Flags
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SYSCFG_FLAG_SRAM2_PE SYSCFG_CFGR2_SPF /*!< SRAM2 parity error */
|
||||
#define SYSCFG_FLAG_SRAM2_BUSY SYSCFG_SCSR_SRAM2BSY /*!< SRAM2 busy by erase operation */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SYSCFG_FastModePlus_GPIO Fast-mode Plus on GPIO
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Fast-mode Plus driving capability on a specific GPIO
|
||||
*/
|
||||
#define SYSCFG_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP /*!< Enable Fast-mode Plus on PB6 */
|
||||
#define SYSCFG_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP /*!< Enable Fast-mode Plus on PB7 */
|
||||
#define SYSCFG_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP /*!< Enable Fast-mode Plus on PB8 */
|
||||
#define SYSCFG_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP /*!< Enable Fast-mode Plus on PB9 */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Secure_IP_Write_Access Secure IP Write Access
|
||||
* @{
|
||||
*/
|
||||
#if defined(LL_SYSCFG_SECURE_ACCESS_AES1)
|
||||
#define HAL_SYSCFG_SECURE_ACCESS_AES1 LL_SYSCFG_SECURE_ACCESS_AES1 /*!< Enabling the security access of Advanced Encryption Standard 1 KEY[7:0] */
|
||||
#endif
|
||||
#define HAL_SYSCFG_SECURE_ACCESS_AES2 LL_SYSCFG_SECURE_ACCESS_AES2 /*!< Enabling the security access of Advanced Encryption Standard 2 */
|
||||
#define HAL_SYSCFG_SECURE_ACCESS_PKA LL_SYSCFG_SECURE_ACCESS_PKA /*!< Enabling the security access of Public Key Accelerator */
|
||||
#define HAL_SYSCFG_SECURE_ACCESS_RNG LL_SYSCFG_SECURE_ACCESS_RNG /*!< Enabling the security access of Random Number Generator */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/** @defgroup HAL_Exported_Macros HAL Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DBGMCU_Exported_Macros DBGMCU Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Freeze and Unfreeze Peripherals in Debug mode
|
||||
*/
|
||||
|
||||
/** @defgroup DBGMCU_APBx_GRPx_STOP_IP DBGMCU CPU1 APBx GRPx STOP IP
|
||||
* @{
|
||||
*/
|
||||
#if defined(LL_DBGMCU_APB1_GRP1_TIM2_STOP)
|
||||
#define __HAL_DBGMCU_FREEZE_TIM2() LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_APB1_GRP1_TIM2_STOP)
|
||||
#define __HAL_DBGMCU_UNFREEZE_TIM2() LL_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_DBGMCU_APB1_GRP1_TIM2_STOP)
|
||||
#endif
|
||||
|
||||
#if defined(LL_DBGMCU_APB1_GRP1_RTC_STOP)
|
||||
#define __HAL_DBGMCU_FREEZE_RTC() LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_APB1_GRP1_RTC_STOP)
|
||||
#define __HAL_DBGMCU_UNFREEZE_RTC() LL_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_DBGMCU_APB1_GRP1_RTC_STOP)
|
||||
#endif
|
||||
|
||||
#if defined(LL_DBGMCU_APB1_GRP1_WWDG_STOP)
|
||||
#define __HAL_DBGMCU_FREEZE_WWDG() LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_APB1_GRP1_WWDG_STOP)
|
||||
#define __HAL_DBGMCU_UNFREEZE_WWDG() LL_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_DBGMCU_APB1_GRP1_WWDG_STOP)
|
||||
#endif
|
||||
|
||||
#if defined(LL_DBGMCU_APB1_GRP1_IWDG_STOP)
|
||||
#define __HAL_DBGMCU_FREEZE_IWDG() LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_APB1_GRP1_IWDG_STOP)
|
||||
#define __HAL_DBGMCU_UNFREEZE_IWDG() LL_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_DBGMCU_APB1_GRP1_IWDG_STOP)
|
||||
#endif
|
||||
|
||||
#if defined(LL_DBGMCU_APB1_GRP1_I2C1_STOP)
|
||||
#define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_APB1_GRP1_I2C1_STOP)
|
||||
#define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() LL_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_DBGMCU_APB1_GRP1_I2C1_STOP)
|
||||
#endif
|
||||
|
||||
#if defined(LL_DBGMCU_APB1_GRP1_I2C3_STOP)
|
||||
#define __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT() LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_APB1_GRP1_I2C3_STOP)
|
||||
#define __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT() LL_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_DBGMCU_APB1_GRP1_I2C3_STOP)
|
||||
#endif
|
||||
|
||||
#if defined(LL_DBGMCU_APB1_GRP1_LPTIM1_STOP)
|
||||
#define __HAL_DBGMCU_FREEZE_LPTIM1() LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_APB1_GRP1_LPTIM1_STOP)
|
||||
#define __HAL_DBGMCU_UNFREEZE_LPTIM1() LL_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_DBGMCU_APB1_GRP1_LPTIM1_STOP)
|
||||
#endif
|
||||
|
||||
#if defined(LL_DBGMCU_APB1_GRP2_LPTIM2_STOP)
|
||||
#define __HAL_DBGMCU_FREEZE_LPTIM2() LL_DBGMCU_APB1_GRP2_FreezePeriph(LL_DBGMCU_APB1_GRP2_LPTIM2_STOP)
|
||||
#define __HAL_DBGMCU_UNFREEZE_LPTIM2() LL_DBGMCU_APB1_GRP2_UnFreezePeriph(LL_DBGMCU_APB1_GRP2_LPTIM2_STOP)
|
||||
#endif
|
||||
|
||||
#if defined(LL_DBGMCU_APB2_GRP1_TIM1_STOP)
|
||||
#define __HAL_DBGMCU_FREEZE_TIM1() LL_DBGMCU_APB2_GRP1_FreezePeriph(LL_DBGMCU_APB2_GRP1_TIM1_STOP)
|
||||
#define __HAL_DBGMCU_UNFREEZE_TIM1() LL_DBGMCU_APB2_GRP1_UnFreezePeriph(LL_DBGMCU_APB2_GRP1_TIM1_STOP)
|
||||
#endif
|
||||
|
||||
#if defined(LL_DBGMCU_APB2_GRP1_TIM16_STOP)
|
||||
#define __HAL_DBGMCU_FREEZE_TIM16() LL_DBGMCU_APB2_GRP1_FreezePeriph(LL_DBGMCU_APB2_GRP1_TIM16_STOP)
|
||||
#define __HAL_DBGMCU_UNFREEZE_TIM16() LL_DBGMCU_APB2_GRP1_UnFreezePeriph(LL_DBGMCU_APB2_GRP1_TIM16_STOP)
|
||||
#endif
|
||||
|
||||
#if defined(LL_DBGMCU_APB2_GRP1_TIM17_STOP)
|
||||
#define __HAL_DBGMCU_FREEZE_TIM17() LL_DBGMCU_APB2_GRP1_FreezePeriph(LL_DBGMCU_APB2_GRP1_TIM17_STOP)
|
||||
#define __HAL_DBGMCU_UNFREEZE_TIM17() LL_DBGMCU_APB2_GRP1_UnFreezePeriph(LL_DBGMCU_APB2_GRP1_TIM17_STOP)
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DBGMCU_C2_APBx_GRPx_STOP_IP DBGMCU CPU2 APBx GRPx STOP IP
|
||||
* @{
|
||||
*/
|
||||
#if defined(LL_C2_DBGMCU_APB1_GRP1_TIM2_STOP)
|
||||
#define __HAL_C2_DBGMCU_FREEZE_TIM2() LL_C2_DBGMCU_APB1_GRP1_FreezePeriph(LL_C2_DBGMCU_APB1_GRP1_TIM2_STOP)
|
||||
#define __HAL_C2_DBGMCU_UNFREEZE_TIM2() LL_C2_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB1_GRP1_TIM2_STOP)
|
||||
#endif
|
||||
|
||||
#if defined(LL_C2_DBGMCU_APB1_GRP1_RTC_STOP)
|
||||
#define __HAL_C2_DBGMCU_FREEZE_RTC() LL_C2_DBGMCU_APB1_GRP1_FreezePeriph(LL_C2_DBGMCU_APB1_GRP1_RTC_STOP)
|
||||
#define __HAL_C2_DBGMCU_UNFREEZE_RTC() LL_C2_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB1_GRP1_RTC_STOP)
|
||||
#endif
|
||||
|
||||
#if defined(LL_C2_DBGMCU_APB1_GRP1_IWDG_STOP)
|
||||
#define __HAL_C2_DBGMCU_FREEZE_IWDG() LL_C2_DBGMCU_APB1_GRP1_FreezePeriph(LL_C2_DBGMCU_APB1_GRP1_IWDG_STOP)
|
||||
#define __HAL_C2_DBGMCU_UNFREEZE_IWDG() LL_C2_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB1_GRP1_IWDG_STOP)
|
||||
#endif
|
||||
|
||||
#if defined(LL_C2_DBGMCU_APB1_GRP1_I2C1_STOP)
|
||||
#define __HAL_C2_DBGMCU_FREEZE_I2C1_TIMEOUT() LL_C2_DBGMCU_APB1_GRP1_FreezePeriph(LL_C2_DBGMCU_APB1_GRP1_I2C1_STOP)
|
||||
#define __HAL_C2_DBGMCU_UNFREEZE_I2C1_TIMEOUT() LL_C2_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB1_GRP1_I2C1_STOP)
|
||||
#endif
|
||||
|
||||
#if defined(LL_C2_DBGMCU_APB1_GRP1_I2C3_STOP)
|
||||
#define __HAL_C2_DBGMCU_FREEZE_I2C3_TIMEOUT() LL_C2_DBGMCU_APB1_GRP1_FreezePeriph(LL_C2_DBGMCU_APB1_GRP1_I2C3_STOP)
|
||||
#define __HAL_C2_DBGMCU_UNFREEZE_I2C3_TIMEOUT() LL_C2_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB1_GRP1_I2C3_STOP)
|
||||
#endif
|
||||
|
||||
#if defined(LL_C2_DBGMCU_APB1_GRP1_LPTIM1_STOP)
|
||||
#define __HAL_C2_DBGMCU_FREEZE_LPTIM1() LL_C2_DBGMCU_APB1_GRP1_FreezePeriph(LL_C2_DBGMCU_APB1_GRP1_LPTIM1_STOP)
|
||||
#define __HAL_C2_DBGMCU_UNFREEZE_LPTIM1() LL_C2_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB1_GRP1_LPTIM1_STOP)
|
||||
#endif
|
||||
|
||||
#if defined(LL_C2_DBGMCU_APB1_GRP2_LPTIM2_STOP)
|
||||
#define __HAL_C2_DBGMCU_FREEZE_LPTIM2() LL_C2_DBGMCU_APB1_GRP2_FreezePeriph(LL_C2_DBGMCU_APB1_GRP2_LPTIM2_STOP)
|
||||
#define __HAL_C2_DBGMCU_UNFREEZE_LPTIM2() LL_C2_DBGMCU_APB1_GRP2_UnFreezePeriph(LL_C2_DBGMCU_APB1_GRP2_LPTIM2_STOP)
|
||||
#endif
|
||||
|
||||
#if defined(LL_C2_DBGMCU_APB2_GRP1_TIM1_STOP)
|
||||
#define __HAL_C2_DBGMCU_FREEZE_TIM1() LL_C2_DBGMCU_APB2_GRP1_FreezePeriph(LL_C2_DBGMCU_APB2_GRP1_TIM1_STOP)
|
||||
#define __HAL_C2_DBGMCU_UNFREEZE_TIM1() LL_C2_DBGMCU_APB2_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB2_GRP1_TIM1_STOP)
|
||||
#endif
|
||||
|
||||
#if defined(LL_C2_DBGMCU_APB2_GRP1_TIM16_STOP)
|
||||
#define __HAL_C2_DBGMCU_FREEZE_TIM16() LL_C2_DBGMCU_APB2_GRP1_FreezePeriph(LL_C2_DBGMCU_APB2_GRP1_TIM16_STOP)
|
||||
#define __HAL_C2_DBGMCU_UNFREEZE_TIM16() LL_C2_DBGMCU_APB2_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB2_GRP1_TIM16_STOP)
|
||||
#endif
|
||||
|
||||
#if defined(LL_C2_DBGMCU_APB2_GRP1_TIM17_STOP)
|
||||
#define __HAL_C2_DBGMCU_FREEZE_TIM17() LL_C2_DBGMCU_APB2_GRP1_FreezePeriph(LL_C2_DBGMCU_APB2_GRP1_TIM17_STOP)
|
||||
#define __HAL_C2_DBGMCU_UNFREEZE_TIM17() LL_C2_DBGMCU_APB2_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB2_GRP1_TIM17_STOP)
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SYSCFG_Exported_Macros SYSCFG Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Main Flash memory mapped at 0x00000000
|
||||
*/
|
||||
#define __HAL_SYSCFG_REMAPMEMORY_FLASH() LL_SYSCFG_SetRemapMemory(LL_SYSCFG_REMAP_FLASH)
|
||||
|
||||
/** @brief System Flash memory mapped at 0x00000000
|
||||
*/
|
||||
#define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH() LL_SYSCFG_SetRemapMemory(LL_SYSCFG_REMAP_SYSTEMFLASH)
|
||||
|
||||
/** @brief Embedded SRAM mapped at 0x00000000
|
||||
*/
|
||||
#define __HAL_SYSCFG_REMAPMEMORY_SRAM() LL_SYSCFG_SetRemapMemory(LL_SYSCFG_REMAP_SRAM)
|
||||
|
||||
#if defined(LL_SYSCFG_REMAP_QUADSPI)
|
||||
/** @brief QUADSPI mapped at 0x00000000.
|
||||
*/
|
||||
#define __HAL_SYSCFG_REMAPMEMORY_QUADSPI() LL_SYSCFG_SetRemapMemory(LL_SYSCFG_REMAP_QUADSPI)
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Return the boot mode as configured by user.
|
||||
* @retval The boot mode as configured by user. The returned value can be one
|
||||
* of the following values:
|
||||
* @arg @ref SYSCFG_BOOT_MAINFLASH
|
||||
* @arg @ref SYSCFG_BOOT_SYSTEMFLASH
|
||||
* @arg @ref SYSCFG_BOOT_SRAM
|
||||
#if defined(LL_SYSCFG_REMAP_QUADSPI)
|
||||
* @arg @ref SYSCFG_BOOT_QUADSPI
|
||||
#endif
|
||||
*/
|
||||
#define __HAL_SYSCFG_GET_BOOT_MODE() LL_SYSCFG_GetRemapMemory()
|
||||
|
||||
/** @brief SRAM2 page 0 to 31 write protection enable macro
|
||||
* @param __SRAM2WRP__ This parameter can be a combination of values of @ref SYSCFG_SRAM2WRP
|
||||
* @note Write protection can only be disabled by a system reset
|
||||
*/
|
||||
/* Legacy define */
|
||||
#define __HAL_SYSCFG_SRAM2_WRP_1_31_ENABLE __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE
|
||||
#define __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE(__SRAM2WRP__) do {assert_param(IS_SYSCFG_SRAM2WRP_PAGE((__SRAM2WRP__)));\
|
||||
LL_SYSCFG_EnableSRAM2PageWRP_0_31(__SRAM2WRP__);\
|
||||
}while(0)
|
||||
|
||||
/** @brief SRAM2 page 32 to 63 write protection enable macro
|
||||
* @param __SRAM2WRP__ This parameter can be a combination of values of @ref SYSCFG_SRAM2WRP_32_63
|
||||
* @note Write protection can only be disabled by a system reset
|
||||
*/
|
||||
#define __HAL_SYSCFG_SRAM2_WRP_32_63_ENABLE(__SRAM2WRP__) do {assert_param(IS_SYSCFG_SRAM2WRP2_PAGE((__SRAM2WRP__)));\
|
||||
LL_SYSCFG_EnableSRAM2PageWRP_32_63(__SRAM2WRP__);\
|
||||
}while(0)
|
||||
|
||||
/** @brief SRAM2 page write protection unlock prior to erase
|
||||
* @note Writing a wrong key reactivates the write protection
|
||||
*/
|
||||
#define __HAL_SYSCFG_SRAM2_WRP_UNLOCK() LL_SYSCFG_UnlockSRAM2WRP()
|
||||
|
||||
/** @brief SRAM2 erase
|
||||
* @note __SYSCFG_GET_FLAG(SYSCFG_FLAG_SRAM2_BUSY) may be used to check end of erase
|
||||
*/
|
||||
#define __HAL_SYSCFG_SRAM2_ERASE() LL_SYSCFG_EnableSRAM2Erase()
|
||||
|
||||
/** @brief Floating Point Unit interrupt enable/disable macros
|
||||
* @param __INTERRUPT__ This parameter can be a value of @ref SYSCFG_FPU_Interrupts
|
||||
*/
|
||||
#define __HAL_SYSCFG_FPU_INTERRUPT_ENABLE(__INTERRUPT__) do {assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__)));\
|
||||
SET_BIT(SYSCFG->CFGR1, (__INTERRUPT__));\
|
||||
}while(0)
|
||||
|
||||
#define __HAL_SYSCFG_FPU_INTERRUPT_DISABLE(__INTERRUPT__) do {assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__)));\
|
||||
CLEAR_BIT(SYSCFG->CFGR1, (__INTERRUPT__));\
|
||||
}while(0)
|
||||
|
||||
/** @brief SYSCFG Break ECC lock.
|
||||
* Enable and lock the connection of Flash ECC error connection to TIM1/16/17 Break input.
|
||||
* @note The selected configuration is locked and can be unlocked only by system reset.
|
||||
*/
|
||||
#define __HAL_SYSCFG_BREAK_ECC_LOCK() LL_SYSCFG_SetTIMBreakInputs(LL_SYSCFG_TIMBREAK_ECC)
|
||||
|
||||
/** @brief SYSCFG Break Cortex-M4 Lockup lock.
|
||||
* Enable and lock the connection of Cortex-M4 LOCKUP (Hardfault) output to TIM1/16/17 Break input.
|
||||
* @note The selected configuration is locked and can be unlocked only by system reset.
|
||||
*/
|
||||
#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK() LL_SYSCFG_SetTIMBreakInputs(LL_SYSCFG_TIMBREAK_LOCKUP)
|
||||
|
||||
/** @brief SYSCFG Break PVD lock.
|
||||
* Enable and lock the PVD connection to Timer1/16/17 Break input, as well as the PVDE and PLS[2:0] in the PWR_CR2 register.
|
||||
* @note The selected configuration is locked and can be unlocked only by system reset.
|
||||
*/
|
||||
#define __HAL_SYSCFG_BREAK_PVD_LOCK() LL_SYSCFG_SetTIMBreakInputs(LL_SYSCFG_TIMBREAK_PVD)
|
||||
|
||||
/** @brief SYSCFG Break SRAM2 parity lock.
|
||||
* Enable and lock the SRAM2 parity error signal connection to TIM1/16/17 Break input.
|
||||
* @note The selected configuration is locked and can be unlocked by system reset.
|
||||
*/
|
||||
#define __HAL_SYSCFG_BREAK_SRAM2PARITY_LOCK() LL_SYSCFG_SetTIMBreakInputs(LL_SYSCFG_TIMBREAK_SRAM2_PARITY)
|
||||
|
||||
/** @brief Check SYSCFG flag is set or not.
|
||||
* @param __FLAG__ specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref SYSCFG_FLAG_SRAM2_PE SRAM2 Parity Error Flag
|
||||
* @arg @ref SYSCFG_FLAG_SRAM2_BUSY SRAM2 Erase Ongoing
|
||||
* @retval The new state of __FLAG__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_SYSCFG_GET_FLAG(__FLAG__) ((((((__FLAG__) == SYSCFG_SCSR_SRAM2BSY)? SYSCFG->SCSR : SYSCFG->CFGR2) & (__FLAG__))!= 0U) ? 1U : 0U)
|
||||
|
||||
/** @brief Set the SPF bit to clear the SRAM Parity Error Flag.
|
||||
*/
|
||||
#define __HAL_SYSCFG_CLEAR_FLAG() LL_SYSCFG_ClearFlag_SP()
|
||||
|
||||
/** @brief Fast mode Plus driving capability enable/disable macros
|
||||
* @param __FASTMODEPLUS__ This parameter can be a value of @ref SYSCFG_FastModePlus_GPIO
|
||||
*/
|
||||
#define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__))); \
|
||||
LL_SYSCFG_EnableFastModePlus(__FASTMODEPLUS__); \
|
||||
}while(0)
|
||||
|
||||
#define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__))); \
|
||||
LL_SYSCFG_DisableFastModePlus(__FASTMODEPLUS__); \
|
||||
}while(0)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup HAL_Private_Macros HAL Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup SYSCFG_Private_Macros SYSCFG Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_SYSCFG_FPU_INTERRUPT(__INTERRUPT__) ((((__INTERRUPT__) & SYSCFG_IT_FPU_IOC) == SYSCFG_IT_FPU_IOC) || \
|
||||
(((__INTERRUPT__) & SYSCFG_IT_FPU_DZC) == SYSCFG_IT_FPU_DZC) || \
|
||||
(((__INTERRUPT__) & SYSCFG_IT_FPU_UFC) == SYSCFG_IT_FPU_UFC) || \
|
||||
(((__INTERRUPT__) & SYSCFG_IT_FPU_OFC) == SYSCFG_IT_FPU_OFC) || \
|
||||
(((__INTERRUPT__) & SYSCFG_IT_FPU_IDC) == SYSCFG_IT_FPU_IDC) || \
|
||||
(((__INTERRUPT__) & SYSCFG_IT_FPU_IXC) == SYSCFG_IT_FPU_IXC))
|
||||
|
||||
#if defined(STM32WB15xx)
|
||||
#define IS_SYSCFG_SRAM2WRP_PAGE(__PAGE__) (((__PAGE__) > 0U) && ((__PAGE__) <= 0xFFFFFFFFU))
|
||||
#define IS_SYSCFG_SRAM2WRP2_PAGE(__PAGE__) (((__PAGE__) > 0U) && ((__PAGE__) <= 0x0000000FU))
|
||||
#else
|
||||
#define IS_SYSCFG_SRAM2WRP_PAGE(__PAGE__) (((__PAGE__) > 0U) && ((__PAGE__) <= 0xFFFFFFFFU))
|
||||
#define IS_SYSCFG_SRAM2WRP2_PAGE(__PAGE__) IS_SYSCFG_SRAM2WRP_PAGE(__PAGE__)
|
||||
#endif
|
||||
|
||||
#if defined(VREFBUF)
|
||||
#define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(__SCALE__) (((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE0) || \
|
||||
((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE1))
|
||||
|
||||
#define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(__VALUE__) (((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE) || \
|
||||
((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE))
|
||||
|
||||
#define IS_SYSCFG_VREFBUF_TRIMMING(__VALUE__) (((__VALUE__) > 0U) && ((__VALUE__) <= VREFBUF_CCR_TRIM))
|
||||
#endif
|
||||
|
||||
#define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \
|
||||
(((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \
|
||||
(((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8) || \
|
||||
(((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9))
|
||||
|
||||
#if defined(LL_SYSCFG_SECURE_ACCESS_AES1)
|
||||
#define IS_SYSCFG_SECURITY_ACCESS(__VALUE__) ((((__VALUE__) & HAL_SYSCFG_SECURE_ACCESS_AES1) == HAL_SYSCFG_SECURE_ACCESS_AES1) || \
|
||||
(((__VALUE__) & HAL_SYSCFG_SECURE_ACCESS_AES2) == HAL_SYSCFG_SECURE_ACCESS_AES2) || \
|
||||
(((__VALUE__) & HAL_SYSCFG_SECURE_ACCESS_PKA) == HAL_SYSCFG_SECURE_ACCESS_PKA) || \
|
||||
(((__VALUE__) & HAL_SYSCFG_SECURE_ACCESS_RNG) == HAL_SYSCFG_SECURE_ACCESS_RNG))
|
||||
#else
|
||||
#define IS_SYSCFG_SECURITY_ACCESS(__VALUE__) ((((__VALUE__) & HAL_SYSCFG_SECURE_ACCESS_AES2) == HAL_SYSCFG_SECURE_ACCESS_AES2) || \
|
||||
(((__VALUE__) & HAL_SYSCFG_SECURE_ACCESS_PKA) == HAL_SYSCFG_SECURE_ACCESS_PKA) || \
|
||||
(((__VALUE__) & HAL_SYSCFG_SECURE_ACCESS_RNG) == HAL_SYSCFG_SECURE_ACCESS_RNG))
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_Private_Macros HAL Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ) || \
|
||||
((FREQ) == HAL_TICK_FREQ_100HZ) || \
|
||||
((FREQ) == HAL_TICK_FREQ_1KHZ))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup HAL_Exported_Functions HAL Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_Exported_Functions_Group1 HAL Initialization and Configuration functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Initialization and Configuration functions ******************************/
|
||||
HAL_StatusTypeDef HAL_Init(void);
|
||||
HAL_StatusTypeDef HAL_DeInit(void);
|
||||
void HAL_MspInit(void);
|
||||
void HAL_MspDeInit(void);
|
||||
|
||||
HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_Exported_Functions_Group2 HAL Control functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Peripheral Control functions ************************************************/
|
||||
void HAL_IncTick(void);
|
||||
void HAL_Delay(uint32_t Delay);
|
||||
uint32_t HAL_GetTick(void);
|
||||
uint32_t HAL_GetTickPrio(void);
|
||||
HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq);
|
||||
HAL_TickFreqTypeDef HAL_GetTickFreq(void);
|
||||
void HAL_SuspendTick(void);
|
||||
void HAL_ResumeTick(void);
|
||||
uint32_t HAL_GetHalVersion(void);
|
||||
uint32_t HAL_GetREVID(void);
|
||||
uint32_t HAL_GetDEVID(void);
|
||||
uint32_t HAL_GetUIDw0(void);
|
||||
uint32_t HAL_GetUIDw1(void);
|
||||
uint32_t HAL_GetUIDw2(void);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_Exported_Functions_Group3 HAL Debug functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* DBGMCU Peripheral Control functions *****************************************/
|
||||
void HAL_DBGMCU_EnableDBGSleepMode(void);
|
||||
void HAL_DBGMCU_DisableDBGSleepMode(void);
|
||||
void HAL_DBGMCU_EnableDBGStopMode(void);
|
||||
void HAL_DBGMCU_DisableDBGStopMode(void);
|
||||
void HAL_DBGMCU_EnableDBGStandbyMode(void);
|
||||
void HAL_DBGMCU_DisableDBGStandbyMode(void);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported variables ---------------------------------------------------------*/
|
||||
/** @addtogroup HAL_Exported_Variables
|
||||
* @{
|
||||
*/
|
||||
extern __IO uint32_t uwTick;
|
||||
extern uint32_t uwTickPrio;
|
||||
extern HAL_TickFreqTypeDef uwTickFreq;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup HAL_Exported_Functions_Group4 HAL System Configuration functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* SYSCFG Control functions ****************************************************/
|
||||
void HAL_SYSCFG_SRAM2Erase(void);
|
||||
void HAL_SYSCFG_DisableSRAMFetch(void);
|
||||
uint32_t HAL_SYSCFG_IsEnabledSRAMFetch(void);
|
||||
|
||||
#if defined(VREFBUF)
|
||||
void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling);
|
||||
void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode);
|
||||
void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue);
|
||||
HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void);
|
||||
void HAL_SYSCFG_DisableVREFBUF(void);
|
||||
#endif
|
||||
|
||||
void HAL_SYSCFG_EnableIOBooster(void);
|
||||
void HAL_SYSCFG_DisableIOBooster(void);
|
||||
#if defined(SYSCFG_CFGR1_ANASWVDD)
|
||||
void HAL_SYSCFG_EnableIOVdd(void);
|
||||
void HAL_SYSCFG_DisableIOVdd(void);
|
||||
#endif
|
||||
|
||||
void HAL_SYSCFG_EnableSecurityAccess(uint32_t SecurityAccess);
|
||||
void HAL_SYSCFG_DisableSecurityAccess(uint32_t SecurityAccess);
|
||||
uint32_t HAL_SYSCFG_IsEnabledSecurityAccess(uint32_t SecurityAccess);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32WBxx_HAL_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,919 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32wbxx_hal_adc_ex.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of ADC HAL extended module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32WBxx_HAL_ADC_EX_H
|
||||
#define STM32WBxx_HAL_ADC_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32wbxx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32WBxx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup ADCEx
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup ADCEx_Exported_Types ADC Extended Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined (ADC_SUPPORT_2_5_MSPS)
|
||||
/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */
|
||||
#else
|
||||
/**
|
||||
* @brief ADC Injected Conversion Oversampling structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Ratio; /*!< Configures the oversampling ratio.
|
||||
This parameter can be a value of @ref ADC_HAL_EC_OVS_RATIO */
|
||||
|
||||
uint32_t RightBitShift; /*!< Configures the division coefficient for the Oversampler.
|
||||
This parameter can be a value of @ref ADC_HAL_EC_OVS_SHIFT */
|
||||
} ADC_InjOversamplingTypeDef;
|
||||
|
||||
/**
|
||||
* @brief Structure definition of ADC group injected and ADC channel affected to ADC group injected
|
||||
* @note Parameters of this structure are shared within 2 scopes:
|
||||
* - Scope channel: InjectedChannel, InjectedRank, InjectedSamplingTime , InjectedSingleDiff, InjectedOffsetNumber, InjectedOffset
|
||||
* - Scope ADC group injected (affects all channels of injected group): InjectedNbrOfConversion, InjectedDiscontinuousConvMode,
|
||||
* AutoInjectedConv, QueueInjectedContext, ExternalTrigInjecConv, ExternalTrigInjecConvEdge, InjecOversamplingMode, InjecOversampling.
|
||||
* @note The setting of these parameters by function HAL_ADCEx_InjectedConfigChannel() is conditioned to ADC state.
|
||||
* ADC state can be either:
|
||||
* - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'InjectedSingleDiff')
|
||||
* - For parameters 'InjectedDiscontinuousConvMode', 'QueueInjectedContext', 'InjecOversampling': ADC enabled without conversion on going on injected group.
|
||||
* - For parameters 'InjectedSamplingTime', 'InjectedOffset', 'InjectedOffsetNumber', 'AutoInjectedConv': ADC enabled without conversion on going on regular and injected groups.
|
||||
* - For parameters 'InjectedChannel', 'InjectedRank', 'InjectedNbrOfConversion', 'ExternalTrigInjecConv', 'ExternalTrigInjecConvEdge': ADC enabled and while conversion on going
|
||||
* on ADC groups regular and injected.
|
||||
* If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
|
||||
* without error reporting (as it can be the expected behavior in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly).
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t InjectedChannel; /*!< Specifies the channel to configure into ADC group injected.
|
||||
This parameter can be a value of @ref ADC_HAL_EC_CHANNEL
|
||||
Note: Depending on devices and ADC instances, some channels may not be available on device package pins. Refer to device datasheet for channels availability. */
|
||||
|
||||
uint32_t InjectedRank; /*!< Specifies the rank in the ADC group injected sequencer.
|
||||
This parameter must be a value of @ref ADC_INJ_SEQ_RANKS.
|
||||
Note: to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by
|
||||
the new channel setting (or parameter number of conversions adjusted) */
|
||||
|
||||
uint32_t InjectedSamplingTime; /*!< Sampling time value to be set for the selected channel.
|
||||
Unit: ADC clock cycles.
|
||||
Conversion time is the addition of sampling time and processing time
|
||||
(12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits).
|
||||
This parameter can be a value of @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME.
|
||||
Caution: This parameter applies to a channel that can be used in a regular and/or injected group.
|
||||
It overwrites the last setting.
|
||||
Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),
|
||||
sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
|
||||
Refer to device datasheet for timings values. */
|
||||
|
||||
uint32_t InjectedSingleDiff; /*!< Selection of single-ended or differential input.
|
||||
In differential mode: Differential measurement is between the selected channel 'i' (positive input) and channel 'i+1' (negative input).
|
||||
Only channel 'i' has to be configured, channel 'i+1' is configured automatically.
|
||||
This parameter must be a value of @ref ADC_HAL_EC_CHANNEL_SINGLE_DIFF_ENDING.
|
||||
Caution: This parameter applies to a channel that can be used in a regular and/or injected group.
|
||||
It overwrites the last setting.
|
||||
Note: Refer to Reference Manual to ensure the selected channel is available in differential mode.
|
||||
Note: When configuring a channel 'i' in differential mode, the channel 'i+1' is not usable separately.
|
||||
Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion).
|
||||
If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behavior in case
|
||||
of another parameter update on the fly) */
|
||||
|
||||
uint32_t InjectedOffsetNumber; /*!< Selects the offset number.
|
||||
This parameter can be a value of @ref ADC_HAL_EC_OFFSET_NB.
|
||||
Caution: Only one offset is allowed per channel. This parameter overwrites the last setting. */
|
||||
|
||||
uint32_t InjectedOffset; /*!< Defines the offset to be subtracted from the raw converted data.
|
||||
Offset value must be a positive number.
|
||||
Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number
|
||||
between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively.
|
||||
Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled
|
||||
without continuous mode or external trigger that could launch a conversion). */
|
||||
|
||||
uint32_t InjectedNbrOfConversion; /*!< Specifies the number of ranks that will be converted within the ADC group injected sequencer.
|
||||
To use the injected group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
|
||||
This parameter must be a number between Min_Data = 1 and Max_Data = 4.
|
||||
Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
|
||||
configure a channel on injected group can impact the configuration of other channels previously set. */
|
||||
|
||||
FunctionalState InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions sequence of ADC group injected is performed in Complete-sequence/Discontinuous-sequence
|
||||
(main sequence subdivided in successive parts).
|
||||
Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
|
||||
Discontinuous mode can be enabled only if continuous mode is disabled.
|
||||
This parameter can be set to ENABLE or DISABLE.
|
||||
Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion).
|
||||
Note: For injected group, discontinuous mode converts the sequence channel by channel (discontinuous length fixed to 1 rank).
|
||||
Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
|
||||
configure a channel on injected group can impact the configuration of other channels previously set. */
|
||||
|
||||
FunctionalState AutoInjectedConv; /*!< Enables or disables the selected ADC group injected automatic conversion after regular one
|
||||
This parameter can be set to ENABLE or DISABLE.
|
||||
Note: To use Automatic injected conversion, discontinuous mode must be disabled ('DiscontinuousConvMode' and 'InjectedDiscontinuousConvMode' set to DISABLE)
|
||||
Note: To use Automatic injected conversion, injected group external triggers must be disabled ('ExternalTrigInjecConv' set to ADC_INJECTED_SOFTWARE_START)
|
||||
Note: In case of DMA used with regular group: if DMA configured in normal mode (single shot) JAUTO will be stopped upon DMA transfer complete.
|
||||
To maintain JAUTO always enabled, DMA must be configured in circular mode.
|
||||
Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
|
||||
configure a channel on injected group can impact the configuration of other channels previously set. */
|
||||
|
||||
FunctionalState QueueInjectedContext; /*!< Specifies whether the context queue feature is enabled.
|
||||
This parameter can be set to ENABLE or DISABLE.
|
||||
If context queue is enabled, injected sequencer&channels configurations are queued on up to 2 contexts. If a
|
||||
new injected context is set when queue is full, error is triggered by interruption and through function
|
||||
'HAL_ADCEx_InjectedQueueOverflowCallback'.
|
||||
Caution: This feature request that the sequence is fully configured before injected conversion start.
|
||||
Therefore, configure channels with as many calls to HAL_ADCEx_InjectedConfigChannel() as the 'InjectedNbrOfConversion' parameter.
|
||||
Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
|
||||
configure a channel on injected group can impact the configuration of other channels previously set.
|
||||
Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). */
|
||||
|
||||
uint32_t ExternalTrigInjecConv; /*!< Selects the external event used to trigger the conversion start of injected group.
|
||||
If set to ADC_INJECTED_SOFTWARE_START, external triggers are disabled and software trigger is used instead.
|
||||
This parameter can be a value of @ref ADC_injected_external_trigger_source.
|
||||
Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
|
||||
configure a channel on injected group can impact the configuration of other channels previously set. */
|
||||
|
||||
uint32_t ExternalTrigInjecConvEdge; /*!< Selects the external trigger edge of injected group.
|
||||
This parameter can be a value of @ref ADC_injected_external_trigger_edge.
|
||||
If trigger source is set to ADC_INJECTED_SOFTWARE_START, this parameter is discarded.
|
||||
Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
|
||||
configure a channel on injected group can impact the configuration of other channels previously set. */
|
||||
|
||||
FunctionalState InjecOversamplingMode; /*!< Specifies whether the oversampling feature is enabled or disabled.
|
||||
This parameter can be set to ENABLE or DISABLE.
|
||||
Note: This parameter can be modified only if there is no conversion is ongoing (both ADSTART and JADSTART cleared). */
|
||||
|
||||
ADC_InjOversamplingTypeDef InjecOversampling; /*!< Specifies the Oversampling parameters.
|
||||
Caution: this setting overwrites the previous oversampling configuration if oversampling already enabled.
|
||||
Note: This parameter can be modified only if there is no conversion is ongoing (both ADSTART and JADSTART cleared). */
|
||||
} ADC_InjectionConfTypeDef;
|
||||
#endif /* ADC_SUPPORT_2_5_MSPS */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup ADCEx_Exported_Constants ADC Extended Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined (ADC_SUPPORT_2_5_MSPS)
|
||||
/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */
|
||||
#else
|
||||
/** @defgroup ADC_injected_external_trigger_source ADC group injected trigger source
|
||||
* @{
|
||||
*/
|
||||
/* ADC group regular trigger sources for all ADC instances */
|
||||
#define ADC_INJECTED_SOFTWARE_START (LL_ADC_INJ_TRIG_SOFTWARE) /*!< Software triggers injected group conversion start */
|
||||
#define ADC_EXTERNALTRIGINJEC_T1_TRGO (LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM1 TRGO. Trigger edge set to rising edge (default setting). */
|
||||
#define ADC_EXTERNALTRIGINJEC_T1_TRGO2 (LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) /*!< ADC group injected conversion trigger from external peripheral: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */
|
||||
#define ADC_EXTERNALTRIGINJEC_T1_CC4 (LL_ADC_INJ_TRIG_EXT_TIM1_CH4) /*!< ADC group injected conversion trigger from external peripheral: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
|
||||
#define ADC_EXTERNALTRIGINJEC_T2_TRGO (LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM2 TRGO. Trigger edge set to rising edge (default setting). */
|
||||
#define ADC_EXTERNALTRIGINJEC_T2_CC1 (LL_ADC_INJ_TRIG_EXT_TIM2_CH1) /*!< ADC group injected conversion trigger from external peripheral: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
|
||||
#define ADC_EXTERNALTRIGINJEC_EXT_IT15 (LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) /*!< ADC group injected conversion trigger from external peripheral: external interrupt line 15. Trigger edge set to rising edge (default setting). */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_injected_external_trigger_edge ADC group injected trigger edge (when external trigger is selected)
|
||||
* @{
|
||||
*/
|
||||
#define ADC_EXTERNALTRIGINJECCONV_EDGE_NONE (0x00000000UL) /*!< Injected conversions hardware trigger detection disabled */
|
||||
#define ADC_EXTERNALTRIGINJECCONV_EDGE_RISING (ADC_JSQR_JEXTEN_0) /*!< Injected conversions hardware trigger detection on the rising edge */
|
||||
#define ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING (ADC_JSQR_JEXTEN_1) /*!< Injected conversions hardware trigger detection on the falling edge */
|
||||
#define ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING (ADC_JSQR_JEXTEN) /*!< Injected conversions hardware trigger detection on both the rising and falling edges */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* ADC_SUPPORT_2_5_MSPS */
|
||||
|
||||
/** @defgroup ADC_HAL_EC_CHANNEL_SINGLE_DIFF_ENDING Channel - Single or differential ending
|
||||
* @{
|
||||
*/
|
||||
#define ADC_SINGLE_ENDED (LL_ADC_SINGLE_ENDED) /*!< ADC channel ending set to single ended (literal also used to set calibration mode) */
|
||||
#if !defined (ADC_SUPPORT_2_5_MSPS)
|
||||
#define ADC_DIFFERENTIAL_ENDED (LL_ADC_DIFFERENTIAL_ENDED) /*!< ADC channel ending set to differential (literal also used to set calibration mode) */
|
||||
#endif
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_HAL_EC_OFFSET_NB ADC instance - Offset number
|
||||
* @{
|
||||
*/
|
||||
#define ADC_OFFSET_NONE (ADC_OFFSET_4 + 1U) /*!< ADC offset disabled: no offset correction for the selected ADC channel */
|
||||
#define ADC_OFFSET_1 (LL_ADC_OFFSET_1) /*!< ADC offset number 1: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
|
||||
#define ADC_OFFSET_2 (LL_ADC_OFFSET_2) /*!< ADC offset number 2: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
|
||||
#define ADC_OFFSET_3 (LL_ADC_OFFSET_3) /*!< ADC offset number 3: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
|
||||
#define ADC_OFFSET_4 (LL_ADC_OFFSET_4) /*!< ADC offset number 4: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if defined (ADC_SUPPORT_2_5_MSPS)
|
||||
/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */
|
||||
#else
|
||||
/** @defgroup ADC_INJ_SEQ_RANKS ADC group injected - Sequencer ranks
|
||||
* @{
|
||||
*/
|
||||
#define ADC_INJECTED_RANK_1 (LL_ADC_INJ_RANK_1) /*!< ADC group injected sequencer rank 1 */
|
||||
#define ADC_INJECTED_RANK_2 (LL_ADC_INJ_RANK_2) /*!< ADC group injected sequencer rank 2 */
|
||||
#define ADC_INJECTED_RANK_3 (LL_ADC_INJ_RANK_3) /*!< ADC group injected sequencer rank 3 */
|
||||
#define ADC_INJECTED_RANK_4 (LL_ADC_INJ_RANK_4) /*!< ADC group injected sequencer rank 4 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* ADC_SUPPORT_2_5_MSPS */
|
||||
|
||||
/** @defgroup ADC_HAL_EC_GROUPS ADC instance - Groups
|
||||
* @{
|
||||
*/
|
||||
#define ADC_REGULAR_GROUP (LL_ADC_GROUP_REGULAR) /*!< ADC group regular (available on all STM32 devices) */
|
||||
#if defined (ADC_SUPPORT_2_5_MSPS)
|
||||
/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */
|
||||
#else
|
||||
#define ADC_INJECTED_GROUP (LL_ADC_GROUP_INJECTED) /*!< ADC group injected (not available on all STM32 devices)*/
|
||||
#define ADC_REGULAR_INJECTED_GROUP (LL_ADC_GROUP_REGULAR_INJECTED) /*!< ADC both groups regular and injected */
|
||||
#endif /* ADC_SUPPORT_2_5_MSPS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_CFGR_fields ADCx CFGR fields
|
||||
* @{
|
||||
*/
|
||||
#define ADC_CFGR_FIELDS (ADC_CFGR_AWD1CH | ADC_CFGR_JAUTO | ADC_CFGR_JAWD1EN |\
|
||||
ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL | ADC_CFGR_JQM |\
|
||||
ADC_CFGR_JDISCEN | ADC_CFGR_DISCNUM | ADC_CFGR_DISCEN |\
|
||||
ADC_CFGR_AUTDLY | ADC_CFGR_CONT | ADC_CFGR_OVRMOD |\
|
||||
ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL | ADC_CFGR_ALIGN |\
|
||||
ADC_CFGR_RES | ADC_CFGR_DMACFG | ADC_CFGR_DMAEN )
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_SMPR1_fields ADCx SMPR1 fields
|
||||
* @{
|
||||
*/
|
||||
#define ADC_SMPR1_FIELDS (ADC_SMPR1_SMP9 | ADC_SMPR1_SMP8 | ADC_SMPR1_SMP7 |\
|
||||
ADC_SMPR1_SMP6 | ADC_SMPR1_SMP5 | ADC_SMPR1_SMP4 |\
|
||||
ADC_SMPR1_SMP3 | ADC_SMPR1_SMP2 | ADC_SMPR1_SMP1 |\
|
||||
ADC_SMPR1_SMP0)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_CFGR_fields_2 ADCx CFGR sub fields
|
||||
* @{
|
||||
*/
|
||||
/* ADC_CFGR fields of parameters that can be updated when no conversion
|
||||
(neither regular nor injected) is on-going */
|
||||
#define ADC_CFGR_FIELDS_2 ((ADC_CFGR_DMACFG | ADC_CFGR_AUTDLY))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup ADCEx_Private_Macro_internal_HAL_driver ADC Extended Private Macros
|
||||
* @{
|
||||
*/
|
||||
/* Macro reserved for internal HAL driver usage, not intended to be used in */
|
||||
/* code of final user. */
|
||||
|
||||
/**
|
||||
* @brief Test if conversion trigger of injected group is software start
|
||||
* or external trigger.
|
||||
* @param __HANDLE__ ADC handle.
|
||||
* @retval SET (software start) or RESET (external trigger).
|
||||
*/
|
||||
#define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) \
|
||||
(((__HANDLE__)->Instance->JSQR & ADC_JSQR_JEXTEN) == 0UL)
|
||||
|
||||
/**
|
||||
* @brief Check whether or not ADC is independent.
|
||||
* @param __HANDLE__ ADC handle.
|
||||
* @note When multimode feature is not available, the macro always returns SET.
|
||||
* @retval SET (ADC is independent) or RESET (ADC is not).
|
||||
*/
|
||||
#define ADC_IS_INDEPENDENT(__HANDLE__) (SET)
|
||||
|
||||
#if defined (ADC_SUPPORT_2_5_MSPS)
|
||||
/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */
|
||||
#else
|
||||
/**
|
||||
* @brief Set the selected injected Channel rank.
|
||||
* @param __CHANNELNB__ Channel number.
|
||||
* @param __RANKNB__ Rank number.
|
||||
* @retval None
|
||||
*/
|
||||
#define ADC_JSQR_RK(__CHANNELNB__, __RANKNB__) ((((__CHANNELNB__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << ((__RANKNB__) & ADC_INJ_RANK_ID_JSQR_MASK))
|
||||
|
||||
/**
|
||||
* @brief Configure ADC injected context queue
|
||||
* @param __INJECT_CONTEXT_QUEUE_MODE__ Injected context queue mode.
|
||||
* @retval None
|
||||
*/
|
||||
#define ADC_CFGR_INJECT_CONTEXT_QUEUE(__INJECT_CONTEXT_QUEUE_MODE__) ((__INJECT_CONTEXT_QUEUE_MODE__) << ADC_CFGR_JQM_Pos)
|
||||
|
||||
/**
|
||||
* @brief Configure ADC discontinuous conversion mode for injected group
|
||||
* @param __INJECT_DISCONTINUOUS_MODE__ Injected discontinuous mode.
|
||||
* @retval None
|
||||
*/
|
||||
#define ADC_CFGR_INJECT_DISCCONTINUOUS(__INJECT_DISCONTINUOUS_MODE__) ((__INJECT_DISCONTINUOUS_MODE__) << ADC_CFGR_JDISCEN_Pos)
|
||||
#endif /* ADC_SUPPORT_2_5_MSPS */
|
||||
|
||||
/**
|
||||
* @brief Configure ADC discontinuous conversion mode for regular group
|
||||
* @param __REG_DISCONTINUOUS_MODE__ Regular discontinuous mode.
|
||||
* @retval None
|
||||
*/
|
||||
#define ADC_CFGR_REG_DISCONTINUOUS(__REG_DISCONTINUOUS_MODE__) ((__REG_DISCONTINUOUS_MODE__) << ADC_CFGR_DISCEN_Pos)
|
||||
|
||||
/**
|
||||
* @brief Configure the number of discontinuous conversions for regular group.
|
||||
* @param __NBR_DISCONTINUOUS_CONV__ Number of discontinuous conversions.
|
||||
* @retval None
|
||||
*/
|
||||
#define ADC_CFGR_DISCONTINUOUS_NUM(__NBR_DISCONTINUOUS_CONV__) (((__NBR_DISCONTINUOUS_CONV__) - 1UL) << ADC_CFGR_DISCNUM_Pos)
|
||||
|
||||
/**
|
||||
* @brief Configure the ADC auto delay mode.
|
||||
* @param __AUTOWAIT__ Auto delay bit enable or disable.
|
||||
* @retval None
|
||||
*/
|
||||
#define ADC_CFGR_AUTOWAIT(__AUTOWAIT__) ((__AUTOWAIT__) << ADC_CFGR_AUTDLY_Pos)
|
||||
|
||||
/**
|
||||
* @brief Configure ADC continuous conversion mode.
|
||||
* @param __CONTINUOUS_MODE__ Continuous mode.
|
||||
* @retval None
|
||||
*/
|
||||
#define ADC_CFGR_CONTINUOUS(__CONTINUOUS_MODE__) ((__CONTINUOUS_MODE__) << ADC_CFGR_CONT_Pos)
|
||||
|
||||
#if defined (ADC_SUPPORT_2_5_MSPS)
|
||||
/**
|
||||
* @brief Enable ADC overrun mode.
|
||||
* @param _OVERRUN_MODE_ Overrun mode.
|
||||
* @retval Overun bit setting to be programmed into CFGR register
|
||||
*/
|
||||
/* Note: Bit ADC_CFGR1_OVRMOD not used directly in constant */
|
||||
/* "ADC_OVR_DATA_OVERWRITTEN" to have this case defined to 0x00, to set it */
|
||||
/* as the default case to be compliant with other STM32 devices. */
|
||||
#define ADC_CFGR_OVERRUN(_OVERRUN_MODE_) \
|
||||
( ( (_OVERRUN_MODE_) != (ADC_OVR_DATA_PRESERVED) \
|
||||
)? (ADC_CFGR1_OVRMOD) : (0x00000000UL) \
|
||||
)
|
||||
|
||||
/**
|
||||
* @brief Enable the ADC auto off mode.
|
||||
* @param _AUTOOFF_ Auto off bit enable or disable.
|
||||
* @retval None
|
||||
*/
|
||||
#define ADC_CFGR_AUTOOFF(_AUTOOFF_) \
|
||||
((_AUTOOFF_) << 15UL)
|
||||
|
||||
/**
|
||||
* @brief Set ADC scan mode with differentiation of sequencer setting
|
||||
* fixed or configurable
|
||||
* @param _SCAN_MODE_ Scan conversion mode.
|
||||
* @retval None
|
||||
*/
|
||||
/* Note: Scan mode set using this macro (instead of parameter direct set) */
|
||||
/* due to different modes on other STM32 devices: */
|
||||
/* if scan mode is disabled, sequencer is set to fully configurable */
|
||||
/* with setting of only rank 1 enabled afterwards. */
|
||||
#define ADC_SCAN_SEQ_MODE(_SCAN_MODE_) \
|
||||
( (((_SCAN_MODE_) & ADC_SCAN_SEQ_FIXED_INT) != 0UL \
|
||||
)? \
|
||||
((_SCAN_MODE_) & (~ADC_SCAN_SEQ_FIXED_INT)) \
|
||||
: \
|
||||
(ADC_CFGR1_CHSELRMOD) \
|
||||
)
|
||||
|
||||
#endif
|
||||
/**
|
||||
* @brief Configure the ADC DMA continuous request.
|
||||
* @param __DMACONTREQ_MODE__ DMA continuous request mode.
|
||||
* @retval None
|
||||
*/
|
||||
#define ADC_CFGR_DMACONTREQ(__DMACONTREQ_MODE__) ((__DMACONTREQ_MODE__) << ADC_CFGR_DMACFG_Pos)
|
||||
|
||||
|
||||
/**
|
||||
* @brief Shift the offset with respect to the selected ADC resolution.
|
||||
* @note Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0.
|
||||
* If resolution 12 bits, no shift.
|
||||
* If resolution 10 bits, shift of 2 ranks on the left.
|
||||
* If resolution 8 bits, shift of 4 ranks on the left.
|
||||
* If resolution 6 bits, shift of 6 ranks on the left.
|
||||
* Therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2)).
|
||||
* @param __HANDLE__ ADC handle
|
||||
* @param __OFFSET__ Value to be shifted
|
||||
* @retval None
|
||||
*/
|
||||
#define ADC_OFFSET_SHIFT_RESOLUTION(__HANDLE__, __OFFSET__) \
|
||||
((__OFFSET__) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3UL) * 2UL))
|
||||
|
||||
/**
|
||||
* @brief Shift the AWD1 threshold with respect to the selected ADC resolution.
|
||||
* @note Thresholds have to be left-aligned on bit 11, the LSB (right bits) are set to 0.
|
||||
* If resolution 12 bits, no shift.
|
||||
* If resolution 10 bits, shift of 2 ranks on the left.
|
||||
* If resolution 8 bits, shift of 4 ranks on the left.
|
||||
* If resolution 6 bits, shift of 6 ranks on the left.
|
||||
* Therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2)).
|
||||
* @param __HANDLE__ ADC handle
|
||||
* @param __THRESHOLD__ Value to be shifted
|
||||
* @retval None
|
||||
*/
|
||||
#if defined (ADC_SUPPORT_2_5_MSPS)
|
||||
#define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \
|
||||
((__THRESHOLD__) << ((((__HANDLE__)->Instance->CFGR1 & ADC_CFGR1_RES) >> 3UL) * 2UL))
|
||||
#else
|
||||
#define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \
|
||||
((__THRESHOLD__) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3UL) * 2UL))
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Shift the AWD2 and AWD3 threshold with respect to the selected ADC resolution.
|
||||
* @note Thresholds have to be left-aligned on bit 7.
|
||||
* If resolution 12 bits, shift of 4 ranks on the right (the 4 LSB are discarded).
|
||||
* If resolution 10 bits, shift of 2 ranks on the right (the 2 LSB are discarded).
|
||||
* If resolution 8 bits, no shift.
|
||||
* If resolution 6 bits, shift of 2 ranks on the left (the 2 LSB are set to 0).
|
||||
* @param __HANDLE__ ADC handle
|
||||
* @param __THRESHOLD__ Value to be shifted
|
||||
* @retval None
|
||||
*/
|
||||
#if defined (ADC_SUPPORT_2_5_MSPS)
|
||||
#define ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \
|
||||
((((__HANDLE__)->Instance->CFGR1 & ADC_CFGR1_RES) != (ADC_CFGR1_RES_1 | ADC_CFGR1_RES_0)) ? \
|
||||
((__THRESHOLD__) >> ((4UL - ((((__HANDLE__)->Instance->CFGR1 & ADC_CFGR1_RES) >> 3UL) * 2UL)) & 0x1FUL)) : \
|
||||
((__THRESHOLD__) << 2UL) \
|
||||
)
|
||||
#else
|
||||
#define ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \
|
||||
((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) != (ADC_CFGR_RES_1 | ADC_CFGR_RES_0)) ? \
|
||||
((__THRESHOLD__) >> ((4UL - ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3UL) * 2UL)) & 0x1FUL)) : \
|
||||
((__THRESHOLD__) << 2UL) \
|
||||
)
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Clear Common Control Register.
|
||||
* @param __HANDLE__ ADC handle.
|
||||
* @retval None
|
||||
*/
|
||||
#if defined (ADC_SUPPORT_2_5_MSPS)
|
||||
#define ADC_CLEAR_COMMON_CONTROL_REGISTER(__HANDLE__) CLEAR_BIT(__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance)->CCR, \
|
||||
ADC_CCR_PRESC | \
|
||||
ADC_CCR_VBATEN | \
|
||||
ADC_CCR_TSEN | \
|
||||
ADC_CCR_VREFEN )
|
||||
#else
|
||||
#define ADC_CLEAR_COMMON_CONTROL_REGISTER(__HANDLE__) CLEAR_BIT(__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance)->CCR, ADC_CCR_CKMODE | \
|
||||
ADC_CCR_PRESC | \
|
||||
ADC_CCR_VBATEN | \
|
||||
ADC_CCR_TSEN | \
|
||||
ADC_CCR_VREFEN )
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
* @brief Verify the ADC instance connected to the temperature sensor.
|
||||
* @param __HANDLE__ ADC handle.
|
||||
* @retval SET (ADC instance is valid) or RESET (ADC instance is invalid)
|
||||
*/
|
||||
#define ADC_TEMPERATURE_SENSOR_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC1)
|
||||
|
||||
/**
|
||||
* @brief Verify the ADC instance connected to the battery voltage VBAT.
|
||||
* @param __HANDLE__ ADC handle.
|
||||
* @retval SET (ADC instance is valid) or RESET (ADC instance is invalid)
|
||||
*/
|
||||
#define ADC_BATTERY_VOLTAGE_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC1)
|
||||
|
||||
/**
|
||||
* @brief Verify the ADC instance connected to the internal voltage reference VREFINT.
|
||||
* @param __HANDLE__ ADC handle.
|
||||
* @retval SET (ADC instance is valid) or RESET (ADC instance is invalid)
|
||||
*/
|
||||
#define ADC_VREFINT_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC1)
|
||||
|
||||
#if defined (ADC_SUPPORT_2_5_MSPS)
|
||||
/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */
|
||||
#else
|
||||
/**
|
||||
* @brief Verify the length of scheduled injected conversions group.
|
||||
* @param __LENGTH__ number of programmed conversions.
|
||||
* @retval SET (__LENGTH__ is within the maximum number of possible programmable injected conversions) or RESET (__LENGTH__ is null or too large)
|
||||
*/
|
||||
#define IS_ADC_INJECTED_NB_CONV(__LENGTH__) (((__LENGTH__) >= (1U)) && ((__LENGTH__) <= (4U)))
|
||||
#endif /* ADC_SUPPORT_2_5_MSPS */
|
||||
|
||||
/**
|
||||
* @brief Calibration factor size verification (7 bits maximum).
|
||||
* @param __CALIBRATION_FACTOR__ Calibration factor value.
|
||||
* @retval SET (__CALIBRATION_FACTOR__ is within the authorized size) or RESET (__CALIBRATION_FACTOR__ is too large)
|
||||
*/
|
||||
#define IS_ADC_CALFACT(__CALIBRATION_FACTOR__) ((__CALIBRATION_FACTOR__) <= (0x7FU))
|
||||
|
||||
|
||||
/**
|
||||
* @brief Verify the ADC channel setting.
|
||||
* @param __HANDLE__ ADC handle.
|
||||
* @param __CHANNEL__ programmed ADC channel.
|
||||
* @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)
|
||||
*/
|
||||
#define IS_ADC_CHANNEL(__HANDLE__, __CHANNEL__) ((((__HANDLE__)->Instance) == ADC1) && \
|
||||
(((__CHANNEL__) == ADC_CHANNEL_0) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_1) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_2) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_3) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_4) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_5) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_6) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_7) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_8) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_9) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_10) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_11) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_12) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_13) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_14) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_15) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_16) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_17) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_18) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_VREFINT) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_VBAT)))
|
||||
|
||||
/**
|
||||
* @brief Verify the ADC channel setting in differential mode.
|
||||
* @param __HANDLE__ ADC handle.
|
||||
* @param __CHANNEL__ programmed ADC channel.
|
||||
* @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)
|
||||
*/
|
||||
#define IS_ADC_DIFF_CHANNEL(__HANDLE__, __CHANNEL__) (((__CHANNEL__) == ADC_CHANNEL_1) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_2) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_3) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_4) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_5) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_6) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_7) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_8) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_9) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_10) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_11) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_12) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_13) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_14) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_15) )
|
||||
|
||||
/**
|
||||
* @brief Verify the ADC single-ended input or differential mode setting.
|
||||
* @param __SING_DIFF__ programmed channel setting.
|
||||
* @retval SET (__SING_DIFF__ is valid) or RESET (__SING_DIFF__ is invalid)
|
||||
*/
|
||||
#if defined (ADC_SUPPORT_2_5_MSPS)
|
||||
#define IS_ADC_SINGLE_DIFFERENTIAL(__SING_DIFF__) ((__SING_DIFF__) == ADC_SINGLE_ENDED)
|
||||
#else
|
||||
#define IS_ADC_SINGLE_DIFFERENTIAL(__SING_DIFF__) (((__SING_DIFF__) == ADC_SINGLE_ENDED) || \
|
||||
((__SING_DIFF__) == ADC_DIFFERENTIAL_ENDED) )
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Verify the ADC offset management setting.
|
||||
* @param __OFFSET_NUMBER__ ADC offset management.
|
||||
* @retval SET (__OFFSET_NUMBER__ is valid) or RESET (__OFFSET_NUMBER__ is invalid)
|
||||
*/
|
||||
#define IS_ADC_OFFSET_NUMBER(__OFFSET_NUMBER__) (((__OFFSET_NUMBER__) == ADC_OFFSET_NONE) || \
|
||||
((__OFFSET_NUMBER__) == ADC_OFFSET_1) || \
|
||||
((__OFFSET_NUMBER__) == ADC_OFFSET_2) || \
|
||||
((__OFFSET_NUMBER__) == ADC_OFFSET_3) || \
|
||||
((__OFFSET_NUMBER__) == ADC_OFFSET_4) )
|
||||
|
||||
#if defined (ADC_SUPPORT_2_5_MSPS)
|
||||
/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */
|
||||
#else
|
||||
/**
|
||||
* @brief Verify the ADC injected channel setting.
|
||||
* @param __CHANNEL__ programmed ADC injected channel.
|
||||
* @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)
|
||||
*/
|
||||
#define IS_ADC_INJECTED_RANK(__CHANNEL__) (((__CHANNEL__) == ADC_INJECTED_RANK_1) || \
|
||||
((__CHANNEL__) == ADC_INJECTED_RANK_2) || \
|
||||
((__CHANNEL__) == ADC_INJECTED_RANK_3) || \
|
||||
((__CHANNEL__) == ADC_INJECTED_RANK_4) )
|
||||
|
||||
/**
|
||||
* @brief Verify the ADC injected conversions external trigger.
|
||||
* @param __HANDLE__ ADC handle.
|
||||
* @param __INJTRIG__ programmed ADC injected conversions external trigger.
|
||||
* @retval SET (__INJTRIG__ is a valid value) or RESET (__INJTRIG__ is invalid)
|
||||
*/
|
||||
#define IS_ADC_EXTTRIGINJEC(__HANDLE__, __INJTRIG__) (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC4) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_TRGO) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_CC1) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT15) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO2) || \
|
||||
((__INJTRIG__) == ADC_INJECTED_SOFTWARE_START) )
|
||||
|
||||
/**
|
||||
* @brief Verify the ADC edge trigger setting for injected group.
|
||||
* @param __EDGE__ programmed ADC edge trigger setting.
|
||||
* @retval SET (__EDGE__ is a valid value) or RESET (__EDGE__ is invalid)
|
||||
*/
|
||||
#define IS_ADC_EXTTRIGINJEC_EDGE(__EDGE__) (((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE) || \
|
||||
((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISING) || \
|
||||
((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING) || \
|
||||
((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING) )
|
||||
#endif /* ADC_SUPPORT_2_5_MSPS */
|
||||
|
||||
/**
|
||||
* @brief Verify the ADC analog watchdog setting.
|
||||
* @param __WATCHDOG__ programmed ADC analog watchdog setting.
|
||||
* @retval SET (__WATCHDOG__ is valid) or RESET (__WATCHDOG__ is invalid)
|
||||
*/
|
||||
#if defined (ADC_SUPPORT_2_5_MSPS)
|
||||
#define IS_ADC_ANALOG_WATCHDOG_NUMBER(__WATCHDOG__) ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_1)
|
||||
#else
|
||||
#define IS_ADC_ANALOG_WATCHDOG_NUMBER(__WATCHDOG__) (((__WATCHDOG__) == ADC_ANALOGWATCHDOG_1) || \
|
||||
((__WATCHDOG__) == ADC_ANALOGWATCHDOG_2) || \
|
||||
((__WATCHDOG__) == ADC_ANALOGWATCHDOG_3) )
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Verify the ADC analog watchdog mode setting.
|
||||
* @param __WATCHDOG_MODE__ programmed ADC analog watchdog mode setting.
|
||||
* @retval SET (__WATCHDOG_MODE__ is valid) or RESET (__WATCHDOG_MODE__ is invalid)
|
||||
*/
|
||||
#if defined (ADC_SUPPORT_2_5_MSPS)
|
||||
#define IS_ADC_ANALOG_WATCHDOG_MODE(__WATCHDOG_MODE__) (((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_NONE) || \
|
||||
((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \
|
||||
((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REG) )
|
||||
#else
|
||||
#define IS_ADC_ANALOG_WATCHDOG_MODE(__WATCHDOG_MODE__) (((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_NONE) || \
|
||||
((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \
|
||||
((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || \
|
||||
((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) || \
|
||||
((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REG) || \
|
||||
((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_INJEC) || \
|
||||
((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) )
|
||||
#endif /* ADC_SUPPORT_2_5_MSPS */
|
||||
|
||||
#if defined (ADC_SUPPORT_2_5_MSPS)
|
||||
#define IS_ADC_TRIGGER_FREQ(TRIGGER_FREQ) (((TRIGGER_FREQ) == LL_ADC_TRIGGER_FREQ_HIGH) || \
|
||||
((TRIGGER_FREQ) == LL_ADC_TRIGGER_FREQ_LOW) )
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Verify the ADC conversion (regular or injected or both).
|
||||
* @param __CONVERSION__ ADC conversion group.
|
||||
* @retval SET (__CONVERSION__ is valid) or RESET (__CONVERSION__ is invalid)
|
||||
*/
|
||||
#define IS_ADC_CONVERSION_GROUP(__CONVERSION__) (((__CONVERSION__) == ADC_REGULAR_GROUP) || \
|
||||
((__CONVERSION__) == ADC_INJECTED_GROUP) || \
|
||||
((__CONVERSION__) == ADC_REGULAR_INJECTED_GROUP) )
|
||||
|
||||
/**
|
||||
* @brief Verify the ADC event type.
|
||||
* @param __EVENT__ ADC event.
|
||||
* @retval SET (__EVENT__ is valid) or RESET (__EVENT__ is invalid)
|
||||
*/
|
||||
#if defined (ADC_SUPPORT_2_5_MSPS)
|
||||
#define IS_ADC_EVENT_TYPE(__EVENT__) (((__EVENT__) == ADC_EOSMP_EVENT) || \
|
||||
((__EVENT__) == ADC_AWD1_EVENT) || \
|
||||
((__EVENT__) == ADC_AWD2_EVENT) || \
|
||||
((__EVENT__) == ADC_AWD3_EVENT) || \
|
||||
((__EVENT__) == ADC_OVR_EVENT) )
|
||||
#else
|
||||
#define IS_ADC_EVENT_TYPE(__EVENT__) (((__EVENT__) == ADC_EOSMP_EVENT) || \
|
||||
((__EVENT__) == ADC_AWD_EVENT) || \
|
||||
((__EVENT__) == ADC_AWD2_EVENT) || \
|
||||
((__EVENT__) == ADC_AWD3_EVENT) || \
|
||||
((__EVENT__) == ADC_OVR_EVENT) || \
|
||||
((__EVENT__) == ADC_JQOVF_EVENT) )
|
||||
#endif /* ADC_SUPPORT_2_5_MSPS */
|
||||
|
||||
#if defined (ADC_SUPPORT_2_5_MSPS)
|
||||
/* Feature "ADC oversampling" not available on ADC peripheral of this STM32WB device */
|
||||
#else
|
||||
/**
|
||||
* @brief Verify the ADC oversampling ratio.
|
||||
* @param __RATIO__ programmed ADC oversampling ratio.
|
||||
* @retval SET (__RATIO__ is a valid value) or RESET (__RATIO__ is invalid)
|
||||
*/
|
||||
#define IS_ADC_OVERSAMPLING_RATIO(__RATIO__) (((__RATIO__) == ADC_OVERSAMPLING_RATIO_2 ) || \
|
||||
((__RATIO__) == ADC_OVERSAMPLING_RATIO_4 ) || \
|
||||
((__RATIO__) == ADC_OVERSAMPLING_RATIO_8 ) || \
|
||||
((__RATIO__) == ADC_OVERSAMPLING_RATIO_16 ) || \
|
||||
((__RATIO__) == ADC_OVERSAMPLING_RATIO_32 ) || \
|
||||
((__RATIO__) == ADC_OVERSAMPLING_RATIO_64 ) || \
|
||||
((__RATIO__) == ADC_OVERSAMPLING_RATIO_128 ) || \
|
||||
((__RATIO__) == ADC_OVERSAMPLING_RATIO_256 ))
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Verify the ADC oversampling shift.
|
||||
* @param __SHIFT__ programmed ADC oversampling shift.
|
||||
* @retval SET (__SHIFT__ is a valid value) or RESET (__SHIFT__ is invalid)
|
||||
*/
|
||||
#define IS_ADC_RIGHT_BIT_SHIFT(__SHIFT__) (((__SHIFT__) == ADC_RIGHTBITSHIFT_NONE) || \
|
||||
((__SHIFT__) == ADC_RIGHTBITSHIFT_1 ) || \
|
||||
((__SHIFT__) == ADC_RIGHTBITSHIFT_2 ) || \
|
||||
((__SHIFT__) == ADC_RIGHTBITSHIFT_3 ) || \
|
||||
((__SHIFT__) == ADC_RIGHTBITSHIFT_4 ) || \
|
||||
((__SHIFT__) == ADC_RIGHTBITSHIFT_5 ) || \
|
||||
((__SHIFT__) == ADC_RIGHTBITSHIFT_6 ) || \
|
||||
((__SHIFT__) == ADC_RIGHTBITSHIFT_7 ) || \
|
||||
((__SHIFT__) == ADC_RIGHTBITSHIFT_8 ))
|
||||
|
||||
/**
|
||||
* @brief Verify the ADC oversampling triggered mode.
|
||||
* @param __MODE__ programmed ADC oversampling triggered mode.
|
||||
* @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
|
||||
*/
|
||||
#define IS_ADC_TRIGGERED_OVERSAMPLING_MODE(__MODE__) (((__MODE__) == ADC_TRIGGEREDMODE_SINGLE_TRIGGER) || \
|
||||
((__MODE__) == ADC_TRIGGEREDMODE_MULTI_TRIGGER) )
|
||||
|
||||
#if defined (ADC_SUPPORT_2_5_MSPS)
|
||||
#else
|
||||
/**
|
||||
* @brief Verify the ADC oversampling regular conversion resumed or continued mode.
|
||||
* @param __MODE__ programmed ADC oversampling regular conversion resumed or continued mode.
|
||||
* @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
|
||||
*/
|
||||
#define IS_ADC_REGOVERSAMPLING_MODE(__MODE__) (((__MODE__) == ADC_REGOVERSAMPLING_CONTINUED_MODE) || \
|
||||
((__MODE__) == ADC_REGOVERSAMPLING_RESUMED_MODE) )
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Verify the DFSDM mode configuration.
|
||||
* @param __HANDLE__ ADC handle.
|
||||
* @note When DMSDFM configuration is not supported, the macro systematically reports SET. For
|
||||
* this reason, the input parameter is the ADC handle and not the configuration parameter
|
||||
* directly.
|
||||
* @retval SET (DFSDM mode configuration is valid) or RESET (DFSDM mode configuration is invalid)
|
||||
*/
|
||||
#define IS_ADC_DFSDMCFG_MODE(__HANDLE__) (SET)
|
||||
|
||||
/**
|
||||
* @brief Return the DFSDM configuration mode.
|
||||
* @param __HANDLE__ ADC handle.
|
||||
* @note When DMSDFM configuration is not supported, the macro systematically reports 0x0 (i.e disabled).
|
||||
* For this reason, the input parameter is the ADC handle and not the configuration parameter
|
||||
* directly.
|
||||
* @retval DFSDM configuration mode
|
||||
*/
|
||||
#define ADC_CFGR_DFSDM(__HANDLE__) (0x0UL)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup ADCEx_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup ADCEx_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
/* IO operation functions *****************************************************/
|
||||
|
||||
/* ADC calibration */
|
||||
HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc, uint32_t SingleDiff);
|
||||
uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff);
|
||||
HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff,
|
||||
uint32_t CalibrationFactor);
|
||||
|
||||
#if defined (ADC_SUPPORT_2_5_MSPS)
|
||||
/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */
|
||||
#else
|
||||
/* Blocking mode: Polling */
|
||||
HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef *hadc);
|
||||
HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef *hadc);
|
||||
HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout);
|
||||
|
||||
/* Non-blocking mode: Interruption */
|
||||
HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef *hadc);
|
||||
HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef *hadc);
|
||||
#endif /* ADC_SUPPORT_2_5_MSPS */
|
||||
|
||||
#if defined (ADC_SUPPORT_2_5_MSPS)
|
||||
/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */
|
||||
#else
|
||||
/* ADC retrieve conversion value intended to be used with polling or interruption */
|
||||
uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef *hadc, uint32_t InjectedRank);
|
||||
#endif /* ADC_SUPPORT_2_5_MSPS */
|
||||
|
||||
/* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption) */
|
||||
#if defined (ADC_SUPPORT_2_5_MSPS)
|
||||
/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */
|
||||
#else
|
||||
void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef *hadc);
|
||||
void HAL_ADCEx_InjectedQueueOverflowCallback(ADC_HandleTypeDef *hadc);
|
||||
#endif /* ADC_SUPPORT_2_5_MSPS */
|
||||
void HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef *hadc);
|
||||
void HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef *hadc);
|
||||
void HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef *hadc);
|
||||
|
||||
#if defined (ADC_SUPPORT_2_5_MSPS)
|
||||
/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */
|
||||
#else
|
||||
/* ADC group regular conversions stop */
|
||||
HAL_StatusTypeDef HAL_ADCEx_RegularStop(ADC_HandleTypeDef *hadc);
|
||||
HAL_StatusTypeDef HAL_ADCEx_RegularStop_IT(ADC_HandleTypeDef *hadc);
|
||||
HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef *hadc);
|
||||
#endif /* ADC_SUPPORT_2_5_MSPS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup ADCEx_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral Control functions ***********************************************/
|
||||
#if defined (ADC_SUPPORT_2_5_MSPS)
|
||||
/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */
|
||||
#else
|
||||
HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc,ADC_InjectionConfTypeDef* sConfigInjected);
|
||||
#endif /* ADC_SUPPORT_2_5_MSPS */
|
||||
#if defined (ADC_SUPPORT_2_5_MSPS)
|
||||
/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */
|
||||
#else
|
||||
HAL_StatusTypeDef HAL_ADCEx_EnableInjectedQueue(ADC_HandleTypeDef *hadc);
|
||||
HAL_StatusTypeDef HAL_ADCEx_DisableInjectedQueue(ADC_HandleTypeDef *hadc);
|
||||
#endif /* ADC_SUPPORT_2_5_MSPS */
|
||||
HAL_StatusTypeDef HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef *hadc);
|
||||
#if defined (ADC_SUPPORT_2_5_MSPS)
|
||||
/* Feature " ADC deep power-down" not available on ADC peripheral of this STM32WB device */
|
||||
#else
|
||||
HAL_StatusTypeDef HAL_ADCEx_EnterADCDeepPowerDownMode(ADC_HandleTypeDef *hadc);
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32WBxx_HAL_ADC_EX_H */
|
||||
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -1,747 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32wbxx_hal_comp.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of COMP HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32WBxx_HAL_COMP_H
|
||||
#define STM32WBxx_HAL_COMP_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32wbxx_hal_def.h"
|
||||
#include "stm32wbxx_ll_exti.h"
|
||||
|
||||
/** @addtogroup STM32WBxx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
#if defined (COMP1) || defined (COMP2)
|
||||
|
||||
/** @addtogroup COMP
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup COMP_Exported_Types COMP Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief COMP Init structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
|
||||
#if defined(COMP2)
|
||||
uint32_t WindowMode; /*!< Set window mode of a pair of comparators instances
|
||||
(2 consecutive instances odd and even COMP<x> and COMP<x+1>).
|
||||
Note: HAL COMP driver allows to set window mode from any COMP instance of the pair of COMP instances composing window mode.
|
||||
This parameter can be a value of @ref COMP_WindowMode */
|
||||
#endif /* COMP2 */
|
||||
|
||||
uint32_t Mode; /*!< Set comparator operating mode to adjust power and speed.
|
||||
Note: For the characteristics of comparator power modes
|
||||
(propagation delay and power consumption), refer to device datasheet.
|
||||
This parameter can be a value of @ref COMP_PowerMode */
|
||||
|
||||
uint32_t InputPlus; /*!< Set comparator input plus (non-inverting input).
|
||||
This parameter can be a value of @ref COMP_InputPlus */
|
||||
|
||||
uint32_t InputMinus; /*!< Set comparator input minus (inverting input).
|
||||
This parameter can be a value of @ref COMP_InputMinus */
|
||||
|
||||
uint32_t Hysteresis; /*!< Set comparator hysteresis mode of the input minus.
|
||||
This parameter can be a value of @ref COMP_Hysteresis */
|
||||
|
||||
uint32_t OutputPol; /*!< Set comparator output polarity.
|
||||
This parameter can be a value of @ref COMP_OutputPolarity */
|
||||
|
||||
uint32_t BlankingSrce; /*!< Set comparator blanking source.
|
||||
This parameter can be a value of @ref COMP_BlankingSrce */
|
||||
|
||||
uint32_t TriggerMode; /*!< Set the comparator output triggering External Interrupt Line (EXTI).
|
||||
This parameter can be a value of @ref COMP_EXTI_TriggerMode */
|
||||
|
||||
} COMP_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL COMP state machine: HAL COMP states definition
|
||||
*/
|
||||
#define COMP_STATE_BITFIELD_LOCK (0x10U)
|
||||
typedef enum
|
||||
{
|
||||
HAL_COMP_STATE_RESET = 0x00U, /*!< COMP not yet initialized */
|
||||
HAL_COMP_STATE_RESET_LOCKED = (HAL_COMP_STATE_RESET | COMP_STATE_BITFIELD_LOCK), /*!< COMP not yet initialized and configuration is locked */
|
||||
HAL_COMP_STATE_READY = 0x01U, /*!< COMP initialized and ready for use */
|
||||
HAL_COMP_STATE_READY_LOCKED = (HAL_COMP_STATE_READY | COMP_STATE_BITFIELD_LOCK), /*!< COMP initialized but configuration is locked */
|
||||
HAL_COMP_STATE_BUSY = 0x02U, /*!< COMP is running */
|
||||
HAL_COMP_STATE_BUSY_LOCKED = (HAL_COMP_STATE_BUSY | COMP_STATE_BITFIELD_LOCK) /*!< COMP is running and configuration is locked */
|
||||
} HAL_COMP_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief COMP Handle Structure definition
|
||||
*/
|
||||
#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
|
||||
typedef struct __COMP_HandleTypeDef
|
||||
#else
|
||||
typedef struct
|
||||
#endif
|
||||
{
|
||||
COMP_TypeDef *Instance; /*!< Register base address */
|
||||
COMP_InitTypeDef Init; /*!< COMP required parameters */
|
||||
HAL_LockTypeDef Lock; /*!< Locking object */
|
||||
__IO HAL_COMP_StateTypeDef State; /*!< COMP communication state */
|
||||
__IO uint32_t ErrorCode; /*!< COMP error code */
|
||||
#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
|
||||
void (* TriggerCallback)(struct __COMP_HandleTypeDef *hcomp); /*!< COMP trigger callback */
|
||||
void (* MspInitCallback)(struct __COMP_HandleTypeDef *hcomp); /*!< COMP Msp Init callback */
|
||||
void (* MspDeInitCallback)(struct __COMP_HandleTypeDef *hcomp); /*!< COMP Msp DeInit callback */
|
||||
#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
|
||||
} COMP_HandleTypeDef;
|
||||
|
||||
#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
|
||||
/**
|
||||
* @brief HAL COMP Callback ID enumeration definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_COMP_TRIGGER_CB_ID = 0x00U, /*!< COMP trigger callback ID */
|
||||
HAL_COMP_MSPINIT_CB_ID = 0x01U, /*!< COMP Msp Init callback ID */
|
||||
HAL_COMP_MSPDEINIT_CB_ID = 0x02U /*!< COMP Msp DeInit callback ID */
|
||||
} HAL_COMP_CallbackIDTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL COMP Callback pointer definition
|
||||
*/
|
||||
typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer to a COMP callback function */
|
||||
|
||||
#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup COMP_Exported_Constants COMP Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_Error_Code COMP Error Code
|
||||
* @{
|
||||
*/
|
||||
#define HAL_COMP_ERROR_NONE (0x00UL) /*!< No error */
|
||||
#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
|
||||
#define HAL_COMP_ERROR_INVALID_CALLBACK (0x01UL) /*!< Invalid Callback error */
|
||||
#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if defined(COMP2)
|
||||
/** @defgroup COMP_WindowMode COMP Window Mode
|
||||
* @{
|
||||
*/
|
||||
#define COMP_WINDOWMODE_DISABLE (0x00000000UL) /*!< Window mode disable: Comparators instances pair COMP1 and COMP2 are independent */
|
||||
#define COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON (COMP_CSR_WINMODE) /*!< Window mode enable: Comparators instances pair COMP1 and COMP2 have their input plus connected together. The common input is COMP1 input plus (COMP2 input plus is no more accessible). */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif
|
||||
|
||||
/** @defgroup COMP_PowerMode COMP power mode
|
||||
* @{
|
||||
*/
|
||||
/* Note: For the characteristics of comparator power modes */
|
||||
/* (propagation delay and power consumption), */
|
||||
/* refer to device datasheet. */
|
||||
#define COMP_POWERMODE_HIGHSPEED (0x00000000UL) /*!< High Speed */
|
||||
#define COMP_POWERMODE_MEDIUMSPEED (COMP_CSR_PWRMODE_0) /*!< Medium Speed */
|
||||
#define COMP_POWERMODE_ULTRALOWPOWER (COMP_CSR_PWRMODE) /*!< Ultra-low power mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_InputPlus COMP input plus (non-inverting input)
|
||||
* @{
|
||||
*/
|
||||
#if defined(STM32WB15xx) || defined(STM32WB10xx)
|
||||
/* COMP_INPUT_PLUS_IO1 not available on this device */
|
||||
#else
|
||||
#define COMP_INPUT_PLUS_IO1 (0x00000000UL) /*!< Comparator input plus connected to IO1 (pin PC5 for COMP1 (except device STM32WB35xx), pin PB4 for COMP2). Note: On STM32WB serie, parameter not available on devices: STM32WB10xx, STM32WB15xx. */
|
||||
#endif
|
||||
#define COMP_INPUT_PLUS_IO2 (COMP_CSR_INPSEL_0) /*!< Comparator input plus connected to IO2 (pin PB2 for COMP1, pin PB6 for COMP2) */
|
||||
#define COMP_INPUT_PLUS_IO3 (COMP_CSR_INPSEL_1) /*!< Comparator input plus connected to IO3 (pin PA1 for COMP1, pin PA3 for COMP2) */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_InputMinus COMP input minus (inverting input)
|
||||
* @{
|
||||
*/
|
||||
#define COMP_INPUT_MINUS_1_4VREFINT ( COMP_CSR_SCALEN | COMP_CSR_BRGEN) /*!< Comparator input minus connected to 1/4 VrefInt */
|
||||
#define COMP_INPUT_MINUS_1_2VREFINT ( COMP_CSR_INMSEL_0 | COMP_CSR_SCALEN | COMP_CSR_BRGEN) /*!< Comparator input minus connected to 1/2 VrefInt */
|
||||
#define COMP_INPUT_MINUS_3_4VREFINT ( COMP_CSR_INMSEL_1 | COMP_CSR_SCALEN | COMP_CSR_BRGEN) /*!< Comparator input minus connected to 3/4 VrefInt */
|
||||
#define COMP_INPUT_MINUS_VREFINT ( COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0 | COMP_CSR_SCALEN ) /*!< Comparator input minus connected to VrefInt */
|
||||
#define COMP_INPUT_MINUS_IO1 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 ) /*!< Comparator input minus connected to IO1 (pin PB1 for COMP1, pin PB3 for COMP2) */
|
||||
#if defined(STM32WB15xx) || defined(STM32WB10xx)
|
||||
/* COMP_INPUT_MINUS_IO2 not available on this device */
|
||||
#else
|
||||
#define COMP_INPUT_MINUS_IO2 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to IO2 (pin PC4 for COMP1 (except device STM32WB35xx), pin PB7 for COMP2). Note: On STM32WB serie, parameter not available on devices: STM32WB10xx, STM32WB15xx. */
|
||||
#endif
|
||||
#define COMP_INPUT_MINUS_IO3 ( COMP_CSR_INMESEL_0 | COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to IO3 (pin PA0 for COMP1, pin PA2 for COMP2) */
|
||||
#define COMP_INPUT_MINUS_IO4 (COMP_CSR_INMESEL_1 | COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to IO4 (pin PA4 for COMP1, pin PA4 for COMP2) */
|
||||
#define COMP_INPUT_MINUS_IO5 (COMP_CSR_INMESEL_1 | COMP_CSR_INMESEL_0 | COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to IO5 (pin PA5 for COMP1, pin PA5 for COMP2) */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_Hysteresis COMP hysteresis
|
||||
* @{
|
||||
*/
|
||||
#define COMP_HYSTERESIS_NONE (0x00000000UL) /*!< No hysteresis */
|
||||
#define COMP_HYSTERESIS_LOW ( COMP_CSR_HYST_0) /*!< Hysteresis level low */
|
||||
#define COMP_HYSTERESIS_MEDIUM (COMP_CSR_HYST_1 ) /*!< Hysteresis level medium */
|
||||
#define COMP_HYSTERESIS_HIGH (COMP_CSR_HYST_1 | COMP_CSR_HYST_0) /*!< Hysteresis level high */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_OutputPolarity COMP output Polarity
|
||||
* @{
|
||||
*/
|
||||
#define COMP_OUTPUTPOL_NONINVERTED (0x00000000UL) /*!< COMP output level is not inverted (comparator output is high when the input plus is at a higher voltage than the input minus) */
|
||||
#define COMP_OUTPUTPOL_INVERTED (COMP_CSR_POLARITY) /*!< COMP output level is inverted (comparator output is low when the input plus is at a higher voltage than the input minus) */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_BlankingSrce COMP blanking source
|
||||
* @{
|
||||
*/
|
||||
#define COMP_BLANKINGSRC_NONE (0x00000000UL) /*!<Comparator output without blanking */
|
||||
/* Note: Output blanking source common to all COMP instances */
|
||||
#define COMP_BLANKINGSRC_TIM1_OC5 (COMP_CSR_BLANKING_0) /*!< Comparator output blanking source TIM1 OC5 (common to all COMP instances: COMP1, COMP2) */
|
||||
#define COMP_BLANKINGSRC_TIM2_OC3 (COMP_CSR_BLANKING_1) /*!< Comparator output blanking source TIM2 OC3 (common to all COMP instances: COMP1, COMP2) */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_OutputLevel COMP Output Level
|
||||
* @{
|
||||
*/
|
||||
/* Note: Comparator output level values are fixed to "0" and "1", */
|
||||
/* corresponding COMP register bit is managed by HAL function to match */
|
||||
/* with these values (independently of bit position in register). */
|
||||
|
||||
/* When output polarity is not inverted, comparator output is low when
|
||||
the input plus is at a lower voltage than the input minus */
|
||||
#define COMP_OUTPUT_LEVEL_LOW (0x00000000UL)
|
||||
/* When output polarity is not inverted, comparator output is high when
|
||||
the input plus is at a higher voltage than the input minus */
|
||||
#define COMP_OUTPUT_LEVEL_HIGH (0x00000001UL)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_EXTI_TriggerMode COMP output to EXTI
|
||||
* @{
|
||||
*/
|
||||
#define COMP_TRIGGERMODE_NONE (0x00000000UL) /*!< Comparator output triggering no External Interrupt Line */
|
||||
#define COMP_TRIGGERMODE_IT_RISING (COMP_EXTI_IT | COMP_EXTI_RISING) /*!< Comparator output triggering External Interrupt Line event with interruption, on rising edge */
|
||||
#define COMP_TRIGGERMODE_IT_FALLING (COMP_EXTI_IT | COMP_EXTI_FALLING) /*!< Comparator output triggering External Interrupt Line event with interruption, on falling edge */
|
||||
#define COMP_TRIGGERMODE_IT_RISING_FALLING (COMP_EXTI_IT | COMP_EXTI_RISING | COMP_EXTI_FALLING) /*!< Comparator output triggering External Interrupt Line event with interruption, on both rising and falling edges */
|
||||
#define COMP_TRIGGERMODE_EVENT_RISING (COMP_EXTI_EVENT | COMP_EXTI_RISING) /*!< Comparator output triggering External Interrupt Line event only (without interruption), on rising edge */
|
||||
#define COMP_TRIGGERMODE_EVENT_FALLING (COMP_EXTI_EVENT | COMP_EXTI_FALLING) /*!< Comparator output triggering External Interrupt Line event only (without interruption), on falling edge */
|
||||
#define COMP_TRIGGERMODE_EVENT_RISING_FALLING (COMP_EXTI_EVENT | COMP_EXTI_RISING | COMP_EXTI_FALLING) /*!< Comparator output triggering External Interrupt Line event only (without interruption), on both rising and falling edges */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup COMP_Exported_Macros COMP Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_Handle_Management COMP Handle Management
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset COMP handle state.
|
||||
* @param __HANDLE__ COMP handle
|
||||
* @retval None
|
||||
*/
|
||||
#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
|
||||
#define __HAL_COMP_RESET_HANDLE_STATE(__HANDLE__) do{ \
|
||||
(__HANDLE__)->State = HAL_COMP_STATE_RESET; \
|
||||
(__HANDLE__)->MspInitCallback = NULL; \
|
||||
(__HANDLE__)->MspDeInitCallback = NULL; \
|
||||
} while(0)
|
||||
#else
|
||||
#define __HAL_COMP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_COMP_STATE_RESET)
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Clear COMP error code (set it to no error code "HAL_COMP_ERROR_NONE").
|
||||
* @param __HANDLE__ COMP handle
|
||||
* @retval None
|
||||
*/
|
||||
#define COMP_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_COMP_ERROR_NONE)
|
||||
|
||||
/**
|
||||
* @brief Enable the specified comparator.
|
||||
* @param __HANDLE__ COMP handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_EN)
|
||||
|
||||
/**
|
||||
* @brief Disable the specified comparator.
|
||||
* @param __HANDLE__ COMP handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_EN)
|
||||
|
||||
/**
|
||||
* @brief Lock the specified comparator configuration.
|
||||
* @note Using this macro induce HAL COMP handle state machine being no
|
||||
* more in line with COMP instance state.
|
||||
* To keep HAL COMP handle state machine updated, it is recommended
|
||||
* to use function "HAL_COMP_Lock')".
|
||||
* @param __HANDLE__ COMP handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_LOCK(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_LOCK)
|
||||
|
||||
/**
|
||||
* @brief Check whether the specified comparator is locked.
|
||||
* @param __HANDLE__ COMP handle
|
||||
* @retval Value 0 if COMP instance is not locked, value 1 if COMP instance is locked
|
||||
*/
|
||||
#define __HAL_COMP_IS_LOCKED(__HANDLE__) (READ_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_LOCK) == COMP_CSR_LOCK)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_Exti_Management COMP external interrupt line management
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enable the COMP1 EXTI line rising edge trigger.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP1)
|
||||
|
||||
/**
|
||||
* @brief Disable the COMP1 EXTI line rising edge trigger.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP1)
|
||||
|
||||
/**
|
||||
* @brief Enable the COMP1 EXTI line falling edge trigger.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP1)
|
||||
|
||||
/**
|
||||
* @brief Disable the COMP1 EXTI line falling edge trigger.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP1)
|
||||
|
||||
/**
|
||||
* @brief Enable the COMP1 EXTI line rising & falling edge trigger.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP1_EXTI_ENABLE_RISING_FALLING_EDGE() do { \
|
||||
LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP1); \
|
||||
LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP1); \
|
||||
} while(0)
|
||||
|
||||
/**
|
||||
* @brief Disable the COMP1 EXTI line rising & falling edge trigger.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP1_EXTI_DISABLE_RISING_FALLING_EDGE() do { \
|
||||
LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP1); \
|
||||
LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP1); \
|
||||
} while(0)
|
||||
|
||||
/**
|
||||
* @brief Enable the COMP1 EXTI line in interrupt mode.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP1_EXTI_ENABLE_IT() LL_EXTI_EnableIT_0_31(COMP_EXTI_LINE_COMP1)
|
||||
|
||||
/**
|
||||
* @brief Disable the COMP1 EXTI line in interrupt mode.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP1_EXTI_DISABLE_IT() LL_EXTI_DisableIT_0_31(COMP_EXTI_LINE_COMP1)
|
||||
|
||||
/**
|
||||
* @brief Generate a software interrupt on the COMP1 EXTI line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP1_EXTI_GENERATE_SWIT() LL_EXTI_GenerateSWI_0_31(COMP_EXTI_LINE_COMP1)
|
||||
|
||||
/**
|
||||
* @brief Enable the COMP1 EXTI line in event mode.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP1_EXTI_ENABLE_EVENT() LL_EXTI_EnableEvent_0_31(COMP_EXTI_LINE_COMP1)
|
||||
|
||||
/**
|
||||
* @brief Disable the COMP1 EXTI line in event mode.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP1_EXTI_DISABLE_EVENT() LL_EXTI_DisableEvent_0_31(COMP_EXTI_LINE_COMP1)
|
||||
|
||||
/**
|
||||
* @brief Check whether the COMP1 EXTI line flag is set.
|
||||
* @retval RESET or SET
|
||||
*/
|
||||
#define __HAL_COMP_COMP1_EXTI_GET_FLAG() LL_EXTI_IsActiveFlag_0_31(COMP_EXTI_LINE_COMP1)
|
||||
|
||||
/**
|
||||
* @brief Clear the COMP1 EXTI flag.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() LL_EXTI_ClearFlag_0_31(COMP_EXTI_LINE_COMP1)
|
||||
|
||||
#if defined(COMP2)
|
||||
/**
|
||||
* @brief Enable the COMP2 EXTI line rising edge trigger.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP2)
|
||||
|
||||
/**
|
||||
* @brief Disable the COMP2 EXTI line rising edge trigger.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP2)
|
||||
|
||||
/**
|
||||
* @brief Enable the COMP2 EXTI line falling edge trigger.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP2)
|
||||
|
||||
/**
|
||||
* @brief Disable the COMP2 EXTI line falling edge trigger.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP2)
|
||||
|
||||
/**
|
||||
* @brief Enable the COMP2 EXTI line rising & falling edge trigger.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP2_EXTI_ENABLE_RISING_FALLING_EDGE() do { \
|
||||
LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP2); \
|
||||
LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP2); \
|
||||
} while(0)
|
||||
|
||||
/**
|
||||
* @brief Disable the COMP2 EXTI line rising & falling edge trigger.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP2_EXTI_DISABLE_RISING_FALLING_EDGE() do { \
|
||||
LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP2); \
|
||||
LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP2); \
|
||||
} while(0)
|
||||
|
||||
/**
|
||||
* @brief Enable the COMP2 EXTI line in interrupt mode.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP2_EXTI_ENABLE_IT() LL_EXTI_EnableIT_0_31(COMP_EXTI_LINE_COMP2)
|
||||
|
||||
/**
|
||||
* @brief Disable the COMP2 EXTI line in interrupt mode.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP2_EXTI_DISABLE_IT() LL_EXTI_DisableIT_0_31(COMP_EXTI_LINE_COMP2)
|
||||
|
||||
/**
|
||||
* @brief Generate a software interrupt on the COMP2 EXTI line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP2_EXTI_GENERATE_SWIT() LL_EXTI_GenerateSWI_0_31(COMP_EXTI_LINE_COMP2)
|
||||
|
||||
/**
|
||||
* @brief Enable the COMP2 EXTI line in event mode.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP2_EXTI_ENABLE_EVENT() LL_EXTI_EnableEvent_0_31(COMP_EXTI_LINE_COMP2)
|
||||
|
||||
/**
|
||||
* @brief Disable the COMP2 EXTI line in event mode.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP2_EXTI_DISABLE_EVENT() LL_EXTI_DisableEvent_0_31(COMP_EXTI_LINE_COMP2)
|
||||
|
||||
/**
|
||||
* @brief Check whether the COMP2 EXTI line flag is set.
|
||||
* @retval RESET or SET
|
||||
*/
|
||||
#define __HAL_COMP_COMP2_EXTI_GET_FLAG() LL_EXTI_IsActiveFlag_0_31(COMP_EXTI_LINE_COMP2)
|
||||
|
||||
/**
|
||||
* @brief Clear the COMP2 EXTI flag.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() LL_EXTI_ClearFlag_0_31(COMP_EXTI_LINE_COMP2)
|
||||
|
||||
#endif /* COMP2 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup COMP_Private_Constants COMP Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_ExtiLine COMP EXTI Lines
|
||||
* @{
|
||||
*/
|
||||
#define COMP_EXTI_LINE_COMP1 (LL_EXTI_LINE_20) /*!< EXTI line 20 connected to COMP1 output */
|
||||
#if defined(COMP2)
|
||||
#define COMP_EXTI_LINE_COMP2 (LL_EXTI_LINE_21) /*!< EXTI line 21 connected to COMP2 output */
|
||||
#endif /* COMP2 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_ExtiLine COMP EXTI Lines
|
||||
* @{
|
||||
*/
|
||||
#define COMP_EXTI_IT (0x00000001UL) /*!< EXTI line event with interruption */
|
||||
#define COMP_EXTI_EVENT (0x00000002UL) /*!< EXTI line event only (without interruption) */
|
||||
#define COMP_EXTI_RISING (0x00000010UL) /*!< EXTI line event on rising edge */
|
||||
#define COMP_EXTI_FALLING (0x00000020UL) /*!< EXTI line event on falling edge */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup COMP_Private_Macros COMP Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_GET_EXTI_LINE COMP private macros to get EXTI line associated with comparators
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief Get the specified EXTI line for a comparator instance.
|
||||
* @param __INSTANCE__ specifies the COMP instance.
|
||||
* @retval value of @ref COMP_ExtiLine
|
||||
*/
|
||||
#if defined(COMP2)
|
||||
#define COMP_GET_EXTI_LINE(__INSTANCE__) (((__INSTANCE__) == COMP1) ? COMP_EXTI_LINE_COMP1 \
|
||||
: COMP_EXTI_LINE_COMP2)
|
||||
#else
|
||||
#define COMP_GET_EXTI_LINE(__INSTANCE__) COMP_EXTI_LINE_COMP1
|
||||
#endif /* COMP2 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_IS_COMP_Private_Definitions COMP private macros to check input parameters
|
||||
* @{
|
||||
*/
|
||||
#if defined(COMP2)
|
||||
#define IS_COMP_WINDOWMODE(__WINDOWMODE__) (((__WINDOWMODE__) == COMP_WINDOWMODE_DISABLE) || \
|
||||
((__WINDOWMODE__) == COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON) )
|
||||
#endif
|
||||
|
||||
#define IS_COMP_POWERMODE(__POWERMODE__) (((__POWERMODE__) == COMP_POWERMODE_HIGHSPEED) || \
|
||||
((__POWERMODE__) == COMP_POWERMODE_MEDIUMSPEED) || \
|
||||
((__POWERMODE__) == COMP_POWERMODE_ULTRALOWPOWER) )
|
||||
|
||||
#if defined(COMP_INPUT_PLUS_IO1)
|
||||
#define IS_COMP_INPUT_PLUS(__COMP_INSTANCE__, __INPUT_PLUS__) (((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO1) || \
|
||||
((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO2) || \
|
||||
((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO3))
|
||||
#else
|
||||
#define IS_COMP_INPUT_PLUS(__COMP_INSTANCE__, __INPUT_PLUS__) (((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO2) || \
|
||||
((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO3))
|
||||
#endif
|
||||
|
||||
/* Note: On this STM32 series, comparator input minus parameters are */
|
||||
/* the same on all COMP instances. */
|
||||
/* However, comparator instance kept as macro parameter for */
|
||||
/* compatibility with other STM32 families. */
|
||||
#if defined(COMP_INPUT_MINUS_IO2)
|
||||
#define IS_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__) (((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_4VREFINT) || \
|
||||
((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_2VREFINT) || \
|
||||
((__INPUT_MINUS__) == COMP_INPUT_MINUS_3_4VREFINT) || \
|
||||
((__INPUT_MINUS__) == COMP_INPUT_MINUS_VREFINT) || \
|
||||
((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO1) || \
|
||||
((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO2) || \
|
||||
((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO3) || \
|
||||
((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO4) || \
|
||||
((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO5))
|
||||
#else
|
||||
#define IS_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__) (((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_4VREFINT) || \
|
||||
((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_2VREFINT) || \
|
||||
((__INPUT_MINUS__) == COMP_INPUT_MINUS_3_4VREFINT) || \
|
||||
((__INPUT_MINUS__) == COMP_INPUT_MINUS_VREFINT) || \
|
||||
((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO1) || \
|
||||
((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO3) || \
|
||||
((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO4) || \
|
||||
((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO5))
|
||||
#endif
|
||||
|
||||
#define IS_COMP_HYSTERESIS(__HYSTERESIS__) (((__HYSTERESIS__) == COMP_HYSTERESIS_NONE) || \
|
||||
((__HYSTERESIS__) == COMP_HYSTERESIS_LOW) || \
|
||||
((__HYSTERESIS__) == COMP_HYSTERESIS_MEDIUM) || \
|
||||
((__HYSTERESIS__) == COMP_HYSTERESIS_HIGH))
|
||||
|
||||
#define IS_COMP_OUTPUTPOL(__POL__) (((__POL__) == COMP_OUTPUTPOL_NONINVERTED) || \
|
||||
((__POL__) == COMP_OUTPUTPOL_INVERTED))
|
||||
|
||||
#define IS_COMP_BLANKINGSRCE(__OUTPUT_BLANKING_SOURCE__) \
|
||||
( ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) \
|
||||
|| ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5) \
|
||||
|| ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3) \
|
||||
)
|
||||
|
||||
/* Note: Output blanking source common to all COMP instances */
|
||||
/* Macro kept for compatibility with other STM32 series */
|
||||
#define IS_COMP_BLANKINGSRC_INSTANCE(__INSTANCE__, __OUTPUT_BLANKING_SOURCE__) \
|
||||
(IS_COMP_BLANKINGSRCE(__OUTPUT_BLANKING_SOURCE__))
|
||||
|
||||
|
||||
#define IS_COMP_TRIGGERMODE(__MODE__) (((__MODE__) == COMP_TRIGGERMODE_NONE) || \
|
||||
((__MODE__) == COMP_TRIGGERMODE_IT_RISING) || \
|
||||
((__MODE__) == COMP_TRIGGERMODE_IT_FALLING) || \
|
||||
((__MODE__) == COMP_TRIGGERMODE_IT_RISING_FALLING) || \
|
||||
((__MODE__) == COMP_TRIGGERMODE_EVENT_RISING) || \
|
||||
((__MODE__) == COMP_TRIGGERMODE_EVENT_FALLING) || \
|
||||
((__MODE__) == COMP_TRIGGERMODE_EVENT_RISING_FALLING))
|
||||
|
||||
#define IS_COMP_OUTPUT_LEVEL(__OUTPUT_LEVEL__) (((__OUTPUT_LEVEL__) == COMP_OUTPUT_LEVEL_LOW) || \
|
||||
((__OUTPUT_LEVEL__) == COMP_OUTPUT_LEVEL_HIGH))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup COMP_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup COMP_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Initialization and de-initialization functions **********************************/
|
||||
HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp);
|
||||
HAL_StatusTypeDef HAL_COMP_DeInit(COMP_HandleTypeDef *hcomp);
|
||||
void HAL_COMP_MspInit(COMP_HandleTypeDef *hcomp);
|
||||
void HAL_COMP_MspDeInit(COMP_HandleTypeDef *hcomp);
|
||||
|
||||
#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
|
||||
/* Callbacks Register/UnRegister functions ***********************************/
|
||||
HAL_StatusTypeDef HAL_COMP_RegisterCallback(COMP_HandleTypeDef *hcomp, HAL_COMP_CallbackIDTypeDef CallbackID,
|
||||
pCOMP_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_COMP_UnRegisterCallback(COMP_HandleTypeDef *hcomp, HAL_COMP_CallbackIDTypeDef CallbackID);
|
||||
#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* IO operation functions *****************************************************/
|
||||
/** @addtogroup COMP_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp);
|
||||
HAL_StatusTypeDef HAL_COMP_Stop(COMP_HandleTypeDef *hcomp);
|
||||
void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Peripheral Control functions ************************************************/
|
||||
/** @addtogroup COMP_Exported_Functions_Group3
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp);
|
||||
uint32_t HAL_COMP_GetOutputLevel(COMP_HandleTypeDef *hcomp);
|
||||
/* Callback in interrupt mode */
|
||||
void HAL_COMP_TriggerCallback(COMP_HandleTypeDef *hcomp);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Peripheral State functions **************************************************/
|
||||
/** @addtogroup COMP_Exported_Functions_Group4
|
||||
* @{
|
||||
*/
|
||||
HAL_COMP_StateTypeDef HAL_COMP_GetState(COMP_HandleTypeDef *hcomp);
|
||||
uint32_t HAL_COMP_GetError(COMP_HandleTypeDef *hcomp);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* COMP1 || COMP2 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32WBxx_HAL_COMP_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -1,355 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32wbxx_hal_conf.h
|
||||
* @author MCD Application Team
|
||||
* @brief HAL configuration file.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32WBxx_HAL_CONF_H
|
||||
#define STM32WBxx_HAL_CONF_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/* ########################## Module Selection ############################## */
|
||||
/**
|
||||
* @brief This is the list of modules to be used in the HAL driver
|
||||
*/
|
||||
#define HAL_MODULE_ENABLED
|
||||
#define HAL_ADC_MODULE_ENABLED
|
||||
#define HAL_COMP_MODULE_ENABLED
|
||||
#define HAL_CORTEX_MODULE_ENABLED
|
||||
#define HAL_CRC_MODULE_ENABLED
|
||||
#define HAL_CRYP_MODULE_ENABLED
|
||||
#define HAL_DMA_MODULE_ENABLED
|
||||
#define HAL_EXTI_MODULE_ENABLED
|
||||
#define HAL_FLASH_MODULE_ENABLED
|
||||
#define HAL_GPIO_MODULE_ENABLED
|
||||
#define HAL_HSEM_MODULE_ENABLED
|
||||
#define HAL_I2C_MODULE_ENABLED
|
||||
#define HAL_IPCC_MODULE_ENABLED
|
||||
#define HAL_IRDA_MODULE_ENABLED
|
||||
#define HAL_IWDG_MODULE_ENABLED
|
||||
#define HAL_LCD_MODULE_ENABLED
|
||||
#define HAL_LPTIM_MODULE_ENABLED
|
||||
#define HAL_PCD_MODULE_ENABLED
|
||||
#define HAL_PKA_MODULE_ENABLED
|
||||
#define HAL_PWR_MODULE_ENABLED
|
||||
#define HAL_QSPI_MODULE_ENABLED
|
||||
#define HAL_RCC_MODULE_ENABLED
|
||||
#define HAL_RNG_MODULE_ENABLED
|
||||
#define HAL_RTC_MODULE_ENABLED
|
||||
#define HAL_SAI_MODULE_ENABLED
|
||||
#define HAL_SMARTCARD_MODULE_ENABLED
|
||||
#define HAL_SMBUS_MODULE_ENABLED
|
||||
#define HAL_SPI_MODULE_ENABLED
|
||||
#define HAL_TIM_MODULE_ENABLED
|
||||
#define HAL_TSC_MODULE_ENABLED
|
||||
#define HAL_UART_MODULE_ENABLED
|
||||
#define HAL_USART_MODULE_ENABLED
|
||||
#define HAL_WWDG_MODULE_ENABLED
|
||||
|
||||
#define USE_HAL_ADC_REGISTER_CALLBACKS 0u
|
||||
#define USE_HAL_COMP_REGISTER_CALLBACKS 0u
|
||||
#define USE_HAL_CRYP_REGISTER_CALLBACKS 0u
|
||||
#define USE_HAL_I2C_REGISTER_CALLBACKS 0u
|
||||
#define USE_HAL_IRDA_REGISTER_CALLBACKS 0u
|
||||
#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0u
|
||||
#define USE_HAL_PCD_REGISTER_CALLBACKS 0u
|
||||
#define USE_HAL_PKA_REGISTER_CALLBACKS 0u
|
||||
#define USE_HAL_QSPI_REGISTER_CALLBACKS 0u
|
||||
#define USE_HAL_RNG_REGISTER_CALLBACKS 0u
|
||||
#define USE_HAL_RTC_REGISTER_CALLBACKS 0u
|
||||
#define USE_HAL_SAI_REGISTER_CALLBACKS 0u
|
||||
#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0u
|
||||
#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0u
|
||||
#define USE_HAL_SPI_REGISTER_CALLBACKS 0u
|
||||
#define USE_HAL_TIM_REGISTER_CALLBACKS 0u
|
||||
#define USE_HAL_TSC_REGISTER_CALLBACKS 0u
|
||||
#define USE_HAL_UART_REGISTER_CALLBACKS 0u
|
||||
#define USE_HAL_USART_REGISTER_CALLBACKS 0u
|
||||
#define USE_HAL_WWDG_REGISTER_CALLBACKS 0u
|
||||
|
||||
#define USE_HAL_CRYP_SUSPEND_RESUME 0u
|
||||
|
||||
/* ########################## Oscillator Values adaptation ####################*/
|
||||
/**
|
||||
* @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
|
||||
* This value is used by the RCC HAL module to compute the system frequency
|
||||
* (when HSE is used as system clock source, directly or through the PLL).
|
||||
*/
|
||||
|
||||
#if !defined (HSE_VALUE)
|
||||
#define HSE_VALUE (32000000UL) /*!< Value of the External oscillator in Hz */
|
||||
#endif /* HSE_VALUE */
|
||||
|
||||
#if !defined (HSE_STARTUP_TIMEOUT)
|
||||
#define HSE_STARTUP_TIMEOUT (100UL) /*!< Time out for HSE start up, in ms */
|
||||
#endif /* HSE_STARTUP_TIMEOUT */
|
||||
|
||||
/**
|
||||
* @brief Internal Multiple Speed oscillator (MSI) default value.
|
||||
* This value is the default MSI range value after Reset.
|
||||
*/
|
||||
#if !defined (MSI_VALUE)
|
||||
#define MSI_VALUE (4000000UL) /*!< Value of the Internal oscillator in Hz*/
|
||||
#endif /* MSI_VALUE */
|
||||
|
||||
/**
|
||||
* @brief Internal High Speed oscillator (HSI) value.
|
||||
* This value is used by the RCC HAL module to compute the system frequency
|
||||
* (when HSI is used as system clock source, directly or through the PLL).
|
||||
*/
|
||||
#if !defined (HSI_VALUE)
|
||||
#define HSI_VALUE (16000000UL) /*!< Value of the Internal oscillator in Hz*/
|
||||
#endif /* HSI_VALUE */
|
||||
|
||||
/**
|
||||
* @brief Internal Low Speed oscillator (LSI1) value.
|
||||
*/
|
||||
#if !defined (LSI1_VALUE)
|
||||
#define LSI1_VALUE (32000UL) /*!< LSI1 Typical Value in Hz*/
|
||||
#endif /* LSI1_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
|
||||
The real value may vary depending on the variations
|
||||
in voltage and temperature.*/
|
||||
/**
|
||||
* @brief Internal Low Speed oscillator (LSI2) value.
|
||||
*/
|
||||
#if !defined (LSI2_VALUE)
|
||||
#define LSI2_VALUE (32000UL) /*!< LSI2 Typical Value in Hz*/
|
||||
#endif /* LSI2_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
|
||||
The real value may vary depending on the variations
|
||||
in voltage and temperature.*/
|
||||
|
||||
/**
|
||||
* @brief External Low Speed oscillator (LSE) value.
|
||||
* This value is used by the UART, RTC HAL module to compute the system frequency
|
||||
*/
|
||||
#if !defined (LSE_VALUE)
|
||||
#define LSE_VALUE (32768UL) /*!< Value of the External oscillator in Hz*/
|
||||
#endif /* LSE_VALUE */
|
||||
|
||||
/**
|
||||
* @brief Internal Multiple Speed oscillator (HSI48) default value.
|
||||
* This value is the default HSI48 range value after Reset.
|
||||
*/
|
||||
#if !defined (HSI48_VALUE)
|
||||
#define HSI48_VALUE (48000000UL) /*!< Value of the Internal oscillator in Hz*/
|
||||
#endif /* HSI48_VALUE */
|
||||
|
||||
#if !defined (LSE_STARTUP_TIMEOUT)
|
||||
#define LSE_STARTUP_TIMEOUT (5000UL) /*!< Time out for LSE start up, in ms */
|
||||
#endif /* LSE_STARTUP_TIMEOUT */
|
||||
|
||||
/**
|
||||
* @brief External clock source for SAI1 peripheral
|
||||
* This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source
|
||||
* frequency.
|
||||
*/
|
||||
#if !defined (EXTERNAL_SAI1_CLOCK_VALUE)
|
||||
#define EXTERNAL_SAI1_CLOCK_VALUE (48000UL) /*!< Value of the SAI1 External clock source in Hz*/
|
||||
#endif /* EXTERNAL_SAI1_CLOCK_VALUE */
|
||||
|
||||
/* Tip: To avoid modifying this file each time you need to use different HSE,
|
||||
=== you can define the HSE value in your toolchain compiler preprocessor. */
|
||||
|
||||
/* ########################### System Configuration ######################### */
|
||||
/**
|
||||
* @brief This is the HAL system configuration section
|
||||
*/
|
||||
#define VDD_VALUE (3300UL) /*!< Value of VDD in mv */
|
||||
#define TICK_INT_PRIORITY ((1UL<<__NVIC_PRIO_BITS) - 1UL) /*!< tick interrupt priority (lowest by default) */
|
||||
#define USE_RTOS 0U
|
||||
#define PREFETCH_ENABLE 0U
|
||||
#define INSTRUCTION_CACHE_ENABLE 1U
|
||||
#define DATA_CACHE_ENABLE 1U
|
||||
|
||||
/* ########################## Assert Selection ############################## */
|
||||
/**
|
||||
* @brief Uncomment the line below to expanse the "assert_param" macro in the
|
||||
* HAL drivers code
|
||||
*/
|
||||
/* #define USE_FULL_ASSERT 1U */
|
||||
|
||||
/* ################## SPI peripheral configuration ########################## */
|
||||
|
||||
/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
|
||||
* Activated: CRC code is present inside driver
|
||||
* Deactivated: CRC code cleaned from driver
|
||||
*/
|
||||
|
||||
#define USE_SPI_CRC 1U
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
/**
|
||||
* @brief Include module's header file
|
||||
*/
|
||||
#ifdef HAL_DMA_MODULE_ENABLED
|
||||
#include "stm32wbxx_hal_dma.h"
|
||||
#endif /* HAL_DMA_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_ADC_MODULE_ENABLED
|
||||
#include "stm32wbxx_hal_adc.h"
|
||||
#endif /* HAL_ADC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_COMP_MODULE_ENABLED
|
||||
#include "stm32wbxx_hal_comp.h"
|
||||
#endif /* HAL_COMP_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_CORTEX_MODULE_ENABLED
|
||||
#include "stm32wbxx_hal_cortex.h"
|
||||
#endif /* HAL_CORTEX_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_CRC_MODULE_ENABLED
|
||||
#include "stm32wbxx_hal_crc.h"
|
||||
#endif /* HAL_CRC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_CRYP_MODULE_ENABLED
|
||||
#include "stm32wbxx_hal_cryp.h"
|
||||
#endif /* HAL_CRYP_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_EXTI_MODULE_ENABLED
|
||||
#include "stm32wbxx_hal_exti.h"
|
||||
#endif /* HAL_EXTI_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_FLASH_MODULE_ENABLED
|
||||
#include "stm32wbxx_hal_flash.h"
|
||||
#endif /* HAL_FLASH_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_GPIO_MODULE_ENABLED
|
||||
#include "stm32wbxx_hal_gpio.h"
|
||||
#endif /* HAL_GPIO_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_HSEM_MODULE_ENABLED
|
||||
#include "stm32wbxx_hal_hsem.h"
|
||||
#endif /* HAL_HSEM_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_I2C_MODULE_ENABLED
|
||||
#include "stm32wbxx_hal_i2c.h"
|
||||
#endif /* HAL_I2C_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_IPCC_MODULE_ENABLED
|
||||
#include "stm32wbxx_hal_ipcc.h"
|
||||
#endif /* HAL_IPCC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_IRDA_MODULE_ENABLED
|
||||
#include "stm32wbxx_hal_irda.h"
|
||||
#endif /* HAL_IRDA_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_IWDG_MODULE_ENABLED
|
||||
#include "stm32wbxx_hal_iwdg.h"
|
||||
#endif /* HAL_IWDG_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_LCD_MODULE_ENABLED
|
||||
#include "stm32wbxx_hal_lcd.h"
|
||||
#endif /* HAL_LCD_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_LPTIM_MODULE_ENABLED
|
||||
#include "stm32wbxx_hal_lptim.h"
|
||||
#endif /* HAL_LPTIM_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_PCD_MODULE_ENABLED
|
||||
#include "stm32wbxx_hal_pcd.h"
|
||||
#endif /* HAL_PCD_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_PKA_MODULE_ENABLED
|
||||
#include "stm32wbxx_hal_pka.h"
|
||||
#endif /* HAL_PKA_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_PWR_MODULE_ENABLED
|
||||
#include "stm32wbxx_hal_pwr.h"
|
||||
#endif /* HAL_PWR_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_QSPI_MODULE_ENABLED
|
||||
#include "stm32wbxx_hal_qspi.h"
|
||||
#endif /* HAL_QSPI_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_RCC_MODULE_ENABLED
|
||||
#include "stm32wbxx_hal_rcc.h"
|
||||
#endif /* HAL_RCC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_RNG_MODULE_ENABLED
|
||||
#include "stm32wbxx_hal_rng.h"
|
||||
#endif /* HAL_RNG_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_RTC_MODULE_ENABLED
|
||||
#include "stm32wbxx_hal_rtc.h"
|
||||
#endif /* HAL_RTC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SAI_MODULE_ENABLED
|
||||
#include "stm32wbxx_hal_sai.h"
|
||||
#endif /* HAL_SAI_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SMARTCARD_MODULE_ENABLED
|
||||
#include "stm32wbxx_hal_smartcard.h"
|
||||
#endif /* HAL_SMARTCARD_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SMBUS_MODULE_ENABLED
|
||||
#include "stm32wbxx_hal_smbus.h"
|
||||
#endif /* HAL_SMBUS_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SPI_MODULE_ENABLED
|
||||
#include "stm32wbxx_hal_spi.h"
|
||||
#endif /* HAL_SPI_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_TIM_MODULE_ENABLED
|
||||
#include "stm32wbxx_hal_tim.h"
|
||||
#endif /* HAL_TIM_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_TSC_MODULE_ENABLED
|
||||
#include "stm32wbxx_hal_tsc.h"
|
||||
#endif /* HAL_TSC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_UART_MODULE_ENABLED
|
||||
#include "stm32wbxx_hal_uart.h"
|
||||
#endif /* HAL_UART_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_USART_MODULE_ENABLED
|
||||
#include "stm32wbxx_hal_usart.h"
|
||||
#endif /* HAL_USART_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_WWDG_MODULE_ENABLED
|
||||
#include "stm32wbxx_hal_wwdg.h"
|
||||
#endif /* HAL_WWDG_MODULE_ENABLED */
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
#ifdef USE_FULL_ASSERT
|
||||
/**
|
||||
* @brief The assert_param macro is used for function's parameters check.
|
||||
* @param expr If expr is false, it calls assert_failed function
|
||||
* which reports the name of the source file and the source
|
||||
* line number of the call that failed.
|
||||
* If expr is true, it returns no value.
|
||||
* @retval None
|
||||
*/
|
||||
#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
void assert_failed(uint8_t* file, uint32_t line);
|
||||
#else
|
||||
#define assert_param(expr) ((void)0U)
|
||||
#endif /* USE_FULL_ASSERT */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32WBxx_HAL_CONF_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -1,419 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32wbxx_hal_cortex.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of CORTEX HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32WBxx_HAL_CORTEX_H
|
||||
#define STM32WBxx_HAL_CORTEX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32wbxx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32WBxx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX CORTEX
|
||||
* @brief CORTEX HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup CORTEX_Exported_Types CORTEX Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if (__MPU_PRESENT == 1)
|
||||
/** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition
|
||||
* @brief MPU Region initialization structure
|
||||
* @{
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint8_t Enable; /*!< Specifies the status of the region.
|
||||
This parameter can be a value of @ref CORTEX_MPU_Region_Enable */
|
||||
uint8_t Number; /*!< Specifies the number of the region to protect.
|
||||
This parameter can be a value of @ref CORTEX_MPU_Region_Number */
|
||||
uint32_t BaseAddress; /*!< Specifies the base address of the region to protect.
|
||||
*/
|
||||
uint8_t Size; /*!< Specifies the size of the region to protect.
|
||||
This parameter can be a value of @ref CORTEX_MPU_Region_Size */
|
||||
uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable.
|
||||
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */
|
||||
uint8_t TypeExtField; /*!< Specifies the TEX field level.
|
||||
This parameter can be a value of @ref CORTEX_MPU_TEX_Levels */
|
||||
uint8_t AccessPermission; /*!< Specifies the region access permission type.
|
||||
This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */
|
||||
uint8_t DisableExec; /*!< Specifies the instruction access status.
|
||||
This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */
|
||||
uint8_t IsShareable; /*!< Specifies the shareability status of the protected region.
|
||||
This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */
|
||||
uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected.
|
||||
This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */
|
||||
uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region.
|
||||
This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */
|
||||
} MPU_Region_InitTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* __MPU_PRESENT */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants
|
||||
* @{
|
||||
*/
|
||||
/** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group
|
||||
* @{
|
||||
*/
|
||||
#define NVIC_PRIORITYGROUP_0 (0x00000007U) /*!< 0 bit for pre-emption priority,
|
||||
4 bits for subpriority */
|
||||
#define NVIC_PRIORITYGROUP_1 (0x00000006U) /*!< 1 bit for pre-emption priority,
|
||||
3 bits for subpriority */
|
||||
#define NVIC_PRIORITYGROUP_2 (0x00000005U) /*!< 2 bits for pre-emption priority,
|
||||
2 bits for subpriority */
|
||||
#define NVIC_PRIORITYGROUP_3 (0x00000004U) /*!< 3 bits for pre-emption priority,
|
||||
1 bit for subpriority */
|
||||
#define NVIC_PRIORITYGROUP_4 (0x00000003U) /*!< 4 bits for pre-emption priority,
|
||||
0 bit for subpriority */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_SysTick_clock_source CORTEX SysTick clock source
|
||||
* @{
|
||||
*/
|
||||
#define SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U
|
||||
#define SYSTICK_CLKSOURCE_HCLK 0x00000004U
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if (__MPU_PRESENT == 1)
|
||||
/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control CORTEX MPU HFNMI and PRIVILEGED Access control
|
||||
* @{
|
||||
*/
|
||||
#define MPU_HFNMI_PRIVDEF_NONE 0x00000000U
|
||||
#define MPU_HARDFAULT_NMI (MPU_CTRL_HFNMIENA_Msk)
|
||||
#define MPU_PRIVILEGED_DEFAULT (MPU_CTRL_PRIVDEFENA_Msk)
|
||||
#define MPU_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable
|
||||
* @{
|
||||
*/
|
||||
#define MPU_REGION_ENABLE ((uint8_t)0x01)
|
||||
#define MPU_REGION_DISABLE ((uint8_t)0x00)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access
|
||||
* @{
|
||||
*/
|
||||
#define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00)
|
||||
#define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable
|
||||
* @{
|
||||
*/
|
||||
#define MPU_ACCESS_SHAREABLE ((uint8_t)0x01)
|
||||
#define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable
|
||||
* @{
|
||||
*/
|
||||
#define MPU_ACCESS_CACHEABLE ((uint8_t)0x01)
|
||||
#define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable
|
||||
* @{
|
||||
*/
|
||||
#define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01)
|
||||
#define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_MPU_TEX_Levels CORTEX MPU TEX Levels
|
||||
* @{
|
||||
*/
|
||||
#define MPU_TEX_LEVEL0 ((uint8_t)0x00)
|
||||
#define MPU_TEX_LEVEL1 ((uint8_t)0x01)
|
||||
#define MPU_TEX_LEVEL2 ((uint8_t)0x02)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size
|
||||
* @{
|
||||
*/
|
||||
#define MPU_REGION_SIZE_32B ((uint8_t)0x04)
|
||||
#define MPU_REGION_SIZE_64B ((uint8_t)0x05)
|
||||
#define MPU_REGION_SIZE_128B ((uint8_t)0x06)
|
||||
#define MPU_REGION_SIZE_256B ((uint8_t)0x07)
|
||||
#define MPU_REGION_SIZE_512B ((uint8_t)0x08)
|
||||
#define MPU_REGION_SIZE_1KB ((uint8_t)0x09)
|
||||
#define MPU_REGION_SIZE_2KB ((uint8_t)0x0A)
|
||||
#define MPU_REGION_SIZE_4KB ((uint8_t)0x0B)
|
||||
#define MPU_REGION_SIZE_8KB ((uint8_t)0x0C)
|
||||
#define MPU_REGION_SIZE_16KB ((uint8_t)0x0D)
|
||||
#define MPU_REGION_SIZE_32KB ((uint8_t)0x0E)
|
||||
#define MPU_REGION_SIZE_64KB ((uint8_t)0x0F)
|
||||
#define MPU_REGION_SIZE_128KB ((uint8_t)0x10)
|
||||
#define MPU_REGION_SIZE_256KB ((uint8_t)0x11)
|
||||
#define MPU_REGION_SIZE_512KB ((uint8_t)0x12)
|
||||
#define MPU_REGION_SIZE_1MB ((uint8_t)0x13)
|
||||
#define MPU_REGION_SIZE_2MB ((uint8_t)0x14)
|
||||
#define MPU_REGION_SIZE_4MB ((uint8_t)0x15)
|
||||
#define MPU_REGION_SIZE_8MB ((uint8_t)0x16)
|
||||
#define MPU_REGION_SIZE_16MB ((uint8_t)0x17)
|
||||
#define MPU_REGION_SIZE_32MB ((uint8_t)0x18)
|
||||
#define MPU_REGION_SIZE_64MB ((uint8_t)0x19)
|
||||
#define MPU_REGION_SIZE_128MB ((uint8_t)0x1A)
|
||||
#define MPU_REGION_SIZE_256MB ((uint8_t)0x1B)
|
||||
#define MPU_REGION_SIZE_512MB ((uint8_t)0x1C)
|
||||
#define MPU_REGION_SIZE_1GB ((uint8_t)0x1D)
|
||||
#define MPU_REGION_SIZE_2GB ((uint8_t)0x1E)
|
||||
#define MPU_REGION_SIZE_4GB ((uint8_t)0x1F)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes
|
||||
* @{
|
||||
*/
|
||||
#define MPU_REGION_NO_ACCESS ((uint8_t)0x00)
|
||||
#define MPU_REGION_PRIV_RW ((uint8_t)0x01)
|
||||
#define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02)
|
||||
#define MPU_REGION_FULL_ACCESS ((uint8_t)0x03)
|
||||
#define MPU_REGION_PRIV_RO ((uint8_t)0x05)
|
||||
#define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number
|
||||
* @{
|
||||
*/
|
||||
#define MPU_REGION_NUMBER0 ((uint8_t)0x00)
|
||||
#define MPU_REGION_NUMBER1 ((uint8_t)0x01)
|
||||
#define MPU_REGION_NUMBER2 ((uint8_t)0x02)
|
||||
#define MPU_REGION_NUMBER3 ((uint8_t)0x03)
|
||||
#define MPU_REGION_NUMBER4 ((uint8_t)0x04)
|
||||
#define MPU_REGION_NUMBER5 ((uint8_t)0x05)
|
||||
#define MPU_REGION_NUMBER6 ((uint8_t)0x06)
|
||||
#define MPU_REGION_NUMBER7 ((uint8_t)0x07)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* __MPU_PRESENT */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/** @defgroup CORTEX_Exported_Macros CORTEX Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_Exported_Functions_Group1 Initialization and Configuration functions
|
||||
* @brief Initialization and Configuration functions
|
||||
* @{
|
||||
*/
|
||||
/* Initialization and Configuration functions *****************************/
|
||||
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup);
|
||||
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority);
|
||||
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn);
|
||||
void HAL_NVIC_DisableIRQ(IRQn_Type IRQn);
|
||||
void HAL_NVIC_SystemReset(void);
|
||||
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions
|
||||
* @brief Cortex control functions
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral Control functions *************************************************/
|
||||
void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority);
|
||||
uint32_t HAL_NVIC_GetPriorityGrouping(void);
|
||||
uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);
|
||||
void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn);
|
||||
void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn);
|
||||
void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);
|
||||
void HAL_SYSTICK_IRQHandler(void);
|
||||
void HAL_SYSTICK_Callback(void);
|
||||
|
||||
#if (__MPU_PRESENT == 1U)
|
||||
void HAL_MPU_Enable(uint32_t MPU_Control);
|
||||
void HAL_MPU_Disable(void);
|
||||
void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
|
||||
#endif /* __MPU_PRESENT */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup CORTEX_Private_Macros CORTEX Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \
|
||||
((GROUP) == NVIC_PRIORITYGROUP_1) || \
|
||||
((GROUP) == NVIC_PRIORITYGROUP_2) || \
|
||||
((GROUP) == NVIC_PRIORITYGROUP_3) || \
|
||||
((GROUP) == NVIC_PRIORITYGROUP_4))
|
||||
|
||||
#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U)
|
||||
|
||||
#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U)
|
||||
|
||||
#define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) > SysTick_IRQn)
|
||||
|
||||
#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \
|
||||
((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))
|
||||
|
||||
#if (__MPU_PRESENT == 1)
|
||||
#define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \
|
||||
((STATE) == MPU_REGION_DISABLE))
|
||||
|
||||
#define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \
|
||||
((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))
|
||||
|
||||
#define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \
|
||||
((STATE) == MPU_ACCESS_NOT_SHAREABLE))
|
||||
|
||||
#define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \
|
||||
((STATE) == MPU_ACCESS_NOT_CACHEABLE))
|
||||
|
||||
#define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \
|
||||
((STATE) == MPU_ACCESS_NOT_BUFFERABLE))
|
||||
|
||||
#define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || \
|
||||
((TYPE) == MPU_TEX_LEVEL1) || \
|
||||
((TYPE) == MPU_TEX_LEVEL2))
|
||||
|
||||
#define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \
|
||||
((TYPE) == MPU_REGION_PRIV_RW) || \
|
||||
((TYPE) == MPU_REGION_PRIV_RW_URO) || \
|
||||
((TYPE) == MPU_REGION_FULL_ACCESS) || \
|
||||
((TYPE) == MPU_REGION_PRIV_RO) || \
|
||||
((TYPE) == MPU_REGION_PRIV_RO_URO))
|
||||
|
||||
#define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \
|
||||
((NUMBER) == MPU_REGION_NUMBER1) || \
|
||||
((NUMBER) == MPU_REGION_NUMBER2) || \
|
||||
((NUMBER) == MPU_REGION_NUMBER3) || \
|
||||
((NUMBER) == MPU_REGION_NUMBER4) || \
|
||||
((NUMBER) == MPU_REGION_NUMBER5) || \
|
||||
((NUMBER) == MPU_REGION_NUMBER6) || \
|
||||
((NUMBER) == MPU_REGION_NUMBER7))
|
||||
|
||||
#define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_32B) || \
|
||||
((SIZE) == MPU_REGION_SIZE_64B) || \
|
||||
((SIZE) == MPU_REGION_SIZE_128B) || \
|
||||
((SIZE) == MPU_REGION_SIZE_256B) || \
|
||||
((SIZE) == MPU_REGION_SIZE_512B) || \
|
||||
((SIZE) == MPU_REGION_SIZE_1KB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_2KB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_4KB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_8KB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_16KB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_32KB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_64KB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_128KB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_256KB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_512KB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_1MB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_2MB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_4MB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_8MB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_16MB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_32MB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_64MB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_128MB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_256MB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_512MB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_1GB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_2GB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_4GB))
|
||||
|
||||
#define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FFU)
|
||||
#endif /* __MPU_PRESENT */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32WBxx_HAL_CORTEX_H */
|
||||
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
||||
|
|
@ -1,344 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32wbxx_hal_crc.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of CRC HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32WBxx_HAL_CRC_H
|
||||
#define STM32WBxx_HAL_CRC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32wbxx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32WBxx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup CRC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup CRC_Exported_Types CRC Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief CRC HAL State Structure definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_CRC_STATE_RESET = 0x00U, /*!< CRC not yet initialized or disabled */
|
||||
HAL_CRC_STATE_READY = 0x01U, /*!< CRC initialized and ready for use */
|
||||
HAL_CRC_STATE_BUSY = 0x02U, /*!< CRC internal process is ongoing */
|
||||
HAL_CRC_STATE_TIMEOUT = 0x03U, /*!< CRC timeout state */
|
||||
HAL_CRC_STATE_ERROR = 0x04U /*!< CRC error state */
|
||||
} HAL_CRC_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief CRC Init Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint8_t DefaultPolynomialUse; /*!< This parameter is a value of @ref CRC_Default_Polynomial and indicates if default polynomial is used.
|
||||
If set to DEFAULT_POLYNOMIAL_ENABLE, resort to default
|
||||
X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2+ X +1.
|
||||
In that case, there is no need to set GeneratingPolynomial field.
|
||||
If otherwise set to DEFAULT_POLYNOMIAL_DISABLE, GeneratingPolynomial and CRCLength fields must be set. */
|
||||
|
||||
uint8_t DefaultInitValueUse; /*!< This parameter is a value of @ref CRC_Default_InitValue_Use and indicates if default init value is used.
|
||||
If set to DEFAULT_INIT_VALUE_ENABLE, resort to default
|
||||
0xFFFFFFFF value. In that case, there is no need to set InitValue field.
|
||||
If otherwise set to DEFAULT_INIT_VALUE_DISABLE, InitValue field must be set. */
|
||||
|
||||
uint32_t GeneratingPolynomial; /*!< Set CRC generating polynomial as a 7, 8, 16 or 32-bit long value for a polynomial degree
|
||||
respectively equal to 7, 8, 16 or 32. This field is written in normal representation,
|
||||
e.g., for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65.
|
||||
No need to specify it if DefaultPolynomialUse is set to DEFAULT_POLYNOMIAL_ENABLE. */
|
||||
|
||||
uint32_t CRCLength; /*!< This parameter is a value of @ref CRC_Polynomial_Sizes and indicates CRC length.
|
||||
Value can be either one of
|
||||
@arg @ref CRC_POLYLENGTH_32B (32-bit CRC),
|
||||
@arg @ref CRC_POLYLENGTH_16B (16-bit CRC),
|
||||
@arg @ref CRC_POLYLENGTH_8B (8-bit CRC),
|
||||
@arg @ref CRC_POLYLENGTH_7B (7-bit CRC). */
|
||||
|
||||
uint32_t InitValue; /*!< Init value to initiate CRC computation. No need to specify it if DefaultInitValueUse
|
||||
is set to DEFAULT_INIT_VALUE_ENABLE. */
|
||||
|
||||
uint32_t InputDataInversionMode; /*!< This parameter is a value of @ref CRCEx_Input_Data_Inversion and specifies input data inversion mode.
|
||||
Can be either one of the following values
|
||||
@arg @ref CRC_INPUTDATA_INVERSION_NONE no input data inversion
|
||||
@arg @ref CRC_INPUTDATA_INVERSION_BYTE byte-wise inversion, 0x1A2B3C4D becomes 0x58D43CB2
|
||||
@arg @ref CRC_INPUTDATA_INVERSION_HALFWORD halfword-wise inversion, 0x1A2B3C4D becomes 0xD458B23C
|
||||
@arg @ref CRC_INPUTDATA_INVERSION_WORD word-wise inversion, 0x1A2B3C4D becomes 0xB23CD458 */
|
||||
|
||||
uint32_t OutputDataInversionMode; /*!< This parameter is a value of @ref CRCEx_Output_Data_Inversion and specifies output data (i.e. CRC) inversion mode.
|
||||
Can be either
|
||||
@arg @ref CRC_OUTPUTDATA_INVERSION_DISABLE no CRC inversion,
|
||||
@arg @ref CRC_OUTPUTDATA_INVERSION_ENABLE CRC 0x11223344 is converted into 0x22CC4488 */
|
||||
} CRC_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief CRC Handle Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
CRC_TypeDef *Instance; /*!< Register base address */
|
||||
|
||||
CRC_InitTypeDef Init; /*!< CRC configuration parameters */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< CRC Locking object */
|
||||
|
||||
__IO HAL_CRC_StateTypeDef State; /*!< CRC communication state */
|
||||
|
||||
uint32_t InputDataFormat; /*!< This parameter is a value of @ref CRC_Input_Buffer_Format and specifies input data format.
|
||||
Can be either
|
||||
@arg @ref CRC_INPUTDATA_FORMAT_BYTES input data is a stream of bytes (8-bit data)
|
||||
@arg @ref CRC_INPUTDATA_FORMAT_HALFWORDS input data is a stream of half-words (16-bit data)
|
||||
@arg @ref CRC_INPUTDATA_FORMAT_WORDS input data is a stream of words (32-bit data)
|
||||
|
||||
Note that constant CRC_INPUT_FORMAT_UNDEFINED is defined but an initialization error
|
||||
must occur if InputBufferFormat is not one of the three values listed above */
|
||||
} CRC_HandleTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup CRC_Exported_Constants CRC Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_Default_Polynomial_Value Default CRC generating polynomial
|
||||
* @{
|
||||
*/
|
||||
#define DEFAULT_CRC32_POLY 0x04C11DB7U /*!< X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2+ X +1 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_Default_InitValue Default CRC computation initialization value
|
||||
* @{
|
||||
*/
|
||||
#define DEFAULT_CRC_INITVALUE 0xFFFFFFFFU /*!< Initial CRC default value */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_Default_Polynomial Indicates whether or not default polynomial is used
|
||||
* @{
|
||||
*/
|
||||
#define DEFAULT_POLYNOMIAL_ENABLE ((uint8_t)0x00U) /*!< Enable default generating polynomial 0x04C11DB7 */
|
||||
#define DEFAULT_POLYNOMIAL_DISABLE ((uint8_t)0x01U) /*!< Disable default generating polynomial 0x04C11DB7 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_Default_InitValue_Use Indicates whether or not default init value is used
|
||||
* @{
|
||||
*/
|
||||
#define DEFAULT_INIT_VALUE_ENABLE ((uint8_t)0x00U) /*!< Enable initial CRC default value */
|
||||
#define DEFAULT_INIT_VALUE_DISABLE ((uint8_t)0x01U) /*!< Disable initial CRC default value */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_Polynomial_Sizes Polynomial sizes to configure the peripheral
|
||||
* @{
|
||||
*/
|
||||
#define CRC_POLYLENGTH_32B 0x00000000U /*!< Resort to a 32-bit long generating polynomial */
|
||||
#define CRC_POLYLENGTH_16B CRC_CR_POLYSIZE_0 /*!< Resort to a 16-bit long generating polynomial */
|
||||
#define CRC_POLYLENGTH_8B CRC_CR_POLYSIZE_1 /*!< Resort to a 8-bit long generating polynomial */
|
||||
#define CRC_POLYLENGTH_7B CRC_CR_POLYSIZE /*!< Resort to a 7-bit long generating polynomial */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_Polynomial_Size_Definitions CRC polynomial possible sizes actual definitions
|
||||
* @{
|
||||
*/
|
||||
#define HAL_CRC_LENGTH_32B 32U /*!< 32-bit long CRC */
|
||||
#define HAL_CRC_LENGTH_16B 16U /*!< 16-bit long CRC */
|
||||
#define HAL_CRC_LENGTH_8B 8U /*!< 8-bit long CRC */
|
||||
#define HAL_CRC_LENGTH_7B 7U /*!< 7-bit long CRC */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_Input_Buffer_Format Input Buffer Format
|
||||
* @{
|
||||
*/
|
||||
/* WARNING: CRC_INPUT_FORMAT_UNDEFINED is created for reference purposes but
|
||||
* an error is triggered in HAL_CRC_Init() if InputDataFormat field is set
|
||||
* to CRC_INPUT_FORMAT_UNDEFINED: the format MUST be defined by the user for
|
||||
* the CRC APIs to provide a correct result */
|
||||
#define CRC_INPUTDATA_FORMAT_UNDEFINED 0x00000000U /*!< Undefined input data format */
|
||||
#define CRC_INPUTDATA_FORMAT_BYTES 0x00000001U /*!< Input data in byte format */
|
||||
#define CRC_INPUTDATA_FORMAT_HALFWORDS 0x00000002U /*!< Input data in half-word format */
|
||||
#define CRC_INPUTDATA_FORMAT_WORDS 0x00000003U /*!< Input data in word format */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_Aliases CRC API aliases
|
||||
* @{
|
||||
*/
|
||||
#define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for inter STM32 series compatibility */
|
||||
#define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for inter STM32 series compatibility */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/** @defgroup CRC_Exported_Macros CRC Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset CRC handle state.
|
||||
* @param __HANDLE__ CRC handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_CRC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRC_STATE_RESET)
|
||||
|
||||
/**
|
||||
* @brief Reset CRC Data Register.
|
||||
* @param __HANDLE__ CRC handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_CRC_DR_RESET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_RESET)
|
||||
|
||||
/**
|
||||
* @brief Set CRC INIT non-default value
|
||||
* @param __HANDLE__ CRC handle
|
||||
* @param __INIT__ 32-bit initial value
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_CRC_INITIALCRCVALUE_CONFIG(__HANDLE__, __INIT__) ((__HANDLE__)->Instance->INIT = (__INIT__))
|
||||
|
||||
/**
|
||||
* @brief Store data in the Independent Data (ID) register.
|
||||
* @param __HANDLE__ CRC handle
|
||||
* @param __VALUE__ Value to be stored in the ID register
|
||||
* @note Refer to the Reference Manual to get the authorized __VALUE__ length in bits
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_CRC_SET_IDR(__HANDLE__, __VALUE__) (WRITE_REG((__HANDLE__)->Instance->IDR, (__VALUE__)))
|
||||
|
||||
/**
|
||||
* @brief Return the data stored in the Independent Data (ID) register.
|
||||
* @param __HANDLE__ CRC handle
|
||||
* @note Refer to the Reference Manual to get the authorized __VALUE__ length in bits
|
||||
* @retval Value of the ID register
|
||||
*/
|
||||
#define __HAL_CRC_GET_IDR(__HANDLE__) (((__HANDLE__)->Instance->IDR) & CRC_IDR_IDR)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Private macros --------------------------------------------------------*/
|
||||
/** @defgroup CRC_Private_Macros CRC Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_DEFAULT_POLYNOMIAL(DEFAULT) (((DEFAULT) == DEFAULT_POLYNOMIAL_ENABLE) || \
|
||||
((DEFAULT) == DEFAULT_POLYNOMIAL_DISABLE))
|
||||
|
||||
|
||||
#define IS_DEFAULT_INIT_VALUE(VALUE) (((VALUE) == DEFAULT_INIT_VALUE_ENABLE) || \
|
||||
((VALUE) == DEFAULT_INIT_VALUE_DISABLE))
|
||||
|
||||
#define IS_CRC_POL_LENGTH(LENGTH) (((LENGTH) == CRC_POLYLENGTH_32B) || \
|
||||
((LENGTH) == CRC_POLYLENGTH_16B) || \
|
||||
((LENGTH) == CRC_POLYLENGTH_8B) || \
|
||||
((LENGTH) == CRC_POLYLENGTH_7B))
|
||||
|
||||
#define IS_CRC_INPUTDATA_FORMAT(FORMAT) (((FORMAT) == CRC_INPUTDATA_FORMAT_BYTES) || \
|
||||
((FORMAT) == CRC_INPUTDATA_FORMAT_HALFWORDS) || \
|
||||
((FORMAT) == CRC_INPUTDATA_FORMAT_WORDS))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Include CRC HAL Extended module */
|
||||
#include "stm32wbxx_hal_crc_ex.h"
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup CRC_Exported_Functions CRC Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Initialization and de-initialization functions ****************************/
|
||||
/** @defgroup CRC_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc);
|
||||
HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc);
|
||||
void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc);
|
||||
void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Peripheral Control functions ***********************************************/
|
||||
/** @defgroup CRC_Exported_Functions_Group2 Peripheral Control functions
|
||||
* @{
|
||||
*/
|
||||
uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength);
|
||||
uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Peripheral State and Error functions ***************************************/
|
||||
/** @defgroup CRC_Exported_Functions_Group3 Peripheral State functions
|
||||
* @{
|
||||
*/
|
||||
HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32WBxx_HAL_CRC_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -1,153 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32wbxx_hal_crc_ex.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of CRC HAL extended module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32WBxx_HAL_CRC_EX_H
|
||||
#define STM32WBxx_HAL_CRC_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32wbxx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32WBxx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup CRCEx
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup CRCEx_Exported_Constants CRC Extended Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CRCEx_Input_Data_Inversion Input Data Inversion Modes
|
||||
* @{
|
||||
*/
|
||||
#define CRC_INPUTDATA_INVERSION_NONE 0x00000000U /*!< No input data inversion */
|
||||
#define CRC_INPUTDATA_INVERSION_BYTE CRC_CR_REV_IN_0 /*!< Byte-wise input data inversion */
|
||||
#define CRC_INPUTDATA_INVERSION_HALFWORD CRC_CR_REV_IN_1 /*!< HalfWord-wise input data inversion */
|
||||
#define CRC_INPUTDATA_INVERSION_WORD CRC_CR_REV_IN /*!< Word-wise input data inversion */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRCEx_Output_Data_Inversion Output Data Inversion Modes
|
||||
* @{
|
||||
*/
|
||||
#define CRC_OUTPUTDATA_INVERSION_DISABLE 0x00000000U /*!< No output data inversion */
|
||||
#define CRC_OUTPUTDATA_INVERSION_ENABLE CRC_CR_REV_OUT /*!< Bit-wise output data inversion */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup CRCEx_Exported_Macros CRC Extended Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Set CRC output reversal
|
||||
* @param __HANDLE__ CRC handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_CRC_OUTPUTREVERSAL_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_REV_OUT)
|
||||
|
||||
/**
|
||||
* @brief Unset CRC output reversal
|
||||
* @param __HANDLE__ CRC handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_CRC_OUTPUTREVERSAL_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(CRC_CR_REV_OUT))
|
||||
|
||||
/**
|
||||
* @brief Set CRC non-default polynomial
|
||||
* @param __HANDLE__ CRC handle
|
||||
* @param __POLYNOMIAL__ 7, 8, 16 or 32-bit polynomial
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_CRC_POLYNOMIAL_CONFIG(__HANDLE__, __POLYNOMIAL__) ((__HANDLE__)->Instance->POL = (__POLYNOMIAL__))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros --------------------------------------------------------*/
|
||||
/** @defgroup CRCEx_Private_Macros CRC Extended Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_CRC_INPUTDATA_INVERSION_MODE(MODE) (((MODE) == CRC_INPUTDATA_INVERSION_NONE) || \
|
||||
((MODE) == CRC_INPUTDATA_INVERSION_BYTE) || \
|
||||
((MODE) == CRC_INPUTDATA_INVERSION_HALFWORD) || \
|
||||
((MODE) == CRC_INPUTDATA_INVERSION_WORD))
|
||||
|
||||
#define IS_CRC_OUTPUTDATA_INVERSION_MODE(MODE) (((MODE) == CRC_OUTPUTDATA_INVERSION_DISABLE) || \
|
||||
((MODE) == CRC_OUTPUTDATA_INVERSION_ENABLE))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/** @addtogroup CRCEx_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup CRCEx_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
/* Initialization and de-initialization functions ****************************/
|
||||
HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength);
|
||||
HAL_StatusTypeDef HAL_CRCEx_Input_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t InputReverseMode);
|
||||
HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t OutputReverseMode);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32WBxx_HAL_CRC_EX_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -1,648 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32wbxx_hal_cryp.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of CRYP HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32WBxx_HAL_CRYP_H
|
||||
#define STM32WBxx_HAL_CRYP_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32wbxx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32WBxx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/** @defgroup CRYP CRYP
|
||||
* @brief CRYP HAL module driver.
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup CRYP_Exported_Types CRYP Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief CRYP Init Structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t DataType; /*!< 32-bit data, 16-bit data, 8-bit data or 1-bit string.
|
||||
This parameter can be a value of @ref CRYP_Data_Type */
|
||||
uint32_t KeySize; /*!< Used only in AES mode : 128, 192 or 256 bit key length in CRYP1.
|
||||
128 or 256 bit key length in TinyAES This parameter can be a value of @ref CRYP_Key_Size */
|
||||
uint32_t *pKey; /*!< The key used for encryption/decryption */
|
||||
uint32_t *pInitVect; /*!< The initialization vector used also as initialization
|
||||
counter in CTR mode */
|
||||
uint32_t Algorithm; /*!< DES/ TDES Algorithm ECB/CBC
|
||||
AES Algorithm ECB/CBC/CTR/GCM or CCM
|
||||
This parameter can be a value of @ref CRYP_Algorithm_Mode */
|
||||
uint32_t *Header; /*!< used only in AES GCM and CCM Algorithm for authentication,
|
||||
GCM : also known as Additional Authentication Data
|
||||
CCM : named B1 composed of the associated data length and Associated Data. */
|
||||
uint32_t HeaderSize; /*!< The size of header buffer */
|
||||
uint32_t *B0; /*!< B0 is first authentication block used only in AES CCM mode */
|
||||
uint32_t DataWidthUnit; /*!< Payload Data Width Unit, this parameter can be value of @ref CRYP_Data_Width_Unit*/
|
||||
uint32_t HeaderWidthUnit; /*!< Header Width Unit, this parameter can be value of @ref CRYP_Header_Width_Unit*/
|
||||
uint32_t KeyIVConfigSkip; /*!< CRYP peripheral Key and IV configuration skip, to config Key and Initialization
|
||||
Vector only once and to skip configuration for consecutive processings.
|
||||
This parameter can be a value of @ref CRYP_Configuration_Skip */
|
||||
|
||||
} CRYP_ConfigTypeDef;
|
||||
|
||||
|
||||
/**
|
||||
* @brief CRYP State Structure definition
|
||||
*/
|
||||
|
||||
typedef enum
|
||||
{
|
||||
HAL_CRYP_STATE_RESET = 0x00U, /*!< CRYP not yet initialized or disabled */
|
||||
HAL_CRYP_STATE_READY = 0x01U, /*!< CRYP initialized and ready for use */
|
||||
HAL_CRYP_STATE_BUSY = 0x02U, /*!< CRYP BUSY, internal processing is ongoing */
|
||||
#if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
|
||||
HAL_CRYP_STATE_SUSPENDED = 0x03U, /*!< CRYP suspended */
|
||||
#endif /* USE_HAL_CRYP_SUSPEND_RESUME */
|
||||
} HAL_CRYP_STATETypeDef;
|
||||
|
||||
#if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
|
||||
/**
|
||||
* @brief HAL CRYP mode suspend definitions
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_CRYP_SUSPEND_NONE = 0x00U, /*!< CRYP processing suspension not requested */
|
||||
HAL_CRYP_SUSPEND = 0x01U /*!< CRYP processing suspension requested */
|
||||
}HAL_SuspendTypeDef;
|
||||
#endif /* USE_HAL_CRYP_SUSPEND_RESUME */
|
||||
|
||||
/**
|
||||
* @brief CRYP handle Structure definition
|
||||
*/
|
||||
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
|
||||
typedef struct __CRYP_HandleTypeDef
|
||||
#else
|
||||
typedef struct
|
||||
#endif
|
||||
{
|
||||
AES_TypeDef *Instance; /*!< AES Register base address */
|
||||
|
||||
CRYP_ConfigTypeDef Init; /*!< CRYP required parameters */
|
||||
|
||||
FunctionalState AutoKeyDerivation; /*!< Used only in TinyAES to allow to bypass or not key write-up before decryption.
|
||||
This parameter can be a value of ENABLE/DISABLE */
|
||||
|
||||
uint32_t *pCrypInBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */
|
||||
|
||||
uint32_t *pCrypOutBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */
|
||||
|
||||
__IO uint16_t CrypHeaderCount; /*!< Counter of header data in words */
|
||||
|
||||
__IO uint16_t CrypInCount; /*!< Counter of input data in words */
|
||||
|
||||
__IO uint16_t CrypOutCount; /*!< Counter of output data in words */
|
||||
|
||||
uint16_t Size; /*!< Length of input data */
|
||||
|
||||
uint32_t Phase; /*!< CRYP peripheral phase */
|
||||
|
||||
DMA_HandleTypeDef *hdmain; /*!< CRYP In DMA handle parameters */
|
||||
|
||||
DMA_HandleTypeDef *hdmaout; /*!< CRYP Out DMA handle parameters */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< CRYP locking object */
|
||||
|
||||
__IO HAL_CRYP_STATETypeDef State; /*!< CRYP peripheral state */
|
||||
|
||||
__IO uint32_t ErrorCode; /*!< CRYP peripheral error code */
|
||||
|
||||
uint32_t KeyIVConfig; /*!< CRYP peripheral Key and IV configuration flag, used when
|
||||
configuration can be skipped */
|
||||
|
||||
uint32_t SizesSum; /*!< Sum of successive payloads lengths (in bytes), stored
|
||||
for a single signature computation after several
|
||||
messages processing */
|
||||
|
||||
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
|
||||
void (*InCpltCallback)(struct __CRYP_HandleTypeDef *hcryp); /*!< CRYP Input FIFO transfer completed callback */
|
||||
void (*OutCpltCallback)(struct __CRYP_HandleTypeDef *hcryp); /*!< CRYP Output FIFO transfer completed callback */
|
||||
void (*ErrorCallback)(struct __CRYP_HandleTypeDef *hcryp); /*!< CRYP Error callback */
|
||||
|
||||
void (* MspInitCallback)(struct __CRYP_HandleTypeDef *hcryp); /*!< CRYP Msp Init callback */
|
||||
void (* MspDeInitCallback)(struct __CRYP_HandleTypeDef *hcryp); /*!< CRYP Msp DeInit callback */
|
||||
|
||||
#endif /* (USE_HAL_CRYP_REGISTER_CALLBACKS) */
|
||||
|
||||
#if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
|
||||
|
||||
__IO HAL_SuspendTypeDef SuspendRequest; /*!< CRYP peripheral suspension request flag */
|
||||
|
||||
CRYP_ConfigTypeDef Init_saved; /*!< copy of CRYP required parameters when processing is suspended */
|
||||
|
||||
uint32_t *pCrypInBuffPtr_saved; /*!< copy of CRYP input pointer when processing is suspended */
|
||||
|
||||
uint32_t *pCrypOutBuffPtr_saved; /*!< copy of CRYP output pointer when processing is suspended */
|
||||
|
||||
uint32_t CrypInCount_saved; /*!< copy of CRYP input data counter when processing is suspended */
|
||||
|
||||
uint32_t CrypOutCount_saved; /*!< copy of CRYP output data counter when processing is suspended */
|
||||
|
||||
uint32_t Phase_saved; /*!< copy of CRYP authentication phase when processing is suspended */
|
||||
|
||||
__IO HAL_CRYP_STATETypeDef State_saved; /*!< copy of CRYP peripheral state when processing is suspended */
|
||||
|
||||
uint32_t IV_saved[4]; /*!< copy of Initialisation Vector registers */
|
||||
|
||||
uint32_t SUSPxR_saved[8]; /*!< copy of suspension registers */
|
||||
|
||||
uint32_t CR_saved; /*!< copy of CRYP control register when processing is suspended*/
|
||||
|
||||
uint32_t Key_saved[8]; /*!< copy of key registers */
|
||||
|
||||
uint16_t Size_saved; /*!< copy of input buffer size */
|
||||
|
||||
uint16_t CrypHeaderCount_saved; /*!< copy of CRYP header data counter when processing is suspended */
|
||||
|
||||
uint32_t SizesSum_saved; /*!< copy of SizesSum when processing is suspended */
|
||||
|
||||
uint32_t ResumingFlag; /*!< resumption flag to bypass steps already carried out */
|
||||
|
||||
FunctionalState AutoKeyDerivation_saved; /*!< copy of CRYP handle auto key derivation parameter */
|
||||
|
||||
#endif /* USE_HAL_CRYP_SUSPEND_RESUME */
|
||||
|
||||
} CRYP_HandleTypeDef;
|
||||
|
||||
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
|
||||
/** @defgroup HAL_CRYP_Callback_ID_enumeration_definition HAL CRYP Callback ID enumeration definition
|
||||
* @brief HAL CRYP Callback ID enumeration definition
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_CRYP_MSPINIT_CB_ID = 0x00U, /*!< CRYP MspInit callback ID */
|
||||
HAL_CRYP_MSPDEINIT_CB_ID = 0x01U, /*!< CRYP MspDeInit callback ID */
|
||||
HAL_CRYP_INPUT_COMPLETE_CB_ID = 0x02U, /*!< CRYP Input FIFO transfer completed callback ID */
|
||||
HAL_CRYP_OUTPUT_COMPLETE_CB_ID = 0x03U, /*!< CRYP Output FIFO transfer completed callback ID */
|
||||
HAL_CRYP_ERROR_CB_ID = 0x04U, /*!< CRYP Error callback ID */
|
||||
} HAL_CRYP_CallbackIDTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_CRYP_Callback_pointer_definition HAL CRYP Callback pointer definition
|
||||
* @brief HAL CRYP Callback pointer definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
typedef void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef *hcryp); /*!< pointer to a common CRYP callback function */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup CRYP_Exported_Constants CRYP Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CRYP_Error_Definition CRYP Error Definition
|
||||
* @{
|
||||
*/
|
||||
#define HAL_CRYP_ERROR_NONE 0x00000000U /*!< No error */
|
||||
#define HAL_CRYP_ERROR_WRITE 0x00000001U /*!< Write error */
|
||||
#define HAL_CRYP_ERROR_READ 0x00000002U /*!< Read error */
|
||||
#define HAL_CRYP_ERROR_DMA 0x00000004U /*!< DMA error */
|
||||
#define HAL_CRYP_ERROR_BUSY 0x00000008U /*!< Busy flag error */
|
||||
#define HAL_CRYP_ERROR_TIMEOUT 0x00000010U /*!< Timeout error */
|
||||
#define HAL_CRYP_ERROR_NOT_SUPPORTED 0x00000020U /*!< Not supported mode */
|
||||
#define HAL_CRYP_ERROR_AUTH_TAG_SEQUENCE 0x00000040U /*!< Sequence are not respected only for GCM or CCM */
|
||||
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
|
||||
#define HAL_CRYP_ERROR_INVALID_CALLBACK ((uint32_t)0x00000080U) /*!< Invalid Callback error */
|
||||
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRYP_Data_Width_Unit CRYP Data Width Unit
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CRYP_DATAWIDTHUNIT_WORD 0x00000000U /*!< By default, size unit is word */
|
||||
#define CRYP_DATAWIDTHUNIT_BYTE 0x00000001U /*!< By default, size unit is byte */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRYP_Header_Width_Unit CRYP Header Width Unit
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CRYP_HEADERWIDTHUNIT_WORD 0x00000000U /*!< By default, header size unit is word */
|
||||
#define CRYP_HEADERWIDTHUNIT_BYTE 0x00000001U /*!< By default, header size unit is byte */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRYP_Algorithm_Mode CRYP Algorithm Mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CRYP_AES_ECB 0x00000000U /*!< Electronic codebook chaining algorithm */
|
||||
#define CRYP_AES_CBC AES_CR_CHMOD_0 /*!< Cipher block chaining algorithm */
|
||||
#define CRYP_AES_CTR AES_CR_CHMOD_1 /*!< Counter mode chaining algorithm */
|
||||
#define CRYP_AES_GCM_GMAC (AES_CR_CHMOD_0 | AES_CR_CHMOD_1) /*!< Galois counter mode - Galois message authentication code */
|
||||
#define CRYP_AES_CCM AES_CR_CHMOD_2 /*!< Counter with Cipher Mode */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRYP_Key_Size CRYP Key Size
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CRYP_KEYSIZE_128B 0x00000000U /*!< 128-bit long key */
|
||||
#define CRYP_KEYSIZE_256B AES_CR_KEYSIZE /*!< 256-bit long key */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRYP_Data_Type CRYP Data Type
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CRYP_DATATYPE_32B 0x00000000U /*!< 32-bit data type (no swapping) */
|
||||
#define CRYP_DATATYPE_16B AES_CR_DATATYPE_0 /*!< 16-bit data type (half-word swapping) */
|
||||
#define CRYP_DATATYPE_8B AES_CR_DATATYPE_1 /*!< 8-bit data type (byte swapping) */
|
||||
#define CRYP_DATATYPE_1B AES_CR_DATATYPE /*!< 1-bit data type (bit swapping) */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRYP_Interrupt CRYP Interrupt
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CRYP_IT_CCFIE AES_CR_CCFIE /*!< Computation Complete interrupt enable */
|
||||
#define CRYP_IT_ERRIE AES_CR_ERRIE /*!< Error interrupt enable */
|
||||
#define CRYP_IT_WRERR AES_SR_WRERR /*!< Write Error */
|
||||
#define CRYP_IT_RDERR AES_SR_RDERR /*!< Read Error */
|
||||
#define CRYP_IT_CCF AES_SR_CCF /*!< Computation completed */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRYP_Flags CRYP Flags
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* status flags */
|
||||
#define CRYP_FLAG_BUSY AES_SR_BUSY /*!< GCM process suspension forbidden */
|
||||
#define CRYP_FLAG_WRERR AES_SR_WRERR /*!< Write Error */
|
||||
#define CRYP_FLAG_RDERR AES_SR_RDERR /*!< Read error */
|
||||
#define CRYP_FLAG_CCF AES_SR_CCF /*!< Computation completed */
|
||||
/* clearing flags */
|
||||
#define CRYP_CCF_CLEAR AES_CR_CCFC /*!< Computation Complete Flag Clear */
|
||||
#define CRYP_ERR_CLEAR AES_CR_ERRC /*!< Error Flag Clear */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRYP_Configuration_Skip CRYP Key and IV Configuration Skip Mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CRYP_KEYIVCONFIG_ALWAYS 0x00000000U /*!< Peripheral Key and IV configuration to do systematically */
|
||||
#define CRYP_KEYIVCONFIG_ONCE 0x00000001U /*!< Peripheral Key and IV configuration to do only once */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/** @defgroup CRYP_Exported_Macros CRYP Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset CRYP handle state
|
||||
* @param __HANDLE__ specifies the CRYP handle.
|
||||
* @retval None
|
||||
*/
|
||||
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
|
||||
#define __HAL_CRYP_RESET_HANDLE_STATE(__HANDLE__) do{\
|
||||
(__HANDLE__)->State = HAL_CRYP_STATE_RESET;\
|
||||
(__HANDLE__)->MspInitCallback = NULL;\
|
||||
(__HANDLE__)->MspDeInitCallback = NULL;\
|
||||
}while(0U)
|
||||
#else
|
||||
#define __HAL_CRYP_RESET_HANDLE_STATE(__HANDLE__) ( (__HANDLE__)->State = HAL_CRYP_STATE_RESET)
|
||||
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @brief Enable/Disable the CRYP peripheral.
|
||||
* @param __HANDLE__ specifies the CRYP handle.
|
||||
* @retval None
|
||||
*/
|
||||
|
||||
#define __HAL_CRYP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= AES_CR_EN)
|
||||
#define __HAL_CRYP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~AES_CR_EN)
|
||||
|
||||
|
||||
/** @brief Check whether the specified CRYP status flag is set or not.
|
||||
* @param __HANDLE__ specifies the CRYP handle.
|
||||
* @param __FLAG__ specifies the flag to check.
|
||||
* This parameter can be one of the following values for TinyAES:
|
||||
* @arg @ref CRYP_FLAG_BUSY GCM process suspension forbidden
|
||||
* @arg @ref CRYP_IT_WRERR Write Error
|
||||
* @arg @ref CRYP_IT_RDERR Read Error
|
||||
* @arg @ref CRYP_IT_CCF Computation Complete
|
||||
* This parameter can be one of the following values for CRYP:
|
||||
* @arg CRYP_FLAG_BUSY: The CRYP core is currently processing a block of data
|
||||
* or a key preparation (for AES decryption).
|
||||
* @arg CRYP_FLAG_IFEM: Input FIFO is empty
|
||||
* @arg CRYP_FLAG_IFNF: Input FIFO is not full
|
||||
* @arg CRYP_FLAG_INRIS: Input FIFO service raw interrupt is pending
|
||||
* @arg CRYP_FLAG_OFNE: Output FIFO is not empty
|
||||
* @arg CRYP_FLAG_OFFU: Output FIFO is full
|
||||
* @arg CRYP_FLAG_OUTRIS: Input FIFO service raw interrupt is pending
|
||||
* @retval The state of __FLAG__ (TRUE or FALSE).
|
||||
*/
|
||||
|
||||
#define CRYP_FLAG_MASK 0x0000001FU
|
||||
#define __HAL_CRYP_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
|
||||
|
||||
/** @brief Clear the CRYP pending status flag.
|
||||
* @param __HANDLE__ specifies the CRYP handle.
|
||||
* @param __FLAG__ specifies the flag to clear.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref CRYP_ERR_CLEAR Read (RDERR) or Write Error (WRERR) Flag Clear
|
||||
* @arg @ref CRYP_CCF_CLEAR Computation Complete Flag (CCF) Clear
|
||||
* @retval None
|
||||
*/
|
||||
|
||||
#define __HAL_CRYP_CLEAR_FLAG(__HANDLE__, __FLAG__) SET_BIT((__HANDLE__)->Instance->CR, (__FLAG__))
|
||||
|
||||
|
||||
/** @brief Check whether the specified CRYP interrupt source is enabled or not.
|
||||
* @param __HANDLE__ specifies the CRYP handle.
|
||||
* @param __INTERRUPT__ CRYP interrupt source to check
|
||||
* This parameter can be one of the following values for TinyAES:
|
||||
* @arg @ref CRYP_IT_ERRIE Error interrupt (used for RDERR and WRERR)
|
||||
* @arg @ref CRYP_IT_CCFIE Computation Complete interrupt
|
||||
* @retval State of interruption (TRUE or FALSE).
|
||||
*/
|
||||
|
||||
#define __HAL_CRYP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__))
|
||||
|
||||
/** @brief Check whether the specified CRYP interrupt is set or not.
|
||||
* @param __HANDLE__ specifies the CRYP handle.
|
||||
* @param __INTERRUPT__ specifies the interrupt to check.
|
||||
* This parameter can be one of the following values for TinyAES:
|
||||
* @arg @ref CRYP_IT_WRERR Write Error
|
||||
* @arg @ref CRYP_IT_RDERR Read Error
|
||||
* @arg @ref CRYP_IT_CCF Computation Complete
|
||||
* This parameter can be one of the following values for CRYP:
|
||||
* @arg CRYP_IT_INI: Input FIFO service masked interrupt status
|
||||
* @arg CRYP_IT_OUTI: Output FIFO service masked interrupt status
|
||||
* @retval The state of __INTERRUPT__ (TRUE or FALSE).
|
||||
*/
|
||||
|
||||
#define __HAL_CRYP_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR & (__INTERRUPT__)) == (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Enable the CRYP interrupt.
|
||||
* @param __HANDLE__ specifies the CRYP handle.
|
||||
* @param __INTERRUPT__ CRYP Interrupt.
|
||||
* This parameter can be one of the following values for TinyAES:
|
||||
* @arg @ref CRYP_IT_ERRIE Error interrupt (used for RDERR and WRERR)
|
||||
* @arg @ref CRYP_IT_CCFIE Computation Complete interrupt
|
||||
* This parameter can be one of the following values for CRYP:
|
||||
* @ CRYP_IT_INI : Input FIFO service interrupt mask.
|
||||
* @ CRYP_IT_OUTI : Output FIFO service interrupt mask.CRYP interrupt.
|
||||
* @retval None
|
||||
*/
|
||||
|
||||
#define __HAL_CRYP_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Disable the CRYP interrupt.
|
||||
* @param __HANDLE__ specifies the CRYP handle.
|
||||
* @param __INTERRUPT__ CRYP Interrupt.
|
||||
* This parameter can be one of the following values for TinyAES:
|
||||
* @arg @ref CRYP_IT_ERRIE Error interrupt (used for RDERR and WRERR)
|
||||
* @arg @ref CRYP_IT_CCFIE Computation Complete interrupt
|
||||
* This parameter can be one of the following values for CRYP:
|
||||
* @ CRYP_IT_INI : Input FIFO service interrupt mask.
|
||||
* @ CRYP_IT_OUTI : Output FIFO service interrupt mask.CRYP interrupt.
|
||||
* @retval None
|
||||
*/
|
||||
|
||||
#define __HAL_CRYP_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Include CRYP HAL Extended module */
|
||||
#include "stm32wbxx_hal_cryp_ex.h"
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup CRYP_Exported_Functions CRYP Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup CRYP_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp);
|
||||
HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp);
|
||||
void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp);
|
||||
void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp);
|
||||
HAL_StatusTypeDef HAL_CRYP_SetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf);
|
||||
HAL_StatusTypeDef HAL_CRYP_GetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf);
|
||||
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
|
||||
HAL_StatusTypeDef HAL_CRYP_RegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID, pCRYP_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_CRYP_UnRegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID);
|
||||
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
|
||||
#if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
|
||||
void HAL_CRYP_ProcessSuspend(CRYP_HandleTypeDef *hcryp);
|
||||
HAL_StatusTypeDef HAL_CRYP_Suspend(CRYP_HandleTypeDef *hcryp);
|
||||
HAL_StatusTypeDef HAL_CRYP_Resume(CRYP_HandleTypeDef *hcryp);
|
||||
#endif /* defined (USE_HAL_CRYP_SUSPEND_RESUME) */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup CRYP_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* encryption/decryption ***********************************/
|
||||
HAL_StatusTypeDef HAL_CRYP_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_CRYP_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_CRYP_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output);
|
||||
HAL_StatusTypeDef HAL_CRYP_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output);
|
||||
HAL_StatusTypeDef HAL_CRYP_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output);
|
||||
HAL_StatusTypeDef HAL_CRYP_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @addtogroup CRYP_Exported_Functions_Group3
|
||||
* @{
|
||||
*/
|
||||
/* Interrupt Handler functions **********************************************/
|
||||
void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp);
|
||||
HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp);
|
||||
void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp);
|
||||
void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp);
|
||||
void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp);
|
||||
uint32_t HAL_CRYP_GetError(CRYP_HandleTypeDef *hcryp);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros --------------------------------------------------------*/
|
||||
/** @defgroup CRYP_Private_Macros CRYP Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CRYP_IS_CRYP_Definitions CRYP Private macros to check input parameters
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_CRYP_ALGORITHM(ALGORITHM) (((ALGORITHM) == CRYP_AES_ECB) || \
|
||||
((ALGORITHM) == CRYP_AES_CBC) || \
|
||||
((ALGORITHM) == CRYP_AES_CTR) || \
|
||||
((ALGORITHM) == CRYP_AES_GCM_GMAC)|| \
|
||||
((ALGORITHM) == CRYP_AES_CCM))
|
||||
|
||||
|
||||
#define IS_CRYP_KEYSIZE(KEYSIZE)(((KEYSIZE) == CRYP_KEYSIZE_128B) || \
|
||||
((KEYSIZE) == CRYP_KEYSIZE_256B))
|
||||
|
||||
#define IS_CRYP_DATATYPE(DATATYPE)(((DATATYPE) == CRYP_DATATYPE_32B) || \
|
||||
((DATATYPE) == CRYP_DATATYPE_16B) || \
|
||||
((DATATYPE) == CRYP_DATATYPE_8B) || \
|
||||
((DATATYPE) == CRYP_DATATYPE_1B))
|
||||
|
||||
#define IS_CRYP_INIT(CONFIG)(((CONFIG) == CRYP_KEYIVCONFIG_ALWAYS) || \
|
||||
((CONFIG) == CRYP_KEYIVCONFIG_ONCE))
|
||||
|
||||
#define IS_CRYP_BUFFERSIZE(ALGO, DATAWIDTH, SIZE) \
|
||||
(((((ALGO) == CRYP_AES_CTR)) && \
|
||||
((((DATAWIDTH) == CRYP_DATAWIDTHUNIT_WORD) && (((SIZE) % 4U) == 0U)) || \
|
||||
(((DATAWIDTH) == CRYP_DATAWIDTHUNIT_BYTE) && (((SIZE) % 16U) == 0U)))) || \
|
||||
(((ALGO) == CRYP_AES_ECB) || ((ALGO) == CRYP_AES_CBC) || \
|
||||
((ALGO)== CRYP_AES_GCM_GMAC) || ((ALGO) == CRYP_AES_CCM)))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup CRYP_Private_Constants CRYP Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Private defines -----------------------------------------------------------*/
|
||||
/** @defgroup CRYP_Private_Defines CRYP Private Defines
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/** @defgroup CRYP_Private_Variables CRYP Private Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/** @defgroup CRYP_Private_Functions CRYP Private Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32WBxx_HAL_CRYP_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -1,133 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32wbxx_hal_cryp_ex.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of CRYPEx HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32WBxx_HAL_CRYP_EX_H
|
||||
#define STM32WBxx_HAL_CRYP_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32wbxx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32WBxx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/** @defgroup CRYPEx CRYPEx
|
||||
* @brief CRYP Extension HAL module driver.
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/** @defgroup CRYPEx_Private_Types CRYPEx Private Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/** @defgroup CRYPEx_Private_Variables CRYPEx Private Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup CRYPEx_Private_Constants CRYPEx Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup CRYPEx_Private_Macros CRYPEx Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/** @defgroup CRYPEx_Private_Functions CRYPEx Private Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup CRYPEx_Exported_Functions CRYPEx Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup CRYPEx_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, uint32_t *AuthTag, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, uint32_t *AuthTag, uint32_t Timeout);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup CRYPEx_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
void HAL_CRYPEx_EnableAutoKeyDerivation(CRYP_HandleTypeDef *hcryp);
|
||||
void HAL_CRYPEx_DisableAutoKeyDerivation(CRYP_HandleTypeDef *hcryp);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32WBxx_HAL_CRYP_EX_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -1,213 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32wbxx_hal_def.h
|
||||
* @author MCD Application Team
|
||||
* @brief This file contains HAL common defines, enumeration, macros and
|
||||
* structures definitions.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32WBxx_HAL_DEF
|
||||
#define __STM32WBxx_HAL_DEF
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32wbxx.h"
|
||||
#include "Legacy/stm32_hal_legacy.h" /* Aliases file for old names compatibility */
|
||||
#include <stddef.h>
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief HAL Status structures definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_OK = 0x00,
|
||||
HAL_ERROR = 0x01,
|
||||
HAL_BUSY = 0x02,
|
||||
HAL_TIMEOUT = 0x03
|
||||
} HAL_StatusTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL Lock structures definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_UNLOCKED = 0x00,
|
||||
HAL_LOCKED = 0x01
|
||||
} HAL_LockTypeDef;
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
#ifndef UNUSED
|
||||
#define UNUSED(X) (void)(X) /* To avoid gcc/g++ warnings */
|
||||
#endif
|
||||
|
||||
#define HAL_MAX_DELAY 0xFFFFFFFFU
|
||||
|
||||
#define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) == (BIT))
|
||||
#define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == 0U)
|
||||
|
||||
#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__) \
|
||||
do{ \
|
||||
(__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \
|
||||
(__DMA_HANDLE__).Parent = (__HANDLE__); \
|
||||
} while(0)
|
||||
|
||||
/** @brief Reset the Handle's State field.
|
||||
* @param __HANDLE__ specifies the Peripheral Handle.
|
||||
* @note This macro can be used for the following purpose:
|
||||
* - When the Handle is declared as local variable; before passing it as parameter
|
||||
* to HAL_PPP_Init() for the first time, it is mandatory to use this macro
|
||||
* to set to 0 the Handle's "State" field.
|
||||
* Otherwise, "State" field may have any random value and the first time the function
|
||||
* HAL_PPP_Init() is called, the low level hardware initialization will be missed
|
||||
* (i.e. HAL_PPP_MspInit() will not be executed).
|
||||
* - When there is a need to reconfigure the low level hardware: instead of calling
|
||||
* HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init().
|
||||
* In this later function, when the Handle's "State" field is set to 0, it will execute the function
|
||||
* HAL_PPP_MspInit() which will reconfigure the low level hardware.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0)
|
||||
|
||||
#if (USE_RTOS == 1)
|
||||
/* Reserved for future use */
|
||||
#error " USE_RTOS should be 0 in the current HAL release "
|
||||
#else
|
||||
#define __HAL_LOCK(__HANDLE__) \
|
||||
do{ \
|
||||
if((__HANDLE__)->Lock == HAL_LOCKED) \
|
||||
{ \
|
||||
return HAL_BUSY; \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__HANDLE__)->Lock = HAL_LOCKED; \
|
||||
} \
|
||||
}while (0)
|
||||
|
||||
#define __HAL_UNLOCK(__HANDLE__) \
|
||||
do{ \
|
||||
(__HANDLE__)->Lock = HAL_UNLOCKED; \
|
||||
}while (0)
|
||||
#endif /* USE_RTOS */
|
||||
|
||||
|
||||
#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */
|
||||
#ifndef __weak
|
||||
#define __weak __attribute__((weak))
|
||||
#endif
|
||||
#ifndef __packed
|
||||
#define __packed __attribute__((packed))
|
||||
#endif
|
||||
#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
|
||||
#ifndef __weak
|
||||
#define __weak __attribute__((weak))
|
||||
#endif /* __weak */
|
||||
#ifndef __packed
|
||||
#define __packed __attribute__((__packed__))
|
||||
#endif /* __packed */
|
||||
#endif /* __GNUC__ */
|
||||
|
||||
|
||||
/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */
|
||||
#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */
|
||||
#ifndef __ALIGN_BEGIN
|
||||
#define __ALIGN_BEGIN
|
||||
#endif
|
||||
#ifndef __ALIGN_END
|
||||
#define __ALIGN_END __attribute__ ((aligned (4)))
|
||||
#endif
|
||||
#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
|
||||
#ifndef __ALIGN_END
|
||||
#define __ALIGN_END __attribute__ ((aligned (4)))
|
||||
#endif /* __ALIGN_END */
|
||||
#ifndef __ALIGN_BEGIN
|
||||
#define __ALIGN_BEGIN
|
||||
#endif /* __ALIGN_BEGIN */
|
||||
#else
|
||||
#ifndef __ALIGN_END
|
||||
#define __ALIGN_END
|
||||
#endif /* __ALIGN_END */
|
||||
#ifndef __ALIGN_BEGIN
|
||||
#if defined (__CC_ARM) /* ARM Compiler V5 */
|
||||
#define __ALIGN_BEGIN __align(4)
|
||||
#elif defined (__ICCARM__) /* IAR Compiler */
|
||||
#define __ALIGN_BEGIN
|
||||
#endif /* __CC_ARM */
|
||||
#endif /* __ALIGN_BEGIN */
|
||||
#endif /* __GNUC__ */
|
||||
|
||||
/**
|
||||
* @brief __RAM_FUNC definition
|
||||
*/
|
||||
#if defined ( __CC_ARM ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
|
||||
/* ARM Compiler V4/V5 and V6
|
||||
--------------------------
|
||||
RAM functions are defined using the toolchain options.
|
||||
Functions that are executed in RAM should reside in a separate source module.
|
||||
Using the 'Options for File' dialog you can simply change the 'Code / Const'
|
||||
area of a module to a memory space in physical RAM.
|
||||
Available memory areas are declared in the 'Target' tab of the 'Options for Target'
|
||||
dialog.
|
||||
*/
|
||||
#define __RAM_FUNC
|
||||
|
||||
#elif defined ( __ICCARM__ )
|
||||
/* ICCARM Compiler
|
||||
---------------
|
||||
RAM functions are defined using a specific toolchain keyword "__ramfunc".
|
||||
*/
|
||||
#define __RAM_FUNC __ramfunc
|
||||
|
||||
#elif defined ( __GNUC__ )
|
||||
/* GNU Compiler
|
||||
------------
|
||||
RAM functions are defined using a specific toolchain attribute
|
||||
"__attribute__((section(".RamFunc")))".
|
||||
*/
|
||||
#define __RAM_FUNC __attribute__((section(".RamFunc")))
|
||||
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief __NOINLINE definition
|
||||
*/
|
||||
#if defined ( __CC_ARM ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || defined ( __GNUC__ )
|
||||
/* ARM V4/V5 and V6 & GNU Compiler
|
||||
-------------------------------
|
||||
*/
|
||||
#define __NOINLINE __attribute__ ( (noinline) )
|
||||
|
||||
#elif defined ( __ICCARM__ )
|
||||
/* ICCARM Compiler
|
||||
---------------
|
||||
*/
|
||||
#define __NOINLINE _Pragma("optimize = no_inline")
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* ___STM32WBxx_HAL_DEF */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -1,715 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32wbxx_hal_dma.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of DMA HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32WBxx_HAL_DMA_H
|
||||
#define STM32WBxx_HAL_DMA_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32wbxx_hal_def.h"
|
||||
#include "stm32wbxx_ll_dma.h"
|
||||
|
||||
/** @addtogroup STM32WBxx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup DMA
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup DMA_Exported_Types DMA Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief DMA Configuration Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Request; /*!< Specifies the request selected for the specified channel.
|
||||
This parameter can be a value of @ref DMA_request */
|
||||
|
||||
uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
|
||||
from memory to memory or from peripheral to memory.
|
||||
This parameter can be a value of @ref DMA_Data_transfer_direction */
|
||||
|
||||
uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not.
|
||||
This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
|
||||
|
||||
uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not.
|
||||
This parameter can be a value of @ref DMA_Memory_incremented_mode */
|
||||
|
||||
uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width.
|
||||
This parameter can be a value of @ref DMA_Peripheral_data_size */
|
||||
|
||||
uint32_t MemDataAlignment; /*!< Specifies the Memory data width.
|
||||
This parameter can be a value of @ref DMA_Memory_data_size */
|
||||
|
||||
uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx.
|
||||
This parameter can be a value of @ref DMA_mode
|
||||
@note The circular buffer mode cannot be used if the memory-to-memory
|
||||
data transfer is configured on the selected Channel */
|
||||
|
||||
uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx.
|
||||
This parameter can be a value of @ref DMA_Priority_level */
|
||||
} DMA_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL DMA State structures definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */
|
||||
HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */
|
||||
HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */
|
||||
HAL_DMA_STATE_TIMEOUT = 0x03U, /*!< DMA timeout state */
|
||||
} HAL_DMA_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL DMA Error Code structure definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */
|
||||
HAL_DMA_HALF_TRANSFER = 0x01U /*!< Half Transfer */
|
||||
} HAL_DMA_LevelCompleteTypeDef;
|
||||
|
||||
|
||||
/**
|
||||
* @brief HAL DMA Callback ID structure definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */
|
||||
HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half transfer */
|
||||
HAL_DMA_XFER_ERROR_CB_ID = 0x02U, /*!< Error */
|
||||
HAL_DMA_XFER_ABORT_CB_ID = 0x03U, /*!< Abort */
|
||||
HAL_DMA_XFER_ALL_CB_ID = 0x04U /*!< All */
|
||||
|
||||
} HAL_DMA_CallbackIDTypeDef;
|
||||
|
||||
/**
|
||||
* @brief DMA handle Structure definition
|
||||
*/
|
||||
typedef struct __DMA_HandleTypeDef
|
||||
{
|
||||
DMA_Channel_TypeDef *Instance; /*!< Register base address */
|
||||
|
||||
DMA_InitTypeDef Init; /*!< DMA communication parameters */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< DMA locking object */
|
||||
|
||||
__IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */
|
||||
|
||||
void *Parent; /*!< Parent object state */
|
||||
|
||||
void (* XferCpltCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer complete callback */
|
||||
|
||||
void (* XferHalfCpltCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA Half transfer complete callback */
|
||||
|
||||
void (* XferErrorCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer error callback */
|
||||
|
||||
void (* XferAbortCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer abort callback */
|
||||
|
||||
__IO uint32_t ErrorCode; /*!< DMA Error code */
|
||||
|
||||
DMA_TypeDef *DmaBaseAddress; /*!< DMA Channel Base Address */
|
||||
|
||||
uint32_t ChannelIndex; /*!< DMA Channel Index */
|
||||
|
||||
DMAMUX_Channel_TypeDef *DMAmuxChannel; /*!< Register base address */
|
||||
|
||||
DMAMUX_ChannelStatus_TypeDef *DMAmuxChannelStatus; /*!< DMAMUX Channels Status Base Address */
|
||||
|
||||
uint32_t DMAmuxChannelStatusMask; /*!< DMAMUX Channel Status Mask */
|
||||
|
||||
DMAMUX_RequestGen_TypeDef *DMAmuxRequestGen; /*!< DMAMUX request generator Base Address */
|
||||
|
||||
DMAMUX_RequestGenStatus_TypeDef *DMAmuxRequestGenStatus; /*!< DMAMUX request generator Address */
|
||||
|
||||
uint32_t DMAmuxRequestGenStatusMask; /*!< DMAMUX request generator Status mask */
|
||||
} DMA_HandleTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup DMA_Exported_Constants DMA Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Error_Code DMA Error Code
|
||||
* @{
|
||||
*/
|
||||
#define HAL_DMA_ERROR_NONE 0x00000000U /*!< No error */
|
||||
#define HAL_DMA_ERROR_TE 0x00000001U /*!< Transfer error */
|
||||
#define HAL_DMA_ERROR_NO_XFER 0x00000004U /*!< Abort requested with no Xfer ongoing */
|
||||
#define HAL_DMA_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */
|
||||
#define HAL_DMA_ERROR_NOT_SUPPORTED 0x00000100U /*!< Not supported mode */
|
||||
#define HAL_DMA_ERROR_SYNC 0x00000200U /*!< DMAMUX sync overrun error */
|
||||
#define HAL_DMA_ERROR_REQGEN 0x00000400U /*!< DMAMUX request generator overrun error */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_request DMA request
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DMA_REQUEST_MEM2MEM LL_DMAMUX_REQ_MEM2MEM /*!< memory to memory transfer */
|
||||
|
||||
#define DMA_REQUEST_GENERATOR0 LL_DMAMUX_REQ_GENERATOR0 /*!< DMAMUX request generator 0 */
|
||||
#define DMA_REQUEST_GENERATOR1 LL_DMAMUX_REQ_GENERATOR1 /*!< DMAMUX request generator 1 */
|
||||
#define DMA_REQUEST_GENERATOR2 LL_DMAMUX_REQ_GENERATOR2 /*!< DMAMUX request generator 2 */
|
||||
#define DMA_REQUEST_GENERATOR3 LL_DMAMUX_REQ_GENERATOR3 /*!< DMAMUX request generator 3 */
|
||||
|
||||
#define DMA_REQUEST_ADC1 LL_DMAMUX_REQ_ADC1 /*!< DMAMUX ADC1 request */
|
||||
|
||||
#define DMA_REQUEST_SPI1_RX LL_DMAMUX_REQ_SPI1_RX /*!< DMAMUX SPI1 RX request */
|
||||
#define DMA_REQUEST_SPI1_TX LL_DMAMUX_REQ_SPI1_TX /*!< DMAMUX SPI1 TX request */
|
||||
#if defined(SPI2)
|
||||
#define DMA_REQUEST_SPI2_RX LL_DMAMUX_REQ_SPI2_RX /*!< DMAMUX SPI2 RX request */
|
||||
#define DMA_REQUEST_SPI2_TX LL_DMAMUX_REQ_SPI2_TX /*!< DMAMUX SPI2 TX request */
|
||||
#endif /* SPI2 */
|
||||
|
||||
#define DMA_REQUEST_I2C1_RX LL_DMAMUX_REQ_I2C1_RX /*!< DMAMUX I2C1 RX request */
|
||||
#define DMA_REQUEST_I2C1_TX LL_DMAMUX_REQ_I2C1_TX /*!< DMAMUX I2C1 TX request */
|
||||
#if defined(I2C3)
|
||||
#define DMA_REQUEST_I2C3_RX LL_DMAMUX_REQ_I2C3_RX /*!< DMAMUX I2C3 RX request */
|
||||
#define DMA_REQUEST_I2C3_TX LL_DMAMUX_REQ_I2C3_TX /*!< DMAMUX I2C3 TX request */
|
||||
#endif /* I2C3 */
|
||||
|
||||
#define DMA_REQUEST_USART1_RX LL_DMAMUX_REQ_USART1_RX /*!< DMAMUX USART1 RX request */
|
||||
#define DMA_REQUEST_USART1_TX LL_DMAMUX_REQ_USART1_TX /*!< DMAMUX USART1 TX request */
|
||||
|
||||
#if defined(LPUART1)
|
||||
#define DMA_REQUEST_LPUART1_RX LL_DMAMUX_REQ_LPUART1_RX /*!< DMAMUX LP_UART1_RX request */
|
||||
#define DMA_REQUEST_LPUART1_TX LL_DMAMUX_REQ_LPUART1_TX /*!< DMAMUX LP_UART1_RX request */
|
||||
#endif /* LPUART1 */
|
||||
|
||||
#if defined (SAI1)
|
||||
#define DMA_REQUEST_SAI1_A LL_DMAMUX_REQ_SAI1_A /*!< DMAMUX SAI1 A request */
|
||||
#define DMA_REQUEST_SAI1_B LL_DMAMUX_REQ_SAI1_B /*!< DMAMUX SAI1 B request */
|
||||
#endif /* SAI1 */
|
||||
|
||||
#if defined(QUADSPI)
|
||||
#define DMA_REQUEST_QUADSPI LL_DMAMUX_REQ_QUADSPI /*!< DMAMUX QUADSPI request */
|
||||
#endif /* QUADSPI */
|
||||
|
||||
#define DMA_REQUEST_TIM1_CH1 LL_DMAMUX_REQ_TIM1_CH1 /*!< DMAMUX TIM1 CH1 request */
|
||||
#define DMA_REQUEST_TIM1_CH2 LL_DMAMUX_REQ_TIM1_CH2 /*!< DMAMUX TIM1 CH2 request */
|
||||
#define DMA_REQUEST_TIM1_CH3 LL_DMAMUX_REQ_TIM1_CH3 /*!< DMAMUX TIM1 CH3 request */
|
||||
#define DMA_REQUEST_TIM1_CH4 LL_DMAMUX_REQ_TIM1_CH4 /*!< DMAMUX TIM1 CH4 request */
|
||||
#define DMA_REQUEST_TIM1_UP LL_DMAMUX_REQ_TIM1_UP /*!< DMAMUX TIM1 UP request */
|
||||
#define DMA_REQUEST_TIM1_TRIG LL_DMAMUX_REQ_TIM1_TRIG /*!< DMAMUX TIM1 TRIG request */
|
||||
#define DMA_REQUEST_TIM1_COM LL_DMAMUX_REQ_TIM1_COM /*!< DMAMUX TIM1 COM request */
|
||||
|
||||
#define DMA_REQUEST_TIM2_CH1 LL_DMAMUX_REQ_TIM2_CH1 /*!< DMAMUX TIM2 CH1 request */
|
||||
#define DMA_REQUEST_TIM2_CH2 LL_DMAMUX_REQ_TIM2_CH2 /*!< DMAMUX TIM2 CH2 request */
|
||||
#define DMA_REQUEST_TIM2_CH3 LL_DMAMUX_REQ_TIM2_CH3 /*!< DMAMUX TIM2 CH3 request */
|
||||
#define DMA_REQUEST_TIM2_CH4 LL_DMAMUX_REQ_TIM2_CH4 /*!< DMAMUX TIM2 CH4 request */
|
||||
#define DMA_REQUEST_TIM2_UP LL_DMAMUX_REQ_TIM2_UP /*!< DMAMUX TIM2 UP request */
|
||||
|
||||
#define DMA_REQUEST_TIM16_CH1 LL_DMAMUX_REQ_TIM16_CH1 /*!< DMAMUX TIM16 CH1 request */
|
||||
#define DMA_REQUEST_TIM16_UP LL_DMAMUX_REQ_TIM16_UP /*!< DMAMUX TIM16 UP request */
|
||||
|
||||
#define DMA_REQUEST_TIM17_CH1 LL_DMAMUX_REQ_TIM17_CH1 /*!< DMAMUX TIM17 CH1 request */
|
||||
#define DMA_REQUEST_TIM17_UP LL_DMAMUX_REQ_TIM17_UP /*!< DMAMUX TIM17 UP request */
|
||||
|
||||
#if defined(AES1)
|
||||
#define DMA_REQUEST_AES1_IN LL_DMAMUX_REQ_AES1_IN /*!< DMAMUX AES1 IN request */
|
||||
#define DMA_REQUEST_AES1_OUT LL_DMAMUX_REQ_AES1_OUT /*!< DMAMUX AES1 OUT request */
|
||||
#endif /* AES1 */
|
||||
|
||||
#define DMA_REQUEST_AES2_IN LL_DMAMUX_REQ_AES2_IN /*!< DMAMUX AES2 IN request */
|
||||
#define DMA_REQUEST_AES2_OUT LL_DMAMUX_REQ_AES2_OUT /*!< DMAMUX AES2 OUT request */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
|
||||
* @{
|
||||
*/
|
||||
#define DMA_PERIPH_TO_MEMORY LL_DMA_DIRECTION_PERIPH_TO_MEMORY /*!< Peripheral to memory direction */
|
||||
#define DMA_MEMORY_TO_PERIPH LL_DMA_DIRECTION_MEMORY_TO_PERIPH /*!< Memory to peripheral direction */
|
||||
#define DMA_MEMORY_TO_MEMORY LL_DMA_DIRECTION_MEMORY_TO_MEMORY /*!< Memory to memory direction */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
|
||||
* @{
|
||||
*/
|
||||
#define DMA_PINC_ENABLE LL_DMA_PERIPH_INCREMENT /*!< Peripheral increment mode Enable */
|
||||
#define DMA_PINC_DISABLE LL_DMA_PERIPH_NOINCREMENT /*!< Peripheral increment mode Disable */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
|
||||
* @{
|
||||
*/
|
||||
#define DMA_MINC_ENABLE LL_DMA_MEMORY_INCREMENT /*!< Memory increment mode Enable */
|
||||
#define DMA_MINC_DISABLE LL_DMA_MEMORY_NOINCREMENT /*!< Memory increment mode Disable */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
|
||||
* @{
|
||||
*/
|
||||
#define DMA_PDATAALIGN_BYTE LL_DMA_PDATAALIGN_BYTE /*!< Peripheral data alignment : Byte */
|
||||
#define DMA_PDATAALIGN_HALFWORD LL_DMA_PDATAALIGN_HALFWORD /*!< Peripheral data alignment : HalfWord */
|
||||
#define DMA_PDATAALIGN_WORD LL_DMA_PDATAALIGN_WORD /*!< Peripheral data alignment : Word */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Memory_data_size DMA Memory data size
|
||||
* @{
|
||||
*/
|
||||
#define DMA_MDATAALIGN_BYTE LL_DMA_MDATAALIGN_BYTE /*!< Memory data alignment : Byte */
|
||||
#define DMA_MDATAALIGN_HALFWORD LL_DMA_MDATAALIGN_HALFWORD /*!< Memory data alignment : HalfWord */
|
||||
#define DMA_MDATAALIGN_WORD LL_DMA_MDATAALIGN_WORD /*!< Memory data alignment : Word */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_mode DMA mode
|
||||
* @{
|
||||
*/
|
||||
#define DMA_NORMAL LL_DMA_MODE_NORMAL /*!< Normal mode */
|
||||
#define DMA_CIRCULAR LL_DMA_MODE_CIRCULAR /*!< Circular mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Priority_level DMA Priority level
|
||||
* @{
|
||||
*/
|
||||
#define DMA_PRIORITY_LOW LL_DMA_PRIORITY_LOW /*!< Priority level : Low */
|
||||
#define DMA_PRIORITY_MEDIUM LL_DMA_PRIORITY_MEDIUM /*!< Priority level : Medium */
|
||||
#define DMA_PRIORITY_HIGH LL_DMA_PRIORITY_HIGH /*!< Priority level : High */
|
||||
#define DMA_PRIORITY_VERY_HIGH LL_DMA_PRIORITY_VERYHIGH /*!< Priority level : Very_High */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
|
||||
* @{
|
||||
*/
|
||||
#define DMA_IT_TC LL_DMA_CCR_TCIE /*!< Transfer complete interrupt */
|
||||
#define DMA_IT_HT LL_DMA_CCR_HTIE /*!< Half Transfer interrupt */
|
||||
#define DMA_IT_TE LL_DMA_CCR_TEIE /*!< Transfer error interrupt */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_flag_definitions DMA flag definitions
|
||||
* @{
|
||||
*/
|
||||
#define DMA_FLAG_GL1 LL_DMA_ISR_GIF1 /*!< Channel 1 global flag */
|
||||
#define DMA_FLAG_TC1 LL_DMA_ISR_TCIF1 /*!< Channel 1 transfer complete flag */
|
||||
#define DMA_FLAG_HT1 LL_DMA_ISR_HTIF1 /*!< Channel 1 half transfer flag */
|
||||
#define DMA_FLAG_TE1 LL_DMA_ISR_TEIF1 /*!< Channel 1 transfer error flag */
|
||||
#define DMA_FLAG_GL2 LL_DMA_ISR_GIF2 /*!< Channel 2 global flag */
|
||||
#define DMA_FLAG_TC2 LL_DMA_ISR_TCIF2 /*!< Channel 2 transfer complete flag */
|
||||
#define DMA_FLAG_HT2 LL_DMA_ISR_HTIF2 /*!< Channel 2 half transfer flag */
|
||||
#define DMA_FLAG_TE2 LL_DMA_ISR_TEIF2 /*!< Channel 2 transfer error flag */
|
||||
#define DMA_FLAG_GL3 LL_DMA_ISR_GIF3 /*!< Channel 3 global flag */
|
||||
#define DMA_FLAG_TC3 LL_DMA_ISR_TCIF3 /*!< Channel 3 transfer complete flag */
|
||||
#define DMA_FLAG_HT3 LL_DMA_ISR_HTIF3 /*!< Channel 3 half transfer flag */
|
||||
#define DMA_FLAG_TE3 LL_DMA_ISR_TEIF3 /*!< Channel 3 transfer error flag */
|
||||
#define DMA_FLAG_GL4 LL_DMA_ISR_GIF4 /*!< Channel 4 global flag */
|
||||
#define DMA_FLAG_TC4 LL_DMA_ISR_TCIF4 /*!< Channel 4 transfer complete flag */
|
||||
#define DMA_FLAG_HT4 LL_DMA_ISR_HTIF4 /*!< Channel 4 half transfer flag */
|
||||
#define DMA_FLAG_TE4 LL_DMA_ISR_TEIF4 /*!< Channel 4 transfer error flag */
|
||||
#define DMA_FLAG_GL5 LL_DMA_ISR_GIF5 /*!< Channel 5 global flag */
|
||||
#define DMA_FLAG_TC5 LL_DMA_ISR_TCIF5 /*!< Channel 5 transfer complete flag */
|
||||
#define DMA_FLAG_HT5 LL_DMA_ISR_HTIF5 /*!< Channel 5 half transfer flag */
|
||||
#define DMA_FLAG_TE5 LL_DMA_ISR_TEIF5 /*!< Channel 5 transfer error flag */
|
||||
#define DMA_FLAG_GL6 LL_DMA_ISR_GIF6 /*!< Channel 6 global flag */
|
||||
#define DMA_FLAG_TC6 LL_DMA_ISR_TCIF6 /*!< Channel 6 transfer complete flag */
|
||||
#define DMA_FLAG_HT6 LL_DMA_ISR_HTIF6 /*!< Channel 6 half transfer flag */
|
||||
#define DMA_FLAG_TE6 LL_DMA_ISR_TEIF6 /*!< Channel 6 transfer error flag */
|
||||
#define DMA_FLAG_GL7 LL_DMA_ISR_GIF7 /*!< Channel 7 global flag */
|
||||
#define DMA_FLAG_TC7 LL_DMA_ISR_TCIF7 /*!< Channel 7 transfer complete flag */
|
||||
#define DMA_FLAG_HT7 LL_DMA_ISR_HTIF7 /*!< Channel 7 half transfer flag */
|
||||
#define DMA_FLAG_TE7 LL_DMA_ISR_TEIF7 /*!< Channel 7 transfer error flag */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/** @defgroup DMA_Exported_Macros DMA Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset DMA handle state.
|
||||
* @param __HANDLE__ DMA handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
|
||||
|
||||
/**
|
||||
* @brief Enable the specified DMA Channel.
|
||||
* @param __HANDLE__ DMA handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN)
|
||||
|
||||
/**
|
||||
* @brief Disable the specified DMA Channel.
|
||||
* @param __HANDLE__ DMA handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR &= ~DMA_CCR_EN)
|
||||
|
||||
|
||||
/* Interrupt & Flag management */
|
||||
|
||||
/**
|
||||
* @brief Return the current DMA Channel transfer complete flag.
|
||||
* @param __HANDLE__ DMA handle
|
||||
* @retval The specified transfer complete flag index.
|
||||
*/
|
||||
|
||||
#if defined(DMA2)
|
||||
#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
|
||||
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TC5 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_TC6 :\
|
||||
DMA_FLAG_TC7)
|
||||
#else
|
||||
#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
|
||||
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
|
||||
DMA_FLAG_TC7)
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Return the current DMA Channel half transfer complete flag.
|
||||
* @param __HANDLE__ DMA handle
|
||||
* @retval The specified half transfer complete flag index.
|
||||
*/
|
||||
#if defined(DMA2)
|
||||
#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
|
||||
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_HT5 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_HT6 :\
|
||||
DMA_FLAG_HT7)
|
||||
#else
|
||||
#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
|
||||
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
|
||||
DMA_FLAG_HT7)
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Return the current DMA Channel transfer error flag.
|
||||
* @param __HANDLE__ DMA handle
|
||||
* @retval The specified transfer error flag index.
|
||||
*/
|
||||
#if defined(DMA2)
|
||||
#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
|
||||
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TE5 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_TE6 :\
|
||||
DMA_FLAG_TE7)
|
||||
#else
|
||||
#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
|
||||
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
|
||||
DMA_FLAG_TE7)
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Return the current DMA Channel Global interrupt flag.
|
||||
* @param __HANDLE__ DMA handle
|
||||
* @retval The specified transfer error flag index.
|
||||
*/
|
||||
#if defined(DMA2)
|
||||
#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\
|
||||
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_ISR_GIF1 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_ISR_GIF1 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_ISR_GIF2 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_ISR_GIF2 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_ISR_GIF3 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_ISR_GIF3 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_ISR_GIF4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_ISR_GIF4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_ISR_GIF5 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_ISR_GIF5 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_ISR_GIF6 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_ISR_GIF6 :\
|
||||
DMA_ISR_GIF7)
|
||||
#else
|
||||
#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\
|
||||
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_ISR_GIF1 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_ISR_GIF2 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_ISR_GIF3 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_ISR_GIF4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_ISR_GIF5 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_ISR_GIF6 :\
|
||||
DMA_ISR_GIF7)
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Get the DMA Channel pending flags.
|
||||
* @param __HANDLE__ DMA handle
|
||||
* @param __FLAG__ Get the specified flag.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DMA_FLAG_TCx: Transfer complete flag
|
||||
* @arg DMA_FLAG_HTx: Half transfer complete flag
|
||||
* @arg DMA_FLAG_TEx: Transfer error flag
|
||||
* @arg DMA_FLAG_GLx: Global interrupt flag
|
||||
* Where x can be from 1 to 7 to select the DMA Channel x flag.
|
||||
* @retval The state of FLAG (SET or RESET).
|
||||
*/
|
||||
#if defined(DMA2)
|
||||
#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel7))? \
|
||||
(DMA2->ISR & (__FLAG__)) : (DMA1->ISR & (__FLAG__)))
|
||||
#else
|
||||
#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (DMA1->ISR & (__FLAG__))
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Clear the DMA Channel pending flags.
|
||||
* @param __HANDLE__ DMA handle
|
||||
* @param __FLAG__ specifies the flag to clear.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DMA_FLAG_TCx: Transfer complete flag
|
||||
* @arg DMA_FLAG_HTx: Half transfer complete flag
|
||||
* @arg DMA_FLAG_TEx: Transfer error flag
|
||||
* @arg DMA_FLAG_GLx: Global interrupt flag
|
||||
* Where x can be from 1 to 7 to select the DMA Channel x flag.
|
||||
* @retval None
|
||||
*/
|
||||
#if defined(DMA2)
|
||||
#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel7))? \
|
||||
(DMA2->IFCR = (__FLAG__)) : (DMA1->IFCR = (__FLAG__)))
|
||||
#else
|
||||
#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR = (__FLAG__))
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enable the specified DMA Channel interrupts.
|
||||
* @param __HANDLE__ DMA handle
|
||||
* @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DMA_IT_TC: Transfer complete interrupt mask
|
||||
* @arg DMA_IT_HT: Half transfer complete interrupt mask
|
||||
* @arg DMA_IT_TE: Transfer error interrupt mask
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Disable the specified DMA Channel interrupts.
|
||||
* @param __HANDLE__ DMA handle
|
||||
* @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DMA_IT_TC: Transfer complete interrupt mask
|
||||
* @arg DMA_IT_HT: Half transfer complete interrupt mask
|
||||
* @arg DMA_IT_TE: Transfer error interrupt mask
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Check whether the specified DMA Channel interrupt is enabled or not.
|
||||
* @param __HANDLE__ DMA handle
|
||||
* @param __INTERRUPT__ specifies the DMA interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DMA_IT_TC: Transfer complete interrupt mask
|
||||
* @arg DMA_IT_HT: Half transfer complete interrupt mask
|
||||
* @arg DMA_IT_TE: Transfer error interrupt mask
|
||||
* @retval The state of DMA_IT (SET or RESET).
|
||||
*/
|
||||
#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CCR & (__INTERRUPT__)))
|
||||
|
||||
/**
|
||||
* @brief Return the number of remaining data units in the current DMA Channel transfer.
|
||||
* @param __HANDLE__ DMA handle
|
||||
* @retval The number of remaining data units in the current DMA Channel transfer.
|
||||
*/
|
||||
#define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Include DMA HAL Extension module */
|
||||
#include "stm32wbxx_hal_dma_ex.h"
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/** @addtogroup DMA_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup DMA_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
/* Initialization and de-initialization functions *****************************/
|
||||
HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
|
||||
HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup DMA_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
/* IO operation functions *****************************************************/
|
||||
HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
|
||||
HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
|
||||
HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
|
||||
HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);
|
||||
HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout);
|
||||
void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
|
||||
HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma));
|
||||
HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup DMA_Exported_Functions_Group3
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral State and Error functions ***************************************/
|
||||
HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
|
||||
uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup DMA_Private_Macros DMA Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
|
||||
((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \
|
||||
((DIRECTION) == DMA_MEMORY_TO_MEMORY))
|
||||
|
||||
#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1U) && ((SIZE) < 0x10000U))
|
||||
|
||||
#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
|
||||
((STATE) == DMA_PINC_DISABLE))
|
||||
|
||||
#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \
|
||||
((STATE) == DMA_MINC_DISABLE))
|
||||
|
||||
|
||||
#define IS_DMA_ALL_REQUEST(REQUEST) ((REQUEST) <= DMA_REQUEST_AES2_OUT)
|
||||
|
||||
#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \
|
||||
((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
|
||||
((SIZE) == DMA_PDATAALIGN_WORD))
|
||||
|
||||
#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \
|
||||
((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
|
||||
((SIZE) == DMA_MDATAALIGN_WORD ))
|
||||
|
||||
#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \
|
||||
((MODE) == DMA_CIRCULAR))
|
||||
|
||||
#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \
|
||||
((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
|
||||
((PRIORITY) == DMA_PRIORITY_HIGH) || \
|
||||
((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32WBxx_HAL_DMA_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -1,265 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32wbxx_hal_dma_ex.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of DMA HAL extension module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32WBxx_HAL_DMA_EX_H
|
||||
#define STM32WBxx_HAL_DMA_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32wbxx_hal_def.h"
|
||||
#include "stm32wbxx_ll_dmamux.h"
|
||||
|
||||
/** @addtogroup STM32WBxx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup DMAEx
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup DMAEx_Exported_Types DMAEx Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief HAL DMA Synchro definition
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @brief HAL DMAMUX Synchronization configuration structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t SyncSignalID; /*!< Specifies the synchronization signal gating the DMA request in periodic mode.
|
||||
This parameter can be a value of @ref DMAEx_DMAMUX_SyncSignalID_selection */
|
||||
|
||||
uint32_t SyncPolarity; /*!< Specifies the polarity of the signal on which the DMA request is synchronized.
|
||||
This parameter can be a value of @ref DMAEx_DMAMUX_SyncPolarity_selection */
|
||||
|
||||
FunctionalState SyncEnable; /*!< Specifies if the synchronization shall be enabled or disabled
|
||||
This parameter can take the value ENABLE or DISABLE*/
|
||||
|
||||
FunctionalState EventEnable; /*!< Specifies if an event shall be generated once the RequestNumber is reached.
|
||||
This parameter can take the value ENABLE or DISABLE */
|
||||
|
||||
uint32_t RequestNumber; /*!< Specifies the number of DMA request that will be authorized after a sync event
|
||||
This parameter must be a number between Min_Data = 1 and Max_Data = 32 */
|
||||
|
||||
|
||||
} HAL_DMA_MuxSyncConfigTypeDef;
|
||||
|
||||
|
||||
/**
|
||||
* @brief HAL DMAMUX request generator parameters structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t SignalID; /*!< Specifies the ID of the signal used for DMAMUX request generator
|
||||
This parameter can be a value of @ref DMAEx_DMAMUX_SignalGeneratorID_selection */
|
||||
|
||||
uint32_t Polarity; /*!< Specifies the polarity of the signal on which the request is generated.
|
||||
This parameter can be a value of @ref DMAEx_DMAMUX_RequestGeneneratorPolarity_selection */
|
||||
|
||||
uint32_t RequestNumber; /*!< Specifies the number of DMA request that will be generated after a signal event
|
||||
This parameter must be a number between Min_Data = 1 and Max_Data = 32 */
|
||||
|
||||
} HAL_DMA_MuxRequestGeneratorConfigTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup DMAEx_Exported_Constants DMAEx Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DMAEx_DMAMUX_SyncSignalID_selection DMAMUX SyncSignalID selection
|
||||
* @{
|
||||
*/
|
||||
#define HAL_DMAMUX1_SYNC_EXTI0 LL_DMAMUX_SYNC_EXTI_LINE0 /*!< Synchronization Signal is EXTI0 IT */
|
||||
#define HAL_DMAMUX1_SYNC_EXTI1 LL_DMAMUX_SYNC_EXTI_LINE1 /*!< Synchronization Signal is EXTI1 IT */
|
||||
#define HAL_DMAMUX1_SYNC_EXTI2 LL_DMAMUX_SYNC_EXTI_LINE2 /*!< Synchronization Signal is EXTI2 IT */
|
||||
#define HAL_DMAMUX1_SYNC_EXTI3 LL_DMAMUX_SYNC_EXTI_LINE3 /*!< Synchronization Signal is EXTI3 IT */
|
||||
#define HAL_DMAMUX1_SYNC_EXTI4 LL_DMAMUX_SYNC_EXTI_LINE4 /*!< Synchronization Signal is EXTI4 IT */
|
||||
#define HAL_DMAMUX1_SYNC_EXTI5 LL_DMAMUX_SYNC_EXTI_LINE5 /*!< Synchronization Signal is EXTI5 IT */
|
||||
#define HAL_DMAMUX1_SYNC_EXTI6 LL_DMAMUX_SYNC_EXTI_LINE6 /*!< Synchronization Signal is EXTI6 IT */
|
||||
#define HAL_DMAMUX1_SYNC_EXTI7 LL_DMAMUX_SYNC_EXTI_LINE7 /*!< Synchronization Signal is EXTI7 IT */
|
||||
#define HAL_DMAMUX1_SYNC_EXTI8 LL_DMAMUX_SYNC_EXTI_LINE8 /*!< Synchronization Signal is EXTI8 IT */
|
||||
#define HAL_DMAMUX1_SYNC_EXTI9 LL_DMAMUX_SYNC_EXTI_LINE9 /*!< Synchronization Signal is EXTI9 IT */
|
||||
#define HAL_DMAMUX1_SYNC_EXTI10 LL_DMAMUX_SYNC_EXTI_LINE10 /*!< Synchronization Signal is EXTI10 IT */
|
||||
#define HAL_DMAMUX1_SYNC_EXTI11 LL_DMAMUX_SYNC_EXTI_LINE11 /*!< Synchronization Signal is EXTI11 IT */
|
||||
#define HAL_DMAMUX1_SYNC_EXTI12 LL_DMAMUX_SYNC_EXTI_LINE12 /*!< Synchronization Signal is EXTI12 IT */
|
||||
#define HAL_DMAMUX1_SYNC_EXTI13 LL_DMAMUX_SYNC_EXTI_LINE13 /*!< Synchronization Signal is EXTI13 IT */
|
||||
#define HAL_DMAMUX1_SYNC_EXTI14 LL_DMAMUX_SYNC_EXTI_LINE14 /*!< Synchronization Signal is EXTI14 IT */
|
||||
#define HAL_DMAMUX1_SYNC_EXTI15 LL_DMAMUX_SYNC_EXTI_LINE15 /*!< Synchronization Signal is EXTI15 IT */
|
||||
#define HAL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT LL_DMAMUX_SYNC_DMAMUX_CH0 /*!< Synchronization Signal is DMAMUX1 Channel0 Event */
|
||||
#define HAL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT LL_DMAMUX_SYNC_DMAMUX_CH1 /*!< Synchronization Signal is DMAMUX1 Channel1 Event */
|
||||
#define HAL_DMAMUX1_SYNC_LPTIM1_OUT LL_DMAMUX_SYNC_LPTIM1_OUT /*!< Synchronization Signal is LPTIM1 OUT */
|
||||
#define HAL_DMAMUX1_SYNC_LPTIM2_OUT LL_DMAMUX_SYNC_LPTIM2_OUT /*!< Synchronization Signal is LPTIM2 OUT */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMAEx_DMAMUX_SyncPolarity_selection DMAMUX SyncPolarity selection
|
||||
* @{
|
||||
*/
|
||||
#define HAL_DMAMUX_SYNC_NO_EVENT LL_DMAMUX_SYNC_NO_EVENT /*!< block synchronization events */
|
||||
#define HAL_DMAMUX_SYNC_RISING LL_DMAMUX_SYNC_POL_RISING /*!< synchronize with rising edge events */
|
||||
#define HAL_DMAMUX_SYNC_FALLING LL_DMAMUX_SYNC_POL_FALLING /*!< synchronize with falling edge events */
|
||||
#define HAL_DMAMUX_SYNC_RISING_FALLING LL_DMAMUX_SYNC_POL_RISING_FALLING /*!< synchronize with rising and falling edge events */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMAEx_DMAMUX_SignalGeneratorID_selection DMAMUX SignalGeneratorID selection
|
||||
* @{
|
||||
*/
|
||||
#define HAL_DMAMUX1_REQ_GEN_EXTI0 LL_DMAMUX_REQ_GEN_EXTI_LINE0 /*!< Request generator Signal is EXTI0 IT */
|
||||
#define HAL_DMAMUX1_REQ_GEN_EXTI1 LL_DMAMUX_REQ_GEN_EXTI_LINE1 /*!< Request generator Signal is EXTI1 IT */
|
||||
#define HAL_DMAMUX1_REQ_GEN_EXTI2 LL_DMAMUX_REQ_GEN_EXTI_LINE2 /*!< Request generator Signal is EXTI2 IT */
|
||||
#define HAL_DMAMUX1_REQ_GEN_EXTI3 LL_DMAMUX_REQ_GEN_EXTI_LINE3 /*!< Request generator Signal is EXTI3 IT */
|
||||
#define HAL_DMAMUX1_REQ_GEN_EXTI4 LL_DMAMUX_REQ_GEN_EXTI_LINE4 /*!< Request generator Signal is EXTI4 IT */
|
||||
#define HAL_DMAMUX1_REQ_GEN_EXTI5 LL_DMAMUX_REQ_GEN_EXTI_LINE5 /*!< Request generator Signal is EXTI5 IT */
|
||||
#define HAL_DMAMUX1_REQ_GEN_EXTI6 LL_DMAMUX_REQ_GEN_EXTI_LINE6 /*!< Request generator Signal is EXTI6 IT */
|
||||
#define HAL_DMAMUX1_REQ_GEN_EXTI7 LL_DMAMUX_REQ_GEN_EXTI_LINE7 /*!< Request generator Signal is EXTI7 IT */
|
||||
#define HAL_DMAMUX1_REQ_GEN_EXTI8 LL_DMAMUX_REQ_GEN_EXTI_LINE8 /*!< Request generator Signal is EXTI8 IT */
|
||||
#define HAL_DMAMUX1_REQ_GEN_EXTI9 LL_DMAMUX_REQ_GEN_EXTI_LINE9 /*!< Request generator Signal is EXTI9 IT */
|
||||
#define HAL_DMAMUX1_REQ_GEN_EXTI10 LL_DMAMUX_REQ_GEN_EXTI_LINE10 /*!< Request generator Signal is EXTI10 IT */
|
||||
#define HAL_DMAMUX1_REQ_GEN_EXTI11 LL_DMAMUX_REQ_GEN_EXTI_LINE11 /*!< Request generator Signal is EXTI11 IT */
|
||||
#define HAL_DMAMUX1_REQ_GEN_EXTI12 LL_DMAMUX_REQ_GEN_EXTI_LINE12 /*!< Request generator Signal is EXTI12 IT */
|
||||
#define HAL_DMAMUX1_REQ_GEN_EXTI13 LL_DMAMUX_REQ_GEN_EXTI_LINE13 /*!< Request generator Signal is EXTI13 IT */
|
||||
#define HAL_DMAMUX1_REQ_GEN_EXTI14 LL_DMAMUX_REQ_GEN_EXTI_LINE14 /*!< Request generator Signal is EXTI14 IT */
|
||||
#define HAL_DMAMUX1_REQ_GEN_EXTI15 LL_DMAMUX_REQ_GEN_EXTI_LINE15 /*!< Request generator Signal is EXTI15 IT */
|
||||
#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT LL_DMAMUX_REQ_GEN_DMAMUX_CH0 /*!< Request generator Signal is DMAMUX1 Channel0 Event */
|
||||
#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT LL_DMAMUX_REQ_GEN_DMAMUX_CH1 /*!< Request generator Signal is DMAMUX1 Channel1 Event */
|
||||
#define HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT LL_DMAMUX_REQ_GEN_LPTIM1_OUT /*!< Request generator Signal is LPTIM1 OUT */
|
||||
#define HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT LL_DMAMUX_REQ_GEN_LPTIM2_OUT /*!< Request generator Signal is LPTIM2 OUT */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMAEx_DMAMUX_RequestGeneneratorPolarity_selection DMAMUX RequestGeneneratorPolarity selection
|
||||
* @{
|
||||
*/
|
||||
#define HAL_DMAMUX_REQ_GEN_NO_EVENT LL_DMAMUX_REQ_GEN_NO_EVENT /*!< block request generator events */
|
||||
#define HAL_DMAMUX_REQ_GEN_RISING LL_DMAMUX_REQ_GEN_POL_RISING /*!< generate request on rising edge events */
|
||||
#define HAL_DMAMUX_REQ_GEN_FALLING LL_DMAMUX_REQ_GEN_POL_FALLING /*!< generate request on falling edge events */
|
||||
#define HAL_DMAMUX_REQ_GEN_RISING_FALLING LL_DMAMUX_REQ_GEN_POL_RISING_FALLING /*!< generate request on rising and falling edge events */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup DMAEx_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* IO operation functions *****************************************************/
|
||||
/** @addtogroup DMAEx_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* ------------------------- REQUEST -----------------------------------------*/
|
||||
HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator(DMA_HandleTypeDef *hdma,
|
||||
HAL_DMA_MuxRequestGeneratorConfigTypeDef *pRequestGeneratorConfig);
|
||||
HAL_StatusTypeDef HAL_DMAEx_EnableMuxRequestGenerator(DMA_HandleTypeDef *hdma);
|
||||
HAL_StatusTypeDef HAL_DMAEx_DisableMuxRequestGenerator(DMA_HandleTypeDef *hdma);
|
||||
/* -------------------------------------------------------------------------- */
|
||||
|
||||
/* ------------------------- SYNCHRO -----------------------------------------*/
|
||||
HAL_StatusTypeDef HAL_DMAEx_ConfigMuxSync(DMA_HandleTypeDef *hdma, HAL_DMA_MuxSyncConfigTypeDef *pSyncConfig);
|
||||
/* -------------------------------------------------------------------------- */
|
||||
|
||||
void HAL_DMAEx_MUX_IRQHandler(DMA_HandleTypeDef *hdma);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup DMAEx_Private_Macros DMAEx Private Macros
|
||||
* @brief DMAEx private macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_DMAMUX_SYNC_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX1_SYNC_LPTIM2_OUT)
|
||||
|
||||
#define IS_DMAMUX_SYNC_REQUEST_NUMBER(REQUEST_NUMBER) (((REQUEST_NUMBER) > 0U) && ((REQUEST_NUMBER) <= 32U))
|
||||
|
||||
#define IS_DMAMUX_SYNC_POLARITY(POLARITY) (((POLARITY) == HAL_DMAMUX_SYNC_NO_EVENT) || \
|
||||
((POLARITY) == HAL_DMAMUX_SYNC_RISING) || \
|
||||
((POLARITY) == HAL_DMAMUX_SYNC_FALLING) || \
|
||||
((POLARITY) == HAL_DMAMUX_SYNC_RISING_FALLING))
|
||||
|
||||
#define IS_DMAMUX_SYNC_STATE(SYNC) (((SYNC) == DISABLE) || ((SYNC) == ENABLE))
|
||||
|
||||
#define IS_DMAMUX_SYNC_EVENT(EVENT) (((EVENT) == DISABLE) || \
|
||||
((EVENT) == ENABLE))
|
||||
|
||||
#define IS_DMAMUX_REQUEST_GEN_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT)
|
||||
|
||||
#define IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER(REQUEST_NUMBER) (((REQUEST_NUMBER) > 0U) && ((REQUEST_NUMBER) <= 32U))
|
||||
|
||||
#define IS_DMAMUX_REQUEST_GEN_POLARITY(POLARITY) (((POLARITY) == HAL_DMAMUX_REQ_GEN_NO_EVENT) || \
|
||||
((POLARITY) == HAL_DMAMUX_REQ_GEN_RISING) || \
|
||||
((POLARITY) == HAL_DMAMUX_REQ_GEN_FALLING) || \
|
||||
((POLARITY) == HAL_DMAMUX_REQ_GEN_RISING_FALLING))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32WBxx_HAL_DMA_EX_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -1,366 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32wbxx_hal_exti.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of EXTI HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32WBxx_HAL_EXTI_H
|
||||
#define STM32WBxx_HAL_EXTI_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32wbxx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32WBxx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI EXTI
|
||||
* @brief EXTI HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup EXTI_Exported_Types EXTI Exported Types
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_EXTI_COMMON_CB_ID = 0x00U,
|
||||
} EXTI_CallbackIDTypeDef;
|
||||
|
||||
|
||||
/**
|
||||
* @brief EXTI Handle structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Line; /*!< Exti line number */
|
||||
void (* PendingCallback)(void); /*!< Exti pending callback */
|
||||
} EXTI_HandleTypeDef;
|
||||
|
||||
/**
|
||||
* @brief EXTI Configuration structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Line; /*!< The Exti line to be configured. This parameter
|
||||
can be a value of @ref EXTI_Line */
|
||||
uint32_t Mode; /*!< The Exit Mode to be configured for a core.
|
||||
This parameter can be a combination of @ref EXTI_Mode */
|
||||
uint32_t Trigger; /*!< The Exti Trigger to be configured. This parameter
|
||||
can be a value of @ref EXTI_Trigger */
|
||||
uint32_t GPIOSel; /*!< The Exti GPIO multiplexer selection to be configured.
|
||||
This parameter is only possible for line 0 to 15. It
|
||||
can be a value of @ref EXTI_GPIOSel */
|
||||
} EXTI_ConfigTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup EXTI_Exported_Constants EXTI Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI_Line EXTI Line
|
||||
* @{
|
||||
*/
|
||||
#define EXTI_LINE_0 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | 0x00u)
|
||||
#define EXTI_LINE_1 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | 0x01u)
|
||||
#define EXTI_LINE_2 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | 0x02u)
|
||||
#define EXTI_LINE_3 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | 0x03u)
|
||||
#define EXTI_LINE_4 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | 0x04u)
|
||||
#define EXTI_LINE_5 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | 0x05u)
|
||||
#define EXTI_LINE_6 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | 0x06u)
|
||||
#define EXTI_LINE_7 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | 0x07u)
|
||||
#define EXTI_LINE_8 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | 0x08u)
|
||||
#define EXTI_LINE_9 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | 0x09u)
|
||||
#define EXTI_LINE_10 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | 0x0Au)
|
||||
#define EXTI_LINE_11 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | 0x0Bu)
|
||||
#define EXTI_LINE_12 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | 0x0Cu)
|
||||
#define EXTI_LINE_13 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | 0x0Du)
|
||||
#define EXTI_LINE_14 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | 0x0Eu)
|
||||
#define EXTI_LINE_15 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | 0x0Fu)
|
||||
#define EXTI_LINE_16 (EXTI_CONFIG | EXTI_REG1 | 0x10u)
|
||||
#define EXTI_LINE_17 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG1 | 0x11u)
|
||||
#define EXTI_LINE_18 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG1 | 0x12u)
|
||||
#define EXTI_LINE_19 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG1 | 0x13u)
|
||||
#if defined (STM32WB55xx) || defined (STM32WB5Mxx) || defined (STM32WB35xx) || defined (STM32WB15xx)
|
||||
#define EXTI_LINE_20 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG1 | 0x14u)
|
||||
#else
|
||||
#define EXTI_LINE_20 (EXTI_RESERVED | EXTI_REG1 | 0x14u)
|
||||
#endif
|
||||
#if defined (STM32WB55xx) || defined (STM32WB5Mxx) || defined (STM32WB35xx)
|
||||
#define EXTI_LINE_21 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG1 | 0x15u)
|
||||
#else
|
||||
#define EXTI_LINE_21 (EXTI_RESERVED | EXTI_REG1 | 0x15u)
|
||||
#endif
|
||||
#define EXTI_LINE_22 (EXTI_DIRECT | EXTI_REG1 | 0x16u)
|
||||
#if defined (STM32WB55xx) || defined (STM32WB5Mxx) || defined (STM32WB35xx)
|
||||
#define EXTI_LINE_23 (EXTI_DIRECT | EXTI_REG1 | 0x17u)
|
||||
#else
|
||||
#define EXTI_LINE_23 (EXTI_RESERVED | EXTI_REG1 | 0x17u)
|
||||
#endif
|
||||
#define EXTI_LINE_24 (EXTI_DIRECT | EXTI_REG1 | 0x18u)
|
||||
#if defined (STM32WB55xx) || defined (STM32WB5Mxx) || defined (STM32WB35xx) || defined (STM32WB15xx)
|
||||
#define EXTI_LINE_25 (EXTI_DIRECT | EXTI_REG1 | 0x19u)
|
||||
#else
|
||||
#define EXTI_LINE_25 (EXTI_RESERVED | EXTI_REG1 | 0x19u)
|
||||
#endif
|
||||
#define EXTI_LINE_26 (EXTI_RESERVED | EXTI_REG1 | 0x1Au)
|
||||
#define EXTI_LINE_27 (EXTI_RESERVED | EXTI_REG1 | 0x1Bu)
|
||||
#if defined (STM32WB55xx) || defined (STM32WB5Mxx) || defined (STM32WB35xx)
|
||||
#define EXTI_LINE_28 (EXTI_DIRECT | EXTI_REG1 | 0x1Cu)
|
||||
#else
|
||||
#define EXTI_LINE_28 (EXTI_RESERVED | EXTI_REG1 | 0x1Cu)
|
||||
#endif
|
||||
#define EXTI_LINE_29 (EXTI_DIRECT | EXTI_REG1 | 0x1Du)
|
||||
#define EXTI_LINE_30 (EXTI_DIRECT | EXTI_REG1 | 0x1Eu)
|
||||
#if defined (STM32WB55xx) || defined (STM32WB5Mxx) || defined (STM32WB35xx) || defined (STM32WB15xx)
|
||||
#define EXTI_LINE_31 (EXTI_CONFIG | EXTI_REG1 | 0x1Fu)
|
||||
#else
|
||||
#define EXTI_LINE_31 (EXTI_RESERVED | EXTI_REG1 | 0x1Fu)
|
||||
#endif
|
||||
#define EXTI_LINE_32 (EXTI_RESERVED | EXTI_REG2 | 0x00u)
|
||||
#define EXTI_LINE_33 (EXTI_CONFIG | EXTI_REG2 | 0x01u)
|
||||
#define EXTI_LINE_34 (EXTI_RESERVED | EXTI_REG2 | 0x02u)
|
||||
#define EXTI_LINE_35 (EXTI_RESERVED | EXTI_REG2 | 0x03u)
|
||||
#define EXTI_LINE_36 (EXTI_DIRECT | EXTI_REG2 | 0x04u)
|
||||
#define EXTI_LINE_37 (EXTI_DIRECT | EXTI_REG2 | 0x05u)
|
||||
#define EXTI_LINE_38 (EXTI_DIRECT | EXTI_REG2 | 0x06u)
|
||||
#define EXTI_LINE_39 (EXTI_DIRECT | EXTI_REG2 | 0x07u)
|
||||
#define EXTI_LINE_40 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG2 | 0x08u)
|
||||
#define EXTI_LINE_41 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG2 | 0x09u)
|
||||
#define EXTI_LINE_42 (EXTI_DIRECT | EXTI_REG2 | 0x0Au)
|
||||
#if defined (STM32WB55xx) || defined (STM32WB5Mxx)
|
||||
#define EXTI_LINE_43 (EXTI_DIRECT | EXTI_REG2 | 0x0Bu)
|
||||
#else
|
||||
#define EXTI_LINE_43 (EXTI_RESERVED | EXTI_REG2 | 0x0Bu)
|
||||
#endif
|
||||
#define EXTI_LINE_44 (EXTI_DIRECT | EXTI_REG2 | 0x0Cu)
|
||||
#define EXTI_LINE_45 (EXTI_DIRECT | EXTI_REG2 | 0x0Du)
|
||||
#if defined (STM32WB55xx) || defined (STM32WB5Mxx) || defined (STM32WB50xx) || defined (STM32WB35xx) || defined (STM32WB30xx)
|
||||
#define EXTI_LINE_46 (EXTI_DIRECT | EXTI_REG2 | 0x0Eu)
|
||||
#else
|
||||
#define EXTI_LINE_46 (EXTI_RESERVED | EXTI_REG2 | 0x0Eu)
|
||||
#endif
|
||||
#define EXTI_LINE_47 (EXTI_RESERVED | EXTI_REG2 | 0x0Fu)
|
||||
#define EXTI_LINE_48 (EXTI_DIRECT | EXTI_REG2 | 0x10u)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI_Mode EXTI Mode
|
||||
* @{
|
||||
*/
|
||||
#define EXTI_MODE_NONE 0x00000000u
|
||||
#define EXTI_MODE_INTERRUPT 0x00000001u
|
||||
#define EXTI_MODE_EVENT 0x00000002u
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI_Trigger EXTI Trigger
|
||||
* @{
|
||||
*/
|
||||
#define EXTI_TRIGGER_NONE 0x00000000u
|
||||
#define EXTI_TRIGGER_RISING 0x00000001u
|
||||
#define EXTI_TRIGGER_FALLING 0x00000002u
|
||||
#define EXTI_TRIGGER_RISING_FALLING (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI_GPIOSel EXTI GPIOSel
|
||||
* @brief
|
||||
* @{
|
||||
*/
|
||||
#define EXTI_GPIOA 0x00000000u
|
||||
#define EXTI_GPIOB 0x00000001u
|
||||
#define EXTI_GPIOC 0x00000002u
|
||||
#if defined (STM32WB55xx) || defined (STM32WB5Mxx)
|
||||
#define EXTI_GPIOD 0x00000003u
|
||||
#endif
|
||||
#define EXTI_GPIOE 0x00000004u
|
||||
#define EXTI_GPIOH 0x00000007u
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup EXTI_Exported_Macros EXTI Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private constants --------------------------------------------------------*/
|
||||
/** @defgroup EXTI_Private_Constants EXTI Private Constants
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief EXTI Line property definition
|
||||
*/
|
||||
#define EXTI_PROPERTY_SHIFT 24u
|
||||
#define EXTI_DIRECT (0x01uL << EXTI_PROPERTY_SHIFT)
|
||||
#define EXTI_CONFIG (0x02uL << EXTI_PROPERTY_SHIFT)
|
||||
#define EXTI_GPIO ((0x04uL << EXTI_PROPERTY_SHIFT) | EXTI_CONFIG)
|
||||
#define EXTI_RESERVED (0x08uL << EXTI_PROPERTY_SHIFT)
|
||||
#define EXTI_PROPERTY_MASK (EXTI_DIRECT | EXTI_CONFIG | EXTI_GPIO)
|
||||
|
||||
/**
|
||||
* @brief EXTI Event presence definition
|
||||
*/
|
||||
#define EXTI_EVENT_PRESENCE_SHIFT 28u
|
||||
#define EXTI_EVENT (0x01uL << EXTI_EVENT_PRESENCE_SHIFT)
|
||||
#define EXTI_EVENT_PRESENCE_MASK (EXTI_EVENT)
|
||||
|
||||
/**
|
||||
* @brief EXTI Register and bit usage
|
||||
*/
|
||||
#define EXTI_REG_SHIFT 16u
|
||||
#define EXTI_REG1 (0x00uL << EXTI_REG_SHIFT)
|
||||
#define EXTI_REG2 (0x01uL << EXTI_REG_SHIFT)
|
||||
#define EXTI_REG_MASK (EXTI_REG1 | EXTI_REG2)
|
||||
#define EXTI_PIN_MASK 0x0000001Fu
|
||||
|
||||
/**
|
||||
* @brief EXTI Mask for interrupt & event mode
|
||||
*/
|
||||
#define EXTI_MODE_MASK (EXTI_MODE_EVENT | EXTI_MODE_INTERRUPT)
|
||||
|
||||
/**
|
||||
* @brief EXTI Mask for trigger possibilities
|
||||
*/
|
||||
#define EXTI_TRIGGER_MASK (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)
|
||||
|
||||
/**
|
||||
* @brief EXTI Line number
|
||||
*/
|
||||
#define EXTI_LINE_NB 49uL
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup EXTI_Private_Macros EXTI Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_EXTI_LINE(__EXTI_LINE__) ((((__EXTI_LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_EVENT_PRESENCE_MASK | EXTI_REG_MASK | EXTI_PIN_MASK)) == 0x00u) && \
|
||||
((((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_DIRECT) || \
|
||||
(((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG) || \
|
||||
(((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO)) && \
|
||||
(((__EXTI_LINE__) & (EXTI_REG_MASK | EXTI_PIN_MASK)) < \
|
||||
(((EXTI_LINE_NB / 32u) << EXTI_REG_SHIFT) | (EXTI_LINE_NB % 32u))))
|
||||
|
||||
#define IS_EXTI_MODE(__EXTI_LINE__) ((((__EXTI_LINE__) & EXTI_MODE_MASK) != 0x00u) && \
|
||||
(((__EXTI_LINE__) & ~EXTI_MODE_MASK) == 0x00u))
|
||||
|
||||
#define IS_EXTI_TRIGGER(__EXTI_LINE__) (((__EXTI_LINE__) & ~EXTI_TRIGGER_MASK) == 0x00u)
|
||||
|
||||
#define IS_EXTI_PENDING_EDGE(__EXTI_LINE__) ((__EXTI_LINE__) == EXTI_TRIGGER_RISING_FALLING)
|
||||
|
||||
#define IS_EXTI_CONFIG_LINE(__EXTI_LINE__) (((__EXTI_LINE__) & EXTI_CONFIG) != 0x00u)
|
||||
|
||||
#if defined (STM32WB55xx) || defined (STM32WB5Mxx)
|
||||
#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \
|
||||
((__PORT__) == EXTI_GPIOB) || \
|
||||
((__PORT__) == EXTI_GPIOC) || \
|
||||
((__PORT__) == EXTI_GPIOD) || \
|
||||
((__PORT__) == EXTI_GPIOE) || \
|
||||
((__PORT__) == EXTI_GPIOH))
|
||||
#else
|
||||
#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \
|
||||
((__PORT__) == EXTI_GPIOB) || \
|
||||
((__PORT__) == EXTI_GPIOC) || \
|
||||
((__PORT__) == EXTI_GPIOE) || \
|
||||
((__PORT__) == EXTI_GPIOH))
|
||||
#endif
|
||||
|
||||
#define IS_EXTI_GPIO_PIN(__PIN__) ((__PIN__) < 16u)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup EXTI_Exported_Functions EXTI Exported Functions
|
||||
* @brief EXTI Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI_Exported_Functions_Group1 Configuration functions
|
||||
* @brief Configuration functions
|
||||
* @{
|
||||
*/
|
||||
/* Configuration functions ****************************************************/
|
||||
HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig);
|
||||
HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig);
|
||||
HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti);
|
||||
HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void));
|
||||
HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI_Exported_Functions_Group2 IO operation functions
|
||||
* @brief IO operation functions
|
||||
* @{
|
||||
*/
|
||||
/* IO operation functions *****************************************************/
|
||||
void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti);
|
||||
uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge);
|
||||
void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge);
|
||||
void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32WBxx_HAL_EXTI_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -1,990 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32wbxx_hal_flash.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of FLASH HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32WBxx_HAL_FLASH_H
|
||||
#define STM32WBxx_HAL_FLASH_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32wbxx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32WBxx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup FLASH
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup FLASH_Exported_Types FLASH Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief FLASH Erase structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t TypeErase; /*!< Page erase.
|
||||
This parameter can be a value of @ref FLASH_TYPE_ERASE */
|
||||
uint32_t Page; /*!< Initial Flash page to erase when page erase is enabled
|
||||
This parameter must be a value between 0 and (FLASH_PAGE_NB - 1) */
|
||||
uint32_t NbPages; /*!< Number of pages to be erased.
|
||||
This parameter must be a value between 1 and (FLASH_PAGE_NB - value of initial page)*/
|
||||
} FLASH_EraseInitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief FLASH Option Bytes Program structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t OptionType; /*!< Option byte to be configured.
|
||||
This parameter can be a combination of the values of @ref FLASH_OB_TYPE */
|
||||
uint32_t WRPArea; /*!< Write protection area to be programmed (used for OPTIONBYTE_WRP).
|
||||
Only one WRP area could be programmed at the same time.
|
||||
This parameter can be value of @ref FLASH_OB_WRP_AREA */
|
||||
uint32_t WRPStartOffset; /*!< Write protection start offset (used for OPTIONBYTE_WRP).
|
||||
This parameter must be a value between 0 and (max number of pages - 1) */
|
||||
uint32_t WRPEndOffset; /*!< Write protection end offset (used for OPTIONBYTE_WRP).
|
||||
This parameter must be a value between WRPStartOffset and (max number of pages - 1) */
|
||||
uint32_t RDPLevel; /*!< Set the read protection level (used for OPTIONBYTE_RDP).
|
||||
This parameter can be a value of @ref FLASH_OB_READ_PROTECTION */
|
||||
uint32_t UserType; /*!< User option byte(s) to be configured (used for OPTIONBYTE_USER).
|
||||
This parameter can be a combination of @ref FLASH_OB_USER_TYPE */
|
||||
uint32_t UserConfig; /*!< Value of the user option byte (used for OPTIONBYTE_USER).
|
||||
This parameter can be a combination of the values of
|
||||
@ref FLASH_OB_USER_AGC_TRIM, @ref FLASH_OB_USER_BOR_LEVEL
|
||||
@ref FLASH_OB_USER_RESET_CONFIG(*), @ref FLASH_OB_USER_INPUT_RESET_HOLDER(*)
|
||||
@ref FLASH_OB_USER_nRST_STOP, @ref FLASH_OB_USER_nRST_STANDBY,
|
||||
@ref FLASH_OB_USER_nRST_SHUTDOWN, @ref FLASH_OB_USER_IWDG_SW,
|
||||
@ref FLASH_OB_USER_IWDG_STOP, @ref FLASH_OB_USER_IWDG_STANDBY,
|
||||
@ref FLASH_OB_USER_WWDG_SW, @ref FLASH_OB_USER_nBOOT1,
|
||||
@ref FLASH_OB_USER_SRAM2PE, @ref FLASH_OB_USER_SRAM2RST,
|
||||
@ref FLASH_OB_USER_nSWBOOT0, @ref FLASH_OB_USER_nBOOT0 */
|
||||
uint32_t PCROPConfig; /*!< Configuration of the PCROP (used for OPTIONBYTE_PCROP).
|
||||
This parameter must be a combination of values of @ref FLASH_OB_PCROP_ZONE
|
||||
and @ref FLASH_OB_PCROP_RDP */
|
||||
uint32_t PCROP1AStartAddr; /*!< PCROP Zone A Start address (used for OPTIONBYTE_PCROP). It represents first address of start block
|
||||
to protect. Make sure this parameter is multiple of PCROP granularity */
|
||||
uint32_t PCROP1AEndAddr; /*!< PCROP Zone A End address (used for OPTIONBYTE_PCROP). It represents first address of end block
|
||||
to protect. Make sure this parameter is multiple of PCROP granularity */
|
||||
uint32_t PCROP1BStartAddr; /*!< PCROP Zone B Start address (used for OPTIONBYTE_PCROP). It represents first address of start block
|
||||
to protect. Make sure this parameter is multiple of PCROP granularity */
|
||||
uint32_t PCROP1BEndAddr; /*!< PCROP Zone B End address (used for OPTIONBYTE_PCROP). It represents first address of end block
|
||||
to protect. Make sure this parameter is multiple of PCROP granularity */
|
||||
uint32_t SecureFlashStartAddr; /*!< Secure Flash start address (used for OPTIONBYTE_SECURE_MODE).
|
||||
This parameter must be a value between begin and end of Flash bank
|
||||
=> Contains the start address of the first 4kB page of the secure Flash area */
|
||||
uint32_t SecureRAM2aStartAddr; /*!< Secure Backup RAM2a start address (used for OPTIONBYTE_SECURE_MODE).
|
||||
This parameter can be a value of @ref FLASH_SRAM2A_ADDRESS_RANGE */
|
||||
uint32_t SecureRAM2bStartAddr; /*!< Secure non-Backup RAM2b start address (used for OPTIONBYTE_SECURE_MODE)
|
||||
This parameter can be a value of @ref FLASH_SRAM2B_ADDRESS_RANGE */
|
||||
uint32_t SecureMode; /*!< Secure mode activated or desactivated.
|
||||
This parameter can be a value of @ref FLASH_OB_SECURITY_MODE */
|
||||
uint32_t C2BootRegion; /*!< CPU2 Secure Boot memory region(used for OPTIONBYTE_C2_BOOT_VECT).
|
||||
This parameter can be a value of @ref FLASH_C2_OB_BOOT_REGION */
|
||||
uint32_t C2SecureBootVectAddr; /*!< CPU2 Secure Boot reset vector (used for OPTIONBYTE_C2_BOOT_VECT).
|
||||
This parameter contains the CPU2 boot reset start address within
|
||||
the selected memory region. Make sure this parameter is word aligned. */
|
||||
uint32_t IPCCdataBufAddr; /*!< IPCC mailbox data buffer base address (used for OPTIONBYTE_IPCC_BUF_ADDR).
|
||||
This parameter contains the IPCC mailbox data buffer start address area in SRAM2.
|
||||
Make sure this parameter is double-word aligned. */
|
||||
} FLASH_OBProgramInitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief FLASH handle Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
HAL_LockTypeDef Lock; /* FLASH locking object */
|
||||
uint32_t ErrorCode; /* FLASH error code */
|
||||
uint32_t ProcedureOnGoing; /* Internal variable to indicate which procedure is ongoing or not in IT context */
|
||||
uint32_t Address; /* Internal variable to save address selected for program in IT context */
|
||||
uint32_t Page; /* Internal variable to define the current page which is erasing in IT context */
|
||||
uint32_t NbPagesToErase; /* Internal variable to save the remaining pages to erase in IT context */
|
||||
} FLASH_ProcessTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup FLASH_Exported_Constants FLASH Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_KEYS FLASH Keys
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_KEY1 0x45670123U /*!< Flash key1 */
|
||||
#define FLASH_KEY2 0xCDEF89ABU /*!< Flash key2: used with FLASH_KEY1
|
||||
to unlock the FLASH registers access */
|
||||
|
||||
#define FLASH_OPTKEY1 0x08192A3BU /*!< Flash option byte key1 */
|
||||
#define FLASH_OPTKEY2 0x4C5D6E7FU /*!< Flash option byte key2: used with FLASH_OPTKEY1
|
||||
to allow option bytes operations */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_LATENCY FLASH Latency
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS /*!< FLASH Zero wait state */
|
||||
#define FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS /*!< FLASH One wait state */
|
||||
#define FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS /*!< FLASH Two wait states */
|
||||
#define FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS /*!< FLASH Three wait states */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_FLAGS FLASH Flags Definition
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_FLAG_EOP FLASH_SR_EOP /*!< FLASH End of operation flag */
|
||||
#define FLASH_FLAG_OPERR FLASH_SR_OPERR /*!< FLASH Operation error flag */
|
||||
#define FLASH_FLAG_PROGERR FLASH_SR_PROGERR /*!< FLASH Programming error flag */
|
||||
#define FLASH_FLAG_WRPERR FLASH_SR_WRPERR /*!< FLASH Write protection error flag */
|
||||
#define FLASH_FLAG_PGAERR FLASH_SR_PGAERR /*!< FLASH Programming alignment error flag */
|
||||
#define FLASH_FLAG_SIZERR FLASH_SR_SIZERR /*!< FLASH Size error flag */
|
||||
#define FLASH_FLAG_PGSERR FLASH_SR_PGSERR /*!< FLASH Programming sequence error flag */
|
||||
#define FLASH_FLAG_MISERR FLASH_SR_MISERR /*!< FLASH Fast programming data miss error flag */
|
||||
#define FLASH_FLAG_FASTERR FLASH_SR_FASTERR /*!< FLASH Fast programming error flag */
|
||||
#define FLASH_FLAG_OPTNV FLASH_SR_OPTNV /*!< FLASH User Option OPTVAL indication */
|
||||
#define FLASH_FLAG_RDERR FLASH_SR_RDERR /*!< FLASH PCROP read error flag */
|
||||
#define FLASH_FLAG_OPTVERR FLASH_SR_OPTVERR /*!< FLASH Option validity error flag */
|
||||
#define FLASH_FLAG_BSY FLASH_SR_BSY /*!< FLASH Busy flag */
|
||||
#define FLASH_FLAG_CFGBSY FLASH_SR_CFGBSY /*!< FLASH Programming/erase configuration busy */
|
||||
#define FLASH_FLAG_PESD FLASH_SR_PESD /*!< FLASH Programming/erase operation suspended */
|
||||
#define FLASH_FLAG_ECCC FLASH_ECCR_ECCC /*!< FLASH ECC correction */
|
||||
#define FLASH_FLAG_ECCD FLASH_ECCR_ECCD /*!< FLASH ECC detection */
|
||||
|
||||
#define FLASH_FLAG_SR_ERRORS (FLASH_FLAG_OPERR | FLASH_FLAG_PROGERR | FLASH_FLAG_WRPERR | \
|
||||
FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR | FLASH_FLAG_PGSERR | \
|
||||
FLASH_FLAG_MISERR | FLASH_FLAG_FASTERR | FLASH_FLAG_RDERR | \
|
||||
FLASH_FLAG_OPTVERR) /*!< All SR error flags */
|
||||
|
||||
#define FLASH_FLAG_ECCR_ERRORS (FLASH_FLAG_ECCC | FLASH_FLAG_ECCD)
|
||||
|
||||
#define FLASH_FLAG_ALL_ERRORS (FLASH_FLAG_SR_ERRORS | FLASH_FLAG_ECCR_ERRORS)
|
||||
|
||||
/** @defgroup FLASH_INTERRUPT_DEFINITION FLASH Interrupts Definition
|
||||
* @brief FLASH Interrupt definition
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_IT_EOP FLASH_CR_EOPIE /*!< End of FLASH Operation Interrupt source */
|
||||
#define FLASH_IT_OPERR FLASH_CR_ERRIE /*!< Error Interrupt source */
|
||||
#define FLASH_IT_RDERR FLASH_CR_RDERRIE /*!< PCROP Read Error Interrupt source */
|
||||
#define FLASH_IT_ECCC (FLASH_ECCR_ECCCIE >> FLASH_ECCR_ECCCIE_Pos) /*!< ECC Correction Interrupt source */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_ERROR FLASH Error
|
||||
* @{
|
||||
*/
|
||||
#define HAL_FLASH_ERROR_NONE 0x00000000U
|
||||
#define HAL_FLASH_ERROR_OP FLASH_FLAG_OPERR
|
||||
#define HAL_FLASH_ERROR_PROG FLASH_FLAG_PROGERR
|
||||
#define HAL_FLASH_ERROR_WRP FLASH_FLAG_WRPERR
|
||||
#define HAL_FLASH_ERROR_PGA FLASH_FLAG_PGAERR
|
||||
#define HAL_FLASH_ERROR_SIZ FLASH_FLAG_SIZERR
|
||||
#define HAL_FLASH_ERROR_PGS FLASH_FLAG_PGSERR
|
||||
#define HAL_FLASH_ERROR_MIS FLASH_FLAG_MISERR
|
||||
#define HAL_FLASH_ERROR_FAST FLASH_FLAG_FASTERR
|
||||
#define HAL_FLASH_ERROR_RD FLASH_FLAG_RDERR
|
||||
#define HAL_FLASH_ERROR_OPTV FLASH_FLAG_OPTVERR
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_TYPE_ERASE FLASH Erase Type
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_TYPEERASE_PAGES FLASH_CR_PER /*!< Pages erase only*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_TYPE_PROGRAM FLASH Program Type
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_TYPEPROGRAM_DOUBLEWORD FLASH_CR_PG /*!< Program a double-word (64-bit) at a specified address.*/
|
||||
#define FLASH_TYPEPROGRAM_FAST FLASH_CR_FSTPG /*!< Fast program a 64 row double-word (64-bit) at a specified address.
|
||||
And another 64 row double-word (64-bit) will be programmed */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_OB_TYPE FLASH Option Bytes Type
|
||||
* @{
|
||||
*/
|
||||
#define OPTIONBYTE_WRP 0x00000001U /*!< WRP option byte configuration */
|
||||
#define OPTIONBYTE_RDP 0x00000002U /*!< RDP option byte configuration */
|
||||
#define OPTIONBYTE_USER 0x00000004U /*!< User option byte configuration */
|
||||
#define OPTIONBYTE_PCROP 0x00000008U /*!< PCROP option byte configuration */
|
||||
#define OPTIONBYTE_IPCC_BUF_ADDR 0x00000010U /*!< IPCC mailbox buffer address configuration */
|
||||
#define OPTIONBYTE_C2_BOOT_VECT 0x00000100U /*!< CPU2 Secure Boot reset vector */
|
||||
#define OPTIONBYTE_SECURE_MODE 0x00000200U /*!< Secure mode on activated or not */
|
||||
#define OPTIONBYTE_ALL (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | \
|
||||
OPTIONBYTE_PCROP | OPTIONBYTE_IPCC_BUF_ADDR | OPTIONBYTE_C2_BOOT_VECT | \
|
||||
OPTIONBYTE_SECURE_MODE) /*!< All option byte configuration */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_OB_WRP_AREA FLASH WRP Area
|
||||
* @{
|
||||
*/
|
||||
#define OB_WRPAREA_BANK1_AREAA 0x00000000U /*!< Flash Area A */
|
||||
#define OB_WRPAREA_BANK1_AREAB 0x00000001U /*!< Flash Area B */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_OB_READ_PROTECTION FLASH Option Bytes Read Protection
|
||||
* @{
|
||||
*/
|
||||
#define OB_RDP_LEVEL_0 0x000000AAU
|
||||
#define OB_RDP_LEVEL_1 0x000000BBU
|
||||
#define OB_RDP_LEVEL_2 0x000000CCU /*!< Warning: When enabling read protection level 2
|
||||
it's no more possible to go back to level 1 or 0 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_OB_USER_TYPE FLASH Option Bytes User Type
|
||||
* @{
|
||||
*/
|
||||
#define OB_USER_BOR_LEV FLASH_OPTR_BOR_LEV /*!< BOR reset Level */
|
||||
#define OB_USER_nRST_STOP FLASH_OPTR_nRST_STOP /*!< Reset generated when entering the stop mode */
|
||||
#define OB_USER_nRST_STDBY FLASH_OPTR_nRST_STDBY /*!< Reset generated when entering the standby mode */
|
||||
#define OB_USER_nRST_SHDW FLASH_OPTR_nRST_SHDW /*!< Reset generated when entering the shutdown mode */
|
||||
#if defined(FLASH_OPTR_IRHEN)
|
||||
#define OB_USER_INPUT_RESET_HOLDER FLASH_OPTR_IRHEN /*!< Internal reset holder enable */
|
||||
#endif
|
||||
#define OB_USER_IWDG_SW FLASH_OPTR_IWDG_SW /*!< Independent watchdog selection */
|
||||
#define OB_USER_IWDG_STOP FLASH_OPTR_IWDG_STOP /*!< Independent watchdog counter freeze in stop mode */
|
||||
#define OB_USER_IWDG_STDBY FLASH_OPTR_IWDG_STDBY /*!< Independent watchdog counter freeze in standby mode */
|
||||
#define OB_USER_WWDG_SW FLASH_OPTR_WWDG_SW /*!< Window watchdog selection */
|
||||
#define OB_USER_nBOOT1 FLASH_OPTR_nBOOT1 /*!< Boot configuration */
|
||||
#define OB_USER_SRAM2PE FLASH_OPTR_SRAM2PE /*!< SRAM2 parity check enable */
|
||||
#define OB_USER_SRAM2RST FLASH_OPTR_SRAM2RST /*!< SRAM2 erase when system reset */
|
||||
#define OB_USER_nSWBOOT0 FLASH_OPTR_nSWBOOT0 /*!< Software BOOT0 */
|
||||
#define OB_USER_nBOOT0 FLASH_OPTR_nBOOT0 /*!< nBOOT0 option bit */
|
||||
#if defined(FLASH_OPTR_nRST_MODE)
|
||||
#define OB_USER_NRST_MODE FLASH_OPTR_nRST_MODE /*!< Reset pin configuration */
|
||||
#endif
|
||||
#define OB_USER_AGC_TRIM FLASH_OPTR_AGC_TRIM /*!< Automatic Gain Control Trimming */
|
||||
#if defined(FLASH_OPTR_IRHEN) && defined(FLASH_OPTR_nRST_MODE)
|
||||
#define OB_USER_ALL (OB_USER_BOR_LEV | OB_USER_nRST_STOP | OB_USER_nRST_STDBY | \
|
||||
OB_USER_nRST_SHDW | OB_USER_IWDG_SW | OB_USER_IWDG_STOP | \
|
||||
OB_USER_IWDG_STDBY | OB_USER_WWDG_SW | OB_USER_nBOOT1 | \
|
||||
OB_USER_SRAM2PE | OB_USER_SRAM2RST | OB_USER_nSWBOOT0 | \
|
||||
OB_USER_nBOOT0 | OB_USER_AGC_TRIM | OB_USER_NRST_MODE | \
|
||||
OB_USER_INPUT_RESET_HOLDER) /*!< all option bits */
|
||||
#else
|
||||
#define OB_USER_ALL (OB_USER_BOR_LEV | OB_USER_nRST_STOP | OB_USER_nRST_STDBY | \
|
||||
OB_USER_nRST_SHDW | OB_USER_IWDG_SW | OB_USER_IWDG_STOP | \
|
||||
OB_USER_IWDG_STDBY | OB_USER_WWDG_SW | OB_USER_nBOOT1 | \
|
||||
OB_USER_SRAM2PE | OB_USER_SRAM2RST | OB_USER_nSWBOOT0 | \
|
||||
OB_USER_nBOOT0 | OB_USER_AGC_TRIM) /*!< all option bits */
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_OB_USER_AGC_TRIM FLASH Option Bytes Automatic Gain Control Trimming
|
||||
* @{
|
||||
*/
|
||||
#define OB_AGC_TRIM_0 0x00000000U /*!< Automatic Gain Control Trimming Value 0 */
|
||||
#define OB_AGC_TRIM_1 FLASH_OPTR_AGC_TRIM_0 /*!< Automatic Gain Control Trimming Value 1 */
|
||||
#define OB_AGC_TRIM_2 FLASH_OPTR_AGC_TRIM_1 /*!< Automatic Gain Control Trimming Value 2 */
|
||||
#define OB_AGC_TRIM_3 (FLASH_OPTR_AGC_TRIM_1 | FLASH_OPTR_AGC_TRIM_0) /*!< Automatic Gain Control Trimming Value 3 */
|
||||
#define OB_AGC_TRIM_4 FLASH_OPTR_AGC_TRIM_2 /*!< Automatic Gain Control Trimming Value 4 */
|
||||
#define OB_AGC_TRIM_5 (FLASH_OPTR_AGC_TRIM_2 | FLASH_OPTR_AGC_TRIM_0) /*!< Automatic Gain Control Trimming Value 5 */
|
||||
#define OB_AGC_TRIM_6 (FLASH_OPTR_AGC_TRIM_2 | FLASH_OPTR_AGC_TRIM_1) /*!< Automatic Gain Control Trimming Value 6 */
|
||||
#define OB_AGC_TRIM_7 (FLASH_OPTR_AGC_TRIM_2 | FLASH_OPTR_AGC_TRIM_1 | FLASH_OPTR_AGC_TRIM_0) /*!< Automatic Gain Control Trimming Value 7 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_OB_USER_BOR_LEVEL FLASH Option Bytes User BOR Level
|
||||
* @{
|
||||
*/
|
||||
#define OB_BOR_LEVEL_0 0x00000000U /*!< Reset level threshold is around 1.7V */
|
||||
#define OB_BOR_LEVEL_1 FLASH_OPTR_BOR_LEV_0 /*!< Reset level threshold is around 2.0V */
|
||||
#define OB_BOR_LEVEL_2 FLASH_OPTR_BOR_LEV_1 /*!< Reset level threshold is around 2.2V */
|
||||
#define OB_BOR_LEVEL_3 (FLASH_OPTR_BOR_LEV_0 | FLASH_OPTR_BOR_LEV_1) /*!< Reset level threshold is around 2.5V */
|
||||
#define OB_BOR_LEVEL_4 FLASH_OPTR_BOR_LEV_2 /*!< Reset level threshold is around 2.8V */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_OB_USER_nRST_STOP FLASH Option Bytes User Reset On Stop
|
||||
* @{
|
||||
*/
|
||||
#define OB_STOP_RST 0x00000000U /*!< Reset generated when entering the stop mode */
|
||||
#define OB_STOP_NORST FLASH_OPTR_nRST_STOP /*!< No reset generated when entering the stop mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_OB_USER_nRST_STANDBY FLASH Option Bytes User Reset On Standby
|
||||
* @{
|
||||
*/
|
||||
#define OB_STANDBY_RST 0x00000000U /*!< Reset generated when entering the standby mode */
|
||||
#define OB_STANDBY_NORST FLASH_OPTR_nRST_STDBY /*!< No reset generated when entering the standby mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_OB_USER_nRST_SHUTDOWN FLASH Option Bytes User Reset On Shutdown
|
||||
* @{
|
||||
*/
|
||||
#define OB_SHUTDOWN_RST 0x00000000U /*!< Reset generated when entering the shutdown mode */
|
||||
#define OB_SHUTDOWN_NORST FLASH_OPTR_nRST_SHDW /*!< No reset generated when entering the shutdown mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_OB_USER_IWDG_SW FLASH Option Bytes User IWDG Type
|
||||
* @{
|
||||
*/
|
||||
#define OB_IWDG_HW 0x00000000U /*!< Hardware independent watchdog */
|
||||
#define OB_IWDG_SW FLASH_OPTR_IWDG_SW /*!< Software independent watchdog */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_OB_USER_IWDG_STOP FLASH Option Bytes User IWDG Mode On Stop
|
||||
* @{
|
||||
*/
|
||||
#define OB_IWDG_STOP_FREEZE 0x00000000U /*!< Independent watchdog counter is frozen in Stop mode */
|
||||
#define OB_IWDG_STOP_RUN FLASH_OPTR_IWDG_STOP /*!< Independent watchdog counter is running in Stop mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_OB_USER_IWDG_STANDBY FLASH Option Bytes User IWDG Mode On Standby
|
||||
* @{
|
||||
*/
|
||||
#define OB_IWDG_STDBY_FREEZE 0x00000000U /*!< Independent watchdog counter is frozen in Standby mode */
|
||||
#define OB_IWDG_STDBY_RUN FLASH_OPTR_IWDG_STDBY /*!< Independent watchdog counter is running in Standby mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_OB_USER_WWDG_SW FLASH Option Bytes User WWDG Type
|
||||
* @{
|
||||
*/
|
||||
#define OB_WWDG_HW 0x00000000U /*!< Hardware window watchdog */
|
||||
#define OB_WWDG_SW FLASH_OPTR_WWDG_SW /*!< Software window watchdog */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_OB_USER_SRAM2PE FLASH Option Bytes SRAM2 parity check
|
||||
* @{
|
||||
*/
|
||||
#define OB_SRAM2_PARITY_ENABLE 0x00000000U /*!< SRAM2 parity check enable */
|
||||
#define OB_SRAM2_PARITY_DISABLE FLASH_OPTR_SRAM2PE /*!< SRAM2 parity check disable */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_OB_USER_SRAM2RST FLASH Option Bytes SRAM2 erase when system reset
|
||||
* @{
|
||||
*/
|
||||
#define OB_SRAM2_RST_ERASE 0x00000000U /*!< SRAM2 erased when a system reset */
|
||||
#define OB_SRAM2_RST_NOT_ERASE FLASH_OPTR_SRAM2RST /*!< SRAM2 is not erased when a system reset */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_OB_USER_nBOOT1 FLASH Option Bytes User BOOT1 Type
|
||||
* @{
|
||||
*/
|
||||
#define OB_BOOT1_SRAM 0x00000000U /*!< Embedded SRAM is selected as boot space (if BOOT0=1) */
|
||||
#define OB_BOOT1_SYSTEM FLASH_OPTR_nBOOT1 /*!< System memory is selected as boot space (if BOOT0=1) */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_OB_USER_nSWBOOT0 FLASH Option Bytes User Software BOOT0
|
||||
* @{
|
||||
*/
|
||||
#define OB_BOOT0_FROM_OB 0x00000000U /*!< BOOT0 taken from the option bit nBOOT0 */
|
||||
#define OB_BOOT0_FROM_PIN FLASH_OPTR_nSWBOOT0 /*!< BOOT0 taken from PH3/BOOT0 pin */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_OB_USER_nBOOT0 FLASH Option Bytes User nBOOT0 option bit
|
||||
* @{
|
||||
*/
|
||||
#define OB_BOOT0_RESET 0x00000000U /*!< nBOOT0 = 0 */
|
||||
#define OB_BOOT0_SET FLASH_OPTR_nBOOT0 /*!< nBOOT0 = 1 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if defined(FLASH_OPTR_nRST_MODE)
|
||||
/** @defgroup FLASH_OB_USER_RESET_CONFIG FLASH Option Bytes User reset config bit
|
||||
* @{
|
||||
*/
|
||||
#define OB_RESET_MODE_INPUT_ONLY FLASH_OPTR_nRST_MODE_0 /*!< Reset pin is in Reset input mode only */
|
||||
#define OB_RESET_MODE_GPIO FLASH_OPTR_nRST_MODE_1 /*!< Reset pin is in GPIO normal mode only */
|
||||
#define OB_RESET_MODE_INPUT_OUTPUT (FLASH_OPTR_nRST_MODE_0 | FLASH_OPTR_nRST_MODE_1) /*!< Reset pin is in Reset input and output mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif
|
||||
|
||||
#if defined(FLASH_OPTR_IRHEN)
|
||||
/** @defgroup FLASH_OB_USER_INPUT_RESET_HOLDER FLASH Option Bytes User input reset holder bit
|
||||
* @{
|
||||
*/
|
||||
#define OB_IRH_ENABLE 0x00000000U /*!< Internal Reset handler enable */
|
||||
#define OB_IRH_DISABLE FLASH_OPTR_IRHEN /*!< Internal Reset handler disable */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif
|
||||
|
||||
/** @defgroup FLASH_OB_PCROP_ZONE FLASH PCROP ZONE
|
||||
* @{
|
||||
*/
|
||||
#define OB_PCROP_ZONE_A 0x00000001U /*!< PCROP Zone A */
|
||||
#define OB_PCROP_ZONE_B 0x00000002U /*!< PCROP Zone B */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_OB_PCROP_RDP FLASH Option Bytes PCROP On RDP Level Type
|
||||
* @{
|
||||
*/
|
||||
#define OB_PCROP_RDP_NOT_ERASE 0x00000000U /*!< PCROP area is not erased when the RDP level
|
||||
is decreased from Level 1 to Level 0 */
|
||||
#define OB_PCROP_RDP_ERASE FLASH_PCROP1AER_PCROP_RDP /*!< PCROP area is erased when the RDP level is
|
||||
decreased from Level 1 to Level 0 (full mass erase) */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_OB_SECURITY_MODE Option Bytes FLASH Secure mode
|
||||
* @{
|
||||
*/
|
||||
#define SYSTEM_NOT_IN_SECURE_MODE 0x00000000U /*!< Unsecure mode: Security disabled */
|
||||
#define SYSTEM_IN_SECURE_MODE FLASH_OPTR_ESE /*!< Secure mode : Security enabled */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_C2_OB_BOOT_REGION CPU2 Option Bytes Reset Boot Vector
|
||||
* @{
|
||||
*/
|
||||
#define OB_C2_BOOT_FROM_SRAM 0x00000000U /*!< CPU2 boot from Sram */
|
||||
#define OB_C2_BOOT_FROM_FLASH FLASH_SRRVR_C2OPT /*!< CPU2 boot from Flash */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_SRAM2A_ADDRESS_RANGE RAM2A address range in secure mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SRAM2A_START_SECURE_ADDR_0 (SRAM2A_BASE + 0x0000U) /* When in secure mode (SRAM2A_BASE + 0x0000) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
|
||||
#define SRAM2A_START_SECURE_ADDR_1 (SRAM2A_BASE + 0x0400U) /* When in secure mode (SRAM2A_BASE + 0x0400) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
|
||||
#define SRAM2A_START_SECURE_ADDR_2 (SRAM2A_BASE + 0x0800U) /* When in secure mode (SRAM2A_BASE + 0x0800) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
|
||||
#define SRAM2A_START_SECURE_ADDR_3 (SRAM2A_BASE + 0x0C00U) /* When in secure mode (SRAM2A_BASE + 0x0C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
|
||||
#define SRAM2A_START_SECURE_ADDR_4 (SRAM2A_BASE + 0x1000U) /* When in secure mode (SRAM2A_BASE + 0x1000) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
|
||||
#define SRAM2A_START_SECURE_ADDR_5 (SRAM2A_BASE + 0x1400U) /* When in secure mode (SRAM2A_BASE + 0x1400) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
|
||||
#define SRAM2A_START_SECURE_ADDR_6 (SRAM2A_BASE + 0x1800U) /* When in secure mode (SRAM2A_BASE + 0x1800) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
|
||||
#define SRAM2A_START_SECURE_ADDR_7 (SRAM2A_BASE + 0x1C00U) /* When in secure mode (SRAM2A_BASE + 0x1C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
|
||||
#define SRAM2A_START_SECURE_ADDR_8 (SRAM2A_BASE + 0x2000U) /* When in secure mode (SRAM2A_BASE + 0x2000) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
|
||||
#define SRAM2A_START_SECURE_ADDR_9 (SRAM2A_BASE + 0x2400U) /* When in secure mode (SRAM2A_BASE + 0x2400) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
|
||||
#define SRAM2A_START_SECURE_ADDR_10 (SRAM2A_BASE + 0x2800U) /* When in secure mode (SRAM2A_BASE + 0x2800) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
|
||||
#define SRAM2A_START_SECURE_ADDR_11 (SRAM2A_BASE + 0x2C00U) /* When in secure mode (SRAM2A_BASE + 0x2C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
|
||||
#define SRAM2A_START_SECURE_ADDR_12 (SRAM2A_BASE + 0x3000U) /* When in secure mode (SRAM2A_BASE + 0x3000) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
|
||||
#define SRAM2A_START_SECURE_ADDR_13 (SRAM2A_BASE + 0x3400U) /* When in secure mode (SRAM2A_BASE + 0x3400) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
|
||||
#define SRAM2A_START_SECURE_ADDR_14 (SRAM2A_BASE + 0x3800U) /* When in secure mode (SRAM2A_BASE + 0x3800) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
|
||||
#define SRAM2A_START_SECURE_ADDR_15 (SRAM2A_BASE + 0x3C00U) /* When in secure mode (SRAM2A_BASE + 0x3C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
|
||||
#define SRAM2A_START_SECURE_ADDR_16 (SRAM2A_BASE + 0x4000U) /* When in secure mode (SRAM2A_BASE + 0x4000) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
|
||||
#define SRAM2A_START_SECURE_ADDR_17 (SRAM2A_BASE + 0x4400U) /* When in secure mode (SRAM2A_BASE + 0x4400) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
|
||||
#define SRAM2A_START_SECURE_ADDR_18 (SRAM2A_BASE + 0x4800U) /* When in secure mode (SRAM2A_BASE + 0x4800) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
|
||||
#define SRAM2A_START_SECURE_ADDR_19 (SRAM2A_BASE + 0x4C00U) /* When in secure mode (SRAM2A_BASE + 0x4C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
|
||||
#define SRAM2A_START_SECURE_ADDR_20 (SRAM2A_BASE + 0x5000U) /* When in secure mode (SRAM2A_BASE + 0x5000) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
|
||||
#define SRAM2A_START_SECURE_ADDR_21 (SRAM2A_BASE + 0x5400U) /* When in secure mode (SRAM2A_BASE + 0x5400) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
|
||||
#define SRAM2A_START_SECURE_ADDR_22 (SRAM2A_BASE + 0x5800U) /* When in secure mode (SRAM2A_BASE + 0x5800) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
|
||||
#define SRAM2A_START_SECURE_ADDR_23 (SRAM2A_BASE + 0x5C00U) /* When in secure mode (SRAM2A_BASE + 0x5C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
|
||||
#define SRAM2A_START_SECURE_ADDR_24 (SRAM2A_BASE + 0x6000U) /* When in secure mode (SRAM2A_BASE + 0x6000) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
|
||||
#define SRAM2A_START_SECURE_ADDR_25 (SRAM2A_BASE + 0x6400U) /* When in secure mode (SRAM2A_BASE + 0x6400) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
|
||||
#define SRAM2A_START_SECURE_ADDR_26 (SRAM2A_BASE + 0x6800U) /* When in secure mode (SRAM2A_BASE + 0x6800) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
|
||||
#define SRAM2A_START_SECURE_ADDR_27 (SRAM2A_BASE + 0x6C00U) /* When in secure mode (SRAM2A_BASE + 0x6C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
|
||||
#define SRAM2A_START_SECURE_ADDR_28 (SRAM2A_BASE + 0x7000U) /* When in secure mode (SRAM2A_BASE + 0x7000) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
|
||||
#define SRAM2A_START_SECURE_ADDR_29 (SRAM2A_BASE + 0x7400U) /* When in secure mode (SRAM2A_BASE + 0x7400) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
|
||||
#define SRAM2A_START_SECURE_ADDR_30 (SRAM2A_BASE + 0x7800U) /* When in secure mode (SRAM2A_BASE + 0x7800) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
|
||||
#define SRAM2A_START_SECURE_ADDR_31 (SRAM2A_BASE + 0x7C00U) /* When in secure mode (SRAM2A_BASE + 0x7C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
|
||||
#define SRAM2A_FULL_UNSECURE (SRAM2A_BASE + 0x8000U) /* The RAM2A is accessible to M0 Plus and M4 */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_SRAM2B_ADDRESS_RANGE RAM2B address range in secure mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SRAM2B_START_SECURE_ADDR_0 (SRAM2B_BASE + 0x0000U) /* When in secure mode (SRAM2B_BASE + 0x0000) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
|
||||
#define SRAM2B_START_SECURE_ADDR_1 (SRAM2B_BASE + 0x0400U) /* When in secure mode (SRAM2B_BASE + 0x0400) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
|
||||
#define SRAM2B_START_SECURE_ADDR_2 (SRAM2B_BASE + 0x0800U) /* When in secure mode (SRAM2B_BASE + 0x0800) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
|
||||
#define SRAM2B_START_SECURE_ADDR_3 (SRAM2B_BASE + 0x0C00U) /* When in secure mode (SRAM2B_BASE + 0x0C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
|
||||
#if !defined(STM32WB15xx)
|
||||
#define SRAM2B_START_SECURE_ADDR_4 (SRAM2B_BASE + 0x1000U) /* When in secure mode (SRAM2B_BASE + 0x1000) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
|
||||
#define SRAM2B_START_SECURE_ADDR_5 (SRAM2B_BASE + 0x1400U) /* When in secure mode (SRAM2B_BASE + 0x1400) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
|
||||
#define SRAM2B_START_SECURE_ADDR_6 (SRAM2B_BASE + 0x1800U) /* When in secure mode (SRAM2B_BASE + 0x1800) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
|
||||
#define SRAM2B_START_SECURE_ADDR_7 (SRAM2B_BASE + 0x1C00U) /* When in secure mode (SRAM2B_BASE + 0x1C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
|
||||
#define SRAM2B_START_SECURE_ADDR_8 (SRAM2B_BASE + 0x2000U) /* When in secure mode (SRAM2B_BASE + 0x2000) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
|
||||
#define SRAM2B_START_SECURE_ADDR_9 (SRAM2B_BASE + 0x2400U) /* When in secure mode (SRAM2B_BASE + 0x2400) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
|
||||
#define SRAM2B_START_SECURE_ADDR_10 (SRAM2B_BASE + 0x2800U) /* When in secure mode (SRAM2B_BASE + 0x2800) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
|
||||
#define SRAM2B_START_SECURE_ADDR_11 (SRAM2B_BASE + 0x2C00U) /* When in secure mode (SRAM2B_BASE + 0x2C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
|
||||
#define SRAM2B_START_SECURE_ADDR_12 (SRAM2B_BASE + 0x3000U) /* When in secure mode (SRAM2B_BASE + 0x3000) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
|
||||
#define SRAM2B_START_SECURE_ADDR_13 (SRAM2B_BASE + 0x3400U) /* When in secure mode (SRAM2B_BASE + 0x3400) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
|
||||
#define SRAM2B_START_SECURE_ADDR_14 (SRAM2B_BASE + 0x3800U) /* When in secure mode (SRAM2B_BASE + 0x3800) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
|
||||
#define SRAM2B_START_SECURE_ADDR_15 (SRAM2B_BASE + 0x3C00U) /* When in secure mode (SRAM2B_BASE + 0x3C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
|
||||
#define SRAM2B_START_SECURE_ADDR_16 (SRAM2B_BASE + 0x4000U) /* When in secure mode (SRAM2B_BASE + 0x4000) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
|
||||
#define SRAM2B_START_SECURE_ADDR_17 (SRAM2B_BASE + 0x4400U) /* When in secure mode (SRAM2B_BASE + 0x4400) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
|
||||
#define SRAM2B_START_SECURE_ADDR_18 (SRAM2B_BASE + 0x4800U) /* When in secure mode (SRAM2B_BASE + 0x4800) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
|
||||
#define SRAM2B_START_SECURE_ADDR_19 (SRAM2B_BASE + 0x4C00U) /* When in secure mode (SRAM2B_BASE + 0x4C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
|
||||
#define SRAM2B_START_SECURE_ADDR_20 (SRAM2B_BASE + 0x5000U) /* When in secure mode (SRAM2B_BASE + 0x5000) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
|
||||
#define SRAM2B_START_SECURE_ADDR_21 (SRAM2B_BASE + 0x5400U) /* When in secure mode (SRAM2B_BASE + 0x5400) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
|
||||
#define SRAM2B_START_SECURE_ADDR_22 (SRAM2B_BASE + 0x5800U) /* When in secure mode (SRAM2B_BASE + 0x5800) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
|
||||
#define SRAM2B_START_SECURE_ADDR_23 (SRAM2B_BASE + 0x5C00U) /* When in secure mode (SRAM2B_BASE + 0x5C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
|
||||
#define SRAM2B_START_SECURE_ADDR_24 (SRAM2B_BASE + 0x6000U) /* When in secure mode (SRAM2B_BASE + 0x6000) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
|
||||
#define SRAM2B_START_SECURE_ADDR_25 (SRAM2B_BASE + 0x6400U) /* When in secure mode (SRAM2B_BASE + 0x6400) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
|
||||
#define SRAM2B_START_SECURE_ADDR_26 (SRAM2B_BASE + 0x6800U) /* When in secure mode (SRAM2B_BASE + 0x6800) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
|
||||
#define SRAM2B_START_SECURE_ADDR_27 (SRAM2B_BASE + 0x6C00U) /* When in secure mode (SRAM2B_BASE + 0x6C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
|
||||
#define SRAM2B_START_SECURE_ADDR_28 (SRAM2B_BASE + 0x7000U) /* When in secure mode (SRAM2B_BASE + 0x7000) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
|
||||
#define SRAM2B_START_SECURE_ADDR_29 (SRAM2B_BASE + 0x7400U) /* When in secure mode (SRAM2B_BASE + 0x7400) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
|
||||
#define SRAM2B_START_SECURE_ADDR_30 (SRAM2B_BASE + 0x7800U) /* When in secure mode (SRAM2B_BASE + 0x7800) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
|
||||
#define SRAM2B_START_SECURE_ADDR_31 (SRAM2B_BASE + 0x7C00U) /* When in secure mode (SRAM2B_BASE + 0x7C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
|
||||
#define SRAM2B_FULL_UNSECURE (SRAM2B_BASE + 0x8000U) /* The RAM2B is accessible to M0 Plus and M4 */
|
||||
#else
|
||||
#define SRAM2B_FULL_UNSECURE (SRAM2B_BASE + 0x0C00U) /* The RAM2B is accessible to M0 Plus and M4 */
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/** @defgroup FLASH_Exported_Macros FLASH Exported Macros
|
||||
* @brief macros to control FLASH features
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Set the FLASH Latency.
|
||||
* @param __LATENCY__ FLASH Latency
|
||||
* This parameter can be one of the following values :
|
||||
* @arg @ref FLASH_LATENCY_0 FLASH Zero wait state
|
||||
* @arg @ref FLASH_LATENCY_1 FLASH One wait state
|
||||
* @arg @ref FLASH_LATENCY_2 FLASH Two wait states
|
||||
* @arg @ref FLASH_LATENCY_3 FLASH Three wait states
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_FLASH_SET_LATENCY(__LATENCY__) MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (__LATENCY__))
|
||||
|
||||
/**
|
||||
* @brief Get the FLASH Latency.
|
||||
* @retval FLASH Latency
|
||||
* Returned value can be one of the following values :
|
||||
* @arg @ref FLASH_LATENCY_0 FLASH Zero wait state
|
||||
* @arg @ref FLASH_LATENCY_1 FLASH One wait state
|
||||
* @arg @ref FLASH_LATENCY_2 FLASH Two wait states
|
||||
* @arg @ref FLASH_LATENCY_3 FLASH Three wait states
|
||||
*/
|
||||
#define __HAL_FLASH_GET_LATENCY() READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY)
|
||||
|
||||
/**
|
||||
* @brief Enable the FLASH prefetch buffer.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN)
|
||||
|
||||
/**
|
||||
* @brief Disable the FLASH prefetch buffer.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_FLASH_PREFETCH_BUFFER_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTEN)
|
||||
|
||||
/**
|
||||
* @brief Enable the FLASH instruction cache.
|
||||
* @retval none
|
||||
*/
|
||||
#define __HAL_FLASH_INSTRUCTION_CACHE_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_ICEN)
|
||||
|
||||
/**
|
||||
* @brief Disable the FLASH instruction cache.
|
||||
* @retval none
|
||||
*/
|
||||
#define __HAL_FLASH_INSTRUCTION_CACHE_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICEN)
|
||||
|
||||
/**
|
||||
* @brief Enable the FLASH data cache.
|
||||
* @retval none
|
||||
*/
|
||||
#define __HAL_FLASH_DATA_CACHE_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_DCEN)
|
||||
|
||||
/**
|
||||
* @brief Disable the FLASH data cache.
|
||||
* @retval none
|
||||
*/
|
||||
#define __HAL_FLASH_DATA_CACHE_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCEN)
|
||||
|
||||
/**
|
||||
* @brief Reset the FLASH instruction Cache.
|
||||
* @note This function must be used only when the Instruction Cache is disabled.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_FLASH_INSTRUCTION_CACHE_RESET() do { SET_BIT(FLASH->ACR, FLASH_ACR_ICRST); \
|
||||
CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICRST); \
|
||||
} while (0)
|
||||
|
||||
/**
|
||||
* @brief Reset the FLASH data Cache.
|
||||
* @note This function must be used only when the data Cache is disabled.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_FLASH_DATA_CACHE_RESET() do { SET_BIT(FLASH->ACR, FLASH_ACR_DCRST); \
|
||||
CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCRST); \
|
||||
} while (0)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Interrupt FLASH Interrupts Macros
|
||||
* @brief macros to handle FLASH interrupts
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enable the specified FLASH interrupt.
|
||||
* @param __INTERRUPT__ FLASH interrupt
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg @ref FLASH_IT_EOP End of FLASH Operation Interrupt
|
||||
* @arg @ref FLASH_IT_OPERR Error Interrupt
|
||||
* @arg @ref FLASH_IT_RDERR PCROP Read Error Interrupt
|
||||
* @arg @ref FLASH_IT_ECCC ECC Correction Interrupt
|
||||
* @retval none
|
||||
*/
|
||||
#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) { SET_BIT(FLASH->ECCR, FLASH_ECCR_ECCCIE); }\
|
||||
if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) { SET_BIT(FLASH->CR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\
|
||||
} while(0)
|
||||
|
||||
/**
|
||||
* @brief Disable the specified FLASH interrupt.
|
||||
* @param __INTERRUPT__ FLASH interrupt
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg @ref FLASH_IT_EOP End of FLASH Operation Interrupt
|
||||
* @arg @ref FLASH_IT_OPERR Error Interrupt
|
||||
* @arg @ref FLASH_IT_RDERR PCROP Read Error Interrupt
|
||||
* @arg @ref FLASH_IT_ECCC ECC Correction Interrupt
|
||||
* @retval none
|
||||
*/
|
||||
#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) { CLEAR_BIT(FLASH->ECCR, FLASH_ECCR_ECCCIE); }\
|
||||
if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) { CLEAR_BIT(FLASH->CR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\
|
||||
} while(0)
|
||||
|
||||
/**
|
||||
* @brief Check whether the specified FLASH flag is set or not.
|
||||
* @param __FLAG__ specifies the FLASH flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref FLASH_FLAG_EOP FLASH End of Operation flag
|
||||
* @arg @ref FLASH_FLAG_OPERR FLASH Operation error flag
|
||||
* @arg @ref FLASH_FLAG_PROGERR FLASH Programming error flag
|
||||
* @arg @ref FLASH_FLAG_WRPERR FLASH Write protection error flag
|
||||
* @arg @ref FLASH_FLAG_PGAERR FLASH Programming alignment error flag
|
||||
* @arg @ref FLASH_FLAG_SIZERR FLASH Size error flag
|
||||
* @arg @ref FLASH_FLAG_PGSERR FLASH Programming sequence error flag
|
||||
* @arg @ref FLASH_FLAG_MISERR FLASH Fast programming data miss error flag
|
||||
* @arg @ref FLASH_FLAG_FASTERR FLASH Fast programming error flag
|
||||
* @arg @ref FLASH_FLAG_OPTNV FLASH User Option OPTVAL indication
|
||||
* @arg @ref FLASH_FLAG_RDERR FLASH PCROP read error flag
|
||||
* @arg @ref FLASH_FLAG_OPTVERR FLASH Option validity error flag
|
||||
* @arg @ref FLASH_FLAG_BSY FLASH write/erase operations in progress flag
|
||||
* @arg @ref FLASH_FLAG_CFGBSY Programming/erase configuration busy
|
||||
* @arg @ref FLASH_FLAG_PESD FLASH Programming/erase operation suspended
|
||||
* @arg @ref FLASH_FLAG_ECCC FLASH one ECC error has been detected and corrected
|
||||
* @arg @ref FLASH_FLAG_ECCD FLASH two ECC errors have been detected
|
||||
* @retval The new state of FLASH_FLAG (SET or RESET).
|
||||
*/
|
||||
#define __HAL_FLASH_GET_FLAG(__FLAG__) ((((__FLAG__) & (FLASH_FLAG_ECCR_ERRORS)) != 0U) ? \
|
||||
(READ_BIT(FLASH->ECCR, (__FLAG__)) == (__FLAG__)) : \
|
||||
(READ_BIT(FLASH->SR, (__FLAG__)) == (__FLAG__)))
|
||||
/**
|
||||
* @brief Clear the FLASH's pending flags.
|
||||
* @param __FLAG__ specifies the FLASH flags to clear.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg @ref FLASH_FLAG_EOP FLASH End of Operation flag
|
||||
* @arg @ref FLASH_FLAG_OPERR FLASH Operation error flag
|
||||
* @arg @ref FLASH_FLAG_PROGERR FLASH Programming error flag
|
||||
* @arg @ref FLASH_FLAG_WRPERR FLASH Write protection error flag
|
||||
* @arg @ref FLASH_FLAG_PGAERR FLASH Programming alignment error flag
|
||||
* @arg @ref FLASH_FLAG_SIZERR FLASH Size error flag
|
||||
* @arg @ref FLASH_FLAG_PGSERR FLASH Programming sequence error flag
|
||||
* @arg @ref FLASH_FLAG_MISERR FLASH Fast programming data miss error flag
|
||||
* @arg @ref FLASH_FLAG_FASTERR FLASH Fast programming error flag
|
||||
* @arg @ref FLASH_FLAG_RDERR FLASH PCROP read error flag
|
||||
* @arg @ref FLASH_FLAG_OPTVERR FLASH Option validity error flag
|
||||
* @arg @ref FLASH_FLAG_ECCC FLASH one ECC error has been detected and corrected
|
||||
* @arg @ref FLASH_FLAG_ECCD FLASH two ECC errors have been detected
|
||||
* @arg @ref FLASH_FLAG_SR_ERRORS FLASH All SR errors flags
|
||||
* @arg @ref FLASH_FLAG_ECCR_ERRORS FLASH All ECCR errors flags
|
||||
* @arg @ref FLASH_FLAG_ALL_ERRORS FLASH All errors flags
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) do { if(((__FLAG__) & (FLASH_FLAG_ECCR_ERRORS)) != 0U) { SET_BIT(FLASH->ECCR, ((__FLAG__) & (FLASH_FLAG_ECCR_ERRORS))); }\
|
||||
if(((__FLAG__) & ~(FLASH_FLAG_ECCR_ERRORS)) != 0U) { WRITE_REG(FLASH->SR, ((__FLAG__) & ~(FLASH_FLAG_ECCR_ERRORS))); }\
|
||||
} while(0)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Include FLASH HAL Extended module */
|
||||
#include "stm32wbxx_hal_flash_ex.h"
|
||||
/* Exported variables --------------------------------------------------------*/
|
||||
/** @defgroup FLASH_Exported_Variables FLASH Exported Variables
|
||||
* @{
|
||||
*/
|
||||
extern FLASH_ProcessTypeDef pFlash;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup FLASH_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Program operation functions ***********************************************/
|
||||
/** @addtogroup FLASH_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
|
||||
HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
|
||||
/* FLASH IRQ handler method */
|
||||
void HAL_FLASH_IRQHandler(void);
|
||||
/* Callbacks in non blocking modes */
|
||||
void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue);
|
||||
void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Peripheral Control functions **********************************************/
|
||||
/** @addtogroup FLASH_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_FLASH_Unlock(void);
|
||||
HAL_StatusTypeDef HAL_FLASH_Lock(void);
|
||||
/* Option bytes control */
|
||||
HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void);
|
||||
HAL_StatusTypeDef HAL_FLASH_OB_Lock(void);
|
||||
HAL_StatusTypeDef HAL_FLASH_OB_Launch(void);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Peripheral State functions ************************************************/
|
||||
/** @addtogroup FLASH_Exported_Functions_Group3
|
||||
* @{
|
||||
*/
|
||||
uint32_t HAL_FLASH_GetError(void);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private types --------------------------------------------------------*/
|
||||
/** @defgroup FLASH_Private_types FLASH Private Types
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private constants --------------------------------------------------------*/
|
||||
/** @defgroup FLASH_Private_Constants FLASH Private Constants
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_END_ADDR (FLASH_BASE + FLASH_SIZE - 1U)
|
||||
|
||||
#define FLASH_BANK_SIZE FLASH_SIZE /*!< FLASH Bank Size */
|
||||
#if defined(STM32WB15xx)
|
||||
#define FLASH_PAGE_SIZE 0x00000800U /*!< FLASH Page Size, 2 KBytes */
|
||||
#else
|
||||
#define FLASH_PAGE_SIZE 0x00001000U /*!< FLASH Page Size, 4 KBytes */
|
||||
#endif
|
||||
#define FLASH_PAGE_NB (FLASH_SIZE / FLASH_PAGE_SIZE)
|
||||
#define FLASH_TIMEOUT_VALUE 1000U /*!< FLASH Execution Timeout, 1 s */
|
||||
|
||||
#if defined(STM32WB15xx)
|
||||
#define FLASH_PCROP_GRANULARITY_OFFSET 10U /*!< FLASH Code Readout Protection granularity offset */
|
||||
#define FLASH_PCROP_GRANULARITY (1UL << FLASH_PCROP_GRANULARITY_OFFSET) /*!< FLASH Code Readout Protection granularity, 1 KBytes */
|
||||
#else
|
||||
#define FLASH_PCROP_GRANULARITY_OFFSET 11U /*!< FLASH Code Readout Protection granularity offset */
|
||||
#define FLASH_PCROP_GRANULARITY (1UL << FLASH_PCROP_GRANULARITY_OFFSET) /*!< FLASH Code Readout Protection granularity, 2 KBytes */
|
||||
#endif
|
||||
|
||||
#define FLASH_TYPENONE 0x00000000U /*!< No Programmation Procedure On Going */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SRAM_MEMORY_SIZE SRAM memory size
|
||||
* @{
|
||||
*/
|
||||
#define SRAM_SECURE_PAGE_GRANULARITY_OFFSET 10U /*!< Secure SRAM2A and SRAM2B Protection granularity offset */
|
||||
#define SRAM_SECURE_PAGE_GRANULARITY (1UL << FLASH_PCROP_GRANULARITY_OFFSET) /*!< Secure SRAM2A and SRAM2B Protection granularity, 1KBytes */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup FLASH_Private_Macros FLASH Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_FLASH_MAIN_MEM_ADDRESS(__VALUE__) (((__VALUE__) >= FLASH_BASE) && ((__VALUE__) <= (FLASH_BASE + FLASH_SIZE - 1UL)))
|
||||
|
||||
#define IS_FLASH_FAST_PROGRAM_ADDRESS(__VALUE__) (((__VALUE__) >= FLASH_BASE) && ((__VALUE__) <= (FLASH_BASE + FLASH_SIZE - 256UL)) && (((__VALUE__) % 256UL) == 0UL))
|
||||
|
||||
#define IS_FLASH_PROGRAM_MAIN_MEM_ADDRESS(__VALUE__) (((__VALUE__) >= FLASH_BASE) && ((__VALUE__) <= (FLASH_BASE + FLASH_SIZE - 8UL)) && (((__VALUE__) % 8UL) == 0UL))
|
||||
|
||||
#define IS_FLASH_PROGRAM_OTP_ADDRESS(__VALUE__) (((__VALUE__) >= OTP_AREA_BASE) && ((__VALUE__) <= (OTP_AREA_END_ADDR + 1UL - 8UL)) && (((__VALUE__) % 8UL) == 0UL))
|
||||
|
||||
#define IS_FLASH_PROGRAM_ADDRESS(__VALUE__) (IS_FLASH_PROGRAM_MAIN_MEM_ADDRESS(__VALUE__) || IS_FLASH_PROGRAM_OTP_ADDRESS(__VALUE__))
|
||||
|
||||
#define IS_FLASH_PAGE(__VALUE__) ((__VALUE__) < FLASH_PAGE_NB)
|
||||
|
||||
#define IS_ADDR_ALIGNED_64BITS(__VALUE__) (((__VALUE__) & 0x7U) == (0x00UL))
|
||||
|
||||
#define IS_FLASH_TYPEERASE(__VALUE__) ((__VALUE__) == FLASH_TYPEERASE_PAGES)
|
||||
|
||||
#define IS_FLASH_TYPEPROGRAM(__VALUE__) (((__VALUE__) == FLASH_TYPEPROGRAM_DOUBLEWORD) || \
|
||||
((__VALUE__) == FLASH_TYPEPROGRAM_FAST))
|
||||
|
||||
#define IS_OB_SFSA_START_ADDR(__VALUE__) (((__VALUE__) >= FLASH_BASE) && ((__VALUE__) <= FLASH_END_ADDR) && (((__VALUE__) & ~(uint32_t)(FLASH_PAGE_SIZE - 1U)) == (__VALUE__)))
|
||||
#define IS_OB_SBRSA_START_ADDR(__VALUE__) (((__VALUE__) >= SRAM2A_BASE) && ((__VALUE__) <= (SRAM2A_BASE + SRAM2A_SIZE - 1U)) && (((__VALUE__) & ~0x3FFU) == (__VALUE__)))
|
||||
#define IS_OB_SNBRSA_START_ADDR(__VALUE__) (((__VALUE__) >= SRAM2B_BASE) && ((__VALUE__) <= (SRAM2B_BASE + SRAM2B_SIZE - 1U)) && (((__VALUE__) & ~0x3FFU) == (__VALUE__)))
|
||||
#define IS_OB_SECURE_MODE(__VALUE__) (((__VALUE__) == SYSTEM_IN_SECURE_MODE) || ((__VALUE__) == SYSTEM_NOT_IN_SECURE_MODE))
|
||||
|
||||
#define IS_OPTIONBYTE(__VALUE__) (((__VALUE__) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_PCROP | \
|
||||
OPTIONBYTE_IPCC_BUF_ADDR | OPTIONBYTE_C2_BOOT_VECT | OPTIONBYTE_SECURE_MODE)))
|
||||
|
||||
#define IS_OB_WRPAREA(__VALUE__) (((__VALUE__) == OB_WRPAREA_BANK1_AREAA) || ((__VALUE__) == OB_WRPAREA_BANK1_AREAB))
|
||||
|
||||
#define IS_OB_RDP_LEVEL(__VALUE__) (((__VALUE__) == OB_RDP_LEVEL_0) ||\
|
||||
((__VALUE__) == OB_RDP_LEVEL_1) ||\
|
||||
((__VALUE__) == OB_RDP_LEVEL_2))
|
||||
|
||||
#define IS_OB_USER_TYPE(__VALUE__) ((((__VALUE__) & OB_USER_ALL) != 0U) && \
|
||||
(((__VALUE__) & ~OB_USER_ALL) == 0U))
|
||||
|
||||
#define IS_OB_USER_CONFIG(__TYPE__, __VALUE__) ((((__TYPE__) & OB_USER_BOR_LEV) == OB_USER_BOR_LEV) \
|
||||
? ((((__VALUE__) & ~(OB_USER_ALL & ~OB_USER_BOR_LEV)) == OB_BOR_LEVEL_0) || \
|
||||
(((__VALUE__) & ~(OB_USER_ALL & ~OB_USER_BOR_LEV)) == OB_BOR_LEVEL_1) || \
|
||||
(((__VALUE__) & ~(OB_USER_ALL & ~OB_USER_BOR_LEV)) == OB_BOR_LEVEL_2) || \
|
||||
(((__VALUE__) & ~(OB_USER_ALL & ~OB_USER_BOR_LEV)) == OB_BOR_LEVEL_3) || \
|
||||
(((__VALUE__) & ~(OB_USER_ALL & ~OB_USER_BOR_LEV)) == OB_BOR_LEVEL_4)) \
|
||||
: ((((__TYPE__) & OB_USER_AGC_TRIM) == OB_USER_AGC_TRIM) \
|
||||
? ((((__VALUE__) & ~(OB_USER_ALL & ~OB_USER_AGC_TRIM)) == OB_AGC_TRIM_0) || \
|
||||
(((__VALUE__) & ~(OB_USER_ALL & ~OB_USER_AGC_TRIM)) == OB_AGC_TRIM_1) || \
|
||||
(((__VALUE__) & ~(OB_USER_ALL & ~OB_USER_AGC_TRIM)) == OB_AGC_TRIM_2) || \
|
||||
(((__VALUE__) & ~(OB_USER_ALL & ~OB_USER_AGC_TRIM)) == OB_AGC_TRIM_3) || \
|
||||
(((__VALUE__) & ~(OB_USER_ALL & ~OB_USER_AGC_TRIM)) == OB_AGC_TRIM_4) || \
|
||||
(((__VALUE__) & ~(OB_USER_ALL & ~OB_USER_AGC_TRIM)) == OB_AGC_TRIM_5) || \
|
||||
(((__VALUE__) & ~(OB_USER_ALL & ~OB_USER_AGC_TRIM)) == OB_AGC_TRIM_6) || \
|
||||
(((__VALUE__) & ~(OB_USER_ALL & ~OB_USER_AGC_TRIM)) == OB_AGC_TRIM_7)) \
|
||||
: ((~(__TYPE__) & (__VALUE__)) == 0U)))
|
||||
|
||||
#define IS_OB_USER_AGC_TRIMMING(__VALUE__) (((__VALUE__) == OB_AGC_TRIM_0) || ((__VALUE__) == OB_AGC_TRIM_1) || \
|
||||
((__VALUE__) == OB_AGC_TRIM_2) || ((__VALUE__) == OB_AGC_TRIM_3) || \
|
||||
((__VALUE__) == OB_AGC_TRIM_4) || ((__VALUE__) == OB_AGC_TRIM_5) || \
|
||||
((__VALUE__) == OB_AGC_TRIM_6) || ((__VALUE__) == OB_AGC_TRIM_7))
|
||||
|
||||
#define IS_OB_USER_BOR_LEVEL(__VALUE__) (((__VALUE__) == OB_BOR_LEVEL_0) || ((__VALUE__) == OB_BOR_LEVEL_1) || \
|
||||
((__VALUE__) == OB_BOR_LEVEL_2) || ((__VALUE__) == OB_BOR_LEVEL_3) || \
|
||||
((__VALUE__) == OB_BOR_LEVEL_4))
|
||||
|
||||
#define IS_OB_PCROP_CONFIG(__VALUE__) (((__VALUE__) & ~(OB_PCROP_ZONE_A | OB_PCROP_ZONE_B | OB_PCROP_RDP_ERASE)) == 0U)
|
||||
|
||||
#define IS_OB_IPCC_BUF_ADDR(__VALUE__) (IS_OB_SBRSA_START_ADDR(__VALUE__) || IS_OB_SNBRSA_START_ADDR(__VALUE__))
|
||||
|
||||
#define IS_OB_BOOT_VECTOR_ADDR(__VALUE__) ((((__VALUE__) >= FLASH_BASE) && ((__VALUE__) <= (FLASH_BASE + FLASH_SIZE - 1U))) || \
|
||||
(((__VALUE__) >= SRAM1_BASE) && ((__VALUE__) <= (SRAM1_BASE + SRAM1_SIZE - 1U))) || \
|
||||
(((__VALUE__) >= SRAM2A_BASE) && ((__VALUE__) <= (SRAM2A_BASE + SRAM2A_SIZE - 1U))) || \
|
||||
(((__VALUE__) >= SRAM2B_BASE) && ((__VALUE__) <= (SRAM2B_BASE + SRAM2B_SIZE - 1U))))
|
||||
|
||||
#define IS_OB_BOOT_REGION(__VALUE__) (((__VALUE__) == OB_C2_BOOT_FROM_FLASH) || ((__VALUE__) == OB_C2_BOOT_FROM_SRAM))
|
||||
|
||||
#define IS_OB_SECURE_CONFIG(__VALUE__) (((__VALUE__) & ~(OB_SECURE_CONFIG_MEMORY | OB_SECURE_CONFIG_BOOT_RESET)) == 0U)
|
||||
|
||||
#define IS_FLASH_LATENCY(__VALUE__) (((__VALUE__) == FLASH_LATENCY_0) || \
|
||||
((__VALUE__) == FLASH_LATENCY_1) || \
|
||||
((__VALUE__) == FLASH_LATENCY_2) || \
|
||||
((__VALUE__) == FLASH_LATENCY_3))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32WBxx_HAL_FLASH_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -1,141 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32wbxx_hal_flash_ex.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of FLASH HAL Extended module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32WBxx_HAL_FLASH_EX_H
|
||||
#define STM32WBxx_HAL_FLASH_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32wbxx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32WBxx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup FLASHEx
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup FLASHEx_Exported_Constants FLASH Exported Constants
|
||||
* @{
|
||||
*/
|
||||
/** @defgroup FLASHEx_EMPTY_CHECK FLASHEx Empty Check
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_PROG_NOT_EMPTY 0x00000000U /*!< 1st location in Flash is programmed */
|
||||
#define FLASH_PROG_EMPTY FLASH_ACR_EMPTY /*!< 1st location in Flash is empty */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup FLASHEx_ECC_CPUID FLASHEx ECC CPU Identification
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_ECC_CPUID_1 0x00000000U /*!< Bus-ID of the CPU1 access causing the ECC failure. */
|
||||
#define FLASH_ECC_CPUID_2 FLASH_ECCR_CPUID_0 /*!< Bus-ID of the CPU2 access causing the ECC failure. */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup FLASH_ECC FLASH ECC Macros
|
||||
* @brief macros to get Error Code Correction informations
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Get the Bus-ID of the CPU access causing the ECC failure
|
||||
* @retval CPUID
|
||||
*/
|
||||
#define __HAL_FLASH_ECC_CPUID() READ_BIT(FLASH->ECCR, FLASH_ECCR_CPUID)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup FLASHEx_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Extended Program operation functions *************************************/
|
||||
/** @addtogroup FLASHEx_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError);
|
||||
HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit);
|
||||
uint32_t HAL_FLASHEx_FlashEmptyCheck(void);
|
||||
void HAL_FLASHEx_ForceFlashEmpty(uint32_t FlashEmpty);
|
||||
HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit);
|
||||
void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);
|
||||
void HAL_FLASHEx_SuspendOperation(void);
|
||||
void HAL_FLASHEx_AllowOperation(void);
|
||||
uint32_t HAL_FLASHEx_IsOperationSuspended(void);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup FLASHEx_Private_Macros FLASHEx Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_FLASH_EMPTY_CHECK(__VALUE__) (((__VALUE__) == FLASH_PROG_EMPTY) || ((__VALUE__) == FLASH_PROG_NOT_EMPTY))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private Functions ---------------------------------------------------------*/
|
||||
/** @defgroup FLASHEx_Private_Functions FLASHEx Private Functions
|
||||
* @{
|
||||
*/
|
||||
void FLASH_PageErase(uint32_t Page);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32WBxx_HAL_FLASH_EX_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -1,327 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32wbxx_hal_gpio.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of GPIO HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32WBxx_HAL_GPIO_H
|
||||
#define STM32WBxx_HAL_GPIO_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32wbxx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32WBxx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO GPIO
|
||||
* @brief GPIO HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup GPIO_Exported_Types GPIO Exported Types
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief GPIO Init structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Pin; /*!< Specifies the GPIO pins to be configured.
|
||||
This parameter can be any value of @ref GPIO_pins */
|
||||
|
||||
uint32_t Mode; /*!< Specifies the operating mode for the selected pins.
|
||||
This parameter can be a value of @ref GPIO_mode */
|
||||
|
||||
uint32_t Pull; /*!< Specifies the Pull-up or Pull-Down activation for the selected pins.
|
||||
This parameter can be a value of @ref GPIO_pull */
|
||||
|
||||
uint32_t Speed; /*!< Specifies the speed for the selected pins.
|
||||
This parameter can be a value of @ref GPIO_speed */
|
||||
|
||||
uint32_t Alternate; /*!< Peripheral to be connected to the selected pins
|
||||
This parameter can be a value of @ref GPIOEx_Alternate_function_selection */
|
||||
} GPIO_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief GPIO Bit SET and Bit RESET enumeration
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
GPIO_PIN_RESET = 0U,
|
||||
GPIO_PIN_SET
|
||||
} GPIO_PinState;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup GPIO_Exported_Constants GPIO Exported Constants
|
||||
* @{
|
||||
*/
|
||||
/** @defgroup GPIO_pins GPIO pins
|
||||
* @{
|
||||
*/
|
||||
#define GPIO_PIN_0 ((uint16_t)0x0001) /* Pin 0 selected */
|
||||
#define GPIO_PIN_1 ((uint16_t)0x0002) /* Pin 1 selected */
|
||||
#define GPIO_PIN_2 ((uint16_t)0x0004) /* Pin 2 selected */
|
||||
#define GPIO_PIN_3 ((uint16_t)0x0008) /* Pin 3 selected */
|
||||
#define GPIO_PIN_4 ((uint16_t)0x0010) /* Pin 4 selected */
|
||||
#define GPIO_PIN_5 ((uint16_t)0x0020) /* Pin 5 selected */
|
||||
#define GPIO_PIN_6 ((uint16_t)0x0040) /* Pin 6 selected */
|
||||
#define GPIO_PIN_7 ((uint16_t)0x0080) /* Pin 7 selected */
|
||||
#define GPIO_PIN_8 ((uint16_t)0x0100) /* Pin 8 selected */
|
||||
#define GPIO_PIN_9 ((uint16_t)0x0200) /* Pin 9 selected */
|
||||
#define GPIO_PIN_10 ((uint16_t)0x0400) /* Pin 10 selected */
|
||||
#define GPIO_PIN_11 ((uint16_t)0x0800) /* Pin 11 selected */
|
||||
#define GPIO_PIN_12 ((uint16_t)0x1000) /* Pin 12 selected */
|
||||
#define GPIO_PIN_13 ((uint16_t)0x2000) /* Pin 13 selected */
|
||||
#define GPIO_PIN_14 ((uint16_t)0x4000) /* Pin 14 selected */
|
||||
#define GPIO_PIN_15 ((uint16_t)0x8000) /* Pin 15 selected */
|
||||
#define GPIO_PIN_All ((uint16_t)0xFFFF) /* All pins selected */
|
||||
|
||||
#define GPIO_PIN_MASK ((uint32_t)0x0000FFFF) /* PIN mask for assert test */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_mode GPIO mode
|
||||
* @brief GPIO Configuration Mode
|
||||
* Elements values convention: 0x00WX00YZ
|
||||
* - W : EXTI trigger detection on 3 bits
|
||||
* - X : EXTI mode (IT or Event) on 2 bits
|
||||
* - Y : Output type (Push Pull or Open Drain) on 1 bit
|
||||
* - Z : GPIO mode (Input, Output, Alternate or Analog) on 2 bits
|
||||
* @{
|
||||
*/
|
||||
#define GPIO_MODE_INPUT MODE_INPUT /*!< Input Floating Mode */
|
||||
#define GPIO_MODE_OUTPUT_PP (MODE_OUTPUT | OUTPUT_PP) /*!< Output Push Pull Mode */
|
||||
#define GPIO_MODE_OUTPUT_OD (MODE_OUTPUT | OUTPUT_OD) /*!< Output Open Drain Mode */
|
||||
#define GPIO_MODE_AF_PP (MODE_AF | OUTPUT_PP) /*!< Alternate Function Push Pull Mode */
|
||||
#define GPIO_MODE_AF_OD (MODE_AF | OUTPUT_OD) /*!< Alternate Function Open Drain Mode */
|
||||
#define GPIO_MODE_ANALOG MODE_ANALOG /*!< Analog Mode */
|
||||
#define GPIO_MODE_IT_RISING (MODE_INPUT | EXTI_IT | TRIGGER_RISING) /*!< External Interrupt Mode with Rising edge trigger detection */
|
||||
#define GPIO_MODE_IT_FALLING (MODE_INPUT | EXTI_IT | TRIGGER_FALLING) /*!< External Interrupt Mode with Falling edge trigger detection */
|
||||
#define GPIO_MODE_IT_RISING_FALLING (MODE_INPUT | EXTI_IT | TRIGGER_RISING | TRIGGER_FALLING) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
|
||||
#define GPIO_MODE_EVT_RISING (MODE_INPUT | EXTI_EVT | TRIGGER_RISING) /*!< External Event Mode with Rising edge trigger detection */
|
||||
#define GPIO_MODE_EVT_FALLING (MODE_INPUT | EXTI_EVT | TRIGGER_FALLING) /*!< External Event Mode with Falling edge trigger detection */
|
||||
#define GPIO_MODE_EVT_RISING_FALLING (MODE_INPUT | EXTI_EVT | TRIGGER_RISING | TRIGGER_FALLING) /*!< External Event Mode with Rising/Falling edge trigger detection */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_speed GPIO speed
|
||||
* @brief GPIO Output Maximum frequency
|
||||
* @{
|
||||
*/
|
||||
#define GPIO_SPEED_FREQ_LOW 0x00000000u /*!< Low speed */
|
||||
#define GPIO_SPEED_FREQ_MEDIUM 0x00000001u /*!< Medium speed */
|
||||
#define GPIO_SPEED_FREQ_HIGH 0x00000002u /*!< High speed */
|
||||
#define GPIO_SPEED_FREQ_VERY_HIGH 0x00000003u /*!< Very high speed */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_pull GPIO pull
|
||||
* @brief GPIO Pull-Up or Pull-Down Activation
|
||||
* @{
|
||||
*/
|
||||
#define GPIO_NOPULL 0x00000000u /*!< No Pull-up or Pull-down activation */
|
||||
#define GPIO_PULLUP 0x00000001u /*!< Pull-up activation */
|
||||
#define GPIO_PULLDOWN 0x00000002u /*!< Pull-down activation */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup GPIO_Exported_Macros GPIO Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Check whether the specified EXTI line flag is set or not.
|
||||
* @param __EXTI_LINE__ specifies the EXTI line flag to check.
|
||||
* This parameter can be GPIO_PIN_x where x can be(0..15)
|
||||
* @retval The new state of __EXTI_LINE__ (SET or RESET).
|
||||
*/
|
||||
#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR1 & (__EXTI_LINE__))
|
||||
|
||||
/**
|
||||
* @brief Clear the EXTI's line pending flags.
|
||||
* @param __EXTI_LINE__ specifies the EXTI lines flags to clear.
|
||||
* This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR1 = (__EXTI_LINE__))
|
||||
|
||||
/**
|
||||
* @brief Check whether the specified EXTI line is asserted or not.
|
||||
* @param __EXTI_LINE__ specifies the EXTI line to check.
|
||||
* This parameter can be GPIO_PIN_x where x can be(0..15)
|
||||
* @retval The new state of __EXTI_LINE__ (SET or RESET).
|
||||
*/
|
||||
#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR1 & (__EXTI_LINE__))
|
||||
|
||||
/**
|
||||
* @brief Clear the EXTI's line pending bits.
|
||||
* @param __EXTI_LINE__ specifies the EXTI lines to clear.
|
||||
* This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR1 = (__EXTI_LINE__))
|
||||
|
||||
/**
|
||||
* @brief Generate a Software interrupt on selected EXTI line.
|
||||
* @param __EXTI_LINE__ specifies the EXTI line to check.
|
||||
* This parameter can be GPIO_PIN_x where x can be(0..15)
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER1 |= (__EXTI_LINE__))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup GPIO_Private_Constants GPIO Private Constants
|
||||
* @{
|
||||
*/
|
||||
#define GPIO_MODE_Pos 0u
|
||||
#define GPIO_MODE (0x3uL << GPIO_MODE_Pos)
|
||||
#define MODE_INPUT (0x0uL << GPIO_MODE_Pos)
|
||||
#define MODE_OUTPUT (0x1uL << GPIO_MODE_Pos)
|
||||
#define MODE_AF (0x2uL << GPIO_MODE_Pos)
|
||||
#define MODE_ANALOG (0x3uL << GPIO_MODE_Pos)
|
||||
#define OUTPUT_TYPE_Pos 4u
|
||||
#define OUTPUT_TYPE (0x1uL << OUTPUT_TYPE_Pos)
|
||||
#define OUTPUT_PP (0x0uL << OUTPUT_TYPE_Pos)
|
||||
#define OUTPUT_OD (0x1uL << OUTPUT_TYPE_Pos)
|
||||
#define EXTI_MODE_Pos 16u
|
||||
#define EXTI_MODE (0x3uL << EXTI_MODE_Pos)
|
||||
#define EXTI_IT (0x1uL << EXTI_MODE_Pos)
|
||||
#define EXTI_EVT (0x2uL << EXTI_MODE_Pos)
|
||||
#define TRIGGER_MODE_Pos 20u
|
||||
#define TRIGGER_MODE (0x7uL << TRIGGER_MODE_Pos)
|
||||
#define TRIGGER_RISING (0x1uL << TRIGGER_MODE_Pos)
|
||||
#define TRIGGER_FALLING (0x2uL << TRIGGER_MODE_Pos)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_Private_Macros GPIO Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
|
||||
|
||||
#define IS_GPIO_PIN(__PIN__) ((((uint32_t)(__PIN__) & GPIO_PIN_MASK) != 0x00u) &&\
|
||||
(((uint32_t)(__PIN__) & ~GPIO_PIN_MASK) == 0x00u))
|
||||
|
||||
#define IS_GPIO_MODE(__MODE__) (((__MODE__) == GPIO_MODE_INPUT) ||\
|
||||
((__MODE__) == GPIO_MODE_OUTPUT_PP) ||\
|
||||
((__MODE__) == GPIO_MODE_OUTPUT_OD) ||\
|
||||
((__MODE__) == GPIO_MODE_AF_PP) ||\
|
||||
((__MODE__) == GPIO_MODE_AF_OD) ||\
|
||||
((__MODE__) == GPIO_MODE_IT_RISING) ||\
|
||||
((__MODE__) == GPIO_MODE_IT_FALLING) ||\
|
||||
((__MODE__) == GPIO_MODE_IT_RISING_FALLING) ||\
|
||||
((__MODE__) == GPIO_MODE_EVT_RISING) ||\
|
||||
((__MODE__) == GPIO_MODE_EVT_FALLING) ||\
|
||||
((__MODE__) == GPIO_MODE_EVT_RISING_FALLING) ||\
|
||||
((__MODE__) == GPIO_MODE_ANALOG))
|
||||
|
||||
#define IS_GPIO_SPEED(__SPEED__) (((__SPEED__) == GPIO_SPEED_FREQ_LOW) ||\
|
||||
((__SPEED__) == GPIO_SPEED_FREQ_MEDIUM) ||\
|
||||
((__SPEED__) == GPIO_SPEED_FREQ_HIGH) ||\
|
||||
((__SPEED__) == GPIO_SPEED_FREQ_VERY_HIGH))
|
||||
|
||||
#define IS_GPIO_PULL(__PULL__) (((__PULL__) == GPIO_NOPULL) ||\
|
||||
((__PULL__) == GPIO_PULLUP) || \
|
||||
((__PULL__) == GPIO_PULLDOWN))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Include GPIO HAL Extended module */
|
||||
#include "stm32wbxx_hal_gpio_ex.h"
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup GPIO_Exported_Functions GPIO Exported Functions
|
||||
* @brief GPIO Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_Exported_Functions_Group1 Initialization/de-initialization functions
|
||||
* @brief Initialization and Configuration functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Initialization and de-initialization functions *****************************/
|
||||
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init);
|
||||
void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_Exported_Functions_Group2 IO operation functions
|
||||
* @brief IO operation functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* IO operation functions *****************************************************/
|
||||
GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
|
||||
void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState);
|
||||
void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
|
||||
HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
|
||||
void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin);
|
||||
void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32WBxx_HAL_GPIO_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -1,682 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32wbxx_hal_gpio_ex.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of GPIO HAL Extended module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32WBxx_HAL_GPIO_EX_H
|
||||
#define STM32WBxx_HAL_GPIO_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32wbxx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32WBxx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup GPIOEx GPIOEx
|
||||
* @brief GPIO Extended HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup GPIOEx_Exported_Constants GPIOEx Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup GPIOEx_Alternate_function_selection GPIOEx Alternate function selection
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/* The table below gives an overview of the different alternate functions per port.
|
||||
* For more details refer yourself to the product data sheet.
|
||||
*
|
||||
*/
|
||||
|
||||
#if defined (STM32WB55xx) || defined (STM32WB5Mxx)
|
||||
/**
|
||||
* @brief AF 0 selection
|
||||
*/
|
||||
#define GPIO_AF0_MCO ((uint8_t)0x00) /*!< MCO Alternate Function mapping */
|
||||
#define GPIO_AF0_LSCO ((uint8_t)0x00) /*!< LSCO Alternate Function mapping */
|
||||
#define GPIO_AF0_JTMS_SWDIO ((uint8_t)0x00) /*!< JTMS-SWDIO Alternate Function mapping */
|
||||
#define GPIO_AF0_JTCK_SWCLK ((uint8_t)0x00) /*!< JTCK-SWCLK Alternate Function mapping */
|
||||
#define GPIO_AF0_JTDI ((uint8_t)0x00) /*!< JTDI Alternate Function mapping */
|
||||
#define GPIO_AF0_RTC_OUT ((uint8_t)0x00) /*!< RCT_OUT Alternate Function mapping */
|
||||
#define GPIO_AF0_JTD_TRACE ((uint8_t)0x00) /*!< JTDO-TRACESWO Alternate Function mapping */
|
||||
#define GPIO_AF0_NJTRST ((uint8_t)0x00) /*!< NJTRST Alternate Function mapping */
|
||||
#define GPIO_AF0_RTC_REFIN ((uint8_t)0x00) /*!< RTC_REFIN Alternate Function mapping */
|
||||
#define GPIO_AF0_TRACED0 ((uint8_t)0x00) /*!< TRACED0 Alternate Function mapping */
|
||||
#define GPIO_AF0_TRACED1 ((uint8_t)0x00) /*!< TRACED1 Alternate Function mapping */
|
||||
#define GPIO_AF0_TRACED2 ((uint8_t)0x00) /*!< TRACED2 Alternate Function mapping */
|
||||
#define GPIO_AF0_TRACED3 ((uint8_t)0x00) /*!< TRACED3 Alternate Function mapping */
|
||||
#define GPIO_AF0_TRIG_INOUT ((uint8_t)0x00) /*!< TRIG_INOUT Alternate Function mapping */
|
||||
#define GPIO_AF0_TRACECK ((uint8_t)0x00) /*!< TRACECK Alternate Function mapping */
|
||||
#define GPIO_AF0_SYS ((uint8_t)0x00) /*!< System Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 1 selection
|
||||
*/
|
||||
#define GPIO_AF1_TIM1 ((uint8_t)0x01) /*!< TIM1 Alternate Function mapping */
|
||||
#define GPIO_AF1_TIM2 ((uint8_t)0x01) /*!< TIM2 Alternate Function mapping */
|
||||
#define GPIO_AF1_LPTIM1 ((uint8_t)0x01) /*!< LPTIM1 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 2 selection
|
||||
*/
|
||||
#define GPIO_AF2_TIM2 ((uint8_t)0x02) /*!< TIM2 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM1 ((uint8_t)0x02) /*!< TIM1 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 3 selection
|
||||
*/
|
||||
#define GPIO_AF3_SAI1 ((uint8_t)0x03) /*!< SAI1_CK1 Alternate Function mapping */
|
||||
#define GPIO_AF3_SPI2 ((uint8_t)0x03) /*!< SPI2 Alternate Function mapping */
|
||||
#define GPIO_AF3_TIM1 ((uint8_t)0x03) /*!< TIM1 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 4 selection
|
||||
*/
|
||||
#define GPIO_AF4_I2C1 ((uint8_t)0x04) /*!< I2C1 Alternate Function mapping */
|
||||
#define GPIO_AF4_I2C3 ((uint8_t)0x04) /*!< I2C3 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 5 selection
|
||||
*/
|
||||
#define GPIO_AF5_SPI1 ((uint8_t)0x05) /*!< SPI1 Alternate Function mapping */
|
||||
#define GPIO_AF5_SPI2 ((uint8_t)0x05) /*!< SPI2 Alternate Function mapping */
|
||||
/**
|
||||
* @brief AF 6 selection
|
||||
*/
|
||||
#define GPIO_AF6_MCO ((uint8_t)0x06) /*!< MCO Alternate Function mapping */
|
||||
#define GPIO_AF6_LSCO ((uint8_t)0x06) /*!< LSCO Alternate Function mapping */
|
||||
#define GPIO_AF6_RF_DTB0 ((uint8_t)0x06) /*!< RF_DTB0 Alternate Function mapping */
|
||||
#define GPIO_AF6_RF_DTB1 ((uint8_t)0x06) /*!< RF_DTB1 Alternate Function mapping */
|
||||
#define GPIO_AF6_RF_DTB2 ((uint8_t)0x06) /*!< RF_DTB2 Alternate Function mapping */
|
||||
#define GPIO_AF6_RF_DTB3 ((uint8_t)0x06) /*!< RF_DTB3 Alternate Function mapping */
|
||||
#define GPIO_AF6_RF_DTB4 ((uint8_t)0x06) /*!< RF_DTB4 Alternate Function mapping */
|
||||
#define GPIO_AF6_RF_DTB5 ((uint8_t)0x06) /*!< RF_DTB5 Alternate Function mapping */
|
||||
#define GPIO_AF6_RF_DTB6 ((uint8_t)0x06) /*!< RF_DTB6 Alternate Function mapping */
|
||||
#define GPIO_AF6_RF_DTB7 ((uint8_t)0x06) /*!< RF_DTB7 Alternate Function mapping */
|
||||
#define GPIO_AF6_RF_DTB8 ((uint8_t)0x06) /*!< RF_DTB8 Alternate Function mapping */
|
||||
#define GPIO_AF6_RF_DTB9 ((uint8_t)0x06) /*!< RF_DTB9 Alternate Function mapping */
|
||||
#define GPIO_AF6_RF_DTB10 ((uint8_t)0x06) /*!< RF_DTB10 Alternate Function mapping */
|
||||
#define GPIO_AF6_RF_DTB11 ((uint8_t)0x06) /*!< RF_DTB11 Alternate Function mapping */
|
||||
#define GPIO_AF6_RF_DTB12 ((uint8_t)0x06) /*!< RF_DTB12 Alternate Function mapping */
|
||||
#define GPIO_AF6_RF_DTB13 ((uint8_t)0x06) /*!< RF_DTB13 Alternate Function mapping */
|
||||
#define GPIO_AF6_RF_DTB14 ((uint8_t)0x06) /*!< RF_DTB14 Alternate Function mapping */
|
||||
#define GPIO_AF6_RF_DTB15 ((uint8_t)0x06) /*!< RF_DTB15 Alternate Function mapping */
|
||||
#define GPIO_AF6_RF_DTB16 ((uint8_t)0x06) /*!< RF_DTB16 Alternate Function mapping */
|
||||
#define GPIO_AF6_RF_DTB17 ((uint8_t)0x06) /*!< RF_DTB17 Alternate Function mapping */
|
||||
#define GPIO_AF6_RF_DTB18 ((uint8_t)0x06) /*!< RF_DTB18 Alternate Function mapping */
|
||||
#define GPIO_AF6_RF_MISO ((uint8_t)0x06) /*!< RF_MISO Alternate Function mapping */
|
||||
#define GPIO_AF6_RF_MOSI ((uint8_t)0x06) /*!< RF_MOSI Alternate Function mapping */
|
||||
#define GPIO_AF6_RF_SCK ((uint8_t)0x06) /*!< RF_SCK Alternate Function mapping */
|
||||
#define GPIO_AF6_RF_NSS ((uint8_t)0x06) /*!< RF_NSS Alternate Function mapping */
|
||||
/**
|
||||
* @brief AF 7 selection
|
||||
*/
|
||||
#define GPIO_AF7_USART1 ((uint8_t)0x07) /*!< USART1 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 8 selection
|
||||
*/
|
||||
#define GPIO_AF8_LPUART1 ((uint8_t)0x08) /*!< LPUART1 Alternate Function mapping */
|
||||
#define GPIO_AF8_IR ((uint8_t)0x08) /*!< IR Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 9 selection
|
||||
*/
|
||||
#define GPIO_AF9_TSC ((uint8_t)0x09) /*!< TSC Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 10 selection
|
||||
*/
|
||||
#define GPIO_AF10_QUADSPI ((uint8_t)0x0a) /*!< QUADSPI Alternate Function mapping */
|
||||
#define GPIO_AF10_USB ((uint8_t)0x0a) /*!< USB Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 11 selection
|
||||
*/
|
||||
#define GPIO_AF11_LCD ((uint8_t)0x0b) /*!< LCD Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 12 selection
|
||||
*/
|
||||
#define GPIO_AF12_COMP1 ((uint8_t)0x0c) /*!< COMP1 Alternate Function mapping */
|
||||
#define GPIO_AF12_COMP2 ((uint8_t)0x0c) /*!< COMP2 Alternate Function mapping */
|
||||
#define GPIO_AF12_TIM1 ((uint8_t)0x0c) /*!< TIM1 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 13 selection
|
||||
*/
|
||||
#define GPIO_AF13_SAI1 ((uint8_t)0x0d) /*!< SAI1 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 14 selection
|
||||
*/
|
||||
#define GPIO_AF14_TIM2 ((uint8_t)0x0e) /*!< TIM2 Alternate Function mapping */
|
||||
#define GPIO_AF14_TIM16 ((uint8_t)0x0e) /*!< TIM16 Alternate Function mapping */
|
||||
#define GPIO_AF14_TIM17 ((uint8_t)0x0e) /*!< TIM17 Alternate Function mapping */
|
||||
#define GPIO_AF14_LPTIM2 ((uint8_t)0x0e) /*!< LPTIM2 Alternate Function mapping */
|
||||
|
||||
|
||||
/**
|
||||
* @brief AF 15 selection
|
||||
*/
|
||||
#define GPIO_AF15_EVENTOUT ((uint8_t)0x0f) /*!< EVENTOUT Alternate Function mapping */
|
||||
|
||||
#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x0f)
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
#if defined (STM32WB50xx)
|
||||
/**
|
||||
* @brief AF 0 selection
|
||||
*/
|
||||
#define GPIO_AF0_MCO ((uint8_t)0x00) /*!< MCO Alternate Function mapping */
|
||||
#define GPIO_AF0_LSCO ((uint8_t)0x00) /*!< LSCO Alternate Function mapping */
|
||||
#define GPIO_AF0_JTMS_SWDIO ((uint8_t)0x00) /*!< JTMS-SWDIO Alternate Function mapping */
|
||||
#define GPIO_AF0_JTCK_SWCLK ((uint8_t)0x00) /*!< JTCK-SWCLK Alternate Function mapping */
|
||||
#define GPIO_AF0_JTDI ((uint8_t)0x00) /*!< JTDI Alternate Function mapping */
|
||||
#define GPIO_AF0_RTC_OUT ((uint8_t)0x00) /*!< RCT_OUT Alternate Function mapping */
|
||||
#define GPIO_AF0_JTD_TRACE ((uint8_t)0x00) /*!< JTDO-TRACESWO Alternate Function mapping */
|
||||
#define GPIO_AF0_NJTRST ((uint8_t)0x00) /*!< NJTRST Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 1 selection
|
||||
*/
|
||||
#define GPIO_AF1_TIM1 ((uint8_t)0x01) /*!< TIM1 Alternate Function mapping */
|
||||
#define GPIO_AF1_TIM2 ((uint8_t)0x01) /*!< TIM2 Alternate Function mapping */
|
||||
#define GPIO_AF1_LPTIM1 ((uint8_t)0x01) /*!< LPTIM1 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 2 selection
|
||||
*/
|
||||
#define GPIO_AF2_TIM1 ((uint8_t)0x02) /*!< TIM1 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM2 ((uint8_t)0x02) /*!< TIM2 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 3 selection
|
||||
*/
|
||||
#define GPIO_AF3_TIM1 ((uint8_t)0x03) /*!< TIM1 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 4 selection
|
||||
*/
|
||||
#define GPIO_AF4_I2C1 ((uint8_t)0x04) /*!< I2C1 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 5 selection
|
||||
*/
|
||||
#define GPIO_AF5_SPI1 ((uint8_t)0x05) /*!< SPI1 Alternate Function mapping */
|
||||
/**
|
||||
* @brief AF 6 selection
|
||||
*/
|
||||
#define GPIO_AF6_MCO ((uint8_t)0x06) /*!< MCO Alternate Function mapping */
|
||||
#define GPIO_AF6_LSCO ((uint8_t)0x06) /*!< LSCO Alternate Function mapping */
|
||||
#define GPIO_AF6_RF_DTB0 ((uint8_t)0x06) /*!< RF_DTB0 Alternate Function mapping */
|
||||
#define GPIO_AF6_RF_DTB1 ((uint8_t)0x06) /*!< RF_DTB1 Alternate Function mapping */
|
||||
#define GPIO_AF6_RF_DTB2 ((uint8_t)0x06) /*!< RF_DTB2 Alternate Function mapping */
|
||||
#define GPIO_AF6_RF_DTB3 ((uint8_t)0x06) /*!< RF_DTB3 Alternate Function mapping */
|
||||
#define GPIO_AF6_RF_DTB4 ((uint8_t)0x06) /*!< RF_DTB4 Alternate Function mapping */
|
||||
#define GPIO_AF6_RF_DTB5 ((uint8_t)0x06) /*!< RF_DTB5 Alternate Function mapping */
|
||||
#define GPIO_AF6_RF_DTB6 ((uint8_t)0x06) /*!< RF_DTB6 Alternate Function mapping */
|
||||
#define GPIO_AF6_RF_DTB7 ((uint8_t)0x06) /*!< RF_DTB7 Alternate Function mapping */
|
||||
#define GPIO_AF6_RF_DTB8 ((uint8_t)0x06) /*!< RF_DTB8 Alternate Function mapping */
|
||||
#define GPIO_AF6_RF_DTB9 ((uint8_t)0x06) /*!< RF_DTB9 Alternate Function mapping */
|
||||
#define GPIO_AF6_RF_DTB10 ((uint8_t)0x06) /*!< RF_DTB10 Alternate Function mapping */
|
||||
#define GPIO_AF6_RF_DTB11 ((uint8_t)0x06) /*!< RF_DTB11 Alternate Function mapping */
|
||||
#define GPIO_AF6_RF_DTB12 ((uint8_t)0x06) /*!< RF_DTB12 Alternate Function mapping */
|
||||
#define GPIO_AF6_RF_DTB13 ((uint8_t)0x06) /*!< RF_DTB13 Alternate Function mapping */
|
||||
#define GPIO_AF6_RF_DTB14 ((uint8_t)0x06) /*!< RF_DTB14 Alternate Function mapping */
|
||||
#define GPIO_AF6_RF_DTB15 ((uint8_t)0x06) /*!< RF_DTB15 Alternate Function mapping */
|
||||
#define GPIO_AF6_RF_DTB16 ((uint8_t)0x06) /*!< RF_DTB16 Alternate Function mapping */
|
||||
#define GPIO_AF6_RF_DTB17 ((uint8_t)0x06) /*!< RF_DTB17 Alternate Function mapping */
|
||||
#define GPIO_AF6_RF_DTB18 ((uint8_t)0x06) /*!< RF_DTB18 Alternate Function mapping */
|
||||
#define GPIO_AF6_RF_MISO ((uint8_t)0x06) /*!< RF_MISO Alternate Function mapping */
|
||||
#define GPIO_AF6_RF_MOSI ((uint8_t)0x06) /*!< RF_MOSI Alternate Function mapping */
|
||||
#define GPIO_AF6_RF_SCK ((uint8_t)0x06) /*!< RF_SCK Alternate Function mapping */
|
||||
#define GPIO_AF6_RF_NSS ((uint8_t)0x06) /*!< RF_NSS Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 7 selection
|
||||
*/
|
||||
#define GPIO_AF7_USART1 ((uint8_t)0x07) /*!< USART1 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 8 selection
|
||||
*/
|
||||
#define GPIO_AF8_IR ((uint8_t)0x08) /*!< IR Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 12 selection
|
||||
*/
|
||||
#define GPIO_AF12_TIM1 ((uint8_t)0x0c) /*!< TIM1 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 14 selection
|
||||
*/
|
||||
#define GPIO_AF14_TIM2 ((uint8_t)0x0e) /*!< TIM2 Alternate Function mapping */
|
||||
#define GPIO_AF14_TIM16 ((uint8_t)0x0e) /*!< TIM16 Alternate Function mapping */
|
||||
#define GPIO_AF14_TIM17 ((uint8_t)0x0e) /*!< TIM17 Alternate Function mapping */
|
||||
#define GPIO_AF14_LPTIM2 ((uint8_t)0x0e) /*!< LPTIM2 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 15 selection
|
||||
*/
|
||||
#define GPIO_AF15_EVENTOUT ((uint8_t)0x0f) /*!< EVENTOUT Alternate Function mapping */
|
||||
|
||||
#define IS_GPIO_AF(AF) (((AF) <= (uint8_t)0x0F)\
|
||||
&& ((AF) != (uint8_t)0x09) && ((AF) != (uint8_t)0x0A) && ((AF) != (uint8_t)0x0B) && ((AF) != (uint8_t)0x0D))
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
#if defined (STM32WB35xx)
|
||||
/**
|
||||
* @brief AF 0 selection
|
||||
*/
|
||||
#define GPIO_AF0_MCO ((uint8_t)0x00) /*!< MCO Alternate Function mapping */
|
||||
#define GPIO_AF0_LSCO ((uint8_t)0x00) /*!< LSCO Alternate Function mapping */
|
||||
#define GPIO_AF0_JTMS_SWDIO ((uint8_t)0x00) /*!< JTMS-SWDIO Alternate Function mapping */
|
||||
#define GPIO_AF0_JTCK_SWCLK ((uint8_t)0x00) /*!< JTCK-SWCLK Alternate Function mapping */
|
||||
#define GPIO_AF0_JTDI ((uint8_t)0x00) /*!< JTDI Alternate Function mapping */
|
||||
#define GPIO_AF0_RTC_OUT ((uint8_t)0x00) /*!< RCT_OUT Alternate Function mapping */
|
||||
#define GPIO_AF0_JTD_TRACE ((uint8_t)0x00) /*!< JTDO-TRACESWO Alternate Function mapping */
|
||||
#define GPIO_AF0_NJTRST ((uint8_t)0x00) /*!< NJTRST Alternate Function mapping */
|
||||
#define GPIO_AF0_TRACED0 ((uint8_t)0x00) /*!< TRACED0 Alternate Function mapping */
|
||||
#define GPIO_AF0_TRACED1 ((uint8_t)0x00) /*!< TRACED1 Alternate Function mapping */
|
||||
#define GPIO_AF0_TRACED2 ((uint8_t)0x00) /*!< TRACED2 Alternate Function mapping */
|
||||
#define GPIO_AF0_TRACED3 ((uint8_t)0x00) /*!< TRACED3 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 1 selection
|
||||
*/
|
||||
#define GPIO_AF1_TIM1 ((uint8_t)0x01) /*!< TIM1 Alternate Function mapping */
|
||||
#define GPIO_AF1_TIM2 ((uint8_t)0x01) /*!< TIM2 Alternate Function mapping */
|
||||
#define GPIO_AF1_LPTIM1 ((uint8_t)0x01) /*!< LPTIM1 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 2 selection
|
||||
*/
|
||||
#define GPIO_AF2_TIM1 ((uint8_t)0x02) /*!< TIM1 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM2 ((uint8_t)0x02) /*!< TIM2 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 3 selection
|
||||
*/
|
||||
#define GPIO_AF3_SAI1 ((uint8_t)0x03) /*!< SAI1_CK1 Alternate Function mapping */
|
||||
#define GPIO_AF3_TIM1 ((uint8_t)0x03) /*!< TIM1 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 4 selection
|
||||
*/
|
||||
#define GPIO_AF4_I2C1 ((uint8_t)0x04) /*!< I2C1 Alternate Function mapping */
|
||||
#define GPIO_AF4_I2C3 ((uint8_t)0x04) /*!< I2C3 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 5 selection
|
||||
*/
|
||||
#define GPIO_AF5_SPI1 ((uint8_t)0x05) /*!< SPI1 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 6 selection
|
||||
*/
|
||||
#define GPIO_AF6_MCO ((uint8_t)0x06) /*!< MCO Alternate Function mapping */
|
||||
#define GPIO_AF6_LSCO ((uint8_t)0x06) /*!< LSCO Alternate Function mapping */
|
||||
#define GPIO_AF6_RF_DTB0 ((uint8_t)0x06) /*!< RF_DTB0 Alternate Function mapping */
|
||||
#define GPIO_AF6_RF_DTB1 ((uint8_t)0x06) /*!< RF_DTB1 Alternate Function mapping */
|
||||
#define GPIO_AF6_RF_DTB2 ((uint8_t)0x06) /*!< RF_DTB2 Alternate Function mapping */
|
||||
#define GPIO_AF6_RF_DTB3 ((uint8_t)0x06) /*!< RF_DTB3 Alternate Function mapping */
|
||||
#define GPIO_AF6_RF_DTB4 ((uint8_t)0x06) /*!< RF_DTB4 Alternate Function mapping */
|
||||
#define GPIO_AF6_RF_DTB5 ((uint8_t)0x06) /*!< RF_DTB5 Alternate Function mapping */
|
||||
#define GPIO_AF6_RF_DTB6 ((uint8_t)0x06) /*!< RF_DTB6 Alternate Function mapping */
|
||||
#define GPIO_AF6_RF_DTB7 ((uint8_t)0x06) /*!< RF_DTB7 Alternate Function mapping */
|
||||
#define GPIO_AF6_RF_DTB8 ((uint8_t)0x06) /*!< RF_DTB8 Alternate Function mapping */
|
||||
#define GPIO_AF6_RF_DTB9 ((uint8_t)0x06) /*!< RF_DTB9 Alternate Function mapping */
|
||||
#define GPIO_AF6_RF_DTB10 ((uint8_t)0x06) /*!< RF_DTB10 Alternate Function mapping */
|
||||
#define GPIO_AF6_RF_DTB11 ((uint8_t)0x06) /*!< RF_DTB11 Alternate Function mapping */
|
||||
#define GPIO_AF6_RF_DTB12 ((uint8_t)0x06) /*!< RF_DTB12 Alternate Function mapping */
|
||||
#define GPIO_AF6_RF_DTB13 ((uint8_t)0x06) /*!< RF_DTB13 Alternate Function mapping */
|
||||
#define GPIO_AF6_RF_DTB14 ((uint8_t)0x06) /*!< RF_DTB14 Alternate Function mapping */
|
||||
#define GPIO_AF6_RF_DTB15 ((uint8_t)0x06) /*!< RF_DTB15 Alternate Function mapping */
|
||||
#define GPIO_AF6_RF_DTB16 ((uint8_t)0x06) /*!< RF_DTB16 Alternate Function mapping */
|
||||
#define GPIO_AF6_RF_DTB17 ((uint8_t)0x06) /*!< RF_DTB17 Alternate Function mapping */
|
||||
#define GPIO_AF6_RF_DTB18 ((uint8_t)0x06) /*!< RF_DTB18 Alternate Function mapping */
|
||||
#define GPIO_AF6_RF_MISO ((uint8_t)0x06) /*!< RF_MISO Alternate Function mapping */
|
||||
#define GPIO_AF6_RF_MOSI ((uint8_t)0x06) /*!< RF_MOSI Alternate Function mapping */
|
||||
#define GPIO_AF6_RF_SCK ((uint8_t)0x06) /*!< RF_SCK Alternate Function mapping */
|
||||
#define GPIO_AF6_RF_NSS ((uint8_t)0x06) /*!< RF_NSS Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 7 selection
|
||||
*/
|
||||
#define GPIO_AF7_USART1 ((uint8_t)0x07) /*!< USART1 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 8 selection
|
||||
*/
|
||||
#define GPIO_AF8_IR ((uint8_t)0x08) /*!< IR Alternate Function mapping */
|
||||
#define GPIO_AF8_LPUART1 ((uint8_t)0x08) /*!< LPUART1 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 10 selection
|
||||
*/
|
||||
#define GPIO_AF10_QUADSPI ((uint8_t)0x0A) /*!< QUADSPI Alternate Function mapping */
|
||||
#define GPIO_AF10_USB ((uint8_t)0x0A) /*!< USB Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 12 selection
|
||||
*/
|
||||
#define GPIO_AF12_COMP1 ((uint8_t)0x0C) /*!< COMP1 Alternate Function mapping */
|
||||
#define GPIO_AF12_COMP2 ((uint8_t)0x0C) /*!< COMP2 Alternate Function mapping */
|
||||
#define GPIO_AF12_TIM1 ((uint8_t)0x0C) /*!< TIM1 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 13 selection
|
||||
*/
|
||||
#define GPIO_AF13_SAI1 ((uint8_t)0x0d) /*!< SAI1 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 14 selection
|
||||
*/
|
||||
#define GPIO_AF14_LPTIM2 ((uint8_t)0x0E) /*!< LPTIM2 Alternate Function mapping */
|
||||
#define GPIO_AF14_TIM2 ((uint8_t)0x0E) /*!< TIM2 Alternate Function mapping */
|
||||
#define GPIO_AF14_TIM16 ((uint8_t)0x0E) /*!< TIM16 Alternate Function mapping */
|
||||
#define GPIO_AF14_TIM17 ((uint8_t)0x0E) /*!< TIM17 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 15 selection
|
||||
*/
|
||||
#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /*!< EVENTOUT Alternate Function mapping */
|
||||
|
||||
#define IS_GPIO_AF(AF) (((AF) <= (uint8_t)0x0F) && ((AF) != (uint8_t)0x0B) && ((AF) != (uint8_t)0x0D))
|
||||
|
||||
#endif
|
||||
|
||||
#if defined (STM32WB30xx)
|
||||
/**
|
||||
* @brief AF 0 selection
|
||||
*/
|
||||
#define GPIO_AF0_MCO ((uint8_t)0x00) /*!< MCO Alternate Function mapping */
|
||||
#define GPIO_AF0_LSCO ((uint8_t)0x00) /*!< LSCO Alternate Function mapping */
|
||||
#define GPIO_AF0_JTMS_SWDIO ((uint8_t)0x00) /*!< JTMS-SWDIO Alternate Function mapping */
|
||||
#define GPIO_AF0_JTCK_SWCLK ((uint8_t)0x00) /*!< JTCK-SWCLK Alternate Function mapping */
|
||||
#define GPIO_AF0_JTDI ((uint8_t)0x00) /*!< JTDI Alternate Function mapping */
|
||||
#define GPIO_AF0_RTC_OUT ((uint8_t)0x00) /*!< RCT_OUT Alternate Function mapping */
|
||||
#define GPIO_AF0_JTD_TRACE ((uint8_t)0x00) /*!< JTDO-TRACESWO Alternate Function mapping */
|
||||
#define GPIO_AF0_NJTRST ((uint8_t)0x00) /*!< NJTRST Alternate Function mapping */
|
||||
#define GPIO_AF0_TRACED0 ((uint8_t)0x00) /*!< TRACED0 Alternate Function mapping */
|
||||
#define GPIO_AF0_TRACED1 ((uint8_t)0x00) /*!< TRACED1 Alternate Function mapping */
|
||||
#define GPIO_AF0_TRACED2 ((uint8_t)0x00) /*!< TRACED2 Alternate Function mapping */
|
||||
#define GPIO_AF0_TRACED3 ((uint8_t)0x00) /*!< TRACED3 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 1 selection
|
||||
*/
|
||||
#define GPIO_AF1_TIM1 ((uint8_t)0x01) /*!< TIM1 Alternate Function mapping */
|
||||
#define GPIO_AF1_TIM2 ((uint8_t)0x01) /*!< TIM2 Alternate Function mapping */
|
||||
#define GPIO_AF1_LPTIM1 ((uint8_t)0x01) /*!< LPTIM1 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 2 selection
|
||||
*/
|
||||
#define GPIO_AF2_TIM1 ((uint8_t)0x02) /*!< TIM1 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM2 ((uint8_t)0x02) /*!< TIM2 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 3 selection
|
||||
*/
|
||||
#define GPIO_AF3_TIM1 ((uint8_t)0x03) /*!< TIM1 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 4 selection
|
||||
*/
|
||||
#define GPIO_AF4_I2C1 ((uint8_t)0x04) /*!< I2C1 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 5 selection
|
||||
*/
|
||||
#define GPIO_AF5_SPI1 ((uint8_t)0x05) /*!< SPI1 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 6 selection
|
||||
*/
|
||||
#define GPIO_AF6_MCO ((uint8_t)0x06) /*!< MCO Alternate Function mapping */
|
||||
#define GPIO_AF6_LSCO ((uint8_t)0x06) /*!< LSCO Alternate Function mapping */
|
||||
#define GPIO_AF6_RF_DTB0 ((uint8_t)0x06) /*!< RF_DTB0 Alternate Function mapping */
|
||||
#define GPIO_AF6_RF_DTB1 ((uint8_t)0x06) /*!< RF_DTB1 Alternate Function mapping */
|
||||
#define GPIO_AF6_RF_DTB2 ((uint8_t)0x06) /*!< RF_DTB2 Alternate Function mapping */
|
||||
#define GPIO_AF6_RF_DTB3 ((uint8_t)0x06) /*!< RF_DTB3 Alternate Function mapping */
|
||||
#define GPIO_AF6_RF_DTB4 ((uint8_t)0x06) /*!< RF_DTB4 Alternate Function mapping */
|
||||
#define GPIO_AF6_RF_DTB5 ((uint8_t)0x06) /*!< RF_DTB5 Alternate Function mapping */
|
||||
#define GPIO_AF6_RF_DTB6 ((uint8_t)0x06) /*!< RF_DTB6 Alternate Function mapping */
|
||||
#define GPIO_AF6_RF_DTB7 ((uint8_t)0x06) /*!< RF_DTB7 Alternate Function mapping */
|
||||
#define GPIO_AF6_RF_DTB8 ((uint8_t)0x06) /*!< RF_DTB8 Alternate Function mapping */
|
||||
#define GPIO_AF6_RF_DTB9 ((uint8_t)0x06) /*!< RF_DTB9 Alternate Function mapping */
|
||||
#define GPIO_AF6_RF_DTB10 ((uint8_t)0x06) /*!< RF_DTB10 Alternate Function mapping */
|
||||
#define GPIO_AF6_RF_DTB11 ((uint8_t)0x06) /*!< RF_DTB11 Alternate Function mapping */
|
||||
#define GPIO_AF6_RF_DTB12 ((uint8_t)0x06) /*!< RF_DTB12 Alternate Function mapping */
|
||||
#define GPIO_AF6_RF_DTB13 ((uint8_t)0x06) /*!< RF_DTB13 Alternate Function mapping */
|
||||
#define GPIO_AF6_RF_DTB14 ((uint8_t)0x06) /*!< RF_DTB14 Alternate Function mapping */
|
||||
#define GPIO_AF6_RF_DTB15 ((uint8_t)0x06) /*!< RF_DTB15 Alternate Function mapping */
|
||||
#define GPIO_AF6_RF_DTB16 ((uint8_t)0x06) /*!< RF_DTB16 Alternate Function mapping */
|
||||
#define GPIO_AF6_RF_DTB17 ((uint8_t)0x06) /*!< RF_DTB17 Alternate Function mapping */
|
||||
#define GPIO_AF6_RF_DTB18 ((uint8_t)0x06) /*!< RF_DTB18 Alternate Function mapping */
|
||||
#define GPIO_AF6_RF_MISO ((uint8_t)0x06) /*!< RF_MISO Alternate Function mapping */
|
||||
#define GPIO_AF6_RF_MOSI ((uint8_t)0x06) /*!< RF_MOSI Alternate Function mapping */
|
||||
#define GPIO_AF6_RF_SCK ((uint8_t)0x06) /*!< RF_SCK Alternate Function mapping */
|
||||
#define GPIO_AF6_RF_NSS ((uint8_t)0x06) /*!< RF_NSS Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 7 selection
|
||||
*/
|
||||
#define GPIO_AF7_USART1 ((uint8_t)0x07) /*!< USART1 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 8 selection
|
||||
*/
|
||||
#define GPIO_AF8_IR ((uint8_t)0x08) /*!< IR Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 12 selection
|
||||
*/
|
||||
#define GPIO_AF12_TIM1 ((uint8_t)0x0C) /*!< TIM1 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 14 selection
|
||||
*/
|
||||
#define GPIO_AF14_LPTIM2 ((uint8_t)0x0E) /*!< LPTIM2 Alternate Function mapping */
|
||||
#define GPIO_AF14_TIM2 ((uint8_t)0x0E) /*!< TIM2 Alternate Function mapping */
|
||||
#define GPIO_AF14_TIM16 ((uint8_t)0x0E) /*!< TIM16 Alternate Function mapping */
|
||||
#define GPIO_AF14_TIM17 ((uint8_t)0x0E) /*!< TIM17 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 15 selection
|
||||
*/
|
||||
#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /*!< EVENTOUT Alternate Function mapping */
|
||||
|
||||
#define IS_GPIO_AF(AF) (((AF) <= (uint8_t)0x0F)\
|
||||
&& ((AF) != (uint8_t)0x0A) && ((AF) != (uint8_t)0x0B) && ((AF) != (uint8_t)0x0D))
|
||||
|
||||
#endif
|
||||
|
||||
#if defined (STM32WB15xx) || defined (STM32WB10xx)
|
||||
/**
|
||||
* @brief AF 0 selection
|
||||
*/
|
||||
#define GPIO_AF0_MCO ((uint8_t)0x00) /*!< MCO Alternate Function mapping */
|
||||
#define GPIO_AF0_LSCO ((uint8_t)0x00) /*!< LSCO Alternate Function mapping */
|
||||
#define GPIO_AF0_JTMS_SWDIO ((uint8_t)0x00) /*!< JTMS-SWDIO Alternate Function mapping */
|
||||
#define GPIO_AF0_JTCK_SWCLK ((uint8_t)0x00) /*!< JTCK-SWCLK Alternate Function mapping */
|
||||
#define GPIO_AF0_JTDI ((uint8_t)0x00) /*!< JTDI Alternate Function mapping */
|
||||
#define GPIO_AF0_RTC_OUT ((uint8_t)0x00) /*!< RCT_OUT Alternate Function mapping */
|
||||
#define GPIO_AF0_JTD_TRACE ((uint8_t)0x00) /*!< JTDO-TRACESWO Alternate Function mapping */
|
||||
#define GPIO_AF0_NJTRST ((uint8_t)0x00) /*!< NJTRST Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 1 selection
|
||||
*/
|
||||
#define GPIO_AF1_TIM1 ((uint8_t)0x01) /*!< TIM1 Alternate Function mapping */
|
||||
#define GPIO_AF1_TIM2 ((uint8_t)0x01) /*!< TIM2 Alternate Function mapping */
|
||||
#define GPIO_AF1_LPTIM1 ((uint8_t)0x01) /*!< LPTIM1 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 2 selection
|
||||
*/
|
||||
#define GPIO_AF2_TIM2 ((uint8_t)0x02) /*!< TIM2 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM1 ((uint8_t)0x02) /*!< TIM1 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 3 selection
|
||||
*/
|
||||
#define GPIO_AF3_TIM1 ((uint8_t)0x03) /*!< TIM1 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 4 selection
|
||||
*/
|
||||
#define GPIO_AF4_I2C1 ((uint8_t)0x04) /*!< I2C1 Alternate Function mapping */
|
||||
#define GPIO_AF4_SPI1 ((uint8_t)0x04) /*!< SPI1 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 5 selection
|
||||
*/
|
||||
#define GPIO_AF5_SPI1 ((uint8_t)0x05) /*!< SPI1 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 6 selection
|
||||
*/
|
||||
#define GPIO_AF6_MCO ((uint8_t)0x06) /*!< MCO Alternate Function mapping */
|
||||
#define GPIO_AF6_RF_DTB0 ((uint8_t)0x06) /*!< RF_DTB0 Alternate Function mapping */
|
||||
#define GPIO_AF6_RF_DTB1 ((uint8_t)0x06) /*!< RF_DTB1 Alternate Function mapping */
|
||||
#define GPIO_AF6_RF_DTB2 ((uint8_t)0x06) /*!< RF_DTB2 Alternate Function mapping */
|
||||
#define GPIO_AF6_RF_DTB3 ((uint8_t)0x06) /*!< RF_DTB3 Alternate Function mapping */
|
||||
#define GPIO_AF6_RF_DTB4 ((uint8_t)0x06) /*!< RF_DTB4 Alternate Function mapping */
|
||||
#define GPIO_AF6_RF_DTB5 ((uint8_t)0x06) /*!< RF_DTB5 Alternate Function mapping */
|
||||
#define GPIO_AF6_RF_DTB6 ((uint8_t)0x06) /*!< RF_DTB6 Alternate Function mapping */
|
||||
#define GPIO_AF6_RF_DTB7 ((uint8_t)0x06) /*!< RF_DTB7 Alternate Function mapping */
|
||||
#define GPIO_AF6_RF_DTB8 ((uint8_t)0x06) /*!< RF_DTB8 Alternate Function mapping */
|
||||
#define GPIO_AF6_RF_DTB9 ((uint8_t)0x06) /*!< RF_DTB9 Alternate Function mapping */
|
||||
#define GPIO_AF6_RF_DTB10 ((uint8_t)0x06) /*!< RF_DTB10 Alternate Function mapping */
|
||||
#define GPIO_AF6_RF_DTB11 ((uint8_t)0x06) /*!< RF_DTB11 Alternate Function mapping */
|
||||
#define GPIO_AF6_RF_DTB12 ((uint8_t)0x06) /*!< RF_DTB12 Alternate Function mapping */
|
||||
#define GPIO_AF6_RF_DTB13 ((uint8_t)0x06) /*!< RF_DTB13 Alternate Function mapping */
|
||||
#define GPIO_AF6_RF_DTB14 ((uint8_t)0x06) /*!< RF_DTB14 Alternate Function mapping */
|
||||
#define GPIO_AF6_RF_DTB15 ((uint8_t)0x06) /*!< RF_DTB15 Alternate Function mapping */
|
||||
#define GPIO_AF6_RF_DTB16 ((uint8_t)0x06) /*!< RF_DTB16 Alternate Function mapping */
|
||||
#define GPIO_AF6_RF_DTB17 ((uint8_t)0x06) /*!< RF_DTB17 Alternate Function mapping */
|
||||
#define GPIO_AF6_RF_DTB18 ((uint8_t)0x06) /*!< RF_DTB18 Alternate Function mapping */
|
||||
#define GPIO_AF6_RF_MISO ((uint8_t)0x06) /*!< RF_MISO Alternate Function mapping */
|
||||
#define GPIO_AF6_RF_MOSI ((uint8_t)0x06) /*!< RF_MOSI Alternate Function mapping */
|
||||
#define GPIO_AF6_RF_SCK ((uint8_t)0x06) /*!< RF_SCK Alternate Function mapping */
|
||||
#define GPIO_AF6_RF_NSS ((uint8_t)0x06) /*!< RF_NSS Alternate Function mapping */
|
||||
/**
|
||||
* @brief AF 7 selection
|
||||
*/
|
||||
#define GPIO_AF7_USART1 ((uint8_t)0x07) /*!< USART1 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 8 selection
|
||||
*/
|
||||
#define GPIO_AF8_LPUART1 ((uint8_t)0x08) /*!< LPUART1 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 9 selection
|
||||
*/
|
||||
#define GPIO_AF9_TSC ((uint8_t)0x09) /*!< TSC Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 12 selection
|
||||
*/
|
||||
#define GPIO_AF12_COMP1 ((uint8_t)0x0c) /*!< COMP1 Alternate Function mapping */
|
||||
#define GPIO_AF12_TIM1 ((uint8_t)0x0c) /*!< TIM1 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 14 selection
|
||||
*/
|
||||
#define GPIO_AF14_TIM2 ((uint8_t)0x0e) /*!< TIM2 Alternate Function mapping */
|
||||
#define GPIO_AF14_LPTIM2 ((uint8_t)0x0e) /*!< LPTIM2 Alternate Function mapping */
|
||||
|
||||
|
||||
/**
|
||||
* @brief AF 15 selection
|
||||
*/
|
||||
#define GPIO_AF15_EVENTOUT ((uint8_t)0x0f) /*!< EVENTOUT Alternate Function mapping */
|
||||
|
||||
#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x0f)
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup GPIOEx_Exported_Macros GPIOEx Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup GPIOEx_Get_Port_Index GPIOEx Get Port Index
|
||||
* @{
|
||||
*/
|
||||
#if defined (STM32WB55xx) || defined (STM32WB5Mxx)
|
||||
#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0uL :\
|
||||
((__GPIOx__) == (GPIOB))? 1uL :\
|
||||
((__GPIOx__) == (GPIOC))? 2uL :\
|
||||
((__GPIOx__) == (GPIOD))? 3uL :\
|
||||
((__GPIOx__) == (GPIOE))? 4uL : 7uL)
|
||||
#else
|
||||
#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0uL :\
|
||||
((__GPIOx__) == (GPIOB))? 1uL :\
|
||||
((__GPIOx__) == (GPIOC))? 2uL :\
|
||||
((__GPIOx__) == (GPIOE))? 4uL : 7uL)
|
||||
#endif
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32WBxx_HAL_GPIO_EX_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -1,210 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32wbxx_hal_hsem.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of HSEM HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32WBxx_HAL_HSEM_H
|
||||
#define STM32WBxx_HAL_HSEM_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32wbxx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32WBxx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup HSEM
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup HSEM_Exported_Macros HSEM Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief SemID to mask helper Macro.
|
||||
* @param __SEMID__: semaphore ID from 0 to 31
|
||||
* @retval Semaphore Mask.
|
||||
*/
|
||||
#define __HAL_HSEM_SEMID_TO_MASK(__SEMID__) (1 << (__SEMID__))
|
||||
|
||||
/**
|
||||
* @brief Enables the specified HSEM interrupts.
|
||||
* @param __SEM_MASK__: semaphores Mask
|
||||
* @retval None.
|
||||
*/
|
||||
#if defined(DUAL_CORE)
|
||||
#define __HAL_HSEM_ENABLE_IT(__SEM_MASK__) ((((SCB->CPUID & 0x000000F0) >> 4 )== 0x7) ? \
|
||||
(HSEM->C1IER |= (__SEM_MASK__)) : \
|
||||
(HSEM->C2IER |= (__SEM_MASK__)))
|
||||
#else
|
||||
#define __HAL_HSEM_ENABLE_IT(__SEM_MASK__) (HSEM->IER |= (__SEM_MASK__))
|
||||
#endif /* DUAL_CORE */
|
||||
/**
|
||||
* @brief Disables the specified HSEM interrupts.
|
||||
* @param __SEM_MASK__: semaphores Mask
|
||||
* @retval None.
|
||||
*/
|
||||
#if defined(DUAL_CORE)
|
||||
#define __HAL_HSEM_DISABLE_IT(__SEM_MASK__) ((((SCB->CPUID & 0x000000F0) >> 4 )== 0x7) ? \
|
||||
(HSEM->C1IER &= ~(__SEM_MASK__)) : \
|
||||
(HSEM->C2IER &= ~(__SEM_MASK__)))
|
||||
#else
|
||||
#define __HAL_HSEM_DISABLE_IT(__SEM_MASK__) (HSEM->IER &= ~(__SEM_MASK__))
|
||||
#endif /* DUAL_CORE */
|
||||
|
||||
/**
|
||||
* @brief Checks whether interrupt has occurred or not for semaphores specified by a mask.
|
||||
* @param __SEM_MASK__: semaphores Mask
|
||||
* @retval semaphores Mask : Semaphores where an interrupt occurred.
|
||||
*/
|
||||
#if defined(DUAL_CORE)
|
||||
#define __HAL_HSEM_GET_IT(__SEM_MASK__) ((((SCB->CPUID & 0x000000F0) >> 4 )== 0x7) ? \
|
||||
((__SEM_MASK__) & HSEM->C1MISR) : \
|
||||
((__SEM_MASK__) & HSEM->C2MISR1))
|
||||
#else
|
||||
#define __HAL_HSEM_GET_IT(__SEM_MASK__) ((__SEM_MASK__) & HSEM->MISR)
|
||||
#endif /* DUAL_CORE */
|
||||
|
||||
/**
|
||||
* @brief Get the semaphores release status flags.
|
||||
* @param __SEM_MASK__: semaphores Mask
|
||||
* @retval semaphores Mask : Semaphores where Release flags rise.
|
||||
*/
|
||||
#if defined(DUAL_CORE)
|
||||
#define __HAL_HSEM_GET_FLAG(__SEM_MASK__) ((((SCB->CPUID & 0x000000F0) >> 4 )== 0x7) ? \
|
||||
(__SEM_MASK__) & HSEM->C1ISR : \
|
||||
(__SEM_MASK__) & HSEM->C2ISR)
|
||||
#else
|
||||
#define __HAL_HSEM_GET_FLAG(__SEM_MASK__) ((__SEM_MASK__) & HSEM->ISR)
|
||||
#endif /* DUAL_CORE */
|
||||
|
||||
/**
|
||||
* @brief Clears the HSEM Interrupt flags.
|
||||
* @param __SEM_MASK__: semaphores Mask
|
||||
* @retval None.
|
||||
*/
|
||||
#if defined(DUAL_CORE)
|
||||
#define __HAL_HSEM_CLEAR_FLAG(__SEM_MASK__) ((((SCB->CPUID & 0x000000F0) >> 4 )== 0x7) ? \
|
||||
(HSEM->C1ICR |= (__SEM_MASK__)) : \
|
||||
(HSEM->C2ICR |= (__SEM_MASK__)))
|
||||
#else
|
||||
#define __HAL_HSEM_CLEAR_FLAG(__SEM_MASK__) (HSEM->ICR |= (__SEM_MASK__))
|
||||
#endif /* DUAL_CORE */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup HSEM_Exported_Functions HSEM Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup HSEM_Exported_Functions_Group1 Take and Release functions
|
||||
* @brief HSEM Take and Release functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* HSEM semaphore take (lock) using 2-Step method ****************************/
|
||||
HAL_StatusTypeDef HAL_HSEM_Take(uint32_t SemID, uint32_t ProcessID);
|
||||
/* HSEM semaphore fast take (lock) using 1-Step method ***********************/
|
||||
HAL_StatusTypeDef HAL_HSEM_FastTake(uint32_t SemID);
|
||||
/* HSEM Check semaphore state Taken or not **********************************/
|
||||
uint32_t HAL_HSEM_IsSemTaken(uint32_t SemID);
|
||||
/* HSEM Release **************************************************************/
|
||||
void HAL_HSEM_Release(uint32_t SemID, uint32_t ProcessID);
|
||||
/* HSEM Release All************************************************************/
|
||||
void HAL_HSEM_ReleaseAll(uint32_t Key, uint32_t CoreID);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup HSEM_Exported_Functions_Group2 HSEM Set and Get Key functions
|
||||
* @brief HSEM Set and Get Key functions.
|
||||
* @{
|
||||
*/
|
||||
/* HSEM Set Clear Key *********************************************************/
|
||||
void HAL_HSEM_SetClearKey(uint32_t Key);
|
||||
/* HSEM Get Clear Key *********************************************************/
|
||||
uint32_t HAL_HSEM_GetClearKey(void);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup HSEM_Exported_Functions_Group3
|
||||
* @brief HSEM Notification functions
|
||||
* @{
|
||||
*/
|
||||
/* HSEM Activate HSEM Notification (When a semaphore is released) ) *****************/
|
||||
void HAL_HSEM_ActivateNotification(uint32_t SemMask);
|
||||
/* HSEM Deactivate HSEM Notification (When a semaphore is released) ****************/
|
||||
void HAL_HSEM_DeactivateNotification(uint32_t SemMask);
|
||||
/* HSEM Free Callback (When a semaphore is released) *******************************/
|
||||
void HAL_HSEM_FreeCallback(uint32_t SemMask);
|
||||
/* HSEM IRQ Handler **********************************************************/
|
||||
void HAL_HSEM_IRQHandler(void);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup HSEM_Private_Macros HSEM Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_HSEM_SEMID(__SEMID__) ((__SEMID__) <= HSEM_SEMID_MAX )
|
||||
|
||||
#define IS_HSEM_PROCESSID(__PROCESSID__) ((__PROCESSID__) <= HSEM_PROCESSID_MAX )
|
||||
|
||||
#define IS_HSEM_KEY(__KEY__) ((__KEY__) <= HSEM_CLEAR_KEY_MAX )
|
||||
|
||||
#define IS_HSEM_COREID(__COREID__) (((__COREID__) == HSEM_CPU1_COREID) || \
|
||||
((__COREID__) == HSEM_CPU2_COREID))
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32WBxx_HAL_HSEM_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -1,838 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32wbxx_hal_i2c.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of I2C HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32WBxx_HAL_I2C_H
|
||||
#define STM32WBxx_HAL_I2C_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32wbxx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32WBxx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup I2C
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup I2C_Exported_Types I2C Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_Configuration_Structure_definition I2C Configuration Structure definition
|
||||
* @brief I2C Configuration Structure definition
|
||||
* @{
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Timing; /*!< Specifies the I2C_TIMINGR_register value.
|
||||
This parameter calculated by referring to I2C initialization section
|
||||
in Reference manual */
|
||||
|
||||
uint32_t OwnAddress1; /*!< Specifies the first device own address.
|
||||
This parameter can be a 7-bit or 10-bit address. */
|
||||
|
||||
uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode is selected.
|
||||
This parameter can be a value of @ref I2C_ADDRESSING_MODE */
|
||||
|
||||
uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected.
|
||||
This parameter can be a value of @ref I2C_DUAL_ADDRESSING_MODE */
|
||||
|
||||
uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected
|
||||
This parameter can be a 7-bit address. */
|
||||
|
||||
uint32_t OwnAddress2Masks; /*!< Specifies the acknowledge mask address second device own address if dual addressing
|
||||
mode is selected.
|
||||
This parameter can be a value of @ref I2C_OWN_ADDRESS2_MASKS */
|
||||
|
||||
uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected.
|
||||
This parameter can be a value of @ref I2C_GENERAL_CALL_ADDRESSING_MODE */
|
||||
|
||||
uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected.
|
||||
This parameter can be a value of @ref I2C_NOSTRETCH_MODE */
|
||||
|
||||
} I2C_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_state_structure_definition HAL state structure definition
|
||||
* @brief HAL State structure definition
|
||||
* @note HAL I2C State value coding follow below described bitmap :\n
|
||||
* b7-b6 Error information\n
|
||||
* 00 : No Error\n
|
||||
* 01 : Abort (Abort user request on going)\n
|
||||
* 10 : Timeout\n
|
||||
* 11 : Error\n
|
||||
* b5 Peripheral initialization status\n
|
||||
* 0 : Reset (peripheral not initialized)\n
|
||||
* 1 : Init done (peripheral initialized and ready to use. HAL I2C Init function called)\n
|
||||
* b4 (not used)\n
|
||||
* x : Should be set to 0\n
|
||||
* b3\n
|
||||
* 0 : Ready or Busy (No Listen mode ongoing)\n
|
||||
* 1 : Listen (peripheral in Address Listen Mode)\n
|
||||
* b2 Intrinsic process state\n
|
||||
* 0 : Ready\n
|
||||
* 1 : Busy (peripheral busy with some configuration or internal operations)\n
|
||||
* b1 Rx state\n
|
||||
* 0 : Ready (no Rx operation ongoing)\n
|
||||
* 1 : Busy (Rx operation ongoing)\n
|
||||
* b0 Tx state\n
|
||||
* 0 : Ready (no Tx operation ongoing)\n
|
||||
* 1 : Busy (Tx operation ongoing)
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_I2C_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized */
|
||||
HAL_I2C_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use */
|
||||
HAL_I2C_STATE_BUSY = 0x24U, /*!< An internal process is ongoing */
|
||||
HAL_I2C_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing */
|
||||
HAL_I2C_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */
|
||||
HAL_I2C_STATE_LISTEN = 0x28U, /*!< Address Listen Mode is ongoing */
|
||||
HAL_I2C_STATE_BUSY_TX_LISTEN = 0x29U, /*!< Address Listen Mode and Data Transmission
|
||||
process is ongoing */
|
||||
HAL_I2C_STATE_BUSY_RX_LISTEN = 0x2AU, /*!< Address Listen Mode and Data Reception
|
||||
process is ongoing */
|
||||
HAL_I2C_STATE_ABORT = 0x60U, /*!< Abort user request ongoing */
|
||||
HAL_I2C_STATE_TIMEOUT = 0xA0U, /*!< Timeout state */
|
||||
HAL_I2C_STATE_ERROR = 0xE0U /*!< Error */
|
||||
|
||||
} HAL_I2C_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_mode_structure_definition HAL mode structure definition
|
||||
* @brief HAL Mode structure definition
|
||||
* @note HAL I2C Mode value coding follow below described bitmap :\n
|
||||
* b7 (not used)\n
|
||||
* x : Should be set to 0\n
|
||||
* b6\n
|
||||
* 0 : None\n
|
||||
* 1 : Memory (HAL I2C communication is in Memory Mode)\n
|
||||
* b5\n
|
||||
* 0 : None\n
|
||||
* 1 : Slave (HAL I2C communication is in Slave Mode)\n
|
||||
* b4\n
|
||||
* 0 : None\n
|
||||
* 1 : Master (HAL I2C communication is in Master Mode)\n
|
||||
* b3-b2-b1-b0 (not used)\n
|
||||
* xxxx : Should be set to 0000
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_I2C_MODE_NONE = 0x00U, /*!< No I2C communication on going */
|
||||
HAL_I2C_MODE_MASTER = 0x10U, /*!< I2C communication is in Master Mode */
|
||||
HAL_I2C_MODE_SLAVE = 0x20U, /*!< I2C communication is in Slave Mode */
|
||||
HAL_I2C_MODE_MEM = 0x40U /*!< I2C communication is in Memory Mode */
|
||||
|
||||
} HAL_I2C_ModeTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_Error_Code_definition I2C Error Code definition
|
||||
* @brief I2C Error Code definition
|
||||
* @{
|
||||
*/
|
||||
#define HAL_I2C_ERROR_NONE (0x00000000U) /*!< No error */
|
||||
#define HAL_I2C_ERROR_BERR (0x00000001U) /*!< BERR error */
|
||||
#define HAL_I2C_ERROR_ARLO (0x00000002U) /*!< ARLO error */
|
||||
#define HAL_I2C_ERROR_AF (0x00000004U) /*!< ACKF error */
|
||||
#define HAL_I2C_ERROR_OVR (0x00000008U) /*!< OVR error */
|
||||
#define HAL_I2C_ERROR_DMA (0x00000010U) /*!< DMA transfer error */
|
||||
#define HAL_I2C_ERROR_TIMEOUT (0x00000020U) /*!< Timeout error */
|
||||
#define HAL_I2C_ERROR_SIZE (0x00000040U) /*!< Size Management error */
|
||||
#define HAL_I2C_ERROR_DMA_PARAM (0x00000080U) /*!< DMA Parameter Error */
|
||||
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
|
||||
#define HAL_I2C_ERROR_INVALID_CALLBACK (0x00000100U) /*!< Invalid Callback error */
|
||||
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
|
||||
#define HAL_I2C_ERROR_INVALID_PARAM (0x00000200U) /*!< Invalid Parameters error */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_handle_Structure_definition I2C handle Structure definition
|
||||
* @brief I2C handle Structure definition
|
||||
* @{
|
||||
*/
|
||||
typedef struct __I2C_HandleTypeDef
|
||||
{
|
||||
I2C_TypeDef *Instance; /*!< I2C registers base address */
|
||||
|
||||
I2C_InitTypeDef Init; /*!< I2C communication parameters */
|
||||
|
||||
uint8_t *pBuffPtr; /*!< Pointer to I2C transfer buffer */
|
||||
|
||||
uint16_t XferSize; /*!< I2C transfer size */
|
||||
|
||||
__IO uint16_t XferCount; /*!< I2C transfer counter */
|
||||
|
||||
__IO uint32_t XferOptions; /*!< I2C sequantial transfer options, this parameter can
|
||||
be a value of @ref I2C_XFEROPTIONS */
|
||||
|
||||
__IO uint32_t PreviousState; /*!< I2C communication Previous state */
|
||||
|
||||
HAL_StatusTypeDef(*XferISR)(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);
|
||||
/*!< I2C transfer IRQ handler function pointer */
|
||||
|
||||
DMA_HandleTypeDef *hdmatx; /*!< I2C Tx DMA handle parameters */
|
||||
|
||||
DMA_HandleTypeDef *hdmarx; /*!< I2C Rx DMA handle parameters */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< I2C locking object */
|
||||
|
||||
__IO HAL_I2C_StateTypeDef State; /*!< I2C communication state */
|
||||
|
||||
__IO HAL_I2C_ModeTypeDef Mode; /*!< I2C communication mode */
|
||||
|
||||
__IO uint32_t ErrorCode; /*!< I2C Error code */
|
||||
|
||||
__IO uint32_t AddrEventCount; /*!< I2C Address Event counter */
|
||||
|
||||
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
|
||||
void (* MasterTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
|
||||
/*!< I2C Master Tx Transfer completed callback */
|
||||
void (* MasterRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
|
||||
/*!< I2C Master Rx Transfer completed callback */
|
||||
void (* SlaveTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
|
||||
/*!< I2C Slave Tx Transfer completed callback */
|
||||
void (* SlaveRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
|
||||
/*!< I2C Slave Rx Transfer completed callback */
|
||||
void (* ListenCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
|
||||
/*!< I2C Listen Complete callback */
|
||||
void (* MemTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
|
||||
/*!< I2C Memory Tx Transfer completed callback */
|
||||
void (* MemRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
|
||||
/*!< I2C Memory Rx Transfer completed callback */
|
||||
void (* ErrorCallback)(struct __I2C_HandleTypeDef *hi2c);
|
||||
/*!< I2C Error callback */
|
||||
void (* AbortCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
|
||||
/*!< I2C Abort callback */
|
||||
|
||||
void (* AddrCallback)(struct __I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode);
|
||||
/*!< I2C Slave Address Match callback */
|
||||
|
||||
void (* MspInitCallback)(struct __I2C_HandleTypeDef *hi2c);
|
||||
/*!< I2C Msp Init callback */
|
||||
void (* MspDeInitCallback)(struct __I2C_HandleTypeDef *hi2c);
|
||||
/*!< I2C Msp DeInit callback */
|
||||
|
||||
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
|
||||
} I2C_HandleTypeDef;
|
||||
|
||||
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
|
||||
/**
|
||||
* @brief HAL I2C Callback ID enumeration definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_I2C_MASTER_TX_COMPLETE_CB_ID = 0x00U, /*!< I2C Master Tx Transfer completed callback ID */
|
||||
HAL_I2C_MASTER_RX_COMPLETE_CB_ID = 0x01U, /*!< I2C Master Rx Transfer completed callback ID */
|
||||
HAL_I2C_SLAVE_TX_COMPLETE_CB_ID = 0x02U, /*!< I2C Slave Tx Transfer completed callback ID */
|
||||
HAL_I2C_SLAVE_RX_COMPLETE_CB_ID = 0x03U, /*!< I2C Slave Rx Transfer completed callback ID */
|
||||
HAL_I2C_LISTEN_COMPLETE_CB_ID = 0x04U, /*!< I2C Listen Complete callback ID */
|
||||
HAL_I2C_MEM_TX_COMPLETE_CB_ID = 0x05U, /*!< I2C Memory Tx Transfer callback ID */
|
||||
HAL_I2C_MEM_RX_COMPLETE_CB_ID = 0x06U, /*!< I2C Memory Rx Transfer completed callback ID */
|
||||
HAL_I2C_ERROR_CB_ID = 0x07U, /*!< I2C Error callback ID */
|
||||
HAL_I2C_ABORT_CB_ID = 0x08U, /*!< I2C Abort callback ID */
|
||||
|
||||
HAL_I2C_MSPINIT_CB_ID = 0x09U, /*!< I2C Msp Init callback ID */
|
||||
HAL_I2C_MSPDEINIT_CB_ID = 0x0AU /*!< I2C Msp DeInit callback ID */
|
||||
|
||||
} HAL_I2C_CallbackIDTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL I2C Callback pointer definition
|
||||
*/
|
||||
typedef void (*pI2C_CallbackTypeDef)(I2C_HandleTypeDef *hi2c);
|
||||
/*!< pointer to an I2C callback function */
|
||||
typedef void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection,
|
||||
uint16_t AddrMatchCode);
|
||||
/*!< pointer to an I2C Address Match callback function */
|
||||
|
||||
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup I2C_Exported_Constants I2C Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_XFEROPTIONS I2C Sequential Transfer Options
|
||||
* @{
|
||||
*/
|
||||
#define I2C_FIRST_FRAME ((uint32_t)I2C_SOFTEND_MODE)
|
||||
#define I2C_FIRST_AND_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))
|
||||
#define I2C_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))
|
||||
#define I2C_FIRST_AND_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE)
|
||||
#define I2C_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE)
|
||||
#define I2C_LAST_FRAME_NO_STOP ((uint32_t)I2C_SOFTEND_MODE)
|
||||
|
||||
/* List of XferOptions in usage of :
|
||||
* 1- Restart condition in all use cases (direction change or not)
|
||||
*/
|
||||
#define I2C_OTHER_FRAME (0x000000AAU)
|
||||
#define I2C_OTHER_AND_LAST_FRAME (0x0000AA00U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_ADDRESSING_MODE I2C Addressing Mode
|
||||
* @{
|
||||
*/
|
||||
#define I2C_ADDRESSINGMODE_7BIT (0x00000001U)
|
||||
#define I2C_ADDRESSINGMODE_10BIT (0x00000002U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_DUAL_ADDRESSING_MODE I2C Dual Addressing Mode
|
||||
* @{
|
||||
*/
|
||||
#define I2C_DUALADDRESS_DISABLE (0x00000000U)
|
||||
#define I2C_DUALADDRESS_ENABLE I2C_OAR2_OA2EN
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_OWN_ADDRESS2_MASKS I2C Own Address2 Masks
|
||||
* @{
|
||||
*/
|
||||
#define I2C_OA2_NOMASK ((uint8_t)0x00U)
|
||||
#define I2C_OA2_MASK01 ((uint8_t)0x01U)
|
||||
#define I2C_OA2_MASK02 ((uint8_t)0x02U)
|
||||
#define I2C_OA2_MASK03 ((uint8_t)0x03U)
|
||||
#define I2C_OA2_MASK04 ((uint8_t)0x04U)
|
||||
#define I2C_OA2_MASK05 ((uint8_t)0x05U)
|
||||
#define I2C_OA2_MASK06 ((uint8_t)0x06U)
|
||||
#define I2C_OA2_MASK07 ((uint8_t)0x07U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_GENERAL_CALL_ADDRESSING_MODE I2C General Call Addressing Mode
|
||||
* @{
|
||||
*/
|
||||
#define I2C_GENERALCALL_DISABLE (0x00000000U)
|
||||
#define I2C_GENERALCALL_ENABLE I2C_CR1_GCEN
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_NOSTRETCH_MODE I2C No-Stretch Mode
|
||||
* @{
|
||||
*/
|
||||
#define I2C_NOSTRETCH_DISABLE (0x00000000U)
|
||||
#define I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_MEMORY_ADDRESS_SIZE I2C Memory Address Size
|
||||
* @{
|
||||
*/
|
||||
#define I2C_MEMADD_SIZE_8BIT (0x00000001U)
|
||||
#define I2C_MEMADD_SIZE_16BIT (0x00000002U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_XFERDIRECTION I2C Transfer Direction Master Point of View
|
||||
* @{
|
||||
*/
|
||||
#define I2C_DIRECTION_TRANSMIT (0x00000000U)
|
||||
#define I2C_DIRECTION_RECEIVE (0x00000001U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_RELOAD_END_MODE I2C Reload End Mode
|
||||
* @{
|
||||
*/
|
||||
#define I2C_RELOAD_MODE I2C_CR2_RELOAD
|
||||
#define I2C_AUTOEND_MODE I2C_CR2_AUTOEND
|
||||
#define I2C_SOFTEND_MODE (0x00000000U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_START_STOP_MODE I2C Start or Stop Mode
|
||||
* @{
|
||||
*/
|
||||
#define I2C_NO_STARTSTOP (0x00000000U)
|
||||
#define I2C_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP)
|
||||
#define I2C_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
|
||||
#define I2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_Interrupt_configuration_definition I2C Interrupt configuration definition
|
||||
* @brief I2C Interrupt definition
|
||||
* Elements values convention: 0xXXXXXXXX
|
||||
* - XXXXXXXX : Interrupt control mask
|
||||
* @{
|
||||
*/
|
||||
#define I2C_IT_ERRI I2C_CR1_ERRIE
|
||||
#define I2C_IT_TCI I2C_CR1_TCIE
|
||||
#define I2C_IT_STOPI I2C_CR1_STOPIE
|
||||
#define I2C_IT_NACKI I2C_CR1_NACKIE
|
||||
#define I2C_IT_ADDRI I2C_CR1_ADDRIE
|
||||
#define I2C_IT_RXI I2C_CR1_RXIE
|
||||
#define I2C_IT_TXI I2C_CR1_TXIE
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_Flag_definition I2C Flag definition
|
||||
* @{
|
||||
*/
|
||||
#define I2C_FLAG_TXE I2C_ISR_TXE
|
||||
#define I2C_FLAG_TXIS I2C_ISR_TXIS
|
||||
#define I2C_FLAG_RXNE I2C_ISR_RXNE
|
||||
#define I2C_FLAG_ADDR I2C_ISR_ADDR
|
||||
#define I2C_FLAG_AF I2C_ISR_NACKF
|
||||
#define I2C_FLAG_STOPF I2C_ISR_STOPF
|
||||
#define I2C_FLAG_TC I2C_ISR_TC
|
||||
#define I2C_FLAG_TCR I2C_ISR_TCR
|
||||
#define I2C_FLAG_BERR I2C_ISR_BERR
|
||||
#define I2C_FLAG_ARLO I2C_ISR_ARLO
|
||||
#define I2C_FLAG_OVR I2C_ISR_OVR
|
||||
#define I2C_FLAG_PECERR I2C_ISR_PECERR
|
||||
#define I2C_FLAG_TIMEOUT I2C_ISR_TIMEOUT
|
||||
#define I2C_FLAG_ALERT I2C_ISR_ALERT
|
||||
#define I2C_FLAG_BUSY I2C_ISR_BUSY
|
||||
#define I2C_FLAG_DIR I2C_ISR_DIR
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
|
||||
/** @defgroup I2C_Exported_Macros I2C Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset I2C handle state.
|
||||
* @param __HANDLE__ specifies the I2C Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
|
||||
#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) do{ \
|
||||
(__HANDLE__)->State = HAL_I2C_STATE_RESET; \
|
||||
(__HANDLE__)->MspInitCallback = NULL; \
|
||||
(__HANDLE__)->MspDeInitCallback = NULL; \
|
||||
} while(0)
|
||||
#else
|
||||
#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET)
|
||||
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
|
||||
|
||||
/** @brief Enable the specified I2C interrupt.
|
||||
* @param __HANDLE__ specifies the I2C Handle.
|
||||
* @param __INTERRUPT__ specifies the interrupt source to enable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref I2C_IT_ERRI Errors interrupt enable
|
||||
* @arg @ref I2C_IT_TCI Transfer complete interrupt enable
|
||||
* @arg @ref I2C_IT_STOPI STOP detection interrupt enable
|
||||
* @arg @ref I2C_IT_NACKI NACK received interrupt enable
|
||||
* @arg @ref I2C_IT_ADDRI Address match interrupt enable
|
||||
* @arg @ref I2C_IT_RXI RX interrupt enable
|
||||
* @arg @ref I2C_IT_TXI TX interrupt enable
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
|
||||
|
||||
/** @brief Disable the specified I2C interrupt.
|
||||
* @param __HANDLE__ specifies the I2C Handle.
|
||||
* @param __INTERRUPT__ specifies the interrupt source to disable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref I2C_IT_ERRI Errors interrupt enable
|
||||
* @arg @ref I2C_IT_TCI Transfer complete interrupt enable
|
||||
* @arg @ref I2C_IT_STOPI STOP detection interrupt enable
|
||||
* @arg @ref I2C_IT_NACKI NACK received interrupt enable
|
||||
* @arg @ref I2C_IT_ADDRI Address match interrupt enable
|
||||
* @arg @ref I2C_IT_RXI RX interrupt enable
|
||||
* @arg @ref I2C_IT_TXI TX interrupt enable
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
|
||||
|
||||
/** @brief Check whether the specified I2C interrupt source is enabled or not.
|
||||
* @param __HANDLE__ specifies the I2C Handle.
|
||||
* @param __INTERRUPT__ specifies the I2C interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref I2C_IT_ERRI Errors interrupt enable
|
||||
* @arg @ref I2C_IT_TCI Transfer complete interrupt enable
|
||||
* @arg @ref I2C_IT_STOPI STOP detection interrupt enable
|
||||
* @arg @ref I2C_IT_NACKI NACK received interrupt enable
|
||||
* @arg @ref I2C_IT_ADDRI Address match interrupt enable
|
||||
* @arg @ref I2C_IT_RXI RX interrupt enable
|
||||
* @arg @ref I2C_IT_TXI TX interrupt enable
|
||||
*
|
||||
* @retval The new state of __INTERRUPT__ (SET or RESET).
|
||||
*/
|
||||
#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & \
|
||||
(__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
|
||||
|
||||
/** @brief Check whether the specified I2C flag is set or not.
|
||||
* @param __HANDLE__ specifies the I2C Handle.
|
||||
* @param __FLAG__ specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref I2C_FLAG_TXE Transmit data register empty
|
||||
* @arg @ref I2C_FLAG_TXIS Transmit interrupt status
|
||||
* @arg @ref I2C_FLAG_RXNE Receive data register not empty
|
||||
* @arg @ref I2C_FLAG_ADDR Address matched (slave mode)
|
||||
* @arg @ref I2C_FLAG_AF Acknowledge failure received flag
|
||||
* @arg @ref I2C_FLAG_STOPF STOP detection flag
|
||||
* @arg @ref I2C_FLAG_TC Transfer complete (master mode)
|
||||
* @arg @ref I2C_FLAG_TCR Transfer complete reload
|
||||
* @arg @ref I2C_FLAG_BERR Bus error
|
||||
* @arg @ref I2C_FLAG_ARLO Arbitration lost
|
||||
* @arg @ref I2C_FLAG_OVR Overrun/Underrun
|
||||
* @arg @ref I2C_FLAG_PECERR PEC error in reception
|
||||
* @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag
|
||||
* @arg @ref I2C_FLAG_ALERT SMBus alert
|
||||
* @arg @ref I2C_FLAG_BUSY Bus busy
|
||||
* @arg @ref I2C_FLAG_DIR Transfer direction (slave mode)
|
||||
*
|
||||
* @retval The new state of __FLAG__ (SET or RESET).
|
||||
*/
|
||||
#define I2C_FLAG_MASK (0x0001FFFFU)
|
||||
#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & \
|
||||
(__FLAG__)) == (__FLAG__)) ? SET : RESET)
|
||||
|
||||
/** @brief Clear the I2C pending flags which are cleared by writing 1 in a specific bit.
|
||||
* @param __HANDLE__ specifies the I2C Handle.
|
||||
* @param __FLAG__ specifies the flag to clear.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg @ref I2C_FLAG_TXE Transmit data register empty
|
||||
* @arg @ref I2C_FLAG_ADDR Address matched (slave mode)
|
||||
* @arg @ref I2C_FLAG_AF Acknowledge failure received flag
|
||||
* @arg @ref I2C_FLAG_STOPF STOP detection flag
|
||||
* @arg @ref I2C_FLAG_BERR Bus error
|
||||
* @arg @ref I2C_FLAG_ARLO Arbitration lost
|
||||
* @arg @ref I2C_FLAG_OVR Overrun/Underrun
|
||||
* @arg @ref I2C_FLAG_PECERR PEC error in reception
|
||||
* @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag
|
||||
* @arg @ref I2C_FLAG_ALERT SMBus alert
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == I2C_FLAG_TXE) ? \
|
||||
((__HANDLE__)->Instance->ISR |= (__FLAG__)) : \
|
||||
((__HANDLE__)->Instance->ICR = (__FLAG__)))
|
||||
|
||||
/** @brief Enable the specified I2C peripheral.
|
||||
* @param __HANDLE__ specifies the I2C Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2C_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
|
||||
|
||||
/** @brief Disable the specified I2C peripheral.
|
||||
* @param __HANDLE__ specifies the I2C Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2C_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
|
||||
|
||||
/** @brief Generate a Non-Acknowledge I2C peripheral in Slave mode.
|
||||
* @param __HANDLE__ specifies the I2C Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2C_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Include I2C HAL Extended module */
|
||||
#include "stm32wbxx_hal_i2c_ex.h"
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup I2C_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
/* Initialization and de-initialization functions******************************/
|
||||
HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c);
|
||||
HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c);
|
||||
|
||||
/* Callbacks Register/UnRegister functions ***********************************/
|
||||
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
|
||||
HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID,
|
||||
pI2C_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID);
|
||||
|
||||
HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c);
|
||||
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup I2C_Exported_Functions_Group2 Input and Output operation functions
|
||||
* @{
|
||||
*/
|
||||
/* IO operation functions ****************************************************/
|
||||
/******* Blocking mode: Polling */
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
|
||||
uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
|
||||
uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
|
||||
uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
|
||||
uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
|
||||
uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
|
||||
uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials,
|
||||
uint32_t Timeout);
|
||||
|
||||
/******* Non-Blocking mode: Interrupt */
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
|
||||
uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
|
||||
uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
|
||||
uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
|
||||
uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
|
||||
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
|
||||
uint16_t Size, uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
|
||||
uint16_t Size, uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
|
||||
uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
|
||||
uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c);
|
||||
HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c);
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress);
|
||||
|
||||
/******* Non-Blocking mode: DMA */
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
|
||||
uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
|
||||
uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
|
||||
uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
|
||||
uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
|
||||
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
|
||||
uint16_t Size, uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
|
||||
uint16_t Size, uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
|
||||
uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
|
||||
uint32_t XferOptions);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
|
||||
* @{
|
||||
*/
|
||||
/******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
|
||||
void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode);
|
||||
void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral State, Mode and Error functions *********************************/
|
||||
HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c);
|
||||
HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c);
|
||||
uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup I2C_Private_Constants I2C Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup I2C_Private_Macro I2C Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_I2C_ADDRESSING_MODE(MODE) (((MODE) == I2C_ADDRESSINGMODE_7BIT) || \
|
||||
((MODE) == I2C_ADDRESSINGMODE_10BIT))
|
||||
|
||||
#define IS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \
|
||||
((ADDRESS) == I2C_DUALADDRESS_ENABLE))
|
||||
|
||||
#define IS_I2C_OWN_ADDRESS2_MASK(MASK) (((MASK) == I2C_OA2_NOMASK) || \
|
||||
((MASK) == I2C_OA2_MASK01) || \
|
||||
((MASK) == I2C_OA2_MASK02) || \
|
||||
((MASK) == I2C_OA2_MASK03) || \
|
||||
((MASK) == I2C_OA2_MASK04) || \
|
||||
((MASK) == I2C_OA2_MASK05) || \
|
||||
((MASK) == I2C_OA2_MASK06) || \
|
||||
((MASK) == I2C_OA2_MASK07))
|
||||
|
||||
#define IS_I2C_GENERAL_CALL(CALL) (((CALL) == I2C_GENERALCALL_DISABLE) || \
|
||||
((CALL) == I2C_GENERALCALL_ENABLE))
|
||||
|
||||
#define IS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \
|
||||
((STRETCH) == I2C_NOSTRETCH_ENABLE))
|
||||
|
||||
#define IS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \
|
||||
((SIZE) == I2C_MEMADD_SIZE_16BIT))
|
||||
|
||||
#define IS_TRANSFER_MODE(MODE) (((MODE) == I2C_RELOAD_MODE) || \
|
||||
((MODE) == I2C_AUTOEND_MODE) || \
|
||||
((MODE) == I2C_SOFTEND_MODE))
|
||||
|
||||
#define IS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == I2C_GENERATE_STOP) || \
|
||||
((REQUEST) == I2C_GENERATE_START_READ) || \
|
||||
((REQUEST) == I2C_GENERATE_START_WRITE) || \
|
||||
((REQUEST) == I2C_NO_STARTSTOP))
|
||||
|
||||
#define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_FIRST_FRAME) || \
|
||||
((REQUEST) == I2C_FIRST_AND_NEXT_FRAME) || \
|
||||
((REQUEST) == I2C_NEXT_FRAME) || \
|
||||
((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \
|
||||
((REQUEST) == I2C_LAST_FRAME) || \
|
||||
((REQUEST) == I2C_LAST_FRAME_NO_STOP) || \
|
||||
IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST))
|
||||
|
||||
#define IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_OTHER_FRAME) || \
|
||||
((REQUEST) == I2C_OTHER_AND_LAST_FRAME))
|
||||
|
||||
#define I2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= \
|
||||
(uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | \
|
||||
I2C_CR2_NBYTES | I2C_CR2_RELOAD | \
|
||||
I2C_CR2_RD_WRN)))
|
||||
|
||||
#define I2C_GET_ADDR_MATCH(__HANDLE__) ((uint16_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) \
|
||||
>> 16U))
|
||||
#define I2C_GET_DIR(__HANDLE__) ((uint8_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) \
|
||||
>> 16U))
|
||||
#define I2C_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)
|
||||
#define I2C_GET_OWN_ADDRESS1(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR1 & I2C_OAR1_OA1))
|
||||
#define I2C_GET_OWN_ADDRESS2(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR2 & I2C_OAR2_OA2))
|
||||
|
||||
#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU)
|
||||
#define IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU)
|
||||
|
||||
#define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & \
|
||||
(uint16_t)(0xFF00U))) >> 8U)))
|
||||
#define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU))))
|
||||
|
||||
#define I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? \
|
||||
(uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \
|
||||
(I2C_CR2_START) | (I2C_CR2_AUTOEND)) & \
|
||||
(~I2C_CR2_RD_WRN)) : \
|
||||
(uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \
|
||||
(I2C_CR2_ADD10) | (I2C_CR2_START)) & \
|
||||
(~I2C_CR2_RD_WRN)))
|
||||
|
||||
#define I2C_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & I2C_FLAG_MASK)) == \
|
||||
((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET)
|
||||
#define I2C_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private Functions ---------------------------------------------------------*/
|
||||
/** @defgroup I2C_Private_Functions I2C Private Functions
|
||||
* @{
|
||||
*/
|
||||
/* Private functions are defined in stm32wbxx_hal_i2c.c file */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* STM32WBxx_HAL_I2C_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -1,173 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32wbxx_hal_i2c_ex.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of I2C HAL Extended module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32WBxx_HAL_I2C_EX_H
|
||||
#define STM32WBxx_HAL_I2C_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32wbxx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32WBxx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup I2CEx
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup I2CEx_Exported_Constants I2C Extended Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup I2CEx_Analog_Filter I2C Extended Analog Filter
|
||||
* @{
|
||||
*/
|
||||
#define I2C_ANALOGFILTER_ENABLE 0x00000000U
|
||||
#define I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2CEx_FastModePlus I2C Extended Fast Mode Plus
|
||||
* @{
|
||||
*/
|
||||
#define I2C_FMP_NOT_SUPPORTED 0xAAAA0000U /*!< Fast Mode Plus not supported */
|
||||
#define I2C_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP /*!< Enable Fast Mode Plus on PB6 */
|
||||
#define I2C_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP /*!< Enable Fast Mode Plus on PB7 */
|
||||
#define I2C_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP /*!< Enable Fast Mode Plus on PB8 */
|
||||
#define I2C_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP /*!< Enable Fast Mode Plus on PB9 */
|
||||
#define I2C_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C1_FMP /*!< Enable Fast Mode Plus on I2C1 pins */
|
||||
#if defined(SYSCFG_CFGR1_I2C3_FMP)
|
||||
#define I2C_FASTMODEPLUS_I2C3 SYSCFG_CFGR1_I2C3_FMP /*!< Enable Fast Mode Plus on I2C3 pins */
|
||||
#else
|
||||
#define I2C_FASTMODEPLUS_I2C3 (uint32_t)(0x00000400U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C3 not supported */
|
||||
#endif /* SYSCFG_CFGR1_I2C3_FMP */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup I2CEx_Exported_Macros I2C Extended Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup I2CEx_Exported_Functions I2C Extended Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup I2CEx_Exported_Functions_Group1 Filter Mode Functions
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral Control functions ************************************************/
|
||||
HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter);
|
||||
HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup I2CEx_Exported_Functions_Group2 WakeUp Mode Functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c);
|
||||
HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup I2CEx_Exported_Functions_Group3 Fast Mode Plus Functions
|
||||
* @{
|
||||
*/
|
||||
void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus);
|
||||
void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup I2CEx_Private_Constants I2C Extended Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup I2CEx_Private_Macro I2C Extended Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_I2C_ANALOG_FILTER(FILTER) (((FILTER) == I2C_ANALOGFILTER_ENABLE) || \
|
||||
((FILTER) == I2C_ANALOGFILTER_DISABLE))
|
||||
|
||||
#define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU)
|
||||
|
||||
#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & (I2C_FASTMODEPLUS_PB6)) == I2C_FASTMODEPLUS_PB6) || \
|
||||
(((__CONFIG__) & (I2C_FASTMODEPLUS_PB7)) == I2C_FASTMODEPLUS_PB7) || \
|
||||
(((__CONFIG__) & (I2C_FASTMODEPLUS_PB8)) == I2C_FASTMODEPLUS_PB8) || \
|
||||
(((__CONFIG__) & (I2C_FASTMODEPLUS_PB9)) == I2C_FASTMODEPLUS_PB9) || \
|
||||
(((__CONFIG__) & (I2C_FASTMODEPLUS_I2C1)) == I2C_FASTMODEPLUS_I2C1) || \
|
||||
(((__CONFIG__) & (I2C_FASTMODEPLUS_I2C3)) == I2C_FASTMODEPLUS_I2C3))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private Functions ---------------------------------------------------------*/
|
||||
/** @defgroup I2CEx_Private_Functions I2C Extended Private Functions
|
||||
* @{
|
||||
*/
|
||||
/* Private functions are defined in stm32wbxx_hal_i2c_ex.c file */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32WBxx_HAL_I2C_EX_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -1,265 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32wbxx_hal_ipcc.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of Mailbox HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32WBxx_HAL_IPCC_H
|
||||
#define STM32WBxx_HAL_IPCC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32wbxx_hal_def.h"
|
||||
|
||||
#if defined(IPCC)
|
||||
|
||||
/** @addtogroup STM32WBxx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup IPCC IPCC
|
||||
* @brief IPCC HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup IPCC_Exported_Constants IPCC Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup IPCC_Channel IPCC Channel
|
||||
* @{
|
||||
*/
|
||||
#define IPCC_CHANNEL_1 0x00000000U
|
||||
#define IPCC_CHANNEL_2 0x00000001U
|
||||
#define IPCC_CHANNEL_3 0x00000002U
|
||||
#define IPCC_CHANNEL_4 0x00000003U
|
||||
#define IPCC_CHANNEL_5 0x00000004U
|
||||
#define IPCC_CHANNEL_6 0x00000005U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup IPCC_Exported_Types IPCC Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief HAL IPCC State structures definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_IPCC_STATE_RESET = 0x00U, /*!< IPCC not yet initialized or disabled */
|
||||
HAL_IPCC_STATE_READY = 0x01U, /*!< IPCC initialized and ready for use */
|
||||
HAL_IPCC_STATE_BUSY = 0x02U /*!< IPCC internal processing is ongoing */
|
||||
} HAL_IPCC_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief IPCC channel direction structure definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
IPCC_CHANNEL_DIR_TX = 0x00U, /*!< Channel direction Tx is used by an MCU to transmit */
|
||||
IPCC_CHANNEL_DIR_RX = 0x01U /*!< Channel direction Rx is used by an MCU to receive */
|
||||
} IPCC_CHANNELDirTypeDef;
|
||||
|
||||
/**
|
||||
* @brief IPCC channel status structure definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
IPCC_CHANNEL_STATUS_FREE = 0x00U, /*!< Means that a new msg can be posted on that channel */
|
||||
IPCC_CHANNEL_STATUS_OCCUPIED = 0x01U /*!< An MCU has posted a msg the other MCU hasn't retrieved */
|
||||
} IPCC_CHANNELStatusTypeDef;
|
||||
|
||||
/**
|
||||
* @brief IPCC handle structure definition
|
||||
*/
|
||||
typedef struct __IPCC_HandleTypeDef
|
||||
{
|
||||
IPCC_TypeDef *Instance; /*!< IPCC registers base address */
|
||||
void (* ChannelCallbackRx[IPCC_CHANNEL_NUMBER])(struct __IPCC_HandleTypeDef *hipcc, uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir); /*!< Rx Callback registration table */
|
||||
void (* ChannelCallbackTx[IPCC_CHANNEL_NUMBER])(struct __IPCC_HandleTypeDef *hipcc, uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir); /*!< Tx Callback registration table */
|
||||
uint32_t callbackRequest; /*!< Store information about callback notification by channel */
|
||||
__IO HAL_IPCC_StateTypeDef State; /*!< IPCC State: initialized or not */
|
||||
} IPCC_HandleTypeDef;
|
||||
|
||||
/**
|
||||
* @brief IPCC callback typedef
|
||||
*/
|
||||
typedef void ChannelCb(IPCC_HandleTypeDef *hipcc, uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/** @defgroup IPCC_Exported_Macros IPCC Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enable the specified interrupt.
|
||||
* @param __HANDLE__ specifies the IPCC Handle
|
||||
* @param __CHDIRECTION__ specifies the channels Direction
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref IPCC_CHANNEL_DIR_TX Transmit channel free interrupt enable
|
||||
* @arg @ref IPCC_CHANNEL_DIR_RX Receive channel occupied interrupt enable
|
||||
*/
|
||||
#define __HAL_IPCC_ENABLE_IT(__HANDLE__, __CHDIRECTION__) \
|
||||
(((__CHDIRECTION__) == IPCC_CHANNEL_DIR_RX) ? \
|
||||
((__HANDLE__)->Instance->C1CR |= IPCC_C1CR_RXOIE) : \
|
||||
((__HANDLE__)->Instance->C1CR |= IPCC_C1CR_TXFIE))
|
||||
|
||||
/**
|
||||
* @brief Disable the specified interrupt.
|
||||
* @param __HANDLE__ specifies the IPCC Handle
|
||||
* @param __CHDIRECTION__ specifies the channels Direction
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref IPCC_CHANNEL_DIR_TX Transmit channel free interrupt enable
|
||||
* @arg @ref IPCC_CHANNEL_DIR_RX Receive channel occupied interrupt enable
|
||||
*/
|
||||
#define __HAL_IPCC_DISABLE_IT(__HANDLE__, __CHDIRECTION__) \
|
||||
(((__CHDIRECTION__) == IPCC_CHANNEL_DIR_RX) ? \
|
||||
((__HANDLE__)->Instance->C1CR &= ~IPCC_C1CR_RXOIE) : \
|
||||
((__HANDLE__)->Instance->C1CR &= ~IPCC_C1CR_TXFIE))
|
||||
|
||||
/**
|
||||
* @brief Mask the specified interrupt.
|
||||
* @param __HANDLE__ specifies the IPCC Handle
|
||||
* @param __CHDIRECTION__ specifies the channels Direction
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref IPCC_CHANNEL_DIR_TX Transmit channel free interrupt enable
|
||||
* @arg @ref IPCC_CHANNEL_DIR_RX Receive channel occupied interrupt enable
|
||||
* @param __CHINDEX__ specifies the channels number:
|
||||
* This parameter can be one of the following values:
|
||||
* @arg IPCC_CHANNEL_1: IPCC Channel 1
|
||||
* @arg IPCC_CHANNEL_2: IPCC Channel 2
|
||||
* @arg IPCC_CHANNEL_3: IPCC Channel 3
|
||||
* @arg IPCC_CHANNEL_4: IPCC Channel 4
|
||||
* @arg IPCC_CHANNEL_5: IPCC Channel 5
|
||||
* @arg IPCC_CHANNEL_6: IPCC Channel 6
|
||||
*/
|
||||
#define __HAL_IPCC_MASK_CHANNEL_IT(__HANDLE__, __CHDIRECTION__, __CHINDEX__) \
|
||||
(((__CHDIRECTION__) == IPCC_CHANNEL_DIR_RX) ? \
|
||||
((__HANDLE__)->Instance->C1MR |= (IPCC_C1MR_CH1OM_Msk << (__CHINDEX__))) : \
|
||||
((__HANDLE__)->Instance->C1MR |= (IPCC_C1MR_CH1FM_Msk << (__CHINDEX__))))
|
||||
|
||||
/**
|
||||
* @brief Unmask the specified interrupt.
|
||||
* @param __HANDLE__ specifies the IPCC Handle
|
||||
* @param __CHDIRECTION__ specifies the channels Direction
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref IPCC_CHANNEL_DIR_TX Transmit channel free interrupt enable
|
||||
* @arg @ref IPCC_CHANNEL_DIR_RX Receive channel occupied interrupt enable
|
||||
* @param __CHINDEX__ specifies the channels number:
|
||||
* This parameter can be one of the following values:
|
||||
* @arg IPCC_CHANNEL_1: IPCC Channel 1
|
||||
* @arg IPCC_CHANNEL_2: IPCC Channel 2
|
||||
* @arg IPCC_CHANNEL_3: IPCC Channel 3
|
||||
* @arg IPCC_CHANNEL_4: IPCC Channel 4
|
||||
* @arg IPCC_CHANNEL_5: IPCC Channel 5
|
||||
* @arg IPCC_CHANNEL_6: IPCC Channel 6
|
||||
*/
|
||||
#define __HAL_IPCC_UNMASK_CHANNEL_IT(__HANDLE__, __CHDIRECTION__, __CHINDEX__) \
|
||||
(((__CHDIRECTION__) == IPCC_CHANNEL_DIR_RX) ? \
|
||||
((__HANDLE__)->Instance->C1MR &= ~(IPCC_C1MR_CH1OM_Msk << (__CHINDEX__))) : \
|
||||
((__HANDLE__)->Instance->C1MR &= ~(IPCC_C1MR_CH1FM_Msk << (__CHINDEX__))))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup IPCC_Exported_Functions IPCC Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Initialization and de-initialization functions *******************************/
|
||||
/** @defgroup IPCC_Exported_Functions_Group1 Initialization and deinitialization functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_IPCC_Init(IPCC_HandleTypeDef *hipcc);
|
||||
HAL_StatusTypeDef HAL_IPCC_DeInit(IPCC_HandleTypeDef *hipcc);
|
||||
void HAL_IPCC_MspInit(IPCC_HandleTypeDef *hipcc);
|
||||
void HAL_IPCC_MspDeInit(IPCC_HandleTypeDef *hipcc);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IPCC_Exported_Functions_Group2 Communication functions
|
||||
* @{
|
||||
*/
|
||||
/* IO operation functions *****************************************************/
|
||||
HAL_StatusTypeDef HAL_IPCC_ActivateNotification(IPCC_HandleTypeDef *hipcc, uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir, ChannelCb cb);
|
||||
HAL_StatusTypeDef HAL_IPCC_DeActivateNotification(IPCC_HandleTypeDef *hipcc, uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir);
|
||||
IPCC_CHANNELStatusTypeDef HAL_IPCC_GetChannelStatus(IPCC_HandleTypeDef const *const hipcc, uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir);
|
||||
HAL_StatusTypeDef HAL_IPCC_NotifyCPU(IPCC_HandleTypeDef const *const hipcc, uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IPCC_Exported_Functions_Group3 Peripheral State and Error functions
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral State and Error functions ****************************************/
|
||||
HAL_IPCC_StateTypeDef HAL_IPCC_GetState(IPCC_HandleTypeDef const *const hipcc);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IPCC_IRQ_Handler_and_Callbacks Peripheral IRQ Handler and Callbacks
|
||||
* @{
|
||||
*/
|
||||
/* IRQHandler and Callbacks used in non blocking modes ************************/
|
||||
void HAL_IPCC_TX_IRQHandler(IPCC_HandleTypeDef *const hipcc);
|
||||
void HAL_IPCC_RX_IRQHandler(IPCC_HandleTypeDef *const hipcc);
|
||||
void HAL_IPCC_TxCallback(IPCC_HandleTypeDef *hipcc, uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir);
|
||||
void HAL_IPCC_RxCallback(IPCC_HandleTypeDef *hipcc, uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* IPCC */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32WBxx_HAL_IPCC_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -1,955 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32wbxx_hal_irda.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of IRDA HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32WBxx_HAL_IRDA_H
|
||||
#define STM32WBxx_HAL_IRDA_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32wbxx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32WBxx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup IRDA
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup IRDA_Exported_Types IRDA Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief IRDA Init Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t BaudRate; /*!< This member configures the IRDA communication baud rate.
|
||||
The baud rate register is computed using the following formula:
|
||||
Baud Rate Register = ((usart_ker_ckpres) / ((hirda->Init.BaudRate)))
|
||||
where usart_ker_ckpres is the IRDA input clock divided by a prescaler */
|
||||
|
||||
uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
|
||||
This parameter can be a value of @ref IRDA_Word_Length */
|
||||
|
||||
uint32_t Parity; /*!< Specifies the parity mode.
|
||||
This parameter can be a value of @ref IRDA_Parity
|
||||
@note When parity is enabled, the computed parity is inserted
|
||||
at the MSB position of the transmitted data (9th bit when
|
||||
the word length is set to 9 data bits; 8th bit when the
|
||||
word length is set to 8 data bits). */
|
||||
|
||||
uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
|
||||
This parameter can be a value of @ref IRDA_Transfer_Mode */
|
||||
|
||||
uint8_t Prescaler; /*!< Specifies the Prescaler value for dividing the UART/USART source clock
|
||||
to achieve low-power frequency.
|
||||
@note Prescaler value 0 is forbidden */
|
||||
|
||||
uint16_t PowerMode; /*!< Specifies the IRDA power mode.
|
||||
This parameter can be a value of @ref IRDA_Low_Power */
|
||||
|
||||
uint32_t ClockPrescaler; /*!< Specifies the prescaler value used to divide the IRDA clock source.
|
||||
This parameter can be a value of @ref IRDA_ClockPrescaler. */
|
||||
|
||||
} IRDA_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL IRDA State definition
|
||||
* @note HAL IRDA State value is a combination of 2 different substates:
|
||||
* gState and RxState (see @ref IRDA_State_Definition).
|
||||
* - gState contains IRDA state information related to global Handle management
|
||||
* and also information related to Tx operations.
|
||||
* gState value coding follow below described bitmap :
|
||||
* b7-b6 Error information
|
||||
* 00 : No Error
|
||||
* 01 : (Not Used)
|
||||
* 10 : Timeout
|
||||
* 11 : Error
|
||||
* b5 Peripheral initialization status
|
||||
* 0 : Reset (Peripheral not initialized)
|
||||
* 1 : Init done (Peripheral initialized. HAL IRDA Init function already called)
|
||||
* b4-b3 (not used)
|
||||
* xx : Should be set to 00
|
||||
* b2 Intrinsic process state
|
||||
* 0 : Ready
|
||||
* 1 : Busy (Peripheral busy with some configuration or internal operations)
|
||||
* b1 (not used)
|
||||
* x : Should be set to 0
|
||||
* b0 Tx state
|
||||
* 0 : Ready (no Tx operation ongoing)
|
||||
* 1 : Busy (Tx operation ongoing)
|
||||
* - RxState contains information related to Rx operations.
|
||||
* RxState value coding follow below described bitmap :
|
||||
* b7-b6 (not used)
|
||||
* xx : Should be set to 00
|
||||
* b5 Peripheral initialization status
|
||||
* 0 : Reset (Peripheral not initialized)
|
||||
* 1 : Init done (Peripheral initialized)
|
||||
* b4-b2 (not used)
|
||||
* xxx : Should be set to 000
|
||||
* b1 Rx state
|
||||
* 0 : Ready (no Rx operation ongoing)
|
||||
* 1 : Busy (Rx operation ongoing)
|
||||
* b0 (not used)
|
||||
* x : Should be set to 0.
|
||||
*/
|
||||
typedef uint32_t HAL_IRDA_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief IRDA clock sources definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
IRDA_CLOCKSOURCE_PCLK2 = 0x01U, /*!< PCLK2 clock source */
|
||||
IRDA_CLOCKSOURCE_HSI = 0x02U, /*!< HSI clock source */
|
||||
IRDA_CLOCKSOURCE_SYSCLK = 0x04U, /*!< SYSCLK clock source */
|
||||
IRDA_CLOCKSOURCE_LSE = 0x10U, /*!< LSE clock source */
|
||||
IRDA_CLOCKSOURCE_UNDEFINED = 0x20U /*!< Undefined clock source */
|
||||
} IRDA_ClockSourceTypeDef;
|
||||
|
||||
/**
|
||||
* @brief IRDA handle Structure definition
|
||||
*/
|
||||
#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
|
||||
typedef struct __IRDA_HandleTypeDef
|
||||
#else
|
||||
typedef struct
|
||||
#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
|
||||
{
|
||||
USART_TypeDef *Instance; /*!< USART registers base address */
|
||||
|
||||
IRDA_InitTypeDef Init; /*!< IRDA communication parameters */
|
||||
|
||||
uint8_t *pTxBuffPtr; /*!< Pointer to IRDA Tx transfer Buffer */
|
||||
|
||||
uint16_t TxXferSize; /*!< IRDA Tx Transfer size */
|
||||
|
||||
__IO uint16_t TxXferCount; /*!< IRDA Tx Transfer Counter */
|
||||
|
||||
uint8_t *pRxBuffPtr; /*!< Pointer to IRDA Rx transfer Buffer */
|
||||
|
||||
uint16_t RxXferSize; /*!< IRDA Rx Transfer size */
|
||||
|
||||
__IO uint16_t RxXferCount; /*!< IRDA Rx Transfer Counter */
|
||||
|
||||
uint16_t Mask; /*!< USART RX RDR register mask */
|
||||
|
||||
DMA_HandleTypeDef *hdmatx; /*!< IRDA Tx DMA Handle parameters */
|
||||
|
||||
DMA_HandleTypeDef *hdmarx; /*!< IRDA Rx DMA Handle parameters */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< Locking object */
|
||||
|
||||
__IO HAL_IRDA_StateTypeDef gState; /*!< IRDA state information related to global Handle management
|
||||
and also related to Tx operations.
|
||||
This parameter can be a value of @ref HAL_IRDA_StateTypeDef */
|
||||
|
||||
__IO HAL_IRDA_StateTypeDef RxState; /*!< IRDA state information related to Rx operations.
|
||||
This parameter can be a value of @ref HAL_IRDA_StateTypeDef */
|
||||
|
||||
uint32_t ErrorCode; /*!< IRDA Error code */
|
||||
|
||||
#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
|
||||
void (* TxHalfCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Tx Half Complete Callback */
|
||||
|
||||
void (* TxCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Tx Complete Callback */
|
||||
|
||||
void (* RxHalfCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Rx Half Complete Callback */
|
||||
|
||||
void (* RxCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Rx Complete Callback */
|
||||
|
||||
void (* ErrorCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Error Callback */
|
||||
|
||||
void (* AbortCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Abort Complete Callback */
|
||||
|
||||
void (* AbortTransmitCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Abort Transmit Complete Callback */
|
||||
|
||||
void (* AbortReceiveCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Abort Receive Complete Callback */
|
||||
|
||||
|
||||
void (* MspInitCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Msp Init callback */
|
||||
|
||||
void (* MspDeInitCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Msp DeInit callback */
|
||||
#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
|
||||
|
||||
} IRDA_HandleTypeDef;
|
||||
|
||||
#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
|
||||
/**
|
||||
* @brief HAL IRDA Callback ID enumeration definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_IRDA_TX_HALFCOMPLETE_CB_ID = 0x00U, /*!< IRDA Tx Half Complete Callback ID */
|
||||
HAL_IRDA_TX_COMPLETE_CB_ID = 0x01U, /*!< IRDA Tx Complete Callback ID */
|
||||
HAL_IRDA_RX_HALFCOMPLETE_CB_ID = 0x02U, /*!< IRDA Rx Half Complete Callback ID */
|
||||
HAL_IRDA_RX_COMPLETE_CB_ID = 0x03U, /*!< IRDA Rx Complete Callback ID */
|
||||
HAL_IRDA_ERROR_CB_ID = 0x04U, /*!< IRDA Error Callback ID */
|
||||
HAL_IRDA_ABORT_COMPLETE_CB_ID = 0x05U, /*!< IRDA Abort Complete Callback ID */
|
||||
HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x06U, /*!< IRDA Abort Transmit Complete Callback ID */
|
||||
HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID = 0x07U, /*!< IRDA Abort Receive Complete Callback ID */
|
||||
|
||||
HAL_IRDA_MSPINIT_CB_ID = 0x08U, /*!< IRDA MspInit callback ID */
|
||||
HAL_IRDA_MSPDEINIT_CB_ID = 0x09U /*!< IRDA MspDeInit callback ID */
|
||||
|
||||
} HAL_IRDA_CallbackIDTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL IRDA Callback pointer definition
|
||||
*/
|
||||
typedef void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda); /*!< pointer to an IRDA callback function */
|
||||
|
||||
#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup IRDA_Exported_Constants IRDA Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup IRDA_State_Definition IRDA State Code Definition
|
||||
* @{
|
||||
*/
|
||||
#define HAL_IRDA_STATE_RESET 0x00000000U /*!< Peripheral is not initialized
|
||||
Value is allowed for gState and RxState */
|
||||
#define HAL_IRDA_STATE_READY 0x00000020U /*!< Peripheral Initialized and ready for use
|
||||
Value is allowed for gState and RxState */
|
||||
#define HAL_IRDA_STATE_BUSY 0x00000024U /*!< An internal process is ongoing
|
||||
Value is allowed for gState only */
|
||||
#define HAL_IRDA_STATE_BUSY_TX 0x00000021U /*!< Data Transmission process is ongoing
|
||||
Value is allowed for gState only */
|
||||
#define HAL_IRDA_STATE_BUSY_RX 0x00000022U /*!< Data Reception process is ongoing
|
||||
Value is allowed for RxState only */
|
||||
#define HAL_IRDA_STATE_BUSY_TX_RX 0x00000023U /*!< Data Transmission and Reception process is ongoing
|
||||
Not to be used for neither gState nor RxState.
|
||||
Value is result of combination (Or) between gState and RxState values */
|
||||
#define HAL_IRDA_STATE_TIMEOUT 0x000000A0U /*!< Timeout state
|
||||
Value is allowed for gState only */
|
||||
#define HAL_IRDA_STATE_ERROR 0x000000E0U /*!< Error
|
||||
Value is allowed for gState only */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IRDA_Error_Definition IRDA Error Code Definition
|
||||
* @{
|
||||
*/
|
||||
#define HAL_IRDA_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
|
||||
#define HAL_IRDA_ERROR_PE ((uint32_t)0x00000001U) /*!< Parity error */
|
||||
#define HAL_IRDA_ERROR_NE ((uint32_t)0x00000002U) /*!< Noise error */
|
||||
#define HAL_IRDA_ERROR_FE ((uint32_t)0x00000004U) /*!< frame error */
|
||||
#define HAL_IRDA_ERROR_ORE ((uint32_t)0x00000008U) /*!< Overrun error */
|
||||
#define HAL_IRDA_ERROR_DMA ((uint32_t)0x00000010U) /*!< DMA transfer error */
|
||||
#define HAL_IRDA_ERROR_BUSY ((uint32_t)0x00000020U) /*!< Busy Error */
|
||||
#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
|
||||
#define HAL_IRDA_ERROR_INVALID_CALLBACK ((uint32_t)0x00000040U) /*!< Invalid Callback error */
|
||||
#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IRDA_Word_Length IRDA Word Length
|
||||
* @{
|
||||
*/
|
||||
#define IRDA_WORDLENGTH_7B USART_CR1_M1 /*!< 7-bit long frame */
|
||||
#define IRDA_WORDLENGTH_8B 0x00000000U /*!< 8-bit long frame */
|
||||
#define IRDA_WORDLENGTH_9B USART_CR1_M0 /*!< 9-bit long frame */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IRDA_Parity IRDA Parity
|
||||
* @{
|
||||
*/
|
||||
#define IRDA_PARITY_NONE 0x00000000U /*!< No parity */
|
||||
#define IRDA_PARITY_EVEN USART_CR1_PCE /*!< Even parity */
|
||||
#define IRDA_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Odd parity */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IRDA_Transfer_Mode IRDA Transfer Mode
|
||||
* @{
|
||||
*/
|
||||
#define IRDA_MODE_RX USART_CR1_RE /*!< RX mode */
|
||||
#define IRDA_MODE_TX USART_CR1_TE /*!< TX mode */
|
||||
#define IRDA_MODE_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< RX and TX mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IRDA_Low_Power IRDA Low Power
|
||||
* @{
|
||||
*/
|
||||
#define IRDA_POWERMODE_NORMAL 0x00000000U /*!< IRDA normal power mode */
|
||||
#define IRDA_POWERMODE_LOWPOWER USART_CR3_IRLP /*!< IRDA low power mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IRDA_ClockPrescaler Clock Prescaler
|
||||
* @{
|
||||
*/
|
||||
#define IRDA_PRESCALER_DIV1 0x00000000U /*!< fclk_pres = fclk */
|
||||
#define IRDA_PRESCALER_DIV2 0x00000001U /*!< fclk_pres = fclk/2 */
|
||||
#define IRDA_PRESCALER_DIV4 0x00000002U /*!< fclk_pres = fclk/4 */
|
||||
#define IRDA_PRESCALER_DIV6 0x00000003U /*!< fclk_pres = fclk/6 */
|
||||
#define IRDA_PRESCALER_DIV8 0x00000004U /*!< fclk_pres = fclk/8 */
|
||||
#define IRDA_PRESCALER_DIV10 0x00000005U /*!< fclk_pres = fclk/10 */
|
||||
#define IRDA_PRESCALER_DIV12 0x00000006U /*!< fclk_pres = fclk/12 */
|
||||
#define IRDA_PRESCALER_DIV16 0x00000007U /*!< fclk_pres = fclk/16 */
|
||||
#define IRDA_PRESCALER_DIV32 0x00000008U /*!< fclk_pres = fclk/32 */
|
||||
#define IRDA_PRESCALER_DIV64 0x00000009U /*!< fclk_pres = fclk/64 */
|
||||
#define IRDA_PRESCALER_DIV128 0x0000000AU /*!< fclk_pres = fclk/128 */
|
||||
#define IRDA_PRESCALER_DIV256 0x0000000BU /*!< fclk_pres = fclk/256 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IRDA_State IRDA State
|
||||
* @{
|
||||
*/
|
||||
#define IRDA_STATE_DISABLE 0x00000000U /*!< IRDA disabled */
|
||||
#define IRDA_STATE_ENABLE USART_CR1_UE /*!< IRDA enabled */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IRDA_Mode IRDA Mode
|
||||
* @{
|
||||
*/
|
||||
#define IRDA_MODE_DISABLE 0x00000000U /*!< Associated UART disabled in IRDA mode */
|
||||
#define IRDA_MODE_ENABLE USART_CR3_IREN /*!< Associated UART enabled in IRDA mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IRDA_One_Bit IRDA One Bit Sampling
|
||||
* @{
|
||||
*/
|
||||
#define IRDA_ONE_BIT_SAMPLE_DISABLE 0x00000000U /*!< One-bit sampling disabled */
|
||||
#define IRDA_ONE_BIT_SAMPLE_ENABLE USART_CR3_ONEBIT /*!< One-bit sampling enabled */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IRDA_DMA_Tx IRDA DMA Tx
|
||||
* @{
|
||||
*/
|
||||
#define IRDA_DMA_TX_DISABLE 0x00000000U /*!< IRDA DMA TX disabled */
|
||||
#define IRDA_DMA_TX_ENABLE USART_CR3_DMAT /*!< IRDA DMA TX enabled */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IRDA_DMA_Rx IRDA DMA Rx
|
||||
* @{
|
||||
*/
|
||||
#define IRDA_DMA_RX_DISABLE 0x00000000U /*!< IRDA DMA RX disabled */
|
||||
#define IRDA_DMA_RX_ENABLE USART_CR3_DMAR /*!< IRDA DMA RX enabled */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IRDA_Request_Parameters IRDA Request Parameters
|
||||
* @{
|
||||
*/
|
||||
#define IRDA_AUTOBAUD_REQUEST USART_RQR_ABRRQ /*!< Auto-Baud Rate Request */
|
||||
#define IRDA_RXDATA_FLUSH_REQUEST USART_RQR_RXFRQ /*!< Receive Data flush Request */
|
||||
#define IRDA_TXDATA_FLUSH_REQUEST USART_RQR_TXFRQ /*!< Transmit data flush Request */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IRDA_Flags IRDA Flags
|
||||
* Elements values convention: 0xXXXX
|
||||
* - 0xXXXX : Flag mask in the ISR register
|
||||
* @{
|
||||
*/
|
||||
#define IRDA_FLAG_REACK USART_ISR_REACK /*!< IRDA receive enable acknowledge flag */
|
||||
#define IRDA_FLAG_TEACK USART_ISR_TEACK /*!< IRDA transmit enable acknowledge flag */
|
||||
#define IRDA_FLAG_BUSY USART_ISR_BUSY /*!< IRDA busy flag */
|
||||
#define IRDA_FLAG_ABRF USART_ISR_ABRF /*!< IRDA auto Baud rate flag */
|
||||
#define IRDA_FLAG_ABRE USART_ISR_ABRE /*!< IRDA auto Baud rate error */
|
||||
#define IRDA_FLAG_TXE USART_ISR_TXE_TXFNF /*!< IRDA transmit data register empty */
|
||||
#define IRDA_FLAG_TC USART_ISR_TC /*!< IRDA transmission complete */
|
||||
#define IRDA_FLAG_RXNE USART_ISR_RXNE_RXFNE /*!< IRDA read data register not empty */
|
||||
#define IRDA_FLAG_ORE USART_ISR_ORE /*!< IRDA overrun error */
|
||||
#define IRDA_FLAG_NE USART_ISR_NE /*!< IRDA noise error */
|
||||
#define IRDA_FLAG_FE USART_ISR_FE /*!< IRDA frame error */
|
||||
#define IRDA_FLAG_PE USART_ISR_PE /*!< IRDA parity error */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IRDA_Interrupt_definition IRDA Interrupts Definition
|
||||
* Elements values convention: 0000ZZZZ0XXYYYYYb
|
||||
* - YYYYY : Interrupt source position in the XX register (5bits)
|
||||
* - XX : Interrupt source register (2bits)
|
||||
* - 01: CR1 register
|
||||
* - 10: CR2 register
|
||||
* - 11: CR3 register
|
||||
* - ZZZZ : Flag position in the ISR register(4bits)
|
||||
* @{
|
||||
*/
|
||||
#define IRDA_IT_PE 0x0028U /*!< IRDA Parity error interruption */
|
||||
#define IRDA_IT_TXE 0x0727U /*!< IRDA Transmit data register empty interruption */
|
||||
#define IRDA_IT_TC 0x0626U /*!< IRDA Transmission complete interruption */
|
||||
#define IRDA_IT_RXNE 0x0525U /*!< IRDA Read data register not empty interruption */
|
||||
#define IRDA_IT_IDLE 0x0424U /*!< IRDA Idle interruption */
|
||||
|
||||
/* Elements values convention: 000000000XXYYYYYb
|
||||
- YYYYY : Interrupt source position in the XX register (5bits)
|
||||
- XX : Interrupt source register (2bits)
|
||||
- 01: CR1 register
|
||||
- 10: CR2 register
|
||||
- 11: CR3 register */
|
||||
#define IRDA_IT_ERR 0x0060U /*!< IRDA Error interruption */
|
||||
|
||||
/* Elements values convention: 0000ZZZZ00000000b
|
||||
- ZZZZ : Flag position in the ISR register(4bits) */
|
||||
#define IRDA_IT_ORE 0x0300U /*!< IRDA Overrun error interruption */
|
||||
#define IRDA_IT_NE 0x0200U /*!< IRDA Noise error interruption */
|
||||
#define IRDA_IT_FE 0x0100U /*!< IRDA Frame error interruption */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IRDA_IT_CLEAR_Flags IRDA Interruption Clear Flags
|
||||
* @{
|
||||
*/
|
||||
#define IRDA_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */
|
||||
#define IRDA_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */
|
||||
#define IRDA_CLEAR_NEF USART_ICR_NECF /*!< Noise Error detected Clear Flag */
|
||||
#define IRDA_CLEAR_OREF USART_ICR_ORECF /*!< OverRun Error Clear Flag */
|
||||
#define IRDA_CLEAR_IDLEF USART_ICR_IDLECF /*!< IDLE line detected Clear Flag */
|
||||
#define IRDA_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IRDA_Interruption_Mask IRDA interruptions flags mask
|
||||
* @{
|
||||
*/
|
||||
#define IRDA_IT_MASK 0x001FU /*!< IRDA Interruptions flags mask */
|
||||
#define IRDA_CR_MASK 0x00E0U /*!< IRDA control register mask */
|
||||
#define IRDA_CR_POS 5U /*!< IRDA control register position */
|
||||
#define IRDA_ISR_MASK 0x1F00U /*!< IRDA ISR register mask */
|
||||
#define IRDA_ISR_POS 8U /*!< IRDA ISR register position */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/** @defgroup IRDA_Exported_Macros IRDA Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset IRDA handle state.
|
||||
* @param __HANDLE__ IRDA handle.
|
||||
* @retval None
|
||||
*/
|
||||
#if USE_HAL_IRDA_REGISTER_CALLBACKS == 1
|
||||
#define __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__) do{ \
|
||||
(__HANDLE__)->gState = HAL_IRDA_STATE_RESET; \
|
||||
(__HANDLE__)->RxState = HAL_IRDA_STATE_RESET; \
|
||||
(__HANDLE__)->MspInitCallback = NULL; \
|
||||
(__HANDLE__)->MspDeInitCallback = NULL; \
|
||||
} while(0)
|
||||
#else
|
||||
#define __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__) do{ \
|
||||
(__HANDLE__)->gState = HAL_IRDA_STATE_RESET; \
|
||||
(__HANDLE__)->RxState = HAL_IRDA_STATE_RESET; \
|
||||
} while(0)
|
||||
#endif /*USE_HAL_IRDA_REGISTER_CALLBACKS */
|
||||
|
||||
/** @brief Flush the IRDA DR register.
|
||||
* @param __HANDLE__ specifies the IRDA Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IRDA_FLUSH_DRREGISTER(__HANDLE__) \
|
||||
do{ \
|
||||
SET_BIT((__HANDLE__)->Instance->RQR, IRDA_RXDATA_FLUSH_REQUEST); \
|
||||
SET_BIT((__HANDLE__)->Instance->RQR, IRDA_TXDATA_FLUSH_REQUEST); \
|
||||
} while(0)
|
||||
|
||||
/** @brief Clear the specified IRDA pending flag.
|
||||
* @param __HANDLE__ specifies the IRDA Handle.
|
||||
* @param __FLAG__ specifies the flag to check.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg @ref IRDA_CLEAR_PEF
|
||||
* @arg @ref IRDA_CLEAR_FEF
|
||||
* @arg @ref IRDA_CLEAR_NEF
|
||||
* @arg @ref IRDA_CLEAR_OREF
|
||||
* @arg @ref IRDA_CLEAR_TCF
|
||||
* @arg @ref IRDA_CLEAR_IDLEF
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IRDA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
|
||||
|
||||
/** @brief Clear the IRDA PE pending flag.
|
||||
* @param __HANDLE__ specifies the IRDA Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_PEF)
|
||||
|
||||
|
||||
/** @brief Clear the IRDA FE pending flag.
|
||||
* @param __HANDLE__ specifies the IRDA Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IRDA_CLEAR_FEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_FEF)
|
||||
|
||||
/** @brief Clear the IRDA NE pending flag.
|
||||
* @param __HANDLE__ specifies the IRDA Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IRDA_CLEAR_NEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_NEF)
|
||||
|
||||
/** @brief Clear the IRDA ORE pending flag.
|
||||
* @param __HANDLE__ specifies the IRDA Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IRDA_CLEAR_OREFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_OREF)
|
||||
|
||||
/** @brief Clear the IRDA IDLE pending flag.
|
||||
* @param __HANDLE__ specifies the IRDA Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IRDA_CLEAR_IDLEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_IDLEF)
|
||||
|
||||
/** @brief Check whether the specified IRDA flag is set or not.
|
||||
* @param __HANDLE__ specifies the IRDA Handle.
|
||||
* @param __FLAG__ specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref IRDA_FLAG_REACK Receive enable acknowledge flag
|
||||
* @arg @ref IRDA_FLAG_TEACK Transmit enable acknowledge flag
|
||||
* @arg @ref IRDA_FLAG_BUSY Busy flag
|
||||
* @arg @ref IRDA_FLAG_ABRF Auto Baud rate detection flag
|
||||
* @arg @ref IRDA_FLAG_ABRE Auto Baud rate detection error flag
|
||||
* @arg @ref IRDA_FLAG_TXE Transmit data register empty flag
|
||||
* @arg @ref IRDA_FLAG_TC Transmission Complete flag
|
||||
* @arg @ref IRDA_FLAG_RXNE Receive data register not empty flag
|
||||
* @arg @ref IRDA_FLAG_ORE OverRun Error flag
|
||||
* @arg @ref IRDA_FLAG_NE Noise Error flag
|
||||
* @arg @ref IRDA_FLAG_FE Framing Error flag
|
||||
* @arg @ref IRDA_FLAG_PE Parity Error flag
|
||||
* @retval The new state of __FLAG__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_IRDA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
|
||||
|
||||
|
||||
/** @brief Enable the specified IRDA interrupt.
|
||||
* @param __HANDLE__ specifies the IRDA Handle.
|
||||
* @param __INTERRUPT__ specifies the IRDA interrupt source to enable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref IRDA_IT_TXE Transmit Data Register empty interrupt
|
||||
* @arg @ref IRDA_IT_TC Transmission complete interrupt
|
||||
* @arg @ref IRDA_IT_RXNE Receive Data register not empty interrupt
|
||||
* @arg @ref IRDA_IT_IDLE Idle line detection interrupt
|
||||
* @arg @ref IRDA_IT_PE Parity Error interrupt
|
||||
* @arg @ref IRDA_IT_ERR Error interrupt(Frame error, noise error, overrun error)
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IRDA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 1)? ((__HANDLE__)->Instance->CR1 |= ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
|
||||
((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 2)? ((__HANDLE__)->Instance->CR2 |= ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
|
||||
((__HANDLE__)->Instance->CR3 |= ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK))))
|
||||
|
||||
/** @brief Disable the specified IRDA interrupt.
|
||||
* @param __HANDLE__ specifies the IRDA Handle.
|
||||
* @param __INTERRUPT__ specifies the IRDA interrupt source to disable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref IRDA_IT_TXE Transmit Data Register empty interrupt
|
||||
* @arg @ref IRDA_IT_TC Transmission complete interrupt
|
||||
* @arg @ref IRDA_IT_RXNE Receive Data register not empty interrupt
|
||||
* @arg @ref IRDA_IT_IDLE Idle line detection interrupt
|
||||
* @arg @ref IRDA_IT_PE Parity Error interrupt
|
||||
* @arg @ref IRDA_IT_ERR Error interrupt(Frame error, noise error, overrun error)
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IRDA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 1)? ((__HANDLE__)->Instance->CR1 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
|
||||
((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 2)? ((__HANDLE__)->Instance->CR2 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
|
||||
((__HANDLE__)->Instance->CR3 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK))))
|
||||
|
||||
|
||||
/** @brief Check whether the specified IRDA interrupt has occurred or not.
|
||||
* @param __HANDLE__ specifies the IRDA Handle.
|
||||
* @param __INTERRUPT__ specifies the IRDA interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref IRDA_IT_TXE Transmit Data Register empty interrupt
|
||||
* @arg @ref IRDA_IT_TC Transmission complete interrupt
|
||||
* @arg @ref IRDA_IT_RXNE Receive Data register not empty interrupt
|
||||
* @arg @ref IRDA_IT_IDLE Idle line detection interrupt
|
||||
* @arg @ref IRDA_IT_ORE OverRun Error interrupt
|
||||
* @arg @ref IRDA_IT_NE Noise Error interrupt
|
||||
* @arg @ref IRDA_IT_FE Framing Error interrupt
|
||||
* @arg @ref IRDA_IT_PE Parity Error interrupt
|
||||
* @retval The new state of __IT__ (SET or RESET).
|
||||
*/
|
||||
#define __HAL_IRDA_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR & (0x01U << (((__INTERRUPT__) & IRDA_ISR_MASK)>> IRDA_ISR_POS))) != 0U) ? SET : RESET)
|
||||
|
||||
/** @brief Check whether the specified IRDA interrupt source is enabled or not.
|
||||
* @param __HANDLE__ specifies the IRDA Handle.
|
||||
* @param __INTERRUPT__ specifies the IRDA interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref IRDA_IT_TXE Transmit Data Register empty interrupt
|
||||
* @arg @ref IRDA_IT_TC Transmission complete interrupt
|
||||
* @arg @ref IRDA_IT_RXNE Receive Data register not empty interrupt
|
||||
* @arg @ref IRDA_IT_IDLE Idle line detection interrupt
|
||||
* @arg @ref IRDA_IT_ERR Framing, overrun or noise error interrupt
|
||||
* @arg @ref IRDA_IT_PE Parity Error interrupt
|
||||
* @retval The new state of __IT__ (SET or RESET).
|
||||
*/
|
||||
#define __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 0x01U)? (__HANDLE__)->Instance->CR1 : \
|
||||
(((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 0x02U)? (__HANDLE__)->Instance->CR2 : \
|
||||
(__HANDLE__)->Instance->CR3)) & ((uint32_t)0x01U << (((uint16_t)(__INTERRUPT__)) & IRDA_IT_MASK))) != 0U) ? SET : RESET)
|
||||
|
||||
/** @brief Clear the specified IRDA ISR flag, in setting the proper ICR register flag.
|
||||
* @param __HANDLE__ specifies the IRDA Handle.
|
||||
* @param __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set
|
||||
* to clear the corresponding interrupt
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref IRDA_CLEAR_PEF Parity Error Clear Flag
|
||||
* @arg @ref IRDA_CLEAR_FEF Framing Error Clear Flag
|
||||
* @arg @ref IRDA_CLEAR_NEF Noise detected Clear Flag
|
||||
* @arg @ref IRDA_CLEAR_OREF OverRun Error Clear Flag
|
||||
* @arg @ref IRDA_CLEAR_TCF Transmission Complete Clear Flag
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IRDA_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
|
||||
|
||||
|
||||
/** @brief Set a specific IRDA request flag.
|
||||
* @param __HANDLE__ specifies the IRDA Handle.
|
||||
* @param __REQ__ specifies the request flag to set
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref IRDA_AUTOBAUD_REQUEST Auto-Baud Rate Request
|
||||
* @arg @ref IRDA_RXDATA_FLUSH_REQUEST Receive Data flush Request
|
||||
* @arg @ref IRDA_TXDATA_FLUSH_REQUEST Transmit data flush Request
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IRDA_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
|
||||
|
||||
/** @brief Enable the IRDA one bit sample method.
|
||||
* @param __HANDLE__ specifies the IRDA Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IRDA_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
|
||||
|
||||
/** @brief Disable the IRDA one bit sample method.
|
||||
* @param __HANDLE__ specifies the IRDA Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IRDA_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
|
||||
|
||||
/** @brief Enable UART/USART associated to IRDA Handle.
|
||||
* @param __HANDLE__ specifies the IRDA Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IRDA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
|
||||
|
||||
/** @brief Disable UART/USART associated to IRDA Handle.
|
||||
* @param __HANDLE__ specifies the IRDA Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IRDA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros --------------------------------------------------------*/
|
||||
/** @addtogroup IRDA_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Compute the mask to apply to retrieve the received data
|
||||
* according to the word length and to the parity bits activation.
|
||||
* @param __HANDLE__ specifies the IRDA Handle.
|
||||
* @retval None, the mask to apply to the associated UART RDR register is stored in (__HANDLE__)->Mask field.
|
||||
*/
|
||||
#define IRDA_MASK_COMPUTATION(__HANDLE__) \
|
||||
do { \
|
||||
if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_9B) \
|
||||
{ \
|
||||
if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \
|
||||
{ \
|
||||
(__HANDLE__)->Mask = 0x01FF ; \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__HANDLE__)->Mask = 0x00FF ; \
|
||||
} \
|
||||
} \
|
||||
else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_8B) \
|
||||
{ \
|
||||
if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \
|
||||
{ \
|
||||
(__HANDLE__)->Mask = 0x00FF ; \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__HANDLE__)->Mask = 0x007F ; \
|
||||
} \
|
||||
} \
|
||||
else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_7B) \
|
||||
{ \
|
||||
if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \
|
||||
{ \
|
||||
(__HANDLE__)->Mask = 0x007F ; \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__HANDLE__)->Mask = 0x003F ; \
|
||||
} \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__HANDLE__)->Mask = 0x0000U; \
|
||||
} \
|
||||
} while(0)
|
||||
|
||||
/** @brief Ensure that IRDA Baud rate is less or equal to maximum value.
|
||||
* @param __BAUDRATE__ specifies the IRDA Baudrate set by the user.
|
||||
* @retval True or False
|
||||
*/
|
||||
#define IS_IRDA_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 115201U)
|
||||
|
||||
/** @brief Ensure that IRDA prescaler value is strictly larger than 0.
|
||||
* @param __PRESCALER__ specifies the IRDA prescaler value set by the user.
|
||||
* @retval True or False
|
||||
*/
|
||||
#define IS_IRDA_PRESCALER(__PRESCALER__) ((__PRESCALER__) > 0U)
|
||||
|
||||
/**
|
||||
* @brief Ensure that IRDA frame length is valid.
|
||||
* @param __LENGTH__ IRDA frame length.
|
||||
* @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
|
||||
*/
|
||||
#define IS_IRDA_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == IRDA_WORDLENGTH_7B) || \
|
||||
((__LENGTH__) == IRDA_WORDLENGTH_8B) || \
|
||||
((__LENGTH__) == IRDA_WORDLENGTH_9B))
|
||||
|
||||
/**
|
||||
* @brief Ensure that IRDA frame parity is valid.
|
||||
* @param __PARITY__ IRDA frame parity.
|
||||
* @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)
|
||||
*/
|
||||
#define IS_IRDA_PARITY(__PARITY__) (((__PARITY__) == IRDA_PARITY_NONE) || \
|
||||
((__PARITY__) == IRDA_PARITY_EVEN) || \
|
||||
((__PARITY__) == IRDA_PARITY_ODD))
|
||||
|
||||
/**
|
||||
* @brief Ensure that IRDA communication mode is valid.
|
||||
* @param __MODE__ IRDA communication mode.
|
||||
* @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
|
||||
*/
|
||||
#define IS_IRDA_TX_RX_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(IRDA_MODE_TX_RX)))) == 0x00U) && ((__MODE__) != 0x00U))
|
||||
|
||||
/**
|
||||
* @brief Ensure that IRDA power mode is valid.
|
||||
* @param __MODE__ IRDA power mode.
|
||||
* @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
|
||||
*/
|
||||
#define IS_IRDA_POWERMODE(__MODE__) (((__MODE__) == IRDA_POWERMODE_LOWPOWER) || \
|
||||
((__MODE__) == IRDA_POWERMODE_NORMAL))
|
||||
|
||||
/**
|
||||
* @brief Ensure that IRDA clock Prescaler is valid.
|
||||
* @param __CLOCKPRESCALER__ IRDA clock Prescaler value.
|
||||
* @retval SET (__CLOCKPRESCALER__ is valid) or RESET (__CLOCKPRESCALER__ is invalid)
|
||||
*/
|
||||
#define IS_IRDA_CLOCKPRESCALER(__CLOCKPRESCALER__) (((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV1) || \
|
||||
((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV2) || \
|
||||
((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV4) || \
|
||||
((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV6) || \
|
||||
((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV8) || \
|
||||
((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV10) || \
|
||||
((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV12) || \
|
||||
((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV16) || \
|
||||
((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV32) || \
|
||||
((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV64) || \
|
||||
((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV128) || \
|
||||
((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV256))
|
||||
|
||||
/**
|
||||
* @brief Ensure that IRDA state is valid.
|
||||
* @param __STATE__ IRDA state mode.
|
||||
* @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid)
|
||||
*/
|
||||
#define IS_IRDA_STATE(__STATE__) (((__STATE__) == IRDA_STATE_DISABLE) || \
|
||||
((__STATE__) == IRDA_STATE_ENABLE))
|
||||
|
||||
/**
|
||||
* @brief Ensure that IRDA associated UART/USART mode is valid.
|
||||
* @param __MODE__ IRDA associated UART/USART mode.
|
||||
* @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
|
||||
*/
|
||||
#define IS_IRDA_MODE(__MODE__) (((__MODE__) == IRDA_MODE_DISABLE) || \
|
||||
((__MODE__) == IRDA_MODE_ENABLE))
|
||||
|
||||
/**
|
||||
* @brief Ensure that IRDA sampling rate is valid.
|
||||
* @param __ONEBIT__ IRDA sampling rate.
|
||||
* @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid)
|
||||
*/
|
||||
#define IS_IRDA_ONE_BIT_SAMPLE(__ONEBIT__) (((__ONEBIT__) == IRDA_ONE_BIT_SAMPLE_DISABLE) || \
|
||||
((__ONEBIT__) == IRDA_ONE_BIT_SAMPLE_ENABLE))
|
||||
|
||||
/**
|
||||
* @brief Ensure that IRDA DMA TX mode is valid.
|
||||
* @param __DMATX__ IRDA DMA TX mode.
|
||||
* @retval SET (__DMATX__ is valid) or RESET (__DMATX__ is invalid)
|
||||
*/
|
||||
#define IS_IRDA_DMA_TX(__DMATX__) (((__DMATX__) == IRDA_DMA_TX_DISABLE) || \
|
||||
((__DMATX__) == IRDA_DMA_TX_ENABLE))
|
||||
|
||||
/**
|
||||
* @brief Ensure that IRDA DMA RX mode is valid.
|
||||
* @param __DMARX__ IRDA DMA RX mode.
|
||||
* @retval SET (__DMARX__ is valid) or RESET (__DMARX__ is invalid)
|
||||
*/
|
||||
#define IS_IRDA_DMA_RX(__DMARX__) (((__DMARX__) == IRDA_DMA_RX_DISABLE) || \
|
||||
((__DMARX__) == IRDA_DMA_RX_ENABLE))
|
||||
|
||||
/**
|
||||
* @brief Ensure that IRDA request is valid.
|
||||
* @param __PARAM__ IRDA request.
|
||||
* @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)
|
||||
*/
|
||||
#define IS_IRDA_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == IRDA_AUTOBAUD_REQUEST) || \
|
||||
((__PARAM__) == IRDA_RXDATA_FLUSH_REQUEST) || \
|
||||
((__PARAM__) == IRDA_TXDATA_FLUSH_REQUEST))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Include IRDA HAL Extended module */
|
||||
#include "stm32wbxx_hal_irda_ex.h"
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup IRDA_Exported_Functions IRDA Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup IRDA_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Initialization and de-initialization functions ****************************/
|
||||
HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda);
|
||||
HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda);
|
||||
void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda);
|
||||
void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda);
|
||||
|
||||
#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
|
||||
/* Callbacks Register/UnRegister functions ***********************************/
|
||||
HAL_StatusTypeDef HAL_IRDA_RegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID, pIRDA_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_IRDA_UnRegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID);
|
||||
#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup IRDA_Exported_Functions_Group2 IO operation functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* IO operation functions *****************************************************/
|
||||
HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda);
|
||||
HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda);
|
||||
HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda);
|
||||
/* Transfer Abort functions */
|
||||
HAL_StatusTypeDef HAL_IRDA_Abort(IRDA_HandleTypeDef *hirda);
|
||||
HAL_StatusTypeDef HAL_IRDA_AbortTransmit(IRDA_HandleTypeDef *hirda);
|
||||
HAL_StatusTypeDef HAL_IRDA_AbortReceive(IRDA_HandleTypeDef *hirda);
|
||||
HAL_StatusTypeDef HAL_IRDA_Abort_IT(IRDA_HandleTypeDef *hirda);
|
||||
HAL_StatusTypeDef HAL_IRDA_AbortTransmit_IT(IRDA_HandleTypeDef *hirda);
|
||||
HAL_StatusTypeDef HAL_IRDA_AbortReceive_IT(IRDA_HandleTypeDef *hirda);
|
||||
|
||||
void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda);
|
||||
void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda);
|
||||
void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda);
|
||||
void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda);
|
||||
void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda);
|
||||
void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda);
|
||||
void HAL_IRDA_AbortCpltCallback(IRDA_HandleTypeDef *hirda);
|
||||
void HAL_IRDA_AbortTransmitCpltCallback(IRDA_HandleTypeDef *hirda);
|
||||
void HAL_IRDA_AbortReceiveCpltCallback(IRDA_HandleTypeDef *hirda);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Peripheral Control functions ************************************************/
|
||||
|
||||
/** @addtogroup IRDA_Exported_Functions_Group4 Peripheral State and Error functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Peripheral State and Error functions ***************************************/
|
||||
HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda);
|
||||
uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32WBxx_HAL_IRDA_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -1,104 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32wbxx_hal_irda_ex.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of IRDA HAL Extended module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32WBxx_HAL_IRDA_EX_H
|
||||
#define STM32WBxx_HAL_IRDA_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32wbxx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32WBxx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup IRDAEx IRDAEx
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup IRDAEx_Private_Macros IRDAEx Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Report the IRDA clock source.
|
||||
* @param __HANDLE__ specifies the IRDA Handle.
|
||||
* @param __CLOCKSOURCE__ output variable.
|
||||
* @retval IRDA clocking source, written in __CLOCKSOURCE__.
|
||||
*/
|
||||
#define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
|
||||
do { \
|
||||
if((__HANDLE__)->Instance == USART1) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART1_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART1CLKSOURCE_PCLK2: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK2; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
default: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
|
||||
} \
|
||||
} while(0U)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32WBxx_HAL_IRDA_EX_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -1,240 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32wbxx_hal_iwdg.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of IWDG HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32WBxx_HAL_IWDG_H
|
||||
#define STM32WBxx_HAL_IWDG_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32wbxx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32WBxx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup IWDG IWDG
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup IWDG_Exported_Types IWDG Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief IWDG Init structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Prescaler; /*!< Select the prescaler of the IWDG.
|
||||
This parameter can be a value of @ref IWDG_Prescaler */
|
||||
|
||||
uint32_t Reload; /*!< Specifies the IWDG down-counter reload value.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF */
|
||||
|
||||
uint32_t Window; /*!< Specifies the window value to be compared to the down-counter.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF */
|
||||
|
||||
} IWDG_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief IWDG Handle Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
IWDG_TypeDef *Instance; /*!< Register base address */
|
||||
|
||||
IWDG_InitTypeDef Init; /*!< IWDG required parameters */
|
||||
} IWDG_HandleTypeDef;
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup IWDG_Exported_Constants IWDG Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup IWDG_Prescaler IWDG Prescaler
|
||||
* @{
|
||||
*/
|
||||
#define IWDG_PRESCALER_4 0x00000000u /*!< IWDG prescaler set to 4 */
|
||||
#define IWDG_PRESCALER_8 IWDG_PR_PR_0 /*!< IWDG prescaler set to 8 */
|
||||
#define IWDG_PRESCALER_16 IWDG_PR_PR_1 /*!< IWDG prescaler set to 16 */
|
||||
#define IWDG_PRESCALER_32 (IWDG_PR_PR_1 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 32 */
|
||||
#define IWDG_PRESCALER_64 IWDG_PR_PR_2 /*!< IWDG prescaler set to 64 */
|
||||
#define IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 128 */
|
||||
#define IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1) /*!< IWDG prescaler set to 256 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IWDG_Window_option IWDG Window option
|
||||
* @{
|
||||
*/
|
||||
#define IWDG_WINDOW_DISABLE IWDG_WINR_WIN
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/** @defgroup IWDG_Exported_Macros IWDG Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enable the IWDG peripheral.
|
||||
* @param __HANDLE__ IWDG handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IWDG_START(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_ENABLE)
|
||||
|
||||
/**
|
||||
* @brief Reload IWDG counter with value defined in the reload register
|
||||
* (write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers disabled).
|
||||
* @param __HANDLE__ IWDG handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IWDG_RELOAD_COUNTER(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_RELOAD)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup IWDG_Exported_Functions IWDG Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup IWDG_Exported_Functions_Group1 Initialization and Start functions
|
||||
* @{
|
||||
*/
|
||||
/* Initialization/Start functions ********************************************/
|
||||
HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IWDG_Exported_Functions_Group2 IO operation functions
|
||||
* @{
|
||||
*/
|
||||
/* I/O operation functions ****************************************************/
|
||||
HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup IWDG_Private_Constants IWDG Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief IWDG Key Register BitMask
|
||||
*/
|
||||
#define IWDG_KEY_RELOAD 0x0000AAAAu /*!< IWDG Reload Counter Enable */
|
||||
#define IWDG_KEY_ENABLE 0x0000CCCCu /*!< IWDG Peripheral Enable */
|
||||
#define IWDG_KEY_WRITE_ACCESS_ENABLE 0x00005555u /*!< IWDG KR Write Access Enable */
|
||||
#define IWDG_KEY_WRITE_ACCESS_DISABLE 0x00000000u /*!< IWDG KR Write Access Disable */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup IWDG_Private_Macros IWDG Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
|
||||
* @param __HANDLE__ IWDG handle
|
||||
* @retval None
|
||||
*/
|
||||
#define IWDG_ENABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_ENABLE)
|
||||
|
||||
/**
|
||||
* @brief Disable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
|
||||
* @param __HANDLE__ IWDG handle
|
||||
* @retval None
|
||||
*/
|
||||
#define IWDG_DISABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_DISABLE)
|
||||
|
||||
/**
|
||||
* @brief Check IWDG prescaler value.
|
||||
* @param __PRESCALER__ IWDG prescaler value
|
||||
* @retval None
|
||||
*/
|
||||
#define IS_IWDG_PRESCALER(__PRESCALER__) (((__PRESCALER__) == IWDG_PRESCALER_4) || \
|
||||
((__PRESCALER__) == IWDG_PRESCALER_8) || \
|
||||
((__PRESCALER__) == IWDG_PRESCALER_16) || \
|
||||
((__PRESCALER__) == IWDG_PRESCALER_32) || \
|
||||
((__PRESCALER__) == IWDG_PRESCALER_64) || \
|
||||
((__PRESCALER__) == IWDG_PRESCALER_128)|| \
|
||||
((__PRESCALER__) == IWDG_PRESCALER_256))
|
||||
|
||||
/**
|
||||
* @brief Check IWDG reload value.
|
||||
* @param __RELOAD__ IWDG reload value
|
||||
* @retval None
|
||||
*/
|
||||
#define IS_IWDG_RELOAD(__RELOAD__) ((__RELOAD__) <= IWDG_RLR_RL)
|
||||
|
||||
/**
|
||||
* @brief Check IWDG window value.
|
||||
* @param __WINDOW__ IWDG window value
|
||||
* @retval None
|
||||
*/
|
||||
#define IS_IWDG_WINDOW(__WINDOW__) ((__WINDOW__) <= IWDG_WINR_WIN)
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32WBxx_HAL_IWDG_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -1,772 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32wbxx_hal_lcd.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of LCD Controller HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32WBxx_HAL_LCD_H
|
||||
#define STM32WBxx_HAL_LCD_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32wbxx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32WBxx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined (LCD)
|
||||
|
||||
/** @addtogroup LCD
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup LCD_Exported_Types LCD Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief LCD Init structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Prescaler; /*!< Configures the LCD Prescaler.
|
||||
This parameter can be one value of @ref LCD_Prescaler */
|
||||
uint32_t Divider; /*!< Configures the LCD Divider.
|
||||
This parameter can be one value of @ref LCD_Divider */
|
||||
uint32_t Duty; /*!< Configures the LCD Duty.
|
||||
This parameter can be one value of @ref LCD_Duty */
|
||||
uint32_t Bias; /*!< Configures the LCD Bias.
|
||||
This parameter can be one value of @ref LCD_Bias */
|
||||
uint32_t VoltageSource; /*!< Selects the LCD Voltage source.
|
||||
This parameter can be one value of @ref LCD_Voltage_Source */
|
||||
uint32_t Contrast; /*!< Configures the LCD Contrast.
|
||||
This parameter can be one value of @ref LCD_Contrast */
|
||||
uint32_t DeadTime; /*!< Configures the LCD Dead Time.
|
||||
This parameter can be one value of @ref LCD_DeadTime */
|
||||
uint32_t PulseOnDuration; /*!< Configures the LCD Pulse On Duration.
|
||||
This parameter can be one value of @ref LCD_PulseOnDuration */
|
||||
uint32_t HighDrive; /*!< Enable or disable the low resistance divider.
|
||||
This parameter can be one value of @ref LCD_HighDrive */
|
||||
uint32_t BlinkMode; /*!< Configures the LCD Blink Mode.
|
||||
This parameter can be one value of @ref LCD_BlinkMode */
|
||||
uint32_t BlinkFrequency; /*!< Configures the LCD Blink frequency.
|
||||
This parameter can be one value of @ref LCD_BlinkFrequency */
|
||||
uint32_t MuxSegment; /*!< Enable or disable mux segment.
|
||||
This parameter can be one value of @ref LCD_MuxSegment */
|
||||
} LCD_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL LCD State structures definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_LCD_STATE_RESET = 0x00, /*!< Peripheral is not yet Initialized */
|
||||
HAL_LCD_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */
|
||||
HAL_LCD_STATE_BUSY = 0x02, /*!< an internal process is ongoing */
|
||||
HAL_LCD_STATE_TIMEOUT = 0x03, /*!< Timeout state */
|
||||
HAL_LCD_STATE_ERROR = 0x04 /*!< Error */
|
||||
} HAL_LCD_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief UART handle Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
LCD_TypeDef *Instance; /* LCD registers base address */
|
||||
|
||||
LCD_InitTypeDef Init; /* LCD communication parameters */
|
||||
|
||||
HAL_LockTypeDef Lock; /* Locking object */
|
||||
|
||||
__IO HAL_LCD_StateTypeDef State; /* LCD communication state */
|
||||
|
||||
__IO uint32_t ErrorCode; /* LCD Error code */
|
||||
|
||||
} LCD_HandleTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup LCD_Exported_Constants LCD Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup LCD_ErrorCode LCD Error Code
|
||||
* @{
|
||||
*/
|
||||
#define HAL_LCD_ERROR_NONE (0x00000000U) /*!< No error */
|
||||
#define HAL_LCD_ERROR_FCRSF (0x00000001U) /*!< Synchro flag timeout error */
|
||||
#define HAL_LCD_ERROR_UDR (0x00000002U) /*!< Update display request flag timeout error */
|
||||
#define HAL_LCD_ERROR_UDD (0x00000004U) /*!< Update display done flag timeout error */
|
||||
#define HAL_LCD_ERROR_ENS (0x00000008U) /*!< LCD enabled status flag timeout error */
|
||||
#define HAL_LCD_ERROR_RDY (0x00000010U) /*!< LCD Booster ready timeout error */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LCD_Prescaler LCD Prescaler
|
||||
* @{
|
||||
*/
|
||||
#define LCD_PRESCALER_1 (0x00000000U) /*!< CLKPS = LCDCLK */
|
||||
#define LCD_PRESCALER_2 (0x00400000U) /*!< CLKPS = LCDCLK/2 */
|
||||
#define LCD_PRESCALER_4 (0x00800000U) /*!< CLKPS = LCDCLK/4 */
|
||||
#define LCD_PRESCALER_8 (0x00C00000U) /*!< CLKPS = LCDCLK/8 */
|
||||
#define LCD_PRESCALER_16 (0x01000000U) /*!< CLKPS = LCDCLK/16 */
|
||||
#define LCD_PRESCALER_32 (0x01400000U) /*!< CLKPS = LCDCLK/32 */
|
||||
#define LCD_PRESCALER_64 (0x01800000U) /*!< CLKPS = LCDCLK/64 */
|
||||
#define LCD_PRESCALER_128 (0x01C00000U) /*!< CLKPS = LCDCLK/128 */
|
||||
#define LCD_PRESCALER_256 (0x02000000U) /*!< CLKPS = LCDCLK/256 */
|
||||
#define LCD_PRESCALER_512 (0x02400000U) /*!< CLKPS = LCDCLK/512 */
|
||||
#define LCD_PRESCALER_1024 (0x02800000U) /*!< CLKPS = LCDCLK/1024 */
|
||||
#define LCD_PRESCALER_2048 (0x02C00000U) /*!< CLKPS = LCDCLK/2048 */
|
||||
#define LCD_PRESCALER_4096 (0x03000000U) /*!< CLKPS = LCDCLK/4096 */
|
||||
#define LCD_PRESCALER_8192 (0x03400000U) /*!< CLKPS = LCDCLK/8192 */
|
||||
#define LCD_PRESCALER_16384 (0x03800000U) /*!< CLKPS = LCDCLK/16384 */
|
||||
#define LCD_PRESCALER_32768 (0x03C00000U) /*!< CLKPS = LCDCLK/32768 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LCD_Divider LCD Divider
|
||||
* @{
|
||||
*/
|
||||
#define LCD_DIVIDER_16 (0x00000000U) /*!< LCD frequency = CLKPS/16 */
|
||||
#define LCD_DIVIDER_17 (0x00040000U) /*!< LCD frequency = CLKPS/17 */
|
||||
#define LCD_DIVIDER_18 (0x00080000U) /*!< LCD frequency = CLKPS/18 */
|
||||
#define LCD_DIVIDER_19 (0x000C0000U) /*!< LCD frequency = CLKPS/19 */
|
||||
#define LCD_DIVIDER_20 (0x00100000U) /*!< LCD frequency = CLKPS/20 */
|
||||
#define LCD_DIVIDER_21 (0x00140000U) /*!< LCD frequency = CLKPS/21 */
|
||||
#define LCD_DIVIDER_22 (0x00180000U) /*!< LCD frequency = CLKPS/22 */
|
||||
#define LCD_DIVIDER_23 (0x001C0000U) /*!< LCD frequency = CLKPS/23 */
|
||||
#define LCD_DIVIDER_24 (0x00200000U) /*!< LCD frequency = CLKPS/24 */
|
||||
#define LCD_DIVIDER_25 (0x00240000U) /*!< LCD frequency = CLKPS/25 */
|
||||
#define LCD_DIVIDER_26 (0x00280000U) /*!< LCD frequency = CLKPS/26 */
|
||||
#define LCD_DIVIDER_27 (0x002C0000U) /*!< LCD frequency = CLKPS/27 */
|
||||
#define LCD_DIVIDER_28 (0x00300000U) /*!< LCD frequency = CLKPS/28 */
|
||||
#define LCD_DIVIDER_29 (0x00340000U) /*!< LCD frequency = CLKPS/29 */
|
||||
#define LCD_DIVIDER_30 (0x00380000U) /*!< LCD frequency = CLKPS/30 */
|
||||
#define LCD_DIVIDER_31 (0x003C0000U) /*!< LCD frequency = CLKPS/31 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup LCD_Duty LCD Duty
|
||||
* @{
|
||||
*/
|
||||
#define LCD_DUTY_STATIC (0x00000000U) /*!< Static duty */
|
||||
#define LCD_DUTY_1_2 (LCD_CR_DUTY_0) /*!< 1/2 duty */
|
||||
#define LCD_DUTY_1_3 (LCD_CR_DUTY_1) /*!< 1/3 duty */
|
||||
#define LCD_DUTY_1_4 ((LCD_CR_DUTY_1 | LCD_CR_DUTY_0)) /*!< 1/4 duty */
|
||||
#define LCD_DUTY_1_8 (LCD_CR_DUTY_2) /*!< 1/8 duty */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup LCD_Bias LCD Bias
|
||||
* @{
|
||||
*/
|
||||
#define LCD_BIAS_1_4 (0x00000000U) /*!< 1/4 Bias */
|
||||
#define LCD_BIAS_1_2 LCD_CR_BIAS_0 /*!< 1/2 Bias */
|
||||
#define LCD_BIAS_1_3 LCD_CR_BIAS_1 /*!< 1/3 Bias */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LCD_Voltage_Source LCD Voltage Source
|
||||
* @{
|
||||
*/
|
||||
#define LCD_VOLTAGESOURCE_INTERNAL (0x00000000U) /*!< Internal voltage source for the LCD */
|
||||
#define LCD_VOLTAGESOURCE_EXTERNAL LCD_CR_VSEL /*!< External voltage source for the LCD */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LCD_Interrupts LCD Interrupts
|
||||
* @{
|
||||
*/
|
||||
#define LCD_IT_SOF LCD_FCR_SOFIE
|
||||
#define LCD_IT_UDD LCD_FCR_UDDIE
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LCD_PulseOnDuration LCD Pulse On Duration
|
||||
* @{
|
||||
*/
|
||||
#define LCD_PULSEONDURATION_0 (0x00000000U) /*!< Pulse ON duration = 0 pulse */
|
||||
#define LCD_PULSEONDURATION_1 (LCD_FCR_PON_0) /*!< Pulse ON duration = 1/CK_PS */
|
||||
#define LCD_PULSEONDURATION_2 (LCD_FCR_PON_1) /*!< Pulse ON duration = 2/CK_PS */
|
||||
#define LCD_PULSEONDURATION_3 (LCD_FCR_PON_1 | LCD_FCR_PON_0) /*!< Pulse ON duration = 3/CK_PS */
|
||||
#define LCD_PULSEONDURATION_4 (LCD_FCR_PON_2) /*!< Pulse ON duration = 4/CK_PS */
|
||||
#define LCD_PULSEONDURATION_5 (LCD_FCR_PON_2 | LCD_FCR_PON_0) /*!< Pulse ON duration = 5/CK_PS */
|
||||
#define LCD_PULSEONDURATION_6 (LCD_FCR_PON_2 | LCD_FCR_PON_1) /*!< Pulse ON duration = 6/CK_PS */
|
||||
#define LCD_PULSEONDURATION_7 (LCD_FCR_PON) /*!< Pulse ON duration = 7/CK_PS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup LCD_DeadTime LCD Dead Time
|
||||
* @{
|
||||
*/
|
||||
#define LCD_DEADTIME_0 (0x00000000U) /*!< No dead Time */
|
||||
#define LCD_DEADTIME_1 (LCD_FCR_DEAD_0) /*!< One Phase between different couple of Frame */
|
||||
#define LCD_DEADTIME_2 (LCD_FCR_DEAD_1) /*!< Two Phase between different couple of Frame */
|
||||
#define LCD_DEADTIME_3 (LCD_FCR_DEAD_1 | LCD_FCR_DEAD_0) /*!< Three Phase between different couple of Frame */
|
||||
#define LCD_DEADTIME_4 (LCD_FCR_DEAD_2) /*!< Four Phase between different couple of Frame */
|
||||
#define LCD_DEADTIME_5 (LCD_FCR_DEAD_2 | LCD_FCR_DEAD_0) /*!< Five Phase between different couple of Frame */
|
||||
#define LCD_DEADTIME_6 (LCD_FCR_DEAD_2 | LCD_FCR_DEAD_1) /*!< Six Phase between different couple of Frame */
|
||||
#define LCD_DEADTIME_7 (LCD_FCR_DEAD) /*!< Seven Phase between different couple of Frame */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LCD_BlinkMode LCD Blink Mode
|
||||
* @{
|
||||
*/
|
||||
#define LCD_BLINKMODE_OFF (0x00000000U) /*!< Blink disabled */
|
||||
#define LCD_BLINKMODE_SEG0_COM0 (LCD_FCR_BLINK_0) /*!< Blink enabled on SEG[0], COM[0] (1 pixel) */
|
||||
#define LCD_BLINKMODE_SEG0_ALLCOM (LCD_FCR_BLINK_1) /*!< Blink enabled on SEG[0], all COM (up to
|
||||
8 pixels according to the programmed duty) */
|
||||
#define LCD_BLINKMODE_ALLSEG_ALLCOM (LCD_FCR_BLINK) /*!< Blink enabled on all SEG and all COM (all pixels) */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LCD_BlinkFrequency LCD Blink Frequency
|
||||
* @{
|
||||
*/
|
||||
#define LCD_BLINKFREQUENCY_DIV8 (0x00000000U) /*!< The Blink frequency = fLCD/8 */
|
||||
#define LCD_BLINKFREQUENCY_DIV16 (LCD_FCR_BLINKF_0) /*!< The Blink frequency = fLCD/16 */
|
||||
#define LCD_BLINKFREQUENCY_DIV32 (LCD_FCR_BLINKF_1) /*!< The Blink frequency = fLCD/32 */
|
||||
#define LCD_BLINKFREQUENCY_DIV64 (LCD_FCR_BLINKF_1 | LCD_FCR_BLINKF_0) /*!< The Blink frequency = fLCD/64 */
|
||||
#define LCD_BLINKFREQUENCY_DIV128 (LCD_FCR_BLINKF_2) /*!< The Blink frequency = fLCD/128 */
|
||||
#define LCD_BLINKFREQUENCY_DIV256 (LCD_FCR_BLINKF_2 |LCD_FCR_BLINKF_0) /*!< The Blink frequency = fLCD/256 */
|
||||
#define LCD_BLINKFREQUENCY_DIV512 (LCD_FCR_BLINKF_2 |LCD_FCR_BLINKF_1) /*!< The Blink frequency = fLCD/512 */
|
||||
#define LCD_BLINKFREQUENCY_DIV1024 (LCD_FCR_BLINKF) /*!< The Blink frequency = fLCD/1024 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LCD_Contrast LCD Contrast
|
||||
* @{
|
||||
*/
|
||||
#define LCD_CONTRASTLEVEL_0 (0x00000000U) /*!< Maximum Voltage = 2.60V */
|
||||
#define LCD_CONTRASTLEVEL_1 (LCD_FCR_CC_0) /*!< Maximum Voltage = 2.73V */
|
||||
#define LCD_CONTRASTLEVEL_2 (LCD_FCR_CC_1) /*!< Maximum Voltage = 2.86V */
|
||||
#define LCD_CONTRASTLEVEL_3 (LCD_FCR_CC_1 | LCD_FCR_CC_0) /*!< Maximum Voltage = 2.99V */
|
||||
#define LCD_CONTRASTLEVEL_4 (LCD_FCR_CC_2) /*!< Maximum Voltage = 3.12V */
|
||||
#define LCD_CONTRASTLEVEL_5 (LCD_FCR_CC_2 | LCD_FCR_CC_0) /*!< Maximum Voltage = 3.26V */
|
||||
#define LCD_CONTRASTLEVEL_6 (LCD_FCR_CC_2 | LCD_FCR_CC_1) /*!< Maximum Voltage = 3.40V */
|
||||
#define LCD_CONTRASTLEVEL_7 (LCD_FCR_CC) /*!< Maximum Voltage = 3.55V */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LCD_RAMRegister LCD RAMRegister
|
||||
* @{
|
||||
*/
|
||||
#define LCD_RAM_REGISTER0 (0x00000000U) /*!< LCD RAM Register 0 */
|
||||
#define LCD_RAM_REGISTER1 (0x00000001U) /*!< LCD RAM Register 1 */
|
||||
#define LCD_RAM_REGISTER2 (0x00000002U) /*!< LCD RAM Register 2 */
|
||||
#define LCD_RAM_REGISTER3 (0x00000003U) /*!< LCD RAM Register 3 */
|
||||
#define LCD_RAM_REGISTER4 (0x00000004U) /*!< LCD RAM Register 4 */
|
||||
#define LCD_RAM_REGISTER5 (0x00000005U) /*!< LCD RAM Register 5 */
|
||||
#define LCD_RAM_REGISTER6 (0x00000006U) /*!< LCD RAM Register 6 */
|
||||
#define LCD_RAM_REGISTER7 (0x00000007U) /*!< LCD RAM Register 7 */
|
||||
#define LCD_RAM_REGISTER8 (0x00000008U) /*!< LCD RAM Register 8 */
|
||||
#define LCD_RAM_REGISTER9 (0x00000009U) /*!< LCD RAM Register 9 */
|
||||
#define LCD_RAM_REGISTER10 (0x0000000AU) /*!< LCD RAM Register 10 */
|
||||
#define LCD_RAM_REGISTER11 (0x0000000BU) /*!< LCD RAM Register 11 */
|
||||
#define LCD_RAM_REGISTER12 (0x0000000CU) /*!< LCD RAM Register 12 */
|
||||
#define LCD_RAM_REGISTER13 (0x0000000DU) /*!< LCD RAM Register 13 */
|
||||
#define LCD_RAM_REGISTER14 (0x0000000EU) /*!< LCD RAM Register 14 */
|
||||
#define LCD_RAM_REGISTER15 (0x0000000FU) /*!< LCD RAM Register 15 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LCD_HighDrive LCD High Drive
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define LCD_HIGHDRIVE_DISABLE ((uint32_t)0x00000000) /*!< High drive disabled */
|
||||
#define LCD_HIGHDRIVE_ENABLE (LCD_FCR_HD) /*!< High drive enabled */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LCD_MuxSegment LCD Mux Segment
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define LCD_MUXSEGMENT_DISABLE (0x00000000U) /*!< SEG pin multiplexing disabled */
|
||||
#define LCD_MUXSEGMENT_ENABLE (LCD_CR_MUX_SEG) /*!< SEG[31:28] are multiplexed with SEG[43:40] */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LCD_Flag_Definition LCD Flags Definition
|
||||
* @{
|
||||
*/
|
||||
#define LCD_FLAG_ENS LCD_SR_ENS /*!< LCD enabled status */
|
||||
#define LCD_FLAG_SOF LCD_SR_SOF /*!< Start of frame flag */
|
||||
#define LCD_FLAG_UDR LCD_SR_UDR /*!< Update display request */
|
||||
#define LCD_FLAG_UDD LCD_SR_UDD /*!< Update display done */
|
||||
#define LCD_FLAG_RDY LCD_SR_RDY /*!< Ready flag */
|
||||
#define LCD_FLAG_FCRSF LCD_SR_FCRSR /*!< LCD Frame Control Register Synchronization flag */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/** @defgroup LCD_Exported_Macros LCD Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset LCD handle state.
|
||||
* @param __HANDLE__ specifies the LCD Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_LCD_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_LCD_STATE_RESET)
|
||||
|
||||
/** @brief Enable the LCD peripheral.
|
||||
* @param __HANDLE__ specifies the LCD Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_LCD_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, LCD_CR_LCDEN)
|
||||
|
||||
/** @brief Disable the LCD peripheral.
|
||||
* @param __HANDLE__ specifies the LCD Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_LCD_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, LCD_CR_LCDEN)
|
||||
|
||||
/** @brief Enable the low resistance divider.
|
||||
* @param __HANDLE__ specifies the LCD Handle.
|
||||
* @note Displays with high internal resistance may need a longer drive time to
|
||||
* achieve satisfactory contrast. This function is useful in this case if
|
||||
* some additional power consumption can be tolerated.
|
||||
* @note When this mode is enabled, the PulseOn Duration (PON) have to be
|
||||
* programmed to 1/CK_PS (LCD_PULSEONDURATION_1).
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_LCD_HIGHDRIVER_ENABLE(__HANDLE__) \
|
||||
do { \
|
||||
SET_BIT((__HANDLE__)->Instance->FCR, LCD_FCR_HD); \
|
||||
LCD_WaitForSynchro(__HANDLE__); \
|
||||
} while(0)
|
||||
|
||||
/** @brief Disable the low resistance divider.
|
||||
* @param __HANDLE__ specifies the LCD Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_LCD_HIGHDRIVER_DISABLE(__HANDLE__) \
|
||||
do { \
|
||||
CLEAR_BIT((__HANDLE__)->Instance->FCR, LCD_FCR_HD); \
|
||||
LCD_WaitForSynchro(__HANDLE__); \
|
||||
} while(0)
|
||||
|
||||
/** @brief Enable the voltage output buffer for higher driving capability.
|
||||
* @param __HANDLE__ specifies the LCD Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_LCD_VOLTAGE_BUFFER_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, LCD_CR_BUFEN)
|
||||
|
||||
/** @brief Disable the voltage output buffer for higher driving capability.
|
||||
* @param __HANDLE__ specifies the LCD Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_LCD_VOLTAGE_BUFFER_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, LCD_CR_BUFEN)
|
||||
|
||||
/**
|
||||
* @brief Configure the LCD pulse on duration.
|
||||
* @param __HANDLE__ specifies the LCD Handle.
|
||||
* @param __DURATION__ specifies the LCD pulse on duration in terms of
|
||||
* CK_PS (prescaled LCD clock period) pulses.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg LCD_PULSEONDURATION_0: 0 pulse
|
||||
* @arg LCD_PULSEONDURATION_1: Pulse ON duration = 1/CK_PS
|
||||
* @arg LCD_PULSEONDURATION_2: Pulse ON duration = 2/CK_PS
|
||||
* @arg LCD_PULSEONDURATION_3: Pulse ON duration = 3/CK_PS
|
||||
* @arg LCD_PULSEONDURATION_4: Pulse ON duration = 4/CK_PS
|
||||
* @arg LCD_PULSEONDURATION_5: Pulse ON duration = 5/CK_PS
|
||||
* @arg LCD_PULSEONDURATION_6: Pulse ON duration = 6/CK_PS
|
||||
* @arg LCD_PULSEONDURATION_7: Pulse ON duration = 7/CK_PS
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_LCD_PULSEONDURATION_CONFIG(__HANDLE__, __DURATION__) \
|
||||
do { \
|
||||
MODIFY_REG((__HANDLE__)->Instance->FCR, LCD_FCR_PON, (__DURATION__)); \
|
||||
LCD_WaitForSynchro(__HANDLE__); \
|
||||
} while(0)
|
||||
|
||||
/**
|
||||
* @brief Configure the LCD dead time.
|
||||
* @param __HANDLE__ specifies the LCD Handle.
|
||||
* @param __DEADTIME__ specifies the LCD dead time.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg LCD_DEADTIME_0: No dead Time
|
||||
* @arg LCD_DEADTIME_1: One Phase between different couple of Frame
|
||||
* @arg LCD_DEADTIME_2: Two Phase between different couple of Frame
|
||||
* @arg LCD_DEADTIME_3: Three Phase between different couple of Frame
|
||||
* @arg LCD_DEADTIME_4: Four Phase between different couple of Frame
|
||||
* @arg LCD_DEADTIME_5: Five Phase between different couple of Frame
|
||||
* @arg LCD_DEADTIME_6: Six Phase between different couple of Frame
|
||||
* @arg LCD_DEADTIME_7: Seven Phase between different couple of Frame
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_LCD_DEADTIME_CONFIG(__HANDLE__, __DEADTIME__) \
|
||||
do { \
|
||||
MODIFY_REG((__HANDLE__)->Instance->FCR, LCD_FCR_DEAD, (__DEADTIME__)); \
|
||||
LCD_WaitForSynchro(__HANDLE__); \
|
||||
} while(0)
|
||||
|
||||
/**
|
||||
* @brief Configure the LCD contrast.
|
||||
* @param __HANDLE__ specifies the LCD Handle.
|
||||
* @param __CONTRAST__ specifies the LCD Contrast.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg LCD_CONTRASTLEVEL_0: Maximum Voltage = 2.60V
|
||||
* @arg LCD_CONTRASTLEVEL_1: Maximum Voltage = 2.73V
|
||||
* @arg LCD_CONTRASTLEVEL_2: Maximum Voltage = 2.86V
|
||||
* @arg LCD_CONTRASTLEVEL_3: Maximum Voltage = 2.99V
|
||||
* @arg LCD_CONTRASTLEVEL_4: Maximum Voltage = 3.12V
|
||||
* @arg LCD_CONTRASTLEVEL_5: Maximum Voltage = 3.25V
|
||||
* @arg LCD_CONTRASTLEVEL_6: Maximum Voltage = 3.38V
|
||||
* @arg LCD_CONTRASTLEVEL_7: Maximum Voltage = 3.51V
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_LCD_CONTRAST_CONFIG(__HANDLE__, __CONTRAST__) \
|
||||
do { \
|
||||
MODIFY_REG((__HANDLE__)->Instance->FCR, LCD_FCR_CC, (__CONTRAST__)); \
|
||||
LCD_WaitForSynchro(__HANDLE__); \
|
||||
} while(0)
|
||||
|
||||
/**
|
||||
* @brief Configure the LCD Blink mode and Blink frequency.
|
||||
* @param __HANDLE__ specifies the LCD Handle.
|
||||
* @param __BLINKMODE__ specifies the LCD blink mode.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg LCD_BLINKMODE_OFF: Blink disabled
|
||||
* @arg LCD_BLINKMODE_SEG0_COM0: Blink enabled on SEG[0], COM[0] (1 pixel)
|
||||
* @arg LCD_BLINKMODE_SEG0_ALLCOM: Blink enabled on SEG[0], all COM (up to 8
|
||||
* pixels according to the programmed duty)
|
||||
* @arg LCD_BLINKMODE_ALLSEG_ALLCOM: Blink enabled on all SEG and all COM
|
||||
* (all pixels)
|
||||
* @param __BLINKFREQUENCY__ specifies the LCD blink frequency.
|
||||
* @arg LCD_BLINKFREQUENCY_DIV8: The Blink frequency = fLcd/8
|
||||
* @arg LCD_BLINKFREQUENCY_DIV16: The Blink frequency = fLcd/16
|
||||
* @arg LCD_BLINKFREQUENCY_DIV32: The Blink frequency = fLcd/32
|
||||
* @arg LCD_BLINKFREQUENCY_DIV64: The Blink frequency = fLcd/64
|
||||
* @arg LCD_BLINKFREQUENCY_DIV128: The Blink frequency = fLcd/128
|
||||
* @arg LCD_BLINKFREQUENCY_DIV256: The Blink frequency = fLcd/256
|
||||
* @arg LCD_BLINKFREQUENCY_DIV512: The Blink frequency = fLcd/512
|
||||
* @arg LCD_BLINKFREQUENCY_DIV1024: The Blink frequency = fLcd/1024
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_LCD_BLINK_CONFIG(__HANDLE__, __BLINKMODE__, __BLINKFREQUENCY__) \
|
||||
do { \
|
||||
MODIFY_REG((__HANDLE__)->Instance->FCR, (LCD_FCR_BLINKF | LCD_FCR_BLINK), ((__BLINKMODE__) | (__BLINKFREQUENCY__))); \
|
||||
LCD_WaitForSynchro(__HANDLE__); \
|
||||
} while(0)
|
||||
|
||||
/** @brief Enable the specified LCD interrupt.
|
||||
* @param __HANDLE__ specifies the LCD Handle.
|
||||
* @param __INTERRUPT__ specifies the LCD interrupt source to be enabled.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg LCD_IT_SOF: Start of Frame Interrupt
|
||||
* @arg LCD_IT_UDD: Update Display Done Interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_LCD_ENABLE_IT(__HANDLE__, __INTERRUPT__) \
|
||||
do { \
|
||||
SET_BIT((__HANDLE__)->Instance->FCR, (__INTERRUPT__)); \
|
||||
LCD_WaitForSynchro(__HANDLE__); \
|
||||
} while(0)
|
||||
|
||||
/** @brief Disable the specified LCD interrupt.
|
||||
* @param __HANDLE__ specifies the LCD Handle.
|
||||
* @param __INTERRUPT__ specifies the LCD interrupt source to be disabled.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg LCD_IT_SOF: Start of Frame Interrupt
|
||||
* @arg LCD_IT_UDD: Update Display Done Interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_LCD_DISABLE_IT(__HANDLE__, __INTERRUPT__) \
|
||||
do { \
|
||||
CLEAR_BIT((__HANDLE__)->Instance->FCR, (__INTERRUPT__)); \
|
||||
LCD_WaitForSynchro(__HANDLE__); \
|
||||
} while(0)
|
||||
|
||||
/** @brief Check whether the specified LCD interrupt source is enabled or not.
|
||||
* @param __HANDLE__ specifies the LCD Handle.
|
||||
* @param __IT__ specifies the LCD interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg LCD_IT_SOF: Start of Frame Interrupt
|
||||
* @arg LCD_IT_UDD: Update Display Done Interrupt.
|
||||
* @note If the device is in STOP mode (PCLK not provided) UDD will not
|
||||
* generate an interrupt even if UDDIE = 1.
|
||||
* If the display is not enabled the UDD interrupt will never occur.
|
||||
* @retval The state of __IT__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_LCD_GET_IT_SOURCE(__HANDLE__, __IT__) (((__HANDLE__)->Instance->FCR) & (__IT__))
|
||||
|
||||
/** @brief Check whether the specified LCD flag is set or not.
|
||||
* @param __HANDLE__ specifies the LCD Handle.
|
||||
* @param __FLAG__ specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg LCD_FLAG_ENS: LCD Enabled flag. It indicates the LCD controller status.
|
||||
* @arg LCD_FLAG_SOF: Start of Frame flag. This flag is set by hardware at
|
||||
* the beginning of a new frame, at the same time as the display data is
|
||||
* updated.
|
||||
* @arg LCD_FLAG_UDR: Update Display Request flag.
|
||||
* @arg LCD_FLAG_UDD: Update Display Done flag.
|
||||
* @arg LCD_FLAG_RDY: Step_up converter Ready flag. It indicates the status
|
||||
* of the step-up converter.
|
||||
* @arg LCD_FLAG_FCRSF: LCD Frame Control Register Synchronization Flag.
|
||||
* This flag is set by hardware each time the LCD_FCR register is updated
|
||||
* in the LCDCLK domain.
|
||||
* @note The ENS bit is set immediately when the LCDEN bit in the LCD_CR
|
||||
* goes from 0 to 1. On deactivation it reflects the real status of
|
||||
* LCD so it becomes 0 at the end of the last displayed frame.
|
||||
* @retval The new state of __FLAG__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_LCD_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
|
||||
|
||||
/** @brief Clear the specified LCD pending flag.
|
||||
* @param __HANDLE__ specifies the LCD Handle.
|
||||
* @param __FLAG__ specifies the flag to clear.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg LCD_FLAG_SOF: Start of Frame Interrupt
|
||||
* @arg LCD_FLAG_UDD: Update Display Done Interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_LCD_CLEAR_FLAG(__HANDLE__, __FLAG__) WRITE_REG((__HANDLE__)->Instance->CLR, (__FLAG__))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
/** @addtogroup LCD_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Initialization/de-initialization methods **********************************/
|
||||
/** @addtogroup LCD_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_LCD_DeInit(LCD_HandleTypeDef *hlcd);
|
||||
HAL_StatusTypeDef HAL_LCD_Init(LCD_HandleTypeDef *hlcd);
|
||||
void HAL_LCD_MspInit(LCD_HandleTypeDef *hlcd);
|
||||
void HAL_LCD_MspDeInit(LCD_HandleTypeDef *hlcd);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* IO operation methods *******************************************************/
|
||||
/** @addtogroup LCD_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_LCD_Write(LCD_HandleTypeDef *hlcd, uint32_t RAMRegisterIndex, uint32_t RAMRegisterMask, uint32_t Data);
|
||||
HAL_StatusTypeDef HAL_LCD_Clear(LCD_HandleTypeDef *hlcd);
|
||||
HAL_StatusTypeDef HAL_LCD_UpdateDisplayRequest(LCD_HandleTypeDef *hlcd);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Peripheral State methods **************************************************/
|
||||
/** @addtogroup LCD_Exported_Functions_Group3
|
||||
* @{
|
||||
*/
|
||||
HAL_LCD_StateTypeDef HAL_LCD_GetState(LCD_HandleTypeDef *hlcd);
|
||||
uint32_t HAL_LCD_GetError(LCD_HandleTypeDef *hlcd);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup LCD_Private_Macros LCD Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_LCD_PRESCALER(__PRESCALER__) (((__PRESCALER__) == LCD_PRESCALER_1) || \
|
||||
((__PRESCALER__) == LCD_PRESCALER_2) || \
|
||||
((__PRESCALER__) == LCD_PRESCALER_4) || \
|
||||
((__PRESCALER__) == LCD_PRESCALER_8) || \
|
||||
((__PRESCALER__) == LCD_PRESCALER_16) || \
|
||||
((__PRESCALER__) == LCD_PRESCALER_32) || \
|
||||
((__PRESCALER__) == LCD_PRESCALER_64) || \
|
||||
((__PRESCALER__) == LCD_PRESCALER_128) || \
|
||||
((__PRESCALER__) == LCD_PRESCALER_256) || \
|
||||
((__PRESCALER__) == LCD_PRESCALER_512) || \
|
||||
((__PRESCALER__) == LCD_PRESCALER_1024) || \
|
||||
((__PRESCALER__) == LCD_PRESCALER_2048) || \
|
||||
((__PRESCALER__) == LCD_PRESCALER_4096) || \
|
||||
((__PRESCALER__) == LCD_PRESCALER_8192) || \
|
||||
((__PRESCALER__) == LCD_PRESCALER_16384) || \
|
||||
((__PRESCALER__) == LCD_PRESCALER_32768))
|
||||
|
||||
#define IS_LCD_DIVIDER(__DIVIDER__) (((__DIVIDER__) == LCD_DIVIDER_16) || \
|
||||
((__DIVIDER__) == LCD_DIVIDER_17) || \
|
||||
((__DIVIDER__) == LCD_DIVIDER_18) || \
|
||||
((__DIVIDER__) == LCD_DIVIDER_19) || \
|
||||
((__DIVIDER__) == LCD_DIVIDER_20) || \
|
||||
((__DIVIDER__) == LCD_DIVIDER_21) || \
|
||||
((__DIVIDER__) == LCD_DIVIDER_22) || \
|
||||
((__DIVIDER__) == LCD_DIVIDER_23) || \
|
||||
((__DIVIDER__) == LCD_DIVIDER_24) || \
|
||||
((__DIVIDER__) == LCD_DIVIDER_25) || \
|
||||
((__DIVIDER__) == LCD_DIVIDER_26) || \
|
||||
((__DIVIDER__) == LCD_DIVIDER_27) || \
|
||||
((__DIVIDER__) == LCD_DIVIDER_28) || \
|
||||
((__DIVIDER__) == LCD_DIVIDER_29) || \
|
||||
((__DIVIDER__) == LCD_DIVIDER_30) || \
|
||||
((__DIVIDER__) == LCD_DIVIDER_31))
|
||||
|
||||
#define IS_LCD_DUTY(__DUTY__) (((__DUTY__) == LCD_DUTY_STATIC) || \
|
||||
((__DUTY__) == LCD_DUTY_1_2) || \
|
||||
((__DUTY__) == LCD_DUTY_1_3) || \
|
||||
((__DUTY__) == LCD_DUTY_1_4) || \
|
||||
((__DUTY__) == LCD_DUTY_1_8))
|
||||
|
||||
#define IS_LCD_BIAS(__BIAS__) (((__BIAS__) == LCD_BIAS_1_4) || \
|
||||
((__BIAS__) == LCD_BIAS_1_2) || \
|
||||
((__BIAS__) == LCD_BIAS_1_3))
|
||||
|
||||
#define IS_LCD_VOLTAGE_SOURCE(SOURCE) (((SOURCE) == LCD_VOLTAGESOURCE_INTERNAL) || \
|
||||
((SOURCE) == LCD_VOLTAGESOURCE_EXTERNAL))
|
||||
|
||||
|
||||
#define IS_LCD_PULSE_ON_DURATION(__DURATION__) (((__DURATION__) == LCD_PULSEONDURATION_0) || \
|
||||
((__DURATION__) == LCD_PULSEONDURATION_1) || \
|
||||
((__DURATION__) == LCD_PULSEONDURATION_2) || \
|
||||
((__DURATION__) == LCD_PULSEONDURATION_3) || \
|
||||
((__DURATION__) == LCD_PULSEONDURATION_4) || \
|
||||
((__DURATION__) == LCD_PULSEONDURATION_5) || \
|
||||
((__DURATION__) == LCD_PULSEONDURATION_6) || \
|
||||
((__DURATION__) == LCD_PULSEONDURATION_7))
|
||||
|
||||
#define IS_LCD_DEAD_TIME(__TIME__) (((__TIME__) == LCD_DEADTIME_0) || \
|
||||
((__TIME__) == LCD_DEADTIME_1) || \
|
||||
((__TIME__) == LCD_DEADTIME_2) || \
|
||||
((__TIME__) == LCD_DEADTIME_3) || \
|
||||
((__TIME__) == LCD_DEADTIME_4) || \
|
||||
((__TIME__) == LCD_DEADTIME_5) || \
|
||||
((__TIME__) == LCD_DEADTIME_6) || \
|
||||
((__TIME__) == LCD_DEADTIME_7))
|
||||
|
||||
#define IS_LCD_BLINK_MODE(__MODE__) (((__MODE__) == LCD_BLINKMODE_OFF) || \
|
||||
((__MODE__) == LCD_BLINKMODE_SEG0_COM0) || \
|
||||
((__MODE__) == LCD_BLINKMODE_SEG0_ALLCOM) || \
|
||||
((__MODE__) == LCD_BLINKMODE_ALLSEG_ALLCOM))
|
||||
|
||||
#define IS_LCD_BLINK_FREQUENCY(__FREQUENCY__) (((__FREQUENCY__) == LCD_BLINKFREQUENCY_DIV8) || \
|
||||
((__FREQUENCY__) == LCD_BLINKFREQUENCY_DIV16) || \
|
||||
((__FREQUENCY__) == LCD_BLINKFREQUENCY_DIV32) || \
|
||||
((__FREQUENCY__) == LCD_BLINKFREQUENCY_DIV64) || \
|
||||
((__FREQUENCY__) == LCD_BLINKFREQUENCY_DIV128) || \
|
||||
((__FREQUENCY__) == LCD_BLINKFREQUENCY_DIV256) || \
|
||||
((__FREQUENCY__) == LCD_BLINKFREQUENCY_DIV512) || \
|
||||
((__FREQUENCY__) == LCD_BLINKFREQUENCY_DIV1024))
|
||||
|
||||
#define IS_LCD_CONTRAST(__CONTRAST__) (((__CONTRAST__) == LCD_CONTRASTLEVEL_0) || \
|
||||
((__CONTRAST__) == LCD_CONTRASTLEVEL_1) || \
|
||||
((__CONTRAST__) == LCD_CONTRASTLEVEL_2) || \
|
||||
((__CONTRAST__) == LCD_CONTRASTLEVEL_3) || \
|
||||
((__CONTRAST__) == LCD_CONTRASTLEVEL_4) || \
|
||||
((__CONTRAST__) == LCD_CONTRASTLEVEL_5) || \
|
||||
((__CONTRAST__) == LCD_CONTRASTLEVEL_6) || \
|
||||
((__CONTRAST__) == LCD_CONTRASTLEVEL_7))
|
||||
|
||||
#define IS_LCD_RAM_REGISTER(__REGISTER__) (((__REGISTER__) == LCD_RAM_REGISTER0) || \
|
||||
((__REGISTER__) == LCD_RAM_REGISTER1) || \
|
||||
((__REGISTER__) == LCD_RAM_REGISTER2) || \
|
||||
((__REGISTER__) == LCD_RAM_REGISTER3) || \
|
||||
((__REGISTER__) == LCD_RAM_REGISTER4) || \
|
||||
((__REGISTER__) == LCD_RAM_REGISTER5) || \
|
||||
((__REGISTER__) == LCD_RAM_REGISTER6) || \
|
||||
((__REGISTER__) == LCD_RAM_REGISTER7) || \
|
||||
((__REGISTER__) == LCD_RAM_REGISTER8) || \
|
||||
((__REGISTER__) == LCD_RAM_REGISTER9) || \
|
||||
((__REGISTER__) == LCD_RAM_REGISTER10) || \
|
||||
((__REGISTER__) == LCD_RAM_REGISTER11) || \
|
||||
((__REGISTER__) == LCD_RAM_REGISTER12) || \
|
||||
((__REGISTER__) == LCD_RAM_REGISTER13) || \
|
||||
((__REGISTER__) == LCD_RAM_REGISTER14) || \
|
||||
((__REGISTER__) == LCD_RAM_REGISTER15))
|
||||
|
||||
#define IS_LCD_HIGH_DRIVE(__VALUE__) (((__VALUE__) == LCD_HIGHDRIVE_DISABLE) || \
|
||||
((__VALUE__) == LCD_HIGHDRIVE_ENABLE))
|
||||
|
||||
#define IS_LCD_MUX_SEGMENT(__VALUE__) (((__VALUE__) == LCD_MUXSEGMENT_ENABLE) || \
|
||||
((__VALUE__) == LCD_MUXSEGMENT_DISABLE))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/** @addtogroup LCD_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
HAL_StatusTypeDef LCD_WaitForSynchro(LCD_HandleTypeDef *hlcd);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* LCD */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32WBxx_HAL_LCD_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -1,847 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32wbxx_hal_lptim.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of LPTIM HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32WBxx_HAL_LPTIM_H
|
||||
#define STM32WBxx_HAL_LPTIM_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32wbxx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32WBxx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined (LPTIM1) || defined (LPTIM2)
|
||||
|
||||
/** @addtogroup LPTIM
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup LPTIM_Exported_Types LPTIM Exported Types
|
||||
* @{
|
||||
*/
|
||||
#define LPTIM_EXTI_LINE_LPTIM1 EXTI_IMR1_IM29 /*!< External interrupt line 29 Connected to the LPTIM1 EXTI Line */
|
||||
#define LPTIM_EXTI_LINE_LPTIM2 EXTI_IMR1_IM30 /*!< External interrupt line 30 Connected to the LPTIM2 EXTI Line */
|
||||
|
||||
/**
|
||||
* @brief LPTIM Clock configuration definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Source; /*!< Selects the clock source.
|
||||
This parameter can be a value of @ref LPTIM_Clock_Source */
|
||||
|
||||
uint32_t Prescaler; /*!< Specifies the counter clock Prescaler.
|
||||
This parameter can be a value of @ref LPTIM_Clock_Prescaler */
|
||||
|
||||
} LPTIM_ClockConfigTypeDef;
|
||||
|
||||
/**
|
||||
* @brief LPTIM Clock configuration definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Polarity; /*!< Selects the polarity of the active edge for the counter unit
|
||||
if the ULPTIM input is selected.
|
||||
Note: This parameter is used only when Ultra low power clock source is used.
|
||||
Note: If the polarity is configured on 'both edges', an auxiliary clock
|
||||
(one of the Low power oscillator) must be active.
|
||||
This parameter can be a value of @ref LPTIM_Clock_Polarity */
|
||||
|
||||
uint32_t SampleTime; /*!< Selects the clock sampling time to configure the clock glitch filter.
|
||||
Note: This parameter is used only when Ultra low power clock source is used.
|
||||
This parameter can be a value of @ref LPTIM_Clock_Sample_Time */
|
||||
|
||||
} LPTIM_ULPClockConfigTypeDef;
|
||||
|
||||
/**
|
||||
* @brief LPTIM Trigger configuration definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Source; /*!< Selects the Trigger source.
|
||||
This parameter can be a value of @ref LPTIM_Trigger_Source */
|
||||
|
||||
uint32_t ActiveEdge; /*!< Selects the Trigger active edge.
|
||||
Note: This parameter is used only when an external trigger is used.
|
||||
This parameter can be a value of @ref LPTIM_External_Trigger_Polarity */
|
||||
|
||||
uint32_t SampleTime; /*!< Selects the trigger sampling time to configure the clock glitch filter.
|
||||
Note: This parameter is used only when an external trigger is used.
|
||||
This parameter can be a value of @ref LPTIM_Trigger_Sample_Time */
|
||||
} LPTIM_TriggerConfigTypeDef;
|
||||
|
||||
/**
|
||||
* @brief LPTIM Initialization Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
LPTIM_ClockConfigTypeDef Clock; /*!< Specifies the clock parameters */
|
||||
|
||||
LPTIM_ULPClockConfigTypeDef UltraLowPowerClock; /*!< Specifies the Ultra Low Power clock parameters */
|
||||
|
||||
LPTIM_TriggerConfigTypeDef Trigger; /*!< Specifies the Trigger parameters */
|
||||
|
||||
uint32_t OutputPolarity; /*!< Specifies the Output polarity.
|
||||
This parameter can be a value of @ref LPTIM_Output_Polarity */
|
||||
|
||||
uint32_t UpdateMode; /*!< Specifies whether the update of the autoreload and the compare
|
||||
values is done immediately or after the end of current period.
|
||||
This parameter can be a value of @ref LPTIM_Updating_Mode */
|
||||
|
||||
uint32_t CounterSource; /*!< Specifies whether the counter is incremented each internal event
|
||||
or each external event.
|
||||
This parameter can be a value of @ref LPTIM_Counter_Source */
|
||||
|
||||
uint32_t Input1Source; /*!< Specifies source selected for input1 (GPIO or comparator output).
|
||||
This parameter can be a value of @ref LPTIM_Input1_Source */
|
||||
|
||||
uint32_t Input2Source; /*!< Specifies source selected for input2 (GPIO or comparator output).
|
||||
Note: This parameter is used only for encoder feature so is used only
|
||||
for LPTIM1 instance.
|
||||
This parameter can be a value of @ref LPTIM_Input2_Source */
|
||||
} LPTIM_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL LPTIM State structure definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_LPTIM_STATE_RESET = 0x00U, /*!< Peripheral not yet initialized or disabled */
|
||||
HAL_LPTIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
|
||||
HAL_LPTIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */
|
||||
HAL_LPTIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */
|
||||
HAL_LPTIM_STATE_ERROR = 0x04U /*!< Internal Process is ongoing */
|
||||
} HAL_LPTIM_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief LPTIM handle Structure definition
|
||||
*/
|
||||
#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
|
||||
typedef struct __LPTIM_HandleTypeDef
|
||||
#else
|
||||
typedef struct
|
||||
#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
|
||||
{
|
||||
LPTIM_TypeDef *Instance; /*!< Register base address */
|
||||
|
||||
LPTIM_InitTypeDef Init; /*!< LPTIM required parameters */
|
||||
|
||||
HAL_StatusTypeDef Status; /*!< LPTIM peripheral status */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< LPTIM locking object */
|
||||
|
||||
__IO HAL_LPTIM_StateTypeDef State; /*!< LPTIM peripheral state */
|
||||
|
||||
#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
|
||||
void (* MspInitCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< LPTIM Base Msp Init Callback */
|
||||
void (* MspDeInitCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< LPTIM Base Msp DeInit Callback */
|
||||
void (* CompareMatchCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Compare match Callback */
|
||||
void (* AutoReloadMatchCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Auto-reload match Callback */
|
||||
void (* TriggerCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< External trigger event detection Callback */
|
||||
void (* CompareWriteCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Compare register write complete Callback */
|
||||
void (* AutoReloadWriteCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Auto-reload register write complete Callback */
|
||||
void (* DirectionUpCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Up-counting direction change Callback */
|
||||
void (* DirectionDownCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Down-counting direction change Callback */
|
||||
#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
|
||||
} LPTIM_HandleTypeDef;
|
||||
|
||||
#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
|
||||
/**
|
||||
* @brief HAL LPTIM Callback ID enumeration definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_LPTIM_MSPINIT_CB_ID = 0x00U, /*!< LPTIM Base Msp Init Callback ID */
|
||||
HAL_LPTIM_MSPDEINIT_CB_ID = 0x01U, /*!< LPTIM Base Msp DeInit Callback ID */
|
||||
HAL_LPTIM_COMPARE_MATCH_CB_ID = 0x02U, /*!< Compare match Callback ID */
|
||||
HAL_LPTIM_AUTORELOAD_MATCH_CB_ID = 0x03U, /*!< Auto-reload match Callback ID */
|
||||
HAL_LPTIM_TRIGGER_CB_ID = 0x04U, /*!< External trigger event detection Callback ID */
|
||||
HAL_LPTIM_COMPARE_WRITE_CB_ID = 0x05U, /*!< Compare register write complete Callback ID */
|
||||
HAL_LPTIM_AUTORELOAD_WRITE_CB_ID = 0x06U, /*!< Auto-reload register write complete Callback ID */
|
||||
HAL_LPTIM_DIRECTION_UP_CB_ID = 0x07U, /*!< Up-counting direction change Callback ID */
|
||||
HAL_LPTIM_DIRECTION_DOWN_CB_ID = 0x08U, /*!< Down-counting direction change Callback ID */
|
||||
} HAL_LPTIM_CallbackIDTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL TIM Callback pointer definition
|
||||
*/
|
||||
typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< pointer to the LPTIM callback function */
|
||||
|
||||
#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup LPTIM_Exported_Constants LPTIM Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup LPTIM_Clock_Source LPTIM Clock Source
|
||||
* @{
|
||||
*/
|
||||
#define LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC 0x00000000U
|
||||
#define LPTIM_CLOCKSOURCE_ULPTIM LPTIM_CFGR_CKSEL
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LPTIM_Clock_Prescaler LPTIM Clock Prescaler
|
||||
* @{
|
||||
*/
|
||||
#define LPTIM_PRESCALER_DIV1 0x00000000U
|
||||
#define LPTIM_PRESCALER_DIV2 LPTIM_CFGR_PRESC_0
|
||||
#define LPTIM_PRESCALER_DIV4 LPTIM_CFGR_PRESC_1
|
||||
#define LPTIM_PRESCALER_DIV8 (LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_1)
|
||||
#define LPTIM_PRESCALER_DIV16 LPTIM_CFGR_PRESC_2
|
||||
#define LPTIM_PRESCALER_DIV32 (LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_2)
|
||||
#define LPTIM_PRESCALER_DIV64 (LPTIM_CFGR_PRESC_1 | LPTIM_CFGR_PRESC_2)
|
||||
#define LPTIM_PRESCALER_DIV128 LPTIM_CFGR_PRESC
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LPTIM_Output_Polarity LPTIM Output Polarity
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define LPTIM_OUTPUTPOLARITY_HIGH 0x00000000U
|
||||
#define LPTIM_OUTPUTPOLARITY_LOW LPTIM_CFGR_WAVPOL
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LPTIM_Clock_Sample_Time LPTIM Clock Sample Time
|
||||
* @{
|
||||
*/
|
||||
#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION 0x00000000U
|
||||
#define LPTIM_CLOCKSAMPLETIME_2TRANSITIONS LPTIM_CFGR_CKFLT_0
|
||||
#define LPTIM_CLOCKSAMPLETIME_4TRANSITIONS LPTIM_CFGR_CKFLT_1
|
||||
#define LPTIM_CLOCKSAMPLETIME_8TRANSITIONS LPTIM_CFGR_CKFLT
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LPTIM_Clock_Polarity LPTIM Clock Polarity
|
||||
* @{
|
||||
*/
|
||||
#define LPTIM_CLOCKPOLARITY_RISING 0x00000000U
|
||||
#define LPTIM_CLOCKPOLARITY_FALLING LPTIM_CFGR_CKPOL_0
|
||||
#define LPTIM_CLOCKPOLARITY_RISING_FALLING LPTIM_CFGR_CKPOL_1
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LPTIM_Trigger_Source LPTIM Trigger Source
|
||||
* @{
|
||||
*/
|
||||
#define LPTIM_TRIGSOURCE_SOFTWARE 0x0000FFFFU
|
||||
#define LPTIM_TRIGSOURCE_0 0x00000000U
|
||||
#define LPTIM_TRIGSOURCE_1 LPTIM_CFGR_TRIGSEL_0
|
||||
#define LPTIM_TRIGSOURCE_2 LPTIM_CFGR_TRIGSEL_1
|
||||
#define LPTIM_TRIGSOURCE_3 (LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_1)
|
||||
#define LPTIM_TRIGSOURCE_4 LPTIM_CFGR_TRIGSEL_2
|
||||
#define LPTIM_TRIGSOURCE_5 (LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_2)
|
||||
#define LPTIM_TRIGSOURCE_6 (LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_2)
|
||||
#define LPTIM_TRIGSOURCE_7 LPTIM_CFGR_TRIGSEL
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LPTIM_External_Trigger_Polarity LPTIM External Trigger Polarity
|
||||
* @{
|
||||
*/
|
||||
#define LPTIM_ACTIVEEDGE_RISING LPTIM_CFGR_TRIGEN_0
|
||||
#define LPTIM_ACTIVEEDGE_FALLING LPTIM_CFGR_TRIGEN_1
|
||||
#define LPTIM_ACTIVEEDGE_RISING_FALLING LPTIM_CFGR_TRIGEN
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LPTIM_Trigger_Sample_Time LPTIM Trigger Sample Time
|
||||
* @{
|
||||
*/
|
||||
#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION 0x00000000U
|
||||
#define LPTIM_TRIGSAMPLETIME_2TRANSITIONS LPTIM_CFGR_TRGFLT_0
|
||||
#define LPTIM_TRIGSAMPLETIME_4TRANSITIONS LPTIM_CFGR_TRGFLT_1
|
||||
#define LPTIM_TRIGSAMPLETIME_8TRANSITIONS LPTIM_CFGR_TRGFLT
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LPTIM_Updating_Mode LPTIM Updating Mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define LPTIM_UPDATE_IMMEDIATE 0x00000000U
|
||||
#define LPTIM_UPDATE_ENDOFPERIOD LPTIM_CFGR_PRELOAD
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LPTIM_Counter_Source LPTIM Counter Source
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define LPTIM_COUNTERSOURCE_INTERNAL 0x00000000U
|
||||
#define LPTIM_COUNTERSOURCE_EXTERNAL LPTIM_CFGR_COUNTMODE
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LPTIM_Input1_Source LPTIM Input1 Source
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define LPTIM_INPUT1SOURCE_GPIO 0x00000000U /*!< For LPTIM1 and LPTIM2 */
|
||||
#if defined(COMP1)
|
||||
#define LPTIM_INPUT1SOURCE_COMP1 LPTIM_OR_OR_0 /*!< For LPTIM1 and LPTIM2 */
|
||||
#endif
|
||||
#if defined(COMP2)
|
||||
#define LPTIM_INPUT1SOURCE_COMP2 LPTIM_OR_OR_1 /*!< For LPTIM2 */
|
||||
#define LPTIM_INPUT1SOURCE_COMP1_COMP2 LPTIM_OR_OR /*!< For LPTIM2 */
|
||||
#endif
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LPTIM_Input2_Source LPTIM Input2 Source
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define LPTIM_INPUT2SOURCE_GPIO 0x00000000U /*!< For LPTIM1 */
|
||||
#if defined(COMP2)
|
||||
#define LPTIM_INPUT2SOURCE_COMP2 LPTIM_OR_OR_1 /*!< For LPTIM1 */
|
||||
#endif
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LPTIM_Flag_Definition LPTIM Flags Definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define LPTIM_FLAG_DOWN LPTIM_ISR_DOWN
|
||||
#define LPTIM_FLAG_UP LPTIM_ISR_UP
|
||||
#define LPTIM_FLAG_ARROK LPTIM_ISR_ARROK
|
||||
#define LPTIM_FLAG_CMPOK LPTIM_ISR_CMPOK
|
||||
#define LPTIM_FLAG_EXTTRIG LPTIM_ISR_EXTTRIG
|
||||
#define LPTIM_FLAG_ARRM LPTIM_ISR_ARRM
|
||||
#define LPTIM_FLAG_CMPM LPTIM_ISR_CMPM
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LPTIM_Interrupts_Definition LPTIM Interrupts Definition
|
||||
* @{
|
||||
*/
|
||||
#define LPTIM_IT_DOWN LPTIM_IER_DOWNIE
|
||||
#define LPTIM_IT_UP LPTIM_IER_UPIE
|
||||
#define LPTIM_IT_ARROK LPTIM_IER_ARROKIE
|
||||
#define LPTIM_IT_CMPOK LPTIM_IER_CMPOKIE
|
||||
#define LPTIM_IT_EXTTRIG LPTIM_IER_EXTTRIGIE
|
||||
#define LPTIM_IT_ARRM LPTIM_IER_ARRMIE
|
||||
#define LPTIM_IT_CMPM LPTIM_IER_CMPMIE
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/** @defgroup LPTIM_Exported_Macros LPTIM Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset LPTIM handle state.
|
||||
* @param __HANDLE__ LPTIM handle
|
||||
* @retval None
|
||||
*/
|
||||
#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
|
||||
#define __HAL_LPTIM_RESET_HANDLE_STATE(__HANDLE__) do { \
|
||||
(__HANDLE__)->State = HAL_LPTIM_STATE_RESET; \
|
||||
(__HANDLE__)->MspInitCallback = NULL; \
|
||||
(__HANDLE__)->MspDeInitCallback = NULL; \
|
||||
} while(0)
|
||||
#else
|
||||
#define __HAL_LPTIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_LPTIM_STATE_RESET)
|
||||
#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @brief Enable the LPTIM peripheral.
|
||||
* @param __HANDLE__ LPTIM handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_LPTIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (LPTIM_CR_ENABLE))
|
||||
|
||||
/**
|
||||
* @brief Disable the LPTIM peripheral.
|
||||
* @param __HANDLE__ LPTIM handle
|
||||
* @note The following sequence is required to solve LPTIM disable HW limitation.
|
||||
* Please check Errata Sheet ES0335 for more details under "MCU may remain
|
||||
* stuck in LPTIM interrupt when entering Stop mode" section.
|
||||
* @note Please call @ref HAL_LPTIM_GetState() after a call to __HAL_LPTIM_DISABLE to
|
||||
* check for TIMEOUT.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_LPTIM_DISABLE(__HANDLE__) LPTIM_Disable(__HANDLE__)
|
||||
|
||||
/**
|
||||
* @brief Start the LPTIM peripheral in Continuous mode.
|
||||
* @param __HANDLE__ LPTIM handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_LPTIM_START_CONTINUOUS(__HANDLE__) ((__HANDLE__)->Instance->CR |= LPTIM_CR_CNTSTRT)
|
||||
/**
|
||||
* @brief Start the LPTIM peripheral in single mode.
|
||||
* @param __HANDLE__ LPTIM handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_LPTIM_START_SINGLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= LPTIM_CR_SNGSTRT)
|
||||
|
||||
/**
|
||||
* @brief Reset the LPTIM Counter register in synchronous mode.
|
||||
* @param __HANDLE__ LPTIM handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_LPTIM_RESET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CR |= LPTIM_CR_COUNTRST)
|
||||
|
||||
/**
|
||||
* @brief Reset after read of the LPTIM Counter register in asynchronous mode.
|
||||
* @param __HANDLE__ LPTIM handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_LPTIM_RESET_COUNTER_AFTERREAD(__HANDLE__) ((__HANDLE__)->Instance->CR |= LPTIM_CR_RSTARE)
|
||||
|
||||
/**
|
||||
* @brief Write the passed parameter in the Autoreload register.
|
||||
* @param __HANDLE__ LPTIM handle
|
||||
* @param __VALUE__ Autoreload value
|
||||
* @retval None
|
||||
* @note The ARR register can only be modified when the LPTIM instance is enabled.
|
||||
*/
|
||||
#define __HAL_LPTIM_AUTORELOAD_SET(__HANDLE__ , __VALUE__) ((__HANDLE__)->Instance->ARR = (__VALUE__))
|
||||
|
||||
/**
|
||||
* @brief Write the passed parameter in the Compare register.
|
||||
* @param __HANDLE__ LPTIM handle
|
||||
* @param __VALUE__ Compare value
|
||||
* @retval None
|
||||
* @note The CMP register can only be modified when the LPTIM instance is enabled.
|
||||
*/
|
||||
#define __HAL_LPTIM_COMPARE_SET(__HANDLE__ , __VALUE__) ((__HANDLE__)->Instance->CMP = (__VALUE__))
|
||||
|
||||
/**
|
||||
* @brief Check whether the specified LPTIM flag is set or not.
|
||||
* @param __HANDLE__ LPTIM handle
|
||||
* @param __FLAG__ LPTIM flag to check
|
||||
* This parameter can be a value of:
|
||||
* @arg LPTIM_FLAG_DOWN : Counter direction change up Flag.
|
||||
* @arg LPTIM_FLAG_UP : Counter direction change down to up Flag.
|
||||
* @arg LPTIM_FLAG_ARROK : Autoreload register update OK Flag.
|
||||
* @arg LPTIM_FLAG_CMPOK : Compare register update OK Flag.
|
||||
* @arg LPTIM_FLAG_EXTTRIG : External trigger edge event Flag.
|
||||
* @arg LPTIM_FLAG_ARRM : Autoreload match Flag.
|
||||
* @arg LPTIM_FLAG_CMPM : Compare match Flag.
|
||||
* @retval The state of the specified flag (SET or RESET).
|
||||
*/
|
||||
#define __HAL_LPTIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR &(__FLAG__)) == (__FLAG__))
|
||||
|
||||
/**
|
||||
* @brief Clear the specified LPTIM flag.
|
||||
* @param __HANDLE__ LPTIM handle.
|
||||
* @param __FLAG__ LPTIM flag to clear.
|
||||
* This parameter can be a value of:
|
||||
* @arg LPTIM_FLAG_DOWN : Counter direction change up Flag.
|
||||
* @arg LPTIM_FLAG_UP : Counter direction change down to up Flag.
|
||||
* @arg LPTIM_FLAG_ARROK : Autoreload register update OK Flag.
|
||||
* @arg LPTIM_FLAG_CMPOK : Compare register update OK Flag.
|
||||
* @arg LPTIM_FLAG_EXTTRIG : External trigger edge event Flag.
|
||||
* @arg LPTIM_FLAG_ARRM : Autoreload match Flag.
|
||||
* @arg LPTIM_FLAG_CMPM : Compare match Flag.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_LPTIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
|
||||
|
||||
/**
|
||||
* @brief Enable the specified LPTIM interrupt.
|
||||
* @param __HANDLE__ LPTIM handle.
|
||||
* @param __INTERRUPT__ LPTIM interrupt to set.
|
||||
* This parameter can be a value of:
|
||||
* @arg LPTIM_IT_DOWN : Counter direction change up Interrupt.
|
||||
* @arg LPTIM_IT_UP : Counter direction change down to up Interrupt.
|
||||
* @arg LPTIM_IT_ARROK : Autoreload register update OK Interrupt.
|
||||
* @arg LPTIM_IT_CMPOK : Compare register update OK Interrupt.
|
||||
* @arg LPTIM_IT_EXTTRIG : External trigger edge event Interrupt.
|
||||
* @arg LPTIM_IT_ARRM : Autoreload match Interrupt.
|
||||
* @arg LPTIM_IT_CMPM : Compare match Interrupt.
|
||||
* @retval None.
|
||||
* @note The LPTIM interrupts can only be enabled when the LPTIM instance is disabled.
|
||||
*/
|
||||
#define __HAL_LPTIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Disable the specified LPTIM interrupt.
|
||||
* @param __HANDLE__ LPTIM handle.
|
||||
* @param __INTERRUPT__ LPTIM interrupt to set.
|
||||
* This parameter can be a value of:
|
||||
* @arg LPTIM_IT_DOWN : Counter direction change up Interrupt.
|
||||
* @arg LPTIM_IT_UP : Counter direction change down to up Interrupt.
|
||||
* @arg LPTIM_IT_ARROK : Autoreload register update OK Interrupt.
|
||||
* @arg LPTIM_IT_CMPOK : Compare register update OK Interrupt.
|
||||
* @arg LPTIM_IT_EXTTRIG : External trigger edge event Interrupt.
|
||||
* @arg LPTIM_IT_ARRM : Autoreload match Interrupt.
|
||||
* @arg LPTIM_IT_CMPM : Compare match Interrupt.
|
||||
* @retval None.
|
||||
* @note The LPTIM interrupts can only be disabled when the LPTIM instance is disabled.
|
||||
*/
|
||||
#define __HAL_LPTIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))
|
||||
|
||||
/**
|
||||
* @brief Check whether the specified LPTIM interrupt source is enabled or not.
|
||||
* @param __HANDLE__ LPTIM handle.
|
||||
* @param __INTERRUPT__ LPTIM interrupt to check.
|
||||
* This parameter can be a value of:
|
||||
* @arg LPTIM_IT_DOWN : Counter direction change up Interrupt.
|
||||
* @arg LPTIM_IT_UP : Counter direction change down to up Interrupt.
|
||||
* @arg LPTIM_IT_ARROK : Autoreload register update OK Interrupt.
|
||||
* @arg LPTIM_IT_CMPOK : Compare register update OK Interrupt.
|
||||
* @arg LPTIM_IT_EXTTRIG : External trigger edge event Interrupt.
|
||||
* @arg LPTIM_IT_ARRM : Autoreload match Interrupt.
|
||||
* @arg LPTIM_IT_CMPM : Compare match Interrupt.
|
||||
* @retval Interrupt status.
|
||||
*/
|
||||
|
||||
#define __HAL_LPTIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER\
|
||||
& (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
|
||||
|
||||
#define __HAL_LPTIM_LPTIM1_EXTI_ENABLE_IT() (EXTI->IMR1 |= LPTIM_EXTI_LINE_LPTIM1)
|
||||
#define __HAL_LPTIM_LPTIM1_EXTI_DISABLE_IT() (EXTI->IMR1\
|
||||
&= ~(LPTIM_EXTI_LINE_LPTIM1))
|
||||
|
||||
#define __HAL_LPTIM_LPTIM2_EXTI_ENABLE_IT() (EXTI->IMR1 |= LPTIM_EXTI_LINE_LPTIM2)
|
||||
#define __HAL_LPTIM_LPTIM2_EXTI_DISABLE_IT() (EXTI->IMR1\
|
||||
&= ~(LPTIM_EXTI_LINE_LPTIM2))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup LPTIM_Exported_Functions LPTIM Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup LPTIM_Exported_Functions_Group1
|
||||
* @brief Initialization and Configuration functions.
|
||||
* @{
|
||||
*/
|
||||
/* Initialization/de-initialization functions ********************************/
|
||||
HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim);
|
||||
HAL_StatusTypeDef HAL_LPTIM_DeInit(LPTIM_HandleTypeDef *hlptim);
|
||||
|
||||
/* MSP functions *************************************************************/
|
||||
void HAL_LPTIM_MspInit(LPTIM_HandleTypeDef *hlptim);
|
||||
void HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef *hlptim);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup LPTIM_Exported_Functions_Group2
|
||||
* @brief Start-Stop operation functions.
|
||||
* @{
|
||||
*/
|
||||
/* Start/Stop operation functions *********************************************/
|
||||
/* ################################# PWM Mode ################################*/
|
||||
/* Blocking mode: Polling */
|
||||
HAL_StatusTypeDef HAL_LPTIM_PWM_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
|
||||
HAL_StatusTypeDef HAL_LPTIM_PWM_Stop(LPTIM_HandleTypeDef *hlptim);
|
||||
/* Non-Blocking mode: Interrupt */
|
||||
HAL_StatusTypeDef HAL_LPTIM_PWM_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
|
||||
HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_IT(LPTIM_HandleTypeDef *hlptim);
|
||||
|
||||
/* ############################# One Pulse Mode ##############################*/
|
||||
/* Blocking mode: Polling */
|
||||
HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
|
||||
HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop(LPTIM_HandleTypeDef *hlptim);
|
||||
/* Non-Blocking mode: Interrupt */
|
||||
HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
|
||||
HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop_IT(LPTIM_HandleTypeDef *hlptim);
|
||||
|
||||
/* ############################## Set once Mode ##############################*/
|
||||
/* Blocking mode: Polling */
|
||||
HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
|
||||
HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop(LPTIM_HandleTypeDef *hlptim);
|
||||
/* Non-Blocking mode: Interrupt */
|
||||
HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
|
||||
HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop_IT(LPTIM_HandleTypeDef *hlptim);
|
||||
|
||||
/* ############################### Encoder Mode ##############################*/
|
||||
/* Blocking mode: Polling */
|
||||
HAL_StatusTypeDef HAL_LPTIM_Encoder_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period);
|
||||
HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop(LPTIM_HandleTypeDef *hlptim);
|
||||
/* Non-Blocking mode: Interrupt */
|
||||
HAL_StatusTypeDef HAL_LPTIM_Encoder_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period);
|
||||
HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop_IT(LPTIM_HandleTypeDef *hlptim);
|
||||
|
||||
/* ############################# Time out Mode ##############################*/
|
||||
/* Blocking mode: Polling */
|
||||
HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop(LPTIM_HandleTypeDef *hlptim);
|
||||
/* Non-Blocking mode: Interrupt */
|
||||
HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop_IT(LPTIM_HandleTypeDef *hlptim);
|
||||
|
||||
/* ############################## Counter Mode ###############################*/
|
||||
/* Blocking mode: Polling */
|
||||
HAL_StatusTypeDef HAL_LPTIM_Counter_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period);
|
||||
HAL_StatusTypeDef HAL_LPTIM_Counter_Stop(LPTIM_HandleTypeDef *hlptim);
|
||||
/* Non-Blocking mode: Interrupt */
|
||||
HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period);
|
||||
HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup LPTIM_Exported_Functions_Group3
|
||||
* @brief Read operation functions.
|
||||
* @{
|
||||
*/
|
||||
/* Reading operation functions ************************************************/
|
||||
uint32_t HAL_LPTIM_ReadCounter(LPTIM_HandleTypeDef *hlptim);
|
||||
uint32_t HAL_LPTIM_ReadAutoReload(LPTIM_HandleTypeDef *hlptim);
|
||||
uint32_t HAL_LPTIM_ReadCompare(LPTIM_HandleTypeDef *hlptim);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup LPTIM_Exported_Functions_Group4
|
||||
* @brief LPTIM IRQ handler and callback functions.
|
||||
* @{
|
||||
*/
|
||||
/* LPTIM IRQ functions *******************************************************/
|
||||
void HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim);
|
||||
|
||||
/* CallBack functions ********************************************************/
|
||||
void HAL_LPTIM_CompareMatchCallback(LPTIM_HandleTypeDef *hlptim);
|
||||
void HAL_LPTIM_AutoReloadMatchCallback(LPTIM_HandleTypeDef *hlptim);
|
||||
void HAL_LPTIM_TriggerCallback(LPTIM_HandleTypeDef *hlptim);
|
||||
void HAL_LPTIM_CompareWriteCallback(LPTIM_HandleTypeDef *hlptim);
|
||||
void HAL_LPTIM_AutoReloadWriteCallback(LPTIM_HandleTypeDef *hlptim);
|
||||
void HAL_LPTIM_DirectionUpCallback(LPTIM_HandleTypeDef *hlptim);
|
||||
void HAL_LPTIM_DirectionDownCallback(LPTIM_HandleTypeDef *hlptim);
|
||||
|
||||
/* Callbacks Register/UnRegister functions ***********************************/
|
||||
#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
|
||||
HAL_StatusTypeDef HAL_LPTIM_RegisterCallback(LPTIM_HandleTypeDef *hlptim,
|
||||
HAL_LPTIM_CallbackIDTypeDef CallbackID,
|
||||
pLPTIM_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *hlptim,
|
||||
HAL_LPTIM_CallbackIDTypeDef CallbackID);
|
||||
#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup LPTIM_Group5
|
||||
* @brief Peripheral State functions.
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral State functions ************************************************/
|
||||
HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/** @defgroup LPTIM_Private_Types LPTIM Private Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/** @defgroup LPTIM_Private_Variables LPTIM Private Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup LPTIM_Private_Constants LPTIM Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup LPTIM_Private_Macros LPTIM Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_LPTIM_CLOCK_SOURCE(__SOURCE__) (((__SOURCE__) == LPTIM_CLOCKSOURCE_ULPTIM) || \
|
||||
((__SOURCE__) == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC))
|
||||
|
||||
|
||||
#define IS_LPTIM_CLOCK_PRESCALER(__PRESCALER__) (((__PRESCALER__) == LPTIM_PRESCALER_DIV1 ) || \
|
||||
((__PRESCALER__) == LPTIM_PRESCALER_DIV2 ) || \
|
||||
((__PRESCALER__) == LPTIM_PRESCALER_DIV4 ) || \
|
||||
((__PRESCALER__) == LPTIM_PRESCALER_DIV8 ) || \
|
||||
((__PRESCALER__) == LPTIM_PRESCALER_DIV16 ) || \
|
||||
((__PRESCALER__) == LPTIM_PRESCALER_DIV32 ) || \
|
||||
((__PRESCALER__) == LPTIM_PRESCALER_DIV64 ) || \
|
||||
((__PRESCALER__) == LPTIM_PRESCALER_DIV128))
|
||||
|
||||
#define IS_LPTIM_CLOCK_PRESCALERDIV1(__PRESCALER__) ((__PRESCALER__) == LPTIM_PRESCALER_DIV1)
|
||||
|
||||
#define IS_LPTIM_OUTPUT_POLARITY(__POLARITY__) (((__POLARITY__) == LPTIM_OUTPUTPOLARITY_LOW ) || \
|
||||
((__POLARITY__) == LPTIM_OUTPUTPOLARITY_HIGH))
|
||||
|
||||
#define IS_LPTIM_CLOCK_SAMPLE_TIME(__SAMPLETIME__) (((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION) || \
|
||||
((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_2TRANSITIONS) || \
|
||||
((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_4TRANSITIONS) || \
|
||||
((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_8TRANSITIONS))
|
||||
|
||||
#define IS_LPTIM_CLOCK_POLARITY(__POLARITY__) (((__POLARITY__) == LPTIM_CLOCKPOLARITY_RISING) || \
|
||||
((__POLARITY__) == LPTIM_CLOCKPOLARITY_FALLING) || \
|
||||
((__POLARITY__) == LPTIM_CLOCKPOLARITY_RISING_FALLING))
|
||||
|
||||
#define IS_LPTIM_TRG_SOURCE(__TRIG__) (((__TRIG__) == LPTIM_TRIGSOURCE_SOFTWARE) || \
|
||||
((__TRIG__) == LPTIM_TRIGSOURCE_0) || \
|
||||
((__TRIG__) == LPTIM_TRIGSOURCE_1) || \
|
||||
((__TRIG__) == LPTIM_TRIGSOURCE_2) || \
|
||||
((__TRIG__) == LPTIM_TRIGSOURCE_3) || \
|
||||
((__TRIG__) == LPTIM_TRIGSOURCE_4) || \
|
||||
((__TRIG__) == LPTIM_TRIGSOURCE_5) || \
|
||||
((__TRIG__) == LPTIM_TRIGSOURCE_6) || \
|
||||
((__TRIG__) == LPTIM_TRIGSOURCE_7))
|
||||
|
||||
#define IS_LPTIM_EXT_TRG_POLARITY(__POLARITY__) (((__POLARITY__) == LPTIM_ACTIVEEDGE_RISING ) || \
|
||||
((__POLARITY__) == LPTIM_ACTIVEEDGE_FALLING ) || \
|
||||
((__POLARITY__) == LPTIM_ACTIVEEDGE_RISING_FALLING ))
|
||||
|
||||
#define IS_LPTIM_TRIG_SAMPLE_TIME(__SAMPLETIME__) (((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION) || \
|
||||
((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_2TRANSITIONS ) || \
|
||||
((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_4TRANSITIONS ) || \
|
||||
((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_8TRANSITIONS ))
|
||||
|
||||
#define IS_LPTIM_UPDATE_MODE(__MODE__) (((__MODE__) == LPTIM_UPDATE_IMMEDIATE) || \
|
||||
((__MODE__) == LPTIM_UPDATE_ENDOFPERIOD))
|
||||
|
||||
#define IS_LPTIM_COUNTER_SOURCE(__SOURCE__) (((__SOURCE__) == LPTIM_COUNTERSOURCE_INTERNAL) || \
|
||||
((__SOURCE__) == LPTIM_COUNTERSOURCE_EXTERNAL))
|
||||
|
||||
#define IS_LPTIM_AUTORELOAD(__AUTORELOAD__) ((__AUTORELOAD__) <= 0x0000FFFFUL)
|
||||
|
||||
#define IS_LPTIM_COMPARE(__COMPARE__) ((__COMPARE__) <= 0x0000FFFFUL)
|
||||
|
||||
#define IS_LPTIM_PERIOD(__PERIOD__) ((__PERIOD__) <= 0x0000FFFFUL)
|
||||
|
||||
#define IS_LPTIM_PULSE(__PULSE__) ((__PULSE__) <= 0x0000FFFFUL)
|
||||
|
||||
#if defined(COMP1)
|
||||
#if defined(COMP2)
|
||||
#define IS_LPTIM_INPUT1_SOURCE(__INSTANCE__, __SOURCE__) \
|
||||
((((__INSTANCE__) == LPTIM1) && \
|
||||
(((__SOURCE__) == LPTIM_INPUT1SOURCE_GPIO) || \
|
||||
((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1))) \
|
||||
|| \
|
||||
(((__INSTANCE__) == LPTIM2) && \
|
||||
(((__SOURCE__) == LPTIM_INPUT1SOURCE_GPIO) || \
|
||||
((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1) || \
|
||||
((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP2) || \
|
||||
((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1_COMP2))))
|
||||
#else
|
||||
#define IS_LPTIM_INPUT1_SOURCE(__INSTANCE__, __SOURCE__) \
|
||||
((((__INSTANCE__) == LPTIM1) && \
|
||||
(((__SOURCE__) == LPTIM_INPUT1SOURCE_GPIO) || \
|
||||
((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1))) \
|
||||
|| \
|
||||
(((__INSTANCE__) == LPTIM2) && \
|
||||
(((__SOURCE__) == LPTIM_INPUT1SOURCE_GPIO) || \
|
||||
((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1))))
|
||||
#endif
|
||||
#else
|
||||
#define IS_LPTIM_INPUT1_SOURCE(__INSTANCE__, __SOURCE__) \
|
||||
((((__INSTANCE__) == LPTIM1) && \
|
||||
((__SOURCE__) == LPTIM_INPUT1SOURCE_GPIO) ) \
|
||||
|| \
|
||||
(((__INSTANCE__) == LPTIM2) && \
|
||||
((__SOURCE__) == LPTIM_INPUT1SOURCE_GPIO)))
|
||||
#endif
|
||||
|
||||
#if defined(COMP2)
|
||||
#define IS_LPTIM_INPUT2_SOURCE(__INSTANCE__, __SOURCE__) \
|
||||
(((__INSTANCE__) == LPTIM1) && \
|
||||
(((__SOURCE__) == LPTIM_INPUT2SOURCE_GPIO) || \
|
||||
((__SOURCE__) == LPTIM_INPUT2SOURCE_COMP2)))
|
||||
#else
|
||||
#define IS_LPTIM_INPUT2_SOURCE(__INSTANCE__, __SOURCE__) \
|
||||
(((__INSTANCE__) == LPTIM1) && \
|
||||
(((__SOURCE__) == LPTIM_INPUT2SOURCE_GPIO)))
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/** @defgroup LPTIM_Private_Functions LPTIM Private Functions
|
||||
* @{
|
||||
*/
|
||||
void LPTIM_Disable(LPTIM_HandleTypeDef *hlptim);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* LPTIM1 || LPTIM2 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32WBxx_HAL_LPTIM_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,91 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32wbxx_hal_pcd_ex.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of PCD HAL Extension module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32WBxx_HAL_PCD_EX_H
|
||||
#define STM32WBxx_HAL_PCD_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32wbxx_hal_def.h"
|
||||
|
||||
#if defined (USB)
|
||||
/** @addtogroup STM32WBxx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup PCDEx
|
||||
* @{
|
||||
*/
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup PCDEx_Exported_Functions PCDEx Exported Functions
|
||||
* @{
|
||||
*/
|
||||
/** @addtogroup PCDEx_Exported_Functions_Group1 Peripheral Control functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
|
||||
HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, uint16_t ep_addr,
|
||||
uint16_t ep_kind, uint32_t pmaadress);
|
||||
|
||||
|
||||
HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd);
|
||||
HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd);
|
||||
|
||||
|
||||
HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd);
|
||||
HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd);
|
||||
void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd);
|
||||
|
||||
void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg);
|
||||
void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* defined (USB) */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* STM32WBxx_HAL_PCD_EX_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -1,567 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32wbxx_hal_pka.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of PKA HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32WBxx_HAL_PKA_H
|
||||
#define STM32WBxx_HAL_PKA_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32wbxx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32WBxx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined(PKA) && defined(HAL_PKA_MODULE_ENABLED)
|
||||
|
||||
/** @addtogroup PKA
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup PKA_Exported_Types PKA Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_state_structure_definition HAL state structure definition
|
||||
* @brief HAL State structures definition
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_PKA_STATE_RESET = 0x00U, /*!< PKA not yet initialized or disabled */
|
||||
HAL_PKA_STATE_READY = 0x01U, /*!< PKA initialized and ready for use */
|
||||
HAL_PKA_STATE_BUSY = 0x02U, /*!< PKA internal processing is ongoing */
|
||||
HAL_PKA_STATE_ERROR = 0x03U, /*!< PKA error state */
|
||||
}
|
||||
HAL_PKA_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if (USE_HAL_PKA_REGISTER_CALLBACKS == 1)
|
||||
/** @defgroup HAL_callback_id HAL callback ID enumeration
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_PKA_OPERATION_COMPLETE_CB_ID = 0x00U, /*!< PKA End of operation callback ID */
|
||||
HAL_PKA_ERROR_CB_ID = 0x01U, /*!< PKA Error callback ID */
|
||||
HAL_PKA_MSPINIT_CB_ID = 0x02U, /*!< PKA Msp Init callback ID */
|
||||
HAL_PKA_MSPDEINIT_CB_ID = 0x03U /*!< PKA Msp DeInit callback ID */
|
||||
} HAL_PKA_CallbackIDTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* USE_HAL_PKA_REGISTER_CALLBACKS */
|
||||
|
||||
/** @defgroup PKA_Error_Code_definition PKA Error Code definition
|
||||
* @brief PKA Error Code definition
|
||||
* @{
|
||||
*/
|
||||
#define HAL_PKA_ERROR_NONE (0x00000000U)
|
||||
#define HAL_PKA_ERROR_ADDRERR (0x00000001U)
|
||||
#define HAL_PKA_ERROR_RAMERR (0x00000002U)
|
||||
#define HAL_PKA_ERROR_TIMEOUT (0x00000004U)
|
||||
#define HAL_PKA_ERROR_OPERATION (0x00000008U)
|
||||
#if (USE_HAL_PKA_REGISTER_CALLBACKS == 1)
|
||||
#define HAL_PKA_ERROR_INVALID_CALLBACK (0x00000010U) /*!< Invalid Callback error */
|
||||
#endif /* USE_HAL_PKA_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PKA_handle_Structure_definition PKA handle Structure definition
|
||||
* @brief PKA handle Structure definition
|
||||
* @{
|
||||
*/
|
||||
#if (USE_HAL_PKA_REGISTER_CALLBACKS == 1)
|
||||
typedef struct __PKA_HandleTypeDef
|
||||
#else
|
||||
typedef struct
|
||||
#endif /* USE_HAL_PKA_REGISTER_CALLBACKS */
|
||||
{
|
||||
PKA_TypeDef *Instance; /*!< Register base address */
|
||||
__IO HAL_PKA_StateTypeDef State; /*!< PKA state */
|
||||
__IO uint32_t ErrorCode; /*!< PKA Error code */
|
||||
#if (USE_HAL_PKA_REGISTER_CALLBACKS == 1)
|
||||
void (* OperationCpltCallback)(struct __PKA_HandleTypeDef *hpka); /*!< PKA End of operation callback */
|
||||
void (* ErrorCallback)(struct __PKA_HandleTypeDef *hpka); /*!< PKA Error callback */
|
||||
void (* MspInitCallback)(struct __PKA_HandleTypeDef *hpka); /*!< PKA Msp Init callback */
|
||||
void (* MspDeInitCallback)(struct __PKA_HandleTypeDef *hpka); /*!< PKA Msp DeInit callback */
|
||||
#endif /* USE_HAL_PKA_REGISTER_CALLBACKS */
|
||||
} PKA_HandleTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if (USE_HAL_PKA_REGISTER_CALLBACKS == 1)
|
||||
/** @defgroup PKA_Callback_definition PKA Callback pointer definition
|
||||
* @brief PKA Callback pointer definition
|
||||
* @{
|
||||
*/
|
||||
typedef void (*pPKA_CallbackTypeDef)(PKA_HandleTypeDef *hpka); /*!< Pointer to a PKA callback function */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* USE_HAL_PKA_REGISTER_CALLBACKS */
|
||||
/** @defgroup PKA_Operation PKA operation structure definition
|
||||
* @brief Input and output data definition
|
||||
* @{
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t scalarMulSize; /*!< Number of element in scalarMul array */
|
||||
uint32_t modulusSize; /*!< Number of element in modulus, coefA, pointX and pointY arrays */
|
||||
uint32_t coefSign; /*!< Curve coefficient a sign */
|
||||
const uint8_t *coefA; /*!< Pointer to curve coefficient |a| (Array of modulusSize elements) */
|
||||
const uint8_t *modulus; /*!< Pointer to curve modulus value p (Array of modulusSize elements) */
|
||||
const uint8_t *pointX; /*!< Pointer to point P coordinate xP (Array of modulusSize elements) */
|
||||
const uint8_t *pointY; /*!< Pointer to point P coordinate yP (Array of modulusSize elements) */
|
||||
const uint8_t *scalarMul; /*!< Pointer to scalar multiplier k (Array of scalarMulSize elements) */
|
||||
const uint32_t *pMontgomeryParam; /*!< Pointer to Montgomery parameter (Array of modulusSize/4 elements) */
|
||||
} PKA_ECCMulFastModeInTypeDef;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t scalarMulSize; /*!< Number of element in scalarMul array */
|
||||
uint32_t modulusSize; /*!< Number of element in modulus, coefA, pointX and pointY arrays */
|
||||
uint32_t coefSign; /*!< Curve coefficient a sign */
|
||||
const uint8_t *coefA; /*!< Pointer to curve coefficient |a| (Array of modulusSize elements) */
|
||||
const uint8_t *modulus; /*!< Pointer to curve modulus value p (Array of modulusSize elements) */
|
||||
const uint8_t *pointX; /*!< Pointer to point P coordinate xP (Array of modulusSize elements) */
|
||||
const uint8_t *pointY; /*!< Pointer to point P coordinate yP (Array of modulusSize elements) */
|
||||
const uint8_t *scalarMul; /*!< Pointer to scalar multiplier k (Array of scalarMulSize elements) */
|
||||
} PKA_ECCMulInTypeDef;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t modulusSize; /*!< Number of element in coefA, coefB, modulus, pointX and pointY arrays */
|
||||
uint32_t coefSign; /*!< Curve coefficient a sign */
|
||||
const uint8_t *coefA; /*!< Pointer to curve coefficient |a| (Array of modulusSize elements) */
|
||||
const uint8_t *coefB; /*!< Pointer to curve coefficient b (Array of modulusSize elements) */
|
||||
const uint8_t *modulus; /*!< Pointer to curve modulus value p (Array of modulusSize elements) */
|
||||
const uint8_t *pointX; /*!< Pointer to point P coordinate xP (Array of modulusSize elements) */
|
||||
const uint8_t *pointY; /*!< Pointer to point P coordinate yP (Array of modulusSize elements) */
|
||||
} PKA_PointCheckInTypeDef;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t size; /*!< Number of element in popA array */
|
||||
const uint8_t *pOpDp; /*!< Pointer to operand dP (Array of size/2 elements) */
|
||||
const uint8_t *pOpDq; /*!< Pointer to operand dQ (Array of size/2 elements) */
|
||||
const uint8_t *pOpQinv; /*!< Pointer to operand qinv (Array of size/2 elements) */
|
||||
const uint8_t *pPrimeP; /*!< Pointer to prime p (Array of size/2 elements) */
|
||||
const uint8_t *pPrimeQ; /*!< Pointer to prime Q (Array of size/2 elements) */
|
||||
const uint8_t *popA; /*!< Pointer to operand A (Array of size elements) */
|
||||
} PKA_RSACRTExpInTypeDef;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t primeOrderSize; /*!< Number of element in primeOrder array */
|
||||
uint32_t modulusSize; /*!< Number of element in modulus array */
|
||||
uint32_t coefSign; /*!< Curve coefficient a sign */
|
||||
const uint8_t *coef; /*!< Pointer to curve coefficient |a| (Array of modulusSize elements) */
|
||||
const uint8_t *modulus; /*!< Pointer to curve modulus value p (Array of modulusSize elements) */
|
||||
const uint8_t *basePointX; /*!< Pointer to curve base point xG (Array of modulusSize elements) */
|
||||
const uint8_t *basePointY; /*!< Pointer to curve base point yG (Array of modulusSize elements) */
|
||||
const uint8_t *pPubKeyCurvePtX; /*!< Pointer to public-key curve point xQ (Array of modulusSize elements) */
|
||||
const uint8_t *pPubKeyCurvePtY; /*!< Pointer to public-key curve point yQ (Array of modulusSize elements) */
|
||||
const uint8_t *RSign; /*!< Pointer to signature part r (Array of primeOrderSize elements) */
|
||||
const uint8_t *SSign; /*!< Pointer to signature part s (Array of primeOrderSize elements) */
|
||||
const uint8_t *hash; /*!< Pointer to hash of the message e (Array of primeOrderSize elements) */
|
||||
const uint8_t *primeOrder; /*!< Pointer to order of the curve n (Array of primeOrderSize elements) */
|
||||
} PKA_ECDSAVerifInTypeDef;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t primeOrderSize; /*!< Number of element in primeOrder array */
|
||||
uint32_t modulusSize; /*!< Number of element in modulus array */
|
||||
uint32_t coefSign; /*!< Curve coefficient a sign */
|
||||
const uint8_t *coef; /*!< Pointer to curve coefficient |a| (Array of modulusSize elements) */
|
||||
const uint8_t *modulus; /*!< Pointer to curve modulus value p (Array of modulusSize elements) */
|
||||
const uint8_t *integer; /*!< Pointer to random integer k (Array of primeOrderSize elements) */
|
||||
const uint8_t *basePointX; /*!< Pointer to curve base point xG (Array of modulusSize elements) */
|
||||
const uint8_t *basePointY; /*!< Pointer to curve base point yG (Array of modulusSize elements) */
|
||||
const uint8_t *hash; /*!< Pointer to hash of the message (Array of primeOrderSize elements) */
|
||||
const uint8_t *privateKey; /*!< Pointer to private key d (Array of primeOrderSize elements) */
|
||||
const uint8_t *primeOrder; /*!< Pointer to order of the curve n (Array of primeOrderSize elements) */
|
||||
} PKA_ECDSASignInTypeDef;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint8_t *RSign; /*!< Pointer to signature part r (Array of modulusSize elements) */
|
||||
uint8_t *SSign; /*!< Pointer to signature part s (Array of modulusSize elements) */
|
||||
} PKA_ECDSASignOutTypeDef;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint8_t *ptX; /*!< Pointer to point P coordinate xP (Array of modulusSize elements) */
|
||||
uint8_t *ptY; /*!< Pointer to point P coordinate yP (Array of modulusSize elements) */
|
||||
} PKA_ECDSASignOutExtParamTypeDef, PKA_ECCMulOutTypeDef;
|
||||
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t expSize; /*!< Number of element in pExp array */
|
||||
uint32_t OpSize; /*!< Number of element in pOp1 and pMod arrays */
|
||||
const uint8_t *pExp; /*!< Pointer to Exponent (Array of expSize elements) */
|
||||
const uint8_t *pOp1; /*!< Pointer to Operand (Array of OpSize elements) */
|
||||
const uint8_t *pMod; /*!< Pointer to modulus (Array of OpSize elements) */
|
||||
} PKA_ModExpInTypeDef;
|
||||
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t expSize; /*!< Number of element in pExp and pMontgomeryParam arrays */
|
||||
uint32_t OpSize; /*!< Number of element in pOp1 and pMod arrays */
|
||||
const uint8_t *pExp; /*!< Pointer to Exponent (Array of expSize elements) */
|
||||
const uint8_t *pOp1; /*!< Pointer to Operand (Array of OpSize elements) */
|
||||
const uint8_t *pMod; /*!< Pointer to modulus (Array of OpSize elements) */
|
||||
const uint32_t *pMontgomeryParam; /*!< Pointer to Montgomery parameter (Array of expSize/4 elements) */
|
||||
} PKA_ModExpFastModeInTypeDef;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t size; /*!< Number of element in pOp1 array */
|
||||
const uint8_t *pOp1; /*!< Pointer to Operand (Array of size elements) */
|
||||
} PKA_MontgomeryParamInTypeDef;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t size; /*!< Number of element in pOp1 and pOp2 arrays */
|
||||
const uint32_t *pOp1; /*!< Pointer to Operand 1 (Array of size elements) */
|
||||
const uint32_t *pOp2; /*!< Pointer to Operand 2 (Array of size elements) */
|
||||
} PKA_AddInTypeDef, PKA_SubInTypeDef, PKA_MulInTypeDef, PKA_CmpInTypeDef;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t size; /*!< Number of element in pOp1 array */
|
||||
const uint32_t *pOp1; /*!< Pointer to Operand 1 (Array of size elements) */
|
||||
const uint8_t *pMod; /*!< Pointer to modulus value n (Array of size*4 elements) */
|
||||
} PKA_ModInvInTypeDef;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t OpSize; /*!< Number of element in pOp1 array */
|
||||
uint32_t modSize; /*!< Number of element in pMod array */
|
||||
const uint32_t *pOp1; /*!< Pointer to Operand 1 (Array of OpSize elements) */
|
||||
const uint8_t *pMod; /*!< Pointer to modulus value n (Array of modSize elements) */
|
||||
} PKA_ModRedInTypeDef;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t size; /*!< Number of element in pOp1 and pOp2 arrays */
|
||||
const uint32_t *pOp1; /*!< Pointer to Operand 1 (Array of size elements) */
|
||||
const uint32_t *pOp2; /*!< Pointer to Operand 2 (Array of size elements) */
|
||||
const uint8_t *pOp3; /*!< Pointer to Operand 3 (Array of size*4 elements) */
|
||||
} PKA_ModAddInTypeDef, PKA_ModSubInTypeDef, PKA_MontgomeryMulInTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup PKA_Exported_Constants PKA Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup PKA_Mode PKA mode
|
||||
* @{
|
||||
*/
|
||||
#define PKA_MODE_MONTGOMERY_PARAM (0x00000001U)
|
||||
#define PKA_MODE_MODULAR_EXP (0x00000000U)
|
||||
#define PKA_MODE_MODULAR_EXP_FAST_MODE (0x00000002U)
|
||||
#define PKA_MODE_ECC_MUL (0x00000020U)
|
||||
#define PKA_MODE_ECC_MUL_FAST_MODE (0x00000022U)
|
||||
#define PKA_MODE_ECDSA_SIGNATURE (0x00000024U)
|
||||
#define PKA_MODE_ECDSA_VERIFICATION (0x00000026U)
|
||||
#define PKA_MODE_POINT_CHECK (0x00000028U)
|
||||
#define PKA_MODE_RSA_CRT_EXP (0x00000007U)
|
||||
#define PKA_MODE_MODULAR_INV (0x00000008U)
|
||||
#define PKA_MODE_ARITHMETIC_ADD (0x00000009U)
|
||||
#define PKA_MODE_ARITHMETIC_SUB (0x0000000AU)
|
||||
#define PKA_MODE_ARITHMETIC_MUL (0x0000000BU)
|
||||
#define PKA_MODE_COMPARISON (0x0000000CU)
|
||||
#define PKA_MODE_MODULAR_RED (0x0000000DU)
|
||||
#define PKA_MODE_MODULAR_ADD (0x0000000EU)
|
||||
#define PKA_MODE_MODULAR_SUB (0x0000000FU)
|
||||
#define PKA_MODE_MONTGOMERY_MUL (0x00000010U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PKA_Interrupt_configuration_definition PKA Interrupt configuration definition
|
||||
* @brief PKA Interrupt definition
|
||||
* @{
|
||||
*/
|
||||
#define PKA_IT_PROCEND PKA_CR_PROCENDIE
|
||||
#define PKA_IT_ADDRERR PKA_CR_ADDRERRIE
|
||||
#define PKA_IT_RAMERR PKA_CR_RAMERRIE
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PKA_Flag_definition PKA Flag definition
|
||||
* @{
|
||||
*/
|
||||
#define PKA_FLAG_PROCEND PKA_SR_PROCENDF
|
||||
#define PKA_FLAG_ADDRERR PKA_SR_ADDRERRF
|
||||
#define PKA_FLAG_RAMERR PKA_SR_RAMERRF
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
|
||||
/** @defgroup PKA_Exported_Macros PKA Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset PKA handle state.
|
||||
* @param __HANDLE__ specifies the PKA Handle
|
||||
* @retval None
|
||||
*/
|
||||
#if (USE_HAL_PKA_REGISTER_CALLBACKS == 1)
|
||||
#define __HAL_PKA_RESET_HANDLE_STATE(__HANDLE__) do{ \
|
||||
(__HANDLE__)->State = HAL_PKA_STATE_RESET; \
|
||||
(__HANDLE__)->MspInitCallback = NULL; \
|
||||
(__HANDLE__)->MspDeInitCallback = NULL; \
|
||||
} while(0)
|
||||
#else
|
||||
#define __HAL_PKA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_PKA_STATE_RESET)
|
||||
#endif
|
||||
|
||||
/** @brief Enable the specified PKA interrupt.
|
||||
* @param __HANDLE__ specifies the PKA Handle
|
||||
* @param __INTERRUPT__ specifies the interrupt source to enable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref PKA_IT_PROCEND End Of Operation interrupt enable
|
||||
* @arg @ref PKA_IT_ADDRERR Address error interrupt enable
|
||||
* @arg @ref PKA_IT_RAMERR RAM error interrupt enable
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PKA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
|
||||
|
||||
/** @brief Disable the specified PKA interrupt.
|
||||
* @param __HANDLE__ specifies the PKA Handle
|
||||
* @param __INTERRUPT__ specifies the interrupt source to disable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref PKA_IT_PROCEND End Of Operation interrupt enable
|
||||
* @arg @ref PKA_IT_ADDRERR Address error interrupt enable
|
||||
* @arg @ref PKA_IT_RAMERR RAM error interrupt enable
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PKA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= (~(__INTERRUPT__)))
|
||||
|
||||
/** @brief Check whether the specified PKA interrupt source is enabled or not.
|
||||
* @param __HANDLE__ specifies the PKA Handle
|
||||
* @param __INTERRUPT__ specifies the PKA interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref PKA_IT_PROCEND End Of Operation interrupt enable
|
||||
* @arg @ref PKA_IT_ADDRERR Address error interrupt enable
|
||||
* @arg @ref PKA_IT_RAMERR RAM error interrupt enable
|
||||
* @retval The new state of __INTERRUPT__ (SET or RESET)
|
||||
*/
|
||||
#define __HAL_PKA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
|
||||
|
||||
/** @brief Check whether the specified PKA flag is set or not.
|
||||
* @param __HANDLE__ specifies the PKA Handle
|
||||
* @param __FLAG__ specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref PKA_FLAG_PROCEND End Of Operation
|
||||
* @arg @ref PKA_FLAG_ADDRERR Address error
|
||||
* @arg @ref PKA_FLAG_RAMERR RAM error
|
||||
* @retval The new state of __FLAG__ (SET or RESET)
|
||||
*/
|
||||
#define __HAL_PKA_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) ? SET : RESET)
|
||||
|
||||
/** @brief Clear the PKA pending flags which are cleared by writing 1 in a specific bit.
|
||||
* @param __HANDLE__ specifies the PKA Handle
|
||||
* @param __FLAG__ specifies the flag to clear.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg @ref PKA_FLAG_PROCEND End Of Operation
|
||||
* @arg @ref PKA_FLAG_ADDRERR Address error
|
||||
* @arg @ref PKA_FLAG_RAMERR RAM error
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PKA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CLRFR = (__FLAG__))
|
||||
|
||||
/** @brief Enable the specified PKA peripheral.
|
||||
* @param __HANDLE__ specifies the PKA Handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PKA_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR, PKA_CR_EN))
|
||||
|
||||
/** @brief Disable the specified PKA peripheral.
|
||||
* @param __HANDLE__ specifies the PKA Handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PKA_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR, PKA_CR_EN))
|
||||
|
||||
/** @brief Start a PKA operation.
|
||||
* @param __HANDLE__ specifies the PKA Handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PKA_START(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR, PKA_CR_START))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros --------------------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup PKA_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup PKA_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
/* Initialization and de-initialization functions *****************************/
|
||||
HAL_StatusTypeDef HAL_PKA_Init(PKA_HandleTypeDef *hpka);
|
||||
HAL_StatusTypeDef HAL_PKA_DeInit(PKA_HandleTypeDef *hpka);
|
||||
void HAL_PKA_MspInit(PKA_HandleTypeDef *hpka);
|
||||
void HAL_PKA_MspDeInit(PKA_HandleTypeDef *hpka);
|
||||
|
||||
#if (USE_HAL_PKA_REGISTER_CALLBACKS == 1)
|
||||
/* Callbacks Register/UnRegister functions ***********************************/
|
||||
HAL_StatusTypeDef HAL_PKA_RegisterCallback(PKA_HandleTypeDef *hpka, HAL_PKA_CallbackIDTypeDef CallbackID, pPKA_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_PKA_UnRegisterCallback(PKA_HandleTypeDef *hpka, HAL_PKA_CallbackIDTypeDef CallbackID);
|
||||
#endif /* USE_HAL_PKA_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup PKA_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
/* IO operation functions *****************************************************/
|
||||
/* High Level Functions *******************************************************/
|
||||
HAL_StatusTypeDef HAL_PKA_ModExp(PKA_HandleTypeDef *hpka, PKA_ModExpInTypeDef *in, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_PKA_ModExp_IT(PKA_HandleTypeDef *hpka, PKA_ModExpInTypeDef *in);
|
||||
HAL_StatusTypeDef HAL_PKA_ModExpFastMode(PKA_HandleTypeDef *hpka, PKA_ModExpFastModeInTypeDef *in, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_PKA_ModExpFastMode_IT(PKA_HandleTypeDef *hpka, PKA_ModExpFastModeInTypeDef *in);
|
||||
void HAL_PKA_ModExp_GetResult(PKA_HandleTypeDef *hpka, uint8_t *pRes);
|
||||
|
||||
HAL_StatusTypeDef HAL_PKA_ECDSASign(PKA_HandleTypeDef *hpka, PKA_ECDSASignInTypeDef *in, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_PKA_ECDSASign_IT(PKA_HandleTypeDef *hpka, PKA_ECDSASignInTypeDef *in);
|
||||
void HAL_PKA_ECDSASign_GetResult(PKA_HandleTypeDef *hpka, PKA_ECDSASignOutTypeDef *out, PKA_ECDSASignOutExtParamTypeDef *outExt);
|
||||
|
||||
HAL_StatusTypeDef HAL_PKA_ECDSAVerif(PKA_HandleTypeDef *hpka, PKA_ECDSAVerifInTypeDef *in, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_PKA_ECDSAVerif_IT(PKA_HandleTypeDef *hpka, PKA_ECDSAVerifInTypeDef *in);
|
||||
uint32_t HAL_PKA_ECDSAVerif_IsValidSignature(PKA_HandleTypeDef const *const hpka);
|
||||
|
||||
HAL_StatusTypeDef HAL_PKA_RSACRTExp(PKA_HandleTypeDef *hpka, PKA_RSACRTExpInTypeDef *in, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_PKA_RSACRTExp_IT(PKA_HandleTypeDef *hpka, PKA_RSACRTExpInTypeDef *in);
|
||||
void HAL_PKA_RSACRTExp_GetResult(PKA_HandleTypeDef *hpka, uint8_t *pRes);
|
||||
|
||||
HAL_StatusTypeDef HAL_PKA_PointCheck(PKA_HandleTypeDef *hpka, PKA_PointCheckInTypeDef *in, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_PKA_PointCheck_IT(PKA_HandleTypeDef *hpka, PKA_PointCheckInTypeDef *in);
|
||||
uint32_t HAL_PKA_PointCheck_IsOnCurve(PKA_HandleTypeDef const *const hpka);
|
||||
|
||||
HAL_StatusTypeDef HAL_PKA_ECCMul(PKA_HandleTypeDef *hpka, PKA_ECCMulInTypeDef *in, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_PKA_ECCMul_IT(PKA_HandleTypeDef *hpka, PKA_ECCMulInTypeDef *in);
|
||||
HAL_StatusTypeDef HAL_PKA_ECCMulFastMode(PKA_HandleTypeDef *hpka, PKA_ECCMulFastModeInTypeDef *in, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_PKA_ECCMulFastMode_IT(PKA_HandleTypeDef *hpka, PKA_ECCMulFastModeInTypeDef *in);
|
||||
void HAL_PKA_ECCMul_GetResult(PKA_HandleTypeDef *hpka, PKA_ECCMulOutTypeDef *out);
|
||||
|
||||
HAL_StatusTypeDef HAL_PKA_Add(PKA_HandleTypeDef *hpka, PKA_AddInTypeDef *in, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_PKA_Add_IT(PKA_HandleTypeDef *hpka, PKA_AddInTypeDef *in);
|
||||
HAL_StatusTypeDef HAL_PKA_Sub(PKA_HandleTypeDef *hpka, PKA_SubInTypeDef *in, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_PKA_Sub_IT(PKA_HandleTypeDef *hpka, PKA_SubInTypeDef *in);
|
||||
HAL_StatusTypeDef HAL_PKA_Cmp(PKA_HandleTypeDef *hpka, PKA_CmpInTypeDef *in, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_PKA_Cmp_IT(PKA_HandleTypeDef *hpka, PKA_CmpInTypeDef *in);
|
||||
HAL_StatusTypeDef HAL_PKA_Mul(PKA_HandleTypeDef *hpka, PKA_MulInTypeDef *in, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_PKA_Mul_IT(PKA_HandleTypeDef *hpka, PKA_MulInTypeDef *in);
|
||||
HAL_StatusTypeDef HAL_PKA_ModAdd(PKA_HandleTypeDef *hpka, PKA_ModAddInTypeDef *in, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_PKA_ModAdd_IT(PKA_HandleTypeDef *hpka, PKA_ModAddInTypeDef *in);
|
||||
HAL_StatusTypeDef HAL_PKA_ModSub(PKA_HandleTypeDef *hpka, PKA_ModSubInTypeDef *in, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_PKA_ModSub_IT(PKA_HandleTypeDef *hpka, PKA_ModSubInTypeDef *in);
|
||||
HAL_StatusTypeDef HAL_PKA_ModInv(PKA_HandleTypeDef *hpka, PKA_ModInvInTypeDef *in, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_PKA_ModInv_IT(PKA_HandleTypeDef *hpka, PKA_ModInvInTypeDef *in);
|
||||
HAL_StatusTypeDef HAL_PKA_ModRed(PKA_HandleTypeDef *hpka, PKA_ModRedInTypeDef *in, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_PKA_ModRed_IT(PKA_HandleTypeDef *hpka, PKA_ModRedInTypeDef *in);
|
||||
HAL_StatusTypeDef HAL_PKA_MontgomeryMul(PKA_HandleTypeDef *hpka, PKA_MontgomeryMulInTypeDef *in, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_PKA_MontgomeryMul_IT(PKA_HandleTypeDef *hpka, PKA_MontgomeryMulInTypeDef *in);
|
||||
void HAL_PKA_Arithmetic_GetResult(PKA_HandleTypeDef *hpka, uint32_t *pRes);
|
||||
|
||||
HAL_StatusTypeDef HAL_PKA_MontgomeryParam(PKA_HandleTypeDef *hpka, PKA_MontgomeryParamInTypeDef *in, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_PKA_MontgomeryParam_IT(PKA_HandleTypeDef *hpka, PKA_MontgomeryParamInTypeDef *in);
|
||||
void HAL_PKA_MontgomeryParam_GetResult(PKA_HandleTypeDef *hpka, uint32_t *pRes);
|
||||
|
||||
|
||||
HAL_StatusTypeDef HAL_PKA_Abort(PKA_HandleTypeDef *hpka);
|
||||
void HAL_PKA_RAMReset(PKA_HandleTypeDef *hpka);
|
||||
void HAL_PKA_OperationCpltCallback(PKA_HandleTypeDef *hpka);
|
||||
void HAL_PKA_ErrorCallback(PKA_HandleTypeDef *hpka);
|
||||
void HAL_PKA_IRQHandler(PKA_HandleTypeDef *hpka);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup PKA_Exported_Functions_Group3
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral State and Error functions ***************************************/
|
||||
HAL_PKA_StateTypeDef HAL_PKA_GetState(PKA_HandleTypeDef *hpka);
|
||||
uint32_t HAL_PKA_GetError(PKA_HandleTypeDef *hpka);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* defined(PKA) && defined(HAL_PKA_MODULE_ENABLED) */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32WBxx_HAL_PKA_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -1,515 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32wbxx_hal_pwr.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of PWR HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32WBxx_HAL_PWR_H
|
||||
#define STM32WBxx_HAL_PWR_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32wbxx_hal_def.h"
|
||||
|
||||
/* Include low level driver */
|
||||
#include "stm32wbxx_ll_pwr.h"
|
||||
#include "stm32wbxx_ll_exti.h"
|
||||
|
||||
/** @addtogroup STM32WBxx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup PWR PWR
|
||||
* @brief PWR HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup PWR_Exported_Types PWR Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief PWR PVD configuration structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level.
|
||||
This parameter can be a value of @ref PWR_PVD_detection_level. */
|
||||
|
||||
uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins.
|
||||
This parameter can be a value of @ref PWR_PVD_Mode. */
|
||||
}PWR_PVDTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup PWR_Exported_Constants PWR Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_PVD_detection_level Power Voltage Detector Level selection
|
||||
* @note Refer datasheet for selection voltage value
|
||||
* @{
|
||||
*/
|
||||
#define PWR_PVDLEVEL_0 (0x00000000U) /*!< PVD threshold around 2.0 V */
|
||||
#define PWR_PVDLEVEL_1 ( PWR_CR2_PLS_0) /*!< PVD threshold around 2.2 V */
|
||||
#define PWR_PVDLEVEL_2 ( PWR_CR2_PLS_1 ) /*!< PVD threshold around 2.4 V */
|
||||
#define PWR_PVDLEVEL_3 ( PWR_CR2_PLS_1 | PWR_CR2_PLS_0) /*!< PVD threshold around 2.5 V */
|
||||
#define PWR_PVDLEVEL_4 (PWR_CR2_PLS_2 ) /*!< PVD threshold around 2.6 V */
|
||||
#define PWR_PVDLEVEL_5 (PWR_CR2_PLS_2 | PWR_CR2_PLS_0) /*!< PVD threshold around 2.8 V */
|
||||
#define PWR_PVDLEVEL_6 (PWR_CR2_PLS_2 | PWR_CR2_PLS_1 ) /*!< PVD threshold around 2.9 V */
|
||||
#define PWR_PVDLEVEL_7 (PWR_CR2_PLS_2 | PWR_CR2_PLS_1 | PWR_CR2_PLS_0) /*!< External input analog voltage (compared internally to VREFINT) */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_PVD_Mode PWR PVD interrupt and event mode
|
||||
* @{
|
||||
*/
|
||||
/* Note: On STM32WB serie, power PVD event is not available on AIEC lines */
|
||||
/* (only interruption is available through AIEC line 16). */
|
||||
#define PWR_PVD_MODE_NORMAL (0x00000000U) /*!< Basic mode is used */
|
||||
|
||||
#define PWR_PVD_MODE_IT_RISING (PVD_MODE_IT | PVD_RISING_EDGE) /*!< External Interrupt Mode with Rising edge trigger detection */
|
||||
#define PWR_PVD_MODE_IT_FALLING (PVD_MODE_IT | PVD_FALLING_EDGE) /*!< External Interrupt Mode with Falling edge trigger detection */
|
||||
#define PWR_PVD_MODE_IT_RISING_FALLING (PVD_MODE_IT | PVD_RISING_FALLING_EDGE) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Note: On STM32WB serie, power PVD event is not available on AIEC lines */
|
||||
/* (only interruption is available through AIEC line 16). */
|
||||
|
||||
/** @defgroup PWR_Low_Power_Mode_Selection PWR Low Power Mode Selection
|
||||
* @{
|
||||
*/
|
||||
#define PWR_LOWPOWERMODE_STOP0 (0x00000000u) /*!< Stop 0: stop mode with main regulator */
|
||||
#define PWR_LOWPOWERMODE_STOP1 (PWR_CR1_LPMS_0) /*!< Stop 1: stop mode with low power regulator */
|
||||
#if defined(PWR_SUPPORT_STOP2)
|
||||
#define PWR_LOWPOWERMODE_STOP2 (PWR_CR1_LPMS_1) /*!< Stop 2: stop mode with low power regulator and VDD12I interruptible digital core domain supply OFF (less peripherals activated than low power mode stop 1 to reduce power consumption)*/
|
||||
#endif
|
||||
#define PWR_LOWPOWERMODE_STANDBY (PWR_CR1_LPMS_0 | PWR_CR1_LPMS_1) /*!< Standby mode */
|
||||
#define PWR_LOWPOWERMODE_SHUTDOWN (PWR_CR1_LPMS_2) /*!< Shutdown mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_Regulator_state_in_SLEEP_STOP_mode PWR regulator mode
|
||||
* @{
|
||||
*/
|
||||
#define PWR_MAINREGULATOR_ON (0x00000000U) /*!< Regulator in main mode */
|
||||
#define PWR_LOWPOWERREGULATOR_ON (PWR_CR1_LPR) /*!< Regulator in low-power mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry
|
||||
* @{
|
||||
*/
|
||||
#define PWR_SLEEPENTRY_WFI ((uint8_t)0x01) /*!< Wait For Interruption instruction to enter Sleep mode */
|
||||
#define PWR_SLEEPENTRY_WFE ((uint8_t)0x02) /*!< Wait For Event instruction to enter Sleep mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_STOP_mode_entry PWR STOP mode entry
|
||||
* @{
|
||||
*/
|
||||
#define PWR_STOPENTRY_WFI ((uint8_t)0x01) /*!< Wait For Interruption instruction to enter Stop mode */
|
||||
#define PWR_STOPENTRY_WFE ((uint8_t)0x02) /*!< Wait For Event instruction to enter Stop mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/** @defgroup PWR_Private_Defines PWR Private Defines
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_PVD_EXTI_LINE PWR PVD external interrupt line
|
||||
* @{
|
||||
*/
|
||||
#define PWR_EXTI_LINE_PVD (LL_EXTI_LINE_16) /*!< External interrupt line 16 Connected to the PWR PVD */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask
|
||||
* @{
|
||||
*/
|
||||
/* Note: On STM32WB serie, power PVD event is not available on AIEC lines */
|
||||
/* (only interruption is available through AIEC line 16). */
|
||||
#define PVD_MODE_IT (0x00010000U) /*!< Mask for interruption yielded by PVD threshold crossing */
|
||||
#define PVD_RISING_EDGE (0x00000001U) /*!< Mask for rising edge set as PVD trigger */
|
||||
#define PVD_FALLING_EDGE (0x00000002U) /*!< Mask for falling edge set as PVD trigger */
|
||||
#define PVD_RISING_FALLING_EDGE (0x00000003U) /*!< Mask for rising and falling edges set as PVD trigger */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/** @defgroup PWR_Exported_Macros PWR Exported Macros
|
||||
* @{
|
||||
*/
|
||||
/** @brief Check whether or not a specific PWR flag is set.
|
||||
* @param __FLAG__ specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
*
|
||||
* /--------------------------------SR1-------------------------------/
|
||||
* @arg @ref PWR_FLAG_WUF1 Wake Up Flag 1. Indicates that a wakeup event
|
||||
* was received from the WKUP pin 1.
|
||||
* @arg @ref PWR_FLAG_WUF2 Wake Up Flag 2. Indicates that a wakeup event
|
||||
* was received from the WKUP pin 2.
|
||||
* @arg @ref PWR_FLAG_WUF3 Wake Up Flag 3. Indicates that a wakeup event
|
||||
* was received from the WKUP pin 3.
|
||||
* @arg @ref PWR_FLAG_WUF4 Wake Up Flag 4. Indicates that a wakeup event
|
||||
* was received from the WKUP pin 4.
|
||||
* @arg @ref PWR_FLAG_WUF5 Wake Up Flag 5. Indicates that a wakeup event
|
||||
* was received from the WKUP pin 5.
|
||||
*
|
||||
* @arg @ref PWR_FLAG_BHWF BLE_Host WakeUp Flag
|
||||
* @arg @ref PWR_FLAG_FRCBYPI SMPS Forced in Bypass Interrupt Flag
|
||||
* @arg @ref PWR_FLAG_RFPHASEI Radio Phase Interrupt Flag
|
||||
* @arg @ref PWR_FLAG_BLEACTI BLE Activity Interrupt Flag
|
||||
* @arg @ref PWR_FLAG_802ACTI 802.15.4 Activity Interrupt Flag
|
||||
* @arg @ref PWR_FLAG_HOLDC2I CPU2 on-Hold Interrupt Flag
|
||||
* @arg @ref PWR_FLAG_WUFI Wake-Up Flag Internal. Set when a wakeup is detected on
|
||||
* the internal wakeup line.
|
||||
*
|
||||
* @arg @ref PWR_FLAG_SMPSRDYF SMPS Ready Flag
|
||||
* @arg @ref PWR_FLAG_SMPSBYPF SMPS Bypass Flag
|
||||
*
|
||||
* /--------------------------------SR2-------------------------------/
|
||||
* @arg @ref PWR_FLAG_REGLPS Low Power Regulator Started. Indicates whether or not the
|
||||
* low-power regulator is ready.
|
||||
* @arg @ref PWR_FLAG_REGLPF Low Power Regulator Flag. Indicates whether the
|
||||
* regulator is ready in main mode or is in low-power mode.
|
||||
*
|
||||
* @arg @ref PWR_FLAG_VOSF Voltage Scaling Flag. Indicates whether the regulator is ready
|
||||
* in the selected voltage range or is still changing to the required voltage level.
|
||||
* @arg @ref PWR_FLAG_PVDO Power Voltage Detector Output. Indicates whether VDD voltage is
|
||||
* below or above the selected PVD threshold.
|
||||
*
|
||||
* @arg @ref PWR_FLAG_PVMO1 Peripheral Voltage Monitoring Output 1. Indicates whether VDDUSB voltage is
|
||||
* is below or above PVM1 threshold (applicable when USB feature is supported).
|
||||
* @arg @ref PWR_FLAG_PVMO3 Peripheral Voltage Monitoring Output 3. Indicates whether VDDA voltage is
|
||||
* is below or above PVM3 threshold.
|
||||
*
|
||||
* /----------------------------EXTSCR--------------------------/
|
||||
* @arg @ref PWR_FLAG_STOP System Stop Flag for CPU1.
|
||||
* @arg @ref PWR_FLAG_SB System Standby Flag for CPU1.
|
||||
*
|
||||
* @arg @ref PWR_FLAG_C2STOP System Stop Flag for CPU2.
|
||||
* @arg @ref PWR_FLAG_C2SB System Standby Flag for CPU2.
|
||||
*
|
||||
* @arg @ref PWR_FLAG_CRITICAL_RF_PHASE Critical radio system phase flag.
|
||||
*
|
||||
* @arg @ref PWR_FLAG_C1DEEPSLEEP CPU1 DeepSleep Flag.
|
||||
* @arg @ref PWR_FLAG_C2DEEPSLEEP CPU2 DeepSleep Flag.
|
||||
*
|
||||
* @retval The new state of __FLAG__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_PWR_GET_FLAG(__FLAG__) ((((__FLAG__) & PWR_FLAG_REG_MASK) == PWR_FLAG_REG_SR1) ? \
|
||||
( \
|
||||
PWR->SR1 & (1UL << ((__FLAG__) & 31UL)) \
|
||||
) \
|
||||
: \
|
||||
( \
|
||||
(((__FLAG__) & PWR_FLAG_REG_MASK) == PWR_FLAG_REG_SR2) ? \
|
||||
( \
|
||||
PWR->SR2 & (1UL << ((__FLAG__) & 31UL)) \
|
||||
) \
|
||||
: \
|
||||
( \
|
||||
PWR->EXTSCR & (1UL << ((__FLAG__) & 31UL)) \
|
||||
) \
|
||||
) \
|
||||
)
|
||||
|
||||
/** @brief Clear a specific PWR flag.
|
||||
* @note Clearing of flags {PWR_FLAG_STOP, PWR_FLAG_SB}
|
||||
* and flags {PWR_FLAG_C2STOP, PWR_FLAG_C2SB} are grouped:
|
||||
* clearing of one flag also clears the other one.
|
||||
* @param __FLAG__ specifies the flag to clear.
|
||||
* This parameter can be one of the following values:
|
||||
*
|
||||
* /--------------------------------SCR (SRR)------------------------------/
|
||||
* @arg @ref PWR_FLAG_WUF1 Wake Up Flag 1. Indicates that a wakeup event
|
||||
* was received from the WKUP pin 1.
|
||||
* @arg @ref PWR_FLAG_WUF2 Wake Up Flag 2. Indicates that a wakeup event
|
||||
* was received from the WKUP pin 2.
|
||||
* @arg @ref PWR_FLAG_WUF3 Wake Up Flag 3. Indicates that a wakeup event
|
||||
* was received from the WKUP pin 3.
|
||||
* @arg @ref PWR_FLAG_WUF4 Wake Up Flag 4. Indicates that a wakeup event
|
||||
* was received from the WKUP pin 4.
|
||||
* @arg @ref PWR_FLAG_WUF5 Wake Up Flag 5. Indicates that a wakeup event
|
||||
* was received from the WKUP pin 5.
|
||||
* @arg @ref PWR_FLAG_WU Encompasses all five Wake Up Flags.
|
||||
*
|
||||
* @arg @ref PWR_FLAG_BHWF Clear BLE_Host Wakeup Flag.
|
||||
* @arg @ref PWR_FLAG_FRCBYPI Clear SMPS Forced in Bypass Interrupt Flag.
|
||||
* @arg @ref PWR_FLAG_RFPHASEI RF Phase Interrupt Clear.
|
||||
* @arg @ref PWR_FLAG_BLEACTI BLE Activity Interrupt Clear.
|
||||
* @arg @ref PWR_FLAG_802ACTI 802.15.4. Activity Interrupt Clear.
|
||||
* @arg @ref PWR_FLAG_HOLDC2I CPU2 on-Hold Interrupt Clear.
|
||||
*
|
||||
* /----------------------------EXTSCR--------------------------/
|
||||
* @arg @ref PWR_FLAG_STOP System Stop Flag for CPU1.
|
||||
* @arg @ref PWR_FLAG_SB System Standby Flag for CPU1.
|
||||
*
|
||||
* @arg @ref PWR_FLAG_C2STOP System Stop Flag for CPU2.
|
||||
* @arg @ref PWR_FLAG_C2SB System Standby Flag for CPU2.
|
||||
*
|
||||
* @arg @ref PWR_FLAG_CRITICAL_RF_PHASE RF phase Flag.
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_CLEAR_FLAG(__FLAG__) ((((__FLAG__) & PWR_FLAG_REG_MASK) == PWR_FLAG_REG_EXTSCR) ? \
|
||||
( \
|
||||
PWR->EXTSCR = (1UL << (((__FLAG__) & PWR_FLAG_EXTSCR_CLR_MASK) >> PWR_FLAG_EXTSCR_CLR_POS)) \
|
||||
) \
|
||||
: \
|
||||
( \
|
||||
(((__FLAG__)) == PWR_FLAG_WU) ? \
|
||||
(PWR->SCR = PWR_SCR_CWUF) : \
|
||||
(PWR->SCR = (1UL << ((__FLAG__) & 31UL))) \
|
||||
) \
|
||||
)
|
||||
|
||||
/**
|
||||
* @brief Enable the PVD Extended Interrupt C1 Line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVD_EXTI_ENABLE_IT() LL_EXTI_EnableIT_0_31(PWR_EXTI_LINE_PVD)
|
||||
|
||||
/**
|
||||
* @brief Enable the PVD Extended Interrupt C2 Line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVD_EXTIC2_ENABLE_IT() LL_C2_EXTI_EnableIT_0_31(PWR_EXTI_LINE_PVD)
|
||||
|
||||
|
||||
/**
|
||||
* @brief Disable the PVD Extended Interrupt C1 Line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVD_EXTI_DISABLE_IT() LL_EXTI_DisableIT_0_31(PWR_EXTI_LINE_PVD)
|
||||
|
||||
/**
|
||||
* @brief Disable the PVD Extended Interrupt C2 Line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVD_EXTIC2_DISABLE_IT() LL_C2_EXTI_DisableIT_0_31(PWR_EXTI_LINE_PVD)
|
||||
|
||||
/* Note: On STM32WB serie, power PVD event is not available on AIEC lines */
|
||||
/* (only interruption is available through AIEC line 16). */
|
||||
|
||||
/**
|
||||
* @brief Enable the PVD Extended Interrupt Rising Trigger.
|
||||
* @note PVD flag polarity is inverted compared to EXTI line, therefore
|
||||
* EXTI rising and falling logic edges are inverted versus PVD voltage edges.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() LL_EXTI_EnableRisingTrig_0_31(PWR_EXTI_LINE_PVD)
|
||||
|
||||
/**
|
||||
* @brief Disable the PVD Extended Interrupt Rising Trigger.
|
||||
* @note PVD flag polarity is inverted compared to EXTI line, therefore
|
||||
* EXTI rising and falling logic edges are inverted versus PVD voltage edges.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() LL_EXTI_DisableFallingTrig_0_31(PWR_EXTI_LINE_PVD)
|
||||
|
||||
/**
|
||||
* @brief Enable the PVD Extended Interrupt Falling Trigger.
|
||||
* @note PVD flag polarity is inverted compared to EXTI line, therefore
|
||||
* EXTI rising and falling logic edges are inverted versus PVD voltage edges.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() LL_EXTI_EnableFallingTrig_0_31(PWR_EXTI_LINE_PVD)
|
||||
|
||||
|
||||
/**
|
||||
* @brief Disable the PVD Extended Interrupt Falling Trigger.
|
||||
* @note PVD flag polarity is inverted compared to EXTI line, therefore
|
||||
* EXTI rising and falling logic edges are inverted versus PVD voltage edges.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() LL_EXTI_DisableRisingTrig_0_31(PWR_EXTI_LINE_PVD)
|
||||
|
||||
|
||||
/**
|
||||
* @brief Enable the PVD Extended Interrupt Rising & Falling Trigger.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() \
|
||||
do { \
|
||||
__HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); \
|
||||
__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); \
|
||||
} while(0)
|
||||
|
||||
/**
|
||||
* @brief Disable the PVD Extended Interrupt Rising & Falling Trigger.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() \
|
||||
do { \
|
||||
__HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); \
|
||||
__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); \
|
||||
} while(0)
|
||||
|
||||
/**
|
||||
* @brief Generate a Software interrupt on selected EXTI line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() LL_EXTI_GenerateSWI_0_31(PWR_EXTI_LINE_PVD)
|
||||
|
||||
/**
|
||||
* @brief Check whether or not the PVD EXTI interrupt flag is set.
|
||||
* @retval EXTI PVD Line Status.
|
||||
*/
|
||||
#define __HAL_PWR_PVD_EXTI_GET_FLAG() LL_EXTI_ReadFlag_0_31(PWR_EXTI_LINE_PVD)
|
||||
|
||||
/**
|
||||
* @brief Clear the PVD EXTI interrupt flag.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() LL_EXTI_ClearFlag_0_31(PWR_EXTI_LINE_PVD)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Private macros --------------------------------------------------------*/
|
||||
/** @defgroup PWR_Private_Macros PWR Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \
|
||||
((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \
|
||||
((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \
|
||||
((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7))
|
||||
|
||||
#define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_NORMAL) ||\
|
||||
((MODE) == PWR_PVD_MODE_IT_RISING) ||\
|
||||
((MODE) == PWR_PVD_MODE_IT_FALLING) ||\
|
||||
((MODE) == PWR_PVD_MODE_IT_RISING_FALLING))
|
||||
|
||||
|
||||
|
||||
#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \
|
||||
((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))
|
||||
|
||||
|
||||
#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || \
|
||||
((ENTRY) == PWR_SLEEPENTRY_WFE))
|
||||
|
||||
#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || \
|
||||
((ENTRY) == PWR_STOPENTRY_WFE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Include PWR HAL Extended module */
|
||||
#include "stm32wbxx_hal_pwr_ex.h"
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup PWR_Exported_Functions PWR Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Initialization and de-initialization functions *******************************/
|
||||
void HAL_PWR_DeInit(void);
|
||||
|
||||
void HAL_PWR_EnableBkUpAccess(void);
|
||||
void HAL_PWR_DisableBkUpAccess(void);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral Control functions ************************************************/
|
||||
HAL_StatusTypeDef HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD);
|
||||
void HAL_PWR_EnablePVD(void);
|
||||
void HAL_PWR_DisablePVD(void);
|
||||
|
||||
/* WakeUp pins configuration functions ****************************************/
|
||||
void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity);
|
||||
void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx);
|
||||
|
||||
/* Low Power modes configuration functions ************************************/
|
||||
void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry);
|
||||
void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry);
|
||||
void HAL_PWR_EnterSTANDBYMode(void);
|
||||
|
||||
void HAL_PWR_PVDCallback(void);
|
||||
void HAL_PWR_EnableSleepOnExit(void);
|
||||
void HAL_PWR_DisableSleepOnExit(void);
|
||||
|
||||
void HAL_PWR_EnableSEVOnPend(void);
|
||||
void HAL_PWR_DisableSEVOnPend(void);
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* STM32WBxx_HAL_PWR_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -1,978 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32wbxx_hal_pwr_ex.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of PWR HAL Extended module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32WBxx_HAL_PWR_EX_H
|
||||
#define STM32WBxx_HAL_PWR_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32wbxx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32WBxx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup PWREx PWREx
|
||||
* @brief PWR Extended HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup PWREx_Exported_Types PWR Extended Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief PWR PVM configuration structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t PVMType; /*!< PVMType: Specifies which voltage is monitored and against which threshold.
|
||||
This parameter can be a value of @ref PWREx_PVM_Type.
|
||||
@arg @ref PWR_PVM_1 Peripheral Voltage Monitoring 1 enable: VDDUSB versus 1.2 V (applicable when USB feature is supported).
|
||||
@arg @ref PWR_PVM_3 Peripheral Voltage Monitoring 3 enable: VDDA versus 1.62 V.
|
||||
*/
|
||||
|
||||
uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins.
|
||||
This parameter can be a value of @ref PWREx_PVM_Mode. */
|
||||
uint32_t WakeupTarget; /*!< Specifies the Wakeup Target
|
||||
This parameter can be a value of @ref PWREx_WakeUpTarget_Definition */
|
||||
}PWR_PVMTypeDef;
|
||||
|
||||
#if defined(PWR_CR5_SMPSEN)
|
||||
/**
|
||||
* @brief PWR SMPS step down configuration structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t StartupCurrent; /*!< SMPS step down converter supply startup current selection.
|
||||
This parameter can be a value of @ref PWREx_SMPS_STARTUP_CURRENT. */
|
||||
|
||||
uint32_t OutputVoltage; /*!< SMPS step down converter output voltage scaling voltage level.
|
||||
This parameter can be a value of @ref PWREx_SMPS_OUTPUT_VOLTAGE_LEVEL */
|
||||
}PWR_SMPSTypeDef;
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup PWREx_Exported_Constants PWR Extended Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup PWREx_WUP_Polarity Shift to apply to retrieve polarity information from PWR_WAKEUP_PINy_xxx constants
|
||||
* @{
|
||||
*/
|
||||
#define PWR_WUP_POLARITY_SHIFT 0x05U /*!< Internal constant used to retrieve wakeup pin polarity */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup PWREx_WakeUp_Pins PWR wake-up pins
|
||||
* @{
|
||||
*/
|
||||
#define PWR_WAKEUP_PIN1_HIGH PWR_CR3_EWUP1 /*!< Wakeup pin 1 (with high level polarity) */
|
||||
#if defined(PWR_CR3_EWUP2)
|
||||
#define PWR_WAKEUP_PIN2_HIGH PWR_CR3_EWUP2 /*!< Wakeup pin 2 (with high level polarity) */
|
||||
#endif
|
||||
#if defined(PWR_CR3_EWUP3)
|
||||
#define PWR_WAKEUP_PIN3_HIGH PWR_CR3_EWUP3 /*!< Wakeup pin 3 (with high level polarity) */
|
||||
#endif
|
||||
#define PWR_WAKEUP_PIN4_HIGH PWR_CR3_EWUP4 /*!< Wakeup pin 4 (with high level polarity) */
|
||||
#if defined(PWR_CR3_EWUP5)
|
||||
#define PWR_WAKEUP_PIN5_HIGH PWR_CR3_EWUP5 /*!< Wakeup pin 5 (with high level polarity) */
|
||||
#endif
|
||||
|
||||
#define PWR_WAKEUP_PIN1_LOW ((PWR_CR4_WP1<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP1) /*!< Wakeup pin 1 (with low level polarity) */
|
||||
#if defined(PWR_CR3_EWUP2)
|
||||
#define PWR_WAKEUP_PIN2_LOW ((PWR_CR4_WP2<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP2) /*!< Wakeup pin 2 (with low level polarity) */
|
||||
#endif
|
||||
#if defined(PWR_CR3_EWUP3)
|
||||
#define PWR_WAKEUP_PIN3_LOW ((PWR_CR4_WP3<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP3) /*!< Wakeup pin 3 (with low level polarity) */
|
||||
#endif
|
||||
#define PWR_WAKEUP_PIN4_LOW ((PWR_CR4_WP4<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP4) /*!< Wakeup pin 4 (with low level polarity) */
|
||||
#if defined(PWR_CR3_EWUP5)
|
||||
#define PWR_WAKEUP_PIN5_LOW ((PWR_CR4_WP5<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP5) /*!< Wakeup pin 5 (with low level polarity) */
|
||||
#endif
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Literals kept for legacy purpose */
|
||||
#define PWR_WAKEUP_PIN1 PWR_CR3_EWUP1 /*!< Wakeup pin 1 (with high level polarity) */
|
||||
#if defined(PWR_CR3_EWUP2)
|
||||
#define PWR_WAKEUP_PIN2 PWR_CR3_EWUP2 /*!< Wakeup pin 2 (with high level polarity) */
|
||||
#endif
|
||||
#if defined(PWR_CR3_EWUP3)
|
||||
#define PWR_WAKEUP_PIN3 PWR_CR3_EWUP3 /*!< Wakeup pin 3 (with high level polarity) */
|
||||
#endif
|
||||
#define PWR_WAKEUP_PIN4 PWR_CR3_EWUP4 /*!< Wakeup pin 4 (with high level polarity) */
|
||||
#if defined(PWR_CR3_EWUP5)
|
||||
#define PWR_WAKEUP_PIN5 PWR_CR3_EWUP5 /*!< Wakeup pin 5 (with high level polarity) */
|
||||
#endif
|
||||
|
||||
/** @defgroup PWREx_PIN_Polarity PWREx Pin Polarity configuration
|
||||
* @{
|
||||
*/
|
||||
#define PWR_PIN_POLARITY_HIGH 0x00000000U
|
||||
#define PWR_PIN_POLARITY_LOW 0x00000001U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWREx_PVM_Type Peripheral Voltage Monitoring type
|
||||
* @{
|
||||
*/
|
||||
#if defined(PWR_CR2_PVME1)
|
||||
#define PWR_PVM_1 PWR_CR2_PVME1 /*!< Peripheral Voltage Monitoring 1 enable: VDDUSB versus 1.2 V (applicable when USB feature is supported) */
|
||||
#endif
|
||||
#define PWR_PVM_3 PWR_CR2_PVME3 /*!< Peripheral Voltage Monitoring 3 enable: VDDA versus 1.62 V */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWREx_PVM_Mode PWR PVM interrupt and event mode
|
||||
* @{
|
||||
*/
|
||||
#define PWR_PVM_MODE_NORMAL (0x00000000U) /*!< basic mode is used */
|
||||
|
||||
#define PWR_PVM_MODE_IT_RISING (PVM_MODE_IT | PVM_RISING_EDGE) /*!< External Interrupt Mode with Rising edge trigger detection */
|
||||
#define PWR_PVM_MODE_IT_FALLING (PVM_MODE_IT | PVM_FALLING_EDGE) /*!< External Interrupt Mode with Falling edge trigger detection */
|
||||
#define PWR_PVM_MODE_IT_RISING_FALLING (PVM_MODE_IT | PVM_RISING_FALLING_EDGE) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
|
||||
|
||||
#define PWR_PVM_MODE_EVENT_RISING (PVM_MODE_EVT | PVM_RISING_EDGE) /*!< Event Mode with Rising edge trigger detection */
|
||||
#define PWR_PVM_MODE_EVENT_FALLING (PVM_MODE_EVT | PVM_FALLING_EDGE) /*!< Event Mode with Falling edge trigger detection */
|
||||
#define PWR_PVM_MODE_EVENT_RISING_FALLING (PVM_MODE_EVT | PVM_RISING_FALLING_EDGE) /*!< Event Mode with Rising/Falling edge trigger detection */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWREx_Flash_PowerDown Flash Power Down modes
|
||||
* @{
|
||||
*/
|
||||
#define PWR_FLASHPD_LPRUN PWR_CR1_FPDR /*!< Enable Flash power down in low power run mode */
|
||||
#define PWR_FLASHPD_LPSLEEP PWR_CR1_FPDS /*!< Enable Flash power down in low power sleep mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWREx_Regulator_Voltage_Scale PWR Regulator voltage scale
|
||||
* @{
|
||||
*/
|
||||
#if defined(PWR_CR1_VOS)
|
||||
#define PWR_REGULATOR_VOLTAGE_SCALE1 PWR_CR1_VOS_0 /*!< Regulator voltage output range 1 mode, typical output voltage at 1.2 V, system frequency up to 64 MHz */
|
||||
#define PWR_REGULATOR_VOLTAGE_SCALE2 PWR_CR1_VOS_1 /*!< Regulator voltage output range 2 mode, typical output voltage at 1.0 V, system frequency up to 16 MHz */
|
||||
#else
|
||||
#define PWR_REGULATOR_VOLTAGE_SCALE1 (0x00000200UL) /*!< Regulator voltage output range 1 mode, typical output voltage at 1.2 V, system frequency up to 64 MHz */
|
||||
#endif
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup PWREx_VBAT_Battery_Charging_Selection PWR battery charging resistor selection
|
||||
* @{
|
||||
*/
|
||||
#define PWR_BATTERY_CHARGING_RESISTOR_5 (0x00000000U) /*!< VBAT charging through a 5 kOhms resistor */
|
||||
#define PWR_BATTERY_CHARGING_RESISTOR_1_5 PWR_CR4_VBRS /*!< VBAT charging through a 1.5 kOhms resistor */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWREx_VBAT_Battery_Charging PWR battery charging
|
||||
* @{
|
||||
*/
|
||||
#define PWR_BATTERY_CHARGING_DISABLE (0x00000000U)
|
||||
#define PWR_BATTERY_CHARGING_ENABLE PWR_CR4_VBE
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWREx_GPIO_Bit_Number GPIO bit number for I/O setting in standby/shutdown mode
|
||||
* @{
|
||||
*/
|
||||
#define PWR_GPIO_BIT_0 PWR_PUCRA_PA0 /*!< GPIO port I/O pin 0 */
|
||||
#define PWR_GPIO_BIT_1 PWR_PUCRA_PA1 /*!< GPIO port I/O pin 1 */
|
||||
#define PWR_GPIO_BIT_2 PWR_PUCRA_PA2 /*!< GPIO port I/O pin 2 */
|
||||
#define PWR_GPIO_BIT_3 PWR_PUCRA_PA3 /*!< GPIO port I/O pin 3 */
|
||||
#define PWR_GPIO_BIT_4 PWR_PUCRA_PA4 /*!< GPIO port I/O pin 4 */
|
||||
#define PWR_GPIO_BIT_5 PWR_PUCRA_PA5 /*!< GPIO port I/O pin 5 */
|
||||
#define PWR_GPIO_BIT_6 PWR_PUCRA_PA6 /*!< GPIO port I/O pin 6 */
|
||||
#define PWR_GPIO_BIT_7 PWR_PUCRA_PA7 /*!< GPIO port I/O pin 7 */
|
||||
#define PWR_GPIO_BIT_8 PWR_PUCRA_PA8 /*!< GPIO port I/O pin 8 */
|
||||
#define PWR_GPIO_BIT_9 PWR_PUCRA_PA9 /*!< GPIO port I/O pin 9 */
|
||||
#define PWR_GPIO_BIT_10 PWR_PUCRA_PA10 /*!< GPIO port I/O pin 10 */
|
||||
#define PWR_GPIO_BIT_11 PWR_PUCRA_PA11 /*!< GPIO port I/O pin 11 */
|
||||
#define PWR_GPIO_BIT_12 PWR_PUCRA_PA12 /*!< GPIO port I/O pin 12 */
|
||||
#define PWR_GPIO_BIT_13 PWR_PUCRA_PA13 /*!< GPIO port I/O pin 14 */
|
||||
#define PWR_GPIO_BIT_14 PWR_PDCRC_PC14 /*!< GPIO port I/O pin 14 */
|
||||
#define PWR_GPIO_BIT_15 PWR_PUCRC_PC15 /*!< GPIO port I/O pin 15 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWREx_GPIO GPIO port
|
||||
* @{
|
||||
*/
|
||||
#define PWR_GPIO_A 0x00000000U /*!< GPIO port A */
|
||||
#define PWR_GPIO_B 0x00000001U /*!< GPIO port B */
|
||||
#define PWR_GPIO_C 0x00000002U /*!< GPIO port C */
|
||||
#if defined(GPIOD)
|
||||
#define PWR_GPIO_D 0x00000003U /*!< GPIO port D */
|
||||
#endif
|
||||
#define PWR_GPIO_E 0x00000004U /*!< GPIO port E */
|
||||
#define PWR_GPIO_H 0x00000007U /*!< GPIO port H */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if defined(PWR_CR5_SMPSEN)
|
||||
/** @defgroup PWREx_BOR_CONFIGURATION BOR configuration
|
||||
* @{
|
||||
*/
|
||||
#define PWR_BOR_SYSTEM_RESET (LL_PWR_BOR_SYSTEM_RESET) /*!< BOR will generate a system reset */
|
||||
#define PWR_BOR_SMPS_FORCE_BYPASS (LL_PWR_BOR_SMPS_FORCE_BYPASS) /*!< BOR will for SMPS step down converter in bypass mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWREx_SMPS_OPERATING_MODES SMPS step down converter operating modes
|
||||
* @{
|
||||
*/
|
||||
/* Note: Literals values are defined from register SR2 bits SMPSF and SMPSBF */
|
||||
/* but they are also used as register CR5 bits SMPSEN and SMPSBEN, */
|
||||
/* as used by all SMPS operating mode functions targetting different */
|
||||
/* registers: */
|
||||
/* "LL_PWR_SMPS_SetMode()", "LL_PWR_SMPS_GetMode()" */
|
||||
/* and "LL_PWR_SMPS_GetEffectiveMode()". */
|
||||
#define PWR_SMPS_BYPASS (PWR_SR2_SMPSBF) /*!< SMPS step down in bypass mode */
|
||||
#define PWR_SMPS_STEP_DOWN (PWR_SR2_SMPSF) /*!< SMPS step down in step down mode if system low power mode is run, LP run or stop0. If system low power mode is stop1, stop2, standby, shutdown, then SMPS is forced in mode open to preserve energy stored in decoupling capacitor as long as possible. */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWREx_SMPS_STARTUP_CURRENT SMPS step down converter supply startup current selection
|
||||
* @{
|
||||
*/
|
||||
#define PWR_SMPS_STARTUP_CURRENT_80MA (0x00000000U) /*!< SMPS step down converter supply startup current 80mA */
|
||||
#define PWR_SMPS_STARTUP_CURRENT_100MA ( PWR_CR5_SMPSSC_0) /*!< SMPS step down converter supply startup current 100mA */
|
||||
#define PWR_SMPS_STARTUP_CURRENT_120MA ( PWR_CR5_SMPSSC_1 ) /*!< SMPS step down converter supply startup current 120mA */
|
||||
#define PWR_SMPS_STARTUP_CURRENT_140MA ( PWR_CR5_SMPSSC_1 | PWR_CR5_SMPSSC_0) /*!< SMPS step down converter supply startup current 140mA */
|
||||
#define PWR_SMPS_STARTUP_CURRENT_160MA (PWR_CR5_SMPSSC_2 ) /*!< SMPS step down converter supply startup current 160mA */
|
||||
#define PWR_SMPS_STARTUP_CURRENT_180MA (PWR_CR5_SMPSSC_2 | PWR_CR5_SMPSSC_0) /*!< SMPS step down converter supply startup current 180mA */
|
||||
#define PWR_SMPS_STARTUP_CURRENT_200MA (PWR_CR5_SMPSSC_2 | PWR_CR5_SMPSSC_1 ) /*!< SMPS step down converter supply startup current 200mA */
|
||||
#define PWR_SMPS_STARTUP_CURRENT_220MA (PWR_CR5_SMPSSC_2 | PWR_CR5_SMPSSC_1 | PWR_CR5_SMPSSC_0) /*!< SMPS step down converter supply startup current 220mA */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWREx_SMPS_OUTPUT_VOLTAGE_LEVEL SMPS step down converter output voltage scaling voltage level
|
||||
* @{
|
||||
*/
|
||||
/* Note: SMPS voltage is trimmed during device production to control
|
||||
the actual voltage level variation from device to device. */
|
||||
#define PWR_SMPS_OUTPUT_VOLTAGE_1V20 (0x00000000U) /*!< SMPS step down converter supply output voltage 1.20V */
|
||||
#define PWR_SMPS_OUTPUT_VOLTAGE_1V25 ( PWR_CR5_SMPSVOS_0) /*!< SMPS step down converter supply output voltage 1.25V */
|
||||
#define PWR_SMPS_OUTPUT_VOLTAGE_1V30 ( PWR_CR5_SMPSVOS_1 ) /*!< SMPS step down converter supply output voltage 1.30V */
|
||||
#define PWR_SMPS_OUTPUT_VOLTAGE_1V35 ( PWR_CR5_SMPSVOS_1 | PWR_CR5_SMPSVOS_0) /*!< SMPS step down converter supply output voltage 1.35V */
|
||||
#define PWR_SMPS_OUTPUT_VOLTAGE_1V40 ( PWR_CR5_SMPSVOS_2 ) /*!< SMPS step down converter supply output voltage 1.40V */
|
||||
#define PWR_SMPS_OUTPUT_VOLTAGE_1V45 ( PWR_CR5_SMPSVOS_2 | PWR_CR5_SMPSVOS_0) /*!< SMPS step down converter supply output voltage 1.45V */
|
||||
#define PWR_SMPS_OUTPUT_VOLTAGE_1V50 ( PWR_CR5_SMPSVOS_2 | PWR_CR5_SMPSVOS_1 ) /*!< SMPS step down converter supply output voltage 1.50V */
|
||||
#define PWR_SMPS_OUTPUT_VOLTAGE_1V55 ( PWR_CR5_SMPSVOS_2 | PWR_CR5_SMPSVOS_1 | PWR_CR5_SMPSVOS_0) /*!< SMPS step down converter supply output voltage 1.55V */
|
||||
#define PWR_SMPS_OUTPUT_VOLTAGE_1V60 (PWR_CR5_SMPSVOS_3 ) /*!< SMPS step down converter supply output voltage 1.60V */
|
||||
#define PWR_SMPS_OUTPUT_VOLTAGE_1V65 (PWR_CR5_SMPSVOS_3 | PWR_CR5_SMPSVOS_0) /*!< SMPS step down converter supply output voltage 1.65V */
|
||||
#define PWR_SMPS_OUTPUT_VOLTAGE_1V70 (PWR_CR5_SMPSVOS_3 | PWR_CR5_SMPSVOS_1 ) /*!< SMPS step down converter supply output voltage 1.70V */
|
||||
#define PWR_SMPS_OUTPUT_VOLTAGE_1V75 (PWR_CR5_SMPSVOS_3 | PWR_CR5_SMPSVOS_1 | PWR_CR5_SMPSVOS_0) /*!< SMPS step down converter supply output voltage 1.75V */
|
||||
#define PWR_SMPS_OUTPUT_VOLTAGE_1V80 (PWR_CR5_SMPSVOS_3 | PWR_CR5_SMPSVOS_2 ) /*!< SMPS step down converter supply output voltage 1.80V */
|
||||
#define PWR_SMPS_OUTPUT_VOLTAGE_1V85 (PWR_CR5_SMPSVOS_3 | PWR_CR5_SMPSVOS_2 | PWR_CR5_SMPSVOS_0) /*!< SMPS step down converter supply output voltage 1.85V */
|
||||
#define PWR_SMPS_OUTPUT_VOLTAGE_1V90 (PWR_CR5_SMPSVOS_3 | PWR_CR5_SMPSVOS_2 | PWR_CR5_SMPSVOS_1 ) /*!< SMPS step down converter supply output voltage 1.90V */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif
|
||||
|
||||
/** @defgroup PWREx_Flag PWR Status Flags
|
||||
* Elements values convention: 0000 0000 0XXY YYYYb
|
||||
* - Y YYYY : Flag position in the XX register (5 bits)
|
||||
* - XX : Status register (2 bits)
|
||||
* - 01: SR1 register
|
||||
* - 10: SR2 register
|
||||
* - 11: EXTSCR register
|
||||
* The only exception is PWR_FLAG_WUF, encompassing all
|
||||
* wake-up flags and set to PWR_SR1_WUF.
|
||||
* @{
|
||||
*/
|
||||
/*--------------------------------SR1-------------------------------*/
|
||||
#define PWR_FLAG_WUF1 (PWR_FLAG_REG_SR1 | PWR_SR1_WUF1_Pos) /*!< Wakeup event on wakeup pin 1 */
|
||||
#if defined(PWR_CR3_EWUP2)
|
||||
#define PWR_FLAG_WUF2 (PWR_FLAG_REG_SR1 | PWR_SR1_WUF2_Pos) /*!< Wakeup event on wakeup pin 2 */
|
||||
#endif
|
||||
#if defined(PWR_CR3_EWUP3)
|
||||
#define PWR_FLAG_WUF3 (PWR_FLAG_REG_SR1 | PWR_SR1_WUF3_Pos) /*!< Wakeup event on wakeup pin 3 */
|
||||
#endif
|
||||
#define PWR_FLAG_WUF4 (PWR_FLAG_REG_SR1 | PWR_SR1_WUF4_Pos) /*!< Wakeup event on wakeup pin 4 */
|
||||
#if defined(PWR_CR3_EWUP5)
|
||||
#define PWR_FLAG_WUF5 (PWR_FLAG_REG_SR1 | PWR_SR1_WUF5_Pos) /*!< Wakeup event on wakeup pin 5 */
|
||||
#endif
|
||||
#define PWR_FLAG_WU (PWR_FLAG_REG_SR1 | PWR_SR1_WUF) /*!< Encompass wakeup event on all wakeup pins */
|
||||
|
||||
#if defined(PWR_CR5_SMPSEN)
|
||||
#define PWR_FLAG_FRCBYPI (PWR_FLAG_REG_SR1 | PWR_SR1_SMPSFBF_Pos) /*!< SMPS Forced in Bypass Interrupt Flag */
|
||||
#endif
|
||||
#define PWR_FLAG_BHWF (PWR_FLAG_REG_SR1 | PWR_SR1_BLEWUF_Pos) /*!< BLE_Host WakeUp Flag */
|
||||
#define PWR_FLAG_RFPHASEI (PWR_FLAG_REG_SR1 | PWR_SR1_CRPEF_Pos) /*!< Radio Phase Interrupt Flag */
|
||||
#define PWR_FLAG_BLEACTI (PWR_FLAG_REG_SR1 | PWR_SR1_BLEAF_Pos) /*!< BLE Activity Interrupt Flag */
|
||||
#define PWR_FLAG_802ACTI (PWR_FLAG_REG_SR1 | PWR_SR1_802AF_Pos) /*!< 802.15.4 Activity Interrupt Flag */
|
||||
#define PWR_FLAG_HOLDC2I (PWR_FLAG_REG_SR1 | PWR_SR1_C2HF_Pos) /*!< CPU2 on-Hold Interrupt Flag */
|
||||
#define PWR_FLAG_WUFI (PWR_FLAG_REG_SR1 | PWR_SR1_WUFI_Pos) /*!< Wakeup on internal wakeup line */
|
||||
|
||||
/*--------------------------------SR2-------------------------------*/
|
||||
#if defined(PWR_CR5_SMPSEN)
|
||||
#define PWR_FLAG_SMPSRDYF (PWR_FLAG_REG_SR2 | PWR_SR2_SMPSBF_Pos) /*!< SMPS Ready Flag */
|
||||
#define PWR_FLAG_SMPSBYPF (PWR_FLAG_REG_SR2 | PWR_SR2_SMPSF_Pos) /*!< SMPS Bypass Flag */
|
||||
#endif
|
||||
|
||||
#define PWR_FLAG_REGLPS (PWR_FLAG_REG_SR2 | PWR_SR2_REGLPS_Pos) /*!< Low-power regulator start flag */
|
||||
#define PWR_FLAG_REGLPF (PWR_FLAG_REG_SR2 | PWR_SR2_REGLPF_Pos) /*!< Low-power regulator flag */
|
||||
|
||||
#if defined(PWR_CR1_VOS)
|
||||
#define PWR_FLAG_VOSF (PWR_FLAG_REG_SR2 | PWR_SR2_VOSF_Pos) /*!< Voltage scaling flag */
|
||||
#endif
|
||||
#define PWR_FLAG_PVDO (PWR_FLAG_REG_SR2 | PWR_SR2_PVDO_Pos) /*!< Power Voltage Detector output flag */
|
||||
|
||||
#if defined(PWR_CR2_PVME1)
|
||||
#define PWR_FLAG_PVMO1 (PWR_FLAG_REG_SR2 | PWR_SR2_PVMO1_Pos) /*!< Power Voltage Monitoring 1 output flag */
|
||||
#endif
|
||||
#define PWR_FLAG_PVMO3 (PWR_FLAG_REG_SR2 | PWR_SR2_PVMO3_Pos) /*!< Power Voltage Monitoring 3 output flag */
|
||||
|
||||
/*------------------------------EXTSCR---------------------------*/
|
||||
#define PWR_FLAG_SB (PWR_FLAG_REG_EXTSCR | PWR_EXTSCR_C1SBF_Pos | (PWR_EXTSCR_C1CSSF_Pos << PWR_FLAG_EXTSCR_CLR_POS)) /*!< System Standby flag for CPU1 */
|
||||
#define PWR_FLAG_STOP (PWR_FLAG_REG_EXTSCR | PWR_EXTSCR_C1STOPF_Pos | (PWR_EXTSCR_C1CSSF_Pos << PWR_FLAG_EXTSCR_CLR_POS)) /*!< System Stop flag for CPU1 */
|
||||
|
||||
#define PWR_FLAG_C2SB (PWR_FLAG_REG_EXTSCR | PWR_EXTSCR_C2SBF_Pos | (PWR_EXTSCR_C2CSSF_Pos << PWR_FLAG_EXTSCR_CLR_POS)) /*!< System Standby flag for CPU2 */
|
||||
#define PWR_FLAG_C2STOP (PWR_FLAG_REG_EXTSCR | PWR_EXTSCR_C2STOPF_Pos | (PWR_EXTSCR_C2CSSF_Pos << PWR_FLAG_EXTSCR_CLR_POS)) /*!< System Stop flag for CPU2 */
|
||||
|
||||
#define PWR_FLAG_CRITICAL_RF_PHASE (PWR_FLAG_REG_EXTSCR | PWR_EXTSCR_CRPF_Pos | (PWR_EXTSCR_CCRPF_Pos << PWR_FLAG_EXTSCR_CLR_POS)) /*!< Critical radio system phase flag */
|
||||
#define PWR_FLAG_C1DEEPSLEEP (PWR_FLAG_REG_EXTSCR | PWR_EXTSCR_C1DS_Pos) /*!< CPU1 DeepSleep Flag */
|
||||
#define PWR_FLAG_C2DEEPSLEEP (PWR_FLAG_REG_EXTSCR | PWR_EXTSCR_C2DS_Pos) /*!< CPU2 DeepSleep Flag */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWREx_WakeUpTarget_Definition PWR Wakeup Target Definition
|
||||
* @{
|
||||
*/
|
||||
#define PWR_WAKEUPTARGET_CPU1 (0x00000001U)
|
||||
#define PWR_WAKEUPTARGET_CPU2 (0x00000002U)
|
||||
#define PWR_WAKEUPTARGET_ALL_CPU (PWR_WAKEUPTARGET_CPU1 | PWR_WAKEUPTARGET_CPU2)
|
||||
#define PWR_WAKEUPTARGET_RF (0x00000004U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWREx_Core_Select PWREx Core definition
|
||||
* @{
|
||||
*/
|
||||
#define PWR_CORE_CPU1 (0x00000000U)
|
||||
#define PWR_CORE_CPU2 (0x00000001U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/** @defgroup PWR_Private_Defines PWR Private Defines
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup PWREx_PVM_EXTI_LINE PWR PVM external interrupts lines
|
||||
* @{
|
||||
*/
|
||||
#if defined(PWR_CR2_PVME1)
|
||||
#define PWR_EXTI_LINE_PVM1 (LL_EXTI_LINE_31) /*!< External interrupt line 31 Connected to PVM1 */
|
||||
#endif
|
||||
#define PWR_EXTI_LINE_PVM3 (LL_EXTI_LINE_33) /*!< External interrupt line 33 Connected to PVM3 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_PVM_Mode_Mask PWR PVM Mode Mask
|
||||
* @{
|
||||
*/
|
||||
/* Note: On STM32WB serie, power PVD event is not available on AIEC lines */
|
||||
/* (only interruption is available through AIEC line 16). */
|
||||
#define PVM_MODE_IT (0x00010000U) /*!< Mask for interruption yielded by PVM threshold crossing */
|
||||
#define PVM_MODE_EVT (0x00020000U) /*!< Mask for event yielded by PVM threshold crossing */
|
||||
#define PVM_RISING_EDGE (0x00000001U) /*!< Mask for rising edge set as PVM trigger */
|
||||
#define PVM_FALLING_EDGE (0x00000002U) /*!< Mask for falling edge set as PVM trigger */
|
||||
#define PVM_RISING_FALLING_EDGE (0x00000003U) /*!< Mask for rising and falling edges set as PVM trigger */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_FLAG_REG PWR flag register
|
||||
* @{
|
||||
*/
|
||||
#define PWR_FLAG_REG_SR1 (0x20UL) /* Bitfield to indicate PWR flag located in register PWR_SR1 */
|
||||
#define PWR_FLAG_REG_SR2 (0x40UL) /* Bitfield to indicate PWR flag located in register PWR_SR2 */
|
||||
#define PWR_FLAG_REG_EXTSCR (0x60UL) /* Bitfield to indicate PWR flag located in register PWR_EXTSCR */
|
||||
#define PWR_FLAG_REG_MASK (PWR_FLAG_REG_SR1 | PWR_FLAG_REG_SR2 | PWR_FLAG_REG_EXTSCR) /* Bitfield mask to indicate PWR flag location in PWR register */
|
||||
#define PWR_FLAG_EXTSCR_CLR_POS (16UL) /* Bitfield for register PWR_EXTSCR clearable bits positions: position of bitfield in flag literals */
|
||||
#define PWR_FLAG_EXTSCR_CLR_MASK ((PWR_EXTSCR_C1CSSF_Pos | PWR_EXTSCR_C2CSSF_Pos | PWR_EXTSCR_CCRPF_Pos) << PWR_FLAG_EXTSCR_CLR_POS) /* Bitfield for register PWR_EXTSCR clearable bits positions: mask of bitfield in flag literals */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/** @defgroup PWREx_Exported_Macros PWR Extended Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined(PWR_CR2_PVME1)
|
||||
/**
|
||||
* @brief Enable the PVM1 Extended Interrupt C1 Line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVM1_EXTI_ENABLE_IT() LL_EXTI_EnableIT_0_31(PWR_EXTI_LINE_PVM1)
|
||||
|
||||
/**
|
||||
* @brief Enable the PVM1 Extended Interrupt C2 Line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVM1_EXTIC2_ENABLE_IT() LL_C2_EXTI_EnableIT_0_31(PWR_EXTI_LINE_PVM1)
|
||||
|
||||
/**
|
||||
* @brief Disable the PVM1 Extended Interrupt C1 Line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVM1_EXTI_DISABLE_IT() LL_EXTI_DisableIT_0_31(PWR_EXTI_LINE_PVM1)
|
||||
|
||||
/**
|
||||
* @brief Disable the PVM1 Extended Interrupt C2 Line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVM1_EXTIC2_DISABLE_IT() LL_C2_EXTI_DisableIT_0_31(PWR_EXTI_LINE_PVM1)
|
||||
|
||||
/**
|
||||
* @brief Enable the PVM1 Event C1 Line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVM1_EXTI_ENABLE_EVENT() LL_EXTI_EnableEvent_0_31(PWR_EXTI_LINE_PVM1)
|
||||
|
||||
/**
|
||||
* @brief Enable the PVM1 Event C2 Line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVM1_EXTIC2_ENABLE_EVENT() LL_C2_EXTI_EnableEvent_0_31(PWR_EXTI_LINE_PVM1)
|
||||
|
||||
/**
|
||||
* @brief Disable the PVM1 Event C1 Line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVM1_EXTI_DISABLE_EVENT() LL_EXTI_DisableEvent_0_31(PWR_EXTI_LINE_PVM1)
|
||||
|
||||
/**
|
||||
* @brief Disable the PVM1 Event C2 Line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVM1_EXTIC2_DISABLE_EVENT() LL_C2_EXTI_DisableEvent_0_31(PWR_EXTI_LINE_PVM1)
|
||||
|
||||
/**
|
||||
* @brief Enable the PVM1 Extended Interrupt Rising Trigger.
|
||||
* @note PVM1 flag polarity is inverted compared to EXTI line, therefore
|
||||
* EXTI rising and falling logic edges are inverted versus PVM1 voltage edges.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVM1_EXTI_ENABLE_RISING_EDGE() LL_EXTI_EnableRisingTrig_0_31(PWR_EXTI_LINE_PVM1)
|
||||
|
||||
/**
|
||||
* @brief Disable the PVM1 Extended Interrupt Rising Trigger.
|
||||
* @note PVM1 flag polarity is inverted compared to EXTI line, therefore
|
||||
* EXTI rising and falling logic edges are inverted versus PVM1 voltage edges.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVM1_EXTI_DISABLE_RISING_EDGE() LL_EXTI_DisableRisingTrig_0_31(PWR_EXTI_LINE_PVM1)
|
||||
|
||||
/**
|
||||
* @brief Enable the PVM1 Extended Interrupt Falling Trigger.
|
||||
* @note PVM1 flag polarity is inverted compared to EXTI line, therefore
|
||||
* EXTI rising and falling logic edges are inverted versus PVM1 voltage edges.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE() LL_EXTI_EnableFallingTrig_0_31(PWR_EXTI_LINE_PVM1)
|
||||
|
||||
|
||||
/**
|
||||
* @brief Disable the PVM1 Extended Interrupt Falling Trigger.
|
||||
* @note PVM1 flag polarity is inverted compared to EXTI line, therefore
|
||||
* EXTI rising and falling logic edges are inverted versus PVM1 voltage edges.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE() LL_EXTI_DisableFallingTrig_0_31(PWR_EXTI_LINE_PVM1)
|
||||
|
||||
/**
|
||||
* @brief PVM1 EXTI line configuration: set rising & falling edge trigger.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVM1_EXTI_ENABLE_RISING_FALLING_EDGE() \
|
||||
do { \
|
||||
__HAL_PWR_PVM1_EXTI_ENABLE_RISING_EDGE(); \
|
||||
__HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE(); \
|
||||
} while(0)
|
||||
|
||||
/**
|
||||
* @brief Disable the PVM1 Extended Interrupt Rising & Falling Trigger.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVM1_EXTI_DISABLE_RISING_FALLING_EDGE() \
|
||||
do { \
|
||||
__HAL_PWR_PVM1_EXTI_DISABLE_RISING_EDGE(); \
|
||||
__HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE(); \
|
||||
} while(0)
|
||||
|
||||
/**
|
||||
* @brief Generate a Software interrupt on selected EXTI line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVM1_EXTI_GENERATE_SWIT() LL_EXTI_GenerateSWI_0_31(PWR_EXTI_LINE_PVM1)
|
||||
|
||||
/**
|
||||
* @brief Check whether the specified PVM1 EXTI interrupt flag is set or not.
|
||||
* @retval EXTI PVM1 Line Status.
|
||||
*/
|
||||
#define __HAL_PWR_PVM1_EXTI_GET_FLAG() LL_EXTI_ReadFlag_0_31(PWR_EXTI_LINE_PVM1)
|
||||
|
||||
/**
|
||||
* @brief Clear the PVM1 EXTI flag.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVM1_EXTI_CLEAR_FLAG() LL_EXTI_ClearFlag_0_31(PWR_EXTI_LINE_PVM1)
|
||||
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enable the PVM3 Extended Interrupt C1 Line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVM3_EXTI_ENABLE_IT() LL_EXTI_EnableIT_32_63(PWR_EXTI_LINE_PVM3)
|
||||
|
||||
/**
|
||||
* @brief Enable the PVM3 Extended Interrupt C2 Line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVM3_EXTIC2_ENABLE_IT() LL_C2_EXTI_EnableIT_32_63(PWR_EXTI_LINE_PVM3)
|
||||
|
||||
/**
|
||||
* @brief Disable the PVM3 Extended Interrupt C1 Line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVM3_EXTI_DISABLE_IT() LL_EXTI_DisableIT_32_63(PWR_EXTI_LINE_PVM3)
|
||||
|
||||
/**
|
||||
* @brief Disable the PVM3 Extended Interrupt C2 Line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVM3_EXTIC2_DISABLE_IT() LL_C2_EXTI_DisableIT_32_63(PWR_EXTI_LINE_PVM3)
|
||||
|
||||
/**
|
||||
* @brief Enable the PVM3 Event C1 Line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVM3_EXTI_ENABLE_EVENT() LL_EXTI_EnableEvent_32_63(PWR_EXTI_LINE_PVM3)
|
||||
|
||||
/**
|
||||
* @brief Enable the PVM3 Event C2 Line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVM3_EXTIC2_ENABLE_EVENT() LL_C2_EXTI_EnableEvent_32_63(PWR_EXTI_LINE_PVM3)
|
||||
|
||||
/**
|
||||
* @brief Disable the PVM3 Event C1 Line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVM3_EXTI_DISABLE_EVENT() LL_EXTI_DisableEvent_32_63(PWR_EXTI_LINE_PVM3)
|
||||
|
||||
/**
|
||||
* @brief Disable the PVM3 Event C2 Line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVM3_EXTIC2_DISABLE_EVENT() LL_C2_EXTI_DisableEvent_32_63(PWR_EXTI_LINE_PVM3)
|
||||
|
||||
/**
|
||||
* @brief Enable the PVM3 Extended Interrupt Rising Trigger.
|
||||
* @note PVM3 flag polarity is inverted compared to EXTI line, therefore
|
||||
* EXTI rising and falling logic edges are inverted versus PVM3 voltage edges.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE() LL_EXTI_EnableRisingTrig_32_63(PWR_EXTI_LINE_PVM3)
|
||||
|
||||
/**
|
||||
* @brief Disable the PVM3 Extended Interrupt Rising Trigger.
|
||||
* @note PVM3 flag polarity is inverted compared to EXTI line, therefore
|
||||
* EXTI rising and falling logic edges are inverted versus PVM3 voltage edges.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE() LL_EXTI_DisableRisingTrig_32_63(PWR_EXTI_LINE_PVM3)
|
||||
|
||||
/**
|
||||
* @brief Enable the PVM3 Extended Interrupt Falling Trigger.
|
||||
* @note PVM3 flag polarity is inverted compared to EXTI line, therefore
|
||||
* EXTI rising and falling logic edges are inverted versus PVM3 voltage edges.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE() LL_EXTI_EnableFallingTrig_32_63(PWR_EXTI_LINE_PVM3)
|
||||
|
||||
|
||||
/**
|
||||
* @brief Disable the PVM3 Extended Interrupt Falling Trigger.
|
||||
* @note PVM3 flag polarity is inverted compared to EXTI line, therefore
|
||||
* EXTI rising and falling logic edges are inverted versus PVM3 voltage edges.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE() LL_EXTI_DisableFallingTrig_32_63(PWR_EXTI_LINE_PVM3)
|
||||
|
||||
/**
|
||||
* @brief PVM3 EXTI line configuration: set rising & falling edge trigger.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVM3_EXTI_ENABLE_RISING_FALLING_EDGE() \
|
||||
do { \
|
||||
__HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE(); \
|
||||
__HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE(); \
|
||||
} while(0)
|
||||
|
||||
/**
|
||||
* @brief Disable the PVM3 Extended Interrupt Rising & Falling Trigger.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVM3_EXTI_DISABLE_RISING_FALLING_EDGE() \
|
||||
do { \
|
||||
__HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE(); \
|
||||
__HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE(); \
|
||||
} while(0)
|
||||
|
||||
/**
|
||||
* @brief Generate a Software interrupt on selected EXTI line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVM3_EXTI_GENERATE_SWIT() LL_EXTI_GenerateSWI_32_63(PWR_EXTI_LINE_PVM3)
|
||||
|
||||
/**
|
||||
* @brief Check whether the specified PVM3 EXTI interrupt flag is set or not.
|
||||
* @retval EXTI PVM3 Line Status.
|
||||
*/
|
||||
#define __HAL_PWR_PVM3_EXTI_GET_FLAG() LL_EXTI_ReadFlag_32_63(PWR_EXTI_LINE_PVM3)
|
||||
|
||||
/**
|
||||
* @brief Clear the PVM3 EXTI flag.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVM3_EXTI_CLEAR_FLAG() LL_EXTI_ClearFlag_32_63(PWR_EXTI_LINE_PVM3)
|
||||
|
||||
#if defined(PWR_CR1_VOS)
|
||||
/**
|
||||
* @brief Configure the main internal regulator output voltage.
|
||||
* @param __REGULATOR__ specifies the regulator output voltage to achieve
|
||||
* a tradeoff between performance and power consumption.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref PWR_REGULATOR_VOLTAGE_SCALE1 Regulator voltage output range 1 mode,
|
||||
* typical output voltage at 1.2 V,
|
||||
* system frequency up to 64 MHz.
|
||||
* @arg @ref PWR_REGULATOR_VOLTAGE_SCALE2 Regulator voltage output range 2 mode,
|
||||
* typical output voltage at 1.0 V,
|
||||
* system frequency up to 16 MHz.
|
||||
* @note This macro is similar to HAL_PWREx_ControlVoltageScaling() API but doesn't check
|
||||
* whether or not VOSF flag is cleared when moving from range 2 to range 1. User
|
||||
* may resort to __HAL_PWR_GET_FLAG() macro to check VOSF bit resetting.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
MODIFY_REG(PWR->CR1, PWR_CR1_VOS, (__REGULATOR__)); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(PWR->CR1, PWR_CR1_VOS); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0)
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Wakeup BLE controller from its sleep mode
|
||||
* @note This bit is automatically reset when 802.15.4 controller
|
||||
* exit its sleep mode.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_C2_PWR_WAKEUP_BLE() LL_C2_PWR_WakeUp_BLE()
|
||||
|
||||
/**
|
||||
* @brief Wakeup 802.15.4 controller from its sleep mode
|
||||
* @note This bit is automatically reset when 802.15.4 controller
|
||||
* exit its sleep mode.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_C2_PWR_WAKEUP_802_15_4() LL_C2_PWR_WakeUp_802_15_4()
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros --------------------------------------------------------*/
|
||||
/** @addtogroup PWREx_Private_Macros PWR Extended Private Macros
|
||||
* @{
|
||||
*/
|
||||
#if defined(PWR_CR3_EWUP2)
|
||||
#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1_HIGH) || \
|
||||
((PIN) == PWR_WAKEUP_PIN2_HIGH) || \
|
||||
((PIN) == PWR_WAKEUP_PIN3_HIGH) || \
|
||||
((PIN) == PWR_WAKEUP_PIN4_HIGH) || \
|
||||
((PIN) == PWR_WAKEUP_PIN5_HIGH) || \
|
||||
((PIN) == PWR_WAKEUP_PIN1_LOW) || \
|
||||
((PIN) == PWR_WAKEUP_PIN2_LOW) || \
|
||||
((PIN) == PWR_WAKEUP_PIN3_LOW) || \
|
||||
((PIN) == PWR_WAKEUP_PIN4_LOW) || \
|
||||
((PIN) == PWR_WAKEUP_PIN5_LOW))
|
||||
#else
|
||||
#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1_HIGH) || \
|
||||
((PIN) == PWR_WAKEUP_PIN4_HIGH) || \
|
||||
((PIN) == PWR_WAKEUP_PIN1_LOW) || \
|
||||
((PIN) == PWR_WAKEUP_PIN4_LOW))
|
||||
#endif
|
||||
|
||||
#define IS_PWR_WAKEUP_PIN_POLARITY(POLARITY) (((POLARITY) == PWR_PIN_POLARITY_HIGH) || \
|
||||
((POLARITY) == PWR_PIN_POLARITY_LOW))
|
||||
|
||||
#if defined(PWR_CR2_PVME1)
|
||||
#define IS_PWR_PVM_TYPE(TYPE) (((TYPE) == PWR_PVM_1) ||\
|
||||
((TYPE) == PWR_PVM_3))
|
||||
#else
|
||||
#define IS_PWR_PVM_TYPE(TYPE) ((TYPE) == PWR_PVM_3)
|
||||
#endif
|
||||
|
||||
#define IS_PWR_PVM_MODE(MODE) (((MODE) == PWR_PVM_MODE_NORMAL) ||\
|
||||
((MODE) == PWR_PVM_MODE_IT_RISING) ||\
|
||||
((MODE) == PWR_PVM_MODE_IT_FALLING) ||\
|
||||
((MODE) == PWR_PVM_MODE_IT_RISING_FALLING) ||\
|
||||
((MODE) == PWR_PVM_MODE_EVENT_RISING) ||\
|
||||
((MODE) == PWR_PVM_MODE_EVENT_FALLING) ||\
|
||||
((MODE) == PWR_PVM_MODE_EVENT_RISING_FALLING))
|
||||
|
||||
#define IS_PWR_FLASH_POWERDOWN(__MODE__) ((((__MODE__) & (PWR_FLASHPD_LPRUN | PWR_FLASHPD_LPSLEEP)) != 0x00u) && \
|
||||
(((__MODE__) & ~(PWR_FLASHPD_LPRUN | PWR_FLASHPD_LPSLEEP)) == 0x00u))
|
||||
|
||||
#if defined(PWR_CR1_VOS)
|
||||
#define IS_PWR_VOLTAGE_SCALING_RANGE(RANGE) (((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \
|
||||
((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE2))
|
||||
#endif
|
||||
|
||||
#define IS_PWR_BATTERY_RESISTOR_SELECT(RESISTOR) (((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_5) ||\
|
||||
((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_1_5))
|
||||
|
||||
#define IS_PWR_BATTERY_CHARGING(CHARGING) (((CHARGING) == PWR_BATTERY_CHARGING_DISABLE) ||\
|
||||
((CHARGING) == PWR_BATTERY_CHARGING_ENABLE))
|
||||
|
||||
|
||||
#define IS_PWR_GPIO_BIT_NUMBER(BIT_NUMBER) (((BIT_NUMBER) & GPIO_PIN_MASK) != (uint32_t)0x00)
|
||||
|
||||
#if defined(GPIOD)
|
||||
#define IS_PWR_GPIO(GPIO) (((GPIO) == PWR_GPIO_A) ||\
|
||||
((GPIO) == PWR_GPIO_B) ||\
|
||||
((GPIO) == PWR_GPIO_C) ||\
|
||||
((GPIO) == PWR_GPIO_D) ||\
|
||||
((GPIO) == PWR_GPIO_E) ||\
|
||||
((GPIO) == PWR_GPIO_H))
|
||||
#else
|
||||
#define IS_PWR_GPIO(GPIO) (((GPIO) == PWR_GPIO_A) ||\
|
||||
((GPIO) == PWR_GPIO_B) ||\
|
||||
((GPIO) == PWR_GPIO_C) ||\
|
||||
((GPIO) == PWR_GPIO_E) ||\
|
||||
((GPIO) == PWR_GPIO_H))
|
||||
#endif
|
||||
|
||||
#if defined(PWR_CR5_SMPSEN)
|
||||
#define IS_PWR_SMPS_MODE(SMPS_MODE) (((SMPS_MODE) == PWR_SMPS_BYPASS) ||\
|
||||
((SMPS_MODE) == PWR_SMPS_STEP_DOWN))
|
||||
|
||||
#define IS_PWR_SMPS_STARTUP_CURRENT(SMPS_STARTUP_CURRENT) (((SMPS_STARTUP_CURRENT) == PWR_SMPS_STARTUP_CURRENT_80MA) ||\
|
||||
((SMPS_STARTUP_CURRENT) == PWR_SMPS_STARTUP_CURRENT_100MA) ||\
|
||||
((SMPS_STARTUP_CURRENT) == PWR_SMPS_STARTUP_CURRENT_120MA) ||\
|
||||
((SMPS_STARTUP_CURRENT) == PWR_SMPS_STARTUP_CURRENT_140MA) ||\
|
||||
((SMPS_STARTUP_CURRENT) == PWR_SMPS_STARTUP_CURRENT_160MA) ||\
|
||||
((SMPS_STARTUP_CURRENT) == PWR_SMPS_STARTUP_CURRENT_180MA) ||\
|
||||
((SMPS_STARTUP_CURRENT) == PWR_SMPS_STARTUP_CURRENT_200MA) ||\
|
||||
((SMPS_STARTUP_CURRENT) == PWR_SMPS_STARTUP_CURRENT_220MA))
|
||||
|
||||
#define IS_PWR_SMPS_OUTPUT_VOLTAGE(SMPS_OUTPUT_VOLTAGE) (((SMPS_OUTPUT_VOLTAGE) == PWR_SMPS_OUTPUT_VOLTAGE_1V20) ||\
|
||||
((SMPS_OUTPUT_VOLTAGE) == PWR_SMPS_OUTPUT_VOLTAGE_1V25) ||\
|
||||
((SMPS_OUTPUT_VOLTAGE) == PWR_SMPS_OUTPUT_VOLTAGE_1V30) ||\
|
||||
((SMPS_OUTPUT_VOLTAGE) == PWR_SMPS_OUTPUT_VOLTAGE_1V35) ||\
|
||||
((SMPS_OUTPUT_VOLTAGE) == PWR_SMPS_OUTPUT_VOLTAGE_1V40) ||\
|
||||
((SMPS_OUTPUT_VOLTAGE) == PWR_SMPS_OUTPUT_VOLTAGE_1V45) ||\
|
||||
((SMPS_OUTPUT_VOLTAGE) == PWR_SMPS_OUTPUT_VOLTAGE_1V50) ||\
|
||||
((SMPS_OUTPUT_VOLTAGE) == PWR_SMPS_OUTPUT_VOLTAGE_1V55) ||\
|
||||
((SMPS_OUTPUT_VOLTAGE) == PWR_SMPS_OUTPUT_VOLTAGE_1V60) ||\
|
||||
((SMPS_OUTPUT_VOLTAGE) == PWR_SMPS_OUTPUT_VOLTAGE_1V65) ||\
|
||||
((SMPS_OUTPUT_VOLTAGE) == PWR_SMPS_OUTPUT_VOLTAGE_1V70) ||\
|
||||
((SMPS_OUTPUT_VOLTAGE) == PWR_SMPS_OUTPUT_VOLTAGE_1V75) ||\
|
||||
((SMPS_OUTPUT_VOLTAGE) == PWR_SMPS_OUTPUT_VOLTAGE_1V80) ||\
|
||||
((SMPS_OUTPUT_VOLTAGE) == PWR_SMPS_OUTPUT_VOLTAGE_1V85) ||\
|
||||
((SMPS_OUTPUT_VOLTAGE) == PWR_SMPS_OUTPUT_VOLTAGE_1V90))
|
||||
#endif
|
||||
|
||||
#define IS_PWR_CORE(CPU) (((CPU) == PWR_CORE_CPU1) || ((CPU) == PWR_CORE_CPU2))
|
||||
|
||||
#define IS_PWR_CORE_HOLD_RELEASE(CPU) ((CPU) == PWR_CORE_CPU2)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @addtogroup PWREx_Exported_Functions PWR Extended Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup PWREx_Exported_Functions_Group1 Extended Peripheral Control functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Peripheral Control functions **********************************************/
|
||||
uint32_t HAL_PWREx_GetVoltageRange(void);
|
||||
HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling);
|
||||
|
||||
void HAL_PWREx_EnableBatteryCharging(uint32_t ResistorSelection);
|
||||
void HAL_PWREx_DisableBatteryCharging(void);
|
||||
|
||||
void HAL_PWREx_EnableVddUSB(void);
|
||||
void HAL_PWREx_DisableVddUSB(void);
|
||||
|
||||
void HAL_PWREx_EnableInternalWakeUpLine(void);
|
||||
void HAL_PWREx_DisableInternalWakeUpLine(void);
|
||||
|
||||
#if defined(PWR_CR5_SMPSEN)
|
||||
void HAL_PWREx_EnableBORH_SMPSBypassIT(void);
|
||||
void HAL_PWREx_DisableBORH_SMPSBypassIT(void);
|
||||
#endif
|
||||
void HAL_PWREx_EnableRFPhaseIT(void);
|
||||
void HAL_PWREx_DisableRFPhaseIT(void);
|
||||
void HAL_PWREx_EnableBLEActivityIT(void);
|
||||
void HAL_PWREx_DisableBLEActivityIT(void);
|
||||
void HAL_PWREx_Enable802ActivityIT(void);
|
||||
void HAL_PWREx_Disable802ActivityIT(void);
|
||||
void HAL_PWREx_EnableHOLDC2IT(void);
|
||||
void HAL_PWREx_DisableHOLDC2IT(void);
|
||||
|
||||
void HAL_PWREx_HoldCore(uint32_t CPU);
|
||||
void HAL_PWREx_ReleaseCore(uint32_t CPU);
|
||||
|
||||
HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber);
|
||||
HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber);
|
||||
HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber);
|
||||
HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber);
|
||||
void HAL_PWREx_EnablePullUpPullDownConfig(void);
|
||||
void HAL_PWREx_DisablePullUpPullDownConfig(void);
|
||||
|
||||
#if defined(PWR_CR5_SMPSEN)
|
||||
void HAL_PWREx_SetBORConfig(uint32_t BORConfiguration);
|
||||
uint32_t HAL_PWREx_GetBORConfig(void);
|
||||
#endif
|
||||
|
||||
void HAL_PWREx_EnableSRAMRetention(void);
|
||||
void HAL_PWREx_DisableSRAMRetention(void);
|
||||
|
||||
void HAL_PWREx_EnableFlashPowerDown(uint32_t PowerMode);
|
||||
void HAL_PWREx_DisableFlashPowerDown(uint32_t PowerMode);
|
||||
|
||||
#if defined(PWR_CR2_PVME1)
|
||||
void HAL_PWREx_EnablePVM1(void);
|
||||
void HAL_PWREx_DisablePVM1(void);
|
||||
#endif
|
||||
|
||||
void HAL_PWREx_EnablePVM3(void);
|
||||
void HAL_PWREx_DisablePVM3(void);
|
||||
|
||||
HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *sConfigPVM);
|
||||
|
||||
#if defined(PWR_CR5_SMPSEN)
|
||||
HAL_StatusTypeDef HAL_PWREx_ConfigSMPS(PWR_SMPSTypeDef *sConfigSMPS);
|
||||
void HAL_PWREx_SMPS_SetMode(uint32_t OperatingMode);
|
||||
uint32_t HAL_PWREx_SMPS_GetEffectiveMode(void);
|
||||
#endif
|
||||
|
||||
/* WakeUp pins configuration functions ****************************************/
|
||||
void HAL_PWREx_EnableWakeUpPin(uint32_t WakeUpPinPolarity, uint32_t wakeupTarget);
|
||||
uint32_t HAL_PWREx_GetWakeupFlag(uint32_t WakeUpFlag);
|
||||
HAL_StatusTypeDef HAL_PWREx_ClearWakeupFlag(uint32_t WakeUpFlag);
|
||||
|
||||
/* Low Power modes configuration functions ************************************/
|
||||
void HAL_PWREx_EnableLowPowerRunMode(void);
|
||||
HAL_StatusTypeDef HAL_PWREx_DisableLowPowerRunMode(void);
|
||||
|
||||
void HAL_PWREx_EnterSTOP0Mode(uint8_t STOPEntry);
|
||||
void HAL_PWREx_EnterSTOP1Mode(uint8_t STOPEntry);
|
||||
#if defined(PWR_SUPPORT_STOP2)
|
||||
void HAL_PWREx_EnterSTOP2Mode(uint8_t STOPEntry);
|
||||
#endif
|
||||
void HAL_PWREx_EnterSHUTDOWNMode(void);
|
||||
|
||||
void HAL_PWREx_PVD_PVM_IRQHandler(void);
|
||||
|
||||
#if defined(PWR_CR2_PVME1)
|
||||
void HAL_PWREx_PVM1Callback(void);
|
||||
#endif
|
||||
void HAL_PWREx_PVM3Callback(void);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* STM32WBxx_HAL_PWR_EX_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -1,709 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32wbxx_hal_qspi.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of QSPI HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32WBxx_HAL_QSPI_H
|
||||
#define STM32WBxx_HAL_QSPI_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32wbxx_hal_def.h"
|
||||
|
||||
#if defined(QUADSPI)
|
||||
|
||||
/** @addtogroup STM32WBxx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup QSPI
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup QSPI_Exported_Types QSPI Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief QSPI Init structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t ClockPrescaler; /* Specifies the prescaler factor for generating clock based on the AHB clock.
|
||||
This parameter can be a number between 0 and 255 */
|
||||
uint32_t FifoThreshold; /* Specifies the threshold number of bytes in the FIFO (used only in indirect mode)
|
||||
This parameter can be a value between 1 and 16 */
|
||||
uint32_t SampleShifting; /* Specifies the Sample Shift. The data is sampled 1/2 clock cycle delay later to
|
||||
take in account external signal delays. (It should be QSPI_SAMPLE_SHIFTING_NONE in DDR mode)
|
||||
This parameter can be a value of @ref QSPI_SampleShifting */
|
||||
uint32_t FlashSize; /* Specifies the Flash Size. FlashSize+1 is effectively the number of address bits
|
||||
required to address the flash memory. The flash capacity can be up to 4GB
|
||||
(addressed using 32 bits) in indirect mode, but the addressable space in
|
||||
memory-mapped mode is limited to 256MB
|
||||
This parameter can be a number between 0 and 31 */
|
||||
uint32_t ChipSelectHighTime; /* Specifies the Chip Select High Time. ChipSelectHighTime+1 defines the minimum number
|
||||
of clock cycles which the chip select must remain high between commands.
|
||||
This parameter can be a value of @ref QSPI_ChipSelectHighTime */
|
||||
uint32_t ClockMode; /* Specifies the Clock Mode. It indicates the level that clock takes between commands.
|
||||
This parameter can be a value of @ref QSPI_ClockMode */
|
||||
}QSPI_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL QSPI State structures definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_QSPI_STATE_RESET = 0x00U, /*!< Peripheral not initialized */
|
||||
HAL_QSPI_STATE_READY = 0x01U, /*!< Peripheral initialized and ready for use */
|
||||
HAL_QSPI_STATE_BUSY = 0x02U, /*!< Peripheral in indirect mode and busy */
|
||||
HAL_QSPI_STATE_BUSY_INDIRECT_TX = 0x12U, /*!< Peripheral in indirect mode with transmission ongoing */
|
||||
HAL_QSPI_STATE_BUSY_INDIRECT_RX = 0x22U, /*!< Peripheral in indirect mode with reception ongoing */
|
||||
HAL_QSPI_STATE_BUSY_AUTO_POLLING = 0x42U, /*!< Peripheral in auto polling mode ongoing */
|
||||
HAL_QSPI_STATE_BUSY_MEM_MAPPED = 0x82U, /*!< Peripheral in memory mapped mode ongoing */
|
||||
HAL_QSPI_STATE_ABORT = 0x08U, /*!< Peripheral with abort request ongoing */
|
||||
HAL_QSPI_STATE_ERROR = 0x04U /*!< Peripheral in error */
|
||||
}HAL_QSPI_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief QSPI Handle Structure definition
|
||||
*/
|
||||
#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
|
||||
typedef struct __QSPI_HandleTypeDef
|
||||
#else
|
||||
typedef struct
|
||||
#endif
|
||||
{
|
||||
QUADSPI_TypeDef *Instance; /* QSPI registers base address */
|
||||
QSPI_InitTypeDef Init; /* QSPI communication parameters */
|
||||
uint8_t *pTxBuffPtr; /* Pointer to QSPI Tx transfer Buffer */
|
||||
__IO uint32_t TxXferSize; /* QSPI Tx Transfer size */
|
||||
__IO uint32_t TxXferCount; /* QSPI Tx Transfer Counter */
|
||||
uint8_t *pRxBuffPtr; /* Pointer to QSPI Rx transfer Buffer */
|
||||
__IO uint32_t RxXferSize; /* QSPI Rx Transfer size */
|
||||
__IO uint32_t RxXferCount; /* QSPI Rx Transfer Counter */
|
||||
DMA_HandleTypeDef *hdma; /* QSPI Rx/Tx DMA Handle parameters */
|
||||
__IO HAL_LockTypeDef Lock; /* Locking object */
|
||||
__IO HAL_QSPI_StateTypeDef State; /* QSPI communication state */
|
||||
__IO uint32_t ErrorCode; /* QSPI Error code */
|
||||
uint32_t Timeout; /* Timeout for the QSPI memory access */
|
||||
#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
|
||||
void (* ErrorCallback) (struct __QSPI_HandleTypeDef *hqspi);
|
||||
void (* AbortCpltCallback) (struct __QSPI_HandleTypeDef *hqspi);
|
||||
void (* FifoThresholdCallback)(struct __QSPI_HandleTypeDef *hqspi);
|
||||
void (* CmdCpltCallback) (struct __QSPI_HandleTypeDef *hqspi);
|
||||
void (* RxCpltCallback) (struct __QSPI_HandleTypeDef *hqspi);
|
||||
void (* TxCpltCallback) (struct __QSPI_HandleTypeDef *hqspi);
|
||||
void (* RxHalfCpltCallback) (struct __QSPI_HandleTypeDef *hqspi);
|
||||
void (* TxHalfCpltCallback) (struct __QSPI_HandleTypeDef *hqspi);
|
||||
void (* StatusMatchCallback) (struct __QSPI_HandleTypeDef *hqspi);
|
||||
void (* TimeOutCallback) (struct __QSPI_HandleTypeDef *hqspi);
|
||||
|
||||
void (* MspInitCallback) (struct __QSPI_HandleTypeDef *hqspi);
|
||||
void (* MspDeInitCallback) (struct __QSPI_HandleTypeDef *hqspi);
|
||||
#endif
|
||||
}QSPI_HandleTypeDef;
|
||||
|
||||
/**
|
||||
* @brief QSPI Command structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Instruction; /* Specifies the Instruction to be sent
|
||||
This parameter can be a value (8-bit) between 0x00 and 0xFF */
|
||||
uint32_t Address; /* Specifies the Address to be sent (Size from 1 to 4 bytes according AddressSize)
|
||||
This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFF */
|
||||
uint32_t AlternateBytes; /* Specifies the Alternate Bytes to be sent (Size from 1 to 4 bytes according AlternateBytesSize)
|
||||
This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFF */
|
||||
uint32_t AddressSize; /* Specifies the Address Size
|
||||
This parameter can be a value of @ref QSPI_AddressSize */
|
||||
uint32_t AlternateBytesSize; /* Specifies the Alternate Bytes Size
|
||||
This parameter can be a value of @ref QSPI_AlternateBytesSize */
|
||||
uint32_t DummyCycles; /* Specifies the Number of Dummy Cycles.
|
||||
This parameter can be a number between 0 and 31 */
|
||||
uint32_t InstructionMode; /* Specifies the Instruction Mode
|
||||
This parameter can be a value of @ref QSPI_InstructionMode */
|
||||
uint32_t AddressMode; /* Specifies the Address Mode
|
||||
This parameter can be a value of @ref QSPI_AddressMode */
|
||||
uint32_t AlternateByteMode; /* Specifies the Alternate Bytes Mode
|
||||
This parameter can be a value of @ref QSPI_AlternateBytesMode */
|
||||
uint32_t DataMode; /* Specifies the Data Mode (used for dummy cycles and data phases)
|
||||
This parameter can be a value of @ref QSPI_DataMode */
|
||||
uint32_t NbData; /* Specifies the number of data to transfer. (This is the number of bytes)
|
||||
This parameter can be any value between 0 and 0xFFFFFFFF (0 means undefined length
|
||||
until end of memory)*/
|
||||
uint32_t DdrMode; /* Specifies the double data rate mode for address, alternate byte and data phase
|
||||
This parameter can be a value of @ref QSPI_DdrMode */
|
||||
uint32_t SIOOMode; /* Specifies the send instruction only once mode
|
||||
This parameter can be a value of @ref QSPI_SIOOMode */
|
||||
}QSPI_CommandTypeDef;
|
||||
|
||||
/**
|
||||
* @brief QSPI Auto Polling mode configuration structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Match; /* Specifies the value to be compared with the masked status register to get a match.
|
||||
This parameter can be any value between 0 and 0xFFFFFFFF */
|
||||
uint32_t Mask; /* Specifies the mask to be applied to the status bytes received.
|
||||
This parameter can be any value between 0 and 0xFFFFFFFF */
|
||||
uint32_t Interval; /* Specifies the number of clock cycles between two read during automatic polling phases.
|
||||
This parameter can be any value between 0 and 0xFFFF */
|
||||
uint32_t StatusBytesSize; /* Specifies the size of the status bytes received.
|
||||
This parameter can be any value between 1 and 4 */
|
||||
uint32_t MatchMode; /* Specifies the method used for determining a match.
|
||||
This parameter can be a value of @ref QSPI_MatchMode */
|
||||
uint32_t AutomaticStop; /* Specifies if automatic polling is stopped after a match.
|
||||
This parameter can be a value of @ref QSPI_AutomaticStop */
|
||||
}QSPI_AutoPollingTypeDef;
|
||||
|
||||
/**
|
||||
* @brief QSPI Memory Mapped mode configuration structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t TimeOutPeriod; /* Specifies the number of clock to wait when the FIFO is full before to release the chip select.
|
||||
This parameter can be any value between 0 and 0xFFFF */
|
||||
uint32_t TimeOutActivation; /* Specifies if the timeout counter is enabled to release the chip select.
|
||||
This parameter can be a value of @ref QSPI_TimeOutActivation */
|
||||
}QSPI_MemoryMappedTypeDef;
|
||||
|
||||
#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
|
||||
/**
|
||||
* @brief HAL QSPI Callback ID enumeration definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_QSPI_ERROR_CB_ID = 0x00U, /*!< QSPI Error Callback ID */
|
||||
HAL_QSPI_ABORT_CB_ID = 0x01U, /*!< QSPI Abort Callback ID */
|
||||
HAL_QSPI_FIFO_THRESHOLD_CB_ID = 0x02U, /*!< QSPI FIFO Threshold Callback ID */
|
||||
HAL_QSPI_CMD_CPLT_CB_ID = 0x03U, /*!< QSPI Command Complete Callback ID */
|
||||
HAL_QSPI_RX_CPLT_CB_ID = 0x04U, /*!< QSPI Rx Complete Callback ID */
|
||||
HAL_QSPI_TX_CPLT_CB_ID = 0x05U, /*!< QSPI Tx Complete Callback ID */
|
||||
HAL_QSPI_RX_HALF_CPLT_CB_ID = 0x06U, /*!< QSPI Rx Half Complete Callback ID */
|
||||
HAL_QSPI_TX_HALF_CPLT_CB_ID = 0x07U, /*!< QSPI Tx Half Complete Callback ID */
|
||||
HAL_QSPI_STATUS_MATCH_CB_ID = 0x08U, /*!< QSPI Status Match Callback ID */
|
||||
HAL_QSPI_TIMEOUT_CB_ID = 0x09U, /*!< QSPI Timeout Callback ID */
|
||||
|
||||
HAL_QSPI_MSP_INIT_CB_ID = 0x0AU, /*!< QSPI MspInit Callback ID */
|
||||
HAL_QSPI_MSP_DEINIT_CB_ID = 0x0B0 /*!< QSPI MspDeInit Callback ID */
|
||||
}HAL_QSPI_CallbackIDTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL QSPI Callback pointer definition
|
||||
*/
|
||||
typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi);
|
||||
#endif
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup QSPI_Exported_Constants QSPI Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup QSPI_ErrorCode QSPI Error Code
|
||||
* @{
|
||||
*/
|
||||
#define HAL_QSPI_ERROR_NONE 0x00000000U /*!< No error */
|
||||
#define HAL_QSPI_ERROR_TIMEOUT 0x00000001U /*!< Timeout error */
|
||||
#define HAL_QSPI_ERROR_TRANSFER 0x00000002U /*!< Transfer error */
|
||||
#define HAL_QSPI_ERROR_DMA 0x00000004U /*!< DMA transfer error */
|
||||
#define HAL_QSPI_ERROR_INVALID_PARAM 0x00000008U /*!< Invalid parameters error */
|
||||
#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
|
||||
#define HAL_QSPI_ERROR_INVALID_CALLBACK 0x00000010U /*!< Invalid callback error */
|
||||
#endif
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup QSPI_SampleShifting QSPI Sample Shifting
|
||||
* @{
|
||||
*/
|
||||
#define QSPI_SAMPLE_SHIFTING_NONE 0x00000000U /*!<No clock cycle shift to sample data*/
|
||||
#define QSPI_SAMPLE_SHIFTING_HALFCYCLE ((uint32_t)QUADSPI_CR_SSHIFT) /*!<1/2 clock cycle shift to sample data*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup QSPI_ChipSelectHighTime QSPI ChipSelect High Time
|
||||
* @{
|
||||
*/
|
||||
#define QSPI_CS_HIGH_TIME_1_CYCLE 0x00000000U /*!<nCS stay high for at least 1 clock cycle between commands*/
|
||||
#define QSPI_CS_HIGH_TIME_2_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0) /*!<nCS stay high for at least 2 clock cycles between commands*/
|
||||
#define QSPI_CS_HIGH_TIME_3_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 3 clock cycles between commands*/
|
||||
#define QSPI_CS_HIGH_TIME_4_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0 | QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 4 clock cycles between commands*/
|
||||
#define QSPI_CS_HIGH_TIME_5_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2) /*!<nCS stay high for at least 5 clock cycles between commands*/
|
||||
#define QSPI_CS_HIGH_TIME_6_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_0) /*!<nCS stay high for at least 6 clock cycles between commands*/
|
||||
#define QSPI_CS_HIGH_TIME_7_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 7 clock cycles between commands*/
|
||||
#define QSPI_CS_HIGH_TIME_8_CYCLE ((uint32_t)QUADSPI_DCR_CSHT) /*!<nCS stay high for at least 8 clock cycles between commands*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup QSPI_ClockMode QSPI Clock Mode
|
||||
* @{
|
||||
*/
|
||||
#define QSPI_CLOCK_MODE_0 0x00000000U /*!<Clk stays low while nCS is released*/
|
||||
#define QSPI_CLOCK_MODE_3 ((uint32_t)QUADSPI_DCR_CKMODE) /*!<Clk goes high while nCS is released*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup QSPI_AddressSize QSPI Address Size
|
||||
* @{
|
||||
*/
|
||||
#define QSPI_ADDRESS_8_BITS 0x00000000U /*!<8-bit address*/
|
||||
#define QSPI_ADDRESS_16_BITS ((uint32_t)QUADSPI_CCR_ADSIZE_0) /*!<16-bit address*/
|
||||
#define QSPI_ADDRESS_24_BITS ((uint32_t)QUADSPI_CCR_ADSIZE_1) /*!<24-bit address*/
|
||||
#define QSPI_ADDRESS_32_BITS ((uint32_t)QUADSPI_CCR_ADSIZE) /*!<32-bit address*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup QSPI_AlternateBytesSize QSPI Alternate Bytes Size
|
||||
* @{
|
||||
*/
|
||||
#define QSPI_ALTERNATE_BYTES_8_BITS 0x00000000U /*!<8-bit alternate bytes*/
|
||||
#define QSPI_ALTERNATE_BYTES_16_BITS ((uint32_t)QUADSPI_CCR_ABSIZE_0) /*!<16-bit alternate bytes*/
|
||||
#define QSPI_ALTERNATE_BYTES_24_BITS ((uint32_t)QUADSPI_CCR_ABSIZE_1) /*!<24-bit alternate bytes*/
|
||||
#define QSPI_ALTERNATE_BYTES_32_BITS ((uint32_t)QUADSPI_CCR_ABSIZE) /*!<32-bit alternate bytes*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup QSPI_InstructionMode QSPI Instruction Mode
|
||||
* @{
|
||||
*/
|
||||
#define QSPI_INSTRUCTION_NONE 0x00000000U /*!<No instruction*/
|
||||
#define QSPI_INSTRUCTION_1_LINE ((uint32_t)QUADSPI_CCR_IMODE_0) /*!<Instruction on a single line*/
|
||||
#define QSPI_INSTRUCTION_2_LINES ((uint32_t)QUADSPI_CCR_IMODE_1) /*!<Instruction on two lines*/
|
||||
#define QSPI_INSTRUCTION_4_LINES ((uint32_t)QUADSPI_CCR_IMODE) /*!<Instruction on four lines*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup QSPI_AddressMode QSPI Address Mode
|
||||
* @{
|
||||
*/
|
||||
#define QSPI_ADDRESS_NONE 0x00000000U /*!<No address*/
|
||||
#define QSPI_ADDRESS_1_LINE ((uint32_t)QUADSPI_CCR_ADMODE_0) /*!<Address on a single line*/
|
||||
#define QSPI_ADDRESS_2_LINES ((uint32_t)QUADSPI_CCR_ADMODE_1) /*!<Address on two lines*/
|
||||
#define QSPI_ADDRESS_4_LINES ((uint32_t)QUADSPI_CCR_ADMODE) /*!<Address on four lines*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup QSPI_AlternateBytesMode QSPI Alternate Bytes Mode
|
||||
* @{
|
||||
*/
|
||||
#define QSPI_ALTERNATE_BYTES_NONE 0x00000000U /*!<No alternate bytes*/
|
||||
#define QSPI_ALTERNATE_BYTES_1_LINE ((uint32_t)QUADSPI_CCR_ABMODE_0) /*!<Alternate bytes on a single line*/
|
||||
#define QSPI_ALTERNATE_BYTES_2_LINES ((uint32_t)QUADSPI_CCR_ABMODE_1) /*!<Alternate bytes on two lines*/
|
||||
#define QSPI_ALTERNATE_BYTES_4_LINES ((uint32_t)QUADSPI_CCR_ABMODE) /*!<Alternate bytes on four lines*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup QSPI_DataMode QSPI Data Mode
|
||||
* @{
|
||||
*/
|
||||
#define QSPI_DATA_NONE 0x00000000U /*!<No data*/
|
||||
#define QSPI_DATA_1_LINE ((uint32_t)QUADSPI_CCR_DMODE_0) /*!<Data on a single line*/
|
||||
#define QSPI_DATA_2_LINES ((uint32_t)QUADSPI_CCR_DMODE_1) /*!<Data on two lines*/
|
||||
#define QSPI_DATA_4_LINES ((uint32_t)QUADSPI_CCR_DMODE) /*!<Data on four lines*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup QSPI_DdrMode QSPI DDR Mode
|
||||
* @{
|
||||
*/
|
||||
#define QSPI_DDR_MODE_DISABLE 0x00000000U /*!<Double data rate mode disabled*/
|
||||
#define QSPI_DDR_MODE_ENABLE ((uint32_t)QUADSPI_CCR_DDRM) /*!<Double data rate mode enabled*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup QSPI_SIOOMode QSPI Send Instruction Mode
|
||||
* @{
|
||||
*/
|
||||
#define QSPI_SIOO_INST_EVERY_CMD 0x00000000U /*!<Send instruction on every transaction*/
|
||||
#define QSPI_SIOO_INST_ONLY_FIRST_CMD ((uint32_t)QUADSPI_CCR_SIOO) /*!<Send instruction only for the first command*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup QSPI_MatchMode QSPI Match Mode
|
||||
* @{
|
||||
*/
|
||||
#define QSPI_MATCH_MODE_AND 0x00000000U /*!<AND match mode between unmasked bits*/
|
||||
#define QSPI_MATCH_MODE_OR ((uint32_t)QUADSPI_CR_PMM) /*!<OR match mode between unmasked bits*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup QSPI_AutomaticStop QSPI Automatic Stop
|
||||
* @{
|
||||
*/
|
||||
#define QSPI_AUTOMATIC_STOP_DISABLE 0x00000000U /*!<AutoPolling stops only with abort or QSPI disabling*/
|
||||
#define QSPI_AUTOMATIC_STOP_ENABLE ((uint32_t)QUADSPI_CR_APMS) /*!<AutoPolling stops as soon as there is a match*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup QSPI_TimeOutActivation QSPI Timeout Activation
|
||||
* @{
|
||||
*/
|
||||
#define QSPI_TIMEOUT_COUNTER_DISABLE 0x00000000U /*!<Timeout counter disabled, nCS remains active*/
|
||||
#define QSPI_TIMEOUT_COUNTER_ENABLE ((uint32_t)QUADSPI_CR_TCEN) /*!<Timeout counter enabled, nCS released when timeout expires*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup QSPI_Flags QSPI Flags
|
||||
* @{
|
||||
*/
|
||||
#define QSPI_FLAG_BUSY QUADSPI_SR_BUSY /*!<Busy flag: operation is ongoing*/
|
||||
#define QSPI_FLAG_TO QUADSPI_SR_TOF /*!<Timeout flag: timeout occurs in memory-mapped mode*/
|
||||
#define QSPI_FLAG_SM QUADSPI_SR_SMF /*!<Status match flag: received data matches in autopolling mode*/
|
||||
#define QSPI_FLAG_FT QUADSPI_SR_FTF /*!<Fifo threshold flag: Fifo threshold reached or data left after read from memory is complete*/
|
||||
#define QSPI_FLAG_TC QUADSPI_SR_TCF /*!<Transfer complete flag: programmed number of data have been transferred or the transfer has been aborted*/
|
||||
#define QSPI_FLAG_TE QUADSPI_SR_TEF /*!<Transfer error flag: invalid address is being accessed*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup QSPI_Interrupts QSPI Interrupts
|
||||
* @{
|
||||
*/
|
||||
#define QSPI_IT_TO QUADSPI_CR_TOIE /*!<Interrupt on the timeout flag*/
|
||||
#define QSPI_IT_SM QUADSPI_CR_SMIE /*!<Interrupt on the status match flag*/
|
||||
#define QSPI_IT_FT QUADSPI_CR_FTIE /*!<Interrupt on the fifo threshold flag*/
|
||||
#define QSPI_IT_TC QUADSPI_CR_TCIE /*!<Interrupt on the transfer complete flag*/
|
||||
#define QSPI_IT_TE QUADSPI_CR_TEIE /*!<Interrupt on the transfer error flag*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup QSPI_Timeout_definition QSPI Timeout definition
|
||||
* @brief QSPI Timeout definition
|
||||
* @{
|
||||
*/
|
||||
#define HAL_QSPI_TIMEOUT_DEFAULT_VALUE 5000U /* 5 s */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/** @defgroup QSPI_Exported_Macros QSPI Exported Macros
|
||||
* @{
|
||||
*/
|
||||
/** @brief Reset QSPI handle state.
|
||||
* @param __HANDLE__ QSPI handle.
|
||||
* @retval None
|
||||
*/
|
||||
#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
|
||||
#define __HAL_QSPI_RESET_HANDLE_STATE(__HANDLE__) do { \
|
||||
(__HANDLE__)->State = HAL_QSPI_STATE_RESET; \
|
||||
(__HANDLE__)->MspInitCallback = NULL; \
|
||||
(__HANDLE__)->MspDeInitCallback = NULL; \
|
||||
} while(0)
|
||||
#else
|
||||
#define __HAL_QSPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_QSPI_STATE_RESET)
|
||||
#endif
|
||||
|
||||
/** @brief Enable the QSPI peripheral.
|
||||
* @param __HANDLE__ specifies the QSPI Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_QSPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)
|
||||
|
||||
/** @brief Disable the QSPI peripheral.
|
||||
* @param __HANDLE__ specifies the QSPI Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_QSPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)
|
||||
|
||||
/** @brief Enable the specified QSPI interrupt.
|
||||
* @param __HANDLE__ specifies the QSPI Handle.
|
||||
* @param __INTERRUPT__ specifies the QSPI interrupt source to enable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg QSPI_IT_TO: QSPI Timeout interrupt
|
||||
* @arg QSPI_IT_SM: QSPI Status match interrupt
|
||||
* @arg QSPI_IT_FT: QSPI FIFO threshold interrupt
|
||||
* @arg QSPI_IT_TC: QSPI Transfer complete interrupt
|
||||
* @arg QSPI_IT_TE: QSPI Transfer error interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_QSPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
|
||||
|
||||
|
||||
/** @brief Disable the specified QSPI interrupt.
|
||||
* @param __HANDLE__ specifies the QSPI Handle.
|
||||
* @param __INTERRUPT__ specifies the QSPI interrupt source to disable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg QSPI_IT_TO: QSPI Timeout interrupt
|
||||
* @arg QSPI_IT_SM: QSPI Status match interrupt
|
||||
* @arg QSPI_IT_FT: QSPI FIFO threshold interrupt
|
||||
* @arg QSPI_IT_TC: QSPI Transfer complete interrupt
|
||||
* @arg QSPI_IT_TE: QSPI Transfer error interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_QSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
|
||||
|
||||
/** @brief Check whether the specified QSPI interrupt source is enabled or not.
|
||||
* @param __HANDLE__ specifies the QSPI Handle.
|
||||
* @param __INTERRUPT__ specifies the QSPI interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg QSPI_IT_TO: QSPI Timeout interrupt
|
||||
* @arg QSPI_IT_SM: QSPI Status match interrupt
|
||||
* @arg QSPI_IT_FT: QSPI FIFO threshold interrupt
|
||||
* @arg QSPI_IT_TC: QSPI Transfer complete interrupt
|
||||
* @arg QSPI_IT_TE: QSPI Transfer error interrupt
|
||||
* @retval The new state of __INTERRUPT__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_QSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) == (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Check whether the selected QSPI flag is set or not.
|
||||
* @param __HANDLE__ specifies the QSPI Handle.
|
||||
* @param __FLAG__ specifies the QSPI flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg QSPI_FLAG_BUSY: QSPI Busy flag
|
||||
* @arg QSPI_FLAG_TO: QSPI Timeout flag
|
||||
* @arg QSPI_FLAG_SM: QSPI Status match flag
|
||||
* @arg QSPI_FLAG_FT: QSPI FIFO threshold flag
|
||||
* @arg QSPI_FLAG_TC: QSPI Transfer complete flag
|
||||
* @arg QSPI_FLAG_TE: QSPI Transfer error flag
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_QSPI_GET_FLAG(__HANDLE__, __FLAG__) ((READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0U) ? SET : RESET)
|
||||
|
||||
/** @brief Clears the specified QSPI's flag status.
|
||||
* @param __HANDLE__ specifies the QSPI Handle.
|
||||
* @param __FLAG__ specifies the QSPI clear register flag that needs to be set
|
||||
* This parameter can be one of the following values:
|
||||
* @arg QSPI_FLAG_TO: QSPI Timeout flag
|
||||
* @arg QSPI_FLAG_SM: QSPI Status match flag
|
||||
* @arg QSPI_FLAG_TC: QSPI Transfer complete flag
|
||||
* @arg QSPI_FLAG_TE: QSPI Transfer error flag
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_QSPI_CLEAR_FLAG(__HANDLE__, __FLAG__) WRITE_REG((__HANDLE__)->Instance->FCR, (__FLAG__))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup QSPI_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup QSPI_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
/* Initialization/de-initialization functions ********************************/
|
||||
HAL_StatusTypeDef HAL_QSPI_Init (QSPI_HandleTypeDef *hqspi);
|
||||
HAL_StatusTypeDef HAL_QSPI_DeInit (QSPI_HandleTypeDef *hqspi);
|
||||
void HAL_QSPI_MspInit (QSPI_HandleTypeDef *hqspi);
|
||||
void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup QSPI_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
/* IO operation functions *****************************************************/
|
||||
/* QSPI IRQ handler method */
|
||||
void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi);
|
||||
|
||||
/* QSPI indirect mode */
|
||||
HAL_StatusTypeDef HAL_QSPI_Command (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_QSPI_Transmit (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_QSPI_Receive (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_QSPI_Command_IT (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd);
|
||||
HAL_StatusTypeDef HAL_QSPI_Transmit_IT (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
|
||||
HAL_StatusTypeDef HAL_QSPI_Receive_IT (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
|
||||
HAL_StatusTypeDef HAL_QSPI_Transmit_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
|
||||
HAL_StatusTypeDef HAL_QSPI_Receive_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
|
||||
|
||||
/* QSPI status flag polling mode */
|
||||
HAL_StatusTypeDef HAL_QSPI_AutoPolling (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg);
|
||||
|
||||
/* QSPI memory-mapped mode */
|
||||
HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_MemoryMappedTypeDef *cfg);
|
||||
|
||||
/* Callback functions in non-blocking modes ***********************************/
|
||||
void HAL_QSPI_ErrorCallback (QSPI_HandleTypeDef *hqspi);
|
||||
void HAL_QSPI_AbortCpltCallback (QSPI_HandleTypeDef *hqspi);
|
||||
void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi);
|
||||
|
||||
/* QSPI indirect mode */
|
||||
void HAL_QSPI_CmdCpltCallback (QSPI_HandleTypeDef *hqspi);
|
||||
void HAL_QSPI_RxCpltCallback (QSPI_HandleTypeDef *hqspi);
|
||||
void HAL_QSPI_TxCpltCallback (QSPI_HandleTypeDef *hqspi);
|
||||
void HAL_QSPI_RxHalfCpltCallback (QSPI_HandleTypeDef *hqspi);
|
||||
void HAL_QSPI_TxHalfCpltCallback (QSPI_HandleTypeDef *hqspi);
|
||||
|
||||
/* QSPI status flag polling mode */
|
||||
void HAL_QSPI_StatusMatchCallback (QSPI_HandleTypeDef *hqspi);
|
||||
|
||||
/* QSPI memory-mapped mode */
|
||||
void HAL_QSPI_TimeOutCallback (QSPI_HandleTypeDef *hqspi);
|
||||
|
||||
#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
|
||||
/* QSPI callback registering/unregistering */
|
||||
HAL_StatusTypeDef HAL_QSPI_RegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDef CallbackId, pQSPI_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_QSPI_UnRegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDef CallbackId);
|
||||
#endif
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup QSPI_Exported_Functions_Group3
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral Control and State functions ************************************/
|
||||
HAL_QSPI_StateTypeDef HAL_QSPI_GetState (QSPI_HandleTypeDef *hqspi);
|
||||
uint32_t HAL_QSPI_GetError (QSPI_HandleTypeDef *hqspi);
|
||||
HAL_StatusTypeDef HAL_QSPI_Abort (QSPI_HandleTypeDef *hqspi);
|
||||
HAL_StatusTypeDef HAL_QSPI_Abort_IT (QSPI_HandleTypeDef *hqspi);
|
||||
void HAL_QSPI_SetTimeout (QSPI_HandleTypeDef *hqspi, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold);
|
||||
uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* End of exported functions -------------------------------------------------*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup QSPI_Private_Macros QSPI Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_QSPI_CLOCK_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFFU)
|
||||
|
||||
#define IS_QSPI_FIFO_THRESHOLD(THR) (((THR) > 0U) && ((THR) <= 16U))
|
||||
|
||||
#define IS_QSPI_SSHIFT(SSHIFT) (((SSHIFT) == QSPI_SAMPLE_SHIFTING_NONE) || \
|
||||
((SSHIFT) == QSPI_SAMPLE_SHIFTING_HALFCYCLE))
|
||||
|
||||
#define IS_QSPI_FLASH_SIZE(FSIZE) (((FSIZE) <= 31U))
|
||||
|
||||
#define IS_QSPI_CS_HIGH_TIME(CSHTIME) (((CSHTIME) == QSPI_CS_HIGH_TIME_1_CYCLE) || \
|
||||
((CSHTIME) == QSPI_CS_HIGH_TIME_2_CYCLE) || \
|
||||
((CSHTIME) == QSPI_CS_HIGH_TIME_3_CYCLE) || \
|
||||
((CSHTIME) == QSPI_CS_HIGH_TIME_4_CYCLE) || \
|
||||
((CSHTIME) == QSPI_CS_HIGH_TIME_5_CYCLE) || \
|
||||
((CSHTIME) == QSPI_CS_HIGH_TIME_6_CYCLE) || \
|
||||
((CSHTIME) == QSPI_CS_HIGH_TIME_7_CYCLE) || \
|
||||
((CSHTIME) == QSPI_CS_HIGH_TIME_8_CYCLE))
|
||||
|
||||
#define IS_QSPI_CLOCK_MODE(CLKMODE) (((CLKMODE) == QSPI_CLOCK_MODE_0) || \
|
||||
((CLKMODE) == QSPI_CLOCK_MODE_3))
|
||||
|
||||
#define IS_QSPI_INSTRUCTION(INSTRUCTION) ((INSTRUCTION) <= 0xFFU)
|
||||
|
||||
#define IS_QSPI_ADDRESS_SIZE(ADDR_SIZE) (((ADDR_SIZE) == QSPI_ADDRESS_8_BITS) || \
|
||||
((ADDR_SIZE) == QSPI_ADDRESS_16_BITS) || \
|
||||
((ADDR_SIZE) == QSPI_ADDRESS_24_BITS) || \
|
||||
((ADDR_SIZE) == QSPI_ADDRESS_32_BITS))
|
||||
|
||||
#define IS_QSPI_ALTERNATE_BYTES_SIZE(SIZE) (((SIZE) == QSPI_ALTERNATE_BYTES_8_BITS) || \
|
||||
((SIZE) == QSPI_ALTERNATE_BYTES_16_BITS) || \
|
||||
((SIZE) == QSPI_ALTERNATE_BYTES_24_BITS) || \
|
||||
((SIZE) == QSPI_ALTERNATE_BYTES_32_BITS))
|
||||
|
||||
#define IS_QSPI_DUMMY_CYCLES(DCY) ((DCY) <= 31U)
|
||||
|
||||
#define IS_QSPI_INSTRUCTION_MODE(MODE) (((MODE) == QSPI_INSTRUCTION_NONE) || \
|
||||
((MODE) == QSPI_INSTRUCTION_1_LINE) || \
|
||||
((MODE) == QSPI_INSTRUCTION_2_LINES) || \
|
||||
((MODE) == QSPI_INSTRUCTION_4_LINES))
|
||||
|
||||
#define IS_QSPI_ADDRESS_MODE(MODE) (((MODE) == QSPI_ADDRESS_NONE) || \
|
||||
((MODE) == QSPI_ADDRESS_1_LINE) || \
|
||||
((MODE) == QSPI_ADDRESS_2_LINES) || \
|
||||
((MODE) == QSPI_ADDRESS_4_LINES))
|
||||
|
||||
#define IS_QSPI_ALTERNATE_BYTES_MODE(MODE) (((MODE) == QSPI_ALTERNATE_BYTES_NONE) || \
|
||||
((MODE) == QSPI_ALTERNATE_BYTES_1_LINE) || \
|
||||
((MODE) == QSPI_ALTERNATE_BYTES_2_LINES) || \
|
||||
((MODE) == QSPI_ALTERNATE_BYTES_4_LINES))
|
||||
|
||||
#define IS_QSPI_DATA_MODE(MODE) (((MODE) == QSPI_DATA_NONE) || \
|
||||
((MODE) == QSPI_DATA_1_LINE) || \
|
||||
((MODE) == QSPI_DATA_2_LINES) || \
|
||||
((MODE) == QSPI_DATA_4_LINES))
|
||||
|
||||
#define IS_QSPI_DDR_MODE(DDR_MODE) (((DDR_MODE) == QSPI_DDR_MODE_DISABLE) || \
|
||||
((DDR_MODE) == QSPI_DDR_MODE_ENABLE))
|
||||
|
||||
#define IS_QSPI_SIOO_MODE(SIOO_MODE) (((SIOO_MODE) == QSPI_SIOO_INST_EVERY_CMD) || \
|
||||
((SIOO_MODE) == QSPI_SIOO_INST_ONLY_FIRST_CMD))
|
||||
|
||||
#define IS_QSPI_INTERVAL(INTERVAL) ((INTERVAL) <= QUADSPI_PIR_INTERVAL)
|
||||
|
||||
#define IS_QSPI_STATUS_BYTES_SIZE(SIZE) (((SIZE) >= 1U) && ((SIZE) <= 4U))
|
||||
|
||||
#define IS_QSPI_MATCH_MODE(MODE) (((MODE) == QSPI_MATCH_MODE_AND) || \
|
||||
((MODE) == QSPI_MATCH_MODE_OR))
|
||||
|
||||
#define IS_QSPI_AUTOMATIC_STOP(APMS) (((APMS) == QSPI_AUTOMATIC_STOP_DISABLE) || \
|
||||
((APMS) == QSPI_AUTOMATIC_STOP_ENABLE))
|
||||
|
||||
#define IS_QSPI_TIMEOUT_ACTIVATION(TCEN) (((TCEN) == QSPI_TIMEOUT_COUNTER_DISABLE) || \
|
||||
((TCEN) == QSPI_TIMEOUT_COUNTER_ENABLE))
|
||||
|
||||
#define IS_QSPI_TIMEOUT_PERIOD(PERIOD) ((PERIOD) <= 0xFFFFU)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* End of private macros -----------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* defined(QUADSPI) || defined(QUADSPI1) || defined(QUADSPI2) */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32WBxx_HAL_QSPI_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -1,380 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32wbxx_hal_rng.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of RNG HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32WBxx_HAL_RNG_H
|
||||
#define STM32WBxx_HAL_RNG_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32wbxx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32WBxx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined (RNG)
|
||||
|
||||
/** @defgroup RNG RNG
|
||||
* @brief RNG HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup RNG_Exported_Types RNG Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup RNG_Exported_Types_Group1 RNG Init Structure definition
|
||||
* @{
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t ClockErrorDetection; /*!< CED Clock error detection */
|
||||
} RNG_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RNG_Exported_Types_Group2 RNG State Structure definition
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_RNG_STATE_RESET = 0x00U, /*!< RNG not yet initialized or disabled */
|
||||
HAL_RNG_STATE_READY = 0x01U, /*!< RNG initialized and ready for use */
|
||||
HAL_RNG_STATE_BUSY = 0x02U, /*!< RNG internal process is ongoing */
|
||||
HAL_RNG_STATE_TIMEOUT = 0x03U, /*!< RNG timeout state */
|
||||
HAL_RNG_STATE_ERROR = 0x04U /*!< RNG error state */
|
||||
|
||||
} HAL_RNG_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RNG_Exported_Types_Group3 RNG Handle Structure definition
|
||||
* @{
|
||||
*/
|
||||
#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
|
||||
typedef struct __RNG_HandleTypeDef
|
||||
#else
|
||||
typedef struct
|
||||
#endif /* (USE_HAL_RNG_REGISTER_CALLBACKS) */
|
||||
{
|
||||
RNG_TypeDef *Instance; /*!< Register base address */
|
||||
|
||||
RNG_InitTypeDef Init; /*!< RNG configuration parameters */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< RNG locking object */
|
||||
|
||||
__IO HAL_RNG_StateTypeDef State; /*!< RNG communication state */
|
||||
|
||||
__IO uint32_t ErrorCode; /*!< RNG Error code */
|
||||
|
||||
uint32_t RandomNumber; /*!< Last Generated RNG Data */
|
||||
|
||||
#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
|
||||
void (* ReadyDataCallback)(struct __RNG_HandleTypeDef *hrng, uint32_t random32bit); /*!< RNG Data Ready Callback */
|
||||
void (* ErrorCallback)(struct __RNG_HandleTypeDef *hrng); /*!< RNG Error Callback */
|
||||
|
||||
void (* MspInitCallback)(struct __RNG_HandleTypeDef *hrng); /*!< RNG Msp Init callback */
|
||||
void (* MspDeInitCallback)(struct __RNG_HandleTypeDef *hrng); /*!< RNG Msp DeInit callback */
|
||||
#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
|
||||
|
||||
} RNG_HandleTypeDef;
|
||||
|
||||
#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
|
||||
/**
|
||||
* @brief HAL RNG Callback ID enumeration definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_RNG_ERROR_CB_ID = 0x00U, /*!< RNG Error Callback ID */
|
||||
|
||||
HAL_RNG_MSPINIT_CB_ID = 0x01U, /*!< RNG MspInit callback ID */
|
||||
HAL_RNG_MSPDEINIT_CB_ID = 0x02U /*!< RNG MspDeInit callback ID */
|
||||
|
||||
} HAL_RNG_CallbackIDTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL RNG Callback pointer definition
|
||||
*/
|
||||
typedef void (*pRNG_CallbackTypeDef)(RNG_HandleTypeDef *hrng); /*!< pointer to a common RNG callback function */
|
||||
typedef void (*pRNG_ReadyDataCallbackTypeDef)(RNG_HandleTypeDef *hrng, uint32_t random32bit); /*!< pointer to an RNG Data Ready specific callback function */
|
||||
|
||||
#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup RNG_Exported_Constants RNG Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup RNG_Exported_Constants_Group1 RNG Interrupt definition
|
||||
* @{
|
||||
*/
|
||||
#define RNG_IT_DRDY RNG_SR_DRDY /*!< Data Ready interrupt */
|
||||
#define RNG_IT_CEI RNG_SR_CEIS /*!< Clock error interrupt */
|
||||
#define RNG_IT_SEI RNG_SR_SEIS /*!< Seed error interrupt */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RNG_Exported_Constants_Group2 RNG Flag definition
|
||||
* @{
|
||||
*/
|
||||
#define RNG_FLAG_DRDY RNG_SR_DRDY /*!< Data ready */
|
||||
#define RNG_FLAG_CECS RNG_SR_CECS /*!< Clock error current status */
|
||||
#define RNG_FLAG_SECS RNG_SR_SECS /*!< Seed error current status */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RNG_Exported_Constants_Group3 RNG Clock Error Detection
|
||||
* @{
|
||||
*/
|
||||
#define RNG_CED_ENABLE 0x00000000U /*!< Clock error detection Enabled */
|
||||
#define RNG_CED_DISABLE RNG_CR_CED /*!< Clock error detection Disabled */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RNG_Error_Definition RNG Error Definition
|
||||
* @{
|
||||
*/
|
||||
#define HAL_RNG_ERROR_NONE 0x00000000U /*!< No error */
|
||||
#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
|
||||
#define HAL_RNG_ERROR_INVALID_CALLBACK 0x00000001U /*!< Invalid Callback error */
|
||||
#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
|
||||
#define HAL_RNG_ERROR_TIMEOUT 0x00000002U /*!< Timeout error */
|
||||
#define HAL_RNG_ERROR_BUSY 0x00000004U /*!< Busy error */
|
||||
#define HAL_RNG_ERROR_SEED 0x00000008U /*!< Seed error */
|
||||
#define HAL_RNG_ERROR_CLOCK 0x00000010U /*!< Clock error */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/** @defgroup RNG_Exported_Macros RNG Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset RNG handle state
|
||||
* @param __HANDLE__ RNG Handle
|
||||
* @retval None
|
||||
*/
|
||||
#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
|
||||
#define __HAL_RNG_RESET_HANDLE_STATE(__HANDLE__) do{ \
|
||||
(__HANDLE__)->State = HAL_RNG_STATE_RESET; \
|
||||
(__HANDLE__)->MspInitCallback = NULL; \
|
||||
(__HANDLE__)->MspDeInitCallback = NULL; \
|
||||
} while(0U)
|
||||
#else
|
||||
#define __HAL_RNG_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RNG_STATE_RESET)
|
||||
#endif /*USE_HAL_RNG_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @brief Enables the RNG peripheral.
|
||||
* @param __HANDLE__ RNG Handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RNG_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= RNG_CR_RNGEN)
|
||||
|
||||
/**
|
||||
* @brief Disables the RNG peripheral.
|
||||
* @param __HANDLE__ RNG Handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RNG_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~RNG_CR_RNGEN)
|
||||
|
||||
/**
|
||||
* @brief Check the selected RNG flag status.
|
||||
* @param __HANDLE__ RNG Handle
|
||||
* @param __FLAG__ RNG flag
|
||||
* This parameter can be one of the following values:
|
||||
* @arg RNG_FLAG_DRDY: Data ready
|
||||
* @arg RNG_FLAG_CECS: Clock error current status
|
||||
* @arg RNG_FLAG_SECS: Seed error current status
|
||||
* @retval The new state of __FLAG__ (SET or RESET).
|
||||
*/
|
||||
#define __HAL_RNG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
|
||||
|
||||
/**
|
||||
* @brief Clears the selected RNG flag status.
|
||||
* @param __HANDLE__ RNG handle
|
||||
* @param __FLAG__ RNG flag to clear
|
||||
* @note WARNING: This is a dummy macro for HAL code alignment,
|
||||
* flags RNG_FLAG_DRDY, RNG_FLAG_CECS and RNG_FLAG_SECS are read-only.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RNG_CLEAR_FLAG(__HANDLE__, __FLAG__) /* dummy macro */
|
||||
|
||||
/**
|
||||
* @brief Enables the RNG interrupts.
|
||||
* @param __HANDLE__ RNG Handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RNG_ENABLE_IT(__HANDLE__) ((__HANDLE__)->Instance->CR |= RNG_CR_IE)
|
||||
|
||||
/**
|
||||
* @brief Disables the RNG interrupts.
|
||||
* @param __HANDLE__ RNG Handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RNG_DISABLE_IT(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~RNG_CR_IE)
|
||||
|
||||
/**
|
||||
* @brief Checks whether the specified RNG interrupt has occurred or not.
|
||||
* @param __HANDLE__ RNG Handle
|
||||
* @param __INTERRUPT__ specifies the RNG interrupt status flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg RNG_IT_DRDY: Data ready interrupt
|
||||
* @arg RNG_IT_CEI: Clock error interrupt
|
||||
* @arg RNG_IT_SEI: Seed error interrupt
|
||||
* @retval The new state of __INTERRUPT__ (SET or RESET).
|
||||
*/
|
||||
#define __HAL_RNG_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR & (__INTERRUPT__)) == (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Clear the RNG interrupt status flags.
|
||||
* @param __HANDLE__ RNG Handle
|
||||
* @param __INTERRUPT__ specifies the RNG interrupt status flag to clear.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg RNG_IT_CEI: Clock error interrupt
|
||||
* @arg RNG_IT_SEI: Seed error interrupt
|
||||
* @note RNG_IT_DRDY flag is read-only, reading RNG_DR register automatically clears RNG_IT_DRDY.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RNG_CLEAR_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR) = ~(__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup RNG_Exported_Functions RNG Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup RNG_Exported_Functions_Group1 Initialization and configuration functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng);
|
||||
HAL_StatusTypeDef HAL_RNG_DeInit(RNG_HandleTypeDef *hrng);
|
||||
void HAL_RNG_MspInit(RNG_HandleTypeDef *hrng);
|
||||
void HAL_RNG_MspDeInit(RNG_HandleTypeDef *hrng);
|
||||
|
||||
/* Callbacks Register/UnRegister functions ***********************************/
|
||||
#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
|
||||
HAL_StatusTypeDef HAL_RNG_RegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID, pRNG_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_RNG_UnRegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID);
|
||||
|
||||
HAL_StatusTypeDef HAL_RNG_RegisterReadyDataCallback(RNG_HandleTypeDef *hrng, pRNG_ReadyDataCallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_RNG_UnRegisterReadyDataCallback(RNG_HandleTypeDef *hrng);
|
||||
#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RNG_Exported_Functions_Group2 Peripheral Control functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t *random32bit);
|
||||
HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber_IT(RNG_HandleTypeDef *hrng);
|
||||
uint32_t HAL_RNG_ReadLastRandomNumber(RNG_HandleTypeDef *hrng);
|
||||
|
||||
void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng);
|
||||
void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng);
|
||||
void HAL_RNG_ReadyDataCallback(RNG_HandleTypeDef *hrng, uint32_t random32bit);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RNG_Exported_Functions_Group3 Peripheral State functions
|
||||
* @{
|
||||
*/
|
||||
HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng);
|
||||
uint32_t HAL_RNG_GetError(RNG_HandleTypeDef *hrng);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup RNG_Private_Macros RNG Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_RNG_IT(IT) (((IT) == RNG_IT_CEI) || \
|
||||
((IT) == RNG_IT_SEI))
|
||||
|
||||
#define IS_RNG_FLAG(FLAG) (((FLAG) == RNG_FLAG_DRDY) || \
|
||||
((FLAG) == RNG_FLAG_CECS) || \
|
||||
((FLAG) == RNG_FLAG_SECS))
|
||||
|
||||
/**
|
||||
* @brief Verify the RNG Clock Error Detection mode.
|
||||
* @param __MODE__ RNG Clock Error Detection mode
|
||||
* @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
|
||||
*/
|
||||
#define IS_RNG_CED(__MODE__) (((__MODE__) == RNG_CED_ENABLE) || \
|
||||
((__MODE__) == RNG_CED_DISABLE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* RNG */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* STM32WBxx_HAL_RNG_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue