mirror of https://github.com/RT-Thread/rt-thread
[bsp][gd32] 添加GD32F527I BSP (#10454)
Co-authored-by: guozhanxin <guozhanxin@rt-thread.com>
This commit is contained in:
Yaochenger
GitHub
parent
ed5d877054
commit
935e1b1db1
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@ -301,6 +301,7 @@
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"gd32/arm/gd32470z-lckfb",
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"gd32/arm/gd32h759i-start",
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"gd32/arm/gd32e503v-eval",
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"gd32/arm/gd32527I-eval",
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"n32/n32g43xcl-stb",
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"n32/n32g45xcl-stb",
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"n32/n32g45xml-stb",
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File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,12 @@
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mainmenu "RT-Thread Configuration"
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BSP_DIR := .
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RTT_DIR := ../../../..
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PKGS_DIR := packages
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source "$(RTT_DIR)/Kconfig"
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osource "$PKGS_DIR/Kconfig"
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rsource "../libraries/Kconfig"
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rsource "board/Kconfig"
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@ -0,0 +1,81 @@
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# GDF527I-EVAL开发板BSP说明
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## 一 外设支持
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本 BSP 目前对外设的支持情况如下：
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| **片上外设** | **支持情况** | **备注** |
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|:-------- |:--------:|:-------------------------------- |
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| GPIO | 支持 | PA0, PA1... ---> PIN: 0, 1...113 |
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| UART | 支持 | UART0 - UART7 |
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| **扩展模块** | **支持情况** | **备注** |
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| 暂无 | 暂不支持 | 暂不支持 |
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## 二 使用说明
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使用说明分为如下两个章节：
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- 快速上手
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本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。
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- 进阶使用
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本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。
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### 三 快速上手
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本 BSP 为开发者提供 MDK5工程，支持 GCC 开发环境，也可使用RT-Thread Studio开发。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。
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### 3.1 硬件连接
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使用调试器连接开发板到 PC，使用USB2TTL连接USART0，并给开发板供电。
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### 3.2 编译下载
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双击 **project.uvprojx** 文件，打开 MDK5 工程，编译并下载程序到开发板。
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> 工程默认配置使用 CMSIS-DAP 仿真器下载程序，在通过 CMSIS-DAP 连接开发板的基础上，点击下载按钮即可下载程序到开发板;
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>
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> EVAL板载DAP-Link，可直接使用板子DAP-Link下载.
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### 3.3 运行结果
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下载程序成功之后，系统会自动运行，LED 闪烁。
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连接开发板对应串口到 PC , 在终端工具里打开相应的串口（115200-8-1-N），复位设备后，可以看到 RT-Thread 的输出信息:
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```apl
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\ | /
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- RT - Thread Operating System
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/ | \ 5.2.1 build Jul 3 2025 11:53:15
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2006 - 2024 Copyright by RT-Thread team
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msh />
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```
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### 3.4 进阶使用
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此 BSP 默认只开启了 GPIO 和 串口1的功能，如果需使用高级功能，需要利用 ENV 工具对BSP 进行配置，步骤如下：
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1. 在 bsp 下打开 env 工具。
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2. 输入`menuconfig`命令配置工程，配置好之后保存退出。
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3. 输入`pkgs --update`命令更新软件包。
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4. 输入`scons --target=mdk4/mdk5/iar` 命令重新生成工程。
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## 3.5 注意事项
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若MDK编译无法运行请更行MDK至较新的版本，在MDK538版本测试通过。
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## 四 联系人信息
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维护人:
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- [yuanzihao](https://github.com/zihao-yuan/), 邮箱：<y@yzh.email>
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- [Guozhanxin](https://github.com/Guozhanxin)
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@ -0,0 +1,15 @@
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# for module compiling
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import os
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Import('RTT_ROOT')
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from building import *
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cwd = GetCurrentDir()
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objs = []
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list = os.listdir(cwd)
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for d in list:
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path = os.path.join(cwd, d)
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if os.path.isfile(os.path.join(path, 'SConscript')):
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objs = objs + SConscript(os.path.join(d, 'SConscript'))
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Return('objs')
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import os
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import sys
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import rtconfig
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if os.getenv('RTT_ROOT'):
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RTT_ROOT = os.getenv('RTT_ROOT')
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else:
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RTT_ROOT = os.path.normpath(os.getcwd() + '/../../../..')
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sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
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try:
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from building import *
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except:
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print('Cannot found RT-Thread root directory, please check RTT_ROOT')
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print(RTT_ROOT)
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exit(-1)
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def bsp_pkg_check():
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import subprocess
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check_paths = [
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os.path.join("packages", "gd32-arm-cmsis-latest"),
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os.path.join("packages", "gd32-arm-series-latest")
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]
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need_update = not all(os.path.exists(p) for p in check_paths)
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if need_update:
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print("\n===============================================================================")
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print("Dependency packages missing, please running 'pkgs --update'...")
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print("If no packages are fetched, run 'pkgs --upgrade' first, then 'pkgs --update'...")
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print("===============================================================================")
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exit(1)
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RegisterPreBuildingAction(bsp_pkg_check)
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TARGET = 'rtthread.' + rtconfig.TARGET_EXT
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DefaultEnvironment(tools=[])
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env = Environment(tools = ['mingw'],
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AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
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CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
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AR = rtconfig.AR, ARFLAGS = '-rc',
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CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
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LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
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env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
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if rtconfig.PLATFORM in ['iccarm']:
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env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
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env.Replace(ARFLAGS = [''])
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env.Replace(LINKCOM = env["LINKCOM"] + ' --map rtthread.map')
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Export('env')
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Export('RTT_ROOT')
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Export('rtconfig')
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SDK_ROOT = os.path.abspath('./')
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if os.path.exists(SDK_ROOT + '/libraries'):
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libraries_path_prefix = SDK_ROOT + '/libraries'
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else:
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libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries'
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SDK_LIB = libraries_path_prefix
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Export('SDK_LIB')
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# prepare building environment
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objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
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gd32_library = 'GD32F5xx_Firmware_Library'
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rtconfig.BSP_LIBRARY_TYPE = gd32_library
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# include libraries
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# objs.extend(SConscript(os.path.join(libraries_path_prefix, gd32_library, 'SConscript')))
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# include drivers
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objs.extend(SConscript(os.path.join(libraries_path_prefix, 'gd32_drivers', 'SConscript')))
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# make a building
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DoBuilding(TARGET, objs)
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from building import *
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import os
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cwd = GetCurrentDir()
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src = Glob('*.c')
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CPPPATH = [cwd]
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group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
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list = os.listdir(cwd)
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for item in list:
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if os.path.isfile(os.path.join(cwd, item, 'SConscript')):
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group = group + SConscript(os.path.join(item, 'SConscript'))
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Return('group')
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@ -0,0 +1,36 @@
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/*
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* Copyright (c) 2006-2023, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2021-08-20 BruceOu first implementation
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* 2023-03-05 yuanzihao change the LED pins
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*/
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#include <stdio.h>
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#include <rtthread.h>
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#include <rtdevice.h>
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#include <board.h>
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/* defined the LED1 pin: PE3 */
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#define LED1_PIN GET_PIN(E, 3)
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int main(void)
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{
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int count = 1;
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/* set LED1 pin mode to output */
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rt_pin_mode(LED1_PIN, PIN_MODE_OUTPUT);
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while (count++)
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{
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rt_pin_write(LED1_PIN, PIN_HIGH);
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rt_thread_mdelay(500);
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rt_pin_write(LED1_PIN, PIN_LOW);
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rt_thread_mdelay(500);
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}
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return RT_EOK;
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}
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menu "Hardware Drivers Config"
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config SOC_SERIES_GD32F5xx
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bool
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select ARCH_ARM_CORTEX_SECURE
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default y
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config SOC_GD32527
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bool
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select SOC_SERIES_GD32F5xx
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select RT_USING_COMPONENTS_INIT
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select RT_USING_USER_MAIN
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default y
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menu "Onboard Peripheral Drivers"
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endmenu
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menu "On-chip Peripheral Drivers"
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config BSP_USING_GPIO
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bool "Enable GPIO"
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select RT_USING_PIN
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default y
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menuconfig BSP_USING_UART
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bool "Enable UART"
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default y
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select RT_USING_SERIAL
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if BSP_USING_UART
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config BSP_USING_UART0
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bool "Enable UART0"
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default y
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config BSP_UART0_RX_USING_DMA
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bool "Enable UART0 RX DMA"
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depends on BSP_USING_UART0
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select RT_SERIAL_USING_DMA
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default n
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config BSP_UART0_TX_USING_DMA
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bool "Enable UART0 TX DMA"
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depends on BSP_USING_UART0
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select RT_SERIAL_USING_DMA
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default n
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config BSP_UART0_RX_BUFSIZE
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int "Set UART0 RX buffer size"
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range 64 65535
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depends on BSP_USING_UART0 && RT_USING_SERIAL_V2
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default 64
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config BSP_UART0_TX_BUFSIZE
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int "Set UART0 TX buffer size"
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range 0 65535
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depends on BSP_USING_UART0 && RT_USING_SERIAL_V2
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default 0
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config BSP_USING_UART1
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bool "Enable UART1"
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default n
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config BSP_UART1_RX_USING_DMA
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bool "Enable UART1 RX DMA"
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depends on BSP_USING_UART1
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select RT_SERIAL_USING_DMA
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default n
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config BSP_UART1_TX_USING_DMA
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bool "Enable UART1 TX DMA"
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depends on BSP_USING_UART1
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select RT_SERIAL_USING_DMA
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default n
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config BSP_UART1_RX_BUFSIZE
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int "Set UART1 RX buffer size"
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range 64 65535
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depends on BSP_USING_UART1 && RT_USING_SERIAL_V2
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default 64
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config BSP_UART1_TX_BUFSIZE
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int "Set UART1 TX buffer size"
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range 0 65535
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depends on BSP_USING_UART1 && RT_USING_SERIAL_V2
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default 0
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config BSP_USING_UART2
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bool "Enable UART2"
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default n
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config BSP_UART2_RX_USING_DMA
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bool "Enable UART2 RX DMA"
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depends on BSP_USING_UART2
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select RT_SERIAL_USING_DMA
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default n
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config BSP_UART2_TX_USING_DMA
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bool "Enable UART2 TX DMA"
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depends on BSP_USING_UART2
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select RT_SERIAL_USING_DMA
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default n
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config BSP_UART2_RX_BUFSIZE
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int "Set UART2 RX buffer size"
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range 64 65535
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depends on BSP_USING_UART2 && RT_USING_SERIAL_V2
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default 64
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config BSP_UART2_TX_BUFSIZE
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int "Set UART2 TX buffer size"
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range 0 65535
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depends on BSP_USING_UART2 && RT_USING_SERIAL_V2
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default 0
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config BSP_USING_UART3
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bool "Enable UART3"
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default n
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config BSP_UART3_RX_USING_DMA
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bool "Enable UART3 RX DMA"
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depends on BSP_USING_UART3
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select RT_SERIAL_USING_DMA
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default n
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config BSP_UART3_TX_USING_DMA
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bool "Enable UART3 TX DMA"
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depends on BSP_USING_UART3
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select RT_SERIAL_USING_DMA
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default n
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config BSP_UART3_RX_BUFSIZE
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int "Set UART3 RX buffer size"
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range 64 65535
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depends on BSP_USING_UART3 && RT_USING_SERIAL_V2
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default 64
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config BSP_UART3_TX_BUFSIZE
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int "Set UART3 TX buffer size"
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range 0 65535
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depends on BSP_USING_UART3 && RT_USING_SERIAL_V2
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default 0
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config BSP_USING_UART4
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bool "Enable UART4"
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default n
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config BSP_UART4_RX_USING_DMA
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bool "Enable UART4 RX DMA"
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depends on BSP_USING_UART4
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select RT_SERIAL_USING_DMA
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default n
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config BSP_UART4_TX_USING_DMA
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bool "Enable UART4 TX DMA"
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depends on BSP_USING_UART4
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select RT_SERIAL_USING_DMA
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default n
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config BSP_UART4_RX_BUFSIZE
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int "Set UART4 RX buffer size"
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range 64 65535
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depends on BSP_USING_UART4 && RT_USING_SERIAL_V2
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default 64
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config BSP_UART4_TX_BUFSIZE
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int "Set UART4 TX buffer size"
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range 0 65535
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depends on BSP_USING_UART4 && RT_USING_SERIAL_V2
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default 0
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config BSP_USING_UART5
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bool "Enable UART5"
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default n
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config BSP_UART5_RX_USING_DMA
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bool "Enable UART5 RX DMA"
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depends on BSP_USING_UART5
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select RT_SERIAL_USING_DMA
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default n
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config BSP_UART5_TX_USING_DMA
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bool "Enable UART5 TX DMA"
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depends on BSP_USING_UART5
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select RT_SERIAL_USING_DMA
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default n
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config BSP_UART5_RX_BUFSIZE
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int "Set UART5 RX buffer size"
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range 64 65535
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depends on BSP_USING_UART5 && RT_USING_SERIAL_V2
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default 64
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config BSP_UART5_TX_BUFSIZE
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int "Set UART5 TX buffer size"
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range 0 65535
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depends on BSP_USING_UART5 && RT_USING_SERIAL_V2
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default 0
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config BSP_USING_UART6
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bool "Enable UART6"
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default n
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config BSP_UART6_RX_USING_DMA
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bool "Enable UART6 RX DMA"
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depends on BSP_USING_UART6
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select RT_SERIAL_USING_DMA
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default n
|
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config BSP_UART6_TX_USING_DMA
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bool "Enable UART6 TX DMA"
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depends on BSP_USING_UART6
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select RT_SERIAL_USING_DMA
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default n
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config BSP_UART6_RX_BUFSIZE
|
||||
int "Set UART6 RX buffer size"
|
||||
range 64 65535
|
||||
depends on BSP_USING_UART6 && RT_USING_SERIAL_V2
|
||||
default 64
|
||||
|
||||
config BSP_UART6_TX_BUFSIZE
|
||||
int "Set UART6 TX buffer size"
|
||||
range 0 65535
|
||||
depends on BSP_USING_UART6 && RT_USING_SERIAL_V2
|
||||
default 0
|
||||
|
||||
config BSP_USING_UART7
|
||||
bool "Enable UART7"
|
||||
default n
|
||||
|
||||
config BSP_UART7_RX_USING_DMA
|
||||
bool "Enable UART7 RX DMA"
|
||||
depends on BSP_USING_UART7
|
||||
select RT_SERIAL_USING_DMA
|
||||
default n
|
||||
|
||||
config BSP_UART7_TX_USING_DMA
|
||||
bool "Enable UART7 TX DMA"
|
||||
depends on BSP_USING_UART7
|
||||
select RT_SERIAL_USING_DMA
|
||||
default n
|
||||
|
||||
config BSP_UART7_RX_BUFSIZE
|
||||
int "Set UART7 RX buffer size"
|
||||
range 64 65535
|
||||
depends on BSP_USING_UART7 && RT_USING_SERIAL_V2
|
||||
default 64
|
||||
|
||||
config BSP_UART7_TX_BUFSIZE
|
||||
int "Set UART7 TX buffer size"
|
||||
range 0 65535
|
||||
depends on BSP_USING_UART7 && RT_USING_SERIAL_V2
|
||||
default 0
|
||||
endif
|
||||
|
||||
menuconfig BSP_USING_SPI
|
||||
bool "Enable SPI BUS"
|
||||
default n
|
||||
select RT_USING_SPI
|
||||
if BSP_USING_SPI
|
||||
config BSP_USING_SPI1
|
||||
bool "Enable SPI1 BUS"
|
||||
default n
|
||||
|
||||
config BSP_SPI1_TX_USING_DMA
|
||||
bool "Enable SPI1 TX DMA"
|
||||
depends on BSP_USING_SPI1
|
||||
default n
|
||||
|
||||
config BSP_SPI1_RX_USING_DMA
|
||||
bool "Enable SPI1 RX DMA"
|
||||
depends on BSP_USING_SPI1
|
||||
select BSP_SPI1_TX_USING_DMA
|
||||
default n
|
||||
endif
|
||||
|
||||
menuconfig BSP_USING_I2C1
|
||||
bool "Enable I2C1 BUS (software simulation)"
|
||||
default n
|
||||
select RT_USING_I2C
|
||||
select RT_USING_I2C_BITOPS
|
||||
select RT_USING_PIN
|
||||
if BSP_USING_I2C1
|
||||
config BSP_I2C1_SCL_PIN
|
||||
int "i2c1 scl pin number"
|
||||
range 1 216
|
||||
default 24
|
||||
config BSP_I2C1_SDA_PIN
|
||||
int "I2C1 sda pin number"
|
||||
range 1 216
|
||||
default 25
|
||||
endif
|
||||
|
||||
menuconfig BSP_USING_ADC
|
||||
bool "Enable ADC"
|
||||
default n
|
||||
select RT_USING_ADC
|
||||
if BSP_USING_ADC
|
||||
config BSP_USING_ADC0
|
||||
bool "Enable ADC0"
|
||||
default n
|
||||
|
||||
config BSP_USING_ADC1
|
||||
bool "Enable ADC1"
|
||||
default n
|
||||
|
||||
config BSP_USING_ADC2
|
||||
bool "Enable ADC2"
|
||||
default n
|
||||
endif
|
||||
|
||||
menuconfig BSP_USING_TIM
|
||||
bool "Enable timer"
|
||||
default n
|
||||
select RT_USING_HWTIMER
|
||||
if BSP_USING_TIM
|
||||
config BSP_USING_TIM10
|
||||
bool "Enable TIM10"
|
||||
default n
|
||||
|
||||
config BSP_USING_TIM11
|
||||
bool "Enable TIM11"
|
||||
default n
|
||||
|
||||
config BSP_USING_TIM12
|
||||
bool "Enable TIM13"
|
||||
default n
|
||||
endif
|
||||
|
||||
menuconfig BSP_USING_ONCHIP_RTC
|
||||
bool "Enable RTC"
|
||||
select RT_USING_RTC
|
||||
default n
|
||||
if BSP_USING_ONCHIP_RTC
|
||||
choice
|
||||
prompt "Select clock source"
|
||||
default BSP_RTC_USING_LSE
|
||||
|
||||
config BSP_RTC_USING_LSE
|
||||
bool "RTC USING LSE"
|
||||
|
||||
config BSP_RTC_USING_LSI
|
||||
bool "RTC USING LSI"
|
||||
endchoice
|
||||
endif
|
||||
|
||||
config BSP_USING_WDT
|
||||
bool "Enable Watchdog Timer"
|
||||
select RT_USING_WDT
|
||||
default n
|
||||
|
||||
config BSP_USING_SDIO
|
||||
bool "Enable SDIO"
|
||||
select RT_USING_SDIO
|
||||
select RT_USING_DFS
|
||||
default n
|
||||
|
||||
config BSP_USING_USBD
|
||||
bool "Enable USB Device"
|
||||
select RT_USING_USB_DEVICE
|
||||
default n
|
||||
|
||||
menuconfig BSP_USING_USBH
|
||||
bool "Enable USB Host"
|
||||
select RT_USING_USB_HOST
|
||||
default n
|
||||
if BSP_USING_USBH
|
||||
menuconfig RT_USBH_MSTORAGE
|
||||
bool "Enable Udisk Drivers"
|
||||
default n
|
||||
if RT_USBH_MSTORAGE
|
||||
config UDISK_MOUNTPOINT
|
||||
string "Udisk mount dir"
|
||||
default "/"
|
||||
endif
|
||||
endif
|
||||
|
||||
config BSP_USING_SDRAM
|
||||
bool "Enable SDRAM"
|
||||
select RT_USING_SDRAM
|
||||
default n
|
||||
|
||||
rsource "../../libraries/gd32_drivers/Kconfig"
|
||||
|
||||
endmenu
|
||||
|
||||
menu "Board extended module Drivers"
|
||||
|
||||
endmenu
|
||||
|
||||
endmenu
|
||||
|
|
@ -0,0 +1,19 @@
|
|||
import os
|
||||
import rtconfig
|
||||
from building import *
|
||||
|
||||
Import('SDK_LIB')
|
||||
|
||||
cwd = GetCurrentDir()
|
||||
|
||||
# add general drivers
|
||||
src = Split('''
|
||||
board.c
|
||||
''')
|
||||
|
||||
path = [cwd]
|
||||
|
||||
CPPDEFINES = ['GD32F527']
|
||||
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
|
||||
|
||||
Return('group')
|
||||
|
|
@ -0,0 +1,95 @@
|
|||
/*
|
||||
* Copyright (c) 2006-2024, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2021-08-20 BruceOu first implementation
|
||||
* 2024-03-19 Evlers add serial supports
|
||||
*/
|
||||
#include <stdint.h>
|
||||
#include <rthw.h>
|
||||
#include <rtthread.h>
|
||||
#include <board.h>
|
||||
|
||||
#ifdef RT_USING_SERIAL_V2
|
||||
#include "drv_usart_v2.h"
|
||||
#else
|
||||
#include "drv_usart.h"
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
* @brief This function is executed in case of error occurrence.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void Error_Handler(void)
|
||||
{
|
||||
/* USER CODE BEGIN Error_Handler */
|
||||
/* User can add his own implementation to report the HAL error return state */
|
||||
while (1)
|
||||
{
|
||||
}
|
||||
/* USER CODE END Error_Handler */
|
||||
}
|
||||
|
||||
/** System Clock Configuration
|
||||
*/
|
||||
void SystemClock_Config(void)
|
||||
{
|
||||
SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND);
|
||||
NVIC_SetPriority(SysTick_IRQn, 0);
|
||||
}
|
||||
|
||||
/**
|
||||
* This is the timer interrupt service routine.
|
||||
*
|
||||
*/
|
||||
void SysTick_Handler(void)
|
||||
{
|
||||
/* enter interrupt */
|
||||
rt_interrupt_enter();
|
||||
|
||||
rt_tick_increase();
|
||||
|
||||
/* leave interrupt */
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
|
||||
/**
|
||||
* This function will initial GD32 board.
|
||||
*/
|
||||
void rt_hw_board_init()
|
||||
{
|
||||
/* NVIC Configuration */
|
||||
#define NVIC_VTOR_MASK 0x3FFFFF80
|
||||
#ifdef VECT_TAB_RAM
|
||||
/* Set the Vector Table base location at 0x10000000 */
|
||||
SCB->VTOR = (0x10000000 & NVIC_VTOR_MASK);
|
||||
#else /* VECT_TAB_FLASH */
|
||||
/* Set the Vector Table base location at 0x08000000 */
|
||||
SCB->VTOR = (0x08000000 & NVIC_VTOR_MASK);
|
||||
#endif
|
||||
|
||||
SystemClock_Config();
|
||||
|
||||
#ifdef RT_USING_SERIAL
|
||||
rt_hw_usart_init();
|
||||
#endif
|
||||
|
||||
#ifdef RT_USING_HEAP
|
||||
rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
|
||||
#endif
|
||||
|
||||
#ifdef RT_USING_CONSOLE
|
||||
rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
|
||||
#endif
|
||||
|
||||
#ifdef RT_USING_COMPONENTS_INIT
|
||||
rt_components_board_init();
|
||||
#endif
|
||||
}
|
||||
|
||||
/*@}*/
|
||||
|
|
@ -0,0 +1,47 @@
|
|||
/*
|
||||
* Copyright (c) 2006-2024, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2021-08-20 BruceOu first implementation
|
||||
* 2024-03-19 Evlers remove the include of drv_usart.h
|
||||
*/
|
||||
#ifndef __BOARD_H__
|
||||
#define __BOARD_H__
|
||||
|
||||
#include "gd32f5xx.h"
|
||||
#include "drv_gpio.h"
|
||||
|
||||
#include "gd32f5xx_exti.h"
|
||||
|
||||
#define EXT_SDRAM_BEGIN (0xC0000000U) /* the begining address of external SDRAM */
|
||||
#define EXT_SDRAM_END (EXT_SDRAM_BEGIN + (32U * 1024 * 1024)) /* the end address of external SDRAM */
|
||||
|
||||
// <o> Internal SRAM memory size[Kbytes] <8-512>
|
||||
// <i>Default: 448
|
||||
#ifdef __ICCARM__
|
||||
// Use *.icf ram symbal, to avoid hardcode.
|
||||
extern char __ICFEDIT_region_RAM_end__;
|
||||
#define GD32_SRAM_END &__ICFEDIT_region_RAM_end__
|
||||
#else
|
||||
#define GD32_SRAM_SIZE 448
|
||||
#define GD32_SRAM_END (0x20000000 + GD32_SRAM_SIZE * 1024)
|
||||
#endif
|
||||
|
||||
#ifdef __ARMCC_VERSION
|
||||
extern int Image$$RW_IRAM1$$ZI$$Limit;
|
||||
#define HEAP_BEGIN (&Image$$RW_IRAM1$$ZI$$Limit)
|
||||
#elif __ICCARM__
|
||||
#pragma section="HEAP"
|
||||
#define HEAP_BEGIN (__segment_end("HEAP"))
|
||||
#else
|
||||
extern int __bss_end;
|
||||
#define HEAP_BEGIN (&__bss_end)
|
||||
#endif
|
||||
|
||||
#define HEAP_END GD32_SRAM_END
|
||||
|
||||
#endif
|
||||
|
||||
|
|
@ -0,0 +1,45 @@
|
|||
/*!
|
||||
\file gd32f5xx_libopt.h
|
||||
\brief library optional for gd32f5xx
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (C) 2016 GigaDevice
|
||||
|
||||
2016-10-19, V1.0.0, firmware for GD32F5xx
|
||||
*/
|
||||
|
||||
#ifndef GD32F5XX_LIBOPT_H
|
||||
#define GD32F5XX_LIBOPT_H
|
||||
#include "gd32f5xx_rcu.h"
|
||||
#include "gd32f5xx_adc.h"
|
||||
#include "gd32f5xx_can.h"
|
||||
#include "gd32f5xx_crc.h"
|
||||
#include "gd32f5xx_ctc.h"
|
||||
#include "gd32f5xx_dac.h"
|
||||
#include "gd32f5xx_dbg.h"
|
||||
#include "gd32f5xx_dci.h"
|
||||
#include "gd32f5xx_dma.h"
|
||||
//#include "gd32f5xx_enet.h"
|
||||
#include "gd32f5xx_exmc.h"
|
||||
#include "gd32f5xx_exti.h"
|
||||
#include "gd32f5xx_fmc.h"
|
||||
#include "gd32f5xx_fwdgt.h"
|
||||
#include "gd32f5xx_gpio.h"
|
||||
#include "gd32f5xx_syscfg.h"
|
||||
#include "gd32f5xx_i2c.h"
|
||||
#include "gd32f5xx_ipa.h"
|
||||
#include "gd32f5xx_iref.h"
|
||||
#include "gd32f5xx_pmu.h"
|
||||
#include "gd32f5xx_rcu.h"
|
||||
#include "gd32f5xx_rtc.h"
|
||||
#include "gd32f5xx_sdio.h"
|
||||
#include "gd32f5xx_spi.h"
|
||||
#include "gd32f5xx_timer.h"
|
||||
#include "gd32f5xx_tli.h"
|
||||
#include "gd32f5xx_trng.h"
|
||||
#include "gd32f5xx_usart.h"
|
||||
#include "gd32f5xx_wwdgt.h"
|
||||
#include "gd32f5xx_misc.h"
|
||||
|
||||
#endif /* GD32F5XX_LIBOPT_H */
|
||||
|
|
@ -0,0 +1,40 @@
|
|||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x08000000;
|
||||
/*-Memory Regions-*/
|
||||
define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
|
||||
define symbol __ICFEDIT_region_ROM_end__ = 0x080FFFFF;
|
||||
define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
|
||||
define symbol __ICFEDIT_region_RAM_end__ = 0x2006FFFF;
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x2000;
|
||||
define symbol __ICFEDIT_size_heap__ = 0x2000;
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
export symbol __ICFEDIT_region_RAM_end__;
|
||||
|
||||
define symbol __region_RAM1_start__ = 0x10000000;
|
||||
define symbol __region_RAM1_end__ = 0x1000FFFF;
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||
define region RAM1_region = mem:[from __region_RAM1_start__ to __region_RAM1_end__];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit };
|
||||
|
||||
keep { section FSymTab };
|
||||
keep { section VSymTab };
|
||||
keep { section .rti_fn* };
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
|
||||
place in ROM_region { readonly };
|
||||
place in RAM_region { readwrite,
|
||||
block CSTACK, block HEAP };
|
||||
place in RAM1_region { section .sram };
|
||||
|
|
@ -0,0 +1,142 @@
|
|||
/*
|
||||
* linker script for GD32F5xx with GNU ld
|
||||
* BruceOu 2021-12-14
|
||||
*/
|
||||
|
||||
/* Program Entry, set to mark it as "used" and avoid gc */
|
||||
MEMORY
|
||||
{
|
||||
CODE (rx) : ORIGIN = 0x08000000, LENGTH = 2048k /* 1024KB flash */
|
||||
DATA (rw) : ORIGIN = 0x20000000, LENGTH = 512k /* 448KB sram */
|
||||
}
|
||||
ENTRY(Reset_Handler)
|
||||
_system_stack_size = 0x200;
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_stext = .;
|
||||
KEEP(*(.isr_vector)) /* Startup code */
|
||||
. = ALIGN(4);
|
||||
*(.text) /* remaining code */
|
||||
*(.text.*) /* remaining code */
|
||||
*(.rodata) /* read-only data (constants) */
|
||||
*(.rodata*)
|
||||
*(.glue_7)
|
||||
*(.glue_7t)
|
||||
*(.gnu.linkonce.t*)
|
||||
|
||||
/* section information for finsh shell */
|
||||
. = ALIGN(4);
|
||||
__fsymtab_start = .;
|
||||
KEEP(*(FSymTab))
|
||||
__fsymtab_end = .;
|
||||
. = ALIGN(4);
|
||||
__vsymtab_start = .;
|
||||
KEEP(*(VSymTab))
|
||||
__vsymtab_end = .;
|
||||
. = ALIGN(4);
|
||||
|
||||
/* section information for initial. */
|
||||
. = ALIGN(4);
|
||||
__rt_init_start = .;
|
||||
KEEP(*(SORT(.rti_fn*)))
|
||||
__rt_init_end = .;
|
||||
. = ALIGN(4);
|
||||
|
||||
. = ALIGN(4);
|
||||
_etext = .;
|
||||
} > CODE = 0
|
||||
|
||||
/* .ARM.exidx is sorted, so has to go in its own output section. */
|
||||
__exidx_start = .;
|
||||
.ARM.exidx :
|
||||
{
|
||||
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
|
||||
|
||||
/* This is used by the startup in order to initialize the .data secion */
|
||||
_sidata = .;
|
||||
} > CODE
|
||||
__exidx_end = .;
|
||||
|
||||
/* .data section which is used for initialized data */
|
||||
|
||||
.data : AT (_sidata)
|
||||
{
|
||||
. = ALIGN(4);
|
||||
/* This is used by the startup in order to initialize the .data secion */
|
||||
_sdata = . ;
|
||||
|
||||
*(.data)
|
||||
*(.data.*)
|
||||
*(.gnu.linkonce.d*)
|
||||
|
||||
. = ALIGN(4);
|
||||
/* This is used by the startup in order to initialize the .data secion */
|
||||
_edata = . ;
|
||||
} >DATA
|
||||
|
||||
.stack :
|
||||
{
|
||||
. = . + _system_stack_size;
|
||||
. = ALIGN(4);
|
||||
_estack = .;
|
||||
} >DATA
|
||||
|
||||
__bss_start = .;
|
||||
.bss :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
/* This is used by the startup in order to initialize the .bss secion */
|
||||
_sbss = .;
|
||||
|
||||
*(.bss)
|
||||
*(.bss.*)
|
||||
*(COMMON)
|
||||
|
||||
. = ALIGN(4);
|
||||
/* This is used by the startup in order to initialize the .bss secion */
|
||||
_ebss = . ;
|
||||
|
||||
*(.bss.init)
|
||||
} > DATA
|
||||
__bss_end = .;
|
||||
|
||||
_end = .;
|
||||
|
||||
/* Stabs debugging sections. */
|
||||
.stab 0 : { *(.stab) }
|
||||
.stabstr 0 : { *(.stabstr) }
|
||||
.stab.excl 0 : { *(.stab.excl) }
|
||||
.stab.exclstr 0 : { *(.stab.exclstr) }
|
||||
.stab.index 0 : { *(.stab.index) }
|
||||
.stab.indexstr 0 : { *(.stab.indexstr) }
|
||||
.comment 0 : { *(.comment) }
|
||||
/* DWARF debug sections.
|
||||
* Symbols in the DWARF debugging sections are relative to the beginning
|
||||
* of the section so we begin them at 0. */
|
||||
/* DWARF 1 */
|
||||
.debug 0 : { *(.debug) }
|
||||
.line 0 : { *(.line) }
|
||||
/* GNU DWARF 1 extensions */
|
||||
.debug_srcinfo 0 : { *(.debug_srcinfo) }
|
||||
.debug_sfnames 0 : { *(.debug_sfnames) }
|
||||
/* DWARF 1.1 and DWARF 2 */
|
||||
.debug_aranges 0 : { *(.debug_aranges) }
|
||||
.debug_pubnames 0 : { *(.debug_pubnames) }
|
||||
/* DWARF 2 */
|
||||
.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
|
||||
.debug_abbrev 0 : { *(.debug_abbrev) }
|
||||
.debug_line 0 : { *(.debug_line) }
|
||||
.debug_frame 0 : { *(.debug_frame) }
|
||||
.debug_str 0 : { *(.debug_str) }
|
||||
.debug_loc 0 : { *(.debug_loc) }
|
||||
.debug_macinfo 0 : { *(.debug_macinfo) }
|
||||
/* SGI/MIPS DWARF 2 extensions */
|
||||
.debug_weaknames 0 : { *(.debug_weaknames) }
|
||||
.debug_funcnames 0 : { *(.debug_funcnames) }
|
||||
.debug_typenames 0 : { *(.debug_typenames) }
|
||||
.debug_varnames 0 : { *(.debug_varnames) }
|
||||
}
|
||||
|
|
@ -0,0 +1,15 @@
|
|||
; *************************************************************
|
||||
; *** Scatter-Loading Description File generated by uVision ***
|
||||
; *************************************************************
|
||||
|
||||
LR_IROM1 0x08000000 0x00200000 { ; load region size_region
|
||||
ER_IROM1 0x08000000 0x00200000 { ; load address = execution address
|
||||
*.o (RESET, +First)
|
||||
*(InRoot$$Sections)
|
||||
.ANY (+RO)
|
||||
}
|
||||
RW_IRAM1 0x20000000 0x00080000 { ; RW data
|
||||
.ANY (+RW +ZI)
|
||||
}
|
||||
}
|
||||
|
||||
Binary file not shown.
|
After Width: | Height: | Size: 602 KiB |
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,10 @@
|
|||
<?xml version="1.0" encoding="iso-8859-1"?>
|
||||
|
||||
<workspace>
|
||||
<project>
|
||||
<path>$WS_DIR$\project.ewp</path>
|
||||
</project>
|
||||
<batchBuild/>
|
||||
</workspace>
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,427 @@
|
|||
#ifndef RT_CONFIG_H__
|
||||
#define RT_CONFIG_H__
|
||||
|
||||
/* RT-Thread Kernel */
|
||||
|
||||
/* klibc options */
|
||||
|
||||
/* rt_vsnprintf options */
|
||||
|
||||
/* end of rt_vsnprintf options */
|
||||
|
||||
/* rt_vsscanf options */
|
||||
|
||||
/* end of rt_vsscanf options */
|
||||
|
||||
/* rt_memset options */
|
||||
|
||||
/* end of rt_memset options */
|
||||
|
||||
/* rt_memcpy options */
|
||||
|
||||
/* end of rt_memcpy options */
|
||||
|
||||
/* rt_memmove options */
|
||||
|
||||
/* end of rt_memmove options */
|
||||
|
||||
/* rt_memcmp options */
|
||||
|
||||
/* end of rt_memcmp options */
|
||||
|
||||
/* rt_strstr options */
|
||||
|
||||
/* end of rt_strstr options */
|
||||
|
||||
/* rt_strcasecmp options */
|
||||
|
||||
/* end of rt_strcasecmp options */
|
||||
|
||||
/* rt_strncpy options */
|
||||
|
||||
/* end of rt_strncpy options */
|
||||
|
||||
/* rt_strcpy options */
|
||||
|
||||
/* end of rt_strcpy options */
|
||||
|
||||
/* rt_strncmp options */
|
||||
|
||||
/* end of rt_strncmp options */
|
||||
|
||||
/* rt_strcmp options */
|
||||
|
||||
/* end of rt_strcmp options */
|
||||
|
||||
/* rt_strlen options */
|
||||
|
||||
/* end of rt_strlen options */
|
||||
|
||||
/* rt_strnlen options */
|
||||
|
||||
/* end of rt_strnlen options */
|
||||
/* end of klibc options */
|
||||
#define RT_NAME_MAX 8
|
||||
#define RT_CPUS_NR 1
|
||||
#define RT_ALIGN_SIZE 8
|
||||
#define RT_THREAD_PRIORITY_32
|
||||
#define RT_THREAD_PRIORITY_MAX 32
|
||||
#define RT_TICK_PER_SECOND 1000
|
||||
#define RT_USING_OVERFLOW_CHECK
|
||||
#define RT_USING_HOOK
|
||||
#define RT_HOOK_USING_FUNC_PTR
|
||||
#define RT_USING_IDLE_HOOK
|
||||
#define RT_IDLE_HOOK_LIST_SIZE 4
|
||||
#define IDLE_THREAD_STACK_SIZE 256
|
||||
#define RT_USING_TIMER_SOFT
|
||||
#define RT_TIMER_THREAD_PRIO 4
|
||||
#define RT_TIMER_THREAD_STACK_SIZE 512
|
||||
|
||||
/* kservice options */
|
||||
|
||||
/* end of kservice options */
|
||||
|
||||
/* Inter-Thread communication */
|
||||
|
||||
#define RT_USING_SEMAPHORE
|
||||
#define RT_USING_MUTEX
|
||||
#define RT_USING_EVENT
|
||||
#define RT_USING_MAILBOX
|
||||
#define RT_USING_MESSAGEQUEUE
|
||||
/* end of Inter-Thread communication */
|
||||
|
||||
/* Memory Management */
|
||||
|
||||
#define RT_USING_MEMPOOL
|
||||
#define RT_USING_SMALL_MEM
|
||||
#define RT_USING_SMALL_MEM_AS_HEAP
|
||||
#define RT_USING_HEAP
|
||||
/* end of Memory Management */
|
||||
#define RT_USING_DEVICE
|
||||
#define RT_USING_CONSOLE
|
||||
#define RT_CONSOLEBUF_SIZE 128
|
||||
#define RT_CONSOLE_DEVICE_NAME "uart0"
|
||||
#define RT_VER_NUM 0x50201
|
||||
#define RT_BACKTRACE_LEVEL_MAX_NR 32
|
||||
/* end of RT-Thread Kernel */
|
||||
#define RT_USING_HW_ATOMIC
|
||||
#define RT_USING_CPU_FFS
|
||||
#define ARCH_ARM
|
||||
#define ARCH_ARM_CORTEX_M
|
||||
#define ARCH_ARM_CORTEX_SECURE
|
||||
#define ARCH_ARM_CORTEX_M33
|
||||
|
||||
/* RT-Thread Components */
|
||||
|
||||
#define RT_USING_COMPONENTS_INIT
|
||||
#define RT_USING_USER_MAIN
|
||||
#define RT_MAIN_THREAD_STACK_SIZE 2048
|
||||
#define RT_MAIN_THREAD_PRIORITY 10
|
||||
#define RT_USING_MSH
|
||||
#define RT_USING_FINSH
|
||||
#define FINSH_USING_MSH
|
||||
#define FINSH_THREAD_NAME "tshell"
|
||||
#define FINSH_THREAD_PRIORITY 20
|
||||
#define FINSH_THREAD_STACK_SIZE 4096
|
||||
#define FINSH_USING_HISTORY
|
||||
#define FINSH_HISTORY_LINES 5
|
||||
#define FINSH_USING_SYMTAB
|
||||
#define FINSH_CMD_SIZE 80
|
||||
#define MSH_USING_BUILT_IN_COMMANDS
|
||||
#define FINSH_USING_DESCRIPTION
|
||||
#define FINSH_ARG_MAX 10
|
||||
#define FINSH_USING_OPTION_COMPLETION
|
||||
|
||||
/* DFS: device virtual file system */
|
||||
|
||||
#define RT_USING_DFS
|
||||
#define DFS_USING_POSIX
|
||||
#define DFS_USING_WORKDIR
|
||||
#define DFS_FD_MAX 16
|
||||
#define RT_USING_DFS_V1
|
||||
#define DFS_FILESYSTEMS_MAX 4
|
||||
#define DFS_FILESYSTEM_TYPES_MAX 4
|
||||
/* end of DFS: device virtual file system */
|
||||
|
||||
/* Device Drivers */
|
||||
|
||||
#define RT_USING_DEVICE_IPC
|
||||
#define RT_UNAMED_PIPE_NUMBER 64
|
||||
#define RT_USING_SERIAL
|
||||
#define RT_USING_SERIAL_V1
|
||||
#define RT_SERIAL_USING_DMA
|
||||
#define RT_SERIAL_RB_BUFSZ 64
|
||||
#define RT_USING_PIN
|
||||
/* end of Device Drivers */
|
||||
|
||||
/* C/C++ and POSIX layer */
|
||||
|
||||
/* ISO-ANSI C layer */
|
||||
|
||||
/* Timezone and Daylight Saving Time */
|
||||
|
||||
#define RT_LIBC_USING_LIGHT_TZ_DST
|
||||
#define RT_LIBC_TZ_DEFAULT_HOUR 8
|
||||
#define RT_LIBC_TZ_DEFAULT_MIN 0
|
||||
#define RT_LIBC_TZ_DEFAULT_SEC 0
|
||||
/* end of Timezone and Daylight Saving Time */
|
||||
/* end of ISO-ANSI C layer */
|
||||
|
||||
/* POSIX (Portable Operating System Interface) layer */
|
||||
|
||||
|
||||
/* Interprocess Communication (IPC) */
|
||||
|
||||
|
||||
/* Socket is in the 'Network' category */
|
||||
|
||||
/* end of Interprocess Communication (IPC) */
|
||||
/* end of POSIX (Portable Operating System Interface) layer */
|
||||
/* end of C/C++ and POSIX layer */
|
||||
|
||||
/* Network */
|
||||
|
||||
/* end of Network */
|
||||
|
||||
/* Memory protection */
|
||||
|
||||
/* end of Memory protection */
|
||||
|
||||
/* Utilities */
|
||||
|
||||
/* end of Utilities */
|
||||
|
||||
/* Using USB legacy version */
|
||||
|
||||
/* end of Using USB legacy version */
|
||||
/* end of RT-Thread Components */
|
||||
|
||||
/* RT-Thread Utestcases */
|
||||
|
||||
/* end of RT-Thread Utestcases */
|
||||
|
||||
/* RT-Thread online packages */
|
||||
|
||||
/* IoT - internet of things */
|
||||
|
||||
|
||||
/* Wi-Fi */
|
||||
|
||||
/* Marvell WiFi */
|
||||
|
||||
/* end of Marvell WiFi */
|
||||
|
||||
/* Wiced WiFi */
|
||||
|
||||
/* end of Wiced WiFi */
|
||||
|
||||
/* CYW43012 WiFi */
|
||||
|
||||
/* end of CYW43012 WiFi */
|
||||
|
||||
/* BL808 WiFi */
|
||||
|
||||
/* end of BL808 WiFi */
|
||||
|
||||
/* CYW43439 WiFi */
|
||||
|
||||
/* end of CYW43439 WiFi */
|
||||
/* end of Wi-Fi */
|
||||
|
||||
/* IoT Cloud */
|
||||
|
||||
/* end of IoT Cloud */
|
||||
/* end of IoT - internet of things */
|
||||
|
||||
/* security packages */
|
||||
|
||||
/* end of security packages */
|
||||
|
||||
/* language packages */
|
||||
|
||||
/* JSON: JavaScript Object Notation, a lightweight data-interchange format */
|
||||
|
||||
/* end of JSON: JavaScript Object Notation, a lightweight data-interchange format */
|
||||
|
||||
/* XML: Extensible Markup Language */
|
||||
|
||||
/* end of XML: Extensible Markup Language */
|
||||
/* end of language packages */
|
||||
|
||||
/* multimedia packages */
|
||||
|
||||
/* LVGL: powerful and easy-to-use embedded GUI library */
|
||||
|
||||
/* end of LVGL: powerful and easy-to-use embedded GUI library */
|
||||
|
||||
/* u8g2: a monochrome graphic library */
|
||||
|
||||
/* end of u8g2: a monochrome graphic library */
|
||||
/* end of multimedia packages */
|
||||
|
||||
/* tools packages */
|
||||
|
||||
/* end of tools packages */
|
||||
|
||||
/* system packages */
|
||||
|
||||
/* enhanced kernel services */
|
||||
|
||||
/* end of enhanced kernel services */
|
||||
|
||||
/* acceleration: Assembly language or algorithmic acceleration packages */
|
||||
|
||||
/* end of acceleration: Assembly language or algorithmic acceleration packages */
|
||||
|
||||
/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
|
||||
|
||||
/* end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
|
||||
|
||||
/* Micrium: Micrium software products porting for RT-Thread */
|
||||
|
||||
/* end of Micrium: Micrium software products porting for RT-Thread */
|
||||
/* end of system packages */
|
||||
|
||||
/* peripheral libraries and drivers */
|
||||
|
||||
/* HAL & SDK Drivers */
|
||||
|
||||
/* STM32 HAL & SDK Drivers */
|
||||
|
||||
/* end of STM32 HAL & SDK Drivers */
|
||||
|
||||
/* Infineon HAL Packages */
|
||||
|
||||
/* end of Infineon HAL Packages */
|
||||
|
||||
/* Kendryte SDK */
|
||||
|
||||
/* end of Kendryte SDK */
|
||||
|
||||
/* WCH HAL & SDK Drivers */
|
||||
|
||||
/* end of WCH HAL & SDK Drivers */
|
||||
|
||||
/* AT32 HAL & SDK Drivers */
|
||||
|
||||
/* end of AT32 HAL & SDK Drivers */
|
||||
|
||||
/* HC32 DDL Drivers */
|
||||
|
||||
/* end of HC32 DDL Drivers */
|
||||
|
||||
/* NXP HAL & SDK Drivers */
|
||||
|
||||
/* end of NXP HAL & SDK Drivers */
|
||||
|
||||
/* NUVOTON Drivers */
|
||||
|
||||
/* end of NUVOTON Drivers */
|
||||
|
||||
/* GD32 Drivers */
|
||||
|
||||
#define PKG_USING_GD32_ARM_CMSIS_DRIVER
|
||||
#define PKG_USING_GD32_ARM_CMSIS_DRIVER_LATEST_VERSION
|
||||
#define PKG_USING_GD32_ARM_SERIES_DRIVER
|
||||
#define PKG_USING_GD32_ARM_SERIES_DRIVER_LATEST_VERSION
|
||||
/* end of GD32 Drivers */
|
||||
/* end of HAL & SDK Drivers */
|
||||
|
||||
/* sensors drivers */
|
||||
|
||||
/* end of sensors drivers */
|
||||
|
||||
/* touch drivers */
|
||||
|
||||
/* end of touch drivers */
|
||||
/* end of peripheral libraries and drivers */
|
||||
|
||||
/* AI packages */
|
||||
|
||||
/* end of AI packages */
|
||||
|
||||
/* Signal Processing and Control Algorithm Packages */
|
||||
|
||||
/* end of Signal Processing and Control Algorithm Packages */
|
||||
|
||||
/* miscellaneous packages */
|
||||
|
||||
/* project laboratory */
|
||||
|
||||
/* end of project laboratory */
|
||||
|
||||
/* samples: kernel and components samples */
|
||||
|
||||
/* end of samples: kernel and components samples */
|
||||
|
||||
/* entertainment: terminal games and other interesting software packages */
|
||||
|
||||
/* end of entertainment: terminal games and other interesting software packages */
|
||||
/* end of miscellaneous packages */
|
||||
|
||||
/* Arduino libraries */
|
||||
|
||||
|
||||
/* Projects and Demos */
|
||||
|
||||
/* end of Projects and Demos */
|
||||
|
||||
/* Sensors */
|
||||
|
||||
/* end of Sensors */
|
||||
|
||||
/* Display */
|
||||
|
||||
/* end of Display */
|
||||
|
||||
/* Timing */
|
||||
|
||||
/* end of Timing */
|
||||
|
||||
/* Data Processing */
|
||||
|
||||
/* end of Data Processing */
|
||||
|
||||
/* Data Storage */
|
||||
|
||||
/* Communication */
|
||||
|
||||
/* end of Communication */
|
||||
|
||||
/* Device Control */
|
||||
|
||||
/* end of Device Control */
|
||||
|
||||
/* Other */
|
||||
|
||||
/* end of Other */
|
||||
|
||||
/* Signal IO */
|
||||
|
||||
/* end of Signal IO */
|
||||
|
||||
/* Uncategorized */
|
||||
|
||||
/* end of Arduino libraries */
|
||||
/* end of RT-Thread online packages */
|
||||
#define SOC_FAMILY_GD32
|
||||
#define SOC_SERIES_GD32F5xx
|
||||
|
||||
/* Hardware Drivers Config */
|
||||
|
||||
#define SOC_GD32527
|
||||
|
||||
/* Onboard Peripheral Drivers */
|
||||
|
||||
/* On-chip Peripheral Drivers */
|
||||
|
||||
#define BSP_USING_GPIO
|
||||
#define BSP_USING_UART
|
||||
#define BSP_USING_UART0
|
||||
/* end of On-chip Peripheral Drivers */
|
||||
|
||||
/* Board extended module Drivers */
|
||||
|
||||
/* end of Hardware Drivers Config */
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,184 @@
|
|||
import os
|
||||
|
||||
# toolchains options
|
||||
ARCH='arm'
|
||||
CPU='cortex-m33'
|
||||
CROSS_TOOL='keil'
|
||||
|
||||
# bsp lib config
|
||||
BSP_LIBRARY_TYPE = None
|
||||
|
||||
if os.getenv('RTT_CC'):
|
||||
CROSS_TOOL = os.getenv('RTT_CC')
|
||||
if os.getenv('RTT_ROOT'):
|
||||
RTT_ROOT = os.getenv('RTT_ROOT')
|
||||
|
||||
# cross_tool provides the cross compiler
|
||||
# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR
|
||||
if CROSS_TOOL == 'gcc':
|
||||
PLATFORM = 'gcc'
|
||||
EXEC_PATH = r'C:\Users\XXYYZZ'
|
||||
elif CROSS_TOOL == 'keil':
|
||||
PLATFORM = 'armclang'
|
||||
EXEC_PATH = r'C:/Keil_v5'
|
||||
elif CROSS_TOOL == 'iar':
|
||||
PLATFORM = 'iccarm'
|
||||
EXEC_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.3'
|
||||
|
||||
if os.getenv('RTT_EXEC_PATH'):
|
||||
EXEC_PATH = os.getenv('RTT_EXEC_PATH')
|
||||
|
||||
BUILD = 'debug'
|
||||
|
||||
if PLATFORM == 'gcc':
|
||||
# toolchains
|
||||
PREFIX = 'arm-none-eabi-'
|
||||
CC = PREFIX + 'gcc'
|
||||
AS = PREFIX + 'gcc'
|
||||
AR = PREFIX + 'ar'
|
||||
CXX = PREFIX + 'g++'
|
||||
LINK = PREFIX + 'gcc'
|
||||
TARGET_EXT = 'elf'
|
||||
SIZE = PREFIX + 'size'
|
||||
OBJDUMP = PREFIX + 'objdump'
|
||||
OBJCPY = PREFIX + 'objcopy'
|
||||
|
||||
DEVICE = ' -mcpu=cortex-m33 -mthumb -mfpu=fpv5-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections -DGD32F527'
|
||||
CFLAGS = DEVICE + ' -Dgcc'
|
||||
AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb '
|
||||
LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.ld'
|
||||
|
||||
CPATH = ''
|
||||
LPATH = ''
|
||||
|
||||
if BUILD == 'debug':
|
||||
CFLAGS += ' -O0 -gdwarf-2 -g'
|
||||
AFLAGS += ' -gdwarf-2'
|
||||
else:
|
||||
CFLAGS += ' -O2'
|
||||
|
||||
CXXFLAGS = CFLAGS
|
||||
|
||||
POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
|
||||
|
||||
elif PLATFORM == 'armclang':
|
||||
# toolchains
|
||||
CC = 'armclang'
|
||||
CXX = 'armclang'
|
||||
AS = 'armasm'
|
||||
AR = 'armar'
|
||||
LINK = 'armlink'
|
||||
TARGET_EXT = 'axf'
|
||||
|
||||
DEVICE = ' --cpu Cortex-M33.no_dsp '
|
||||
CFLAGS = ' --target=arm-arm-none-eabi -mcpu=cortex-m33+nodsp '
|
||||
CFLAGS += ' -mfpu=fpv5-sp-d16 '
|
||||
CFLAGS += ' -mfloat-abi=hard -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar '
|
||||
CFLAGS += ' -gdwarf-3 -ffunction-sections '
|
||||
AFLAGS = DEVICE + ' --apcs=interwork -mfpu=FPv5-SP'
|
||||
LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers '
|
||||
LFLAGS += ' --list rt-thread.map '
|
||||
LFLAGS += r' --strict --scatter "board\linker_scripts\link.sct" '
|
||||
CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCLANG/include'
|
||||
LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCLANG/lib'
|
||||
|
||||
EXEC_PATH += '/ARM/ARMCLANG/bin/'
|
||||
|
||||
if BUILD == 'debug':
|
||||
CFLAGS += ' -g -O1' # armclang recommend
|
||||
AFLAGS += ' -g'
|
||||
else:
|
||||
CFLAGS += ' -O2'
|
||||
|
||||
CXXFLAGS = CFLAGS
|
||||
CFLAGS += ' -std=c99'
|
||||
|
||||
POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET'
|
||||
|
||||
elif PLATFORM == 'armcc':
|
||||
# toolchains
|
||||
CC = 'armcc'
|
||||
CXX = 'armcc'
|
||||
AS = 'armasm'
|
||||
AR = 'armar'
|
||||
LINK = 'armlink'
|
||||
TARGET_EXT = 'axf'
|
||||
|
||||
DEVICE = ' --cpu Cortex-M33.fp '
|
||||
CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99'
|
||||
AFLAGS = DEVICE + ' --apcs=interwork '
|
||||
LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict'
|
||||
CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include'
|
||||
LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib'
|
||||
|
||||
CFLAGS += ' -D__MICROLIB '
|
||||
AFLAGS += ' --pd "__MICROLIB SETA 1" '
|
||||
LFLAGS += ' --library_type=microlib '
|
||||
EXEC_PATH += '/ARM/ARMCC/bin/'
|
||||
|
||||
if BUILD == 'debug':
|
||||
CFLAGS += ' -g -O0'
|
||||
AFLAGS += ' -g'
|
||||
else:
|
||||
CFLAGS += ' -O2'
|
||||
|
||||
CXXFLAGS = CFLAGS
|
||||
CFLAGS += ' -std=c99'
|
||||
|
||||
POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET'
|
||||
|
||||
elif PLATFORM == 'iccarm':
|
||||
# toolchains
|
||||
CC = 'iccarm'
|
||||
CXX = 'iccarm'
|
||||
AS = 'iasmarm'
|
||||
AR = 'iarchive'
|
||||
LINK = 'ilinkarm'
|
||||
TARGET_EXT = 'out'
|
||||
|
||||
DEVICE = '-Dewarm'
|
||||
|
||||
CFLAGS = DEVICE
|
||||
CFLAGS += ' --diag_suppress Pa050'
|
||||
CFLAGS += ' --no_cse'
|
||||
CFLAGS += ' --no_unroll'
|
||||
CFLAGS += ' --no_inline'
|
||||
CFLAGS += ' --no_code_motion'
|
||||
CFLAGS += ' --no_tbaa'
|
||||
CFLAGS += ' --no_clustering'
|
||||
CFLAGS += ' --no_scheduling'
|
||||
CFLAGS += ' --endian=little'
|
||||
CFLAGS += ' --cpu=Cortex-M33'
|
||||
CFLAGS += ' -e'
|
||||
CFLAGS += ' --fpu=VFPv5_sp'
|
||||
CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"'
|
||||
CFLAGS += ' --silent'
|
||||
|
||||
AFLAGS = DEVICE
|
||||
AFLAGS += ' -s+'
|
||||
AFLAGS += ' -w+'
|
||||
AFLAGS += ' -r'
|
||||
AFLAGS += ' --cpu Cortex-M33'
|
||||
AFLAGS += ' --fpu VFPv5_sp'
|
||||
AFLAGS += ' -S'
|
||||
|
||||
if BUILD == 'debug':
|
||||
CFLAGS += ' --debug'
|
||||
CFLAGS += ' -On'
|
||||
else:
|
||||
CFLAGS += ' -Oh'
|
||||
|
||||
LFLAGS = ' --config "board/linker_scripts/link.icf"'
|
||||
LFLAGS += ' --entry __iar_program_start'
|
||||
|
||||
CXXFLAGS = CFLAGS
|
||||
|
||||
EXEC_PATH = EXEC_PATH + '/arm/bin/'
|
||||
POST_ACTION = 'ielftool --bin $TARGET rtthread.bin'
|
||||
|
||||
def dist_handle(BSP_ROOT, dist_dir):
|
||||
import sys
|
||||
cwd_path = os.getcwd()
|
||||
sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools'))
|
||||
from sdk_dist import dist_do_building
|
||||
dist_do_building(BSP_ROOT, dist_dir)
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,190 @@
|
|||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
|
||||
|
||||
<SchemaVersion>1.0</SchemaVersion>
|
||||
|
||||
<Header>### uVision Project, (C) Keil Software</Header>
|
||||
|
||||
<Extensions>
|
||||
<cExt>*.c</cExt>
|
||||
<aExt>*.s*; *.src; *.a*</aExt>
|
||||
<oExt>*.obj; *.o</oExt>
|
||||
<lExt>*.lib</lExt>
|
||||
<tExt>*.txt; *.h; *.inc; *.md</tExt>
|
||||
<pExt>*.plm</pExt>
|
||||
<CppX>*.cpp</CppX>
|
||||
<nMigrate>0</nMigrate>
|
||||
</Extensions>
|
||||
|
||||
<DaveTm>
|
||||
<dwLowDateTime>0</dwLowDateTime>
|
||||
<dwHighDateTime>0</dwHighDateTime>
|
||||
</DaveTm>
|
||||
|
||||
<Target>
|
||||
<TargetName>rt-thread</TargetName>
|
||||
<ToolsetNumber>0x4</ToolsetNumber>
|
||||
<ToolsetName>ARM-ADS</ToolsetName>
|
||||
<TargetOption>
|
||||
<CLKADS>12000000</CLKADS>
|
||||
<OPTTT>
|
||||
<gFlags>1</gFlags>
|
||||
<BeepAtEnd>1</BeepAtEnd>
|
||||
<RunSim>0</RunSim>
|
||||
<RunTarget>1</RunTarget>
|
||||
<RunAbUc>0</RunAbUc>
|
||||
</OPTTT>
|
||||
<OPTHX>
|
||||
<HexSelection>1</HexSelection>
|
||||
<FlashByte>65535</FlashByte>
|
||||
<HexRangeLowAddress>0</HexRangeLowAddress>
|
||||
<HexRangeHighAddress>0</HexRangeHighAddress>
|
||||
<HexOffset>0</HexOffset>
|
||||
</OPTHX>
|
||||
<OPTLEX>
|
||||
<PageWidth>79</PageWidth>
|
||||
<PageLength>66</PageLength>
|
||||
<TabStop>8</TabStop>
|
||||
<ListingPath>.\build\</ListingPath>
|
||||
</OPTLEX>
|
||||
<ListingPage>
|
||||
<CreateCListing>1</CreateCListing>
|
||||
<CreateAListing>1</CreateAListing>
|
||||
<CreateLListing>1</CreateLListing>
|
||||
<CreateIListing>0</CreateIListing>
|
||||
<AsmCond>1</AsmCond>
|
||||
<AsmSymb>1</AsmSymb>
|
||||
<AsmXref>0</AsmXref>
|
||||
<CCond>1</CCond>
|
||||
<CCode>0</CCode>
|
||||
<CListInc>0</CListInc>
|
||||
<CSymb>0</CSymb>
|
||||
<LinkerCodeListing>0</LinkerCodeListing>
|
||||
</ListingPage>
|
||||
<OPTXL>
|
||||
<LMap>1</LMap>
|
||||
<LComments>1</LComments>
|
||||
<LGenerateSymbols>1</LGenerateSymbols>
|
||||
<LLibSym>1</LLibSym>
|
||||
<LLines>1</LLines>
|
||||
<LLocSym>1</LLocSym>
|
||||
<LPubSym>1</LPubSym>
|
||||
<LXref>0</LXref>
|
||||
<LExpSel>0</LExpSel>
|
||||
</OPTXL>
|
||||
<OPTFL>
|
||||
<tvExp>1</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<IsCurrentTarget>1</IsCurrentTarget>
|
||||
</OPTFL>
|
||||
<CpuCode>255</CpuCode>
|
||||
<DebugOpt>
|
||||
<uSim>0</uSim>
|
||||
<uTrg>1</uTrg>
|
||||
<sLdApp>1</sLdApp>
|
||||
<sGomain>1</sGomain>
|
||||
<sRbreak>1</sRbreak>
|
||||
<sRwatch>1</sRwatch>
|
||||
<sRmem>1</sRmem>
|
||||
<sRfunc>1</sRfunc>
|
||||
<sRbox>1</sRbox>
|
||||
<tLdApp>1</tLdApp>
|
||||
<tGomain>1</tGomain>
|
||||
<tRbreak>1</tRbreak>
|
||||
<tRwatch>1</tRwatch>
|
||||
<tRmem>1</tRmem>
|
||||
<tRfunc>0</tRfunc>
|
||||
<tRbox>1</tRbox>
|
||||
<tRtrace>1</tRtrace>
|
||||
<sRSysVw>1</sRSysVw>
|
||||
<tRSysVw>1</tRSysVw>
|
||||
<sRunDeb>0</sRunDeb>
|
||||
<sLrtime>0</sLrtime>
|
||||
<bEvRecOn>1</bEvRecOn>
|
||||
<bSchkAxf>0</bSchkAxf>
|
||||
<bTchkAxf>0</bTchkAxf>
|
||||
<nTsel>14</nTsel>
|
||||
<sDll></sDll>
|
||||
<sDllPa></sDllPa>
|
||||
<sDlgDll></sDlgDll>
|
||||
<sDlgPa></sDlgPa>
|
||||
<sIfile></sIfile>
|
||||
<tDll></tDll>
|
||||
<tDllPa></tDllPa>
|
||||
<tDlgDll></tDlgDll>
|
||||
<tDlgPa></tDlgPa>
|
||||
<tIfile></tIfile>
|
||||
<pMon>BIN\CMSIS_AGDI_V8M.DLL</pMon>
|
||||
</DebugOpt>
|
||||
<TargetDriverDllRegistry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>CMSIS_AGDI_V8M</Key>
|
||||
<Name>-X"Any" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BE12477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC80000 -FN1 -FF0GD32F5xx_7M.FLM -FS08000000 -FL0780000 -FP0($$Device:GD32F527IS$Flash\GD32F5xx_7M.FLM)</Name>
|
||||
</SetRegEntry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>UL2V8M</Key>
|
||||
<Name>UL2V8M(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0GD32F5xx_7M -FS08000000 -FL0780000 -FP0($$Device:GD32F527IS$Flash\GD32F5xx_7M.FLM))</Name>
|
||||
</SetRegEntry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>CMSIS_AGDI</Key>
|
||||
<Name>UL2V8M(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0GD32F5xx_7M -FS08000000 -FL0780000 -FP0($$Device:GD32F527IS$Flash\GD32F5xx_7M.FLM))</Name>
|
||||
</SetRegEntry>
|
||||
</TargetDriverDllRegistry>
|
||||
<Breakpoint/>
|
||||
<Tracepoint>
|
||||
<THDelay>0</THDelay>
|
||||
</Tracepoint>
|
||||
<DebugFlag>
|
||||
<trace>0</trace>
|
||||
<periodic>0</periodic>
|
||||
<aLwin>0</aLwin>
|
||||
<aCover>0</aCover>
|
||||
<aSer1>0</aSer1>
|
||||
<aSer2>0</aSer2>
|
||||
<aPa>0</aPa>
|
||||
<viewmode>0</viewmode>
|
||||
<vrSel>0</vrSel>
|
||||
<aSym>0</aSym>
|
||||
<aTbox>0</aTbox>
|
||||
<AscS1>0</AscS1>
|
||||
<AscS2>0</AscS2>
|
||||
<AscS3>0</AscS3>
|
||||
<aSer3>0</aSer3>
|
||||
<eProf>0</eProf>
|
||||
<aLa>0</aLa>
|
||||
<aPa1>0</aPa1>
|
||||
<AscS4>0</AscS4>
|
||||
<aSer4>0</aSer4>
|
||||
<StkLoc>0</StkLoc>
|
||||
<TrcWin>0</TrcWin>
|
||||
<newCpu>0</newCpu>
|
||||
<uProt>0</uProt>
|
||||
</DebugFlag>
|
||||
<LintExecutable></LintExecutable>
|
||||
<LintConfigFile></LintConfigFile>
|
||||
<bLintAuto>0</bLintAuto>
|
||||
<bAutoGenD>0</bAutoGenD>
|
||||
<LntExFlags>0</LntExFlags>
|
||||
<pMisraName></pMisraName>
|
||||
<pszMrule></pszMrule>
|
||||
<pSingCmds></pSingCmds>
|
||||
<pMultCmds></pMultCmds>
|
||||
<pMisraNamep></pMisraNamep>
|
||||
<pszMrulep></pszMrulep>
|
||||
<pSingCmdsp></pSingCmdsp>
|
||||
<pMultCmdsp></pMultCmdsp>
|
||||
</TargetOption>
|
||||
</Target>
|
||||
|
||||
<Group>
|
||||
<GroupName>::CMSIS</GroupName>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<cbSel>0</cbSel>
|
||||
<RteFlg>1</RteFlg>
|
||||
</Group>
|
||||
|
||||
</ProjectOpt>
|
||||
|
|
@ -0,0 +1,628 @@
|
|||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_proj.xsd">
|
||||
|
||||
<SchemaVersion>1.1</SchemaVersion>
|
||||
|
||||
<Header>### uVision Project, (C) Keil Software</Header>
|
||||
|
||||
<Targets>
|
||||
<Target>
|
||||
<TargetName>rt-thread</TargetName>
|
||||
<ToolsetNumber>0x4</ToolsetNumber>
|
||||
<ToolsetName>ARM-ADS</ToolsetName>
|
||||
<uAC6>0</uAC6>
|
||||
<TargetOption>
|
||||
<TargetCommonOption>
|
||||
<Device>GD32F450ZK</Device>
|
||||
<Vendor>GigaDevice</Vendor>
|
||||
<Cpu>IRAM(0x20000000-0x20030000) IRAM2(0x10000000-0x10010000) IROM(0x08000000-0x08300000) CLOCK(25000000) CPUTYPE("Cortex-M4") FPU2</Cpu>
|
||||
<FlashUtilSpec></FlashUtilSpec>
|
||||
<StartupFile>"Startup\GD\GD32F4xx\startup_gd32f4xx.s" ("GD32F4xx Startup Code")</StartupFile>
|
||||
<FlashDriverDll>UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC800 -FN1 -FF0GD32F4xx_3MB -FS08000000 -FL0300000)</FlashDriverDll>
|
||||
<DeviceId>0</DeviceId>
|
||||
<RegisterFile>gd32f4xx0.h</RegisterFile>
|
||||
<MemoryEnv></MemoryEnv>
|
||||
<Cmp></Cmp>
|
||||
<Asm></Asm>
|
||||
<Linker></Linker>
|
||||
<OHString></OHString>
|
||||
<InfinionOptionDll></InfinionOptionDll>
|
||||
<SLE66CMisc></SLE66CMisc>
|
||||
<SLE66AMisc></SLE66AMisc>
|
||||
<SLE66LinkerMisc></SLE66LinkerMisc>
|
||||
<SFDFile>SFD\GD\GD32F4xx\GD32F4xx.SFR</SFDFile>
|
||||
<bCustSvd>0</bCustSvd>
|
||||
<UseEnv>0</UseEnv>
|
||||
<BinPath></BinPath>
|
||||
<IncludePath></IncludePath>
|
||||
<LibPath></LibPath>
|
||||
<RegisterFilePath>GD\GD32F4xx\</RegisterFilePath>
|
||||
<DBRegisterFilePath>GD\GD32F4xx\</DBRegisterFilePath>
|
||||
<TargetStatus>
|
||||
<Error>0</Error>
|
||||
<ExitCodeStop>0</ExitCodeStop>
|
||||
<ButtonStop>0</ButtonStop>
|
||||
<NotGenerated>0</NotGenerated>
|
||||
<InvalidFlash>1</InvalidFlash>
|
||||
</TargetStatus>
|
||||
<OutputDirectory>.\output\</OutputDirectory>
|
||||
<OutputName>rtthread</OutputName>
|
||||
<CreateExecutable>1</CreateExecutable>
|
||||
<CreateLib>0</CreateLib>
|
||||
<CreateHexFile>1</CreateHexFile>
|
||||
<DebugInformation>1</DebugInformation>
|
||||
<BrowseInformation>1</BrowseInformation>
|
||||
<ListingPath>.\build\</ListingPath>
|
||||
<HexFormatSelection>1</HexFormatSelection>
|
||||
<Merge32K>0</Merge32K>
|
||||
<CreateBatchFile>0</CreateBatchFile>
|
||||
<BeforeCompile>
|
||||
<RunUserProg1>0</RunUserProg1>
|
||||
<RunUserProg2>0</RunUserProg2>
|
||||
<UserProg1Name></UserProg1Name>
|
||||
<UserProg2Name></UserProg2Name>
|
||||
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||
<nStopU1X>0</nStopU1X>
|
||||
<nStopU2X>0</nStopU2X>
|
||||
</BeforeCompile>
|
||||
<BeforeMake>
|
||||
<RunUserProg1>0</RunUserProg1>
|
||||
<RunUserProg2>0</RunUserProg2>
|
||||
<UserProg1Name></UserProg1Name>
|
||||
<UserProg2Name></UserProg2Name>
|
||||
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||
<nStopB1X>0</nStopB1X>
|
||||
<nStopB2X>0</nStopB2X>
|
||||
</BeforeMake>
|
||||
<AfterMake>
|
||||
<RunUserProg1>0</RunUserProg1>
|
||||
<RunUserProg2>0</RunUserProg2>
|
||||
<UserProg1Name></UserProg1Name>
|
||||
<UserProg2Name></UserProg2Name>
|
||||
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||
<nStopA1X>0</nStopA1X>
|
||||
<nStopA2X>0</nStopA2X>
|
||||
</AfterMake>
|
||||
<SelectedForBatchBuild>0</SelectedForBatchBuild>
|
||||
<SVCSIdString></SVCSIdString>
|
||||
</TargetCommonOption>
|
||||
<CommonProperty>
|
||||
<UseCPPCompiler>0</UseCPPCompiler>
|
||||
<RVCTCodeConst>0</RVCTCodeConst>
|
||||
<RVCTZI>0</RVCTZI>
|
||||
<RVCTOtherData>0</RVCTOtherData>
|
||||
<ModuleSelection>0</ModuleSelection>
|
||||
<IncludeInBuild>1</IncludeInBuild>
|
||||
<AlwaysBuild>0</AlwaysBuild>
|
||||
<GenerateAssemblyFile>0</GenerateAssemblyFile>
|
||||
<AssembleAssemblyFile>0</AssembleAssemblyFile>
|
||||
<PublicsOnly>0</PublicsOnly>
|
||||
<StopOnExitCode>3</StopOnExitCode>
|
||||
<CustomArgument></CustomArgument>
|
||||
<IncludeLibraryModules></IncludeLibraryModules>
|
||||
<ComprImg>1</ComprImg>
|
||||
</CommonProperty>
|
||||
<DllOption>
|
||||
<SimDllName>SARMCM3.DLL</SimDllName>
|
||||
<SimDllArguments> -REMAP</SimDllArguments>
|
||||
<SimDlgDll>DCM.DLL</SimDlgDll>
|
||||
<SimDlgDllArguments>-pCM3</SimDlgDllArguments>
|
||||
<TargetDllName>SARMCM3.DLL</TargetDllName>
|
||||
<TargetDllArguments></TargetDllArguments>
|
||||
<TargetDlgDll>TCM.DLL</TargetDlgDll>
|
||||
<TargetDlgDllArguments>-pCM3</TargetDlgDllArguments>
|
||||
</DllOption>
|
||||
<DebugOption>
|
||||
<OPTHX>
|
||||
<HexSelection>1</HexSelection>
|
||||
<HexRangeLowAddress>0</HexRangeLowAddress>
|
||||
<HexRangeHighAddress>0</HexRangeHighAddress>
|
||||
<HexOffset>0</HexOffset>
|
||||
<Oh166RecLen>16</Oh166RecLen>
|
||||
</OPTHX>
|
||||
<Simulator>
|
||||
<UseSimulator>0</UseSimulator>
|
||||
<LoadApplicationAtStartup>1</LoadApplicationAtStartup>
|
||||
<RunToMain>1</RunToMain>
|
||||
<RestoreBreakpoints>1</RestoreBreakpoints>
|
||||
<RestoreWatchpoints>1</RestoreWatchpoints>
|
||||
<RestoreMemoryDisplay>1</RestoreMemoryDisplay>
|
||||
<RestoreFunctions>1</RestoreFunctions>
|
||||
<RestoreToolbox>1</RestoreToolbox>
|
||||
<LimitSpeedToRealTime>0</LimitSpeedToRealTime>
|
||||
<RestoreSysVw>1</RestoreSysVw>
|
||||
</Simulator>
|
||||
<Target>
|
||||
<UseTarget>1</UseTarget>
|
||||
<LoadApplicationAtStartup>1</LoadApplicationAtStartup>
|
||||
<RunToMain>1</RunToMain>
|
||||
<RestoreBreakpoints>1</RestoreBreakpoints>
|
||||
<RestoreWatchpoints>1</RestoreWatchpoints>
|
||||
<RestoreMemoryDisplay>1</RestoreMemoryDisplay>
|
||||
<RestoreFunctions>0</RestoreFunctions>
|
||||
<RestoreToolbox>1</RestoreToolbox>
|
||||
<RestoreTracepoints>0</RestoreTracepoints>
|
||||
<RestoreSysVw>1</RestoreSysVw>
|
||||
</Target>
|
||||
<RunDebugAfterBuild>0</RunDebugAfterBuild>
|
||||
<TargetSelection>3</TargetSelection>
|
||||
<SimDlls>
|
||||
<CpuDll></CpuDll>
|
||||
<CpuDllArguments></CpuDllArguments>
|
||||
<PeripheralDll></PeripheralDll>
|
||||
<PeripheralDllArguments></PeripheralDllArguments>
|
||||
<InitializationFile></InitializationFile>
|
||||
</SimDlls>
|
||||
<TargetDlls>
|
||||
<CpuDll></CpuDll>
|
||||
<CpuDllArguments></CpuDllArguments>
|
||||
<PeripheralDll></PeripheralDll>
|
||||
<PeripheralDllArguments></PeripheralDllArguments>
|
||||
<InitializationFile></InitializationFile>
|
||||
<Driver>BIN\CMSIS_AGDI.dll</Driver>
|
||||
</TargetDlls>
|
||||
</DebugOption>
|
||||
<Utilities>
|
||||
<Flash1>
|
||||
<UseTargetDll>1</UseTargetDll>
|
||||
<UseExternalTool>0</UseExternalTool>
|
||||
<RunIndependent>0</RunIndependent>
|
||||
<UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
|
||||
<Capability>1</Capability>
|
||||
<DriverSelection>4096</DriverSelection>
|
||||
</Flash1>
|
||||
<bUseTDR>1</bUseTDR>
|
||||
<Flash2>BIN\UL2CM3.DLL</Flash2>
|
||||
<Flash3>"" ()</Flash3>
|
||||
<Flash4></Flash4>
|
||||
<pFcarmOut></pFcarmOut>
|
||||
<pFcarmGrp></pFcarmGrp>
|
||||
<pFcArmRoot></pFcArmRoot>
|
||||
<FcArmLst>0</FcArmLst>
|
||||
</Utilities>
|
||||
<TargetArmAds>
|
||||
<ArmAdsMisc>
|
||||
<GenerateListings>0</GenerateListings>
|
||||
<asHll>1</asHll>
|
||||
<asAsm>1</asAsm>
|
||||
<asMacX>1</asMacX>
|
||||
<asSyms>1</asSyms>
|
||||
<asFals>1</asFals>
|
||||
<asDbgD>1</asDbgD>
|
||||
<asForm>1</asForm>
|
||||
<ldLst>0</ldLst>
|
||||
<ldmm>1</ldmm>
|
||||
<ldXref>1</ldXref>
|
||||
<BigEnd>0</BigEnd>
|
||||
<AdsALst>1</AdsALst>
|
||||
<AdsACrf>1</AdsACrf>
|
||||
<AdsANop>0</AdsANop>
|
||||
<AdsANot>0</AdsANot>
|
||||
<AdsLLst>1</AdsLLst>
|
||||
<AdsLmap>1</AdsLmap>
|
||||
<AdsLcgr>1</AdsLcgr>
|
||||
<AdsLsym>1</AdsLsym>
|
||||
<AdsLszi>1</AdsLszi>
|
||||
<AdsLtoi>1</AdsLtoi>
|
||||
<AdsLsun>1</AdsLsun>
|
||||
<AdsLven>1</AdsLven>
|
||||
<AdsLsxf>1</AdsLsxf>
|
||||
<RvctClst>0</RvctClst>
|
||||
<GenPPlst>0</GenPPlst>
|
||||
<AdsCpuType>"Cortex-M4"</AdsCpuType>
|
||||
<RvctDeviceName></RvctDeviceName>
|
||||
<mOS>0</mOS>
|
||||
<uocRom>0</uocRom>
|
||||
<uocRam>0</uocRam>
|
||||
<hadIROM>1</hadIROM>
|
||||
<hadIRAM>1</hadIRAM>
|
||||
<hadXRAM>0</hadXRAM>
|
||||
<uocXRam>0</uocXRam>
|
||||
<RvdsVP>2</RvdsVP>
|
||||
<hadIRAM2>1</hadIRAM2>
|
||||
<hadIROM2>0</hadIROM2>
|
||||
<StupSel>8</StupSel>
|
||||
<useUlib>1</useUlib>
|
||||
<EndSel>0</EndSel>
|
||||
<uLtcg>0</uLtcg>
|
||||
<nSecure>0</nSecure>
|
||||
<RoSelD>3</RoSelD>
|
||||
<RwSelD>3</RwSelD>
|
||||
<CodeSel>0</CodeSel>
|
||||
<OptFeed>0</OptFeed>
|
||||
<NoZi1>0</NoZi1>
|
||||
<NoZi2>0</NoZi2>
|
||||
<NoZi3>0</NoZi3>
|
||||
<NoZi4>0</NoZi4>
|
||||
<NoZi5>0</NoZi5>
|
||||
<Ro1Chk>0</Ro1Chk>
|
||||
<Ro2Chk>0</Ro2Chk>
|
||||
<Ro3Chk>0</Ro3Chk>
|
||||
<Ir1Chk>1</Ir1Chk>
|
||||
<Ir2Chk>0</Ir2Chk>
|
||||
<Ra1Chk>0</Ra1Chk>
|
||||
<Ra2Chk>0</Ra2Chk>
|
||||
<Ra3Chk>0</Ra3Chk>
|
||||
<Im1Chk>1</Im1Chk>
|
||||
<Im2Chk>0</Im2Chk>
|
||||
<OnChipMemories>
|
||||
<Ocm1>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm1>
|
||||
<Ocm2>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm2>
|
||||
<Ocm3>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm3>
|
||||
<Ocm4>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm4>
|
||||
<Ocm5>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm5>
|
||||
<Ocm6>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm6>
|
||||
<IRAM>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x20000000</StartAddress>
|
||||
<Size>0x30000</Size>
|
||||
</IRAM>
|
||||
<IROM>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x8000000</StartAddress>
|
||||
<Size>0x300000</Size>
|
||||
</IROM>
|
||||
<XRAM>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</XRAM>
|
||||
<OCR_RVCT1>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT1>
|
||||
<OCR_RVCT2>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT2>
|
||||
<OCR_RVCT3>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT3>
|
||||
<OCR_RVCT4>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x8000000</StartAddress>
|
||||
<Size>0x300000</Size>
|
||||
</OCR_RVCT4>
|
||||
<OCR_RVCT5>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT5>
|
||||
<OCR_RVCT6>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT6>
|
||||
<OCR_RVCT7>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT7>
|
||||
<OCR_RVCT8>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT8>
|
||||
<OCR_RVCT9>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x20000000</StartAddress>
|
||||
<Size>0x30000</Size>
|
||||
</OCR_RVCT9>
|
||||
<OCR_RVCT10>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x10000000</StartAddress>
|
||||
<Size>0x10000</Size>
|
||||
</OCR_RVCT10>
|
||||
</OnChipMemories>
|
||||
<RvctStartVector></RvctStartVector>
|
||||
</ArmAdsMisc>
|
||||
<Cads>
|
||||
<interw>1</interw>
|
||||
<Optim>1</Optim>
|
||||
<oTime>0</oTime>
|
||||
<SplitLS>0</SplitLS>
|
||||
<OneElfS>1</OneElfS>
|
||||
<Strict>0</Strict>
|
||||
<EnumInt>0</EnumInt>
|
||||
<PlainCh>0</PlainCh>
|
||||
<Ropi>0</Ropi>
|
||||
<Rwpi>0</Rwpi>
|
||||
<wLevel>2</wLevel>
|
||||
<uThumb>0</uThumb>
|
||||
<uSurpInc>0</uSurpInc>
|
||||
<uC99>1</uC99>
|
||||
<uGnu>0</uGnu>
|
||||
<useXO>0</useXO>
|
||||
<v6Lang>1</v6Lang>
|
||||
<v6LangP>1</v6LangP>
|
||||
<vShortEn>1</vShortEn>
|
||||
<vShortWch>1</vShortWch>
|
||||
<v6Lto>0</v6Lto>
|
||||
<v6WtE>0</v6WtE>
|
||||
<v6Rtti>0</v6Rtti>
|
||||
<VariousControls>
|
||||
<MiscControls></MiscControls>
|
||||
<Define></Define>
|
||||
<Undefine></Undefine>
|
||||
<IncludePath>..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Include;..\..\..\Library\Firmware\CMSIS\GD\GD32F4xx\Include;..\..\..\Library\Utilities;..\</IncludePath>
|
||||
</VariousControls>
|
||||
</Cads>
|
||||
<Aads>
|
||||
<interw>1</interw>
|
||||
<Ropi>0</Ropi>
|
||||
<Rwpi>0</Rwpi>
|
||||
<thumb>0</thumb>
|
||||
<SplitLS>0</SplitLS>
|
||||
<SwStkChk>0</SwStkChk>
|
||||
<NoWarn>0</NoWarn>
|
||||
<uSurpInc>0</uSurpInc>
|
||||
<useXO>0</useXO>
|
||||
<uClangAs>0</uClangAs>
|
||||
<VariousControls>
|
||||
<MiscControls></MiscControls>
|
||||
<Define></Define>
|
||||
<Undefine></Undefine>
|
||||
<IncludePath></IncludePath>
|
||||
</VariousControls>
|
||||
</Aads>
|
||||
<LDads>
|
||||
<umfTarg>1</umfTarg>
|
||||
<Ropi>0</Ropi>
|
||||
<Rwpi>0</Rwpi>
|
||||
<noStLib>0</noStLib>
|
||||
<RepFail>1</RepFail>
|
||||
<useFile>0</useFile>
|
||||
<TextAddressRange>0x08000000</TextAddressRange>
|
||||
<DataAddressRange>0x20000000</DataAddressRange>
|
||||
<pXoBase></pXoBase>
|
||||
<ScatterFile></ScatterFile>
|
||||
<IncludeLibs></IncludeLibs>
|
||||
<IncludeLibsPath></IncludeLibsPath>
|
||||
<Misc></Misc>
|
||||
<LinkerInputFile></LinkerInputFile>
|
||||
<DisabledWarnings></DisabledWarnings>
|
||||
</LDads>
|
||||
</TargetArmAds>
|
||||
</TargetOption>
|
||||
<Groups>
|
||||
<Group>
|
||||
<GroupName>Application</GroupName>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>main.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\main.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>gd32f4xx_it.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\gd32f4xx_it.c</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
</Group>
|
||||
<Group>
|
||||
<GroupName>CMSIS</GroupName>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>system_gd32f4xx.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\Library\Firmware\CMSIS\GD\GD32F4xx\Source\system_gd32f4xx.c</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
</Group>
|
||||
<Group>
|
||||
<GroupName>GD32F4xx_Peripherals</GroupName>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>gd32f4xx_adc.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_adc.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>gd32f4xx_can.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_can.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>gd32f4xx_crc.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_crc.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>gd32f4xx_ctc.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_ctc.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>gd32f4xx_dac.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_dac.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>gd32f4xx_dbg.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_dbg.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>gd32f4xx_dci.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_dci.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>gd32f4xx_dma.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_dma.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>gd32f4xx_enet.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_enet.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>gd32f4xx_exmc.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_exmc.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>gd32f4xx_exti.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_exti.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>gd32f4xx_fmc.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_fmc.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>gd32f4xx_fwdgt.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_fwdgt.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>gd32f4xx_gpio.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_gpio.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>gd32f4xx_i2c.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_i2c.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>gd32f4xx_ipa.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_ipa.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>gd32f4xx_iref.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_iref.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>gd32f4xx_misc.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_misc.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>gd32f4xx_pmu.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_pmu.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>gd32f4xx_rcu.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_rcu.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>gd32f4xx_rtc.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_rtc.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>gd32f4xx_sdio.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_sdio.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>gd32f4xx_spi.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_spi.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>gd32f4xx_syscfg.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_syscfg.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>gd32f4xx_timer.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_timer.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>gd32f4xx_tli.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_tli.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>gd32f4xx_trng.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_trng.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>gd32f4xx_usart.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_usart.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>gd32f4xx_wwdgt.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_wwdgt.c</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
</Group>
|
||||
<Group>
|
||||
<GroupName>GD32F4xx_EVAL</GroupName>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>gd32f450z_eval.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\Library\Utilities\gd32f450z_eval.c</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
</Group>
|
||||
<Group>
|
||||
<GroupName>Startup</GroupName>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>startup_gd32f4xx.s</FileName>
|
||||
<FileType>2</FileType>
|
||||
<FilePath>..\..\..\Library\Firmware\CMSIS\GD\GD32F4xx\Source\ARM\startup_gd32f4xx.s</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
</Group>
|
||||
<Group>
|
||||
<GroupName>Doc</GroupName>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>readme.txt</FileName>
|
||||
<FileType>5</FileType>
|
||||
<FilePath>..\readme.txt</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
</Group>
|
||||
</Groups>
|
||||
</Target>
|
||||
</Targets>
|
||||
|
||||
</Project>
|
||||
|
|
@ -0,0 +1,413 @@
|
|||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
|
||||
|
||||
<SchemaVersion>2.1</SchemaVersion>
|
||||
|
||||
<Header>### uVision Project, (C) Keil Software</Header>
|
||||
|
||||
<Targets>
|
||||
<Target>
|
||||
<TargetName>rt-thread</TargetName>
|
||||
<ToolsetNumber>0x4</ToolsetNumber>
|
||||
<ToolsetName>ARM-ADS</ToolsetName>
|
||||
<uAC6>1</uAC6>
|
||||
<TargetOption>
|
||||
<TargetCommonOption>
|
||||
<Device>GD32F527IS</Device>
|
||||
<Vendor>GigaDevice</Vendor>
|
||||
<PackID>GigaDevice.GD32F5xx_DFP.1.2.1</PackID>
|
||||
<PackURL>https://gd32mcu.com/data/documents/pack/</PackURL>
|
||||
<Cpu>IRAM(0x20000000,0x080000) IROM(0x08000000,0x780000) CPUTYPE("Cortex-M33") FPU3(SFPU) DSP CLOCK(12000000) ELITTLE</Cpu>
|
||||
<FlashUtilSpec></FlashUtilSpec>
|
||||
<StartupFile></StartupFile>
|
||||
<FlashDriverDll>UL2V8M(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0GD32F5xx_7M -FS08000000 -FL0780000 -FP0($$Device:GD32F527IS$Flash\GD32F5xx_7M.FLM))</FlashDriverDll>
|
||||
<DeviceId>0</DeviceId>
|
||||
<RegisterFile></RegisterFile>
|
||||
<MemoryEnv></MemoryEnv>
|
||||
<Cmp></Cmp>
|
||||
<Asm></Asm>
|
||||
<Linker></Linker>
|
||||
<OHString></OHString>
|
||||
<InfinionOptionDll></InfinionOptionDll>
|
||||
<SLE66CMisc></SLE66CMisc>
|
||||
<SLE66AMisc></SLE66AMisc>
|
||||
<SLE66LinkerMisc></SLE66LinkerMisc>
|
||||
<SFDFile>$$Device:GD32F527IS$SVD\GD32F5xx.svd</SFDFile>
|
||||
<bCustSvd>0</bCustSvd>
|
||||
<UseEnv>0</UseEnv>
|
||||
<BinPath></BinPath>
|
||||
<IncludePath></IncludePath>
|
||||
<LibPath></LibPath>
|
||||
<RegisterFilePath></RegisterFilePath>
|
||||
<DBRegisterFilePath></DBRegisterFilePath>
|
||||
<TargetStatus>
|
||||
<Error>0</Error>
|
||||
<ExitCodeStop>0</ExitCodeStop>
|
||||
<ButtonStop>0</ButtonStop>
|
||||
<NotGenerated>0</NotGenerated>
|
||||
<InvalidFlash>1</InvalidFlash>
|
||||
</TargetStatus>
|
||||
<OutputDirectory>.\build\</OutputDirectory>
|
||||
<OutputName>rtthread</OutputName>
|
||||
<CreateExecutable>1</CreateExecutable>
|
||||
<CreateLib>0</CreateLib>
|
||||
<CreateHexFile>0</CreateHexFile>
|
||||
<DebugInformation>1</DebugInformation>
|
||||
<BrowseInformation>0</BrowseInformation>
|
||||
<ListingPath>.\build\</ListingPath>
|
||||
<HexFormatSelection>1</HexFormatSelection>
|
||||
<Merge32K>0</Merge32K>
|
||||
<CreateBatchFile>0</CreateBatchFile>
|
||||
<BeforeCompile>
|
||||
<RunUserProg1>0</RunUserProg1>
|
||||
<RunUserProg2>0</RunUserProg2>
|
||||
<UserProg1Name></UserProg1Name>
|
||||
<UserProg2Name></UserProg2Name>
|
||||
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||
<nStopU1X>0</nStopU1X>
|
||||
<nStopU2X>0</nStopU2X>
|
||||
</BeforeCompile>
|
||||
<BeforeMake>
|
||||
<RunUserProg1>0</RunUserProg1>
|
||||
<RunUserProg2>0</RunUserProg2>
|
||||
<UserProg1Name></UserProg1Name>
|
||||
<UserProg2Name></UserProg2Name>
|
||||
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||
<nStopB1X>0</nStopB1X>
|
||||
<nStopB2X>0</nStopB2X>
|
||||
</BeforeMake>
|
||||
<AfterMake>
|
||||
<RunUserProg1>1</RunUserProg1>
|
||||
<RunUserProg2>0</RunUserProg2>
|
||||
<UserProg1Name>fromelf --bin !L --output rtthread.bin</UserProg1Name>
|
||||
<UserProg2Name></UserProg2Name>
|
||||
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||
<nStopA1X>0</nStopA1X>
|
||||
<nStopA2X>0</nStopA2X>
|
||||
</AfterMake>
|
||||
<SelectedForBatchBuild>0</SelectedForBatchBuild>
|
||||
<SVCSIdString></SVCSIdString>
|
||||
</TargetCommonOption>
|
||||
<CommonProperty>
|
||||
<UseCPPCompiler>0</UseCPPCompiler>
|
||||
<RVCTCodeConst>0</RVCTCodeConst>
|
||||
<RVCTZI>0</RVCTZI>
|
||||
<RVCTOtherData>0</RVCTOtherData>
|
||||
<ModuleSelection>0</ModuleSelection>
|
||||
<IncludeInBuild>1</IncludeInBuild>
|
||||
<AlwaysBuild>0</AlwaysBuild>
|
||||
<GenerateAssemblyFile>0</GenerateAssemblyFile>
|
||||
<AssembleAssemblyFile>0</AssembleAssemblyFile>
|
||||
<PublicsOnly>0</PublicsOnly>
|
||||
<StopOnExitCode>3</StopOnExitCode>
|
||||
<CustomArgument></CustomArgument>
|
||||
<IncludeLibraryModules></IncludeLibraryModules>
|
||||
<ComprImg>1</ComprImg>
|
||||
</CommonProperty>
|
||||
<DllOption>
|
||||
<SimDllName></SimDllName>
|
||||
<SimDllArguments></SimDllArguments>
|
||||
<SimDlgDll></SimDlgDll>
|
||||
<SimDlgDllArguments></SimDlgDllArguments>
|
||||
<TargetDllName>SARMV8M.DLL</TargetDllName>
|
||||
<TargetDllArguments> -MPU</TargetDllArguments>
|
||||
<TargetDlgDll>TCM.DLL</TargetDlgDll>
|
||||
<TargetDlgDllArguments>-pCM33</TargetDlgDllArguments>
|
||||
</DllOption>
|
||||
<DebugOption>
|
||||
<OPTHX>
|
||||
<HexSelection>1</HexSelection>
|
||||
<HexRangeLowAddress>0</HexRangeLowAddress>
|
||||
<HexRangeHighAddress>0</HexRangeHighAddress>
|
||||
<HexOffset>0</HexOffset>
|
||||
<Oh166RecLen>16</Oh166RecLen>
|
||||
</OPTHX>
|
||||
</DebugOption>
|
||||
<Utilities>
|
||||
<Flash1>
|
||||
<UseTargetDll>1</UseTargetDll>
|
||||
<UseExternalTool>0</UseExternalTool>
|
||||
<RunIndependent>0</RunIndependent>
|
||||
<UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
|
||||
<Capability>1</Capability>
|
||||
<DriverSelection>4096</DriverSelection>
|
||||
</Flash1>
|
||||
<bUseTDR>1</bUseTDR>
|
||||
<Flash2>BIN\UL2V8M.DLL</Flash2>
|
||||
<Flash3></Flash3>
|
||||
<Flash4></Flash4>
|
||||
<pFcarmOut></pFcarmOut>
|
||||
<pFcarmGrp></pFcarmGrp>
|
||||
<pFcArmRoot></pFcArmRoot>
|
||||
<FcArmLst>0</FcArmLst>
|
||||
</Utilities>
|
||||
<TargetArmAds>
|
||||
<ArmAdsMisc>
|
||||
<GenerateListings>0</GenerateListings>
|
||||
<asHll>1</asHll>
|
||||
<asAsm>1</asAsm>
|
||||
<asMacX>1</asMacX>
|
||||
<asSyms>1</asSyms>
|
||||
<asFals>1</asFals>
|
||||
<asDbgD>1</asDbgD>
|
||||
<asForm>1</asForm>
|
||||
<ldLst>0</ldLst>
|
||||
<ldmm>1</ldmm>
|
||||
<ldXref>1</ldXref>
|
||||
<BigEnd>0</BigEnd>
|
||||
<AdsALst>1</AdsALst>
|
||||
<AdsACrf>1</AdsACrf>
|
||||
<AdsANop>0</AdsANop>
|
||||
<AdsANot>0</AdsANot>
|
||||
<AdsLLst>1</AdsLLst>
|
||||
<AdsLmap>1</AdsLmap>
|
||||
<AdsLcgr>1</AdsLcgr>
|
||||
<AdsLsym>1</AdsLsym>
|
||||
<AdsLszi>1</AdsLszi>
|
||||
<AdsLtoi>1</AdsLtoi>
|
||||
<AdsLsun>1</AdsLsun>
|
||||
<AdsLven>1</AdsLven>
|
||||
<AdsLsxf>1</AdsLsxf>
|
||||
<RvctClst>0</RvctClst>
|
||||
<GenPPlst>0</GenPPlst>
|
||||
<AdsCpuType>"Cortex-M33"</AdsCpuType>
|
||||
<RvctDeviceName></RvctDeviceName>
|
||||
<mOS>0</mOS>
|
||||
<uocRom>0</uocRom>
|
||||
<uocRam>0</uocRam>
|
||||
<hadIROM>1</hadIROM>
|
||||
<hadIRAM>1</hadIRAM>
|
||||
<hadXRAM>0</hadXRAM>
|
||||
<uocXRam>0</uocXRam>
|
||||
<RvdsVP>2</RvdsVP>
|
||||
<RvdsMve>0</RvdsMve>
|
||||
<RvdsCdeCp>0</RvdsCdeCp>
|
||||
<nBranchProt>0</nBranchProt>
|
||||
<hadIRAM2>0</hadIRAM2>
|
||||
<hadIROM2>0</hadIROM2>
|
||||
<StupSel>8</StupSel>
|
||||
<useUlib>0</useUlib>
|
||||
<EndSel>0</EndSel>
|
||||
<uLtcg>0</uLtcg>
|
||||
<nSecure>0</nSecure>
|
||||
<RoSelD>3</RoSelD>
|
||||
<RwSelD>3</RwSelD>
|
||||
<CodeSel>0</CodeSel>
|
||||
<OptFeed>0</OptFeed>
|
||||
<NoZi1>0</NoZi1>
|
||||
<NoZi2>0</NoZi2>
|
||||
<NoZi3>0</NoZi3>
|
||||
<NoZi4>0</NoZi4>
|
||||
<NoZi5>0</NoZi5>
|
||||
<Ro1Chk>0</Ro1Chk>
|
||||
<Ro2Chk>0</Ro2Chk>
|
||||
<Ro3Chk>0</Ro3Chk>
|
||||
<Ir1Chk>1</Ir1Chk>
|
||||
<Ir2Chk>0</Ir2Chk>
|
||||
<Ra1Chk>0</Ra1Chk>
|
||||
<Ra2Chk>0</Ra2Chk>
|
||||
<Ra3Chk>0</Ra3Chk>
|
||||
<Im1Chk>1</Im1Chk>
|
||||
<Im2Chk>0</Im2Chk>
|
||||
<OnChipMemories>
|
||||
<Ocm1>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm1>
|
||||
<Ocm2>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm2>
|
||||
<Ocm3>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm3>
|
||||
<Ocm4>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm4>
|
||||
<Ocm5>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm5>
|
||||
<Ocm6>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm6>
|
||||
<IRAM>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x20000000</StartAddress>
|
||||
<Size>0x80000</Size>
|
||||
</IRAM>
|
||||
<IROM>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x8000000</StartAddress>
|
||||
<Size>0x780000</Size>
|
||||
</IROM>
|
||||
<XRAM>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</XRAM>
|
||||
<OCR_RVCT1>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT1>
|
||||
<OCR_RVCT2>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT2>
|
||||
<OCR_RVCT3>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT3>
|
||||
<OCR_RVCT4>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x8000000</StartAddress>
|
||||
<Size>0x780000</Size>
|
||||
</OCR_RVCT4>
|
||||
<OCR_RVCT5>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT5>
|
||||
<OCR_RVCT6>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT6>
|
||||
<OCR_RVCT7>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT7>
|
||||
<OCR_RVCT8>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT8>
|
||||
<OCR_RVCT9>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x20000000</StartAddress>
|
||||
<Size>0x80000</Size>
|
||||
</OCR_RVCT9>
|
||||
<OCR_RVCT10>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT10>
|
||||
</OnChipMemories>
|
||||
<RvctStartVector></RvctStartVector>
|
||||
</ArmAdsMisc>
|
||||
<Cads>
|
||||
<interw>1</interw>
|
||||
<Optim>4</Optim>
|
||||
<oTime>0</oTime>
|
||||
<SplitLS>0</SplitLS>
|
||||
<OneElfS>1</OneElfS>
|
||||
<Strict>0</Strict>
|
||||
<EnumInt>0</EnumInt>
|
||||
<PlainCh>0</PlainCh>
|
||||
<Ropi>0</Ropi>
|
||||
<Rwpi>0</Rwpi>
|
||||
<wLevel>0</wLevel>
|
||||
<uThumb>0</uThumb>
|
||||
<uSurpInc>0</uSurpInc>
|
||||
<uC99>1</uC99>
|
||||
<uGnu>0</uGnu>
|
||||
<useXO>0</useXO>
|
||||
<v6Lang>1</v6Lang>
|
||||
<v6LangP>1</v6LangP>
|
||||
<vShortEn>1</vShortEn>
|
||||
<vShortWch>1</vShortWch>
|
||||
<v6Lto>0</v6Lto>
|
||||
<v6WtE>0</v6WtE>
|
||||
<v6Rtti>0</v6Rtti>
|
||||
<VariousControls>
|
||||
<MiscControls></MiscControls>
|
||||
<Define></Define>
|
||||
<Undefine></Undefine>
|
||||
<IncludePath></IncludePath>
|
||||
</VariousControls>
|
||||
</Cads>
|
||||
<Aads>
|
||||
<interw>1</interw>
|
||||
<Ropi>0</Ropi>
|
||||
<Rwpi>0</Rwpi>
|
||||
<thumb>0</thumb>
|
||||
<SplitLS>0</SplitLS>
|
||||
<SwStkChk>0</SwStkChk>
|
||||
<NoWarn>0</NoWarn>
|
||||
<uSurpInc>0</uSurpInc>
|
||||
<useXO>0</useXO>
|
||||
<ClangAsOpt>4</ClangAsOpt>
|
||||
<VariousControls>
|
||||
<MiscControls></MiscControls>
|
||||
<Define></Define>
|
||||
<Undefine></Undefine>
|
||||
<IncludePath></IncludePath>
|
||||
</VariousControls>
|
||||
</Aads>
|
||||
<LDads>
|
||||
<umfTarg>0</umfTarg>
|
||||
<Ropi>0</Ropi>
|
||||
<Rwpi>0</Rwpi>
|
||||
<noStLib>0</noStLib>
|
||||
<RepFail>1</RepFail>
|
||||
<useFile>0</useFile>
|
||||
<TextAddressRange>0x08000000</TextAddressRange>
|
||||
<DataAddressRange>0x20000000</DataAddressRange>
|
||||
<pXoBase></pXoBase>
|
||||
<ScatterFile>.\board\linker_scripts\link.sct</ScatterFile>
|
||||
<IncludeLibs></IncludeLibs>
|
||||
<IncludeLibsPath></IncludeLibsPath>
|
||||
<Misc></Misc>
|
||||
<LinkerInputFile></LinkerInputFile>
|
||||
<DisabledWarnings></DisabledWarnings>
|
||||
</LDads>
|
||||
</TargetArmAds>
|
||||
</TargetOption>
|
||||
<Groups>
|
||||
<Group>
|
||||
<GroupName>::CMSIS</GroupName>
|
||||
</Group>
|
||||
</Groups>
|
||||
</Target>
|
||||
</Targets>
|
||||
|
||||
<RTE>
|
||||
<apis/>
|
||||
<components>
|
||||
<component Cclass="CMSIS" Cgroup="CORE" Cvendor="ARM" Cversion="5.6.0" condition="ARMv6_7_8-M Device">
|
||||
<package name="CMSIS" schemaVersion="1.7.7" url="http://www.keil.com/pack/" vendor="ARM" version="5.9.0"/>
|
||||
<targetInfos>
|
||||
<targetInfo name="rt-thread"/>
|
||||
</targetInfos>
|
||||
</component>
|
||||
</components>
|
||||
<files/>
|
||||
</RTE>
|
||||
|
||||
<LayerInfo>
|
||||
<Layers>
|
||||
<Layer>
|
||||
<LayName><Project Info></LayName>
|
||||
<LayTarg>0</LayTarg>
|
||||
<LayPrjMark>1</LayPrjMark>
|
||||
</Layer>
|
||||
</Layers>
|
||||
</LayerInfo>
|
||||
|
||||
</Project>
|
||||
|
|
@ -30,3 +30,8 @@ config SOC_SERIES_GD32H7xx
|
|||
bool
|
||||
select ARCH_ARM_CORTEX_M7
|
||||
select SOC_FAMILY_GD32
|
||||
|
||||
config SOC_SERIES_GD32F5xx
|
||||
bool
|
||||
select ARCH_ARM_CORTEX_M33
|
||||
select SOC_FAMILY_GD32
|
||||
|
|
@ -257,7 +257,7 @@ static void gd32_pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode)
|
|||
const struct pin_index *index = RT_NULL;
|
||||
rt_uint32_t pin_mode = 0;
|
||||
|
||||
#if defined SOC_SERIES_GD32F4xx || defined SOC_SERIES_GD32H7xx
|
||||
#if defined SOC_SERIES_GD32F4xx || defined SOC_SERIES_GD32H7xx || defined SOC_SERIES_GD32F5xx
|
||||
rt_uint32_t pin_pupd = 0, pin_odpp = 0;
|
||||
#endif
|
||||
|
||||
|
|
@ -269,7 +269,7 @@ static void gd32_pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode)
|
|||
|
||||
/* GPIO Periph clock enable */
|
||||
rcu_periph_clock_enable(index->clk);
|
||||
#if defined SOC_SERIES_GD32F4xx || defined SOC_SERIES_GD32H7xx
|
||||
#if defined SOC_SERIES_GD32F4xx || defined SOC_SERIES_GD32H7xx || defined SOC_SERIES_GD32F5xx
|
||||
pin_mode = GPIO_MODE_OUTPUT;
|
||||
#else
|
||||
pin_mode = GPIO_MODE_OUT_PP;
|
||||
|
|
@ -279,7 +279,7 @@ static void gd32_pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode)
|
|||
{
|
||||
case PIN_MODE_OUTPUT:
|
||||
/* output setting */
|
||||
#if defined SOC_SERIES_GD32F4xx || defined SOC_SERIES_GD32H7xx
|
||||
#if defined SOC_SERIES_GD32F4xx || defined SOC_SERIES_GD32H7xx || defined SOC_SERIES_GD32F5xx
|
||||
pin_mode = GPIO_MODE_OUTPUT;
|
||||
pin_pupd = GPIO_PUPD_NONE;
|
||||
pin_odpp = GPIO_OTYPE_PP;
|
||||
|
|
@ -289,7 +289,7 @@ static void gd32_pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode)
|
|||
break;
|
||||
case PIN_MODE_OUTPUT_OD:
|
||||
/* output setting: od. */
|
||||
#if defined SOC_SERIES_GD32F4xx || defined SOC_SERIES_GD32H7xx
|
||||
#if defined SOC_SERIES_GD32F4xx || defined SOC_SERIES_GD32H7xx || defined SOC_SERIES_GD32F5xx
|
||||
pin_mode = GPIO_MODE_OUTPUT;
|
||||
pin_pupd = GPIO_PUPD_NONE;
|
||||
pin_odpp = GPIO_OTYPE_OD;
|
||||
|
|
@ -299,7 +299,7 @@ static void gd32_pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode)
|
|||
break;
|
||||
case PIN_MODE_INPUT:
|
||||
/* input setting: not pull. */
|
||||
#if defined SOC_SERIES_GD32F4xx || defined SOC_SERIES_GD32H7xx
|
||||
#if defined SOC_SERIES_GD32F4xx || defined SOC_SERIES_GD32H7xx || defined SOC_SERIES_GD32F5xx
|
||||
pin_mode = GPIO_MODE_INPUT;
|
||||
pin_pupd = GPIO_PUPD_PULLUP | GPIO_PUPD_PULLDOWN;
|
||||
#else
|
||||
|
|
@ -308,7 +308,7 @@ static void gd32_pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode)
|
|||
break;
|
||||
case PIN_MODE_INPUT_PULLUP:
|
||||
/* input setting: pull up. */
|
||||
#if defined SOC_SERIES_GD32F4xx || defined SOC_SERIES_GD32H7xx
|
||||
#if defined SOC_SERIES_GD32F4xx || defined SOC_SERIES_GD32H7xx || defined SOC_SERIES_GD32F5xx
|
||||
pin_mode = GPIO_MODE_INPUT;
|
||||
pin_pupd = GPIO_PUPD_PULLUP;
|
||||
#else
|
||||
|
|
@ -317,7 +317,7 @@ static void gd32_pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode)
|
|||
break;
|
||||
case PIN_MODE_INPUT_PULLDOWN:
|
||||
/* input setting: pull down. */
|
||||
#if defined SOC_SERIES_GD32F4xx || defined SOC_SERIES_GD32H7xx
|
||||
#if defined SOC_SERIES_GD32F4xx || defined SOC_SERIES_GD32H7xx || defined SOC_SERIES_GD32F5xx
|
||||
pin_mode = GPIO_MODE_INPUT;
|
||||
pin_pupd = GPIO_PUPD_PULLDOWN;
|
||||
#else
|
||||
|
|
@ -328,7 +328,7 @@ static void gd32_pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode)
|
|||
break;
|
||||
}
|
||||
|
||||
#if defined SOC_SERIES_GD32F4xx
|
||||
#if defined SOC_SERIES_GD32F4xx || defined SOC_SERIES_GD32F5xx
|
||||
gpio_mode_set(index->gpio_periph, pin_mode, pin_pupd, index->pin);
|
||||
if(pin_mode == GPIO_MODE_OUTPUT)
|
||||
{
|
||||
|
|
@ -553,7 +553,7 @@ static rt_err_t gd32_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_
|
|||
return -RT_EINVAL;
|
||||
}
|
||||
|
||||
#if defined SOC_SERIES_GD32F4xx || defined SOC_SERIES_GD32H7xx
|
||||
#if defined SOC_SERIES_GD32F4xx || defined SOC_SERIES_GD32H7xx || defined SOC_SERIES_GD32F5xx
|
||||
rcu_periph_clock_enable(RCU_SYSCFG);
|
||||
#else
|
||||
rcu_periph_clock_enable(RCU_AF);
|
||||
|
|
@ -563,7 +563,7 @@ static rt_err_t gd32_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_
|
|||
nvic_irq_enable(irqmap->irqno, 5U, 0U);
|
||||
|
||||
/* connect EXTI line to GPIO pin */
|
||||
#if defined SOC_SERIES_GD32F4xx || defined SOC_SERIES_GD32H7xx
|
||||
#if defined SOC_SERIES_GD32F4xx || defined SOC_SERIES_GD32H7xx || defined SOC_SERIES_GD32F5xx
|
||||
syscfg_exti_line_config(index->port_src, index->pin_src);
|
||||
#else
|
||||
gpio_exti_source_select(index->port_src, index->pin_src);
|
||||
|
|
|
|||
|
|
@ -31,11 +31,13 @@ extern "C" {
|
|||
#include "gd32h7xx_gpio.h"
|
||||
#elif defined SOC_SERIES_GD32E50x
|
||||
#include "gd32e50x_gpio.h"
|
||||
#elif defined SOC_SERIES_GD32F5xx
|
||||
#include "gd32f5xx_gpio.h"
|
||||
#endif
|
||||
|
||||
#define __GD32_PORT(port) GPIO##port
|
||||
|
||||
#if defined SOC_SERIES_GD32F4xx || defined SOC_SERIES_GD32H7xx
|
||||
#if defined SOC_SERIES_GD32F4xx || defined SOC_SERIES_GD32H7xx || defined SOC_SERIES_GD32F5xx
|
||||
#define GD32_PIN(index, port, pin) {index, RCU_GPIO##port, \
|
||||
GPIO##port, GPIO_PIN_##pin, \
|
||||
EXTI_SOURCE_GPIO##port, \
|
||||
|
|
|
|||
|
|
@ -157,7 +157,7 @@ static const struct gd32_uart uart_obj[] = {
|
|||
USART0, // uart peripheral index
|
||||
USART0_IRQn, // uart iqrn
|
||||
RCU_USART0, // uart periph clock
|
||||
#if defined SOC_SERIES_GD32F4xx
|
||||
#if defined SOC_SERIES_GD32F4xx || defined SOC_SERIES_GD32F5xx
|
||||
RCU_GPIOA, RCU_GPIOA, // tx gpio clock, rx gpio clock
|
||||
GPIOA, GPIO_AF_7, GPIO_PIN_9, // tx port, tx alternate, tx pin
|
||||
GPIOA, GPIO_AF_7, GPIO_PIN_10, // rx port, rx alternate, rx pin
|
||||
|
|
@ -186,7 +186,7 @@ static const struct gd32_uart uart_obj[] = {
|
|||
USART1, // uart peripheral index
|
||||
USART1_IRQn, // uart iqrn
|
||||
RCU_USART1, // uart periph clock
|
||||
#if defined SOC_SERIES_GD32F4xx || defined SOC_SERIES_GD32H7xx
|
||||
#if defined SOC_SERIES_GD32F4xx || defined SOC_SERIES_GD32H7xx || defined SOC_SERIES_GD32F5xx
|
||||
RCU_GPIOA, RCU_GPIOA, // tx gpio clock, rx gpio clock
|
||||
GPIOA, GPIO_AF_7, GPIO_PIN_2, // tx port, tx alternate, tx pin
|
||||
GPIOA, GPIO_AF_7, GPIO_PIN_3, // rx port, rx alternate, rx pin
|
||||
|
|
@ -210,7 +210,7 @@ static const struct gd32_uart uart_obj[] = {
|
|||
USART2, // uart peripheral index
|
||||
USART2_IRQn, // uart iqrn
|
||||
RCU_USART2, // uart periph clock
|
||||
#if defined SOC_SERIES_GD32F4xx || defined SOC_SERIES_GD32H7xx
|
||||
#if defined SOC_SERIES_GD32F4xx || defined SOC_SERIES_GD32H7xx || defined SOC_SERIES_GD32F5xx
|
||||
RCU_GPIOB, RCU_GPIOB, // tx gpio clock, rt gpio clock
|
||||
GPIOB, GPIO_AF_7, GPIO_PIN_10, // tx port, tx alternate, tx pin
|
||||
GPIOB, GPIO_AF_7, GPIO_PIN_11, // rx port, rx alternate, rx pin
|
||||
|
|
@ -234,7 +234,7 @@ static const struct gd32_uart uart_obj[] = {
|
|||
UART3, // uart peripheral index
|
||||
UART3_IRQn, // uart iqrn
|
||||
RCU_UART3, // uart periph clock
|
||||
#if defined SOC_SERIES_GD32F4xx
|
||||
#if defined SOC_SERIES_GD32F4xx || defined SOC_SERIES_GD32F5xx
|
||||
RCU_GPIOC, RCU_GPIOC, // tx gpio clock, rt gpio clock
|
||||
GPIOC, GPIO_AF_8, GPIO_PIN_10, // tx port, tx alternate, tx pin
|
||||
GPIOC, GPIO_AF_8, GPIO_PIN_11, // rx port, rx alternate, rx pin
|
||||
|
|
@ -258,7 +258,7 @@ static const struct gd32_uart uart_obj[] = {
|
|||
UART4, // uart peripheral index
|
||||
UART4_IRQn, // uart iqrn
|
||||
RCU_UART4, RCU_GPIOC, RCU_GPIOD, // periph clock, tx gpio clock, rt gpio clock
|
||||
#if defined SOC_SERIES_GD32F4xx
|
||||
#if defined SOC_SERIES_GD32F4xx || defined SOC_SERIES_GD32F5xx
|
||||
GPIOC, GPIO_AF_8, GPIO_PIN_12, // tx port, tx alternate, tx pin
|
||||
GPIOD, GPIO_AF_8, GPIO_PIN_2, // rx port, rx alternate, rx pin
|
||||
#elif defined SOC_SERIES_GD32E50x
|
||||
|
|
@ -279,7 +279,7 @@ static const struct gd32_uart uart_obj[] = {
|
|||
USART5, // uart peripheral index
|
||||
USART5_IRQn, // uart iqrn
|
||||
RCU_USART5, RCU_GPIOC, RCU_GPIOC, // periph clock, tx gpio clock, rt gpio clock
|
||||
#if defined SOC_SERIES_GD32F4xx
|
||||
#if defined SOC_SERIES_GD32F4xx || defined SOC_SERIES_GD32F5xx
|
||||
GPIOC, GPIO_AF_8, GPIO_PIN_6, // tx port, tx alternate, tx pin
|
||||
GPIOC, GPIO_AF_8, GPIO_PIN_7, // rx port, rx alternate, rx pin
|
||||
#elif defined SOC_SERIES_GD32E50x
|
||||
|
|
@ -300,7 +300,7 @@ static const struct gd32_uart uart_obj[] = {
|
|||
UART6, // uart peripheral index
|
||||
UART6_IRQn, // uart iqrn
|
||||
RCU_UART6, RCU_GPIOE, RCU_GPIOE, // periph clock, tx gpio clock, rt gpio clock
|
||||
#if defined SOC_SERIES_GD32F4xx
|
||||
#if defined SOC_SERIES_GD32F4xx || defined SOC_SERIES_GD32F5xx
|
||||
GPIOE, GPIO_AF_8, GPIO_PIN_7, // tx port, tx alternate, tx pin
|
||||
GPIOE, GPIO_AF_8, GPIO_PIN_8, // rx port, rx alternate, rx pin
|
||||
#else
|
||||
|
|
@ -317,7 +317,7 @@ static const struct gd32_uart uart_obj[] = {
|
|||
UART7, // uart peripheral index
|
||||
UART7_IRQn, // uart iqrn
|
||||
RCU_UART7, RCU_GPIOE, RCU_GPIOE, // periph clock, tx gpio clock, rt gpio clock
|
||||
#if defined SOC_SERIES_GD32F4xx
|
||||
#if defined SOC_SERIES_GD32F4xx || defined SOC_SERIES_GD32F5xx
|
||||
GPIOE, GPIO_AF_8, GPIO_PIN_0, // tx port, tx alternate, tx pin
|
||||
GPIOE, GPIO_AF_8, GPIO_PIN_1, // rx port, rx alternate, rx pin
|
||||
#else
|
||||
|
|
@ -347,7 +347,7 @@ void gd32_uart_gpio_init(struct gd32_uart *uart)
|
|||
rcu_periph_clock_enable(uart->rx_gpio_clk);
|
||||
rcu_periph_clock_enable(uart->per_clk);
|
||||
|
||||
#if defined SOC_SERIES_GD32F4xx
|
||||
#if defined SOC_SERIES_GD32F4xx || defined SOC_SERIES_GD32F5xx
|
||||
/* connect port to USARTx_Tx */
|
||||
gpio_af_set(uart->tx_port, uart->tx_af, uart->tx_pin);
|
||||
|
||||
|
|
|
|||
|
|
@ -33,14 +33,14 @@ struct gd32_uart
|
|||
rcu_periph_enum tx_gpio_clk; //Todo: 5bits
|
||||
rcu_periph_enum rx_gpio_clk; //Todo: 5bits
|
||||
uint32_t tx_port; //Todo: 4bits
|
||||
#if defined SOC_SERIES_GD32F4xx || defined SOC_SERIES_GD32H7xx
|
||||
#if defined SOC_SERIES_GD32F4xx || defined SOC_SERIES_GD32H7xx || defined SOC_SERIES_GD32F5xx
|
||||
uint16_t tx_af; //Todo: 4bits
|
||||
#elif defined SOC_SERIES_GD32E50x
|
||||
uint32_t tx_af; //alternate1 cfg
|
||||
#endif
|
||||
uint16_t tx_pin; //Todo: 4bits
|
||||
uint32_t rx_port; //Todo: 4bits
|
||||
#if defined SOC_SERIES_GD32F4xx || defined SOC_SERIES_GD32H7xx
|
||||
#if defined SOC_SERIES_GD32F4xx || defined SOC_SERIES_GD32H7xx || defined SOC_SERIES_GD32F5xx
|
||||
uint16_t rx_af; //Todo: 4bits
|
||||
#elif defined SOC_SERIES_GD32E50x
|
||||
uint32_t rx_af; //alternate1 cfg
|
||||
|
|
|
|||
|
|
@ -56,7 +56,7 @@ static struct gd32_uart uart_obj[] = {
|
|||
USART0, // uart peripheral index
|
||||
USART0_IRQn, // uart iqrn
|
||||
RCU_USART0, RCU_GPIOA, RCU_GPIOA, // periph clock, tx gpio clock, rt gpio clock
|
||||
#if defined SOC_SERIES_GD32F4xx
|
||||
#if defined SOC_SERIES_GD32F4xx || defined SOC_SERIES_GD32F5xx
|
||||
GPIOA, GPIO_AF_7, GPIO_PIN_9, // tx port, tx alternate, tx pin
|
||||
GPIOA, GPIO_AF_7, GPIO_PIN_10, // rx port, rx alternate, rx pin
|
||||
#else
|
||||
|
|
@ -78,7 +78,7 @@ static struct gd32_uart uart_obj[] = {
|
|||
USART1, // uart peripheral index
|
||||
USART1_IRQn, // uart iqrn
|
||||
RCU_USART1, RCU_GPIOA, RCU_GPIOA, // periph clock, tx gpio clock, rt gpio clock
|
||||
#if defined SOC_SERIES_GD32F4xx
|
||||
#if defined SOC_SERIES_GD32F4xx || defined SOC_SERIES_GD32F5xx
|
||||
GPIOA, GPIO_AF_7, GPIO_PIN_2, // tx port, tx alternate, tx pin
|
||||
GPIOA, GPIO_AF_7, GPIO_PIN_3, // rx port, rx alternate, rx pin
|
||||
#else
|
||||
|
|
@ -100,7 +100,7 @@ static struct gd32_uart uart_obj[] = {
|
|||
USART2, // uart peripheral index
|
||||
USART2_IRQn, // uart iqrn
|
||||
RCU_USART2, RCU_GPIOB, RCU_GPIOB, // periph clock, tx gpio clock, rt gpio clock
|
||||
#if defined SOC_SERIES_GD32F4xx
|
||||
#if defined SOC_SERIES_GD32F4xx || defined SOC_SERIES_GD32F5xx
|
||||
GPIOB, GPIO_AF_7, GPIO_PIN_10, // tx port, tx alternate, tx pin
|
||||
GPIOB, GPIO_AF_7, GPIO_PIN_11, // rx port, rx alternate, rx pin
|
||||
#else
|
||||
|
|
@ -122,7 +122,7 @@ static struct gd32_uart uart_obj[] = {
|
|||
UART3, // uart peripheral index
|
||||
UART3_IRQn, // uart iqrn
|
||||
RCU_UART3, RCU_GPIOC, RCU_GPIOC, // periph clock, tx gpio clock, rt gpio clock
|
||||
#if defined SOC_SERIES_GD32F4xx
|
||||
#if defined SOC_SERIES_GD32F4xx || defined SOC_SERIES_GD32F5xx
|
||||
GPIOC, GPIO_AF_8, GPIO_PIN_10, // tx port, tx alternate, tx pin
|
||||
GPIOC, GPIO_AF_8, GPIO_PIN_11, // rx port, rx alternate, rx pin
|
||||
#else
|
||||
|
|
@ -144,7 +144,7 @@ static struct gd32_uart uart_obj[] = {
|
|||
UART4, // uart peripheral index
|
||||
UART4_IRQn, // uart iqrn
|
||||
RCU_UART4, RCU_GPIOC, RCU_GPIOD, // periph clock, tx gpio clock, rt gpio clock
|
||||
#if defined SOC_SERIES_GD32F4xx
|
||||
#if defined SOC_SERIES_GD32F4xx || defined SOC_SERIES_GD32F5xx
|
||||
GPIOC, GPIO_AF_8, GPIO_PIN_12, // tx port, tx alternate, tx pin
|
||||
GPIOD, GPIO_AF_8, GPIO_PIN_2, // rx port, rx alternate, rx pin
|
||||
#else
|
||||
|
|
@ -166,7 +166,7 @@ static struct gd32_uart uart_obj[] = {
|
|||
USART5, // uart peripheral index
|
||||
USART5_IRQn, // uart iqrn
|
||||
RCU_USART5, RCU_GPIOC, RCU_GPIOC, // periph clock, tx gpio clock, rt gpio clock
|
||||
#if defined SOC_SERIES_GD32F4xx
|
||||
#if defined SOC_SERIES_GD32F4xx || defined SOC_SERIES_GD32F5xx
|
||||
GPIOC, GPIO_AF_8, GPIO_PIN_6, // tx port, tx alternate, tx pin
|
||||
GPIOC, GPIO_AF_8, GPIO_PIN_7, // rx port, rx alternate, rx pin
|
||||
#else
|
||||
|
|
@ -188,7 +188,7 @@ static struct gd32_uart uart_obj[] = {
|
|||
UART6, // uart peripheral index
|
||||
UART6_IRQn, // uart iqrn
|
||||
RCU_UART6, RCU_GPIOE, RCU_GPIOE, // periph clock, tx gpio clock, rt gpio clock
|
||||
#if defined SOC_SERIES_GD32F4xx
|
||||
#if defined SOC_SERIES_GD32F4xx || defined SOC_SERIES_GD32F5xx
|
||||
GPIOE, GPIO_AF_8, GPIO_PIN_7, // tx port, tx alternate, tx pin
|
||||
GPIOE, GPIO_AF_8, GPIO_PIN_8, // rx port, rx alternate, rx pin
|
||||
#else
|
||||
|
|
@ -210,7 +210,7 @@ static struct gd32_uart uart_obj[] = {
|
|||
UART7, // uart peripheral index
|
||||
UART7_IRQn, // uart iqrn
|
||||
RCU_UART7, RCU_GPIOE, RCU_GPIOE, // periph clock, tx gpio clock, rt gpio clock
|
||||
#if defined SOC_SERIES_GD32F4xx
|
||||
#if defined SOC_SERIES_GD32F4xx || defined SOC_SERIES_GD32F5xx
|
||||
GPIOE, GPIO_AF_8, GPIO_PIN_0, // tx port, tx alternate, tx pin
|
||||
GPIOE, GPIO_AF_8, GPIO_PIN_1, // rx port, rx alternate, rx pin
|
||||
#else
|
||||
|
|
@ -664,7 +664,7 @@ void gd32_uart_gpio_init (struct gd32_uart *uart)
|
|||
rcu_periph_clock_enable(uart->rx_gpio_clk);
|
||||
rcu_periph_clock_enable(uart->per_clk);
|
||||
|
||||
#if defined SOC_SERIES_GD32F4xx
|
||||
#if defined SOC_SERIES_GD32F4xx || defined SOC_SERIES_GD32F5xx
|
||||
/* connect port to USARTx_Tx */
|
||||
gpio_af_set(uart->tx_port, uart->tx_af, uart->tx_pin);
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue