The boot EL will save in x0, when current EL is EL3,
kernel will jump to the EL2 after EL3.
But the x0 value is **3**, The init for EL2 will not work.
To fix it: the EL3 should jump to the EL2 init branch with not check,
and when SoC boot in EL2, kernel will jump to the EL2 test branch.
Link: https://club.rt-thread.org/ask/question/ec320a6765389f67.html
Signed-off-by: wusongjie <wusongjie@rt-thread.com>
1. Configure the kernel default vaddr by RAM and TEXT offset.
2. Check the p_addr 2M align when set the stride in `rt_hw_mmu_map`.
Signed-off-by: GuEe-GUI <2991707448@qq.com>
libcpu/risc-v/common64/mmu.c uses the external
symbol "__bss_end" (this symbol generally is
defined in the link script file) and depends
on the extern declaration of this symbol in
the bsp's "board.h". This is not a problem in
implementation, but it is not a good habit.
If this extern symbol is used locally, just
declare it locally should be better.
In this way, there will be no dependency of
the kernel core on the bsp header file. And
there will be no special requirements for the
bsp board code, such as the need to make
extern declarations for these "__bss_end"
symbols in "board.h".
This patch currently only explicitly externly
declares "__bss_end" inside libcpu itself.
The code of "#include <board.h>" is kept, because
the modification involved is too large, it is
necessary to clean up the bsp involved before
cleaning this include code line uniformly.
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
* libcpu: cleanup undefined rt_hw_mmu_kernel_map_init
rt_hw_mmu_kernel_map_init() is declared in header files but
no definition found, cleanup the code.
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
* bsp: allwinner: d1: remove calling of rt_hw_mmu_kernel_map_init
rt_hw_mmu_kernel_map_init is an undefined function, calling it
is meaningless.
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
---------
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
This patch introduces a tagged pages allocator to address the existing problems
of page aliasing on specific platforms and the requirement of page coloring.
It implements an affinity-id aware page manager by separating the runtime page
list into two types: a normal single linked-list and a multi-dimensional affinity-list.
Changes:
- Introduced tagged pages allocator and managing algorithm for affinity pages list
- Modified components to support affinity-id list management
- Updated page allocation and freeing functions to handle tagged pages
- Added configuration options for page affinity block size and debugging
- Modified mmap and elf loading to respect affinity settings
- Enhanced page list management to support multi-dimensional affinity-list
Signed-off-by: Shell <smokewood@qq.com>
description: Using the vector instruction set to trigger
an illegal instruction exception when ARCH_SISCV_VECTOR=y.
analysis: When initializing the thread stack,
the rt_cw_stack_init function did not enable VS for SSTATUS.
Solution: When ARCH_SISCV_VECTOR=y,
increment the initial value of sstatus by 0x600(SSTATUS_VS).
Signed-off-by: Liu Gui <kenneth.liu@sophgo.com>
When building bsp/cvitek/c906_little, compiler reports:
```
.../rt-thread/libcpu/risc-v/rv64/trap.c:
In function 'handle_trap':
.../rt-thread/libcpu/risc-v/rv64/trap.c:106:13:
warning: implicit declaration of function 'rt_hw_tick_isr';
did you mean 'rt_hw_stack_init'? [-Wimplicit-function-declaration]
106 | rt_hw_tick_isr();
| ^~~~~~~~~~~~~~
| rt_hw_stack_init
.../rt-thread/libcpu/risc-v/rv64/trap.c:110:13:
warning: implicit declaration of function 'rt_hw_irq_isr';
did you mean 'rt_hw_soft_irq_isr'? [-Wimplicit-function-declaration]
110 | rt_hw_irq_isr();
| ^~~~~~~~~~~~~
| rt_hw_soft_irq_isr
```
rt_hw_tick_isr()/rt_hw_irq_isr() are implemented by bsp, but
libcpu/risc-v/rv64 doesn't declare them, so compiler warns.
There are three BSPs using 'rv64' (libcpu/risc-v/rv64):
- `bsp/cvitek/c906_little/rtconfig.py`
- `bsp/juicevm/rtconfig.py`
- `bsp/k210/rtconfig.py`
`handle_trap` in `libcpu/risc-v/rv64` is defined as weak.
BSP can use this function directly or define and overload
it by itself.
If bsp use this function directly, bsp need to pay
attention to the fact that three functions will be called
in this function:
- `rt_hw_soft_irq_isr`
- `rt_hw_tick_isr`
- `rt_hw_irq_isr`
In `libcpu/risc-v/rv64`, `rt_hw_soft_irq_isr` has a weak
definition, while the other two do not. This means that
if the bsp does not overload `handle_trap`, bsp must
define `rt_hw_tick_isr` and `rt_hw_irq_isr` itself.
This is also the practice of `bsp/cvitek/c906_little`.
There is also a similar bsp `bsp/k210`, and the form of
`bsp/juicevm` implements `handle_trap` by itself.
It seems that `rt_hw_tick_isr` and `rt_hw_irq_isr` are
not required to be implemented by all BSPs using
`libcpu/risc-v/rv64`. The premise for BSP to implement
them is that it does not overload `handle_trap`. So
declaring `rt_hw_tick_isr` and `rt_hw_irq_isr` with
extern in `libcpu/risc-v/rv64` is not proper.
In addition, the `rt_hw_tick_isr/rt_hw_irq_isr` are only
used by `libcpu/risc-v/rv64`, so it is not worth putting
the declaration in `./include/rthw.h`.
Sum up, the best solution is to add weak definition to
`rt_hw_tick_isr/rt_hw_irq_isr` as existing `rt_hw_soft_irq_isr`.
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
When building bsp/cvitek/c906_little, compiler warns:
```
.../rt-thread/libcpu/risc-v/common/trap_common.c:
In function 'rt_hw_interrupt_install':
.../rt-thread/libcpu/risc-v/common/trap_common.c:50:11:
warning: unused variable 'user_param' [-Wunused-variable]
50 | void *user_param = param;
| ^~~~~~~~~~
.../rt-thread/libcpu/risc-v/common/trap_common.c:
In function 'rt_rv32_system_irq_handler':
.../rt-thread/libcpu/risc-v/common/trap_common.c:77:25:
warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
77 | s_stack_frame = (rt_hw_stack_frame_t *)mscratch;
| ^
```
Fixed these warnings as per indication from gcc.
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
RISCV_S_MODE configuration only affects the code in
libcpu/risc-v/virt64, and the only bsp using this
libcpu is qemu-virt64-riscv.
Considering s-mode is the default mode RT-Thread
running on virt64 machine, it seems unnecessary to
make RISCV_S_MODE a Kconfig option.
Solution: Remove RISCV_S_MODE from Kconfig and define
it as a macro in the code in libcpu/risc-v/virt64.
Plus, due to this macro is only related to virt64, rename
RISCV_S_MODE to RISCV_VIRT64_S_MODE.
Update the .config/rtconfig.h in this patch.
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
Improves the memory mapping process by dynamically selecting the optimal
paging stride (4K or 2M) based on virtual address alignment and mapping
size. This eliminates the need for upfront stride determination, enhancing
flexibility and maintainability in memory management.
Changes:
- Replaced fixed stride selection logic with a dynamic decision loop.
- Removed `npages` calculation and replaced with `remaining_sz` to track
unprocessed memory size.
- Added assertions to ensure `size` is properly aligned to the smallest
page size.
- Adjusted loop to dynamically determine and apply the appropriate stride
(4K or 2M) for each mapping iteration.
- Updated virtual and physical address increments to use the dynamically
selected stride.
Signed-off-by: Shell <smokewood@qq.com>
Support for ARM64 ASID to enhance virtual memory management efficiency
by reducing the need for TLB flushes during address space switches.
These changes improve performance especially for multi-process systems.
Changes:
- Added `ARCH_USING_ASID` configuration in `libcpu/aarch64/Kconfig`.
- Defined ASID-related constants in `mmu.h`.
- Updated `TLBI_ARG` macro to include ASID manipulation.
- Implemented ASID allocation mechanism with spinlock synchronization.
- Enhanced TLB invalidation to support ASID-specific operations.
- Modified `rt_hw_aspace_switch` to use ASIDs when switching address spaces.
- Adjusted debug logging and function documentation to reflect ASID usage.
- Refactored AArch64 MMU and TLB handling for ASID integration.
Signed-off-by: Shell <smokewood@qq.com>
Yulong Wang