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picker
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356 Commits

Author SHA1 Message Date
J. Wang eb9e61023b
Update example.java (#45) 2025-07-24 14:54:11 +08:00
Makiras 0903a84e90
[fix] parallel build error & non-appimage (#44) 2025-07-10 14:48:27 +08:00
Makiras ba5127bd4b
add new feat: appimage (#43) 
* [fix] performance analysis and internal signal config

* add dockerfile and ci builder

* [feat] add appimage building process, basic cpp support

* [fix] appimage multi-language support, appimage mode detection

* [feat] integrate verible-verilog-syntax in appiamge, fix dynamic lib search priority

* try ci appimages

* [fix] cmake CMP0171 for codegen keyword

* [fix] cmake CMP0171 for codegen keyword

* [fix] cmake CMP0171 for codegen keyword

* [fix] cmake CMP0171 for codegen keyword

* [fix] cmake CMP0171 for codegen keyword

* [fix] arm64 autobuild

* [fix] arm64 autobuild

* [fix] tag right release

* [fix] format and typos

* [fix] typo explaination should be corrected to 'explanation'

Co-authored-by: Copilot <175728472+Copilot@users.noreply.github.com>

---------

Co-authored-by: Copilot <175728472+Copilot@users.noreply.github.com>
 2025-07-08 16:04:14 +08:00
Makiras b3da72f4d4 fix typo for \; 2025-06-12 16:08:18 +08:00
Makiras 09bd083451
Fix ptr (#41) 
* [fix] quick fix for GetInternalSignal raw ptr to shared_ptr

* [fix] DutUnifiedBase::DutUnifiedBase args initialization for allocate memory
 2025-06-10 18:44:25 +08:00
Makiras 5abf516100
[fix] quick fix for GetInternalSignal raw ptr to shared_ptr (#40) 2025-06-09 10:00:10 +08:00
yaozhicheng 7df84adb88 fix(java/scala): fix pakage name 2025-04-30 11:23:00 +08:00
yaozhicheng 2a94e65732 fix(java/scala): make default example to pakage com.ut 2025-04-30 11:23:00 +08:00
yaozhicheng 10eb845acd fix(issue #36): add dut name to pakage name 2025-04-30 11:23:00 +08:00
yaozhicheng c728f70fae refine(mem_direct): append CFLAGS to CXXFLAGS 2025-04-30 11:23:00 +08:00
yaozhicheng bface44974 fix(build): remove -flto opt 2025-04-30 11:23:00 +08:00
yaozhicheng 1d09427913 fix(interlsignal/XCFG): Adapt to VPI and Mem direct internal signals 2025-04-30 11:23:00 +08:00
yaozhicheng 4519c0dbc6 fix(interlsignal): use new GetInternalSignal interface 2025-04-30 11:23:00 +08:00
yaozhicheng 72fd3fa853 feat(test): add test_vpi_all, test_mem_direct_all 2025-04-30 11:23:00 +08:00
yaozhicheng 64b98a71a0 feat(swig): add GetInternalSignal/GetInternalSignalList for lua 2025-04-30 11:23:00 +08:00
yaozhicheng f17211c8b1 feat(swig): add GetInternalSignal/GetInternalSignalList for golang 2025-04-30 11:23:00 +08:00
yaozhicheng dc974c3033 fix(golang): cp yaml to package src 2025-04-30 11:23:00 +08:00
yaozhicheng ee41d8bf4b new feat(cpp): add GetInternalSignalList/GetInternalSignal for cpp && test pass 2025-04-30 11:23:00 +08:00
yaozhicheng 32f43c1769 new feat(swig): add GetInternalSignalList/GetInternalSignal for java && test pass 2025-04-30 11:23:00 +08:00
yaozhicheng 0b6dd5dc6f feat(swig): add attrOf example 2025-04-30 11:23:00 +08:00
yaozhicheng 65cf7b22c3 fix(chisel): fix compile with jar path 2025-04-30 11:23:00 +08:00
yaozhicheng 3f7f8dfd8d refine example(chisel): add reserve internal signals demo 2025-04-30 11:23:00 +08:00
yaozhicheng 7f0ab3da56 fix(example): make waveFile as the class name in chiselUT 2025-04-30 11:23:00 +08:00
yaozhicheng a0f5db47e1 fix(example): add picker check in chiselUT 2025-04-30 11:23:00 +08:00
yaozhicheng aefc247da7 refine(example): chiselUT add inner-signal access 2025-04-30 11:23:00 +08:00
yaozhicheng 716c4072eb refine(ignore): default ignore new add files in example 2025-04-30 11:23:00 +08:00
yaozhicheng 88ce73f1c9 refine(example): refine chiselUT example 2025-04-30 11:23:00 +08:00
yaozhicheng 7f68d8b78e fix(mem_direct): add lnk option -lz 2025-04-30 11:23:00 +08:00
yaozhicheng cf4b8c6743 fix(mem_direct): delete mem_direct_tmp dir 2025-04-30 11:23:00 +08:00
yaozhicheng f8706a0e89 fix(swig): add xcfg and test 2025-04-30 11:23:00 +08:00
yaozhicheng 7a2dc6a7f2 fix(swig): pack *_offset.yaml into jar file 2025-04-30 11:23:00 +08:00
yaozhicheng e62ea8ac0a new example(chisel): add a chisel ut test example 2025-04-30 11:23:00 +08:00
yaozhicheng 97949c235b fix(swig): rename StringVector to avoid xcom confilict 2025-04-30 11:23:00 +08:00
yaozhicheng b87c740c67 fix (swig): fix scala -classpath 2025-04-30 11:23:00 +08:00
yaozhicheng f9a23afc0c fix (swig): xspcomm => xspcommLoader 2025-04-30 11:23:00 +08:00
yaozhicheng 6300e85d47 fix (swig): del -ea for scala 2.13.* 2025-04-30 11:23:00 +08:00
yaozhicheng 77faf6fda8 fix (swig): fix grammar to scala 2.13.* 2025-04-30 11:23:00 +08:00
yaozhicheng 81dde2cc72 feat(scala): DUT extends BaseDUTTrait 2025-04-30 11:23:00 +08:00
yaozhicheng bbca48b8ae feat: export new API GetXClock/GetXPort/OpenWaveform/CloseWaveform 2025-04-30 11:23:00 +08:00
yaozhicheng f2495f4e3e fix(typo): fix show_xcom_lib_location_scala typo 2025-04-30 11:23:00 +08:00
yaozhicheng 047d426bd5 feat: test Open/CloseWaveform functions 2025-04-30 11:23:00 +08:00
yaozhicheng 7cef2ee866 feat: add Open/CloseWaveform support 2025-04-30 11:23:00 +08:00
Makiras cec359b0a5 fix: non-struct verilator codegen 2025-04-30 11:23:00 +08:00
yaozhicheng efd44173d9 python: add more assert int GetInternalSignal 2025-04-30 11:23:00 +08:00
yaozhicheng 3af2c8c32d python: refine typo 2025-04-30 11:23:00 +08:00
yaozhicheng 66ad33e179 python: support xdata array in GetInternalSignal 2025-04-30 11:23:00 +08:00
yaozhicheng 83b8e5c8c4 python: refine GetInternalSignal & GetInternalSignalList to support both memdirect and vpi 2025-04-30 11:23:00 +08:00
yaozhicheng 7e72f73ee4 memdirect: add tag __RW_TYPE__ check 2025-04-30 11:23:00 +08:00
yaozhicheng 9a6773a070 XClock: new XClock with step func ptr 2025-04-30 11:23:00 +08:00
Makiras 09039290fb fix: too big gen_addr example 2025-04-30 11:23:00 +08:00