Fix public_module requiring a wire to become public (#4916).

Changes

@@ -33,6 +33,7 @@ Verilator 5.031 devel
 * Improve concatenation performance (#5598) (#5599) (#5602). [Geza Lore]
 * Fix dotted reference in delay value (#2410).
 * Fix `function fork...join_none` regression with unknown type (#4449).
+* Fix public_module requiring a wire to become public (#4916). [Andrew Nolte]
 * Fix can't locate scope error in interface task delayed assignment (#5462) (#5568). [Zhou Shen]
 * Fix BLKANDNBLK for for VARXREFs (#5569). [Todd Strader]
 * Fix VPI error instead of fatal for vpi_get_value() on large signals (#5571). [Todd Strader]

src/V3Dead.cpp

@@ -109,16 +109,16 @@ class DeadVisitor final : public VNVisitor {
         if (m_modp) m_modp->user1Inc();  // e.g. Class under Package
         VL_RESTORER(m_modp);
         m_modp = nodep;
-        if (!nodep->dead()) {
-            iterateChildren(nodep);
-            checkAll(nodep);
-            if (AstClass* const classp = VN_CAST(nodep, Class)) {
-                if (classp->extendsp()) classp->extendsp()->user1Inc();
-                if (classp->classOrPackagep()) classp->classOrPackagep()->user1Inc();
-                m_classesp.push_back(classp);
-                // TODO we don't reclaim dead classes yet - graph implementation instead?
-                classp->user1Inc();
-            }
+        if (nodep->dead()) return;
+        if (nodep->modPublic()) m_modp->user1Inc();
+        iterateChildren(nodep);
+        checkAll(nodep);
+        if (AstClass* const classp = VN_CAST(nodep, Class)) {
+            if (classp->extendsp()) classp->extendsp()->user1Inc();
+            if (classp->classOrPackagep()) classp->classOrPackagep()->user1Inc();
+            m_classesp.push_back(classp);
+            // TODO we don't reclaim dead classes yet - graph implementation instead?
+            classp->user1Inc();
         }
     }
     void visit(AstCFunc* nodep) override {

test_regress/t/t_inst_public.py

@@ -0,0 +1,19 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+
+test.compile(verilator_make_gmake=False)
+
+test.file_grep(test.obj_dir + "/" + test.vm_prefix + "_Pub.h", r'')
+test.file_grep_not(test.obj_dir + "/" + test.vm_prefix + "__Syms.h", r'Dead')
+
+test.passes()

test_regress/t/t_inst_public.v

@@ -0,0 +1,31 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2024 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+module t (/*AUTOARG*/);
+
+   Pub pub();
+
+   localparam ZERO = 0;
+   if (ZERO) Dead dead();
+
+   initial begin
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+
+endmodule
+
+module Pub;
+
+   // verilator public_module
+
+   // no signals here
+
+endmodule
+
+module Dead;
+   // verilator public_module
+endmodule