Tests: Add test and assert for nested simulated loops (#6223)

src/V3Simulate.h

@@ -973,6 +973,8 @@ private:
         checkNodeInfo(nodep);
         if (!m_checkOnly) {
             UINFO(5, "   JUMP GO " << nodep);
+            // Should be back at the JumpBlock and clear m_jumpp before another JumpGo
+            UASSERT_OBJ(!m_jumpp, nodep, "Jump inside jump");
             m_jumpp = nodep;
         }
     }

test_regress/t/t_unroll_double_param.py

@@ -10,10 +10,9 @@
 import vltest_bootstrap
 
 test.scenarios('simulator')
-test.top_filename = 't/t_unroll_double.v'
-test.golden_filename = 't/t_unroll_double.out'
+test.golden_filename = 't/t_unroll_nested.out'
 
-test.compile(v_flags2=['+define+TEST_FULL'])
+test.compile()
 
 test.execute(expect_filename=test.golden_filename)
 

test_regress/t/t_unroll_double_param.v

@@ -0,0 +1,46 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2025 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+module t;
+
+  int a, b;
+  int pos;
+
+  function string value;
+    // Debug 'initial' loops first
+    value = "";
+    for (int exit_a = 0; exit_a < 2; ++exit_a) begin
+      for (int exit_b = 0; exit_b < 3; ++exit_b) begin
+        b = 0;
+        value = {value, $sformatf("exit_a %0d %0d", exit_a, exit_b)};
+        for (a = 0; a < 3; ++a) begin : a_loop
+          value = {value, $sformatf("  A%0d", a * 10 + b)};
+          for (b = 0; b < 3; ++b) begin : b_loop
+            value = {value, $sformatf(" B%0d", a * 10 + b)};
+            if (exit_b == 1 && b == 1) disable b_loop;
+            value = {value, $sformatf(" C%0d", a * 10 + b)};
+            if (exit_b == 2 && a == 1) disable a_loop;
+            value = {value, $sformatf(" D%0d", a * 10 + b)};
+          end
+          value = {value, $sformatf("  Y%0d", a * 10 + b)};
+          if (exit_a == 1 && a == 1) disable a_loop;
+          value = {value, $sformatf("  Z%0d", a * 10 + b)};
+        end
+        value = {value, "\n"};
+      end
+    end
+  endfunction
+
+  localparam string VALUE = value();
+
+  initial begin
+    $write("%s", VALUE);
+
+    $write("*-* All Finished *-*\n");
+    $finish;
+  end
+
+endmodule

test_regress/t/t_unroll_nested_unroll.py

@@ -0,0 +1,23 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2025 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+test.top_filename = 't/t_unroll_nested.v'
+test.golden_filename = 't/t_unroll_nested.out'
+
+test.compile(v_flags2=['+define+TEST_FULL', '--stats'])
+
+test.execute(expect_filename=test.golden_filename)
+
+test.file_grep(test.stats, r'Optimizations, Unrolled Iterations\s+(\d+)', 11)
+test.file_grep(test.stats, r'Optimizations, Unrolled Loops\s+(\d+)', 4)
+
+test.passes()