Tests: Add test and assert for nested simulated loops (#6223)
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@ -973,6 +973,8 @@ private:
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checkNodeInfo(nodep);
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checkNodeInfo(nodep);
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if (!m_checkOnly) {
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if (!m_checkOnly) {
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UINFO(5, " JUMP GO " << nodep);
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UINFO(5, " JUMP GO " << nodep);
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// Should be back at the JumpBlock and clear m_jumpp before another JumpGo
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UASSERT_OBJ(!m_jumpp, nodep, "Jump inside jump");
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m_jumpp = nodep;
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m_jumpp = nodep;
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}
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}
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}
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}
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@ -10,10 +10,9 @@
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import vltest_bootstrap
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import vltest_bootstrap
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test.scenarios('simulator')
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test.scenarios('simulator')
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test.top_filename = 't/t_unroll_double.v'
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test.golden_filename = 't/t_unroll_nested.out'
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test.golden_filename = 't/t_unroll_double.out'
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test.compile(v_flags2=['+define+TEST_FULL'])
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test.compile()
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test.execute(expect_filename=test.golden_filename)
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test.execute(expect_filename=test.golden_filename)
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@ -0,0 +1,46 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t;
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int a, b;
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int pos;
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function string value;
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// Debug 'initial' loops first
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value = "";
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for (int exit_a = 0; exit_a < 2; ++exit_a) begin
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for (int exit_b = 0; exit_b < 3; ++exit_b) begin
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b = 0;
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value = {value, $sformatf("exit_a %0d %0d", exit_a, exit_b)};
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for (a = 0; a < 3; ++a) begin : a_loop
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value = {value, $sformatf(" A%0d", a * 10 + b)};
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for (b = 0; b < 3; ++b) begin : b_loop
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value = {value, $sformatf(" B%0d", a * 10 + b)};
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if (exit_b == 1 && b == 1) disable b_loop;
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value = {value, $sformatf(" C%0d", a * 10 + b)};
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if (exit_b == 2 && a == 1) disable a_loop;
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value = {value, $sformatf(" D%0d", a * 10 + b)};
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end
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value = {value, $sformatf(" Y%0d", a * 10 + b)};
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if (exit_a == 1 && a == 1) disable a_loop;
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value = {value, $sformatf(" Z%0d", a * 10 + b)};
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end
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value = {value, "\n"};
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end
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end
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endfunction
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localparam string VALUE = value();
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initial begin
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$write("%s", VALUE);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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@ -0,0 +1,23 @@
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#!/usr/bin/env python3
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2025 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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import vltest_bootstrap
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test.scenarios('simulator')
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test.top_filename = 't/t_unroll_nested.v'
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test.golden_filename = 't/t_unroll_nested.out'
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test.compile(v_flags2=['+define+TEST_FULL', '--stats'])
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test.execute(expect_filename=test.golden_filename)
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test.file_grep(test.stats, r'Optimizations, Unrolled Iterations\s+(\d+)', 11)
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test.file_grep(test.stats, r'Optimizations, Unrolled Loops\s+(\d+)', 4)
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test.passes()
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