fix fanout with iNO
This commit is contained in:
Zihao Yu
parent
9b3f065b07
commit
5965b4c967
26
Makefile
26
Makefile
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@ -6,22 +6,34 @@ RTL_FILES ?= $(shell find $(PROJ_PATH)/example -name "*.v")
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export CLK_FREQ_MHZ ?= 500
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RESULT_DIR = $(PROJ_PATH)/result/$(DESIGN)-$(CLK_FREQ_MHZ)MHz
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NETLIST_V = $(RESULT_DIR)/$(DESIGN).netlist.v
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SCRIPT_DIR = $(PROJ_PATH)/scripts
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NETLIST_SYN_V = $(RESULT_DIR)/$(DESIGN).netlist.syn.v
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NETLIST_FIXED_V = $(RESULT_DIR)/$(DESIGN).netlist.fixed.v
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SYN_DEF = $(RESULT_DIR)/$(DESIGN).syn.def
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FIXED_DEF = $(RESULT_DIR)/$(DESIGN).fixed.def
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TIMING_RPT = $(RESULT_DIR)/$(DESIGN).rpt
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init:
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bash -c "$$(wget -O - https://ysyx.oscc.cc/slides/resources/scripts/init-yosys-sta.sh)"
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syn: $(NETLIST_V)
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$(NETLIST_V): $(RTL_FILES) yosys.tcl
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syn: $(NETLIST_SYN_V)
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$(NETLIST_SYN_V): $(RTL_FILES) $(SCRIPT_DIR)/yosys.tcl
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mkdir -p $(@D)
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echo tcl yosys.tcl $(DESIGN) \"$(RTL_FILES)\" $(NETLIST_V) | yosys -l $(@D)/yosys.log -s -
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echo tcl $(SCRIPT_DIR)/yosys.tcl $(DESIGN) \"$(RTL_FILES)\" $@ | yosys -l $(@D)/yosys.log -s -
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def: $(SYN_DEF)
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$(SYN_DEF): $(SCRIPT_DIR)/def.tcl $(NETLIST_SYN_V)
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LD_LIBRARY_PATH=bin/ ./bin/iEDA $^ $(DESIGN) $@ | tee $(RESULT_DIR)/gen-def.log
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fix-fanout: $(NETLIST_FIXED_V)
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$(NETLIST_FIXED_V): $(SCRIPT_DIR)/fix-fanout.tcl $(SDC_FILE) $(SYN_DEF)
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LD_LIBRARY_PATH=bin/ ./bin/iEDA -script $^ $@ 2>&1 | tee $(RESULT_DIR)/fix-fanout.log
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sta: $(TIMING_RPT)
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$(TIMING_RPT): $(SDC_FILE) $(NETLIST_V)
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LD_LIBRARY_PATH=bin/ ./bin/iSTA $(PROJ_PATH)/sta.tcl $(DESIGN) $(SDC_FILE) $(NETLIST_V)
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$(TIMING_RPT): $(SCRIPT_DIR)/sta.tcl $(SDC_FILE) $(NETLIST_FIXED_V)
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LD_LIBRARY_PATH=bin/ ./bin/iEDA -script $^ $(DESIGN) 2>&1 | tee $(RESULT_DIR)/sta.log
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clean:
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-rm -rf result/
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.PHONY: init syn sta clean
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.PHONY: init syn def fix-fanout sta clean
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@ -0,0 +1,10 @@
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set PROJ_PATH "[file dirname [info script]]/.."
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set NETLIST_SYN_V [lindex $argv 0]
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set DESIGN [lindex $argv 1]
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set DEF_FILE [lindex $argv 2]
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set LEF_FILES "\
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$PROJ_PATH/nangate45/lef/NangateOpenCellLibrary.tech.lef \
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$PROJ_PATH/nangate45/lef/NangateOpenCellLibrary.macro.mod.lef"
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verilog_to_def -lef $LEF_FILES -verilog $NETLIST_SYN_V -top $DESIGN -def $DEF_FILE
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@ -0,0 +1,13 @@
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{
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"file_path": {
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"design_work_space": "",
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"sdc_file": "",
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"lib_files": "",
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"lef_files": "",
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"def_file": "",
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"output_def": "",
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"report_file": ""
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},
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"insert_buffer": "BUF_X8",
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"max_fanout": 30
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}
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@ -0,0 +1,14 @@
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set PROJ_PATH "[file dirname [info script]]/.."
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set SDC_FILE [lindex $argv 0]
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set DEF_FILE [lindex $argv 1]
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set NETLIST_FIXED_V [lindex $argv 2]
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db_init -lib_path $PROJ_PATH/nangate45/lib/merged.lib
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db_init -sdc_path $SDC_FILE
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tech_lef_init -path $PROJ_PATH/nangate45/lef/NangateOpenCellLibrary.tech.lef
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lef_init -path $PROJ_PATH/nangate45/lef/NangateOpenCellLibrary.macro.mod.lef
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def_init -path $DEF_FILE
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run_no_fixfanout -config $PROJ_PATH/scripts/fix-fanout.json
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#def_save -path fix_fanout_result.def
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netlist_save -path $NETLIST_FIXED_V -exclude_cell_names {}
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@ -1,7 +1,7 @@
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set PROJ_PATH [file dirname [info script]]
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set DESIGN [lindex $argv 0]
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set SDC_FILE [lindex $argv 1]
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set NETLIST_V [lindex $argv 2]
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set PROJ_PATH "[file dirname [info script]]/.."
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set SDC_FILE [lindex $argv 0]
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set NETLIST_V [lindex $argv 1]
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set DESIGN [lindex $argv 2]
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set RESULT_DIR [file dirname $NETLIST_V]
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set LIB_FILES $PROJ_PATH/nangate45/lib/merged.lib
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@ -3,16 +3,16 @@
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#===========================================================
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set DESIGN [lindex $argv 0]
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set VERILOG_FILES [string map {"\"" ""} [lindex $argv 1]]
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set NETLIST_V [lindex $argv 2]
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set NETLIST_SYN_V [lindex $argv 2]
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set VERILOG_INCLUDE_DIRS ""
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set RESULT_DIR [file dirname $NETLIST_V]
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set RESULT_DIR [file dirname $NETLIST_SYN_V]
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set PROJ_PATH [file dirname [info script]]
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set MERGED_LIB_FILE "$PROJ_PATH/nangate45/lib/merged.lib"
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set BLACKBOX_V_FILE "$PROJ_PATH/nangate45/verilog/blackbox.v"
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set CLKGATE_MAP_FILE "$PROJ_PATH/nangate45/verilog/cells_clkgate.v"
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set LATCH_MAP_FILE "$PROJ_PATH/nangate45/verilog/cells_latch.v"
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set BLACKBOX_MAP_TCL "$PROJ_PATH/nangate45/blackbox_map.tcl"
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set FOUNDARY_PATH "[file dirname [info script]]/../nangate45"
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set MERGED_LIB_FILE "$FOUNDARY_PATH/lib/merged.lib"
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set BLACKBOX_V_FILE "$FOUNDARY_PATH/verilog/blackbox.v"
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set CLKGATE_MAP_FILE "$FOUNDARY_PATH/verilog/cells_clkgate.v"
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set LATCH_MAP_FILE "$FOUNDARY_PATH/verilog/cells_latch.v"
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set BLACKBOX_MAP_TCL "$FOUNDARY_PATH/blackbox_map.tcl"
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set CLK_FREQ_MHZ 500
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if {[info exists env(CLK_FREQ_MHZ)]} {
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@ -120,4 +120,4 @@ tee -o $RESULT_DIR/synth_check.txt check
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tee -o $RESULT_DIR/synth_stat.txt stat -liberty $MERGED_LIB_FILE
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# write synthesized design
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write_verilog -noattr -noexpr -nohex -nodec $NETLIST_V
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write_verilog -noattr -noexpr -nohex -nodec $NETLIST_SYN_V
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