mirror of https://github.com/llvm/circt.git
[RTGTest] Add the last remaining ops for RV32I (#8142)
This commit is contained in:
Martin Erhart
GitHub
parent
deb88ba5ec
commit
5aa1cc3157
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@ -40,6 +40,12 @@ MLIR_CAPI_EXPORTED MlirType rtgtestIntegerRegisterTypeGet(MlirContext ctxt);
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// Immediates.
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//===----------------------------------------------------------------------===//
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/// If the type is an RTGTest Imm5Type.
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MLIR_CAPI_EXPORTED bool rtgtestTypeIsAImm5(MlirType type);
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/// Creates an RTGTest Imm5 type in the context.
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MLIR_CAPI_EXPORTED MlirType rtgtestImm5TypeGet(MlirContext ctxt);
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/// If the type is an RTGTest Imm12Type.
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MLIR_CAPI_EXPORTED bool rtgtestTypeIsAImm12(MlirType type);
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@ -276,6 +282,16 @@ MLIR_CAPI_EXPORTED MlirAttribute rtgtestRegT6AttrGet(MlirContext ctxt);
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// Immediates.
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//===----------------------------------------------------------------------===//
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/// If the attribute is an RTGTest Imm5Attr.
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MLIR_CAPI_EXPORTED bool rtgtestAttrIsAImm5(MlirAttribute attr);
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/// Creates an RTGTest Imm5 attribute in the context.
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MLIR_CAPI_EXPORTED MlirAttribute rtgtestImm5AttrGet(MlirContext ctxt,
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unsigned value);
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/// Returns the value represented by the Imm5 attribute.
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MLIR_CAPI_EXPORTED unsigned rtgtestImm5AttrGetValue(MlirAttribute attr);
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/// If the attribute is an RTGTest Imm12Attr.
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MLIR_CAPI_EXPORTED bool rtgtestAttrIsAImm12(MlirAttribute attr);
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@ -71,6 +71,7 @@ class ImmediateAttrBase<int width> : RTGTestAttrDef<"Imm" # width, [
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let genVerifyDecl = 1;
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}
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def Imm5 : ImmediateAttrBase<5>;
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def Imm12 : ImmediateAttrBase<12>;
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def Imm13 : ImmediateAttrBase<13>;
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def Imm21 : ImmediateAttrBase<21>;
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@ -48,7 +48,7 @@ def ImmediateOp : RTGTestOp<"immediate", [
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]> {
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let summary = "declare an immediate value";
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let arguments = (ins AnyAttrOf<[Imm12, Imm13, Imm21, Imm32]>:$imm);
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let arguments = (ins AnyAttrOf<[Imm5, Imm12, Imm13, Imm21, Imm32]>:$imm);
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let results = (outs AnyType:$result);
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let assemblyFormat = "$imm attr-dict";
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@ -98,7 +98,8 @@ class InstFormatIOpBase<string mnemonic, int opcode7, int funct3>
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<< cast<rtg::RegisterAttrInterface>(adaptor.getRd())
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.getRegisterAssembly()
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<< ", "
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<< cast<Imm12Attr>(adaptor.getImm()).getValue()
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// The assembler only accepts signed values here.
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<< cast<Imm12Attr>(adaptor.getImm()).getAPInt().getSExtValue()
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<< "("
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<< cast<rtg::RegisterAttrInterface>(adaptor.getRs())
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.getRegisterAssembly()
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@ -182,6 +183,7 @@ class InstFormatBOpBase<string mnemonic, int opcode7, int funct3>
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return;
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}
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// The assembler is fine with unsigned and signed values here.
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os << cast<Imm13Attr>(adaptor.getImm()).getValue();
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}
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}];
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@ -266,7 +268,8 @@ class InstFormatSOpBase<string mnemonic, int opcode7, int funct3>
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<< cast<rtg::RegisterAttrInterface>(adaptor.getRs1())
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.getRegisterAssembly()
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<< ", "
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<< cast<Imm12Attr>(adaptor.getImm()).getValue()
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// The assembler only accepts signed values here.
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<< cast<Imm12Attr>(adaptor.getImm()).getAPInt().getSExtValue()
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<< "("
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<< cast<rtg::RegisterAttrInterface>(adaptor.getRs2())
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.getRegisterAssembly()
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@ -275,8 +278,192 @@ class InstFormatSOpBase<string mnemonic, int opcode7, int funct3>
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}];
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}
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class InstFormatUOpBase<string mnemonic, int opcode7>
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: RTGTestOp<"rv32i." # mnemonic, [InstructionOpAdaptor]> {
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let arguments = (ins IntegerRegisterType:$rd,
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AnyTypeOf<[Imm32Type, LabelType]>:$imm);
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let assemblyFormat = "$rd `,` $imm `:` type($imm) attr-dict";
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let extraClassDefinition = [{
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void $cppClass::printInstructionBinary(llvm::raw_ostream &os,
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FoldAdaptor adaptor) {
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assert (isa<Imm32Attr>(adaptor.getImm()) &&
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"binary of labels not supported");
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auto rd = cast<rtg::RegisterAttrInterface>(adaptor.getRd());
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auto imm = cast<Imm32Attr>(adaptor.getImm()).getAPInt();
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auto binary = imm.extractBits(20, 12)
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.concat(llvm::APInt(5, rd.getClassIndex()))
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.concat(llvm::APInt(7, }] # opcode7 # [{));
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SmallVector<char> str;
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binary.toStringUnsigned(str, 16);
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os << str;
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}
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void $cppClass::printInstructionAssembly(llvm::raw_ostream &os,
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FoldAdaptor adaptor) {
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os << getOperationName().rsplit('.').second
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<< " "
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<< cast<rtg::RegisterAttrInterface>(adaptor.getRd())
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.getRegisterAssembly()
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<< ", ";
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if (auto label = dyn_cast<StringAttr>(adaptor.getImm())) {
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os << label.getValue();
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return;
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}
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// The assembler wants an unsigned value here.
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os << cast<Imm32Attr>(adaptor.getImm()).getValue();
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}
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}];
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}
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class InstFormatJOpBase<string mnemonic, int opcode7>
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: RTGTestOp<"rv32i." # mnemonic, [InstructionOpAdaptor]> {
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let arguments = (ins IntegerRegisterType:$rd,
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AnyTypeOf<[Imm21Type, LabelType]>:$imm);
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let assemblyFormat = "$rd `,` $imm `:` type($imm) attr-dict";
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let extraClassDefinition = [{
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void $cppClass::printInstructionBinary(llvm::raw_ostream &os,
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FoldAdaptor adaptor) {
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assert (isa<Imm21Attr>(adaptor.getImm()) &&
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"binary of labels not supported");
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auto rd = cast<rtg::RegisterAttrInterface>(adaptor.getRd());
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auto imm = cast<Imm21Attr>(adaptor.getImm()).getAPInt();
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auto binary = imm.extractBits(1, 20)
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.concat(imm.extractBits(10, 1))
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.concat(imm.extractBits(1, 1))
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.concat(imm.extractBits(8, 12))
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.concat(llvm::APInt(5, rd.getClassIndex()))
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.concat(llvm::APInt(7, }] # opcode7 # [{));
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SmallVector<char> str;
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binary.toStringUnsigned(str, 16);
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os << str;
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}
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void $cppClass::printInstructionAssembly(llvm::raw_ostream &os,
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FoldAdaptor adaptor) {
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os << getOperationName().rsplit('.').second
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<< " "
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<< cast<rtg::RegisterAttrInterface>(adaptor.getRd())
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.getRegisterAssembly()
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<< ", ";
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if (auto label = dyn_cast<StringAttr>(adaptor.getImm())) {
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os << label.getValue();
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return;
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}
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// The assembler is fine with signed and unsigned values here.
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os << cast<Imm21Attr>(adaptor.getImm()).getAPInt().getSExtValue();
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}
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}];
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}
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class InstFormatIAOpBase<string mnemonic, int opcode7, int funct3>
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: RTGTestOp<"rv32i." # mnemonic, [InstructionOpAdaptor]> {
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let arguments = (ins IntegerRegisterType:$rd,
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IntegerRegisterType:$rs,
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Imm12Type:$imm);
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let assemblyFormat = "$rd `,` $rs `,` $imm attr-dict";
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let extraClassDefinition = [{
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void $cppClass::printInstructionBinary(llvm::raw_ostream &os,
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FoldAdaptor adaptor) {
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auto rd = cast<rtg::RegisterAttrInterface>(adaptor.getRd());
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auto rs = cast<rtg::RegisterAttrInterface>(adaptor.getRs());
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auto imm = cast<Imm12Attr>(adaptor.getImm()).getAPInt();
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auto binary = imm
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.concat(llvm::APInt(5, rs.getClassIndex()))
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.concat(llvm::APInt(3, }] # funct3 # [{))
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.concat(llvm::APInt(5, rd.getClassIndex()))
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.concat(llvm::APInt(7, }] # opcode7 # [{));
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SmallVector<char> str;
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binary.toStringUnsigned(str, 16);
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os << str;
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}
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void $cppClass::printInstructionAssembly(llvm::raw_ostream &os,
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FoldAdaptor adaptor) {
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os << getOperationName().rsplit('.').second
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<< " "
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<< cast<rtg::RegisterAttrInterface>(adaptor.getRd())
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.getRegisterAssembly()
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<< ", "
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<< cast<rtg::RegisterAttrInterface>(adaptor.getRs())
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.getRegisterAssembly()
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<< ", "
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// The assembler only accepts signed values here.
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<< cast<Imm12Attr>(adaptor.getImm()).getAPInt().getSExtValue();
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}
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}];
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}
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class InstFormatShiftOpBase<string mnemonic, int opcode7,
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int funct3, int funct7>
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: RTGTestOp<"rv32i." # mnemonic, [InstructionOpAdaptor]> {
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let arguments = (ins IntegerRegisterType:$rd,
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IntegerRegisterType:$rs,
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Imm5Type:$imm);
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let assemblyFormat = "$rd `,` $rs `,` $imm attr-dict";
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let extraClassDefinition = [{
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void $cppClass::printInstructionBinary(llvm::raw_ostream &os,
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FoldAdaptor adaptor) {
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auto rd = cast<rtg::RegisterAttrInterface>(adaptor.getRd());
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auto rs = cast<rtg::RegisterAttrInterface>(adaptor.getRs());
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auto imm = cast<Imm5Attr>(adaptor.getImm()).getAPInt();
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auto binary = llvm::APInt(7, }] # funct7 # [{)
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.concat(imm.extractBits(5, 0))
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.concat(llvm::APInt(5, rs.getClassIndex()))
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.concat(llvm::APInt(3, }] # funct3 # [{))
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.concat(llvm::APInt(5, rd.getClassIndex()))
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.concat(llvm::APInt(7, }] # opcode7 # [{));
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SmallVector<char> str;
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binary.toStringUnsigned(str, 16);
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os << str;
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}
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void $cppClass::printInstructionAssembly(llvm::raw_ostream &os,
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FoldAdaptor adaptor) {
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os << getOperationName().rsplit('.').second
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<< " "
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<< cast<rtg::RegisterAttrInterface>(adaptor.getRd())
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.getRegisterAssembly()
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<< ", "
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<< cast<rtg::RegisterAttrInterface>(adaptor.getRs())
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.getRegisterAssembly()
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<< ", "
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// The assembler only accepts an unsigned value here.
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<< cast<Imm5Attr>(adaptor.getImm()).getValue();
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}
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}];
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}
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//===- Instructions -------------------------------------------------------===//
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def RV32I_LUI : InstFormatUOpBase<"lui", 0b0110111>;
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def RV32I_AUIPC : InstFormatUOpBase<"auipc", 0b0010111>;
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def RV32I_JAL : InstFormatJOpBase<"jal", 0b1101111>;
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def RV32I_JALROp : InstFormatIOpBase<"jalr", 0b1100111, 0b000>;
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def RV32I_BEQ : InstFormatBOpBase<"beq", 0b1100011, 0b000>;
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@ -296,6 +483,17 @@ def RV32I_SB : InstFormatSOpBase<"sb", 0b0100011, 0b000>;
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def RV32I_SH : InstFormatSOpBase<"sh", 0b0100011, 0b001>;
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def RV32I_SW : InstFormatSOpBase<"sw", 0b0100011, 0b010>;
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def RV32I_ADDI : InstFormatIAOpBase<"addi", 0b0010011, 0b000>;
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def RV32I_SLTI : InstFormatIAOpBase<"slti", 0b0010011, 0b010>;
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def RV32I_SLTIU : InstFormatIAOpBase<"sltiu", 0b0010011, 0b011>;
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def RV32I_XORI : InstFormatIAOpBase<"xori", 0b0010011, 0b100>;
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def RV32I_ORI : InstFormatIAOpBase<"ori", 0b0010011, 0b110>;
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def RV32I_ANDI : InstFormatIAOpBase<"andi", 0b0010011, 0b111>;
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def RV32I_SLLI : InstFormatShiftOpBase<"slli", 0b0010011, 0b001, 0b0000000>;
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def RV32I_SRLI : InstFormatShiftOpBase<"srli", 0b0010011, 0b101, 0b0000000>;
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def RV32I_SRAI : InstFormatShiftOpBase<"srai", 0b0010011, 0b101, 0b0100000>;
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def RV32I_ADD : InstFormatROpBase<"add", 0b110011, 0b000, 0b0000000>;
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def RV32I_SUB : InstFormatROpBase<"sub", 0b110011, 0b000, 0b0100000>;
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def RV32I_SLL : InstFormatROpBase<"sll", 0b110011, 0b001, 0b0000000>;
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@ -38,6 +38,7 @@ class ImmTypeBase<int width> : TypeDef<RTGTestDialect, "Imm" # width, []> {
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let mnemonic = "imm" # width;
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}
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def Imm5Type : ImmTypeBase<5>;
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def Imm12Type : ImmTypeBase<12>;
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def Imm13Type : ImmTypeBase<13>;
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def Imm21Type : ImmTypeBase<21>;
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@ -172,6 +172,8 @@ with Context() as ctx, Location.unknown():
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circt.register_dialects(ctx)
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m = Module.create()
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with InsertionPoint(m.body):
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# CHECK: rtgtest.immediate #rtgtest.imm5<3> : !rtgtest.imm5
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rtgtest.ImmediateOp(rtgtest.Imm5Attr.get(3))
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# CHECK: rtgtest.immediate #rtgtest.imm12<3> : !rtgtest.imm12
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rtgtest.ImmediateOp(rtgtest.Imm12Attr.get(3))
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# CHECK: rtgtest.immediate #rtgtest.imm13<3> : !rtgtest.imm13
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@ -38,6 +38,14 @@ void circt::python::populateDialectRTGTestSubmodule(nb::module_ &m) {
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},
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nb::arg("self"), nb::arg("ctxt") = nullptr);
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mlir_type_subclass(m, "Imm5Type", rtgtestTypeIsAImm5)
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.def_classmethod(
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"get",
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[](nb::object cls, MlirContext ctxt) {
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return cls(rtgtestImm5TypeGet(ctxt));
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},
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nb::arg("self"), nb::arg("ctxt") = nullptr);
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mlir_type_subclass(m, "Imm12Type", rtgtestTypeIsAImm12)
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.def_classmethod(
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"get",
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@ -336,6 +344,17 @@ void circt::python::populateDialectRTGTestSubmodule(nb::module_ &m) {
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},
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nb::arg("self"), nb::arg("ctxt") = nullptr);
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mlir_attribute_subclass(m, "Imm5Attr", rtgtestAttrIsAImm5)
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.def_classmethod(
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"get",
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[](nb::object cls, unsigned value, MlirContext ctxt) {
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return cls(rtgtestImm5AttrGet(ctxt, value));
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},
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nb::arg("self"), nb::arg("value"), nb::arg("ctxt") = nullptr)
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.def_property_readonly("value", [](MlirAttribute self) {
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return rtgtestImm5AttrGetValue(self);
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});
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mlir_attribute_subclass(m, "Imm12Attr", rtgtestAttrIsAImm12)
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.def_classmethod(
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"get",
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@ -43,6 +43,12 @@ MlirType rtgtestIntegerRegisterTypeGet(MlirContext ctxt) {
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// Immediates.
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//===----------------------------------------------------------------------===//
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bool rtgtestTypeIsAImm5(MlirType type) { return isa<Imm5Type>(unwrap(type)); }
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MlirType rtgtestImm5TypeGet(MlirContext ctxt) {
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return wrap(Imm5Type::get(unwrap(ctxt)));
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}
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bool rtgtestTypeIsAImm12(MlirType type) { return isa<Imm12Type>(unwrap(type)); }
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MlirType rtgtestImm12TypeGet(MlirContext ctxt) {
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@ -345,6 +351,18 @@ MlirAttribute rtgtestRegT6AttrGet(MlirContext ctxt) {
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// Immediates.
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//===----------------------------------------------------------------------===//
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bool rtgtestAttrIsAImm5(MlirAttribute attr) {
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return isa<Imm5Attr>(unwrap(attr));
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}
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MlirAttribute rtgtestImm5AttrGet(MlirContext ctxt, unsigned value) {
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return wrap(Imm5Attr::get(unwrap(ctxt), value));
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}
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unsigned rtgtestImm5AttrGetValue(MlirAttribute attr) {
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return cast<Imm5Attr>(unwrap(attr)).getValue();
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}
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bool rtgtestAttrIsAImm12(MlirAttribute attr) {
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return isa<Imm12Attr>(unwrap(attr));
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}
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@ -271,6 +271,12 @@ static void testRegisters(MlirContext ctx) {
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}
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static void testImmediates(MlirContext ctx) {
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MlirType imm5Type = rtgtestImm5TypeGet(ctx);
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// CHECK: is_imm5
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fprintf(stderr, rtgtestTypeIsAImm5(imm5Type) ? "is_imm5\n" : "isnot_imm5\n");
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// CHECK: !rtgtest.imm5
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mlirTypeDump(imm5Type);
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MlirType imm12Type = rtgtestImm12TypeGet(ctx);
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// CHECK: is_imm12
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fprintf(stderr,
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@ -299,6 +305,14 @@ static void testImmediates(MlirContext ctx) {
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// CHECK: !rtgtest.imm32
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mlirTypeDump(imm32Type);
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MlirAttribute imm5Attr = rtgtestImm5AttrGet(ctx, 3);
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// CHECK: is_imm5
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fprintf(stderr, rtgtestAttrIsAImm5(imm5Attr) ? "is_imm5\n" : "isnot_imm5\n");
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// CHECK: 3
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fprintf(stderr, "%u\n", rtgtestImm5AttrGetValue(imm5Attr));
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// CHECK: #rtgtest.imm5<3>
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mlirAttributeDump(imm5Attr);
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MlirAttribute imm12Attr = rtgtestImm12AttrGet(ctx, 3);
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// CHECK: is_imm12
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fprintf(stderr,
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@ -27,6 +27,12 @@ rtg.test @test0 : !rtg.dict<> {
|
|||
rtgtest.rv32i.bltu %rd, %rs, %label : !rtg.label
|
||||
// CHECK-NEXT: bgeu ra, s0, label_name
|
||||
rtgtest.rv32i.bgeu %rd, %rs, %label : !rtg.label
|
||||
// CHECK-NEXT: lui ra, label_name
|
||||
rtgtest.rv32i.lui %rd, %label : !rtg.label
|
||||
// CHECK-NEXT: auipc ra, label_name
|
||||
rtgtest.rv32i.auipc %rd, %label : !rtg.label
|
||||
// CHECK-NEXT: jal ra, label_name
|
||||
rtgtest.rv32i.jal %rd, %label : !rtg.label
|
||||
}
|
||||
|
||||
// CHECK-EMPTY:
|
||||
|
|
|
|||
|
|
@ -10,12 +10,16 @@ rtg.test @test0 : !rtg.dict<> {
|
|||
%rd = rtg.fixed_reg #rtgtest.ra
|
||||
%rs = rtg.fixed_reg #rtgtest.s0
|
||||
%imm = rtgtest.immediate #rtgtest.imm12<0>
|
||||
%imm5 = rtgtest.immediate #rtgtest.imm5<31>
|
||||
%imm21 = rtgtest.immediate #rtgtest.imm21<0>
|
||||
%imm32 = rtgtest.immediate #rtgtest.imm32<0>
|
||||
%neg_imm = rtgtest.immediate #rtgtest.imm12<4080>
|
||||
%imm13 = rtgtest.immediate #rtgtest.imm13<6144>
|
||||
|
||||
// CHECK-ALLOWED-NEXT: jalr ra, 0(s0)
|
||||
// CHECK-NEXT: # jalr ra, 0(s0)
|
||||
// CHECK-NEXT: .word 0x400E7
|
||||
rtgtest.rv32i.jalr %rd, %rs, %imm
|
||||
// CHECK-ALLOWED-NEXT: jalr ra, -16(s0)
|
||||
// CHECK-NEXT: # jalr ra, -16(s0)
|
||||
// CHECK-NEXT: .word 0xFF0400E7
|
||||
rtgtest.rv32i.jalr %rd, %rs, %neg_imm
|
||||
|
||||
// CHECK-ALLOWED-NEXT: lb ra, 0(s0)
|
||||
// CHECK-NEXT: # lb ra, 0(s0)
|
||||
|
|
@ -132,10 +136,10 @@ rtg.test @test0 : !rtg.dict<> {
|
|||
// CHECK-NEXT: .word 0x8470B3
|
||||
rtgtest.rv32i.and %rd, %rs, %rs
|
||||
|
||||
// CHECK-ALLOWED-NEXT: sb ra, 0(s0)
|
||||
// CHECK-NEXT: # sb ra, 0(s0)
|
||||
// CHECK-NEXT: .word 0x808023
|
||||
rtgtest.rv32i.sb %rd, %rs, %imm
|
||||
// CHECK-ALLOWED-NEXT: sb ra, -16(s0)
|
||||
// CHECK-NEXT: # sb ra, -16(s0)
|
||||
// CHECK-NEXT: .word 0xFE808823
|
||||
rtgtest.rv32i.sb %rd, %rs, %neg_imm
|
||||
|
||||
// CHECK-ALLOWED-NEXT: sh ra, 0(s0)
|
||||
// CHECK-NEXT: # sh ra, 0(s0)
|
||||
|
|
@ -146,6 +150,66 @@ rtg.test @test0 : !rtg.dict<> {
|
|||
// CHECK-NEXT: # sw ra, 0(s0)
|
||||
// CHECK-NEXT: .word 0x80A023
|
||||
rtgtest.rv32i.sw %rd, %rs, %imm
|
||||
|
||||
// CHECK-ALLOWED-NEXT: lui ra, 0
|
||||
// CHECK-NEXT: # lui ra, 0
|
||||
// CHECK-NEXT: .word 0xB7
|
||||
rtgtest.rv32i.lui %rd, %imm32 : !rtgtest.imm32
|
||||
|
||||
// CHECK-ALLOWED-NEXT: auipc ra, 0
|
||||
// CHECK-NEXT: # auipc ra, 0
|
||||
// CHECK-NEXT: .word 0x97
|
||||
rtgtest.rv32i.auipc %rd, %imm32 : !rtgtest.imm32
|
||||
|
||||
// CHECK-ALLOWED-NEXT: jal ra, 0
|
||||
// CHECK-NEXT: # jal ra, 0
|
||||
// CHECK-NEXT: .word 0xEF
|
||||
rtgtest.rv32i.jal %rd, %imm21 : !rtgtest.imm21
|
||||
|
||||
// CHECK-ALLOWED-NEXT: addi ra, s0, -16
|
||||
// CHECK-NEXT: # addi ra, s0, -16
|
||||
// CHECK-NEXT: .word 0xFF040093
|
||||
rtgtest.rv32i.addi %rd, %rs, %neg_imm
|
||||
|
||||
// CHECK-ALLOWED-NEXT: slti ra, s0, 0
|
||||
// CHECK-NEXT: # slti ra, s0, 0
|
||||
// CHECK-NEXT: .word 0x42093
|
||||
rtgtest.rv32i.slti %rd, %rs, %imm
|
||||
|
||||
// CHECK-ALLOWED-NEXT: sltiu ra, s0, 0
|
||||
// CHECK-NEXT: # sltiu ra, s0, 0
|
||||
// CHECK-NEXT: .word 0x43093
|
||||
rtgtest.rv32i.sltiu %rd, %rs, %imm
|
||||
|
||||
// CHECK-ALLOWED-NEXT: xori ra, s0, 0
|
||||
// CHECK-NEXT: # xori ra, s0, 0
|
||||
// CHECK-NEXT: .word 0x44093
|
||||
rtgtest.rv32i.xori %rd, %rs, %imm
|
||||
|
||||
// CHECK-ALLOWED-NEXT: ori ra, s0, 0
|
||||
// CHECK-NEXT: # ori ra, s0, 0
|
||||
// CHECK-NEXT: .word 0x46093
|
||||
rtgtest.rv32i.ori %rd, %rs, %imm
|
||||
|
||||
// CHECK-ALLOWED-NEXT: andi ra, s0, 0
|
||||
// CHECK-NEXT: # andi ra, s0, 0
|
||||
// CHECK-NEXT: .word 0x47093
|
||||
rtgtest.rv32i.andi %rd, %rs, %imm
|
||||
|
||||
// CHECK-ALLOWED-NEXT: slli ra, s0, 31
|
||||
// CHECK-NEXT: # slli ra, s0, 31
|
||||
// CHECK-NEXT: .word 0x1F41093
|
||||
rtgtest.rv32i.slli %rd, %rs, %imm5
|
||||
|
||||
// CHECK-ALLOWED-NEXT: srli ra, s0, 31
|
||||
// CHECK-NEXT: # srli ra, s0, 31
|
||||
// CHECK-NEXT: .word 0x1F45093
|
||||
rtgtest.rv32i.srli %rd, %rs, %imm5
|
||||
|
||||
// CHECK-ALLOWED-NEXT: srai ra, s0, 31
|
||||
// CHECK-NEXT: # srai ra, s0, 31
|
||||
// CHECK-NEXT: .word 0x41F45093
|
||||
rtgtest.rv32i.srai %rd, %rs, %imm5
|
||||
}
|
||||
|
||||
// CHECK-EMPTY:
|
||||
|
|
|
|||
|
|
@ -1 +1 @@
|
|||
rtgtest.rv32i.jalr,rtgtest.rv32i.lb,rtgtest.rv32i.lh,rtgtest.rv32i.lw,rtgtest.rv32i.lbu,rtgtest.rv32i.lhu,rtgtest.rv32i.beq,rtgtest.rv32i.bne,rtgtest.rv32i.blt,rtgtest.rv32i.bge,rtgtest.rv32i.bltu,rtgtest.rv32i.bgeu,rtgtest.rv32i.add,rtgtest.rv32i.sub,rtgtest.rv32i.sll,rtgtest.rv32i.slt,rtgtest.rv32i.sltu,rtgtest.rv32i.xor,rtgtest.rv32i.srl,rtgtest.rv32i.sra,rtgtest.rv32i.or,rtgtest.rv32i.and,rtgtest.rv32i.sb,rtgtest.rv32i.sh,rtgtest.rv32i.sw
|
||||
rtgtest.rv32i.jalr,rtgtest.rv32i.lb,rtgtest.rv32i.lh,rtgtest.rv32i.lw,rtgtest.rv32i.lbu,rtgtest.rv32i.lhu,rtgtest.rv32i.beq,rtgtest.rv32i.bne,rtgtest.rv32i.blt,rtgtest.rv32i.bge,rtgtest.rv32i.bltu,rtgtest.rv32i.bgeu,rtgtest.rv32i.add,rtgtest.rv32i.sub,rtgtest.rv32i.sll,rtgtest.rv32i.slt,rtgtest.rv32i.sltu,rtgtest.rv32i.xor,rtgtest.rv32i.srl,rtgtest.rv32i.sra,rtgtest.rv32i.or,rtgtest.rv32i.and,rtgtest.rv32i.sb,rtgtest.rv32i.sh,rtgtest.rv32i.sw,rtgtest.rv32i.lui,rtgtest.rv32i.auipc,rtgtest.rv32i.jal,rtgtest.rv32i.addi,rtgtest.rv32i.slti,rtgtest.rv32i.sltiu,rtgtest.rv32i.xori,rtgtest.rv32i.ori,rtgtest.rv32i.andi,rtgtest.rv32i.slli,rtgtest.rv32i.srli,rtgtest.rv32i.srai
|
||||
|
|
|
|||
|
|
@ -88,6 +88,8 @@ rtg.test @registers : !rtg.dict<reg: !rtgtest.ireg> {
|
|||
|
||||
// CHECK-LABEL: @immediates
|
||||
rtg.test @immediates : !rtg.dict<> {
|
||||
// CHECK: rtgtest.immediate #rtgtest.imm5<3> : !rtgtest.imm5
|
||||
rtgtest.immediate #rtgtest.imm5<3> : !rtgtest.imm5
|
||||
// CHECK: rtgtest.immediate #rtgtest.imm12<3> : !rtgtest.imm12
|
||||
rtgtest.immediate #rtgtest.imm12<3> : !rtgtest.imm12
|
||||
// CHECK: rtgtest.immediate #rtgtest.imm13<3> : !rtgtest.imm13
|
||||
|
|
@ -99,9 +101,9 @@ rtg.test @immediates : !rtg.dict<> {
|
|||
}
|
||||
|
||||
// CHECK-LABEL: @instructions
|
||||
rtg.test @instructions : !rtg.dict<imm: !rtgtest.imm12, imm13: !rtgtest.imm13, label: !rtg.label, rd: !rtgtest.ireg, rs: !rtgtest.ireg> {
|
||||
// CHECK: ([[IMM:%.+]]: !rtgtest.imm12, [[IMM13:%.+]]: !rtgtest.imm13, [[LABEL:%.+]]: !rtg.label, [[RD:%.+]]: !rtgtest.ireg, [[RS:%.+]]: !rtgtest.ireg)
|
||||
^bb0(%imm: !rtgtest.imm12, %imm13: !rtgtest.imm13, %label: !rtg.label, %rd: !rtgtest.ireg, %rs: !rtgtest.ireg):
|
||||
rtg.test @instructions : !rtg.dict<imm: !rtgtest.imm12, imm13: !rtgtest.imm13, imm21: !rtgtest.imm21, imm32: !rtgtest.imm32, imm5: !rtgtest.imm5, label: !rtg.label, rd: !rtgtest.ireg, rs: !rtgtest.ireg> {
|
||||
// CHECK: ([[IMM:%.+]]: !rtgtest.imm12, [[IMM13:%.+]]: !rtgtest.imm13, [[IMM21:%.+]]: !rtgtest.imm21, [[IMM32:%.+]]: !rtgtest.imm32, [[IMM5:%.+]]: !rtgtest.imm5, [[LABEL:%.+]]: !rtg.label, [[RD:%.+]]: !rtgtest.ireg, [[RS:%.+]]: !rtgtest.ireg)
|
||||
^bb0(%imm: !rtgtest.imm12, %imm13: !rtgtest.imm13, %imm21: !rtgtest.imm21, %imm32: !rtgtest.imm32, %imm5: !rtgtest.imm5, %label: !rtg.label, %rd: !rtgtest.ireg, %rs: !rtgtest.ireg):
|
||||
// CHECK: rtgtest.rv32i.jalr [[RD]], [[RS]], [[IMM]]
|
||||
rtgtest.rv32i.jalr %rd, %rs, %imm
|
||||
// CHECK: rtgtest.rv32i.lb [[RD]], [[RS]], [[IMM]]
|
||||
|
|
@ -170,6 +172,40 @@ rtg.test @instructions : !rtg.dict<imm: !rtgtest.imm12, imm13: !rtgtest.imm13, l
|
|||
rtgtest.rv32i.sh %rd, %rs, %imm {rtg.some_attr}
|
||||
// CHECK: rtgtest.rv32i.sw [[RD]], [[RS]], [[IMM]] {rtg.some_attr}
|
||||
rtgtest.rv32i.sw %rd, %rs, %imm {rtg.some_attr}
|
||||
|
||||
// CHECK: rtgtest.rv32i.lui [[RD]], [[IMM32]] : !rtgtest.imm32 {rtg.some_attr}
|
||||
rtgtest.rv32i.lui %rd, %imm32 : !rtgtest.imm32 {rtg.some_attr}
|
||||
// CHECK: rtgtest.rv32i.auipc [[RD]], [[IMM32]] : !rtgtest.imm32 {rtg.some_attr}
|
||||
rtgtest.rv32i.auipc %rd, %imm32 : !rtgtest.imm32 {rtg.some_attr}
|
||||
// CHECK: rtgtest.rv32i.jal [[RD]], [[IMM21]] : !rtgtest.imm21 {rtg.some_attr}
|
||||
rtgtest.rv32i.jal %rd, %imm21 : !rtgtest.imm21 {rtg.some_attr}
|
||||
|
||||
// CHECK: rtgtest.rv32i.lui [[RD]], [[LABEL]] : !rtg.label {rtg.some_attr}
|
||||
rtgtest.rv32i.lui %rd, %label : !rtg.label {rtg.some_attr}
|
||||
// CHECK: rtgtest.rv32i.auipc [[RD]], [[LABEL]] : !rtg.label {rtg.some_attr}
|
||||
rtgtest.rv32i.auipc %rd, %label : !rtg.label {rtg.some_attr}
|
||||
// CHECK: rtgtest.rv32i.jal [[RD]], [[LABEL]] : !rtg.label {rtg.some_attr}
|
||||
rtgtest.rv32i.jal %rd, %label : !rtg.label {rtg.some_attr}
|
||||
|
||||
// CHECK: rtgtest.rv32i.addi [[RD]], [[RS]], [[IMM]] {rtg.some_attr}
|
||||
rtgtest.rv32i.addi %rd, %rs, %imm {rtg.some_attr}
|
||||
// CHECK: rtgtest.rv32i.slti [[RD]], [[RS]], [[IMM]] {rtg.some_attr}
|
||||
rtgtest.rv32i.slti %rd, %rs, %imm {rtg.some_attr}
|
||||
// CHECK: rtgtest.rv32i.sltiu [[RD]], [[RS]], [[IMM]] {rtg.some_attr}
|
||||
rtgtest.rv32i.sltiu %rd, %rs, %imm {rtg.some_attr}
|
||||
// CHECK: rtgtest.rv32i.xori [[RD]], [[RS]], [[IMM]] {rtg.some_attr}
|
||||
rtgtest.rv32i.xori %rd, %rs, %imm {rtg.some_attr}
|
||||
// CHECK: rtgtest.rv32i.ori [[RD]], [[RS]], [[IMM]] {rtg.some_attr}
|
||||
rtgtest.rv32i.ori %rd, %rs, %imm {rtg.some_attr}
|
||||
// CHECK: rtgtest.rv32i.andi [[RD]], [[RS]], [[IMM]] {rtg.some_attr}
|
||||
rtgtest.rv32i.andi %rd, %rs, %imm {rtg.some_attr}
|
||||
|
||||
// CHECK: rtgtest.rv32i.slli [[RD]], [[RS]], [[IMM5]] {rtg.some_attr}
|
||||
rtgtest.rv32i.slli %rd, %rs, %imm5 {rtg.some_attr}
|
||||
// CHECK: rtgtest.rv32i.srli [[RD]], [[RS]], [[IMM5]] {rtg.some_attr}
|
||||
rtgtest.rv32i.srli %rd, %rs, %imm5 {rtg.some_attr}
|
||||
// CHECK: rtgtest.rv32i.srai [[RD]], [[RS]], [[IMM5]] {rtg.some_attr}
|
||||
rtgtest.rv32i.srai %rd, %rs, %imm5 {rtg.some_attr}
|
||||
}
|
||||
|
||||
// -----
|
||||
|
|
|
|||
Loading…
Reference in New Issue