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AIGToComb
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[AIGToComb] [circt-synth] Add a AIG to Comb conversion pass (#7742)
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2024-10-29 14:15:41 +09:00 |
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AffineToLoopSchedule
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[LoopSchedule] Move PipelineWhile and Related Ops from Pipeline to LoopSchedule (#4947)
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2023-04-18 11:56:07 -04:00 |
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ArcToLLVM
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Bump LLVM to 289b17635958d986b74683c932df6b1d12f37b70. (#8225)
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2025-02-13 14:32:11 -07:00 |
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CFToHandshake
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Bump LLVM to 76bebb5be9daf9ca035777b17fa63d4ce13e79b9 (#8796)
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2025-07-29 17:16:26 +01:00 |
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CalyxToFSM
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[calyx] fix calyx canonicalization. (#7456)
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2024-08-10 10:02:08 -04:00 |
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CalyxToHW
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Add emission for calyx std_signext (#6285)
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2023-10-12 12:17:44 -04:00 |
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CombToAIG
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[Datapath] Create Datapath to Comb Pass (#8736)
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2025-07-25 14:13:24 +01:00 |
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CombToArith
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[CombToArith] Fix coarsening of division by zero UB (#6945)
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2024-05-06 15:59:36 +02:00 |
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CombToDatapath
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[Datapath] Conversion Pass Comb to Datapath (#8664)
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2025-07-09 08:54:55 -07:00 |
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CombToSMT
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[CombToSMT] Force conversion from bool to bv<1> after icmp (#8737)
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2025-07-18 14:02:13 +01:00 |
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ConvertToArcs
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[Seq][Arc] Allow seq.initial to take immutable operands. Add a cast operation (#7656)
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2024-10-04 02:20:12 +09:00 |
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DCToHW
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[ESI] Move to somewhat more standard asm format (#8482)
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2025-05-13 17:41:23 -07:00 |
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DatapathToComb
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[Datapath] Create Datapath to Comb Pass (#8736)
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2025-07-25 14:13:24 +01:00 |
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DatapathToSMT
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[Datapath] Add Datapath to SMT conversion pass (#8682)
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2025-07-11 08:13:11 -07:00 |
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ExportAIGER
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[AIG][AIGER] Add AIGER Exporter (#8582)
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2025-06-22 19:21:55 -07:00 |
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ExportChiselInterface
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[ExportChiselInterface] Support probe types (#5497)
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2023-06-30 09:22:46 -06:00 |
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ExportVerilog
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[Comb] Add comb.reverse operation (#8758)
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2025-07-28 11:28:22 -07:00 |
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FIRRTLToHW
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[FIRRTL] LowerToHW: handle TagExtractOp (#8726)
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2025-07-18 12:05:20 -07:00 |
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FSMToSV
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[FSMToSV] Fix bug of operations not being cloned in transition region (#8753)
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2025-07-21 17:27:07 +01:00 |
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HWArithToHW
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[HWArithToHW] Add support for unpacked arrays
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2025-07-07 19:11:21 +00:00 |
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HWToBTOR2
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[HWToBTOR2] Fix incorrect le/ge predicate name emission (#8028)
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2025-01-04 21:14:21 +00:00 |
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HWToLLVM
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[HWToLLVM] Add lowering support for 'hw.array_inject' op (#8774)
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2025-07-30 10:31:23 +02:00 |
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HWToSMT
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[HWToSMT] Return an unbound value for OOB hw.array_inject (#8794)
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2025-07-29 17:00:06 -07:00 |
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HWToSV
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[NFC][HW] Fix parsing of nullary hw.triggered ops (#7291)
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2024-07-09 17:51:03 +02:00 |
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HWToSystemC
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[HW] Change printer for modules (#6205)
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2023-09-28 16:30:15 -05:00 |
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HandshakeToDC
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[HandshakeToDC] Fix a bug in the sync conversion pattern
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2024-12-02 18:55:14 +00:00 |
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HandshakeToHW
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[Handshake] Adding func instance op for integration (#7812)
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2024-11-15 12:00:40 -08:00 |
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ImportAIGER
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[AIG][ImportAIGER] Fix incorrect tokenization and simplify parser (#8588)
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2025-06-22 16:26:41 -07:00 |
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ImportVerilog
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[ImportVerilog] Add full_case attribute support (#8762)
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2025-07-22 10:46:16 -07:00 |
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LTLToCore
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[Seq][Arc] Allow seq.initial to take immutable operands. Add a cast operation (#7656)
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2024-10-04 02:20:12 +09:00 |
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LoopScheduleToCalyx
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[NFC] fix test comment.
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2025-01-10 08:55:35 -08:00 |
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MooreToCore
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[MooreToCore] Preserve module port order (#8768)
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2025-07-23 10:39:09 -07:00 |
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PipelineToHW
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[Pipeline] Make `reset` signal optional (#8104)
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2025-01-23 14:15:50 +01:00 |
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SCFToCalyx
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[SCFToCalyx] Lower Math AbsFOp (#8492)
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2025-06-03 10:44:49 -04:00 |
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SMTToZ3LLVM
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[LowerSMTToZ3LLVM] Change printf type provided to lookupOrCreateFn (#8327)
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2025-03-19 10:21:05 +00:00 |
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SeqToSV
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[SeqToSV] Put fragments on hw.module.generated
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2025-02-01 22:11:09 -05:00 |
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SimToSV
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SimToSV: Keep plusargs non-synth === under !SYNTHESIS block (#8478)
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2025-05-15 16:13:22 -07:00 |
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VerifToSMT
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[VerifToSMT] Lower `verif.refines` to SMT (#8749)
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2025-07-23 11:42:19 +02:00 |
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VerifToSV
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[HW] Change printer for modules (#6205)
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2023-09-28 16:30:15 -05:00 |
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