mirror of https://github.com/llvm/circt.git
2f0ca3c18e
This commit introduces a new operation to the Comb dialect:
`comb.reverse`, which performs bitwise reversal (mirroring) of an
integer value.
It also adds Verilog export support for this operation using
SystemVerilog’s streaming operator `{<<{}}`.
Bit reversal is a common operation in hardware design, especially in
signal processing and communication protocols. Previously, reversing
bits required generating many explicit `assign` statements. This new
operation makes the IR cleaner and enables direct export to compact
Verilog syntax.
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| .. | ||
| basic.mlir | ||
| canonicalization.mlir | ||
| comb-int-range-narrowing.mlir | ||
| errors.mlir | ||
| lower-comb.mlir | ||