Hideto Ueno 1fb38a58ea [circt-synth] [Synthesis] Add synthesis pipeline and refactor the lib structure (#8681) ... This commit introduces a standardized synthesis pipeline and restructures the codebase: * Creates a new SynthesisPipeline class to define the default synthesis pipeline. This pipeline serves both circt-synth and is exposed through the C API for Python bindings. * Added a dedicated Synthesis directory under `lib/` to house synthesis-related code. This architectural change is aimed to promote synthesis capabilities to a first-class component within CIRCT rather than limiting it to the circt-synth tool.		2025-07-10 16:16:11 -07:00
..
arcilator	[Arcilator] Don't try to run JIT if only part of the pipeline is run (#8575)	2025-06-18 10:14:24 +01:00
circt-as	[CMake] Implement add_circt_tool() (#5821)	2023-08-10 18:37:45 -05:00
circt-bmc	[circt-bmc] Add feature to ignore asserts on some initial cycles (#8573)	2025-06-18 09:52:27 +01:00
circt-cocotb-driver	[circt-cocotb-driver.py] Fixing simulator path issue	2025-01-07 20:39:12 +00:00
circt-dis	[CMake] Implement add_circt_tool() (#5821)	2023-08-10 18:37:45 -05:00
circt-lec	[circt-lec] Implement emit-smtlib functionality for circt-lec (#8497)	2025-05-22 15:26:10 +01:00
circt-lsp-server	[CMake] Implement add_circt_tool() (#5821)	2023-08-10 18:37:45 -05:00
circt-opt	[circt-opt][Calyx] Integrate the Math to `circt-opt` and lower `math.sqrt` to Calyx (#8475)	2025-05-11 13:02:19 -04:00
circt-reduce	[circt-reduce] Add bytecode import/export (#8347)	2025-03-28 17:20:17 -04:00
circt-rtl-sim	[verilator driver] Fix for clang (#8427)	2025-04-18 16:53:33 -07:00
circt-synth	[circt-synth] [Synthesis] Add synthesis pipeline and refactor the lib structure (#8681)	2025-07-10 16:16:11 -07:00
circt-test	[Verif] Add pass to lower symbolic values (#8422)	2025-04-22 10:47:31 -07:00
circt-translate	[LLVM] bump to 9deb08a and integrate upstream SMT C APIs (#8424)	2025-04-17 15:26:22 -04:00
circt-verilog	Convert to CF before running LLHD inline. (#8667)	2025-07-08 10:07:29 -07:00
circt-verilog-lsp-server	[circt-verilog-lsp-server] Add Verilog Language Server (#8234)	2025-02-27 16:36:53 -08:00
firld	[firld] Add firld to link FIRRTL circuits (#8561)	2025-06-24 12:44:54 +08:00
firtool	[firtool] Add an option to dump MLIR errors to a json file (#8496)	2025-05-23 11:01:35 -07:00
handshake-runner	Bump LLVM to 3cc852ece438a63e7b09d1c84a81d21598454e1a. (#7847)	2024-11-21 20:15:27 -07:00
hlstool	Bump LLVM to c6c2e21028cadef854cf22f6ecaa5eb9d224b76d. (#8467)	2025-05-06 09:07:04 -06:00
kanagawatool	[Kanagawa] Replace CSE with specialized pass (#8599)	2025-06-24 18:09:44 -07:00
om-linker	bump llvm to tip of main (#7440)	2024-08-09 17:10:30 -05:00
py-split-input-file	[PyCDE] Add .py ext to py-split-input-file to make Windows happy	2022-06-17 14:13:46 +02:00
CMakeLists.txt	[firld] Add firld to link FIRRTL circuits (#8561)	2025-06-24 12:44:54 +08:00