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Analysis
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[Debug] Add scope op (#6454)
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2023-12-08 09:38:46 -08:00 |
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CAPI
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[ARC][CAPI] Add basic C API for initializing ARC (#6997)
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2024-05-09 15:48:12 -07:00 |
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Conversion
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[LLHD] Remove llhd-sim (#7351)
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2024-07-19 17:54:14 +01:00 |
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Dialect
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[Seq] Canonicalize firreg with a preset (#7350)
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2024-07-19 09:23:33 -07:00 |
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Scheduling
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FileCheck directive fixup, now filecheck_lint-clean. (#7057)
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2024-05-16 16:25:52 -05:00 |
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Target
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[SMT] Added support for :pattern attribute (#6976)
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2024-05-28 11:13:15 +02:00 |
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Tools
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[circt-bmc] Add ExternalizeRegisters Pass (#7285)
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2024-07-16 19:34:12 +01:00 |
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Transforms
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[Transforms] Also convert constants in `map-arith-to-comb`
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2023-10-03 12:30:55 +00:00 |
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Unit
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[Moore] Add SystemVerilog types (#2699)
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2022-03-04 08:48:45 +01:00 |
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arcilator
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[Arc] Hoist reset value in CompReg when lowering for simulation (#6972)
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2024-05-02 11:13:56 +02:00 |
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circt-as-dis
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[NFC, FIRRTL] Rename StrictConnect to MatchingConnect. (#7116)
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2024-06-04 09:19:00 -05:00 |
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circt-opt
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[SMT] Add Dialect rationale and boilerplate
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2024-03-12 08:12:50 +01:00 |
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circt-reduce
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[HW] Change printer for modules (#6205)
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2023-09-28 16:30:15 -05:00 |
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circt-translate
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[FIRRTL] Bump minimum to 2.0.0, remove partial conect (#5075)
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2024-06-11 11:07:18 -05:00 |
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circt-verilog
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[ImportVerilog] Fix single unit preprocessor option (#6682)
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2024-02-09 09:15:43 -08:00 |
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firtool
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[FIRRTL][FIRParser] Tokenize Commas (#7206)
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2024-07-19 02:43:37 +09:00 |
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hlstool
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Don't read lowering options from hidden global options (#4038)
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2022-10-04 15:41:03 -05:00 |
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ibistool
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[Ibis] Divorce symbol and actual names in class and container ops (#7123)
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2024-06-10 10:06:16 +02:00 |
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lib
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[NFC] Added newlines to the end of files
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2022-03-28 18:58:23 +03:00 |
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om-linker
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[OM] Register Verif dialect in om-linker.
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2024-06-07 11:10:58 -07:00 |
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CMakeLists.txt
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[LLHD] Remove llhd-sim (#7351)
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2024-07-19 17:54:14 +01:00 |
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lit.cfg.py
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[LLHD] Remove llhd-sim (#7351)
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2024-07-19 17:54:14 +01:00 |
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lit.site.cfg.py.in
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[LLHD] Remove llhd-sim (#7351)
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2024-07-19 17:54:14 +01:00 |
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