mirror of https://github.com/llvm/circt.git
254 lines
8.9 KiB
Python
254 lines
8.9 KiB
Python
# REQUIRES: bindings_python
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# RUN: %PYTHON% %s | FileCheck %s
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import circt
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from circt.dialects import rtg, rtgtest
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from circt.ir import Context, Location, Module, InsertionPoint, Block, StringAttr, TypeAttr, IndexType
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from circt.passmanager import PassManager
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from circt import rtgtool_support as rtgtool
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with Context() as ctx, Location.unknown():
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circt.register_dialects(ctx)
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m = Module.create()
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with InsertionPoint(m.body):
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cpuTy = rtgtest.CPUType.get()
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dictTy = rtg.DictType.get([(StringAttr.get('cpu0'), cpuTy),
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(StringAttr.get('cpu1'), cpuTy)], ctx)
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target = rtg.TargetOp('target_name', TypeAttr.get(dictTy))
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targetBlock = Block.create_at_start(target.bodyRegion, [])
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with InsertionPoint(targetBlock):
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cpuAttr = rtgtest.CPUAttr.get(0)
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cpu0 = rtg.ConstantOp(cpuAttr)
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cpu1 = rtg.ConstantOp(rtgtest.CPUAttr.get(cpuAttr.id + 1))
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rtg.YieldOp([cpu0, cpu1])
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test = rtg.TestOp('test_name', 'test_name', TypeAttr.get(dictTy))
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Block.create_at_start(test.bodyRegion, [cpuTy, cpuTy])
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# CHECK: rtg.target @target_name : !rtg.dict<cpu0: !rtgtest.cpu, cpu1: !rtgtest.cpu> {
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# CHECK: [[V0:%.+]] = rtg.constant #rtgtest.cpu<0>
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# CHECK: [[V1:%.+]] = rtg.constant #rtgtest.cpu<1>
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# CHECK: rtg.yield [[V0]], [[V1]] : !rtgtest.cpu, !rtgtest.cpu
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# CHECK: }
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# CHECK: rtg.test @test_name(cpu0 = %cpu0: !rtgtest.cpu, cpu1 = %cpu1: !rtgtest.cpu) {
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# CHECK: }
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print(m)
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with Context() as ctx, Location.unknown():
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circt.register_dialects(ctx)
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m = Module.create()
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with InsertionPoint(m.body):
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setTy = rtg.SetType.get(rtg.SequenceType.get())
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seq = rtg.SequenceOp('seq', TypeAttr.get(rtg.SequenceType.get([setTy])))
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seqBlock = Block.create_at_start(seq.bodyRegion, [setTy])
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# CHECK: !rtg.sequence{{$}}
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print(setTy.element_type)
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# CHECK: rtg.sequence @seq(%{{.*}}: !rtg.set<!rtg.sequence>) {
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# CHECK: }
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print(m)
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with Context() as ctx, Location.unknown():
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circt.register_dialects(ctx)
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m = Module.create()
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with InsertionPoint(m.body):
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seq = rtg.SequenceOp('sequence_name', TypeAttr.get(rtg.SequenceType.get()))
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Block.create_at_start(seq.bodyRegion, [])
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test = rtg.TestOp('test_name', 'test_name',
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TypeAttr.get(rtg.DictType.get()))
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block = Block.create_at_start(test.bodyRegion, [])
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with InsertionPoint(block):
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seq_get = rtg.GetSequenceOp(rtg.SequenceType.get(), 'sequence_name')
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rtg.RandomizeSequenceOp(seq_get)
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target = rtg.TargetOp('target', TypeAttr.get(rtg.DictType.get()))
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block = Block.create_at_start(target.bodyRegion, [])
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with InsertionPoint(block):
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rtg.YieldOp([])
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# CHECK: rtg.test @test_name() {
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# CHECK-NEXT: [[SEQ:%.+]] = rtg.get_sequence @sequence_name
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# CHECK-NEXT: rtg.randomize_sequence [[SEQ]]
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# CHECK-NEXT: }
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print(m)
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pm = PassManager()
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options = rtgtool.Options(
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seed=0,
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output_format=rtgtool.OutputFormat.ELABORATED_MLIR,
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)
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rtgtool.populate_randomizer_pipeline(pm, options)
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pm.run(m.operation)
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# CHECK: rtg.test @test_name_target() template "test_name" target @target {
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# CHECK-NEXT: }
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print(m)
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with Context() as ctx, Location.unknown():
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circt.register_dialects(ctx)
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m = Module.create()
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with InsertionPoint(m.body):
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indexTy = IndexType.get()
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sequenceTy = rtg.SequenceType.get()
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labelTy = rtg.LabelType.get()
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setTy = rtg.SetType.get(indexTy)
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bagTy = rtg.BagType.get(indexTy)
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ireg = rtgtest.IntegerRegisterType.get()
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randomizedSequenceTy = rtg.RandomizedSequenceType.get()
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seq = rtg.SequenceOp(
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'seq',
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TypeAttr.get(
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rtg.SequenceType.get(
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[sequenceTy, labelTy, setTy, bagTy, ireg,
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randomizedSequenceTy])))
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Block.create_at_start(
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seq.bodyRegion,
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[sequenceTy, labelTy, setTy, bagTy, ireg, randomizedSequenceTy])
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# CHECK: index{{$}}
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print(bagTy.element_type)
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# CHECK: rtg.sequence @seq(%{{.*}}: !rtg.sequence, %{{.*}}: !rtg.isa.label, %{{.*}}: !rtg.set<index>, %{{.*}}: !rtg.bag<index>, %{{.*}}: !rtgtest.ireg, %{{.*}}: !rtg.randomized_sequence)
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print(m)
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with Context() as ctx, Location.unknown():
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circt.register_dialects(ctx)
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m = Module.create()
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with InsertionPoint(m.body):
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# CHECK: rtg.fixed_reg #rtgtest.zero
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rtg.FixedRegisterOp(rtgtest.RegZeroAttr.get())
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# CHECK: rtg.fixed_reg #rtgtest.ra
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rtg.FixedRegisterOp(rtgtest.RegRaAttr.get())
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# CHECK: rtg.fixed_reg #rtgtest.sp
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rtg.FixedRegisterOp(rtgtest.RegSpAttr.get())
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# CHECK: rtg.fixed_reg #rtgtest.gp
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rtg.FixedRegisterOp(rtgtest.RegGpAttr.get())
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# CHECK: rtg.fixed_reg #rtgtest.tp
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rtg.FixedRegisterOp(rtgtest.RegTpAttr.get())
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# CHECK: rtg.fixed_reg #rtgtest.t0
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rtg.FixedRegisterOp(rtgtest.RegT0Attr.get())
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# CHECK: rtg.fixed_reg #rtgtest.t1
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rtg.FixedRegisterOp(rtgtest.RegT1Attr.get())
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# CHECK: rtg.fixed_reg #rtgtest.t2
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rtg.FixedRegisterOp(rtgtest.RegT2Attr.get())
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# CHECK: rtg.fixed_reg #rtgtest.s0
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rtg.FixedRegisterOp(rtgtest.RegS0Attr.get())
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# CHECK: rtg.fixed_reg #rtgtest.s1
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rtg.FixedRegisterOp(rtgtest.RegS1Attr.get())
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# CHECK: rtg.fixed_reg #rtgtest.a0
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rtg.FixedRegisterOp(rtgtest.RegA0Attr.get())
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# CHECK: rtg.fixed_reg #rtgtest.a1
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rtg.FixedRegisterOp(rtgtest.RegA1Attr.get())
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# CHECK: rtg.fixed_reg #rtgtest.a2
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rtg.FixedRegisterOp(rtgtest.RegA2Attr.get())
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# CHECK: rtg.fixed_reg #rtgtest.a3
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rtg.FixedRegisterOp(rtgtest.RegA3Attr.get())
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# CHECK: rtg.fixed_reg #rtgtest.a4
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rtg.FixedRegisterOp(rtgtest.RegA4Attr.get())
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# CHECK: rtg.fixed_reg #rtgtest.a5
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rtg.FixedRegisterOp(rtgtest.RegA5Attr.get())
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# CHECK: rtg.fixed_reg #rtgtest.a6
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rtg.FixedRegisterOp(rtgtest.RegA6Attr.get())
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# CHECK: rtg.fixed_reg #rtgtest.a7
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rtg.FixedRegisterOp(rtgtest.RegA7Attr.get())
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# CHECK: rtg.fixed_reg #rtgtest.s2
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rtg.FixedRegisterOp(rtgtest.RegS2Attr.get())
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# CHECK: rtg.fixed_reg #rtgtest.s3
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rtg.FixedRegisterOp(rtgtest.RegS3Attr.get())
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# CHECK: rtg.fixed_reg #rtgtest.s4
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rtg.FixedRegisterOp(rtgtest.RegS4Attr.get())
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# CHECK: rtg.fixed_reg #rtgtest.s5
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rtg.FixedRegisterOp(rtgtest.RegS5Attr.get())
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# CHECK: rtg.fixed_reg #rtgtest.s6
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rtg.FixedRegisterOp(rtgtest.RegS6Attr.get())
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# CHECK: rtg.fixed_reg #rtgtest.s7
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rtg.FixedRegisterOp(rtgtest.RegS7Attr.get())
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# CHECK: rtg.fixed_reg #rtgtest.s8
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rtg.FixedRegisterOp(rtgtest.RegS8Attr.get())
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# CHECK: rtg.fixed_reg #rtgtest.s9
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rtg.FixedRegisterOp(rtgtest.RegS9Attr.get())
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# CHECK: rtg.fixed_reg #rtgtest.s10
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rtg.FixedRegisterOp(rtgtest.RegS10Attr.get())
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# CHECK: rtg.fixed_reg #rtgtest.s11
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rtg.FixedRegisterOp(rtgtest.RegS11Attr.get())
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# CHECK: rtg.fixed_reg #rtgtest.t3
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rtg.FixedRegisterOp(rtgtest.RegT3Attr.get())
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# CHECK: rtg.fixed_reg #rtgtest.t4
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rtg.FixedRegisterOp(rtgtest.RegT4Attr.get())
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# CHECK: rtg.fixed_reg #rtgtest.t5
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rtg.FixedRegisterOp(rtgtest.RegT5Attr.get())
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# CHECK: rtg.fixed_reg #rtgtest.t6
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rtg.FixedRegisterOp(rtgtest.RegT6Attr.get())
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print(m)
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with Context() as ctx, Location.unknown():
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circt.register_dialects(ctx)
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m = Module.create()
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with InsertionPoint(m.body):
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seq = rtg.SequenceOp('seq', TypeAttr.get(rtg.SequenceType.get([])))
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block = Block.create_at_start(seq.bodyRegion, [])
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with InsertionPoint(block):
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l = rtg.label_decl("label", [])
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visibility = rtg.LabelVisibilityAttr.get(rtg.GLOBAL)
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rtg.label(visibility, l)
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assert visibility.value == rtg.GLOBAL
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# CHECK: rtg.sequence @seq
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# CHECK: rtg.label_decl "label"
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# CHECK: rtg.label global {{%.+}}
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print(m)
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with Context() as ctx, Location.unknown():
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circt.register_dialects(ctx)
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attr = rtg.DefaultContextAttr.get(rtgtest.CPUType.get())
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# CHECK: !rtgtest.cpu
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print(attr.type)
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# CHECK: #rtg.default : !rtgtest.cpu
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print(attr)
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attr = rtg.AnyContextAttr.get(rtgtest.CPUType.get())
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# CHECK: !rtgtest.cpu
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print(attr.type)
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# CHECK: #rtg.any_context : !rtgtest.cpu
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print(attr)
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immediate_type = rtg.ImmediateType.get(32)
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# CHECK: width=32
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print(f"width={immediate_type.width}")
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# CHECK: !rtg.isa.immediate<32>
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print(immediate_type)
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immediate_attr = rtg.ImmediateAttr.get(32, 42)
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# CHECK: width=32
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print(f"width={immediate_attr.width}")
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# CHECK: value=42
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print(f"value={immediate_attr.value}")
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# CHECK: #rtg.isa.immediate<32, 42>
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print(immediate_attr)
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memory_block_type = rtg.MemoryBlockType.get(32)
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# CHECK: width=32
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print(f"width={memory_block_type.address_width}")
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# CHECK: !rtg.isa.memory_block<32>
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print(memory_block_type)
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memoryTy = rtg.MemoryType.get(32)
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# CHECK: address_width=32
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print(f'address_width={memoryTy.address_width}')
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# CHECK: !rtg.isa.memory<32>
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print(memoryTy)
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with Context() as ctx, Location.unknown():
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circt.register_dialects(ctx)
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indexTy = IndexType.get()
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arr = rtg.ArrayType.get(indexTy)
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# CHECK: element_type=index
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print(f"element_type={arr.element_type}")
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# CHECK: !rtg.array<index>
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print(arr)
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