5f6c93701b
Temporarily revert this. This breaks Olden/bisort on PPC
...
llvm-svn: 30628
2006-09-27 16:59:16 +00:00
0a7f617a6c
PR878: Instead of calculating the vreg to PHI use count everytime we get
...
a function, do it up front in linear time (going through all of the
instructions once). We create a map out of them. Then it's no problem to
use the information in it during elimination...
llvm-svn: 30624
2006-09-27 09:04:15 +00:00
30b4708df2
Add support for ${:private} which prints "L" on darwin.
...
llvm-svn: 30620
2006-09-27 00:06:07 +00:00
a32814b033
Add support for ${:comment}, which expands to the current target's comment
...
character, and ${:uid} which expands to a unique ID for the MachineInstr.
More can be added if/when they are needed.
llvm-svn: 30619
2006-09-26 23:59:50 +00:00
5405c06737
Rename function. It's determining which callee-save registers to save.
...
llvm-svn: 30616
2006-09-26 22:29:31 +00:00
c19ef92403
Comments on JumpTableness
...
llvm-svn: 30615
2006-09-26 20:02:30 +00:00
60832693a7
Load chain check is not needed
...
llvm-svn: 30613
2006-09-26 17:44:58 +00:00
dde51671e5
Chain can be any operand
...
llvm-svn: 30611
2006-09-26 09:32:41 +00:00
5f3e0af9d0
Wrong size for load
...
llvm-svn: 30610
2006-09-26 08:14:06 +00:00
b4a864d533
Can't move a load node if it's chain is not used.
...
llvm-svn: 30609
2006-09-26 07:37:42 +00:00
9a1e91b107
print the preds of each MBB
...
llvm-svn: 30606
2006-09-26 03:41:59 +00:00
66af390631
Add support for targets that want to do something with the llvm.used list,
...
because they have an aggressive linker that does dead code stripping.
llvm-svn: 30604
2006-09-26 03:38:18 +00:00
7aa0638aa9
Accidental enable of bad code
...
llvm-svn: 30601
2006-09-25 21:11:32 +00:00
b5534e5c28
Fix chain dropping in load and drop unused stores in ret blocks.
...
llvm-svn: 30600
2006-09-25 19:32:58 +00:00
d07be232ba
Core antialiasing for load and store.
...
llvm-svn: 30597
2006-09-25 16:29:54 +00:00
783a4a9d86
Add support for other relocation bases to jump tables, as well as custom asm directives
...
llvm-svn: 30593
2006-09-24 19:45:58 +00:00
77c0757f8b
PIC jump table entries are always 32-bit. This fixes PIC jump table support on X86-64.
...
llvm-svn: 30590
2006-09-24 05:22:38 +00:00
449a0c7e33
Make it work for DAG combine of multi-value nodes.
...
llvm-svn: 30573
2006-09-21 19:04:05 +00:00
35f7eebb49
core corrections
...
llvm-svn: 30570
2006-09-21 17:35:47 +00:00
5d19d59017
Basic "in frame" alias analysis.
...
llvm-svn: 30568
2006-09-21 16:28:59 +00:00
082db3f9aa
fold (aext (and (trunc x), cst)) -> (and x, cst).
...
llvm-svn: 30561
2006-09-21 06:40:43 +00:00
fa9f92cf65
Check the right value type. This fixes 186.crafty on x86
...
llvm-svn: 30560
2006-09-21 06:17:39 +00:00
8d8a3bf9c9
Compile:
...
int %test(ulong *%tmp) {
%tmp = load ulong* %tmp ; <ulong> [#uses=1]
%tmp.mask = shr ulong %tmp, ubyte 50 ; <ulong> [#uses=1]
%tmp.mask = cast ulong %tmp.mask to ubyte
%tmp2 = and ubyte %tmp.mask, 3 ; <ubyte> [#uses=1]
%tmp2 = cast ubyte %tmp2 to int ; <int> [#uses=1]
ret int %tmp2
}
to:
_test:
movl 4(%esp), %eax
movl 4(%eax), %eax
shrl $18, %eax
andl $3, %eax
ret
instead of:
_test:
movl 4(%esp), %eax
movl 4(%eax), %eax
shrl $18, %eax
# TRUNCATE movb %al, %al
andb $3, %al
movzbl %al, %eax
ret
llvm-svn: 30558
2006-09-21 06:14:31 +00:00
a31f0a622b
Generalize (zext (truncate x)) and (sext (truncate x)) folding to work when
...
the src/dst are not the same size. This catches things like "truncate
32-bit X to 8 bits, then zext to 16", which happens a bit on X86.
llvm-svn: 30557
2006-09-21 06:00:20 +00:00
c8cd62d381
Compile:
...
int test3(int a, int b) { return (a < 0) ? a : 0; }
to:
_test3:
srawi r2, r3, 31
and r3, r2, r3
blr
instead of:
_test3:
cmpwi cr0, r3, 1
li r2, 0
blt cr0, LBB2_2 ;entry
LBB2_1: ;entry
mr r3, r2
LBB2_2: ;entry
blr
This implements: PowerPC/select_lt0.ll:seli32_a_a
llvm-svn: 30517
2006-09-20 06:41:35 +00:00
8746e2cd57
Fold the full generality of (any_extend (truncate x))
...
llvm-svn: 30514
2006-09-20 06:29:17 +00:00
8b68decb27
Two things:
...
1. teach SimplifySetCC that '(srl (ctlz x), 5) == 0' is really x != 0.
2. Teach visitSELECT_CC to use SimplifySetCC instead of calling it and
ignoring the result. This allows us to compile:
bool %test(ulong %x) {
%tmp = setlt ulong %x, 4294967296
ret bool %tmp
}
to:
_test:
cntlzw r2, r3
cmplwi cr0, r3, 1
srwi r2, r2, 5
li r3, 0
beq cr0, LBB1_2 ;
LBB1_1: ;
mr r3, r2
LBB1_2: ;
blr
instead of:
_test:
addi r2, r3, -1
cntlzw r2, r2
cntlzw r3, r3
srwi r2, r2, 5
cmplwi cr0, r2, 0
srwi r2, r3, 5
li r3, 0
bne cr0, LBB1_2 ;
LBB1_1: ;
mr r3, r2
LBB1_2: ;
blr
This isn't wonderful, but it's an improvement.
llvm-svn: 30513
2006-09-20 06:19:26 +00:00
875ea0cdbd
Expand 64-bit shifts more optimally if we know that the high bit of the
...
shift amount is one or zero. For example, for:
long long foo1(long long X, int C) {
return X << (C|32);
}
long long foo2(long long X, int C) {
return X << (C&~32);
}
we get:
_foo1:
movb $31, %cl
movl 4(%esp), %edx
andb 12(%esp), %cl
shll %cl, %edx
xorl %eax, %eax
ret
_foo2:
movb $223, %cl
movl 4(%esp), %eax
movl 8(%esp), %edx
andb 12(%esp), %cl
shldl %cl, %eax, %edx
shll %cl, %eax
ret
instead of:
_foo1:
subl $4, %esp
movl %ebx, (%esp)
movb $32, %bl
movl 8(%esp), %eax
movl 12(%esp), %edx
movb %bl, %cl
orb 16(%esp), %cl
shldl %cl, %eax, %edx
shll %cl, %eax
xorl %ecx, %ecx
testb %bl, %bl
cmovne %eax, %edx
cmovne %ecx, %eax
movl (%esp), %ebx
addl $4, %esp
ret
_foo2:
subl $4, %esp
movl %ebx, (%esp)
movb $223, %cl
movl 8(%esp), %eax
movl 12(%esp), %edx
andb 16(%esp), %cl
shldl %cl, %eax, %edx
shll %cl, %eax
xorl %ecx, %ecx
xorb %bl, %bl
testb %bl, %bl
cmovne %eax, %edx
cmovne %ecx, %eax
movl (%esp), %ebx
addl $4, %esp
ret
llvm-svn: 30506
2006-09-20 03:38:48 +00:00
698000b0da
Fix UnitTests/2005-05-12-Int64ToFP.c with llc-beta. In particular, do not
...
allow it to go into an infinite loop, filling up the disk!
llvm-svn: 30494
2006-09-19 18:02:01 +00:00
5a42ebcff3
Fold extract_element(cst) to cst
...
llvm-svn: 30478
2006-09-19 05:02:39 +00:00
4c059f4962
Minor speedup for legalize by avoiding some malloc traffic
...
llvm-svn: 30477
2006-09-19 04:51:23 +00:00
1fc7c363e6
Fix a typo.
...
llvm-svn: 30474
2006-09-18 23:28:33 +00:00
4bfaf0bd2c
Allow i32 UDIV, SDIV, UREM, SREM to be expanded into libcalls.
...
llvm-svn: 30470
2006-09-18 21:49:04 +00:00
51ad73c98c
oops
...
llvm-svn: 30462
2006-09-18 18:00:18 +00:00
c50458fb90
absolute addresses must match pointer size
...
llvm-svn: 30461
2006-09-18 17:59:35 +00:00
d30bba331f
Sort out mangled names for globals
...
llvm-svn: 30460
2006-09-18 14:47:26 +00:00
e50f5d1fb1
Oh yeah, this is needed too
...
llvm-svn: 30407
2006-09-16 05:08:34 +00:00
1b63391fdf
simplify control flow, no functionality change
...
llvm-svn: 30403
2006-09-16 00:21:44 +00:00
fbadbda6ba
Allow custom expand of mul
...
llvm-svn: 30402
2006-09-16 00:09:24 +00:00
8fb3d445f5
Keep track of the start of MBB's in a separate map from instructions. This
...
is faster and is needed for future improvements.
llvm-svn: 30383
2006-09-15 03:57:23 +00:00
46d710e6ea
Fold (X & C1) | (Y & C2) -> (X|Y) & C3 when possible.
...
This implements CodeGen/X86/and-or-fold.ll
llvm-svn: 30379
2006-09-14 21:11:37 +00:00
97614c86ce
Split rotate matching code out to its own function. Make it stronger, by
...
matching things like ((x >> c1) & c2) | ((x << c3) & c4) to (rot x, c5) & c6
llvm-svn: 30376
2006-09-14 20:50:57 +00:00
616aa548b2
Use getOffset() instead.
...
llvm-svn: 30327
2006-09-14 07:41:12 +00:00
2ad050fb3e
Use MachineConstantPoolEntry getOffset() and getType() accessors.
...
llvm-svn: 30326
2006-09-14 07:35:00 +00:00
4f9299552b
A MachineConstantPool may have mixed Constant* and MachineConstantPoolValue* values.
...
llvm-svn: 30316
2006-09-14 05:50:57 +00:00
84cc1f7cb8
If LSR went through a lot of trouble to put constants (e.g. the addr of a global
...
in a specific BB, don't undo this!). This allows us to compile
CodeGen/X86/loop-hoist.ll into:
_foo:
xorl %eax, %eax
*** movl L_Arr$non_lazy_ptr, %ecx
movl 4(%esp), %edx
LBB1_1: #cond_true
movl %eax, (%ecx,%eax,4)
incl %eax
cmpl %edx, %eax
jne LBB1_1 #cond_true
LBB1_2: #return
ret
instead of:
_foo:
xorl %eax, %eax
movl 4(%esp), %ecx
LBB1_1: #cond_true
*** movl L_Arr$non_lazy_ptr, %edx
movl %eax, (%edx,%eax,4)
incl %eax
cmpl %ecx, %eax
jne LBB1_1 #cond_true
LBB1_2: #return
ret
This was noticed in 464.h264ref. This doesn't usually affect PPC,
but strikes X86 all the time.
llvm-svn: 30290
2006-09-13 06:02:42 +00:00
72b503bcad
Compile X << 1 (where X is a long-long) to:
...
addl %ecx, %ecx
adcl %eax, %eax
instead of:
movl %ecx, %edx
addl %edx, %edx
shrl $31, %ecx
addl %eax, %eax
orl %ecx, %eax
and to:
addc r5, r5, r5
adde r4, r4, r4
instead of:
slwi r2,r9,1
srwi r0,r11,31
slwi r3,r11,1
or r2,r0,r2
on PPC.
llvm-svn: 30284
2006-09-13 03:50:39 +00:00
45fe3bc72c
Added support for machine specific constantpool values. These are useful for
...
representing expressions that can only be resolved at link time, etc.
llvm-svn: 30278
2006-09-12 21:00:35 +00:00
a0d95a8da9
Behold, more work on relocations. Things are looking pretty good now.
...
llvm-svn: 30240
2006-09-10 23:03:44 +00:00
2e0dfb0b16
This code was trying too hard. By eliminating redundant edges in the CFG
...
due to switch cases going to the same place, it make #pred != #phi entries,
breaking live interval analysis.
This fixes 458.sjeng on x86 with llc.
llvm-svn: 30236
2006-09-10 06:36:57 +00:00
f0359b343a
Implement the fpowi now by lowering to a libcall
...
llvm-svn: 30225
2006-09-09 06:03:30 +00:00
e4bbb6c341
Allow targets to custom lower expanded BIT_CONVERT's
...
llvm-svn: 30217
2006-09-09 00:20:27 +00:00
69df6132d7
First pass at supporting relocations. Relocations are written correctly to
...
the file now, however the relocated address is currently wrong. Fixing
that will require some deep pondering.
llvm-svn: 30207
2006-09-08 22:42:09 +00:00
b2e7316b2d
Non-allocatable physregs can be killed and dead, but don't treat them as
...
safe for later allocation. This fixes McCat/18-imp with llc-beta.
llvm-svn: 30204
2006-09-08 20:21:31 +00:00
050c64c51d
This fixes Benchmarks/Prolangs-C/unix-smail
...
llvm-svn: 30198
2006-09-08 19:11:11 +00:00
9b1a6ebf20
Fix a bunch of llc-beta failures on x86 yesterday. Don't allow selection
...
of unallocatable registers, just because an alias is allocatable. We were
picking registers like SIL just because ESI was being used.
llvm-svn: 30197
2006-09-08 19:03:30 +00:00
261779bb45
Make target asm info a property of the target machine.
...
llvm-svn: 30162
2006-09-07 22:06:40 +00:00
95b3dde8bb
Fix pasto that was breaking x86 tests.
...
llvm-svn: 30151
2006-09-07 18:50:20 +00:00
707339a57b
Fix CodeGen/Generic/2006-09-06-SwitchLowering.ll, a bug where SDIsel inserted
...
too many phi operands when lowering a switch to branches in some cases.
llvm-svn: 30142
2006-09-07 01:59:34 +00:00
a6211dcdad
Separate target specific asm properties from the asm printers.
...
llvm-svn: 30126
2006-09-06 18:34:40 +00:00
ddfb10b5af
Only call isUse/isDef on register operands
...
llvm-svn: 30122
2006-09-05 20:32:06 +00:00
2cb238320d
Only call isUse/isDef on register operands
...
llvm-svn: 30118
2006-09-05 20:19:27 +00:00
45456d44e3
Don't call isDef on non-registers
...
llvm-svn: 30117
2006-09-05 20:02:51 +00:00
0dce3311c4
Change the default to 0, which means 'default'.
...
llvm-svn: 30114
2006-09-05 17:39:15 +00:00
af23f9b5f6
Completely eliminate def&use operands. Now a register operand is EITHER a
...
def operand or a use operand.
llvm-svn: 30109
2006-09-05 02:31:13 +00:00
13a5dcddce
Fix a long-standing wart in the code generator: two-address instruction lowering
...
actually *removes* one of the operands, instead of just assigning both operands
the same register. This make reasoning about instructions unnecessarily complex,
because you need to know if you are before or after register allocation to match
up operand #'s with the target description file.
Changing this also gets rid of a bunch of hacky code in various places.
This patch also includes changes to fold loads into cmp/test instructions in
the X86 backend, along with a significant simplification to the X86 spill
folding code.
llvm-svn: 30108
2006-09-05 02:12:02 +00:00
1eed04d1fb
Correct fix for a crasher on functions with live in values
...
llvm-svn: 30099
2006-09-04 18:27:40 +00:00
bff0b5969f
Hack around a regression I introduced yesterday
...
llvm-svn: 30098
2006-09-04 18:20:15 +00:00
373be1d1a2
forgot this
...
llvm-svn: 30097
2006-09-04 07:44:11 +00:00
cf6749e4c0
add setJumpBufSize() and setJumpBufAlignment() to target-lowering.
...
Call these from your backend to enjoy setjmp/longjmp goodness, see
lib/Target/IA64/IA64ISelLowering.cpp for an example
llvm-svn: 30095
2006-09-04 06:21:35 +00:00
a916db12e4
new file
...
llvm-svn: 30082
2006-09-04 04:16:09 +00:00
8584e940b8
Avoid beating on the mi2i map when we know the answer already.
...
llvm-svn: 30066
2006-09-03 08:07:11 +00:00
774785a79d
minor speedup
...
llvm-svn: 30065
2006-09-03 07:53:50 +00:00
7cc20d418b
Fix Regression/CodeGen/Generic/2006-09-02-LocalAllocCrash.ll on X86.
...
Just because an alias of a register is available, it doesn't mean that we
can arbitrarily evict the register.
llvm-svn: 30064
2006-09-03 07:15:37 +00:00
bd79458b0e
When deleting a machine instruction, make sure to remove it from the
...
livevariables information. This fixes several regalloc=local failures on x86
llvm-svn: 30062
2006-09-03 00:06:08 +00:00
f8f724a2b1
Move two methods out of line, make them work when the record for a machine
...
instruction includes physregs.
llvm-svn: 30061
2006-09-03 00:05:09 +00:00
f2ce949ae9
improve compat with certain versions of GCC (on cygwin?)
...
llvm-svn: 30054
2006-09-02 17:37:30 +00:00
75742e532a
Iteration is required for some cases, even if they don't occur in crafty.
...
Restore it, which re-fixes X86/2006-08-21-ExtraMovInst.ll
llvm-svn: 30050
2006-09-02 05:32:53 +00:00
5a56d30906
When joining two intervals where the RHS is really simple, use a light-weight
...
method for joining the live ranges instead of the fully-general one.
llvm-svn: 30049
2006-09-02 05:26:59 +00:00
e93762d36e
Allow legalizer to expand ISD::MUL using only MULHS in the rare case that is
...
possible and the target only supports MULHS.
llvm-svn: 30022
2006-09-01 18:17:58 +00:00
5352d0cc4d
Corrections.
...
llvm-svn: 30021
2006-09-01 12:55:05 +00:00
93c067dc2d
Pull some code out of a hot recursive function because the common case doesn't
...
need recursion.
llvm-svn: 30015
2006-09-01 07:00:23 +00:00
3eac2c87aa
Reserve space in the ValueNumberInfo vector. This speeds up live interval
...
analysis 16% on crafty.
Wrap long lines.
llvm-svn: 30012
2006-09-01 06:10:18 +00:00
f765351978
Iterative coallescing doesn't buy us anything (we get identical results on
...
crafty with and without it). Removing it speeds up live intervals 6%.
llvm-svn: 30010
2006-09-01 04:02:42 +00:00
31305c45da
DAG combiner fix for rotates. Previously the outer-most condition checks
...
for ROTL availability. This prevents it from forming ROTR for targets that
has ROTR only.
llvm-svn: 29997
2006-08-31 07:41:12 +00:00
a700a19d04
Add a special case that speeds up coallescing a bit, but not enough.
...
llvm-svn: 29996
2006-08-31 06:48:26 +00:00
78cca7243c
Delete copies as they are coallesced instead of waiting until the end.
...
llvm-svn: 29995
2006-08-31 05:58:59 +00:00
aa36808fd3
avoid calling the virtual isMoveInstr method endlessly by caching its results.
...
llvm-svn: 29994
2006-08-31 05:54:43 +00:00
cb74860cce
Fix a compiler crash bootstrapping llvm-gcc.
...
llvm-svn: 29989
2006-08-30 23:02:29 +00:00
34434e97c9
Teach the coallescer to coallesce live intervals joined by an arbitrary
...
number of copies, potentially defining live ranges that appear to have
differing value numbers that become identical when coallsced. Among other
things, this fixes CodeGen/X86/shift-coalesce.ll and PR687.
llvm-svn: 29968
2006-08-29 23:18:15 +00:00
2eebe8b05e
Handle callee saved registers in dwarf frame info (lead up to exception
...
handling.)
llvm-svn: 29954
2006-08-29 16:24:26 +00:00
e5570a4c3f
Move isCommutativeBinOp from SelectionDAG.cpp and DAGCombiner.cpp out. Make it a static method of SelectionDAG.
...
llvm-svn: 29951
2006-08-29 06:42:35 +00:00
c2d3d3112e
eliminate RegisterOpt. It does the same thing as RegisterPass.
...
llvm-svn: 29925
2006-08-27 22:42:52 +00:00
3c9b2420df
Eliminate RegisterAnalysis. RegisterPass now does all that is necessary.
...
llvm-svn: 29921
2006-08-27 22:30:17 +00:00
3d27be1333
s|llvm/Support/Visibility.h|llvm/Support/Compiler.h|
...
llvm-svn: 29911
2006-08-27 12:54:02 +00:00
2c3683a901
typo fix
...
llvm-svn: 29910
2006-08-27 12:47:48 +00:00
849f4bf8dd
Eliminate SelectNodeTo() and getTargetNode() variants which take more than
...
3 SDOperand operands. They are replaced by versions which take an array
of SDOperand and the number of operands.
llvm-svn: 29905
2006-08-27 08:08:54 +00:00
7851db75d9
Properly size the string table, and emit symbol table and string table
...
entries in the correct order, fixing several fixmes.
llvm-svn: 29902
2006-08-26 15:46:34 +00:00
34b70eea5c
SelectNodeTo now returns a SDNode*.
...
llvm-svn: 29901
2006-08-26 08:00:10 +00:00
122f2bcdc2
Simplifications to liveinterval analysis, no functionality change.
...
llvm-svn: 29896
2006-08-26 01:28:16 +00:00
f4f0b1995c
Completely change the way that joining with physregs is implemented. This
...
paves the way for future changes, increases coallescing opportunities (in
theory, not witnessed in practice), and eliminates the really expensive
LiveIntervals::overlapsAliases method.
llvm-svn: 29890
2006-08-25 23:41:24 +00:00
fb96c74874
Tidy up.
...
llvm-svn: 29888
2006-08-25 22:56:30 +00:00
92206f9404
Consolidate callee saved register information so that it can me used by debug
...
information and exception handling.
llvm-svn: 29881
2006-08-25 19:45:51 +00:00
f8bf1e6034
Allow for register numbers > 31.
...
llvm-svn: 29879
2006-08-25 19:39:52 +00:00
89fa9c7d65
Get closer to handling globals correctly. We now generally get them in the
...
right section.
llvm-svn: 29871
2006-08-25 06:36:58 +00:00
24d4208c97
When replacing value numbers, make sure to compactify the value # space.
...
llvm-svn: 29865
2006-08-24 23:22:59 +00:00
bdf121060c
Take advantage of the recent improvements to the liveintervals set (tracking
...
instructions which define each value#) to simplify and improve the coallescer.
In particular, this patch:
1. Implements iterative coallescing.
2. Reverts an unsafe hack from handlePhysRegDef, superceeding it with a
better solution.
3. Implements PR865, "coallescing" away the second copy in code like:
A = B
...
B = A
This also includes changes to symbolically print registers in intervals
when possible.
llvm-svn: 29862
2006-08-24 22:43:55 +00:00
3cb3921a60
Initial checkin of the Mach-O emitter. There's plenty of fixmes, but it
...
does emit linkable .o files in very simple cases.
llvm-svn: 29850
2006-08-23 21:08:52 +00:00
2e9f1bc056
Improve the LiveInterval class to keep track of which machine instruction
...
defines each value# tracked by the interval. This will be used to improve
coallescing.
llvm-svn: 29830
2006-08-22 18:19:46 +00:00
1d77a0ff88
Print physreg names symbolically in dumps
...
llvm-svn: 29805
2006-08-21 23:03:54 +00:00
213159a6ee
Print debug info as:
...
*** Register mapping ***
reg 1024 -> %reg1028
reg 1026 -> EAX
reg 1027 -> %reg1028
instead of:
*** Register mapping ***
reg 1024 -> reg 1028
reg 1026 -> reg 15
reg 1027 -> reg 1028
llvm-svn: 29803
2006-08-21 22:56:29 +00:00
b6ac11e120
Adding C++ member support.
...
llvm-svn: 29799
2006-08-21 21:20:18 +00:00
451b099113
Fix PR861
...
llvm-svn: 29796
2006-08-21 20:24:53 +00:00
04f2246400
Added a check so that if we have two machine instructions in this form
...
MOV R0, R1
MOV R1, R0
the second machine instruction is removed. Added a regression test.
llvm-svn: 29792
2006-08-21 07:33:33 +00:00
d86418ab20
switch the SUnit pred/succ sets from being std::sets to being smallvectors.
...
This reduces selectiondag time on kc++ from 5.43s to 4.98s (9%). More
significantly, this speeds up the default ppc scheduler from ~1571ms to 1063ms,
a 33% speedup.
llvm-svn: 29743
2006-08-17 00:09:56 +00:00
65879caf07
minor changes.
...
llvm-svn: 29740
2006-08-16 22:57:46 +00:00
a4f3625c23
Use the appropriate typedef
...
llvm-svn: 29730
2006-08-16 20:59:32 +00:00
a5a3eafbd0
Start using SDVTList more consistently
...
llvm-svn: 29711
2006-08-15 19:11:05 +00:00
f98411a220
add a new SDVTList type and new SelectionDAG::getVTList methods to streamline
...
the creation of canonical VTLists.
llvm-svn: 29709
2006-08-15 17:46:01 +00:00
bd8877744b
eliminate use of getNode that takes vector of valuetypes.
...
llvm-svn: 29687
2006-08-14 23:53:35 +00:00
3bf4be453f
Add a new getNode() method that takes a pointer to an already-intern'd list
...
of value-type nodes. This avoids having to do mallocs for std::vectors of
valuetypes when a node returns more than one type.
llvm-svn: 29685
2006-08-14 23:31:51 +00:00
e93a39f2d7
remove SelectionDAG::InsertISelMapEntry, it is dead
...
llvm-svn: 29677
2006-08-14 22:24:39 +00:00
63268f0672
Add code to resize the CSEMap hash table. This doesn't speedup codegen of
...
kimwitu, but seems like a good idea from a "avoid performance cliffs" standpoint :)
llvm-svn: 29675
2006-08-14 22:19:25 +00:00
8e37283d8b
Add the actual constant to the hash for ConstantPool nodes. Thanks to
...
Rafael Espindola for pointing this out.
llvm-svn: 29669
2006-08-14 20:12:44 +00:00
984c1a4a8f
Emit .set directives for jump table entries when possible, which reduces
...
the number of relocations in object files, shrinkifying them.
llvm-svn: 29650
2006-08-12 21:29:52 +00:00
167ea3eb5f
Fix an obvious bug, noticed by inspection. No current targets trigger this.
...
llvm-svn: 29648
2006-08-12 05:41:39 +00:00
0a60294fa0
Switch to using SuperFastHash instead of adding all elements together. This
...
doesn't significantly improve performance but it helps a small amount.
llvm-svn: 29642
2006-08-12 01:07:10 +00:00
04aa034f38
Switch NodeID to track 32-bit chunks instead of 8-bit chunks, for a 2.5%
...
speedup in isel time.
llvm-svn: 29640
2006-08-11 23:55:53 +00:00
0c2e5412bb
Remove 8 more std::map's.
...
llvm-svn: 29631
2006-08-11 21:55:30 +00:00
3f16b201e2
Move the BBNodes, GlobalValues, TargetGlobalValues, Constants, TargetConstants,
...
RegNodes, and ValueNodes maps into the CSEMap.
llvm-svn: 29626
2006-08-11 21:01:22 +00:00
fcb16470ec
eliminate the NullaryOps map, use CSEMap instead.
...
llvm-svn: 29621
2006-08-11 18:38:11 +00:00
6f22ebd8be
change internal impl of dag combiner so that calls to CombineTo never have to
...
make a temporary vector.
llvm-svn: 29618
2006-08-11 17:56:38 +00:00
a2f4086828
Change one ReplaceAllUsesWith method to take an array of operands to replace
...
instead of a vector of operands.
llvm-svn: 29616
2006-08-11 17:46:28 +00:00
c24a1d3093
Start eliminating temporary vectors used to create DAG nodes. Instead, pass
...
in the start of an array and a count of operands where applicable. In many
cases, the number of operands is known, so this static array can be allocated
on the stack, avoiding the heap. In many other cases, a SmallVector can be
used, which has the same benefit in the common cases.
I updated a lot of code calling getNode that takes a vector, but ran out of
time. The rest of the code should be updated, and these methods should be
removed.
We should also do the same thing to eliminate the methods that take a
vector of MVT::ValueTypes.
It would be extra nice to convert the dagiselemitter to avoid creating vectors
for operands when calling getTargetNode.
llvm-svn: 29566
2006-08-08 02:23:42 +00:00
97af9d5d3a
Eliminate some malloc traffic by allocating vectors on the stack. Change some
...
method that took std::vector<SDOperand> to take a pointer to a first operand
and #operands.
This speeds up isel on kc++ by about 3%.
llvm-svn: 29561
2006-08-08 01:09:31 +00:00
1ee75ce65d
Revamp the "CSEMap" datastructure used in the SelectionDAG class. This
...
eliminates a bunch of std::map's in the SelectionDAG, replacing them with a
home-grown hashtable.
This is still a work in progress: not all the maps have been moved over and the
hashtable never resizes. That said, this still speeds up llc 20% on kimwitu++
with -fast -regalloc=local using a release build.
llvm-svn: 29550
2006-08-07 23:03:03 +00:00
445b91a041
Clear TopOrder before assigning topological order. Some clean ups.
...
llvm-svn: 29546
2006-08-07 22:13:29 +00:00
1640ae5a84
Reverse the FlaggedNodes after scanning up for flagged preds or else the order would be reversed.
...
llvm-svn: 29545
2006-08-07 22:12:12 +00:00
8927c875bb
Make SelectionDAG::RemoveDeadNodes iterative instead of recursive, which
...
also make it simpler.
llvm-svn: 29524
2006-08-04 17:45:20 +00:00
a5b707e3ad
Copy the liveins for the first block. PR859
...
llvm-svn: 29511
2006-08-03 20:51:06 +00:00
524c1a21f2
Work around a GCC 3.3.5 bug noticed by a user.
...
llvm-svn: 29490
2006-08-03 00:18:59 +00:00
6efe304ec8
Work around a bug in gcc 3.3.5, reported by a user
...
llvm-svn: 29489
2006-08-03 00:16:56 +00:00
bba1ebda32
- Change AssignTopologicalOrder to return vector of SDNode* by reference.
...
- Tweak implementation to avoid using std::map.
llvm-svn: 29479
2006-08-02 22:00:34 +00:00
29e635d3c9
Final polish on machine pass registries.
...
llvm-svn: 29471
2006-08-02 12:30:23 +00:00
17c67efe8a
Now that the ISel is available, it's possible to create a default instruction
...
scheduler creator.
llvm-svn: 29452
2006-08-01 19:14:14 +00:00
03593f72db
1. Change use of "Cache" to "Default".
...
2. Added argument to instruction scheduler creators so the creators can do
special things.
3. Repaired target hazard code.
4. Misc.
More to follow.
llvm-svn: 29450
2006-08-01 18:29:48 +00:00
0ec39ee28e
Forgot the added files for plugable machine passes.
...
llvm-svn: 29436
2006-08-01 16:31:08 +00:00
95eda5b1f3
Introducing plugable register allocators and instruction schedulers.
...
llvm-svn: 29434
2006-08-01 14:21:23 +00:00
9631a60020
Added AssignTopologicalOrder() to assign each node an unique id based on their topological order.
...
llvm-svn: 29431
2006-08-01 08:20:41 +00:00
6ae6ac1216
PIC jump table entries are always 32-bit even in 64-bit mode.
...
llvm-svn: 29422
2006-08-01 01:03:13 +00:00
85492427f2
Instead of blindly looking past constantexpr casts, actually constant
...
fold them. This correctly truncates constants that are too large for the
destination slot and makes the code easier to understand. This fixes PR853
and Regression/CodeGen/X86/2006-07-28-AsmPrint-Long-As-Pointer.ll
llvm-svn: 29408
2006-07-29 01:57:19 +00:00
b572401bea
Remove InFlightSet hack. No longer needed.
...
llvm-svn: 29373
2006-07-28 00:47:19 +00:00
3390cbed2c
Print empty inline asms as a blank line instead of:
...
# InlineAsm Start
# InlineAsm End
llvm-svn: 29372
2006-07-28 00:17:20 +00:00
d1a714e503
Working toward registration of register allocators.
...
llvm-svn: 29360
2006-07-27 20:05:00 +00:00
efc312a5c7
Code cleanups, per review
...
llvm-svn: 29347
2006-07-27 16:46:58 +00:00
acb606ff33
AssignNodeIds should return unsigned.
...
llvm-svn: 29343
2006-07-27 07:36:47 +00:00
29eefc164c
AssignNodeIds assign each node in the DAG an unique id.
...
llvm-svn: 29337
2006-07-27 06:39:06 +00:00
85ea83e821
Add some advice
...
llvm-svn: 29324
2006-07-27 04:24:14 +00:00
787565024a
Support jump tables when in PIC relocation model
...
llvm-svn: 29318
2006-07-27 01:13:04 +00:00
4488f0c303
Fix a case where LegalizeAllNodesNotLeadingTo could take exponential time.
...
This manifested itself as really long time to compile
Regression/CodeGen/Generic/2003-05-28-ManyArgs.ll on ppc.
This is PR847.
llvm-svn: 29313
2006-07-26 23:55:56 +00:00
421475cd3b
For PR780:
...
1. Move IncludeFile.h to System library
2. Move IncludeFile.cpp to System library
3. #1 and #2 required to prevent cyclic library dependencies for libSystem
4. Convert all existing uses of Support/IncludeFile.h to System/IncludeFile.h
5. Add IncludeFile support to various lib/System classes.
6. Add new lib/System classes to LinkAllVMCore.h
All this in an attempt to pull in lib/System to what's required for VMCore
llvm-svn: 29287
2006-07-26 16:18:00 +00:00
658b9476f0
Initialize some variables the compiler warns about.
...
llvm-svn: 29277
2006-07-25 20:44:41 +00:00
4b49c23571
Eliminate data relocations by using NULL instead of global empty list.
...
llvm-svn: 29250
2006-07-21 21:15:20 +00:00
4e153f1b91
Use an enumeration to eliminate data relocations.
...
llvm-svn: 29249
2006-07-21 20:57:35 +00:00
7c970b98d0
If a shuffle is a splat, check if the argument is a build_vector with all elements being the same. If so, return the argument.
...
llvm-svn: 29242
2006-07-21 08:25:53 +00:00
55782c6c41
Build more debugger/selectiondag libraries as archives instead of .o files.
...
This works around bugs in some versions of the cygwin linker.
Patch contributed by Anton Korobeynikov.
llvm-svn: 29239
2006-07-21 00:10:47 +00:00
8472e0c4af
If a shuffle is unary, i.e. one of the vector argument is not needed, turn the
...
operand into a undef and adjust mask accordingly.
llvm-svn: 29232
2006-07-20 22:44:41 +00:00
b030532910
Mems can be in the output list also. This is the second half of a fix for
...
PR833
llvm-svn: 29224
2006-07-20 19:02:21 +00:00
ec104a2b41
80 cols
...
llvm-svn: 29221
2006-07-20 17:43:27 +00:00
c496b418b5
Reduce number of exported symbols
...
llvm-svn: 29220
2006-07-20 17:28:38 +00:00
2b0baddc33
Fix linking on Alpha
...
llvm-svn: 29219
2006-07-20 17:27:58 +00:00
4238ca55ef
Move MVT::getVectorType out of line, it is large and shouldn't be inlined.
...
llvm-svn: 29195
2006-07-19 00:40:45 +00:00
c0973edc69
Add an out-of-line virtual method for the sdnode class to give it a home.
...
llvm-svn: 29192
2006-07-19 00:00:37 +00:00
fd5a8ebb74
On 64-bit targets like ppc64, we should use .quad to output pointer directives,
...
not .long.
llvm-svn: 29157
2006-07-15 01:34:12 +00:00
436c2dd927
Add an out-of-line virtual function to home class.
...
llvm-svn: 29154
2006-07-14 23:08:47 +00:00
194bef7ff4
Fixed a bug handling void function types.
...
Requires rebuild of llvm-gcc4 (touch llvm-debug.cpp.)
llvm-svn: 29131
2006-07-13 15:27:42 +00:00
f7300b2706
It was pointed out that DEBUG() is only available with -debug.
...
llvm-svn: 29106
2006-07-11 18:25:13 +00:00
c3d341ea98
Ensure that dump calls that are associated with asserts are removed from
...
non-debug build.
llvm-svn: 29105
2006-07-11 17:58:07 +00:00
6c72aa7411
1. Support for c++ mangled names.
...
2. Support for private/protected class members.
llvm-svn: 29104
2006-07-11 15:58:09 +00:00
1b8ea1f5ba
Fix CodeGen/Alpha/2006-07-03-ASMFormalLowering.ll and PR818.
...
llvm-svn: 29099
2006-07-11 01:40:09 +00:00
d19938834b
Ugly hack! Add helper functions InsertInFlightSetEntry and
...
RemoveInFlightSetEntry. They are used in place of direct set operators to
reduce instruction selection function stack size.
llvm-svn: 28987
2006-06-29 23:57:05 +00:00
ec1d60bd98
Add support to print 4-, 8-, and 16- byte constant literals in special
...
sections. e.g. On Darwin that would be .literal4 and .literal8.
llvm-svn: 28977
2006-06-29 00:26:09 +00:00
996795b0dd
Use hidden visibility to make symbols in an anonymous namespace get
...
dropped. This shrinks libllvmgcc.dylib another 67K
llvm-svn: 28975
2006-06-28 23:17:24 +00:00
e097e6f7c7
Shave another 27K off libllvmgcc.dylib with visibility hidden
...
llvm-svn: 28973
2006-06-28 22:17:39 +00:00
54a34cd20b
Mark these two classes as hidden, shrinking libllbmgcc.dylib by 25K
...
llvm-svn: 28970
2006-06-28 21:58:30 +00:00
710b3d5ea1
Fix CodeGen/Generic/2006-06-28-SimplifySetCCCrash.ll
...
llvm-svn: 28965
2006-06-28 18:29:47 +00:00
ee7eaa25cf
For PR801:
...
Refactor the Graph writing code to use a common implementation which is
now in lib/Support/GraphWriter.cpp. This completes the PR.
Patch by Anton Korobeynikov. Thanks, Anton!
llvm-svn: 28925
2006-06-27 16:49:46 +00:00
a7b2bd5997
Add and sort "sections" in debug lines. This always stepping through
...
code in sections other than ".text", including weak sections like ctors and
dtors.
llvm-svn: 28909
2006-06-23 12:51:53 +00:00
0a9e837b6f
Add support for function types.
...
llvm-svn: 28874
2006-06-20 19:41:06 +00:00
2837e3204f
References need to be section relative.
...
llvm-svn: 28861
2006-06-19 19:49:42 +00:00
f32058a2b7
References need to be section relative.
...
llvm-svn: 28858
2006-06-19 15:48:00 +00:00
90cd68acc6
Handle versioning of compile unit.
...
llvm-svn: 28855
2006-06-19 12:54:15 +00:00
b2ff2d481e
1. Revise vector debug support.
...
2. Update docs for vector debug support and new version control.
3. Simplify serialization of DebugDescInfo subclasses.
llvm-svn: 28816
2006-06-16 13:14:03 +00:00
4ff6c1646f
Teach the local allocator to know that live-in values (e.g. arguments) are
...
live at function entry. This prevents it from using arg registers for other
purposes before the arguments are used.
llvm-svn: 28809
2006-06-15 22:21:53 +00:00
19f964e048
1. Support standard dwarf format (was bootstrapping in Apple format.)
...
2. Add vector support.
llvm-svn: 28807
2006-06-15 20:51:43 +00:00
3519b87758
Was pointed out that structure alignment and type alignment are not the same
...
thing. Doubles still need to be special cased.
llvm-svn: 28806
2006-06-15 19:37:14 +00:00
dce07568f2
Alignment of globals has not been quite right. Needed to drop the pointer type
...
to get the alignment of the element type.
llvm-svn: 28799
2006-06-15 13:10:58 +00:00
ef9e07d3f0
Consistency. EXTRACT_ELEMENT index operand should have ptr type.
...
llvm-svn: 28795
2006-06-15 08:11:54 +00:00
df63179d95
Assert. Rather than silently stop printing.
...
llvm-svn: 28794
2006-06-15 08:10:56 +00:00
55772ccfd6
Instructions with variable operands (variable_ops) can have a number required
...
operands. e.g.
def CALL32r : I<0xFF, MRM2r, (ops GR32:$dst, variable_ops),
"call {*}$dst", [(X86call GR32:$dst)]>;
TableGen should emit operand informations for the "required" operands.
Added a target instruction info flag M_VARIABLE_OPS to indicate the target
instruction may have more operands in addition to the minimum required
operands.
llvm-svn: 28791
2006-06-15 07:22:16 +00:00
f0a7a1a117
Change versioning to per debug info descriptor (merged with tag.)
...
llvm-svn: 28782
2006-06-14 14:45:39 +00:00
f67bec0579
Place dwarf headers at earliest possible point. Well behaved when skipping
...
functions.
llvm-svn: 28781
2006-06-14 11:35:03 +00:00
32d92e004d
Make sure to update the CFG correctly if a switch only has a default dest.
...
This fixes CodeGen/Generic/2006-06-12-LowerSwitchCrash.ll
llvm-svn: 28755
2006-06-12 18:25:29 +00:00
0e57b2cb92
Start on my todo list
...
llvm-svn: 28752
2006-06-12 16:07:18 +00:00
c03a9259c0
Fix X86/inline-asm.ll:test2, a case where an input value was implicitly
...
truncated.
llvm-svn: 28733
2006-06-08 18:27:11 +00:00
705948d742
Fix Regression/CodeGen/X86/inline-asm.ll, a case where inline asm causes
...
implement extension of a register.
llvm-svn: 28731
2006-06-08 18:22:48 +00:00
8f8b5e4631
Fix an assert-on-inline-inline-asm bug.
...
llvm-svn: 28727
2006-06-08 18:00:47 +00:00
614cb2ff82
For PR798:
...
Provide GraphViz support for MingW32. Patch provided by Anton Korobeynikov
llvm-svn: 28688
2006-06-05 16:26:06 +00:00
7c77323e1d
For PR798:
...
Add support for Graphviz. Patch contributed by Anton Korobeynikov.
llvm-svn: 28684
2006-06-05 15:44:46 +00:00
cd8f67a106
Prevent the -pedantic option from causing Mac OS/X build problems:
...
LiveIntervalAnalysis.cpp:218: error: floating constant exceeds range of 'double'
llvm-svn: 28620
2006-06-01 06:12:21 +00:00
a647c7ff42
Use archive libraries instead of object files for VMCore, BCReader,
...
BCWriter, and bzip2 libraries. Adjust the various makefiles to accommodate
these changes. This was done to speed up link times.
llvm-svn: 28610
2006-06-01 01:30:27 +00:00
0c0996a97b
commuteInstruction() does not always create a new MI!
...
llvm-svn: 28592
2006-05-31 18:03:39 +00:00
9d91caa053
Eliminate a memory leak.
...
llvm-svn: 28585
2006-05-31 07:13:03 +00:00
64d2846017
visitVBinOp: Can't fold divide by zero!
...
llvm-svn: 28584
2006-05-31 06:08:35 +00:00
d12c97d23a
Make sure the register pressure reduction schedulers work for non-uniform
...
latency targets, e.g. PPC32.
llvm-svn: 28561
2006-05-30 18:05:39 +00:00
61e9f0d680
When a priority_queue is empty, the behavior of top() operator is
...
non-deterministic. Returns NULL when it's empty!
llvm-svn: 28560
2006-05-30 18:04:34 +00:00
8f872d2091
Fix a nasty dag combiner bug that caused nondeterminstic crashes (MY FAVORITE!):
...
SimplifySelectOps would eliminate a Select, delete it, then return true.
The clients would see that it did something and return null.
The top level would see a null return, and decide that nothing happened,
proceeding to process the node in other ways: boom.
The fix is simple: clients of SimplifySelectOps should return the select
node itself.
In order to catch really obnoxious boogs like this in the future, add an
assert that nodes are not deleted. We do this by checking for a sentry node
type that the SDNode dtor sets when a node is destroyed.
llvm-svn: 28514
2006-05-27 00:43:02 +00:00
21dee4e0b2
Make CALL node consistent with RET node. Signness of value has type MVT::i32
...
instead of MVT::i1. Either is fine except MVT::i32 is probably a legal type
for most (if not all) platforms while MVT::i1 is not.
llvm-svn: 28511
2006-05-26 23:13:20 +00:00
a2e9953c54
Change RET node to include signness information of the return values. e.g.
...
RET chain, value1, sign1, value2, sign2
llvm-svn: 28509
2006-05-26 23:09:09 +00:00
0f5c7936e7
Remove a bogus cast.
...
llvm-svn: 28492
2006-05-26 08:00:14 +00:00
009f5f55f7
Turn on -sched-commute-nodes by default.
...
llvm-svn: 28465
2006-05-25 08:37:31 +00:00
4582771f3f
CALL node change: now including signness of every argument.
...
llvm-svn: 28461
2006-05-25 00:55:32 +00:00
aa2372562e
Patches to make the LLVM sources more -pedantic clean. Patch provided
...
by Anton Korobeynikov! This is a step towards closing PR786.
llvm-svn: 28447
2006-05-24 17:04:05 +00:00
ac4f66ff24
-enable-unsafe-fp-math implies -enable-finite-only-fp-math
...
llvm-svn: 28437
2006-05-23 18:18:46 +00:00
df1d439849
Fix missing include
...
llvm-svn: 28435
2006-05-23 13:43:15 +00:00
1c5b7d12df
Incorrect SETCC CondCode used for FP comparisons.
...
llvm-svn: 28433
2006-05-23 06:40:47 +00:00
d8e2f6ebc1
lib/Target/Target.td
...
llvm-svn: 28386
2006-05-18 20:42:07 +00:00
7949c2e8b2
Fix the result of the call to use a correct vbitconvert. There is no need to
...
use getPackedTypeBreakdown at all here.
llvm-svn: 28365
2006-05-17 20:49:36 +00:00
938155ca57
Correct a previous patch which broke CodeGen/PowerPC/vec_call.ll
...
llvm-svn: 28364
2006-05-17 20:43:21 +00:00
751cd7653d
Fixed a LowerCallTo and LowerArguments bug. They were introducing illegal
...
VBIT_VECTOR nodes. There were some confusion about the semantics of
getPackedTypeBreakdown(). e.g. for <4 x f32> it returns 1 and v4f32, not 4,
and f32.
llvm-svn: 28352
2006-05-17 18:16:39 +00:00
62f1b83c0e
When we legalize target nodes, do not use getNode to create a new node,
...
use UpdateNodeOperands to just update the operands! This is important because
getNode will allocate a new node if the node returns a flag and this breaks
assumptions in the legalizer that you can legalize some things multiple times
and get exactly the same results.
This latent bug was exposed by my ppc patch last night, and this fixes
gsm/toast.
llvm-svn: 28348
2006-05-17 18:00:08 +00:00
a1cec0106a
Add an assertion, avoid some unneeded work for each call. No functionality
...
change.
llvm-svn: 28347
2006-05-17 17:55:45 +00:00
b77ba73a29
Add support for calls that pass and return legal vectors.
...
llvm-svn: 28340
2006-05-16 23:39:44 +00:00
aaa23d953f
Add a new ISD::CALL node, make the default impl of TargetLowering::LowerCallTo
...
produce it.
llvm-svn: 28338
2006-05-16 22:53:20 +00:00
1dc9ec5874
Move this code to a common place
...
llvm-svn: 28329
2006-05-16 17:42:15 +00:00
3d82699605
Add a chain to FORMAL_ARGUMENTS. This is a minimal port of the X86 backend,
...
it doesn't currently use/maintain the chain properly. Also, make the
X86ISelLowering.cpp file 80-col clean.
llvm-svn: 28320
2006-05-16 06:45:34 +00:00
957cb6733a
Move function-live-in-handling code from the sdisel code to the scheduler.
...
This code should be emitted after legalize, so it can't be in sdisel.
Note that the EmitFunctionEntryCode hook should be updated to operate on the
DAG. The X86 backend is the only one currently using this hook.
llvm-svn: 28315
2006-05-16 06:10:58 +00:00
52d0c78de8
Print the vreg that livein physregs are live in
...
llvm-svn: 28314
2006-05-16 05:55:30 +00:00
5f0edfb849
Legalize FORMAL_ARGUMENTS nodes correctly, we don't want to legalize them once
...
for each argument.
llvm-svn: 28313
2006-05-16 05:49:56 +00:00
99f2f79e2f
Fixing 2006-05-01-SchedCausingSpills.ll; some clean up
...
llvm-svn: 28279
2006-05-13 08:22:24 +00:00
d1915cfa6f
Revert an un-intended change
...
llvm-svn: 28278
2006-05-13 05:53:47 +00:00
69a0ce6261
Merge identical code.
...
llvm-svn: 28274
2006-05-13 02:11:14 +00:00
a726fc6dbf
If the register allocator cannot find a register to spill, try the aliases. If
...
that still fails (because all the register spill weights are inf), just grab
one.
llvm-svn: 28262
2006-05-12 19:07:46 +00:00
53cdb2f2b0
Remove dead vars
...
llvm-svn: 28255
2006-05-12 18:06:45 +00:00
da076e41ab
remove dead vars
...
llvm-svn: 28254
2006-05-12 18:04:28 +00:00
fe211deedf
Remove dead variable
...
llvm-svn: 28253
2006-05-12 18:02:04 +00:00
afe72481f6
Comment out dead variables
...
llvm-svn: 28252
2006-05-12 17:57:54 +00:00
936cd3390d
Remove dead var
...
llvm-svn: 28250
2006-05-12 17:50:35 +00:00
8c02c3f41a
Compile:
...
%tmp152 = setgt uint %tmp144, %tmp149 ; <bool> [#uses=1]
%tmp159 = setlt uint %tmp144, %tmp149 ; <bool> [#uses=1]
%bothcond2 = or bool %tmp152, %tmp159 ; <bool> [#uses=1]
To setne, not setune, which causes an assertion fault.
llvm-svn: 28244
2006-05-12 17:03:46 +00:00
8c2c1e90c4
Refactor a bunch of includes so that TargetMachine.h doesn't have to include
...
TargetData.h. This should make recompiles a bit faster with my current
TargetData tinkering.
llvm-svn: 28238
2006-05-12 06:33:49 +00:00
6a6886185b
Backing out fix for PR770. Need to re-apply it after live range splitting is possible
...
llvm-svn: 28236
2006-05-12 06:06:34 +00:00
095c9d9b7f
Duh. That could take a long time.
...
llvm-svn: 28235
2006-05-12 06:05:18 +00:00
66adee93aa
Two simplifications for token factor nodes: simplify tf(x,x) -> x.
...
simplify tf(x,y,y,z) -> tf(x,y,z).
llvm-svn: 28233
2006-05-12 05:01:37 +00:00
afed73eebe
Add capability to scheduler to commute nodes for profit.
...
If a two-address code whose first operand has uses below, it should be commuted
when possible.
llvm-svn: 28230
2006-05-12 01:58:24 +00:00
d38c22bdd3
Refactor scheduler code. Move register-reduction list scheduler to a
...
separate file. Added an initial implementation of top-down register pressure
reduction list scheduler.
llvm-svn: 28226
2006-05-11 23:55:42 +00:00
47926aff96
Set weight of zero length intervals to infinite to prevent them from being
...
spilled.
llvm-svn: 28220
2006-05-11 07:29:24 +00:00
db6aa4896b
Backing out previous check-in.
...
llvm-svn: 28219
2006-05-11 07:28:16 +00:00
6ad040a6bc
If the live interval legnth is essentially zero, i.e. in every live range
...
the use follows def immediately, it doesn't make sense to spill it and
hope it will be easier to allocate for this LI.
llvm-svn: 28217
2006-05-10 22:30:41 +00:00
9665ba053f
Templatify RegReductionPriorityQueue
...
llvm-svn: 28212
2006-05-10 06:16:44 +00:00
1a225d23ae
Fix PR773
...
llvm-svn: 28207
2006-05-09 18:20:51 +00:00
f801792e08
Fix a regression in my patch from last night that broke the llvmgcc4 build on
...
ppc
llvm-svn: 28205
2006-05-09 16:41:59 +00:00
7d693898ee
Add pseudo dependency to force a def&use operand to be scheduled last (unless
...
the distance between the def and another use is much longer). This is under
option control for now "-sched-lower-defnuse".
llvm-svn: 28201
2006-05-09 07:13:34 +00:00
2c74848af1
Debugging info
...
llvm-svn: 28200
2006-05-09 06:55:15 +00:00
ae45020720
PR 770 - permit coallescing of registers in subset register classes.
...
llvm-svn: 28197
2006-05-09 06:37:48 +00:00
4ebc6a2311
Implement MASM sections correctly, without a "has masm sections flag" and a bunch of special case code.
...
llvm-svn: 28194
2006-05-09 05:33:48 +00:00
8c2bfc0659
Oh yeah, there are two of these now, unify both.
...
llvm-svn: 28192
2006-05-09 05:24:50 +00:00
6341df8069
Setting SwitchToSectionDirective properly in the MASM backend permits a bunch
...
of code to be unified.
llvm-svn: 28191
2006-05-09 05:23:12 +00:00
d36cc2b610
Don't prefix section directives with a tab. Doing so causes blank lines to
...
be emitted to the .s file.
llvm-svn: 28189
2006-05-09 05:19:59 +00:00
e64f764d25
Make the masm codepath work like the normal code path.
...
llvm-svn: 28188
2006-05-09 05:15:58 +00:00
c0f0dfa56f
The MASM asmprinter has been fixed, these hacks are no longer needed.
...
llvm-svn: 28186
2006-05-09 05:13:34 +00:00
8488ba2e41
Split SwitchSection into SwitchTo{Text|Data}Section methods.
...
llvm-svn: 28184
2006-05-09 04:59:56 +00:00
446e1ef26a
Make the case I just checked in stronger. Now we compile this:
...
short test2(short X, short x) {
int Y = (short)(X+x);
return Y >> 1;
}
to:
_test2:
add r2, r3, r4
extsh r2, r2
srawi r3, r2, 1
blr
instead of:
_test2:
add r2, r3, r4
extsh r2, r2
srwi r2, r2, 1
extsh r3, r2
blr
llvm-svn: 28175
2006-05-08 21:18:59 +00:00
29062da0ac
Implement and_sext.ll:test3, generating:
...
_test4:
srawi r3, r3, 16
blr
instead of:
_test4:
srwi r2, r3, 16
extsh r3, r2
blr
for:
short test4(unsigned X) {
return (X >> 16);
}
llvm-svn: 28174
2006-05-08 20:59:41 +00:00
2935d8190c
Compile this:
...
short test4(unsigned X) {
return (X >> 16);
}
to:
_test4:
movl 4(%esp), %eax
sarl $16, %eax
ret
instead of:
_test4:
movl $-65536, %eax
andl 4(%esp), %eax
sarl $16, %eax
ret
llvm-svn: 28171
2006-05-08 20:51:54 +00:00
78da6792e7
Fold shifts with undef operands.
...
llvm-svn: 28167
2006-05-08 17:29:49 +00:00
d7a19102d1
Make emission of jump tables a bit less conservative; they are now required
...
to be only 31.25% dense, rather than 75% dense.
llvm-svn: 28165
2006-05-08 16:51:36 +00:00
e5ce5bb6da
Fix PR772
...
llvm-svn: 28161
2006-05-08 01:35:01 +00:00
7e7bcf3a54
Simplify some code, add a couple minor missed folds
...
llvm-svn: 28152
2006-05-06 23:06:26 +00:00
751817c54f
constant fold sign_extend_inreg
...
llvm-svn: 28151
2006-05-06 23:05:41 +00:00
2a4d7b845b
remove cases handled elsewhere
...
llvm-svn: 28150
2006-05-06 22:43:44 +00:00
ce9b9fe6eb
Fix some loose ends in MASM support.
...
llvm-svn: 28148
2006-05-06 21:27:14 +00:00
1ecb2a2dac
Use the new TargetLowering::ComputeNumSignBits method to eliminate
...
sign_extend_inreg operations. Though ComputeNumSignBits is still rudimentary,
this is enough to compile this:
short test(short X, short x) {
int Y = X+x;
return (Y >> 1);
}
short test2(short X, short x) {
int Y = (short)(X+x);
return Y >> 1;
}
into:
_test:
add r2, r3, r4
srawi r3, r2, 1
blr
_test2:
add r2, r3, r4
extsh r2, r2
srawi r3, r2, 1
blr
instead of:
_test:
add r2, r3, r4
srawi r2, r2, 1
extsh r3, r2
blr
_test2:
add r2, r3, r4
extsh r2, r2
srawi r2, r2, 1
extsh r3, r2
blr
llvm-svn: 28146
2006-05-06 09:30:03 +00:00
21cd99024a
When inserting casts, be careful of where we put them. We cannot insert
...
a cast immediately before a PHI node.
This fixes Regression/CodeGen/Generic/2006-05-06-GEP-Cast-Sink-Crash.ll
llvm-svn: 28143
2006-05-06 09:10:37 +00:00
907e392dba
Fold trunc(any_ext). This gives stuff like:
...
27,28c27
< movzwl %di, %edi
< movl %edi, %ebx
---
> movw %di, %bx
llvm-svn: 28137
2006-05-05 22:56:26 +00:00
57f8c5a387
Shrink shifts when possible.
...
llvm-svn: 28136
2006-05-05 22:53:17 +00:00
a633c31319
Indent multiline asm strings more nicely
...
llvm-svn: 28132
2006-05-05 21:47:05 +00:00
3d26577396
Fold (fpext (load x)) -> (extload x)
...
llvm-svn: 28130
2006-05-05 21:34:35 +00:00
3e3f2c63c3
More aggressively sink GEP offsets into loops. For example, before we
...
generated:
movl 8(%esp), %eax
movl %eax, %edx
addl $4316, %edx
cmpb $1, %cl
ja LBB1_2 #cond_false
LBB1_1: #cond_true
movl L_QuantizationTables720$non_lazy_ptr, %ecx
movl %ecx, (%edx)
movl L_QNOtoQuantTableShift720$non_lazy_ptr, %edx
movl %edx, 4460(%eax)
ret
...
Now we generate:
movl 8(%esp), %eax
cmpb $1, %cl
ja LBB1_2 #cond_false
LBB1_1: #cond_true
movl L_QuantizationTables720$non_lazy_ptr, %ecx
movl %ecx, 4316(%eax)
movl L_QNOtoQuantTableShift720$non_lazy_ptr, %ecx
movl %ecx, 4460(%eax)
ret
... which uses one fewer register.
llvm-svn: 28129
2006-05-05 21:17:49 +00:00
25a5283a86
Fold some common code.
...
llvm-svn: 28124
2006-05-05 06:32:04 +00:00
002ee91457
Implement:
...
// fold (and (sext x), (sext y)) -> (sext (and x, y))
// fold (or (sext x), (sext y)) -> (sext (or x, y))
// fold (xor (sext x), (sext y)) -> (sext (xor x, y))
// fold (and (aext x), (aext y)) -> (aext (and x, y))
// fold (or (aext x), (aext y)) -> (aext (or x, y))
// fold (xor (aext x), (aext y)) -> (aext (xor x, y))
llvm-svn: 28123
2006-05-05 06:31:05 +00:00
5ac4293606
Pull and through and/or/xor. This compiles some bitfield code to:
...
mov EAX, DWORD PTR [ESP + 4]
mov ECX, DWORD PTR [EAX]
mov EDX, ECX
add EDX, EDX
or EDX, ECX
and EDX, -2147483648
and ECX, 2147483647
or EDX, ECX
mov DWORD PTR [EAX], EDX
ret
instead of:
sub ESP, 4
mov DWORD PTR [ESP], ESI
mov EAX, DWORD PTR [ESP + 8]
mov ECX, DWORD PTR [EAX]
mov EDX, ECX
add EDX, EDX
mov ESI, ECX
and ESI, -2147483648
and EDX, -2147483648
or EDX, ESI
and ECX, 2147483647
or EDX, ECX
mov DWORD PTR [EAX], EDX
mov ESI, DWORD PTR [ESP]
add ESP, 4
ret
llvm-svn: 28122
2006-05-05 06:10:43 +00:00
812646aa0c
Implement a variety of simplifications for ANY_EXTEND.
...
llvm-svn: 28121
2006-05-05 05:58:59 +00:00
8d6fc20181
Factor some code, add these transformations:
...
// fold (and (trunc x), (trunc y)) -> (trunc (and x, y))
// fold (or (trunc x), (trunc y)) -> (trunc (or x, y))
// fold (xor (trunc x), (trunc y)) -> (trunc (xor x, y))
llvm-svn: 28120
2006-05-05 05:51:50 +00:00
78a7f0e05e
Fix VC++ compilation error.
...
llvm-svn: 28117
2006-05-05 01:47:05 +00:00
7a3ecf7993
Sink noop copies into the basic block that uses them. This reduces the number
...
of cross-block live ranges, and allows the bb-at-a-time selector to always
coallesce these away, at isel time.
This reduces the load on the coallescer and register allocator. For example
on a codec on X86, we went from:
1643 asm-printer - Number of machine instrs printed
419 liveintervals - Number of loads/stores folded into instructions
1144 liveintervals - Number of identity moves eliminated after coalescing
1022 liveintervals - Number of interval joins performed
282 liveintervals - Number of intervals after coalescing
1304 liveintervals - Number of original intervals
86 regalloc - Number of times we had to backtrack
1.90232 regalloc - Ratio of intervals processed over total intervals
40 spiller - Number of values reused
182 spiller - Number of loads added
121 spiller - Number of stores added
132 spiller - Number of register spills
6 twoaddressinstruction - Number of instructions commuted to coalesce
360 twoaddressinstruction - Number of two-address instructions
to:
1636 asm-printer - Number of machine instrs printed
403 liveintervals - Number of loads/stores folded into instructions
1155 liveintervals - Number of identity moves eliminated after coalescing
1033 liveintervals - Number of interval joins performed
279 liveintervals - Number of intervals after coalescing
1312 liveintervals - Number of original intervals
76 regalloc - Number of times we had to backtrack
1.88998 regalloc - Ratio of intervals processed over total intervals
1 spiller - Number of copies elided
41 spiller - Number of values reused
191 spiller - Number of loads added
114 spiller - Number of stores added
128 spiller - Number of register spills
4 twoaddressinstruction - Number of instructions commuted to coalesce
356 twoaddressinstruction - Number of two-address instructions
On this testcase, this change provides a modest reduction in spill code,
regalloc iterations, and total instructions emitted. It increases the number
of register coallesces.
llvm-svn: 28115
2006-05-05 01:04:50 +00:00
abdf4d569c
Final pass of minor cleanups for MachineInstr
...
llvm-svn: 28110
2006-05-04 19:36:09 +00:00
9add880566
Initial support for register pressure aware scheduling. The register reduction
...
scheduler can go into a "vertical mode" (i.e. traversing up the two-address
chain, etc.) when the register pressure is low.
This does seem to reduce the number of spills in the cases I've looked at. But
with x86, it's no guarantee the performance of the code improves.
It can be turned on with -sched-vertically option.
llvm-svn: 28108
2006-05-04 19:16:39 +00:00
53af9da363
Remove redundancy and a level of indirection when creating machine operands
...
llvm-svn: 28107
2006-05-04 19:14:44 +00:00
469647bf38
Remove and simplify some more machineinstr/machineoperand stuff.
...
llvm-svn: 28105
2006-05-04 18:16:01 +00:00
10b71c0d08
Rename MO_VirtualRegister -> MO_Register. Clean up immediate handling.
...
llvm-svn: 28104
2006-05-04 18:05:43 +00:00
10d6341618
Move some methods out of MachineInstr into MachineOperand
...
llvm-svn: 28102
2006-05-04 17:52:23 +00:00
fef7a2d0f5
There shalt be only one "immediate" operand type!
...
llvm-svn: 28099
2006-05-04 17:21:20 +00:00
15c52bda1d
Change "value" in MachineOperand to be a GlobalValue, as that is the only
...
thing that can be in it. Remove a dead method.
llvm-svn: 28098
2006-05-04 17:02:51 +00:00
ee64b6b40f
Remove a bunch more dead V9 specific stuff
...
llvm-svn: 28094
2006-05-04 01:26:39 +00:00
940cc978ef
Remove a bunch more SparcV9 specific stuff
...
llvm-svn: 28093
2006-05-04 01:15:02 +00:00
6e663f1c1e
Remove some more V9-specific stuff.
...
llvm-svn: 28092
2006-05-04 00:49:59 +00:00
9f6639b64d
Remove some more unused stuff from MachineInstr that was leftover from V9.
...
llvm-svn: 28091
2006-05-04 00:44:25 +00:00
1d8ee1fc80
Suck block address tracking out of targets into the JIT Emitter. This
...
simplifies the MachineCodeEmitter interface just a little bit and makes
BasicBlocks work like constant pools and jump tables.
llvm-svn: 28082
2006-05-03 17:10:41 +00:00
df4883971e
Finish up the initial jump table implementation by allowing jump tables to
...
not be 100% dense. Increase the minimum threshold for the number of cases
in a switch statement from 4 to 6 in order to create a jump table.
llvm-svn: 28079
2006-05-03 03:48:02 +00:00
ffef8b9412
Bottom up register pressure reduction work: clean up some hacks and enhanced
...
the heuristic to further reduce spills for several test cases. (Note, it may
not necessarily translate to runtime win!)
llvm-svn: 28076
2006-05-03 02:10:45 +00:00
20a631fde7
Refactor TargetMachine, pushing handling of TargetData into the target-specific subclasses. This has one caller-visible change: getTargetData() now returns a pointer instead of a reference.
...
This fixes PR 759.
llvm-svn: 28074
2006-05-03 01:29:57 +00:00
d8b192ba3b
Change the BasicBlockAddrs map to be a vector, indexed by MBB number.
...
llvm-svn: 28069
2006-05-03 00:32:55 +00:00
b8065a9a3a
Several related changes:
...
1. Change several methods in the MachineCodeEmitter class to be pure virtual.
2. Suck emitConstantPool/initJumpTableInfo into startFunction, removing them
from the MachineCodeEmitter interface, and reducing the amount of target-
specific code.
3. Change the JITEmitter so that it allocates constantpools and jump tables
*right* next to the functions that they belong to, instead of in a separate
pool of memory. This makes all memory for a function be contiguous, and
means the JITEmitter only tracks one block of memory now.
llvm-svn: 28065
2006-05-02 23:22:24 +00:00
23621fe8f4
Do not make the JIT memory manager manage the memory for globals. Instead
...
just have the JIT malloc them.
llvm-svn: 28062
2006-05-02 21:57:51 +00:00
c9aa3715e8
Refactor the machine code emitter interface to pull the pointers for the current
...
code emission location into the base class, instead of being in the derived classes.
This change means that low-level methods like emitByte/emitWord now are no longer
virtual (yaay for speed), and we now have a framework to support growable code
segments. This implements feature request #1 of PR469.
llvm-svn: 28059
2006-05-02 18:27:26 +00:00
4971ba5f41
Print function number instead of name
...
llvm-svn: 28057
2006-05-02 17:36:46 +00:00
67a3aa2aaa
Remove dead method
...
llvm-svn: 28055
2006-05-02 17:20:28 +00:00
bb1c345ec6
Remove the debug machine code emitter. The "FilePrinterEmitter" is more
...
useful for debugging.
llvm-svn: 28051
2006-05-02 16:59:24 +00:00
b9d4f8324d
Extend printBasicBlockLabel a bit so that it can be used to print all
...
basic block labels, consolidating the code to do so in one place for each
target.
llvm-svn: 28050
2006-05-02 05:37:32 +00:00
470f431f44
De-virtualize SwitchSection.
...
llvm-svn: 28047
2006-05-02 03:58:45 +00:00
f34ddb1e0d
De-virtualize EmitZeroes.
...
llvm-svn: 28046
2006-05-02 03:46:13 +00:00
24a62a9bc1
Make Intel syntax mode friendlier to Microsoft ML assembler (still needs more work).
...
llvm-svn: 28044
2006-05-02 01:16:28 +00:00
fd0a5478a1
Fix a latent bug that my spiller patch last week exposed: we were leaving
...
instructions in the virtregfolded map that were deleted. Because they
were deleted, newly allocated instructions could end up at the same address,
magically finding themselves in the map. The solution is to remove entries
from the map when we delete the instructions.
llvm-svn: 28041
2006-05-01 22:03:24 +00:00
ab7dbe0cc9
When promoting a load to a reg-reg copy, where the load was a previous
...
instruction folded with spill code, make sure the remove the load from
the virt reg folded map.
llvm-svn: 28040
2006-05-01 21:17:10 +00:00
4dee67c2cd
Remove previous patch, which wasn't quite right.
...
llvm-svn: 28039
2006-05-01 21:16:03 +00:00
0d084fb9ca
Dis-favor stores more
...
llvm-svn: 28035
2006-05-01 09:20:44 +00:00
24e795496d
Bottom up register-pressure reduction scheduler now pushes store operations
...
up the schedule. This helps code that looks like this:
loads ...
computations (first set) ...
stores (first set) ...
loads
computations (seccond set) ...
stores (seccond set) ...
Without this change, the stores and computations are more likely to
interleave:
loads ...
loads ...
computations (first set) ...
computations (second set) ...
computations (first set) ...
stores (first set) ...
computations (second set) ...
stores (stores set) ...
This can increase the number of spills if we are unlucky.
llvm-svn: 28033
2006-05-01 09:14:40 +00:00
10ff7b27ce
Didn't mean ScheduleDAGList.cpp to make the last checkin.
...
llvm-svn: 28030
2006-05-01 08:56:34 +00:00
a656242690
Remove temp. option -spiller-check-liveout, it didn't cause any failure nor performance regressions.
...
llvm-svn: 28029
2006-05-01 08:54:57 +00:00
25f55ae74a
Format #APP lines a bit nicer
...
llvm-svn: 28026
2006-05-01 04:11:03 +00:00
f71f0f2e0b
Local spiller kills a store if the folded restore is turned into a copy.
...
But this is incorrect if the spilled value live range extends beyond the
current BB.
It is currently controlled by a temporary option -spiller-check-liveout.
llvm-svn: 28024
2006-04-30 08:41:47 +00:00
2b48a94413
Remove a bogus transformation. This fixes SingleSource/UnitTests/2006-01-23-InitializedBitField.c
...
with some changes I have to the new CFE.
llvm-svn: 28022
2006-04-28 23:33:20 +00:00
c5e8ce8b8c
Remove the temporary option: -no-isel-fold-inflight
...
llvm-svn: 28012
2006-04-28 18:54:11 +00:00
d43c5c6046
TargetLowering::LowerArguments should return a VBIT_CONVERT of
...
FORMAL_ARGUMENTS SDOperand in the return result vector.
llvm-svn: 28009
2006-04-28 05:25:15 +00:00
79c50d96c9
Mapping of physregs can make it so that the designated and input physregs are
...
the same. In this case, don't emit a noop copy.
llvm-svn: 28008
2006-04-28 04:43:18 +00:00
51ab4498e7
Added a temporary option -no-isel-fold-inflight to control whether a "inflight"
...
node can be folded.
llvm-svn: 28003
2006-04-28 02:09:19 +00:00
84e95d00b5
When we have a two-address instruction where the input cannot be clobbered
...
and is already available, instead of falling back to emitting a load, fall
back to emitting a reg-reg copy. This generates significantly better code
for some SSE testcases, as SSE has lots of two-address instructions and
none of them are read/modify/write. As one example, this change does:
pshufd %XMM5, XMMWORD PTR [%ESP + 84], 255
xorps %XMM2, %XMM5
cmpltps %XMM1, %XMM0
- movaps XMMWORD PTR [%ESP + 52], %XMM0
- movapd %XMM6, XMMWORD PTR [%ESP + 52]
+ movaps %XMM6, %XMM0
cmpltps %XMM6, XMMWORD PTR [%ESP + 68]
movapd XMMWORD PTR [%ESP + 52], %XMM6
movaps %XMM6, %XMM0
cmpltps %XMM6, XMMWORD PTR [%ESP + 36]
cmpltps %XMM3, %XMM0
- movaps XMMWORD PTR [%ESP + 20], %XMM0
- movapd %XMM7, XMMWORD PTR [%ESP + 20]
+ movaps %XMM7, %XMM0
cmpltps %XMM7, XMMWORD PTR [%ESP + 4]
movapd XMMWORD PTR [%ESP + 20], %XMM7
cmpltps %XMM4, %XMM0
... which is far better than a store followed by a load!
llvm-svn: 28001
2006-04-28 01:46:50 +00:00
3784f3c57c
Insert a VBIT_CONVERT between a FORMAL_ARGUMENT node and its vector uses
...
(VAND, VADD, etc.). Legalizer will assert otherwise.
llvm-svn: 27991
2006-04-27 08:29:42 +00:00
393d96a56c
Fix Regression/CodeGen/Generic/2006-04-26-SetCCAnd.ll and
...
PR748.
llvm-svn: 27987
2006-04-27 05:01:07 +00:00
9618df1190
Don't forget return void.
...
llvm-svn: 27974
2006-04-25 23:03:35 +00:00
866b4b4d45
Fix the updating of the machine CFG when a PHI node was in a successor of
...
the jump table's range check block. This re-enables 100% dense jump tables
by default on PPC & x86
llvm-svn: 27952
2006-04-23 06:26:20 +00:00
3e04bb482b
Code cleanup associated with jump tables, thanks to Chris for noticing
...
these.
llvm-svn: 27950
2006-04-22 23:52:35 +00:00
ecb1dafd3d
Turn of jump tables for a bit, there are still some issues to work out with
...
updating the machine CFG.
llvm-svn: 27949
2006-04-22 23:51:56 +00:00
4ca2ea5b43
JumpTable support! What this represents is working asm and jit support for
...
x86 and ppc for 100% dense switch statements when relocations are non-PIC.
This support will be extended and enhanced in the coming days to support
PIC, and less dense forms of jump tables.
llvm-svn: 27947
2006-04-22 18:53:45 +00:00
b21d3bfd1f
The BFS scheduler is apparently nondeterminstic (causes many llvmgcc bootstrap
...
miscompares). Switch RISC targets to use the list-td scheduler, which isn't.
llvm-svn: 27933
2006-04-21 17:16:16 +00:00
662e940f73
Fix a couple more memory issues
...
llvm-svn: 27930
2006-04-21 15:32:26 +00:00
cc47ab3305
Fix a really subtle and obnoxious memory bug that caused issues with an
...
llvm-gcc4 boostrap. Whenever a node is deleted by the dag combiner, it
*must* be returned by the visit function, or the dag combiner will not
know that the node has been processed (and will, e.g., send it to the
target dag combine xforms).
llvm-svn: 27922
2006-04-20 23:55:59 +00:00
dcc1f995eb
This field no longer exists
...
llvm-svn: 27899
2006-04-20 18:32:41 +00:00
a38c3580bd
Remove some of the obvious V9-specific cruft
...
llvm-svn: 27893
2006-04-20 18:08:53 +00:00
a320abc494
Turn a VAND into a VECTOR_SHUFFLE is applicable.
...
DAG combiner can turn a VAND V, <-1, 0, -1, -1>, i.e. vector clear elements,
into a vector shuffle with a zero vector. It only does so when TLI tells it
the xform is profitable.
llvm-svn: 27874
2006-04-20 08:56:16 +00:00
bc1b262725
Implement folding of a bunch of binops with undef
...
llvm-svn: 27863
2006-04-20 05:39:12 +00:00
73eb58e1a2
Simplify some code
...
llvm-svn: 27846
2006-04-19 23:17:50 +00:00
916ae0775e
Fix handling of calls in functions that use vectors. This fixes a crash on
...
the code in GCC PR26546.
llvm-svn: 27780
2006-04-17 22:10:08 +00:00
bec79b4a59
Add a MachineInstr::eraseFromParent convenience method.
...
llvm-svn: 27775
2006-04-17 21:35:41 +00:00
326870b40b
Codegen insertelement with constant insertion points as scalar_to_vector
...
and a shuffle. For this:
void %test2(<4 x float>* %F, float %f) {
%tmp = load <4 x float>* %F ; <<4 x float>> [#uses=2]
%tmp3 = add <4 x float> %tmp, %tmp ; <<4 x float>> [#uses=1]
%tmp2 = insertelement <4 x float> %tmp3, float %f, uint 2 ; <<4 x float>> [#uses=2]
%tmp6 = add <4 x float> %tmp2, %tmp2 ; <<4 x float>> [#uses=1]
store <4 x float> %tmp6, <4 x float>* %F
ret void
}
we now get this on X86 (which will get better):
_test2:
movl 4(%esp), %eax
movaps (%eax), %xmm0
addps %xmm0, %xmm0
movaps %xmm0, %xmm1
shufps $3, %xmm1, %xmm1
movaps %xmm0, %xmm2
shufps $1, %xmm2, %xmm2
unpcklps %xmm1, %xmm2
movss 8(%esp), %xmm1
unpcklps %xmm1, %xmm0
unpcklps %xmm2, %xmm0
addps %xmm0, %xmm0
movaps %xmm0, (%eax)
ret
instead of:
_test2:
subl $28, %esp
movl 32(%esp), %eax
movaps (%eax), %xmm0
addps %xmm0, %xmm0
movaps %xmm0, (%esp)
movss 36(%esp), %xmm0
movss %xmm0, 8(%esp)
movaps (%esp), %xmm0
addps %xmm0, %xmm0
movaps %xmm0, (%eax)
addl $28, %esp
ret
llvm-svn: 27765
2006-04-17 19:21:01 +00:00
91226e5799
Add support for promoting stores from one legal type to another, allowing us
...
to write one pattern for vector stores instead of 4.
llvm-svn: 27730
2006-04-16 01:36:45 +00:00
7e7ad593cc
Make these predicates return true for bit_convert(buildvector)'s as well as
...
buildvectors.
llvm-svn: 27723
2006-04-15 23:38:00 +00:00
086e986e94
Make this assertion better
...
llvm-svn: 27695
2006-04-14 06:08:35 +00:00
709eaacb36
Expand some code with temporary variables to rid ourselves of the warning
...
about "dereferencing type-punned pointer will break strict-aliasing rules"
llvm-svn: 27671
2006-04-13 18:29:58 +00:00
119266ea92
Promote vector AND, OR, and XOR
...
llvm-svn: 27632
2006-04-12 21:20:24 +00:00
be8a8933e6
Vector type promotion for ISD::LOAD and ISD::SELECT
...
llvm-svn: 27606
2006-04-12 16:33:18 +00:00
d3b504ae10
Implement support for the formal_arguments node. To get this, targets shouldcustom legalize it and remove their XXXTargetLowering::LowerArguments overload
...
llvm-svn: 27604
2006-04-12 16:20:43 +00:00
417b96b6dd
Don't memoize vloads in the load map! Don't memoize them anywhere here, let
...
getNode do it. This fixes CodeGen/Generic/2006-04-11-vecload.ll
llvm-svn: 27602
2006-04-12 03:25:41 +00:00
7256b0ae05
Only get Tmp2 for cases where number of operands is > 1. Fixed return void.
...
llvm-svn: 27586
2006-04-11 06:33:39 +00:00
6cf3bbbe17
add some todos
...
llvm-svn: 27580
2006-04-11 02:00:08 +00:00
2eb22eef7d
Add basic support for legalizing returns of vectors
...
llvm-svn: 27578
2006-04-11 01:31:51 +00:00
dca2655daa
Use existing information.
...
llvm-svn: 27574
2006-04-10 23:09:19 +00:00
cb73b8d419
Missing break
...
llvm-svn: 27559
2006-04-10 18:54:36 +00:00
02274a5265
Add code generator support for VSELECT
...
llvm-svn: 27542
2006-04-08 22:22:57 +00:00
e1401e3610
Canonicalize vvector_shuffle(x,x) -> vvector_shuffle(x,undef) to enable patterns
...
to match again :)
llvm-svn: 27533
2006-04-08 05:34:25 +00:00
098c01e94e
Codegen shufflevector as VVECTOR_SHUFFLE
...
llvm-svn: 27529
2006-04-08 04:15:24 +00:00
101ea66813
add a sanity check: LegalizeOp should return a value that is the same type
...
as its input.
llvm-svn: 27528
2006-04-08 04:13:17 +00:00
78e3d565af
INSERT_VECTOR_ELT lowering bug:
...
store vector to $esp
store element to $esp + sizeof(VT) * index
load vector from $esp
The bug is VT is the type of the vector element, not the type of the vector!
llvm-svn: 27517
2006-04-08 01:46:37 +00:00
aa3185f12e
Stub out shufflevector
...
llvm-svn: 27514
2006-04-08 01:19:25 +00:00
7d4592733c
Remove section change in function end, preventing override of function's real
...
section.
llvm-svn: 27503
2006-04-08 00:35:59 +00:00
c0d6518f27
Make sure that debug labels are defined within the same section and after the
...
entry point of a function.
llvm-svn: 27494
2006-04-07 20:44:42 +00:00
2d7298c362
Foundation for call frame information.
...
llvm-svn: 27491
2006-04-07 16:34:46 +00:00
613996c55e
1. If both vector operands of a vector_shuffle are undef, turn it into an undef.
...
2. A shuffle mask element can also be an undef.
llvm-svn: 27472
2006-04-06 23:20:43 +00:00
4a2413a590
Make a vector live across blocks have the correct Vec type. This fixes
...
CodeGen/X86/2006-04-04-CrossBlockCrash.ll
llvm-svn: 27436
2006-04-05 06:54:42 +00:00
9fa8959dce
Exapnd a VECTOR_SHUFFLE to a BUILD_VECTOR if target asks for it to be expanded
...
or custom lowering fails.
llvm-svn: 27432
2006-04-05 06:07:11 +00:00
4ea52cac01
Do not create ZEXTLOAD's unless we are before legalize or the operation is
...
legal.
llvm-svn: 27402
2006-04-04 17:39:18 +00:00
6be79823e7
* Add supprot for SCALAR_TO_VECTOR operations where the input needs to be
...
promoted/expanded (e.g. SCALAR_TO_VECTOR from i8/i16 on PPC).
* Add support for targets to request that VECTOR_SHUFFLE nodes be promoted
to a canonical type, for example, we only want v16i8 shuffles on PPC.
* Move isShuffleLegal out of TLI into Legalize.
* Teach isShuffleLegal to allow shuffles that need to be promoted.
llvm-svn: 27399
2006-04-04 17:23:26 +00:00
a9e77d14c7
Constant fold bitconvert(undef)
...
llvm-svn: 27391
2006-04-04 01:02:22 +00:00
b710a81e54
The stack alignment is now computed dynamically, just verify it is correct.
...
llvm-svn: 27380
2006-04-03 21:39:57 +00:00
6bc4b9c7f8
Remove unused method
...
llvm-svn: 27379
2006-04-03 21:39:03 +00:00
e1e3adf802
Add a missing check, this fixes UnitTests/Vector/sumarray.c
...
llvm-svn: 27375
2006-04-03 17:29:28 +00:00
04c00fc844
Add a missing check, which broke a bunch of vector tests.
...
llvm-svn: 27374
2006-04-03 17:21:50 +00:00
94f012f606
back this out
...
llvm-svn: 27367
2006-04-03 03:16:50 +00:00
015eaf5f33
This should be a win of every arch
...
llvm-svn: 27364
2006-04-02 21:42:45 +00:00
4993249a04
Add a little dag combine to compile this:
...
int %AreSecondAndThirdElementsBothNegative(<4 x float>* %in) {
entry:
%tmp1 = load <4 x float>* %in ; <<4 x float>> [#uses=1]
%tmp = tail call int %llvm.ppc.altivec.vcmpgefp.p( int 1, <4 x float> < float 0x7FF8000000000000, float 0.000000e+00, float 0.000000e+00, float 0x7FF8000000000000 >, <4 x float> %tmp1 ) ; <int> [#uses=1]
%tmp = seteq int %tmp, 0 ; <bool> [#uses=1]
%tmp3 = cast bool %tmp to int ; <int> [#uses=1]
ret int %tmp3
}
into this:
_AreSecondAndThirdElementsBothNegative:
mfspr r2, 256
oris r4, r2, 49152
mtspr 256, r4
li r4, lo16(LCPI1_0)
lis r5, ha16(LCPI1_0)
lvx v0, 0, r3
lvx v1, r5, r4
vcmpgefp. v0, v1, v0
mfcr r3, 2
rlwinm r3, r3, 27, 31, 31
mtspr 256, r2
blr
instead of this:
_AreSecondAndThirdElementsBothNegative:
mfspr r2, 256
oris r4, r2, 49152
mtspr 256, r4
li r4, lo16(LCPI1_0)
lis r5, ha16(LCPI1_0)
lvx v0, 0, r3
lvx v1, r5, r4
vcmpgefp. v0, v1, v0
mfcr r3, 2
rlwinm r3, r3, 27, 31, 31
xori r3, r3, 1
cntlzw r3, r3
srwi r3, r3, 5
mtspr 256, r2
blr
llvm-svn: 27356
2006-04-02 06:11:11 +00:00
42a5fca47e
Implement promotion for EXTRACT_VECTOR_ELT, allowing v16i8 multiplies to work with PowerPC.
...
llvm-svn: 27349
2006-04-02 05:06:04 +00:00
87f080949b
Implement the Expand action for binary vector operations to break the binop
...
into elements and operate on each piece. This allows generic vector integer
multiplies to work on PPC, though the generated code is horrible.
llvm-svn: 27347
2006-04-02 03:57:31 +00:00
a9c59156be
Intrinsics that just load from memory can be treated like loads: they don't
...
have to serialize against each other. This allows us to schedule lvx's
across each other, for example.
llvm-svn: 27346
2006-04-02 03:41:14 +00:00
0442a18758
Constant fold all of the vector binops. This allows us to compile this:
...
"vector unsigned char mergeLowHigh = (vector unsigned char)
( 8, 9, 10, 11, 16, 17, 18, 19, 12, 13, 14, 15, 20, 21, 22, 23 );
vector unsigned char mergeHighLow = vec_xor( mergeLowHigh, vec_splat_u8(8));"
aka:
void %test2(<16 x sbyte>* %P) {
store <16 x sbyte> cast (<4 x int> xor (<4 x int> cast (<16 x ubyte> < ubyte 8, ubyte 9, ubyte 10, ubyte 11, ubyte 16, ubyte 17, ubyte 18, ubyte 19, ubyte 12, ubyte 13, ubyte 14, ubyte 15, ubyte 20, ubyte 21, ubyte 22, ubyte 23 > to <4 x int>), <4 x int> cast (<16 x sbyte> < sbyte 8, sbyte 8, sbyte 8, sbyte 8, sbyte 8, sbyte 8, sbyte 8, sbyte 8, sbyte 8, sbyte 8, sbyte 8, sbyte 8, sbyte 8, sbyte 8, sbyte 8, sbyte 8 > to <4 x int>)) to <16 x sbyte>), <16 x sbyte> * %P
ret void
}
into this:
_test2:
mfspr r2, 256
oris r4, r2, 32768
mtspr 256, r4
li r4, lo16(LCPI2_0)
lis r5, ha16(LCPI2_0)
lvx v0, r5, r4
stvx v0, 0, r3
mtspr 256, r2
blr
instead of this:
_test2:
mfspr r2, 256
oris r4, r2, 49152
mtspr 256, r4
li r4, lo16(LCPI2_0)
lis r5, ha16(LCPI2_0)
vspltisb v0, 8
lvx v1, r5, r4
vxor v0, v1, v0
stvx v0, 0, r3
mtspr 256, r2
blr
... which occurs here:
http://developer.apple.com/hardware/ve/calcspeed.html
llvm-svn: 27343
2006-04-02 03:25:57 +00:00
ef598059f2
Add a new -view-legalize-dags command line option
...
llvm-svn: 27342
2006-04-02 03:07:27 +00:00
e4e64b6b85
Implement constant folding of bit_convert of arbitrary constant vbuild_vector nodes.
...
llvm-svn: 27341
2006-04-02 02:53:43 +00:00
1c22728787
These entries already exist
...
llvm-svn: 27340
2006-04-02 02:51:27 +00:00
1985e1cbb8
Add some missing node names
...
llvm-svn: 27339
2006-04-02 02:41:18 +00:00
bec582f4cd
Prefer larger register classes over smaller ones when a register occurs in
...
multiple register classes. This fixes PowerPC/2006-04-01-FloatDoubleExtend.ll
llvm-svn: 27334
2006-04-02 00:24:45 +00:00
39dcf1a9e2
Delete identity shuffles, implementing CodeGen/Generic/vector-identity-shuffle.ll
...
llvm-svn: 27317
2006-03-31 22:16:43 +00:00
d9e4daabd2
Do not endian swap split vector loads. This fixes UnitTests/Vector/sumarray-dbl on PPC.
...
Now all UnitTests/Vector/* tests pass on PPC.
llvm-svn: 27299
2006-03-31 18:22:37 +00:00
8d90f526d7
Do not endian swap the operands to a store if the operands came from a vector.
...
This fixes UnitTests/Vector/simple.c with altivec.
llvm-svn: 27298
2006-03-31 18:20:46 +00:00
7e30af3887
Remove dead *extloads. This allows us to codegen vector.ll:test_extract_elt
...
to:
test_extract_elt:
alloc r3 = ar.pfs,0,1,0,0
adds r8 = 12, r32
;;
ldfs f8 = [r8]
mov ar.pfs = r3
br.ret.sptk.many rp
instead of:
test_extract_elt:
alloc r3 = ar.pfs,0,1,0,0
adds r8 = 28, r32
adds r9 = 24, r32
adds r10 = 20, r32
adds r11 = 16, r32
;;
ldfs f6 = [r8]
;;
ldfs f6 = [r9]
adds r8 = 12, r32
adds r9 = 8, r32
adds r14 = 4, r32
;;
ldfs f6 = [r10]
;;
ldfs f6 = [r11]
ldfs f8 = [r8]
;;
ldfs f6 = [r9]
;;
ldfs f6 = [r14]
;;
ldfs f6 = [r32]
mov ar.pfs = r3
br.ret.sptk.many rp
llvm-svn: 27297
2006-03-31 18:10:41 +00:00
2d8551c85b
Delete dead loads in the dag. This allows us to compile
...
vector.ll:test_extract_elt2 into:
_test_extract_elt2:
lfd f1, 32(r3)
blr
instead of:
_test_extract_elt2:
lfd f0, 56(r3)
lfd f0, 48(r3)
lfd f0, 40(r3)
lfd f1, 32(r3)
lfd f0, 24(r3)
lfd f0, 16(r3)
lfd f0, 8(r3)
lfd f0, 0(r3)
blr
llvm-svn: 27296
2006-03-31 18:06:18 +00:00
6f42325dca
Implement PromoteOp for VEXTRACT_VECTOR_ELT. Thsi fixes
...
Generic/vector.ll:test_extract_elt on non-sse X86 systems.
llvm-svn: 27294
2006-03-31 17:55:51 +00:00
8e1fcab2bc
Scalarized vector stores need not be legal, e.g. if the vector element type
...
needs to be promoted or expanded. Relegalize the scalar store once created.
This fixes CodeGen/Generic/vector.ll:test1 on non-SSE x86 targets.
llvm-svn: 27293
2006-03-31 17:37:22 +00:00
ba38035e21
Make sure to pass enough values to phi nodes when we are dealing with
...
decimated vectors. This fixes UnitTests/Vector/sumarray-dbl.c
llvm-svn: 27280
2006-03-31 02:12:18 +00:00
5fe1f54c17
Significantly improve handling of vectors that are live across basic blocks,
...
handling cases where the vector elements need promotion, expansion, and when
the vector type itself needs to be decimated.
llvm-svn: 27278
2006-03-31 02:06:56 +00:00
168e45b0b3
Expand INSERT_VECTOR_ELT to store vec, sp; store elt, sp+k; vec = load sp;
...
llvm-svn: 27274
2006-03-31 01:27:51 +00:00
67271869a8
Bug fixes: handle constantexpr insert/extract element operations
...
Handle constantpacked vectors with constantexpr elements.
This fixes CodeGen/Generic/vector-constantexpr.ll
llvm-svn: 27241
2006-03-29 00:11:43 +00:00
20e619fba3
When building a VVECTOR_SHUFFLE node from extract_element operations, make
...
sure to build it as SHUFFLE(X, undef, mask), not SHUFFLE(X, X, mask).
The later is not canonical form, and prevents the PPC splat pattern from
matching. For a particular splat, we go from generating this:
li r10, lo16(LCPI1_0)
lis r11, ha16(LCPI1_0)
lvx v3, r11, r10
vperm v3, v2, v2, v3
to generating:
vspltw v3, v2, 3
llvm-svn: 27236
2006-03-28 22:19:47 +00:00
a46dfe80c8
Canonicalize VECTOR_SHUFFLE(X, X, Y) -> VECTOR_SHUFFLE(X,undef,Y')
...
llvm-svn: 27235
2006-03-28 22:11:53 +00:00
c9992548fc
Turn a series of extract_element's feeding a build_vector into a
...
vector_shuffle node. For this:
void test(__m128 *res, __m128 *A, __m128 *B) {
*res = _mm_unpacklo_ps(*A, *B);
}
we now produce this code:
_test:
movl 8(%esp), %eax
movaps (%eax), %xmm0
movl 12(%esp), %eax
unpcklps (%eax), %xmm0
movl 4(%esp), %eax
movaps %xmm0, (%eax)
ret
instead of this:
_test:
subl $76, %esp
movl 88(%esp), %eax
movaps (%eax), %xmm0
movaps %xmm0, (%esp)
movaps %xmm0, 32(%esp)
movss 4(%esp), %xmm0
movss 32(%esp), %xmm1
unpcklps %xmm0, %xmm1
movl 84(%esp), %eax
movaps (%eax), %xmm0
movaps %xmm0, 16(%esp)
movaps %xmm0, 48(%esp)
movss 20(%esp), %xmm0
movss 48(%esp), %xmm2
unpcklps %xmm0, %xmm2
unpcklps %xmm1, %xmm2
movl 80(%esp), %eax
movaps %xmm2, (%eax)
addl $76, %esp
ret
GCC produces this (with -fomit-frame-pointer):
_test:
subl $12, %esp
movl 20(%esp), %eax
movaps (%eax), %xmm0
movl 24(%esp), %eax
unpcklps (%eax), %xmm0
movl 16(%esp), %eax
movaps %xmm0, (%eax)
addl $12, %esp
ret
llvm-svn: 27233
2006-03-28 20:28:38 +00:00
f6f94d3bce
Teach Legalize how to pack VVECTOR_SHUFFLE nodes into VECTOR_SHUFFLE nodes.
...
llvm-svn: 27232
2006-03-28 20:24:43 +00:00
8d57da2ffc
new node
...
llvm-svn: 27231
2006-03-28 19:54:42 +00:00
b7163598f9
Don't crash on X^X if X is a vector. Instead, produce a vector of zeros.
...
llvm-svn: 27229
2006-03-28 19:11:05 +00:00
ffec47ebff
Add an assertion
...
llvm-svn: 27228
2006-03-28 19:04:49 +00:00
dea0348853
Refactor address attributes. Add base register to frame info.
...
llvm-svn: 27226
2006-03-28 14:58:32 +00:00
67a636c587
More bulletproofing of llvm.dbg.declare.
...
llvm-svn: 27224
2006-03-28 13:45:20 +00:00
8374e9c4eb
More bulletproofing of DebugInfoDesc verify.
...
llvm-svn: 27203
2006-03-28 01:30:18 +00:00
e55d171ccd
Tblgen doesn't like multiple SDNode<> definitions that map to the sameenum value. Split them into separate enums.
...
llvm-svn: 27201
2006-03-28 00:40:33 +00:00
d387cc5cde
Reactivate llvm.dbg.declare.
...
llvm-svn: 27192
2006-03-27 23:31:10 +00:00
5bb1d90afd
Disable dbg_declare, it currently breaks the CFE build
...
llvm-svn: 27182
2006-03-27 21:36:03 +00:00
d5f94c9574
Fix legalization of intrinsics with chain and result values
...
llvm-svn: 27181
2006-03-27 20:28:29 +00:00
0e84f1e532
Unbreak the build on non-apple compilers :-(
...
llvm-svn: 27173
2006-03-27 16:10:59 +00:00
d09b05b0bc
Try again
...
llvm-svn: 27171
2006-03-27 08:10:26 +00:00
64efb35c32
Incorrect check for FP all one's
...
llvm-svn: 27169
2006-03-27 07:26:17 +00:00
c70e33cd6e
Change isBuildVectorAllOnesInteger to isBuildVectorAllOnes. Also check for
...
floating point cases.
llvm-svn: 27165
2006-03-27 06:58:47 +00:00
52fcad3a37
Instead of printing "INTRINSIC" on intrinsic node, print the intrinsic name.
...
llvm-svn: 27164
2006-03-27 06:45:25 +00:00
6e792f9ff8
Pass llvm/test/Regression/CodeGen/Generic/debug-info.ll.
...
llvm-svn: 27158
2006-03-27 01:51:47 +00:00
ed728c1291
SelectionDAGISel can now natively handle Switch instructions, in the same
...
manner that the LowerSwitch LLVM to LLVM pass does: emitting a binary
search tree of basic blocks. The new approach has several advantages:
it is faster, it generates significantly smaller code in many cases, and
it paves the way for implementing dense switch tables as a jump table by
handling switches directly in the instruction selector.
This functionality is currently only enabled on x86, but should be safe for
every target. In anticipation of making it the default, the cfg is now
properly updated in the x86, ppc, and sparc select lowering code.
llvm-svn: 27156
2006-03-27 01:32:24 +00:00
7092888bcc
Bullet proof against undefined args produced by upgrading ols-style debug info.
...
llvm-svn: 27155
2006-03-26 22:46:27 +00:00
84c2f0a705
How to be dumb on $5/day. Need a tri-state to track valid debug descriptors.
...
llvm-svn: 27154
2006-03-26 22:45:20 +00:00
a67899195f
Add ISD::isBuildVectorAllZeros predicate
...
llvm-svn: 27147
2006-03-26 09:50:58 +00:00
30ee72586d
Allow targets to custom lower their own intrinsics if desired.
...
llvm-svn: 27146
2006-03-26 09:12:51 +00:00
b6e2d0027a
Add some comments.
...
llvm-svn: 27133
2006-03-25 23:00:56 +00:00
f6e3b957b8
Fix a bug in ISD::isBuildVectorAllOnesInteger that caused it to always return
...
false
llvm-svn: 27131
2006-03-25 22:59:28 +00:00
c2d2811a07
Implement the ISD::isBuildVectorAllOnesInteger predicate
...
llvm-svn: 27130
2006-03-25 22:57:01 +00:00
dc1eab5886
Don't call SimplifyDemandedBits on vectors
...
llvm-svn: 27128
2006-03-25 22:19:00 +00:00
313229c74b
fix inverted conditional
...
llvm-svn: 27089
2006-03-24 22:49:42 +00:00
3324c7236f
Hack no more.
...
llvm-svn: 27079
2006-03-24 21:10:36 +00:00
68d9bf26c8
Only to vector shuffle for {x,x,y,y} cases when SCALAR_TO_VECTOR is free.
...
llvm-svn: 27071
2006-03-24 18:45:20 +00:00
53f1ecc560
Rename for truth in advertising.
...
llvm-svn: 27063
2006-03-24 09:50:27 +00:00
77e271cb4e
prefer to generate constant pool loads over splats. This prevents us from
...
using a splat for {1.0,1.0,1.0,1.0}
llvm-svn: 27055
2006-03-24 07:29:17 +00:00
87b1dddb1c
fix spello
...
llvm-svn: 27053
2006-03-24 07:15:07 +00:00
a4f6805a86
legalize vbit_convert nodes whose result is a legal type.
...
Legalize intrinsic nodes.
llvm-svn: 27036
2006-03-24 02:26:29 +00:00
d96b09a7b9
Lower target intrinsics into an INTRINSIC node
...
llvm-svn: 27035
2006-03-24 02:22:33 +00:00
6b05290922
fix some bogus assertions: noop bitconverts are legal
...
llvm-svn: 27032
2006-03-24 02:20:47 +00:00
1d2e995fc1
Lower BUILD_VECTOR to VECTOR_SHUFFLE if there are two distinct nodes (and if
...
the target can handle it). Issue two SCALAR_TO_VECTOR ops followed by a
VECTOR_SHUFFLE to select from the two vectors.
llvm-svn: 27023
2006-03-24 01:17:21 +00:00
ebac9a4adf
Identify the INTRINSIC node
...
llvm-svn: 27020
2006-03-24 01:04:30 +00:00
fb39d2a7f7
Unneeded forward.
...
llvm-svn: 27004
2006-03-23 23:05:52 +00:00
f7cfa52e7a
Make sure types are allocated in the scope of their use.
...
llvm-svn: 27002
2006-03-23 23:02:34 +00:00
d7c4e7d255
add support for splitting casts. This implements
...
CodeGen/Generic/vector.ll:test_cast_2.
llvm-svn: 26999
2006-03-23 21:16:34 +00:00
2b74656f25
Generate local variable and scope information and equivalent dwarf forms.
...
llvm-svn: 26989
2006-03-23 18:07:55 +00:00
a8bdac875d
Handle new forms of llvm.dbg intrinsics.
...
llvm-svn: 26988
2006-03-23 18:06:46 +00:00
9ea1b3f9fd
simplify some code
...
llvm-svn: 26972
2006-03-23 05:29:04 +00:00
b893d04a67
Fix a typo
...
llvm-svn: 26965
2006-03-22 22:20:49 +00:00
2f4119a608
Implement simple support for vector casting. This can currently only handle
...
casts between legal vector types.
llvm-svn: 26961
2006-03-22 20:09:35 +00:00
8fa445a89d
Endianness does not affect the order of vector fields. This fixes
...
SingleSource/UnitTests/Vector/build.c
llvm-svn: 26936
2006-03-22 01:46:54 +00:00
5be4352124
Enclose some variables in a scope to avoid error with some gcc versions
...
llvm-svn: 26934
2006-03-22 00:12:37 +00:00
340a6b5c26
add expand support for extractelement
...
llvm-svn: 26931
2006-03-21 21:02:03 +00:00
7c0cd8cafc
add some trivial support for extractelement.
...
llvm-svn: 26928
2006-03-21 20:44:12 +00:00
672a42d731
Add a hacky workaround for crashes due to vectors live across blocks.
...
Note that this code won't work for vectors that aren't legal on the
target. Improvements coming.
llvm-svn: 26925
2006-03-21 19:20:37 +00:00
21e68c8001
If a target supports splatting with SHUFFLE_VECTOR, lower to it from BUILD_VECTOR(x,x,x,x)
...
llvm-svn: 26885
2006-03-20 01:52:29 +00:00
6b20104410
TargetData doesn't know the alignment of vectors :(
...
llvm-svn: 26884
2006-03-20 01:51:46 +00:00
00f0589bc0
Add very basic support for VECTOR_SHUFFLE
...
llvm-svn: 26880
2006-03-19 23:56:04 +00:00
79fb91cc69
Allow SCALAR_TO_VECTOR to be custom lowered.
...
llvm-svn: 26867
2006-03-19 06:47:21 +00:00
9cdc5a0ce7
Add SCALAR_TO_VECTOR support
...
llvm-svn: 26866
2006-03-19 06:31:19 +00:00
eb5b2e705c
Don't bother storing undef elements of BUILD_VECTOR's
...
llvm-svn: 26858
2006-03-19 05:46:04 +00:00
5d3ff12c8f
Implement expand of BUILD_VECTOR containing variable elements.
...
This implements CodeGen/Generic/vector.ll:test_variable_buildvector
llvm-svn: 26852
2006-03-19 04:18:56 +00:00
5336a59e4b
fold insertelement(buildvector) -> buildvector if the inserted element # is
...
a constant. This implements test_constant_insert in CodeGen/Generic/vector.ll
llvm-svn: 26851
2006-03-19 01:27:56 +00:00
29b2301460
implement basic support for INSERT_VECTOR_ELT.
...
llvm-svn: 26849
2006-03-19 01:17:20 +00:00
f4e1a53647
Rename ConstantVec -> BUILD_VECTOR and VConstant -> VBUILD_VECTOR. Allow*BUILD_VECTOR to take variable inputs.
...
llvm-svn: 26847
2006-03-19 00:52:58 +00:00
c16b05e67d
implement vector.ll:test_undef
...
llvm-svn: 26845
2006-03-19 00:20:20 +00:00
93640543a9
Fix the remaining bugs in the vector expansion rework I commited yesterday.
...
This fixes CodeGen/Generic/vector.ll
llvm-svn: 26843
2006-03-19 00:07:49 +00:00
32206f54c6
Change the structure of lowering vector stuff. Note: This breaks some
...
things.
llvm-svn: 26840
2006-03-18 01:44:44 +00:00
98931bc381
add a couple enum values
...
llvm-svn: 26830
2006-03-17 19:53:59 +00:00
bb01d4f272
Remove BRTWOWAY*
...
Make the PPC backend not dependent on BRTWOWAY_CC and make the branch
selector smarter about the code it generates, fixing a case in the
readme.
llvm-svn: 26814
2006-03-17 01:40:33 +00:00
7ececaad83
Fix a problem fully scalarizing values.
...
llvm-svn: 26811
2006-03-16 23:05:19 +00:00
8471b15706
Add support for CopyFromReg from vector values. Note: this doesn't support
...
illegal vector types yet!
llvm-svn: 26799
2006-03-16 19:57:50 +00:00
49409cb925
Teach CreateRegForValue how to handle vector types.
...
llvm-svn: 26798
2006-03-16 19:51:18 +00:00
4024c00ce7
add support for vector->vector casts
...
llvm-svn: 26788
2006-03-15 22:19:46 +00:00
cad70c3e46
Add a note, this code should be moved to the dag combiner.
...
llvm-svn: 26787
2006-03-15 22:19:18 +00:00
71050ba709
Expand subprogram and added block descriptor.
...
llvm-svn: 26782
2006-03-15 19:09:58 +00:00
b8e155567a
1. Use null for serialized empty strings.
...
2. Allow for user defined debug descriptors.
3. Allow for user augmented fields on debug descriptors.
llvm-svn: 26760
2006-03-14 18:37:57 +00:00
68ac09d5cb
make sure dead token factor nodes are removed by the dag combiner.
...
llvm-svn: 26731
2006-03-13 18:37:30 +00:00
acb6e34277
Handle the removal of the debug chain.
...
llvm-svn: 26729
2006-03-13 13:07:37 +00:00
d8c2a48d58
Fold X+Y -> X|Y when safe. This implements:
...
Regression/CodeGen/PowerPC/and_add.ll
a case that occurs with dynamic allocas of constant size.
llvm-svn: 26727
2006-03-13 06:51:27 +00:00
8bb6cb7d7b
add a couple of missing folds
...
llvm-svn: 26724
2006-03-13 06:26:26 +00:00
994d8e6bd4
For targets with FABS/FNEG support, lower copysign to an integer load,
...
a select and FABS/FNEG.
This speeds up a trivial (aka stupid) copysign benchmark I wrote from 6.73s
to 2.64s, woo.
llvm-svn: 26723
2006-03-13 06:08:38 +00:00
a767dbf197
Don't advance the hazard recognizer when there are no hazards and no instructions
...
to be emitted.
Don't add one to the latency of a completed instruction if the latency of the
op is 0.
llvm-svn: 26718
2006-03-12 09:01:41 +00:00
86a9b60a25
Chain operands aren't real uses: they don't require the full latency of the
...
predecessor to finish before they can start.
llvm-svn: 26717
2006-03-12 03:52:09 +00:00
572003ca15
As a pending queue data structure to keep track of instructions whose
...
operands have all issued, but whose results are not yet available. This
allows us to compile:
int G;
int test(int A, int B, int* P) {
return (G+A)*(B+1);
}
to:
_test:
lis r2, ha16(L_G$non_lazy_ptr)
addi r4, r4, 1
lwz r2, lo16(L_G$non_lazy_ptr)(r2)
lwz r2, 0(r2)
add r2, r2, r3
mullw r3, r2, r4
blr
instead of this, which has a stall between the lis/lwz:
_test:
lis r2, ha16(L_G$non_lazy_ptr)
lwz r2, lo16(L_G$non_lazy_ptr)(r2)
addi r4, r4, 1
lwz r2, 0(r2)
add r2, r2, r3
mullw r3, r2, r4
blr
llvm-svn: 26716
2006-03-12 00:38:57 +00:00
356183d91e
rename priorityqueue -> availablequeue. When a node is scheduled, remember
...
which cycle it lands on.
llvm-svn: 26714
2006-03-11 22:44:37 +00:00
063086b0f4
Make CurrCycle a local var instead of an instance var
...
llvm-svn: 26713
2006-03-11 22:34:41 +00:00
9995a0c019
Move some methods around so that BU specific code is together, TD specific code
...
is together, and direction independent code is together.
llvm-svn: 26712
2006-03-11 22:28:35 +00:00
578d8fcb59
merge preds/chainpreds -> preds set
...
merge succs/chainsuccs -> succs set
This has no functionality change, simplifies the code, and reduces the size
of sunits.
llvm-svn: 26711
2006-03-11 22:24:20 +00:00
38280c0020
Added a parameter to control whether Constant::getStringValue() would chop
...
off the result string at the first null terminator.
llvm-svn: 26704
2006-03-10 23:52:03 +00:00
d3ef6c290a
scrape out bits of llvm-db
...
llvm-svn: 26701
2006-03-10 22:48:19 +00:00
f918e15362
Move simple-selector-specific types to the simple selector.
...
llvm-svn: 26693
2006-03-10 07:51:18 +00:00
5255d04357
Simplify the interface to the schedulers, to not pass the selected heuristicin.
...
llvm-svn: 26692
2006-03-10 07:49:12 +00:00
a5b93b8c6d
Move some simple-sched-specific instance vars to the simple scheduler.
...
llvm-svn: 26690
2006-03-10 07:42:02 +00:00
e015178de1
prune #includes
...
llvm-svn: 26689
2006-03-10 07:37:35 +00:00
4b70ff7876
move some simple scheduler methods into the simple scheduler
...
llvm-svn: 26688
2006-03-10 07:35:21 +00:00
dc2f135f5c
Make EmitNode take a SDNode instead of a NodeInfo*
...
llvm-svn: 26687
2006-03-10 07:28:36 +00:00
b9d8fa0342
Move the VRBase field from NodeInfo to being a separate, explicit, map.
...
llvm-svn: 26686
2006-03-10 07:25:12 +00:00
c48cfba44b
no need to build groups anymore
...
llvm-svn: 26684
2006-03-10 07:15:58 +00:00
6f82fe8106
Create SUnits directly from the SelectionDAG.
...
llvm-svn: 26683
2006-03-10 07:13:32 +00:00
2f8c7c3d55
Push PrepareNodeInfo/IdentifyGroups down the inheritance hierarchy
...
llvm-svn: 26682
2006-03-10 06:34:51 +00:00
349e9ddccc
Teach the latency scheduler some new tricks. In particular, to break ties,
...
keep track of a sense of "mobility", i.e. how many other nodes scheduling one
node will free up. For something like this:
float testadd(float *X, float *Y, float *Z, float *W, float *V) {
return (*X+*Y)*(*Z+*W)+*V;
}
For example, this makes us schedule *X then *Y, not *X then *Z. The former
allows us to issue the add, the later only lets us issue other loads.
This turns the above code from this:
_testadd:
lfs f0, 0(r3)
lfs f1, 0(r6)
lfs f2, 0(r4)
lfs f3, 0(r5)
fadds f0, f0, f2
fadds f1, f3, f1
lfs f2, 0(r7)
fmadds f1, f0, f1, f2
blr
into this:
_testadd:
lfs f0, 0(r6)
lfs f1, 0(r5)
fadds f0, f1, f0
lfs f1, 0(r4)
lfs f2, 0(r3)
fadds f1, f2, f1
lfs f2, 0(r7)
fmadds f1, f1, f0, f2
blr
llvm-svn: 26680
2006-03-10 05:51:05 +00:00
25e2556b71
add an aggregate method for reinserting scheduled nodes, add a callback for
...
priority impls that want to be notified when a node is scheduled
llvm-svn: 26678
2006-03-10 04:32:49 +00:00
6ce97687f7
Fix VC++ build breakage.
...
llvm-svn: 26676
2006-03-10 03:57:45 +00:00
213209a248
remove dbg_declare, it's not used yet.
...
llvm-svn: 26659
2006-03-09 20:02:42 +00:00
f0fc6bbaf3
back out my previous hack
...
llvm-svn: 26650
2006-03-09 17:48:46 +00:00
c6c9e65301
remove temporary option
...
llvm-svn: 26646
2006-03-09 17:31:22 +00:00
c44be2c4ef
temporary hack to get the build working again, apparently a header
...
commit was forgotten
llvm-svn: 26642
2006-03-09 17:11:08 +00:00
4b0e1d9e6c
Move bit field endianness to backend.
...
llvm-svn: 26639
2006-03-09 13:28:47 +00:00
d17d77aa1d
yes yes, enabled debug output is bad
...
llvm-svn: 26637
2006-03-09 07:39:25 +00:00
6398c13128
switch the t-d scheduler to use a really dumb and trivial critical path
...
latency priority function.
llvm-svn: 26636
2006-03-09 07:38:27 +00:00
d4130375c0
Pull latency information for target instructions out of the latency tables. :)
...
Only enable this with -use-sched-latencies, I'll enable it by default with a
clean nightly tester run tonight.
PPC is the only target that provides latency info currently.
llvm-svn: 26634
2006-03-09 07:15:18 +00:00
da6aafeef4
don't copy all itinerary data
...
llvm-svn: 26633
2006-03-09 07:13:00 +00:00
399bee27f0
PriorityQueue is an instance var, use it.
...
llvm-svn: 26632
2006-03-09 06:48:37 +00:00
9e95accf4e
add some comments
...
llvm-svn: 26631
2006-03-09 06:37:29 +00:00
9df647539d
Refactor the priority mechanism one step further: now that it is a separate
...
class, sever its implementation from the interface. Now we can provide new
implementations of the same interface (priority computation) without touching
the scheduler itself.
llvm-svn: 26630
2006-03-09 06:35:14 +00:00
2698f0de7a
Get rid of the multiple copies of getStringValue. Now a Constant:: method.
...
llvm-svn: 26616
2006-03-08 18:11:07 +00:00
fd22d42945
Split the priority function computation and priority queue management out
...
of the ScheduleDAGList class into a new SchedulingPriorityQueue class.
llvm-svn: 26613
2006-03-08 05:18:27 +00:00
42e2026cb0
switch from an explicitly managed list of SUnits to a simple vector of sunits
...
llvm-svn: 26612
2006-03-08 04:54:34 +00:00
12c6d89204
Shrinkify some fields, fit to 80 columns
...
llvm-svn: 26611
2006-03-08 04:41:06 +00:00
3fe975b846
revert the previous patch, didn't mean to check it in yet
...
llvm-svn: 26610
2006-03-08 04:39:05 +00:00
af5e26c980
remove "Slot", it is dead
...
llvm-svn: 26609
2006-03-08 04:37:58 +00:00
543832d39d
Change the interface for getting a target HazardRecognizer to be more clean.
...
llvm-svn: 26608
2006-03-08 04:25:59 +00:00
2370265550
libstdc++-v3 was failing to build. Needed to handle composite types with empty
...
members (running into a zero initializer.)
llvm-svn: 26607
2006-03-08 02:07:02 +00:00
313570fb17
Use "llvm.metadata" section for debug globals. Filter out these globals in the
...
asm printer.
llvm-svn: 26599
2006-03-07 22:00:35 +00:00
69effa2325
Switch to using a numeric id for anchors.
...
llvm-svn: 26598
2006-03-07 20:53:47 +00:00
3bad199894
Bitfield support.
...
llvm-svn: 26593
2006-03-07 15:51:33 +00:00
0c801bd1cf
Fix some formatting, when looking for hazards, prefer target nodes over
...
things like copyfromreg.
llvm-svn: 26586
2006-03-07 05:40:43 +00:00
01aa752a36
update file comment
...
llvm-svn: 26573
2006-03-06 17:58:04 +00:00
a00c61932d
Remove some code that doesn't make sense
...
llvm-svn: 26572
2006-03-06 07:31:44 +00:00
c5c0658aa6
Remove SUnit::Priority1: it is re-calculated on demand as number of live
...
range to be generated.
llvm-svn: 26570
2006-03-06 06:08:54 +00:00
47639dbb93
Hoist the HazardRecognizer out of the ScheduleDAGList.cpp file to where
...
targets can implement them. Make the top-down scheduler non-g5-specific.
Remove the old testing hazard recognizer.
llvm-svn: 26569
2006-03-06 00:22:00 +00:00
00b52ea8f9
Comment fixes
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llvm-svn: 26567
2006-03-05 23:59:20 +00:00
80268aaeed
Don't depend on the C99 copysign function, implement it ourselves.
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llvm-svn: 26566
2006-03-05 23:57:58 +00:00
2d945ba4c7
When a hazard recognizer needs noops to be inserted, do so. This represents
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noops as null pointers in the instruction sequence.
llvm-svn: 26564
2006-03-05 23:51:47 +00:00
fa5e1c9c26
Implement G5HazardRecognizer as a trivial thing that wants 5 cycles between
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copyfromreg nodes. Clearly useful!
llvm-svn: 26559
2006-03-05 23:13:56 +00:00
e50c092b7c
Add basic hazard recognizer support. noop insertion isn't complete yet though.
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llvm-svn: 26558
2006-03-05 22:45:01 +00:00
55e2aac24b
Fix VC++ compilation error.
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llvm-svn: 26554
2006-03-05 21:43:37 +00:00
98ecb8ec61
Split the list scheduler into top-down and bottom-up pieces. The priority
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function of the top-down scheduler are completely bogus currently, and
having (future) PPC specific in this file is also wrong, but this is a
small incremental step.
llvm-svn: 26552
2006-03-05 21:10:33 +00:00
7a36d97518
Move the available queue to being inside the ListSchedule method, since it
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bounds its lifetime.
llvm-svn: 26550
2006-03-05 20:21:55 +00:00
bdaf4f38b5
Reinstate this now that the offending opposite xform has been removed.
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llvm-svn: 26548
2006-03-05 19:53:55 +00:00
c610e62e46
print arbitrary constant pool entries
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llvm-svn: 26545
2006-03-05 09:38:03 +00:00
Chris Lattner