4c3ef4782d
disable this code for now, it's not yet safely updating phi nodes
...
llvm-svn: 31124
2006-10-22 22:47:10 +00:00
6d6fc26257
Implement PR964 and Regression/CodeGen/Generic/SwitchLowering.ll
...
llvm-svn: 31119
2006-10-22 21:36:53 +00:00
9f5a129543
don't break infinite loops
...
llvm-svn: 31102
2006-10-21 06:11:43 +00:00
28f17f45be
Use branch reversal to do stuff like this:
...
call L_strcmp$stub
testl %eax, %eax
- jne LBB26_208 #cond_true6020
- jmp LBB26_227 #bb7119
+ je LBB26_227 #bb7119
LBB26_208: #cond_true6020
movl $l31_str14, 4(%esp)
testl %eax, %eax
- jne LBB26_704 #cond_true13042
- jmp LBB26_713 #bb13151
+ je LBB26_713 #bb13151
LBB26_704: #cond_true13042
movl $_str52, 4(%esp)
cmpl 76(%ecx), %eax
- jge LBB26_1628 #cond_false63.i.i
- jmp LBB26_1769 #_Z8makeGridP13mrSurfaceListidiidd.exit.i
+ jl LBB26_1769 #_Z8makeGridP13mrSurfaceListidiidd.exit.i
LBB26_1628: #cond_false63.i.i
movl $0, 48964(%esp)
llvm-svn: 31100
2006-10-21 05:54:00 +00:00
3ca52185af
Transform code like:
...
jle FOO
jmp BAR
BAR:
into:
jle FOO
BAR:
... whoa!
llvm-svn: 31098
2006-10-21 05:43:30 +00:00
4fe01c42ca
Three changes:
...
1. Remove a bunch of ifdef'd code.
2. When a block just contains an uncond branch, change all blocks branching
to it to jump to the destination instead.
3. If branch analysis tells us some edges in the machinecfg are not actually
possible, remove them.
#2 triggers a suprisingly large number of times.
llvm-svn: 31094
2006-10-21 05:08:28 +00:00
60c9d4dc76
Add an experimental cross-jumping implementation.
...
This is currently disabled by default and limited in several ways, but does
have a positive effect.
llvm-svn: 31090
2006-10-21 00:47:49 +00:00
33f5af09e4
implement MachineOperand::isIdenticalTo
...
llvm-svn: 31088
2006-10-20 22:39:59 +00:00
c5ab6ce613
Make flag and chain edges visually distinguishable from value edges in DOT
...
output.
llvm-svn: 31067
2006-10-20 18:06:09 +00:00
e0fc4dfc22
For PR950:
...
This patch implements the first increment for the Signless Types feature.
All changes pertain to removing the ConstantSInt and ConstantUInt classes
in favor of just using ConstantInt.
llvm-svn: 31063
2006-10-20 07:07:24 +00:00
be96e1cd09
Partially in response to PR926: insert the newly created machine basic
...
blocks into the basic block list when lowering the switch inst. into a
binary tree of if-then statements. This allows the "visitSwitchCase" func
to allow for fall-through behavior.
llvm-svn: 31057
2006-10-19 21:46:38 +00:00
55e4dcad36
Add option for controlling inclusion of global AA.
...
llvm-svn: 31040
2006-10-18 19:08:31 +00:00
a15b0ebb5e
Use global info for alias analysis.
...
llvm-svn: 31035
2006-10-18 12:29:57 +00:00
73da320e50
Teach the branch folder to update debug info if it removes blocks with line
...
# notes in it.
llvm-svn: 31026
2006-10-17 23:17:27 +00:00
34136d0cc1
add a method to remove a line # record.
...
llvm-svn: 31025
2006-10-17 23:16:42 +00:00
145f6b3ec8
Do not leak all of the SourceLineInfo objects. Do not bother mallocing each
...
one separately.
llvm-svn: 31022
2006-10-17 22:06:46 +00:00
78fd0f83ff
Trivial patch to speed up legalizing common i64 constants.
...
llvm-svn: 31020
2006-10-17 21:47:13 +00:00
327b88b102
Fix CodeGen/PowerPC/2006-10-17-brcc-miscompile.ll
...
llvm-svn: 31019
2006-10-17 21:24:15 +00:00
2f4ddce75c
Fix printer for StoreSDNode.
...
llvm-svn: 31017
2006-10-17 21:18:26 +00:00
1839d76f69
Reflect MemOpAddrMode change; added a helper to create pre-indexed load.
...
llvm-svn: 31016
2006-10-17 21:14:32 +00:00
e7d2c24a7d
Make it simplier to dump DAGs while in DAGCombiner. Remove a nasty optimization.
...
llvm-svn: 31009
2006-10-17 19:33:52 +00:00
bca3e297fe
Enable deleting branches to successor blocks. With the previous patches,
...
branch folding can now compile stuff like this:
void foo(int W, int X, int Y, int Z) {
if (W & 1) {
for (; X;--X) bar();
} else if (W & 2) {
for (; Y;--Y) bar();
} else if (W & 4) {
for (; Z;--Z) bar();
} else if (W & 8) {
for (; W;--W) bar();
}
if (W) {
bar();
}
}
contrived testcase where loops exits all end up merging together. To have
the loop merges be:
...
cmplw cr0, r30, r27
bne cr0, LBB1_14 ;bb38
LBB1_16: ;cond_next48.loopexit
mr r27, r29
LBB1_20: ;cond_next48
cmplwi cr0, r27, 0
beq cr0, LBB1_22 ;UnifiedReturnBlock
...
instead of:
...
cmplw cr0, r30, r27
bne cr0, LBB1_14 ;bb38
LBB1_16: ;cond_next48.loopexit
mr r27, r29
b LBB1_20 ;cond_next48
LBB1_17: ;cond_next48.loopexit1
b LBB1_20 ;cond_next48
LBB1_18: ;cond_next48.loopexit2
b LBB1_20 ;cond_next48
LBB1_19: ;cond_next48.loopexit3
LBB1_20: ;cond_next48
cmplwi cr0, r27, 0
beq cr0, LBB1_22 ;UnifiedReturnBlock
...
This is CodeGen/PowerPC/branch-opt.ll
llvm-svn: 31006
2006-10-17 18:16:40 +00:00
d24b913a61
Clean up interface to getGlobalLinkName.
...
llvm-svn: 31001
2006-10-17 17:17:24 +00:00
56c9d2597e
Reenable this pass, fixing the bugs in it.
...
It now correctly deletes unreachable blocks and blocks that are empty.
llvm-svn: 31000
2006-10-17 17:13:52 +00:00
1e3a39cd08
Make sure operand does have size and element type operands.
...
llvm-svn: 30999
2006-10-17 17:06:35 +00:00
7126254a0e
Basic support for getGlobalLinkName.
...
llvm-svn: 30997
2006-10-17 13:41:07 +00:00
f3ae00a64a
Be careful when looking through a vbit_convert. Optimizing this:
...
(vector_shuffle
(vbitconvert (vbuildvector (copyfromreg v4f32), 1, v4f32), 4, f32),
(undef, undef, undef, undef), (0, 0, 0, 0), 4, f32)
to the
vbitconvert
is a very bad idea.
llvm-svn: 30989
2006-10-16 22:49:37 +00:00
dcb2b83886
Pass AliasAnalysis thru to DAGCombiner.
...
llvm-svn: 30984
2006-10-16 20:52:31 +00:00
9db3a08864
Global name regression.
...
llvm-svn: 30982
2006-10-16 19:38:41 +00:00
3bf4f3bd60
Tidy up after truncstore changes.
...
llvm-svn: 30961
2006-10-14 12:14:27 +00:00
47fbeda5ce
Debug tweak.
...
llvm-svn: 30959
2006-10-14 08:34:06 +00:00
6a1b2de8c4
Make sure that the node returned by SimplifySetCC is added to the worklist
...
so that it can be deleted if unused.
llvm-svn: 30955
2006-10-14 03:52:46 +00:00
0626bd2fbc
fold setcc of a setcc.
...
llvm-svn: 30953
2006-10-14 01:02:29 +00:00
bd9acad805
When SimplifySetCC was moved to the DAGCombiner, it was never removed from
...
SelectionDAG and it has since bitrotted. Remove the copy from SelectionDAG.
Next, remove the constant folding piece of DAGCombiner::SimplifySetCC into
a new FoldSetCC method which can be used by getNode() and SimplifySetCC.
This fixes obscure bugs.
llvm-svn: 30952
2006-10-14 00:41:01 +00:00
47db29a405
disable this pass for now, it's causing issues
...
llvm-svn: 30951
2006-10-14 00:30:06 +00:00
3218e0eed5
falling off the end of a function is ok with an unreachable instruction.
...
llvm-svn: 30950
2006-10-14 00:21:48 +00:00
dcf983ce41
Reduce the workload by not adding chain users to work list.
...
llvm-svn: 30948
2006-10-13 23:32:28 +00:00
45ffb1eb70
Fix a bug where we incorrectly turned '(X & 0) == 0' into '(X & 0) >> -1',
...
which is undefined. "0" isn't a power of 2.
llvm-svn: 30947
2006-10-13 22:46:18 +00:00
ab51cf2e78
Merge ISD::TRUNCSTORE to ISD::STORE. Switch to using StoreSDNode.
...
llvm-svn: 30945
2006-10-13 21:14:26 +00:00
55ad08a59b
add the branch folding pass as a late cleanup pass for all targets. For now
...
it just deletes empty MBB's. Soon it will do more :)
llvm-svn: 30941
2006-10-13 20:45:56 +00:00
3e8e57c771
disable some objectionable code, maybe we can bring this pass to life
...
llvm-svn: 30939
2006-10-13 20:43:10 +00:00
ccee9baebe
Workaround for templates
...
llvm-svn: 30927
2006-10-13 13:02:19 +00:00
13d3373e72
Clean up dump.
...
llvm-svn: 30926
2006-10-13 13:01:34 +00:00
d0620d2773
Lower X%C into X/C+stuff. This allows the 'division by a constant' logic to
...
apply to rems as well as divs. This fixes PR945 and speeds up ReedSolomon
from 14.57s to 10.90s (which is now faster than gcc).
It compiles CodeGen/X86/rem.ll into:
_test1:
subl $4, %esp
movl %esi, (%esp)
movl $2155905153, %ecx
movl 8(%esp), %esi
movl %esi, %eax
imull %ecx
addl %esi, %edx
movl %edx, %eax
shrl $31, %eax
sarl $7, %edx
addl %eax, %edx
imull $255, %edx, %eax
subl %eax, %esi
movl %esi, %eax
movl (%esp), %esi
addl $4, %esp
ret
_test2:
movl 4(%esp), %eax
movl %eax, %ecx
sarl $31, %ecx
shrl $24, %ecx
addl %eax, %ecx
andl $4294967040, %ecx
subl %ecx, %eax
ret
_test3:
subl $4, %esp
movl %esi, (%esp)
movl $2155905153, %ecx
movl 8(%esp), %esi
movl %esi, %eax
mull %ecx
shrl $7, %edx
imull $255, %edx, %eax
subl %eax, %esi
movl %esi, %eax
movl (%esp), %esi
addl $4, %esp
ret
instead of div/idiv instructions.
llvm-svn: 30920
2006-10-12 20:58:32 +00:00
a731cb674a
Add RemoveDeadNode to remove a dead node and its (potentially) dead operands.
...
llvm-svn: 30916
2006-10-12 20:34:05 +00:00
2e33fb453b
add a minor dag combine noticed when looking at PR945
...
llvm-svn: 30915
2006-10-12 20:23:19 +00:00
c040e53372
restore my previous patch, now that the X86 backend bug has been fixed:
...
http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20061009/038518.html
llvm-svn: 30906
2006-10-12 17:45:38 +00:00
df2ccc395e
D'oh - need to use the rigth kind of store.
...
llvm-svn: 30903
2006-10-12 15:22:24 +00:00
c935741b1d
Backing out Chris' last commit. It's breaking llvm-gcc bootstrapping.
...
It's turning:
movl -24(%ebp), %esp
subl $16, %esp
movl -24(%ebp), %ecx
into
movl -24(%ebp), %esp
subl $16, %esp
movl %esp, (%esp)
llvm-svn: 30902
2006-10-12 08:00:47 +00:00
86a012ab61
If we see a load from a stack slot into a physreg, consider it as providing
...
the stack slot. This fixes PR943.
llvm-svn: 30898
2006-10-12 02:34:07 +00:00
a13b9c7aa4
Alias analysis of TRUNCSTORE.
...
llvm-svn: 30889
2006-10-11 18:55:16 +00:00
6a4c6d3a7a
Typo
...
llvm-svn: 30884
2006-10-11 17:52:19 +00:00
0f7c328ae7
Handle aliasing of loadext.
...
llvm-svn: 30883
2006-10-11 17:47:52 +00:00
08edf332ed
Fix regression in combiner alias analysis.
...
llvm-svn: 30880
2006-10-11 13:47:09 +00:00
d35734bd1f
Naming consistency.
...
llvm-svn: 30878
2006-10-11 07:10:22 +00:00
a6bbf33cbf
Jimptables working again on alpha.
...
As a bonus, use the GOT node instead of the AlphaISD::GOT for internal stuff.
llvm-svn: 30873
2006-10-11 04:29:42 +00:00
6df349676e
add two helper methods.
...
llvm-svn: 30869
2006-10-11 03:58:02 +00:00
2da4671e05
FindModifiedNodeSlot needs to add LoadSDNode ivars to create proper SelectionDAGCSEMap ID.
...
llvm-svn: 30866
2006-10-11 01:47:58 +00:00
7994aec7b5
Also update getNodeLabel for LoadSDNode.
...
llvm-svn: 30861
2006-10-10 20:11:26 +00:00
fe858538c0
SDNode::dump should also print out extension type and VT.
...
llvm-svn: 30860
2006-10-10 20:05:10 +00:00
8438429c96
Fix another bug in extload promotion.
...
llvm-svn: 30857
2006-10-10 18:54:19 +00:00
dc6a3aab71
Fix a bug introduced by my LOAD/LOADX changes.
...
llvm-svn: 30853
2006-10-10 07:51:21 +00:00
e71fe34d75
Reflects ISD::LOAD / ISD::LOADX / LoadSDNode changes.
...
llvm-svn: 30844
2006-10-09 20:57:25 +00:00
5ab6d8b3fc
Eliminate more token factors by taking advantage of transitivity:
...
if TF depends on A and B, and A depends on B, TF just needs to depend on
A. With Jim's alias-analysis stuff enabled, this compiles the testcase in
PR892 into:
__Z4test3Val:
subl $44, %esp
call L__Z3foov$stub
movl %edx, 28(%esp)
movl %eax, 32(%esp)
movl %eax, 24(%esp)
movl %edx, 36(%esp)
movl 52(%esp), %ecx
movl %ecx, 4(%esp)
movl %eax, 8(%esp)
movl %edx, 12(%esp)
movl 48(%esp), %eax
movl %eax, (%esp)
call L__Z3bar3ValS_$stub
addl $44, %esp
ret
instead of:
__Z4test3Val:
subl $44, %esp
call L__Z3foov$stub
movl %eax, 24(%esp)
movl %edx, 28(%esp)
movl 24(%esp), %eax
movl %eax, 32(%esp)
movl 28(%esp), %eax
movl %eax, 36(%esp)
movl 32(%esp), %eax
movl 36(%esp), %ecx
movl 52(%esp), %edx
movl %edx, 4(%esp)
movl %eax, 8(%esp)
movl %ecx, 12(%esp)
movl 48(%esp), %eax
movl %eax, (%esp)
call L__Z3bar3ValS_$stub
addl $44, %esp
ret
llvm-svn: 30821
2006-10-08 22:57:01 +00:00
0463e08005
Combiner alias analysis passes Multisource (release-asserts.)
...
llvm-svn: 30818
2006-10-07 23:37:56 +00:00
f9f90bc239
Fix a bug legalizing zero-extending i64 loads into 32-bit loads. The bottom
...
part was always forced to be sextload, even when we needed an zextload.
llvm-svn: 30782
2006-10-07 00:58:36 +00:00
a389a612bb
initialize ivar
...
llvm-svn: 30780
2006-10-06 22:52:08 +00:00
9043823cf4
If a target uses a GOT, put it in the jt data section, not the text
...
section. This will fix alpha when Andrew implements
AlphaTargetMachine::getTargetLowering().
llvm-svn: 30779
2006-10-06 22:50:56 +00:00
9d75324ddf
jump tables handle pic
...
llvm-svn: 30776
2006-10-06 22:32:29 +00:00
4e107aa0b6
print labels even if a MBB doesn't have a corresponding LLVM BB, just don't
...
print the LLVM BB label.
llvm-svn: 30775
2006-10-06 21:28:17 +00:00
f5839a0816
Fix a miscompilation of:
...
long long foo(long long X) {
return (long long)(signed char)(int)X;
}
Instead of:
_foo:
extsb r2, r4
srawi r3, r4, 31
mr r4, r2
blr
we now produce:
_foo:
extsb r4, r4
srawi r3, r4, 31
blr
This fixes a miscompilation in ConstantFolding.cpp.
llvm-svn: 30768
2006-10-06 17:34:12 +00:00
16ae43e901
MachineBasicBlock::splice was incorrectly updating parent pointers on
...
instructions.
llvm-svn: 30760
2006-10-06 01:12:44 +00:00
df9ac47e5e
Make use of getStore().
...
llvm-svn: 30759
2006-10-05 23:01:46 +00:00
af309d29b1
Add getStore() helper function to create ISD::STORE nodes.
...
llvm-svn: 30758
2006-10-05 22:57:11 +00:00
8b1a59a272
Don't crash if an MBB doesn't have an LLVM BB
...
llvm-svn: 30757
2006-10-05 21:40:14 +00:00
6549d22ef9
Alias analysis code clean ups.
...
llvm-svn: 30753
2006-10-05 15:07:25 +00:00
66c1625a37
Emit pic jumptables to the same section that the function is emitted to,
...
allowing label differences to work. This fixes CodeGen/X86/pic_jumptable.ll
llvm-svn: 30744
2006-10-05 03:13:28 +00:00
a6a570e02f
Pass the MachineFunction into EmitJumpTableInfo.
...
llvm-svn: 30742
2006-10-05 03:01:21 +00:00
dc82241182
move getSectionForFunction to AsmPrinter
...
llvm-svn: 30736
2006-10-05 02:42:47 +00:00
f80dfa83a0
Fix some typos that can cause a flag value to have more than one use.
...
llvm-svn: 30727
2006-10-04 22:23:53 +00:00
708d0db2d8
More extensive alias analysis.
...
llvm-svn: 30721
2006-10-04 16:53:27 +00:00
0d5a0eae57
More long term solution
...
llvm-svn: 30720
2006-10-04 10:40:15 +00:00
66b0b55816
Work around for some problems with templates.
...
llvm-svn: 30715
2006-10-04 01:43:13 +00:00
5d9fd977d3
Combine ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD into ISD::LOADX. Add an
...
extra operand to LOADX to specify the exact value extension type.
llvm-svn: 30714
2006-10-04 00:56:09 +00:00
fc416faaa0
Use $( $| $) to represent alternatives in asm blocks instead of {|}. This
...
is needed to support targets where {|} aren't special symbols.
llvm-svn: 30712
2006-10-03 23:27:09 +00:00
91d76cb27f
Fix an obvious typo.
...
llvm-svn: 30711
2006-10-03 23:08:27 +00:00
bd7286e606
Bugfixes
...
llvm-svn: 30709
2006-10-03 20:19:23 +00:00
de154b1737
Print the MBB ID # along with the bb tag in the -print-machine-instrs output.
...
llvm-svn: 30708
2006-10-03 20:17:24 +00:00
64fd9487bd
Provide a function that ensures MBB numbering is dense and inorder. This
...
can be used by MachineFunctionPasses who need this property.
llvm-svn: 30706
2006-10-03 19:18:57 +00:00
984f0ce06b
Fix for PR929. The PHI nodes were being gone through for each instruction
...
in a successor block for every block...resulting in some O(N^k) algorithm
which wasn't very good for performance. Calculating this information up
front and keeping it in a map made it much faster.
llvm-svn: 30697
2006-10-03 07:20:20 +00:00
e73a22514d
Debugging kruft
...
llvm-svn: 30688
2006-10-02 13:01:17 +00:00
1368c265da
Add ability to annotate (color) nodes in a viewGraph.
...
llvm-svn: 30686
2006-10-02 12:26:53 +00:00
eea983eb5d
simplify code
...
llvm-svn: 30659
2006-09-28 23:17:41 +00:00
bcf1b4120f
TargetRegisterClass specifies the desired spill alignment. However, it cannot be honored if stack alignment is smaller.
...
llvm-svn: 30648
2006-09-28 18:52:32 +00:00
5d409822d6
"Once more into the breach, dear friends, once more, or fill the wall up
...
with our English dead."
No! Really! Serious this time...It was how the vreg uses were being
adjusted that was causing hte Olden tests to fail. I corrected this and
the Olden and Regression tests all passed.
llvm-svn: 30644
2006-09-28 07:10:24 +00:00
a9caf95591
refactor critical edge breaking out into the SplitCritEdgesForPHIConstants method.
...
This is a baby step towards fixing PR925.
llvm-svn: 30643
2006-09-28 06:17:10 +00:00
764caf6129
re-re-revert this, back to the right revision. It currently breaks bisort/mst
...
in olden among others.
llvm-svn: 30637
2006-09-28 00:11:54 +00:00
d31f55c236
PEI now place callee save spills closest to the address pointed to by the
...
incoming stack. This allows X86 backend to use push / pop in epilogue /
prologue.
llvm-svn: 30636
2006-09-28 00:10:27 +00:00
9f7d0d1dc5
re-revert this patch, bisort and mst are still broken in Olden.
...
llvm-svn: 30634
2006-09-28 00:04:21 +00:00
1f29e6c5c5
Reapplying this patch. With the newest commits, the error in Olden/bisort
...
has disappeared.
llvm-svn: 30633
2006-09-27 22:37:35 +00:00
5f6c93701b
Temporarily revert this. This breaks Olden/bisort on PPC
...
llvm-svn: 30628
2006-09-27 16:59:16 +00:00
0a7f617a6c
PR878: Instead of calculating the vreg to PHI use count everytime we get
...
a function, do it up front in linear time (going through all of the
instructions once). We create a map out of them. Then it's no problem to
use the information in it during elimination...
llvm-svn: 30624
2006-09-27 09:04:15 +00:00
30b4708df2
Add support for ${:private} which prints "L" on darwin.
...
llvm-svn: 30620
2006-09-27 00:06:07 +00:00
a32814b033
Add support for ${:comment}, which expands to the current target's comment
...
character, and ${:uid} which expands to a unique ID for the MachineInstr.
More can be added if/when they are needed.
llvm-svn: 30619
2006-09-26 23:59:50 +00:00
5405c06737
Rename function. It's determining which callee-save registers to save.
...
llvm-svn: 30616
2006-09-26 22:29:31 +00:00
c19ef92403
Comments on JumpTableness
...
llvm-svn: 30615
2006-09-26 20:02:30 +00:00
60832693a7
Load chain check is not needed
...
llvm-svn: 30613
2006-09-26 17:44:58 +00:00
dde51671e5
Chain can be any operand
...
llvm-svn: 30611
2006-09-26 09:32:41 +00:00
5f3e0af9d0
Wrong size for load
...
llvm-svn: 30610
2006-09-26 08:14:06 +00:00
b4a864d533
Can't move a load node if it's chain is not used.
...
llvm-svn: 30609
2006-09-26 07:37:42 +00:00
9a1e91b107
print the preds of each MBB
...
llvm-svn: 30606
2006-09-26 03:41:59 +00:00
66af390631
Add support for targets that want to do something with the llvm.used list,
...
because they have an aggressive linker that does dead code stripping.
llvm-svn: 30604
2006-09-26 03:38:18 +00:00
7aa0638aa9
Accidental enable of bad code
...
llvm-svn: 30601
2006-09-25 21:11:32 +00:00
b5534e5c28
Fix chain dropping in load and drop unused stores in ret blocks.
...
llvm-svn: 30600
2006-09-25 19:32:58 +00:00
d07be232ba
Core antialiasing for load and store.
...
llvm-svn: 30597
2006-09-25 16:29:54 +00:00
783a4a9d86
Add support for other relocation bases to jump tables, as well as custom asm directives
...
llvm-svn: 30593
2006-09-24 19:45:58 +00:00
77c0757f8b
PIC jump table entries are always 32-bit. This fixes PIC jump table support on X86-64.
...
llvm-svn: 30590
2006-09-24 05:22:38 +00:00
449a0c7e33
Make it work for DAG combine of multi-value nodes.
...
llvm-svn: 30573
2006-09-21 19:04:05 +00:00
35f7eebb49
core corrections
...
llvm-svn: 30570
2006-09-21 17:35:47 +00:00
5d19d59017
Basic "in frame" alias analysis.
...
llvm-svn: 30568
2006-09-21 16:28:59 +00:00
082db3f9aa
fold (aext (and (trunc x), cst)) -> (and x, cst).
...
llvm-svn: 30561
2006-09-21 06:40:43 +00:00
fa9f92cf65
Check the right value type. This fixes 186.crafty on x86
...
llvm-svn: 30560
2006-09-21 06:17:39 +00:00
8d8a3bf9c9
Compile:
...
int %test(ulong *%tmp) {
%tmp = load ulong* %tmp ; <ulong> [#uses=1]
%tmp.mask = shr ulong %tmp, ubyte 50 ; <ulong> [#uses=1]
%tmp.mask = cast ulong %tmp.mask to ubyte
%tmp2 = and ubyte %tmp.mask, 3 ; <ubyte> [#uses=1]
%tmp2 = cast ubyte %tmp2 to int ; <int> [#uses=1]
ret int %tmp2
}
to:
_test:
movl 4(%esp), %eax
movl 4(%eax), %eax
shrl $18, %eax
andl $3, %eax
ret
instead of:
_test:
movl 4(%esp), %eax
movl 4(%eax), %eax
shrl $18, %eax
# TRUNCATE movb %al, %al
andb $3, %al
movzbl %al, %eax
ret
llvm-svn: 30558
2006-09-21 06:14:31 +00:00
a31f0a622b
Generalize (zext (truncate x)) and (sext (truncate x)) folding to work when
...
the src/dst are not the same size. This catches things like "truncate
32-bit X to 8 bits, then zext to 16", which happens a bit on X86.
llvm-svn: 30557
2006-09-21 06:00:20 +00:00
c8cd62d381
Compile:
...
int test3(int a, int b) { return (a < 0) ? a : 0; }
to:
_test3:
srawi r2, r3, 31
and r3, r2, r3
blr
instead of:
_test3:
cmpwi cr0, r3, 1
li r2, 0
blt cr0, LBB2_2 ;entry
LBB2_1: ;entry
mr r3, r2
LBB2_2: ;entry
blr
This implements: PowerPC/select_lt0.ll:seli32_a_a
llvm-svn: 30517
2006-09-20 06:41:35 +00:00
8746e2cd57
Fold the full generality of (any_extend (truncate x))
...
llvm-svn: 30514
2006-09-20 06:29:17 +00:00
8b68decb27
Two things:
...
1. teach SimplifySetCC that '(srl (ctlz x), 5) == 0' is really x != 0.
2. Teach visitSELECT_CC to use SimplifySetCC instead of calling it and
ignoring the result. This allows us to compile:
bool %test(ulong %x) {
%tmp = setlt ulong %x, 4294967296
ret bool %tmp
}
to:
_test:
cntlzw r2, r3
cmplwi cr0, r3, 1
srwi r2, r2, 5
li r3, 0
beq cr0, LBB1_2 ;
LBB1_1: ;
mr r3, r2
LBB1_2: ;
blr
instead of:
_test:
addi r2, r3, -1
cntlzw r2, r2
cntlzw r3, r3
srwi r2, r2, 5
cmplwi cr0, r2, 0
srwi r2, r3, 5
li r3, 0
bne cr0, LBB1_2 ;
LBB1_1: ;
mr r3, r2
LBB1_2: ;
blr
This isn't wonderful, but it's an improvement.
llvm-svn: 30513
2006-09-20 06:19:26 +00:00
875ea0cdbd
Expand 64-bit shifts more optimally if we know that the high bit of the
...
shift amount is one or zero. For example, for:
long long foo1(long long X, int C) {
return X << (C|32);
}
long long foo2(long long X, int C) {
return X << (C&~32);
}
we get:
_foo1:
movb $31, %cl
movl 4(%esp), %edx
andb 12(%esp), %cl
shll %cl, %edx
xorl %eax, %eax
ret
_foo2:
movb $223, %cl
movl 4(%esp), %eax
movl 8(%esp), %edx
andb 12(%esp), %cl
shldl %cl, %eax, %edx
shll %cl, %eax
ret
instead of:
_foo1:
subl $4, %esp
movl %ebx, (%esp)
movb $32, %bl
movl 8(%esp), %eax
movl 12(%esp), %edx
movb %bl, %cl
orb 16(%esp), %cl
shldl %cl, %eax, %edx
shll %cl, %eax
xorl %ecx, %ecx
testb %bl, %bl
cmovne %eax, %edx
cmovne %ecx, %eax
movl (%esp), %ebx
addl $4, %esp
ret
_foo2:
subl $4, %esp
movl %ebx, (%esp)
movb $223, %cl
movl 8(%esp), %eax
movl 12(%esp), %edx
andb 16(%esp), %cl
shldl %cl, %eax, %edx
shll %cl, %eax
xorl %ecx, %ecx
xorb %bl, %bl
testb %bl, %bl
cmovne %eax, %edx
cmovne %ecx, %eax
movl (%esp), %ebx
addl $4, %esp
ret
llvm-svn: 30506
2006-09-20 03:38:48 +00:00
698000b0da
Fix UnitTests/2005-05-12-Int64ToFP.c with llc-beta. In particular, do not
...
allow it to go into an infinite loop, filling up the disk!
llvm-svn: 30494
2006-09-19 18:02:01 +00:00
5a42ebcff3
Fold extract_element(cst) to cst
...
llvm-svn: 30478
2006-09-19 05:02:39 +00:00
4c059f4962
Minor speedup for legalize by avoiding some malloc traffic
...
llvm-svn: 30477
2006-09-19 04:51:23 +00:00
1fc7c363e6
Fix a typo.
...
llvm-svn: 30474
2006-09-18 23:28:33 +00:00
4bfaf0bd2c
Allow i32 UDIV, SDIV, UREM, SREM to be expanded into libcalls.
...
llvm-svn: 30470
2006-09-18 21:49:04 +00:00
51ad73c98c
oops
...
llvm-svn: 30462
2006-09-18 18:00:18 +00:00
c50458fb90
absolute addresses must match pointer size
...
llvm-svn: 30461
2006-09-18 17:59:35 +00:00
d30bba331f
Sort out mangled names for globals
...
llvm-svn: 30460
2006-09-18 14:47:26 +00:00
e50f5d1fb1
Oh yeah, this is needed too
...
llvm-svn: 30407
2006-09-16 05:08:34 +00:00
1b63391fdf
simplify control flow, no functionality change
...
llvm-svn: 30403
2006-09-16 00:21:44 +00:00
fbadbda6ba
Allow custom expand of mul
...
llvm-svn: 30402
2006-09-16 00:09:24 +00:00
8fb3d445f5
Keep track of the start of MBB's in a separate map from instructions. This
...
is faster and is needed for future improvements.
llvm-svn: 30383
2006-09-15 03:57:23 +00:00
46d710e6ea
Fold (X & C1) | (Y & C2) -> (X|Y) & C3 when possible.
...
This implements CodeGen/X86/and-or-fold.ll
llvm-svn: 30379
2006-09-14 21:11:37 +00:00
97614c86ce
Split rotate matching code out to its own function. Make it stronger, by
...
matching things like ((x >> c1) & c2) | ((x << c3) & c4) to (rot x, c5) & c6
llvm-svn: 30376
2006-09-14 20:50:57 +00:00
616aa548b2
Use getOffset() instead.
...
llvm-svn: 30327
2006-09-14 07:41:12 +00:00
2ad050fb3e
Use MachineConstantPoolEntry getOffset() and getType() accessors.
...
llvm-svn: 30326
2006-09-14 07:35:00 +00:00
4f9299552b
A MachineConstantPool may have mixed Constant* and MachineConstantPoolValue* values.
...
llvm-svn: 30316
2006-09-14 05:50:57 +00:00
84cc1f7cb8
If LSR went through a lot of trouble to put constants (e.g. the addr of a global
...
in a specific BB, don't undo this!). This allows us to compile
CodeGen/X86/loop-hoist.ll into:
_foo:
xorl %eax, %eax
*** movl L_Arr$non_lazy_ptr, %ecx
movl 4(%esp), %edx
LBB1_1: #cond_true
movl %eax, (%ecx,%eax,4)
incl %eax
cmpl %edx, %eax
jne LBB1_1 #cond_true
LBB1_2: #return
ret
instead of:
_foo:
xorl %eax, %eax
movl 4(%esp), %ecx
LBB1_1: #cond_true
*** movl L_Arr$non_lazy_ptr, %edx
movl %eax, (%edx,%eax,4)
incl %eax
cmpl %ecx, %eax
jne LBB1_1 #cond_true
LBB1_2: #return
ret
This was noticed in 464.h264ref. This doesn't usually affect PPC,
but strikes X86 all the time.
llvm-svn: 30290
2006-09-13 06:02:42 +00:00
72b503bcad
Compile X << 1 (where X is a long-long) to:
...
addl %ecx, %ecx
adcl %eax, %eax
instead of:
movl %ecx, %edx
addl %edx, %edx
shrl $31, %ecx
addl %eax, %eax
orl %ecx, %eax
and to:
addc r5, r5, r5
adde r4, r4, r4
instead of:
slwi r2,r9,1
srwi r0,r11,31
slwi r3,r11,1
or r2,r0,r2
on PPC.
llvm-svn: 30284
2006-09-13 03:50:39 +00:00
45fe3bc72c
Added support for machine specific constantpool values. These are useful for
...
representing expressions that can only be resolved at link time, etc.
llvm-svn: 30278
2006-09-12 21:00:35 +00:00
a0d95a8da9
Behold, more work on relocations. Things are looking pretty good now.
...
llvm-svn: 30240
2006-09-10 23:03:44 +00:00
2e0dfb0b16
This code was trying too hard. By eliminating redundant edges in the CFG
...
due to switch cases going to the same place, it make #pred != #phi entries,
breaking live interval analysis.
This fixes 458.sjeng on x86 with llc.
llvm-svn: 30236
2006-09-10 06:36:57 +00:00
f0359b343a
Implement the fpowi now by lowering to a libcall
...
llvm-svn: 30225
2006-09-09 06:03:30 +00:00
e4bbb6c341
Allow targets to custom lower expanded BIT_CONVERT's
...
llvm-svn: 30217
2006-09-09 00:20:27 +00:00
69df6132d7
First pass at supporting relocations. Relocations are written correctly to
...
the file now, however the relocated address is currently wrong. Fixing
that will require some deep pondering.
llvm-svn: 30207
2006-09-08 22:42:09 +00:00
b2e7316b2d
Non-allocatable physregs can be killed and dead, but don't treat them as
...
safe for later allocation. This fixes McCat/18-imp with llc-beta.
llvm-svn: 30204
2006-09-08 20:21:31 +00:00
050c64c51d
This fixes Benchmarks/Prolangs-C/unix-smail
...
llvm-svn: 30198
2006-09-08 19:11:11 +00:00
9b1a6ebf20
Fix a bunch of llc-beta failures on x86 yesterday. Don't allow selection
...
of unallocatable registers, just because an alias is allocatable. We were
picking registers like SIL just because ESI was being used.
llvm-svn: 30197
2006-09-08 19:03:30 +00:00
261779bb45
Make target asm info a property of the target machine.
...
llvm-svn: 30162
2006-09-07 22:06:40 +00:00
95b3dde8bb
Fix pasto that was breaking x86 tests.
...
llvm-svn: 30151
2006-09-07 18:50:20 +00:00
707339a57b
Fix CodeGen/Generic/2006-09-06-SwitchLowering.ll, a bug where SDIsel inserted
...
too many phi operands when lowering a switch to branches in some cases.
llvm-svn: 30142
2006-09-07 01:59:34 +00:00
a6211dcdad
Separate target specific asm properties from the asm printers.
...
llvm-svn: 30126
2006-09-06 18:34:40 +00:00
ddfb10b5af
Only call isUse/isDef on register operands
...
llvm-svn: 30122
2006-09-05 20:32:06 +00:00
2cb238320d
Only call isUse/isDef on register operands
...
llvm-svn: 30118
2006-09-05 20:19:27 +00:00
45456d44e3
Don't call isDef on non-registers
...
llvm-svn: 30117
2006-09-05 20:02:51 +00:00
0dce3311c4
Change the default to 0, which means 'default'.
...
llvm-svn: 30114
2006-09-05 17:39:15 +00:00
af23f9b5f6
Completely eliminate def&use operands. Now a register operand is EITHER a
...
def operand or a use operand.
llvm-svn: 30109
2006-09-05 02:31:13 +00:00
13a5dcddce
Fix a long-standing wart in the code generator: two-address instruction lowering
...
actually *removes* one of the operands, instead of just assigning both operands
the same register. This make reasoning about instructions unnecessarily complex,
because you need to know if you are before or after register allocation to match
up operand #'s with the target description file.
Changing this also gets rid of a bunch of hacky code in various places.
This patch also includes changes to fold loads into cmp/test instructions in
the X86 backend, along with a significant simplification to the X86 spill
folding code.
llvm-svn: 30108
2006-09-05 02:12:02 +00:00
1eed04d1fb
Correct fix for a crasher on functions with live in values
...
llvm-svn: 30099
2006-09-04 18:27:40 +00:00
bff0b5969f
Hack around a regression I introduced yesterday
...
llvm-svn: 30098
2006-09-04 18:20:15 +00:00
373be1d1a2
forgot this
...
llvm-svn: 30097
2006-09-04 07:44:11 +00:00
cf6749e4c0
add setJumpBufSize() and setJumpBufAlignment() to target-lowering.
...
Call these from your backend to enjoy setjmp/longjmp goodness, see
lib/Target/IA64/IA64ISelLowering.cpp for an example
llvm-svn: 30095
2006-09-04 06:21:35 +00:00
a916db12e4
new file
...
llvm-svn: 30082
2006-09-04 04:16:09 +00:00
8584e940b8
Avoid beating on the mi2i map when we know the answer already.
...
llvm-svn: 30066
2006-09-03 08:07:11 +00:00
774785a79d
minor speedup
...
llvm-svn: 30065
2006-09-03 07:53:50 +00:00
7cc20d418b
Fix Regression/CodeGen/Generic/2006-09-02-LocalAllocCrash.ll on X86.
...
Just because an alias of a register is available, it doesn't mean that we
can arbitrarily evict the register.
llvm-svn: 30064
2006-09-03 07:15:37 +00:00
bd79458b0e
When deleting a machine instruction, make sure to remove it from the
...
livevariables information. This fixes several regalloc=local failures on x86
llvm-svn: 30062
2006-09-03 00:06:08 +00:00
f8f724a2b1
Move two methods out of line, make them work when the record for a machine
...
instruction includes physregs.
llvm-svn: 30061
2006-09-03 00:05:09 +00:00
f2ce949ae9
improve compat with certain versions of GCC (on cygwin?)
...
llvm-svn: 30054
2006-09-02 17:37:30 +00:00
75742e532a
Iteration is required for some cases, even if they don't occur in crafty.
...
Restore it, which re-fixes X86/2006-08-21-ExtraMovInst.ll
llvm-svn: 30050
2006-09-02 05:32:53 +00:00
5a56d30906
When joining two intervals where the RHS is really simple, use a light-weight
...
method for joining the live ranges instead of the fully-general one.
llvm-svn: 30049
2006-09-02 05:26:59 +00:00
e93762d36e
Allow legalizer to expand ISD::MUL using only MULHS in the rare case that is
...
possible and the target only supports MULHS.
llvm-svn: 30022
2006-09-01 18:17:58 +00:00
5352d0cc4d
Corrections.
...
llvm-svn: 30021
2006-09-01 12:55:05 +00:00
93c067dc2d
Pull some code out of a hot recursive function because the common case doesn't
...
need recursion.
llvm-svn: 30015
2006-09-01 07:00:23 +00:00
3eac2c87aa
Reserve space in the ValueNumberInfo vector. This speeds up live interval
...
analysis 16% on crafty.
Wrap long lines.
llvm-svn: 30012
2006-09-01 06:10:18 +00:00
f765351978
Iterative coallescing doesn't buy us anything (we get identical results on
...
crafty with and without it). Removing it speeds up live intervals 6%.
llvm-svn: 30010
2006-09-01 04:02:42 +00:00
31305c45da
DAG combiner fix for rotates. Previously the outer-most condition checks
...
for ROTL availability. This prevents it from forming ROTR for targets that
has ROTR only.
llvm-svn: 29997
2006-08-31 07:41:12 +00:00
a700a19d04
Add a special case that speeds up coallescing a bit, but not enough.
...
llvm-svn: 29996
2006-08-31 06:48:26 +00:00
78cca7243c
Delete copies as they are coallesced instead of waiting until the end.
...
llvm-svn: 29995
2006-08-31 05:58:59 +00:00
aa36808fd3
avoid calling the virtual isMoveInstr method endlessly by caching its results.
...
llvm-svn: 29994
2006-08-31 05:54:43 +00:00
cb74860cce
Fix a compiler crash bootstrapping llvm-gcc.
...
llvm-svn: 29989
2006-08-30 23:02:29 +00:00
34434e97c9
Teach the coallescer to coallesce live intervals joined by an arbitrary
...
number of copies, potentially defining live ranges that appear to have
differing value numbers that become identical when coallsced. Among other
things, this fixes CodeGen/X86/shift-coalesce.ll and PR687.
llvm-svn: 29968
2006-08-29 23:18:15 +00:00
2eebe8b05e
Handle callee saved registers in dwarf frame info (lead up to exception
...
handling.)
llvm-svn: 29954
2006-08-29 16:24:26 +00:00
e5570a4c3f
Move isCommutativeBinOp from SelectionDAG.cpp and DAGCombiner.cpp out. Make it a static method of SelectionDAG.
...
llvm-svn: 29951
2006-08-29 06:42:35 +00:00
c2d3d3112e
eliminate RegisterOpt. It does the same thing as RegisterPass.
...
llvm-svn: 29925
2006-08-27 22:42:52 +00:00
3c9b2420df
Eliminate RegisterAnalysis. RegisterPass now does all that is necessary.
...
llvm-svn: 29921
2006-08-27 22:30:17 +00:00
3d27be1333
s|llvm/Support/Visibility.h|llvm/Support/Compiler.h|
...
llvm-svn: 29911
2006-08-27 12:54:02 +00:00
2c3683a901
typo fix
...
llvm-svn: 29910
2006-08-27 12:47:48 +00:00
849f4bf8dd
Eliminate SelectNodeTo() and getTargetNode() variants which take more than
...
3 SDOperand operands. They are replaced by versions which take an array
of SDOperand and the number of operands.
llvm-svn: 29905
2006-08-27 08:08:54 +00:00
7851db75d9
Properly size the string table, and emit symbol table and string table
...
entries in the correct order, fixing several fixmes.
llvm-svn: 29902
2006-08-26 15:46:34 +00:00
34b70eea5c
SelectNodeTo now returns a SDNode*.
...
llvm-svn: 29901
2006-08-26 08:00:10 +00:00
122f2bcdc2
Simplifications to liveinterval analysis, no functionality change.
...
llvm-svn: 29896
2006-08-26 01:28:16 +00:00
f4f0b1995c
Completely change the way that joining with physregs is implemented. This
...
paves the way for future changes, increases coallescing opportunities (in
theory, not witnessed in practice), and eliminates the really expensive
LiveIntervals::overlapsAliases method.
llvm-svn: 29890
2006-08-25 23:41:24 +00:00
fb96c74874
Tidy up.
...
llvm-svn: 29888
2006-08-25 22:56:30 +00:00
92206f9404
Consolidate callee saved register information so that it can me used by debug
...
information and exception handling.
llvm-svn: 29881
2006-08-25 19:45:51 +00:00
f8bf1e6034
Allow for register numbers > 31.
...
llvm-svn: 29879
2006-08-25 19:39:52 +00:00
89fa9c7d65
Get closer to handling globals correctly. We now generally get them in the
...
right section.
llvm-svn: 29871
2006-08-25 06:36:58 +00:00
24d4208c97
When replacing value numbers, make sure to compactify the value # space.
...
llvm-svn: 29865
2006-08-24 23:22:59 +00:00
bdf121060c
Take advantage of the recent improvements to the liveintervals set (tracking
...
instructions which define each value#) to simplify and improve the coallescer.
In particular, this patch:
1. Implements iterative coallescing.
2. Reverts an unsafe hack from handlePhysRegDef, superceeding it with a
better solution.
3. Implements PR865, "coallescing" away the second copy in code like:
A = B
...
B = A
This also includes changes to symbolically print registers in intervals
when possible.
llvm-svn: 29862
2006-08-24 22:43:55 +00:00
3cb3921a60
Initial checkin of the Mach-O emitter. There's plenty of fixmes, but it
...
does emit linkable .o files in very simple cases.
llvm-svn: 29850
2006-08-23 21:08:52 +00:00
2e9f1bc056
Improve the LiveInterval class to keep track of which machine instruction
...
defines each value# tracked by the interval. This will be used to improve
coallescing.
llvm-svn: 29830
2006-08-22 18:19:46 +00:00
1d77a0ff88
Print physreg names symbolically in dumps
...
llvm-svn: 29805
2006-08-21 23:03:54 +00:00
213159a6ee
Print debug info as:
...
*** Register mapping ***
reg 1024 -> %reg1028
reg 1026 -> EAX
reg 1027 -> %reg1028
instead of:
*** Register mapping ***
reg 1024 -> reg 1028
reg 1026 -> reg 15
reg 1027 -> reg 1028
llvm-svn: 29803
2006-08-21 22:56:29 +00:00
b6ac11e120
Adding C++ member support.
...
llvm-svn: 29799
2006-08-21 21:20:18 +00:00
451b099113
Fix PR861
...
llvm-svn: 29796
2006-08-21 20:24:53 +00:00
04f2246400
Added a check so that if we have two machine instructions in this form
...
MOV R0, R1
MOV R1, R0
the second machine instruction is removed. Added a regression test.
llvm-svn: 29792
2006-08-21 07:33:33 +00:00
d86418ab20
switch the SUnit pred/succ sets from being std::sets to being smallvectors.
...
This reduces selectiondag time on kc++ from 5.43s to 4.98s (9%). More
significantly, this speeds up the default ppc scheduler from ~1571ms to 1063ms,
a 33% speedup.
llvm-svn: 29743
2006-08-17 00:09:56 +00:00
65879caf07
minor changes.
...
llvm-svn: 29740
2006-08-16 22:57:46 +00:00
a4f3625c23
Use the appropriate typedef
...
llvm-svn: 29730
2006-08-16 20:59:32 +00:00
a5a3eafbd0
Start using SDVTList more consistently
...
llvm-svn: 29711
2006-08-15 19:11:05 +00:00
f98411a220
add a new SDVTList type and new SelectionDAG::getVTList methods to streamline
...
the creation of canonical VTLists.
llvm-svn: 29709
2006-08-15 17:46:01 +00:00
bd8877744b
eliminate use of getNode that takes vector of valuetypes.
...
llvm-svn: 29687
2006-08-14 23:53:35 +00:00
3bf4be453f
Add a new getNode() method that takes a pointer to an already-intern'd list
...
of value-type nodes. This avoids having to do mallocs for std::vectors of
valuetypes when a node returns more than one type.
llvm-svn: 29685
2006-08-14 23:31:51 +00:00
e93a39f2d7
remove SelectionDAG::InsertISelMapEntry, it is dead
...
llvm-svn: 29677
2006-08-14 22:24:39 +00:00
63268f0672
Add code to resize the CSEMap hash table. This doesn't speedup codegen of
...
kimwitu, but seems like a good idea from a "avoid performance cliffs" standpoint :)
llvm-svn: 29675
2006-08-14 22:19:25 +00:00
8e37283d8b
Add the actual constant to the hash for ConstantPool nodes. Thanks to
...
Rafael Espindola for pointing this out.
llvm-svn: 29669
2006-08-14 20:12:44 +00:00
984c1a4a8f
Emit .set directives for jump table entries when possible, which reduces
...
the number of relocations in object files, shrinkifying them.
llvm-svn: 29650
2006-08-12 21:29:52 +00:00
167ea3eb5f
Fix an obvious bug, noticed by inspection. No current targets trigger this.
...
llvm-svn: 29648
2006-08-12 05:41:39 +00:00
0a60294fa0
Switch to using SuperFastHash instead of adding all elements together. This
...
doesn't significantly improve performance but it helps a small amount.
llvm-svn: 29642
2006-08-12 01:07:10 +00:00
04aa034f38
Switch NodeID to track 32-bit chunks instead of 8-bit chunks, for a 2.5%
...
speedup in isel time.
llvm-svn: 29640
2006-08-11 23:55:53 +00:00
0c2e5412bb
Remove 8 more std::map's.
...
llvm-svn: 29631
2006-08-11 21:55:30 +00:00
3f16b201e2
Move the BBNodes, GlobalValues, TargetGlobalValues, Constants, TargetConstants,
...
RegNodes, and ValueNodes maps into the CSEMap.
llvm-svn: 29626
2006-08-11 21:01:22 +00:00
fcb16470ec
eliminate the NullaryOps map, use CSEMap instead.
...
llvm-svn: 29621
2006-08-11 18:38:11 +00:00
6f22ebd8be
change internal impl of dag combiner so that calls to CombineTo never have to
...
make a temporary vector.
llvm-svn: 29618
2006-08-11 17:56:38 +00:00
a2f4086828
Change one ReplaceAllUsesWith method to take an array of operands to replace
...
instead of a vector of operands.
llvm-svn: 29616
2006-08-11 17:46:28 +00:00
c24a1d3093
Start eliminating temporary vectors used to create DAG nodes. Instead, pass
...
in the start of an array and a count of operands where applicable. In many
cases, the number of operands is known, so this static array can be allocated
on the stack, avoiding the heap. In many other cases, a SmallVector can be
used, which has the same benefit in the common cases.
I updated a lot of code calling getNode that takes a vector, but ran out of
time. The rest of the code should be updated, and these methods should be
removed.
We should also do the same thing to eliminate the methods that take a
vector of MVT::ValueTypes.
It would be extra nice to convert the dagiselemitter to avoid creating vectors
for operands when calling getTargetNode.
llvm-svn: 29566
2006-08-08 02:23:42 +00:00
97af9d5d3a
Eliminate some malloc traffic by allocating vectors on the stack. Change some
...
method that took std::vector<SDOperand> to take a pointer to a first operand
and #operands.
This speeds up isel on kc++ by about 3%.
llvm-svn: 29561
2006-08-08 01:09:31 +00:00
1ee75ce65d
Revamp the "CSEMap" datastructure used in the SelectionDAG class. This
...
eliminates a bunch of std::map's in the SelectionDAG, replacing them with a
home-grown hashtable.
This is still a work in progress: not all the maps have been moved over and the
hashtable never resizes. That said, this still speeds up llc 20% on kimwitu++
with -fast -regalloc=local using a release build.
llvm-svn: 29550
2006-08-07 23:03:03 +00:00
445b91a041
Clear TopOrder before assigning topological order. Some clean ups.
...
llvm-svn: 29546
2006-08-07 22:13:29 +00:00
1640ae5a84
Reverse the FlaggedNodes after scanning up for flagged preds or else the order would be reversed.
...
llvm-svn: 29545
2006-08-07 22:12:12 +00:00
8927c875bb
Make SelectionDAG::RemoveDeadNodes iterative instead of recursive, which
...
also make it simpler.
llvm-svn: 29524
2006-08-04 17:45:20 +00:00
a5b707e3ad
Copy the liveins for the first block. PR859
...
llvm-svn: 29511
2006-08-03 20:51:06 +00:00
524c1a21f2
Work around a GCC 3.3.5 bug noticed by a user.
...
llvm-svn: 29490
2006-08-03 00:18:59 +00:00
6efe304ec8
Work around a bug in gcc 3.3.5, reported by a user
...
llvm-svn: 29489
2006-08-03 00:16:56 +00:00
bba1ebda32
- Change AssignTopologicalOrder to return vector of SDNode* by reference.
...
- Tweak implementation to avoid using std::map.
llvm-svn: 29479
2006-08-02 22:00:34 +00:00
29e635d3c9
Final polish on machine pass registries.
...
llvm-svn: 29471
2006-08-02 12:30:23 +00:00
17c67efe8a
Now that the ISel is available, it's possible to create a default instruction
...
scheduler creator.
llvm-svn: 29452
2006-08-01 19:14:14 +00:00
03593f72db
1. Change use of "Cache" to "Default".
...
2. Added argument to instruction scheduler creators so the creators can do
special things.
3. Repaired target hazard code.
4. Misc.
More to follow.
llvm-svn: 29450
2006-08-01 18:29:48 +00:00
0ec39ee28e
Forgot the added files for plugable machine passes.
...
llvm-svn: 29436
2006-08-01 16:31:08 +00:00
95eda5b1f3
Introducing plugable register allocators and instruction schedulers.
...
llvm-svn: 29434
2006-08-01 14:21:23 +00:00
9631a60020
Added AssignTopologicalOrder() to assign each node an unique id based on their topological order.
...
llvm-svn: 29431
2006-08-01 08:20:41 +00:00
6ae6ac1216
PIC jump table entries are always 32-bit even in 64-bit mode.
...
llvm-svn: 29422
2006-08-01 01:03:13 +00:00
85492427f2
Instead of blindly looking past constantexpr casts, actually constant
...
fold them. This correctly truncates constants that are too large for the
destination slot and makes the code easier to understand. This fixes PR853
and Regression/CodeGen/X86/2006-07-28-AsmPrint-Long-As-Pointer.ll
llvm-svn: 29408
2006-07-29 01:57:19 +00:00
b572401bea
Remove InFlightSet hack. No longer needed.
...
llvm-svn: 29373
2006-07-28 00:47:19 +00:00
3390cbed2c
Print empty inline asms as a blank line instead of:
...
# InlineAsm Start
# InlineAsm End
llvm-svn: 29372
2006-07-28 00:17:20 +00:00
d1a714e503
Working toward registration of register allocators.
...
llvm-svn: 29360
2006-07-27 20:05:00 +00:00
efc312a5c7
Code cleanups, per review
...
llvm-svn: 29347
2006-07-27 16:46:58 +00:00
acb606ff33
AssignNodeIds should return unsigned.
...
llvm-svn: 29343
2006-07-27 07:36:47 +00:00
29eefc164c
AssignNodeIds assign each node in the DAG an unique id.
...
llvm-svn: 29337
2006-07-27 06:39:06 +00:00
85ea83e821
Add some advice
...
llvm-svn: 29324
2006-07-27 04:24:14 +00:00
787565024a
Support jump tables when in PIC relocation model
...
llvm-svn: 29318
2006-07-27 01:13:04 +00:00
4488f0c303
Fix a case where LegalizeAllNodesNotLeadingTo could take exponential time.
...
This manifested itself as really long time to compile
Regression/CodeGen/Generic/2003-05-28-ManyArgs.ll on ppc.
This is PR847.
llvm-svn: 29313
2006-07-26 23:55:56 +00:00
421475cd3b
For PR780:
...
1. Move IncludeFile.h to System library
2. Move IncludeFile.cpp to System library
3. #1 and #2 required to prevent cyclic library dependencies for libSystem
4. Convert all existing uses of Support/IncludeFile.h to System/IncludeFile.h
5. Add IncludeFile support to various lib/System classes.
6. Add new lib/System classes to LinkAllVMCore.h
All this in an attempt to pull in lib/System to what's required for VMCore
llvm-svn: 29287
2006-07-26 16:18:00 +00:00
658b9476f0
Initialize some variables the compiler warns about.
...
llvm-svn: 29277
2006-07-25 20:44:41 +00:00
4b49c23571
Eliminate data relocations by using NULL instead of global empty list.
...
llvm-svn: 29250
2006-07-21 21:15:20 +00:00
4e153f1b91
Use an enumeration to eliminate data relocations.
...
llvm-svn: 29249
2006-07-21 20:57:35 +00:00
7c970b98d0
If a shuffle is a splat, check if the argument is a build_vector with all elements being the same. If so, return the argument.
...
llvm-svn: 29242
2006-07-21 08:25:53 +00:00
55782c6c41
Build more debugger/selectiondag libraries as archives instead of .o files.
...
This works around bugs in some versions of the cygwin linker.
Patch contributed by Anton Korobeynikov.
llvm-svn: 29239
2006-07-21 00:10:47 +00:00
8472e0c4af
If a shuffle is unary, i.e. one of the vector argument is not needed, turn the
...
operand into a undef and adjust mask accordingly.
llvm-svn: 29232
2006-07-20 22:44:41 +00:00
b030532910
Mems can be in the output list also. This is the second half of a fix for
...
PR833
llvm-svn: 29224
2006-07-20 19:02:21 +00:00
ec104a2b41
80 cols
...
llvm-svn: 29221
2006-07-20 17:43:27 +00:00
c496b418b5
Reduce number of exported symbols
...
llvm-svn: 29220
2006-07-20 17:28:38 +00:00
2b0baddc33
Fix linking on Alpha
...
llvm-svn: 29219
2006-07-20 17:27:58 +00:00
4238ca55ef
Move MVT::getVectorType out of line, it is large and shouldn't be inlined.
...
llvm-svn: 29195
2006-07-19 00:40:45 +00:00
c0973edc69
Add an out-of-line virtual method for the sdnode class to give it a home.
...
llvm-svn: 29192
2006-07-19 00:00:37 +00:00
fd5a8ebb74
On 64-bit targets like ppc64, we should use .quad to output pointer directives,
...
not .long.
llvm-svn: 29157
2006-07-15 01:34:12 +00:00
436c2dd927
Add an out-of-line virtual function to home class.
...
llvm-svn: 29154
2006-07-14 23:08:47 +00:00
194bef7ff4
Fixed a bug handling void function types.
...
Requires rebuild of llvm-gcc4 (touch llvm-debug.cpp.)
llvm-svn: 29131
2006-07-13 15:27:42 +00:00
f7300b2706
It was pointed out that DEBUG() is only available with -debug.
...
llvm-svn: 29106
2006-07-11 18:25:13 +00:00
c3d341ea98
Ensure that dump calls that are associated with asserts are removed from
...
non-debug build.
llvm-svn: 29105
2006-07-11 17:58:07 +00:00
6c72aa7411
1. Support for c++ mangled names.
...
2. Support for private/protected class members.
llvm-svn: 29104
2006-07-11 15:58:09 +00:00
1b8ea1f5ba
Fix CodeGen/Alpha/2006-07-03-ASMFormalLowering.ll and PR818.
...
llvm-svn: 29099
2006-07-11 01:40:09 +00:00
d19938834b
Ugly hack! Add helper functions InsertInFlightSetEntry and
...
RemoveInFlightSetEntry. They are used in place of direct set operators to
reduce instruction selection function stack size.
llvm-svn: 28987
2006-06-29 23:57:05 +00:00
ec1d60bd98
Add support to print 4-, 8-, and 16- byte constant literals in special
...
sections. e.g. On Darwin that would be .literal4 and .literal8.
llvm-svn: 28977
2006-06-29 00:26:09 +00:00
996795b0dd
Use hidden visibility to make symbols in an anonymous namespace get
...
dropped. This shrinks libllvmgcc.dylib another 67K
llvm-svn: 28975
2006-06-28 23:17:24 +00:00
e097e6f7c7
Shave another 27K off libllvmgcc.dylib with visibility hidden
...
llvm-svn: 28973
2006-06-28 22:17:39 +00:00
54a34cd20b
Mark these two classes as hidden, shrinking libllbmgcc.dylib by 25K
...
llvm-svn: 28970
2006-06-28 21:58:30 +00:00
710b3d5ea1
Fix CodeGen/Generic/2006-06-28-SimplifySetCCCrash.ll
...
llvm-svn: 28965
2006-06-28 18:29:47 +00:00
ee7eaa25cf
For PR801:
...
Refactor the Graph writing code to use a common implementation which is
now in lib/Support/GraphWriter.cpp. This completes the PR.
Patch by Anton Korobeynikov. Thanks, Anton!
llvm-svn: 28925
2006-06-27 16:49:46 +00:00
a7b2bd5997
Add and sort "sections" in debug lines. This always stepping through
...
code in sections other than ".text", including weak sections like ctors and
dtors.
llvm-svn: 28909
2006-06-23 12:51:53 +00:00
0a9e837b6f
Add support for function types.
...
llvm-svn: 28874
2006-06-20 19:41:06 +00:00
2837e3204f
References need to be section relative.
...
llvm-svn: 28861
2006-06-19 19:49:42 +00:00
f32058a2b7
References need to be section relative.
...
llvm-svn: 28858
2006-06-19 15:48:00 +00:00
90cd68acc6
Handle versioning of compile unit.
...
llvm-svn: 28855
2006-06-19 12:54:15 +00:00
b2ff2d481e
1. Revise vector debug support.
...
2. Update docs for vector debug support and new version control.
3. Simplify serialization of DebugDescInfo subclasses.
llvm-svn: 28816
2006-06-16 13:14:03 +00:00
4ff6c1646f
Teach the local allocator to know that live-in values (e.g. arguments) are
...
live at function entry. This prevents it from using arg registers for other
purposes before the arguments are used.
llvm-svn: 28809
2006-06-15 22:21:53 +00:00
19f964e048
1. Support standard dwarf format (was bootstrapping in Apple format.)
...
2. Add vector support.
llvm-svn: 28807
2006-06-15 20:51:43 +00:00
3519b87758
Was pointed out that structure alignment and type alignment are not the same
...
thing. Doubles still need to be special cased.
llvm-svn: 28806
2006-06-15 19:37:14 +00:00
dce07568f2
Alignment of globals has not been quite right. Needed to drop the pointer type
...
to get the alignment of the element type.
llvm-svn: 28799
2006-06-15 13:10:58 +00:00
ef9e07d3f0
Consistency. EXTRACT_ELEMENT index operand should have ptr type.
...
llvm-svn: 28795
2006-06-15 08:11:54 +00:00
df63179d95
Assert. Rather than silently stop printing.
...
llvm-svn: 28794
2006-06-15 08:10:56 +00:00
55772ccfd6
Instructions with variable operands (variable_ops) can have a number required
...
operands. e.g.
def CALL32r : I<0xFF, MRM2r, (ops GR32:$dst, variable_ops),
"call {*}$dst", [(X86call GR32:$dst)]>;
TableGen should emit operand informations for the "required" operands.
Added a target instruction info flag M_VARIABLE_OPS to indicate the target
instruction may have more operands in addition to the minimum required
operands.
llvm-svn: 28791
2006-06-15 07:22:16 +00:00
f0a7a1a117
Change versioning to per debug info descriptor (merged with tag.)
...
llvm-svn: 28782
2006-06-14 14:45:39 +00:00
f67bec0579
Place dwarf headers at earliest possible point. Well behaved when skipping
...
functions.
llvm-svn: 28781
2006-06-14 11:35:03 +00:00
32d92e004d
Make sure to update the CFG correctly if a switch only has a default dest.
...
This fixes CodeGen/Generic/2006-06-12-LowerSwitchCrash.ll
llvm-svn: 28755
2006-06-12 18:25:29 +00:00
0e57b2cb92
Start on my todo list
...
llvm-svn: 28752
2006-06-12 16:07:18 +00:00
c03a9259c0
Fix X86/inline-asm.ll:test2, a case where an input value was implicitly
...
truncated.
llvm-svn: 28733
2006-06-08 18:27:11 +00:00
705948d742
Fix Regression/CodeGen/X86/inline-asm.ll, a case where inline asm causes
...
implement extension of a register.
llvm-svn: 28731
2006-06-08 18:22:48 +00:00
8f8b5e4631
Fix an assert-on-inline-inline-asm bug.
...
llvm-svn: 28727
2006-06-08 18:00:47 +00:00
614cb2ff82
For PR798:
...
Provide GraphViz support for MingW32. Patch provided by Anton Korobeynikov
llvm-svn: 28688
2006-06-05 16:26:06 +00:00
7c77323e1d
For PR798:
...
Add support for Graphviz. Patch contributed by Anton Korobeynikov.
llvm-svn: 28684
2006-06-05 15:44:46 +00:00
cd8f67a106
Prevent the -pedantic option from causing Mac OS/X build problems:
...
LiveIntervalAnalysis.cpp:218: error: floating constant exceeds range of 'double'
llvm-svn: 28620
2006-06-01 06:12:21 +00:00
a647c7ff42
Use archive libraries instead of object files for VMCore, BCReader,
...
BCWriter, and bzip2 libraries. Adjust the various makefiles to accommodate
these changes. This was done to speed up link times.
llvm-svn: 28610
2006-06-01 01:30:27 +00:00
0c0996a97b
commuteInstruction() does not always create a new MI!
...
llvm-svn: 28592
2006-05-31 18:03:39 +00:00
9d91caa053
Eliminate a memory leak.
...
llvm-svn: 28585
2006-05-31 07:13:03 +00:00
64d2846017
visitVBinOp: Can't fold divide by zero!
...
llvm-svn: 28584
2006-05-31 06:08:35 +00:00
d12c97d23a
Make sure the register pressure reduction schedulers work for non-uniform
...
latency targets, e.g. PPC32.
llvm-svn: 28561
2006-05-30 18:05:39 +00:00
61e9f0d680
When a priority_queue is empty, the behavior of top() operator is
...
non-deterministic. Returns NULL when it's empty!
llvm-svn: 28560
2006-05-30 18:04:34 +00:00
8f872d2091
Fix a nasty dag combiner bug that caused nondeterminstic crashes (MY FAVORITE!):
...
SimplifySelectOps would eliminate a Select, delete it, then return true.
The clients would see that it did something and return null.
The top level would see a null return, and decide that nothing happened,
proceeding to process the node in other ways: boom.
The fix is simple: clients of SimplifySelectOps should return the select
node itself.
In order to catch really obnoxious boogs like this in the future, add an
assert that nodes are not deleted. We do this by checking for a sentry node
type that the SDNode dtor sets when a node is destroyed.
llvm-svn: 28514
2006-05-27 00:43:02 +00:00
21dee4e0b2
Make CALL node consistent with RET node. Signness of value has type MVT::i32
...
instead of MVT::i1. Either is fine except MVT::i32 is probably a legal type
for most (if not all) platforms while MVT::i1 is not.
llvm-svn: 28511
2006-05-26 23:13:20 +00:00
a2e9953c54
Change RET node to include signness information of the return values. e.g.
...
RET chain, value1, sign1, value2, sign2
llvm-svn: 28509
2006-05-26 23:09:09 +00:00
0f5c7936e7
Remove a bogus cast.
...
llvm-svn: 28492
2006-05-26 08:00:14 +00:00
009f5f55f7
Turn on -sched-commute-nodes by default.
...
llvm-svn: 28465
2006-05-25 08:37:31 +00:00
4582771f3f
CALL node change: now including signness of every argument.
...
llvm-svn: 28461
2006-05-25 00:55:32 +00:00
aa2372562e
Patches to make the LLVM sources more -pedantic clean. Patch provided
...
by Anton Korobeynikov! This is a step towards closing PR786.
llvm-svn: 28447
2006-05-24 17:04:05 +00:00
ac4f66ff24
-enable-unsafe-fp-math implies -enable-finite-only-fp-math
...
llvm-svn: 28437
2006-05-23 18:18:46 +00:00
df1d439849
Fix missing include
...
llvm-svn: 28435
2006-05-23 13:43:15 +00:00
1c5b7d12df
Incorrect SETCC CondCode used for FP comparisons.
...
llvm-svn: 28433
2006-05-23 06:40:47 +00:00
d8e2f6ebc1
lib/Target/Target.td
...
llvm-svn: 28386
2006-05-18 20:42:07 +00:00
7949c2e8b2
Fix the result of the call to use a correct vbitconvert. There is no need to
...
use getPackedTypeBreakdown at all here.
llvm-svn: 28365
2006-05-17 20:49:36 +00:00
938155ca57
Correct a previous patch which broke CodeGen/PowerPC/vec_call.ll
...
llvm-svn: 28364
2006-05-17 20:43:21 +00:00
751cd7653d
Fixed a LowerCallTo and LowerArguments bug. They were introducing illegal
...
VBIT_VECTOR nodes. There were some confusion about the semantics of
getPackedTypeBreakdown(). e.g. for <4 x f32> it returns 1 and v4f32, not 4,
and f32.
llvm-svn: 28352
2006-05-17 18:16:39 +00:00
62f1b83c0e
When we legalize target nodes, do not use getNode to create a new node,
...
use UpdateNodeOperands to just update the operands! This is important because
getNode will allocate a new node if the node returns a flag and this breaks
assumptions in the legalizer that you can legalize some things multiple times
and get exactly the same results.
This latent bug was exposed by my ppc patch last night, and this fixes
gsm/toast.
llvm-svn: 28348
2006-05-17 18:00:08 +00:00
a1cec0106a
Add an assertion, avoid some unneeded work for each call. No functionality
...
change.
llvm-svn: 28347
2006-05-17 17:55:45 +00:00
b77ba73a29
Add support for calls that pass and return legal vectors.
...
llvm-svn: 28340
2006-05-16 23:39:44 +00:00
aaa23d953f
Add a new ISD::CALL node, make the default impl of TargetLowering::LowerCallTo
...
produce it.
llvm-svn: 28338
2006-05-16 22:53:20 +00:00
1dc9ec5874
Move this code to a common place
...
llvm-svn: 28329
2006-05-16 17:42:15 +00:00
3d82699605
Add a chain to FORMAL_ARGUMENTS. This is a minimal port of the X86 backend,
...
it doesn't currently use/maintain the chain properly. Also, make the
X86ISelLowering.cpp file 80-col clean.
llvm-svn: 28320
2006-05-16 06:45:34 +00:00
957cb6733a
Move function-live-in-handling code from the sdisel code to the scheduler.
...
This code should be emitted after legalize, so it can't be in sdisel.
Note that the EmitFunctionEntryCode hook should be updated to operate on the
DAG. The X86 backend is the only one currently using this hook.
llvm-svn: 28315
2006-05-16 06:10:58 +00:00
52d0c78de8
Print the vreg that livein physregs are live in
...
llvm-svn: 28314
2006-05-16 05:55:30 +00:00
5f0edfb849
Legalize FORMAL_ARGUMENTS nodes correctly, we don't want to legalize them once
...
for each argument.
llvm-svn: 28313
2006-05-16 05:49:56 +00:00
99f2f79e2f
Fixing 2006-05-01-SchedCausingSpills.ll; some clean up
...
llvm-svn: 28279
2006-05-13 08:22:24 +00:00
d1915cfa6f
Revert an un-intended change
...
llvm-svn: 28278
2006-05-13 05:53:47 +00:00
69a0ce6261
Merge identical code.
...
llvm-svn: 28274
2006-05-13 02:11:14 +00:00
a726fc6dbf
If the register allocator cannot find a register to spill, try the aliases. If
...
that still fails (because all the register spill weights are inf), just grab
one.
llvm-svn: 28262
2006-05-12 19:07:46 +00:00
53cdb2f2b0
Remove dead vars
...
llvm-svn: 28255
2006-05-12 18:06:45 +00:00
da076e41ab
remove dead vars
...
llvm-svn: 28254
2006-05-12 18:04:28 +00:00
fe211deedf
Remove dead variable
...
llvm-svn: 28253
2006-05-12 18:02:04 +00:00
afe72481f6
Comment out dead variables
...
llvm-svn: 28252
2006-05-12 17:57:54 +00:00
936cd3390d
Remove dead var
...
llvm-svn: 28250
2006-05-12 17:50:35 +00:00
8c02c3f41a
Compile:
...
%tmp152 = setgt uint %tmp144, %tmp149 ; <bool> [#uses=1]
%tmp159 = setlt uint %tmp144, %tmp149 ; <bool> [#uses=1]
%bothcond2 = or bool %tmp152, %tmp159 ; <bool> [#uses=1]
To setne, not setune, which causes an assertion fault.
llvm-svn: 28244
2006-05-12 17:03:46 +00:00
8c2c1e90c4
Refactor a bunch of includes so that TargetMachine.h doesn't have to include
...
TargetData.h. This should make recompiles a bit faster with my current
TargetData tinkering.
llvm-svn: 28238
2006-05-12 06:33:49 +00:00
6a6886185b
Backing out fix for PR770. Need to re-apply it after live range splitting is possible
...
llvm-svn: 28236
2006-05-12 06:06:34 +00:00
095c9d9b7f
Duh. That could take a long time.
...
llvm-svn: 28235
2006-05-12 06:05:18 +00:00
66adee93aa
Two simplifications for token factor nodes: simplify tf(x,x) -> x.
...
simplify tf(x,y,y,z) -> tf(x,y,z).
llvm-svn: 28233
2006-05-12 05:01:37 +00:00
afed73eebe
Add capability to scheduler to commute nodes for profit.
...
If a two-address code whose first operand has uses below, it should be commuted
when possible.
llvm-svn: 28230
2006-05-12 01:58:24 +00:00
d38c22bdd3
Refactor scheduler code. Move register-reduction list scheduler to a
...
separate file. Added an initial implementation of top-down register pressure
reduction list scheduler.
llvm-svn: 28226
2006-05-11 23:55:42 +00:00
47926aff96
Set weight of zero length intervals to infinite to prevent them from being
...
spilled.
llvm-svn: 28220
2006-05-11 07:29:24 +00:00
db6aa4896b
Backing out previous check-in.
...
llvm-svn: 28219
2006-05-11 07:28:16 +00:00
6ad040a6bc
If the live interval legnth is essentially zero, i.e. in every live range
...
the use follows def immediately, it doesn't make sense to spill it and
hope it will be easier to allocate for this LI.
llvm-svn: 28217
2006-05-10 22:30:41 +00:00
9665ba053f
Templatify RegReductionPriorityQueue
...
llvm-svn: 28212
2006-05-10 06:16:44 +00:00
1a225d23ae
Fix PR773
...
llvm-svn: 28207
2006-05-09 18:20:51 +00:00
f801792e08
Fix a regression in my patch from last night that broke the llvmgcc4 build on
...
ppc
llvm-svn: 28205
2006-05-09 16:41:59 +00:00
7d693898ee
Add pseudo dependency to force a def&use operand to be scheduled last (unless
...
the distance between the def and another use is much longer). This is under
option control for now "-sched-lower-defnuse".
llvm-svn: 28201
2006-05-09 07:13:34 +00:00
2c74848af1
Debugging info
...
llvm-svn: 28200
2006-05-09 06:55:15 +00:00
ae45020720
PR 770 - permit coallescing of registers in subset register classes.
...
llvm-svn: 28197
2006-05-09 06:37:48 +00:00
4ebc6a2311
Implement MASM sections correctly, without a "has masm sections flag" and a bunch of special case code.
...
llvm-svn: 28194
2006-05-09 05:33:48 +00:00
8c2bfc0659
Oh yeah, there are two of these now, unify both.
...
llvm-svn: 28192
2006-05-09 05:24:50 +00:00
6341df8069
Setting SwitchToSectionDirective properly in the MASM backend permits a bunch
...
of code to be unified.
llvm-svn: 28191
2006-05-09 05:23:12 +00:00
d36cc2b610
Don't prefix section directives with a tab. Doing so causes blank lines to
...
be emitted to the .s file.
llvm-svn: 28189
2006-05-09 05:19:59 +00:00
e64f764d25
Make the masm codepath work like the normal code path.
...
llvm-svn: 28188
2006-05-09 05:15:58 +00:00
c0f0dfa56f
The MASM asmprinter has been fixed, these hacks are no longer needed.
...
llvm-svn: 28186
2006-05-09 05:13:34 +00:00
8488ba2e41
Split SwitchSection into SwitchTo{Text|Data}Section methods.
...
llvm-svn: 28184
2006-05-09 04:59:56 +00:00
446e1ef26a
Make the case I just checked in stronger. Now we compile this:
...
short test2(short X, short x) {
int Y = (short)(X+x);
return Y >> 1;
}
to:
_test2:
add r2, r3, r4
extsh r2, r2
srawi r3, r2, 1
blr
instead of:
_test2:
add r2, r3, r4
extsh r2, r2
srwi r2, r2, 1
extsh r3, r2
blr
llvm-svn: 28175
2006-05-08 21:18:59 +00:00
29062da0ac
Implement and_sext.ll:test3, generating:
...
_test4:
srawi r3, r3, 16
blr
instead of:
_test4:
srwi r2, r3, 16
extsh r3, r2
blr
for:
short test4(unsigned X) {
return (X >> 16);
}
llvm-svn: 28174
2006-05-08 20:59:41 +00:00
2935d8190c
Compile this:
...
short test4(unsigned X) {
return (X >> 16);
}
to:
_test4:
movl 4(%esp), %eax
sarl $16, %eax
ret
instead of:
_test4:
movl $-65536, %eax
andl 4(%esp), %eax
sarl $16, %eax
ret
llvm-svn: 28171
2006-05-08 20:51:54 +00:00
78da6792e7
Fold shifts with undef operands.
...
llvm-svn: 28167
2006-05-08 17:29:49 +00:00
d7a19102d1
Make emission of jump tables a bit less conservative; they are now required
...
to be only 31.25% dense, rather than 75% dense.
llvm-svn: 28165
2006-05-08 16:51:36 +00:00
e5ce5bb6da
Fix PR772
...
llvm-svn: 28161
2006-05-08 01:35:01 +00:00
7e7bcf3a54
Simplify some code, add a couple minor missed folds
...
llvm-svn: 28152
2006-05-06 23:06:26 +00:00
751817c54f
constant fold sign_extend_inreg
...
llvm-svn: 28151
2006-05-06 23:05:41 +00:00
2a4d7b845b
remove cases handled elsewhere
...
llvm-svn: 28150
2006-05-06 22:43:44 +00:00
ce9b9fe6eb
Fix some loose ends in MASM support.
...
llvm-svn: 28148
2006-05-06 21:27:14 +00:00
1ecb2a2dac
Use the new TargetLowering::ComputeNumSignBits method to eliminate
...
sign_extend_inreg operations. Though ComputeNumSignBits is still rudimentary,
this is enough to compile this:
short test(short X, short x) {
int Y = X+x;
return (Y >> 1);
}
short test2(short X, short x) {
int Y = (short)(X+x);
return Y >> 1;
}
into:
_test:
add r2, r3, r4
srawi r3, r2, 1
blr
_test2:
add r2, r3, r4
extsh r2, r2
srawi r3, r2, 1
blr
instead of:
_test:
add r2, r3, r4
srawi r2, r2, 1
extsh r3, r2
blr
_test2:
add r2, r3, r4
extsh r2, r2
srawi r2, r2, 1
extsh r3, r2
blr
llvm-svn: 28146
2006-05-06 09:30:03 +00:00
21cd99024a
When inserting casts, be careful of where we put them. We cannot insert
...
a cast immediately before a PHI node.
This fixes Regression/CodeGen/Generic/2006-05-06-GEP-Cast-Sink-Crash.ll
llvm-svn: 28143
2006-05-06 09:10:37 +00:00
907e392dba
Fold trunc(any_ext). This gives stuff like:
...
27,28c27
< movzwl %di, %edi
< movl %edi, %ebx
---
> movw %di, %bx
llvm-svn: 28137
2006-05-05 22:56:26 +00:00
57f8c5a387
Shrink shifts when possible.
...
llvm-svn: 28136
2006-05-05 22:53:17 +00:00
a633c31319
Indent multiline asm strings more nicely
...
llvm-svn: 28132
2006-05-05 21:47:05 +00:00
3d26577396
Fold (fpext (load x)) -> (extload x)
...
llvm-svn: 28130
2006-05-05 21:34:35 +00:00
3e3f2c63c3
More aggressively sink GEP offsets into loops. For example, before we
...
generated:
movl 8(%esp), %eax
movl %eax, %edx
addl $4316, %edx
cmpb $1, %cl
ja LBB1_2 #cond_false
LBB1_1: #cond_true
movl L_QuantizationTables720$non_lazy_ptr, %ecx
movl %ecx, (%edx)
movl L_QNOtoQuantTableShift720$non_lazy_ptr, %edx
movl %edx, 4460(%eax)
ret
...
Now we generate:
movl 8(%esp), %eax
cmpb $1, %cl
ja LBB1_2 #cond_false
LBB1_1: #cond_true
movl L_QuantizationTables720$non_lazy_ptr, %ecx
movl %ecx, 4316(%eax)
movl L_QNOtoQuantTableShift720$non_lazy_ptr, %ecx
movl %ecx, 4460(%eax)
ret
... which uses one fewer register.
llvm-svn: 28129
2006-05-05 21:17:49 +00:00
25a5283a86
Fold some common code.
...
llvm-svn: 28124
2006-05-05 06:32:04 +00:00
002ee91457
Implement:
...
// fold (and (sext x), (sext y)) -> (sext (and x, y))
// fold (or (sext x), (sext y)) -> (sext (or x, y))
// fold (xor (sext x), (sext y)) -> (sext (xor x, y))
// fold (and (aext x), (aext y)) -> (aext (and x, y))
// fold (or (aext x), (aext y)) -> (aext (or x, y))
// fold (xor (aext x), (aext y)) -> (aext (xor x, y))
llvm-svn: 28123
2006-05-05 06:31:05 +00:00
5ac4293606
Pull and through and/or/xor. This compiles some bitfield code to:
...
mov EAX, DWORD PTR [ESP + 4]
mov ECX, DWORD PTR [EAX]
mov EDX, ECX
add EDX, EDX
or EDX, ECX
and EDX, -2147483648
and ECX, 2147483647
or EDX, ECX
mov DWORD PTR [EAX], EDX
ret
instead of:
sub ESP, 4
mov DWORD PTR [ESP], ESI
mov EAX, DWORD PTR [ESP + 8]
mov ECX, DWORD PTR [EAX]
mov EDX, ECX
add EDX, EDX
mov ESI, ECX
and ESI, -2147483648
and EDX, -2147483648
or EDX, ESI
and ECX, 2147483647
or EDX, ECX
mov DWORD PTR [EAX], EDX
mov ESI, DWORD PTR [ESP]
add ESP, 4
ret
llvm-svn: 28122
2006-05-05 06:10:43 +00:00
812646aa0c
Implement a variety of simplifications for ANY_EXTEND.
...
llvm-svn: 28121
2006-05-05 05:58:59 +00:00
8d6fc20181
Factor some code, add these transformations:
...
// fold (and (trunc x), (trunc y)) -> (trunc (and x, y))
// fold (or (trunc x), (trunc y)) -> (trunc (or x, y))
// fold (xor (trunc x), (trunc y)) -> (trunc (xor x, y))
llvm-svn: 28120
2006-05-05 05:51:50 +00:00
78a7f0e05e
Fix VC++ compilation error.
...
llvm-svn: 28117
2006-05-05 01:47:05 +00:00
7a3ecf7993
Sink noop copies into the basic block that uses them. This reduces the number
...
of cross-block live ranges, and allows the bb-at-a-time selector to always
coallesce these away, at isel time.
This reduces the load on the coallescer and register allocator. For example
on a codec on X86, we went from:
1643 asm-printer - Number of machine instrs printed
419 liveintervals - Number of loads/stores folded into instructions
1144 liveintervals - Number of identity moves eliminated after coalescing
1022 liveintervals - Number of interval joins performed
282 liveintervals - Number of intervals after coalescing
1304 liveintervals - Number of original intervals
86 regalloc - Number of times we had to backtrack
1.90232 regalloc - Ratio of intervals processed over total intervals
40 spiller - Number of values reused
182 spiller - Number of loads added
121 spiller - Number of stores added
132 spiller - Number of register spills
6 twoaddressinstruction - Number of instructions commuted to coalesce
360 twoaddressinstruction - Number of two-address instructions
to:
1636 asm-printer - Number of machine instrs printed
403 liveintervals - Number of loads/stores folded into instructions
1155 liveintervals - Number of identity moves eliminated after coalescing
1033 liveintervals - Number of interval joins performed
279 liveintervals - Number of intervals after coalescing
1312 liveintervals - Number of original intervals
76 regalloc - Number of times we had to backtrack
1.88998 regalloc - Ratio of intervals processed over total intervals
1 spiller - Number of copies elided
41 spiller - Number of values reused
191 spiller - Number of loads added
114 spiller - Number of stores added
128 spiller - Number of register spills
4 twoaddressinstruction - Number of instructions commuted to coalesce
356 twoaddressinstruction - Number of two-address instructions
On this testcase, this change provides a modest reduction in spill code,
regalloc iterations, and total instructions emitted. It increases the number
of register coallesces.
llvm-svn: 28115
2006-05-05 01:04:50 +00:00
abdf4d569c
Final pass of minor cleanups for MachineInstr
...
llvm-svn: 28110
2006-05-04 19:36:09 +00:00
9add880566
Initial support for register pressure aware scheduling. The register reduction
...
scheduler can go into a "vertical mode" (i.e. traversing up the two-address
chain, etc.) when the register pressure is low.
This does seem to reduce the number of spills in the cases I've looked at. But
with x86, it's no guarantee the performance of the code improves.
It can be turned on with -sched-vertically option.
llvm-svn: 28108
2006-05-04 19:16:39 +00:00
53af9da363
Remove redundancy and a level of indirection when creating machine operands
...
llvm-svn: 28107
2006-05-04 19:14:44 +00:00
469647bf38
Remove and simplify some more machineinstr/machineoperand stuff.
...
llvm-svn: 28105
2006-05-04 18:16:01 +00:00
10b71c0d08
Rename MO_VirtualRegister -> MO_Register. Clean up immediate handling.
...
llvm-svn: 28104
2006-05-04 18:05:43 +00:00
10d6341618
Move some methods out of MachineInstr into MachineOperand
...
llvm-svn: 28102
2006-05-04 17:52:23 +00:00
fef7a2d0f5
There shalt be only one "immediate" operand type!
...
llvm-svn: 28099
2006-05-04 17:21:20 +00:00
15c52bda1d
Change "value" in MachineOperand to be a GlobalValue, as that is the only
...
thing that can be in it. Remove a dead method.
llvm-svn: 28098
2006-05-04 17:02:51 +00:00
ee64b6b40f
Remove a bunch more dead V9 specific stuff
...
llvm-svn: 28094
2006-05-04 01:26:39 +00:00
940cc978ef
Remove a bunch more SparcV9 specific stuff
...
llvm-svn: 28093
2006-05-04 01:15:02 +00:00
6e663f1c1e
Remove some more V9-specific stuff.
...
llvm-svn: 28092
2006-05-04 00:49:59 +00:00
9f6639b64d
Remove some more unused stuff from MachineInstr that was leftover from V9.
...
llvm-svn: 28091
2006-05-04 00:44:25 +00:00
1d8ee1fc80
Suck block address tracking out of targets into the JIT Emitter. This
...
simplifies the MachineCodeEmitter interface just a little bit and makes
BasicBlocks work like constant pools and jump tables.
llvm-svn: 28082
2006-05-03 17:10:41 +00:00
df4883971e
Finish up the initial jump table implementation by allowing jump tables to
...
not be 100% dense. Increase the minimum threshold for the number of cases
in a switch statement from 4 to 6 in order to create a jump table.
llvm-svn: 28079
2006-05-03 03:48:02 +00:00
ffef8b9412
Bottom up register pressure reduction work: clean up some hacks and enhanced
...
the heuristic to further reduce spills for several test cases. (Note, it may
not necessarily translate to runtime win!)
llvm-svn: 28076
2006-05-03 02:10:45 +00:00
20a631fde7
Refactor TargetMachine, pushing handling of TargetData into the target-specific subclasses. This has one caller-visible change: getTargetData() now returns a pointer instead of a reference.
...
This fixes PR 759.
llvm-svn: 28074
2006-05-03 01:29:57 +00:00
d8b192ba3b
Change the BasicBlockAddrs map to be a vector, indexed by MBB number.
...
llvm-svn: 28069
2006-05-03 00:32:55 +00:00
b8065a9a3a
Several related changes:
...
1. Change several methods in the MachineCodeEmitter class to be pure virtual.
2. Suck emitConstantPool/initJumpTableInfo into startFunction, removing them
from the MachineCodeEmitter interface, and reducing the amount of target-
specific code.
3. Change the JITEmitter so that it allocates constantpools and jump tables
*right* next to the functions that they belong to, instead of in a separate
pool of memory. This makes all memory for a function be contiguous, and
means the JITEmitter only tracks one block of memory now.
llvm-svn: 28065
2006-05-02 23:22:24 +00:00
23621fe8f4
Do not make the JIT memory manager manage the memory for globals. Instead
...
just have the JIT malloc them.
llvm-svn: 28062
2006-05-02 21:57:51 +00:00
c9aa3715e8
Refactor the machine code emitter interface to pull the pointers for the current
...
code emission location into the base class, instead of being in the derived classes.
This change means that low-level methods like emitByte/emitWord now are no longer
virtual (yaay for speed), and we now have a framework to support growable code
segments. This implements feature request #1 of PR469.
llvm-svn: 28059
2006-05-02 18:27:26 +00:00
4971ba5f41
Print function number instead of name
...
llvm-svn: 28057
2006-05-02 17:36:46 +00:00
67a3aa2aaa
Remove dead method
...
llvm-svn: 28055
2006-05-02 17:20:28 +00:00
bb1c345ec6
Remove the debug machine code emitter. The "FilePrinterEmitter" is more
...
useful for debugging.
llvm-svn: 28051
2006-05-02 16:59:24 +00:00
b9d4f8324d
Extend printBasicBlockLabel a bit so that it can be used to print all
...
basic block labels, consolidating the code to do so in one place for each
target.
llvm-svn: 28050
2006-05-02 05:37:32 +00:00
470f431f44
De-virtualize SwitchSection.
...
llvm-svn: 28047
2006-05-02 03:58:45 +00:00
f34ddb1e0d
De-virtualize EmitZeroes.
...
llvm-svn: 28046
2006-05-02 03:46:13 +00:00
24a62a9bc1
Make Intel syntax mode friendlier to Microsoft ML assembler (still needs more work).
...
llvm-svn: 28044
2006-05-02 01:16:28 +00:00
fd0a5478a1
Fix a latent bug that my spiller patch last week exposed: we were leaving
...
instructions in the virtregfolded map that were deleted. Because they
were deleted, newly allocated instructions could end up at the same address,
magically finding themselves in the map. The solution is to remove entries
from the map when we delete the instructions.
llvm-svn: 28041
2006-05-01 22:03:24 +00:00
ab7dbe0cc9
When promoting a load to a reg-reg copy, where the load was a previous
...
instruction folded with spill code, make sure the remove the load from
the virt reg folded map.
llvm-svn: 28040
2006-05-01 21:17:10 +00:00
4dee67c2cd
Remove previous patch, which wasn't quite right.
...
llvm-svn: 28039
2006-05-01 21:16:03 +00:00
0d084fb9ca
Dis-favor stores more
...
llvm-svn: 28035
2006-05-01 09:20:44 +00:00
24e795496d
Bottom up register-pressure reduction scheduler now pushes store operations
...
up the schedule. This helps code that looks like this:
loads ...
computations (first set) ...
stores (first set) ...
loads
computations (seccond set) ...
stores (seccond set) ...
Without this change, the stores and computations are more likely to
interleave:
loads ...
loads ...
computations (first set) ...
computations (second set) ...
computations (first set) ...
stores (first set) ...
computations (second set) ...
stores (stores set) ...
This can increase the number of spills if we are unlucky.
llvm-svn: 28033
2006-05-01 09:14:40 +00:00
10ff7b27ce
Didn't mean ScheduleDAGList.cpp to make the last checkin.
...
llvm-svn: 28030
2006-05-01 08:56:34 +00:00
a656242690
Remove temp. option -spiller-check-liveout, it didn't cause any failure nor performance regressions.
...
llvm-svn: 28029
2006-05-01 08:54:57 +00:00
25f55ae74a
Format #APP lines a bit nicer
...
llvm-svn: 28026
2006-05-01 04:11:03 +00:00
f71f0f2e0b
Local spiller kills a store if the folded restore is turned into a copy.
...
But this is incorrect if the spilled value live range extends beyond the
current BB.
It is currently controlled by a temporary option -spiller-check-liveout.
llvm-svn: 28024
2006-04-30 08:41:47 +00:00
2b48a94413
Remove a bogus transformation. This fixes SingleSource/UnitTests/2006-01-23-InitializedBitField.c
...
with some changes I have to the new CFE.
llvm-svn: 28022
2006-04-28 23:33:20 +00:00
c5e8ce8b8c
Remove the temporary option: -no-isel-fold-inflight
...
llvm-svn: 28012
2006-04-28 18:54:11 +00:00
d43c5c6046
TargetLowering::LowerArguments should return a VBIT_CONVERT of
...
FORMAL_ARGUMENTS SDOperand in the return result vector.
llvm-svn: 28009
2006-04-28 05:25:15 +00:00
79c50d96c9
Mapping of physregs can make it so that the designated and input physregs are
...
the same. In this case, don't emit a noop copy.
llvm-svn: 28008
2006-04-28 04:43:18 +00:00
51ab4498e7
Added a temporary option -no-isel-fold-inflight to control whether a "inflight"
...
node can be folded.
llvm-svn: 28003
2006-04-28 02:09:19 +00:00
84e95d00b5
When we have a two-address instruction where the input cannot be clobbered
...
and is already available, instead of falling back to emitting a load, fall
back to emitting a reg-reg copy. This generates significantly better code
for some SSE testcases, as SSE has lots of two-address instructions and
none of them are read/modify/write. As one example, this change does:
pshufd %XMM5, XMMWORD PTR [%ESP + 84], 255
xorps %XMM2, %XMM5
cmpltps %XMM1, %XMM0
- movaps XMMWORD PTR [%ESP + 52], %XMM0
- movapd %XMM6, XMMWORD PTR [%ESP + 52]
+ movaps %XMM6, %XMM0
cmpltps %XMM6, XMMWORD PTR [%ESP + 68]
movapd XMMWORD PTR [%ESP + 52], %XMM6
movaps %XMM6, %XMM0
cmpltps %XMM6, XMMWORD PTR [%ESP + 36]
cmpltps %XMM3, %XMM0
- movaps XMMWORD PTR [%ESP + 20], %XMM0
- movapd %XMM7, XMMWORD PTR [%ESP + 20]
+ movaps %XMM7, %XMM0
cmpltps %XMM7, XMMWORD PTR [%ESP + 4]
movapd XMMWORD PTR [%ESP + 20], %XMM7
cmpltps %XMM4, %XMM0
... which is far better than a store followed by a load!
llvm-svn: 28001
2006-04-28 01:46:50 +00:00
3784f3c57c
Insert a VBIT_CONVERT between a FORMAL_ARGUMENT node and its vector uses
...
(VAND, VADD, etc.). Legalizer will assert otherwise.
llvm-svn: 27991
2006-04-27 08:29:42 +00:00
393d96a56c
Fix Regression/CodeGen/Generic/2006-04-26-SetCCAnd.ll and
...
PR748.
llvm-svn: 27987
2006-04-27 05:01:07 +00:00
9618df1190
Don't forget return void.
...
llvm-svn: 27974
2006-04-25 23:03:35 +00:00
866b4b4d45
Fix the updating of the machine CFG when a PHI node was in a successor of
...
the jump table's range check block. This re-enables 100% dense jump tables
by default on PPC & x86
llvm-svn: 27952
2006-04-23 06:26:20 +00:00
3e04bb482b
Code cleanup associated with jump tables, thanks to Chris for noticing
...
these.
llvm-svn: 27950
2006-04-22 23:52:35 +00:00
ecb1dafd3d
Turn of jump tables for a bit, there are still some issues to work out with
...
updating the machine CFG.
llvm-svn: 27949
2006-04-22 23:51:56 +00:00
4ca2ea5b43
JumpTable support! What this represents is working asm and jit support for
...
x86 and ppc for 100% dense switch statements when relocations are non-PIC.
This support will be extended and enhanced in the coming days to support
PIC, and less dense forms of jump tables.
llvm-svn: 27947
2006-04-22 18:53:45 +00:00
b21d3bfd1f
The BFS scheduler is apparently nondeterminstic (causes many llvmgcc bootstrap
...
miscompares). Switch RISC targets to use the list-td scheduler, which isn't.
llvm-svn: 27933
2006-04-21 17:16:16 +00:00
662e940f73
Fix a couple more memory issues
...
llvm-svn: 27930
2006-04-21 15:32:26 +00:00
cc47ab3305
Fix a really subtle and obnoxious memory bug that caused issues with an
...
llvm-gcc4 boostrap. Whenever a node is deleted by the dag combiner, it
*must* be returned by the visit function, or the dag combiner will not
know that the node has been processed (and will, e.g., send it to the
target dag combine xforms).
llvm-svn: 27922
2006-04-20 23:55:59 +00:00
dcc1f995eb
This field no longer exists
...
llvm-svn: 27899
2006-04-20 18:32:41 +00:00
a38c3580bd
Remove some of the obvious V9-specific cruft
...
llvm-svn: 27893
2006-04-20 18:08:53 +00:00
a320abc494
Turn a VAND into a VECTOR_SHUFFLE is applicable.
...
DAG combiner can turn a VAND V, <-1, 0, -1, -1>, i.e. vector clear elements,
into a vector shuffle with a zero vector. It only does so when TLI tells it
the xform is profitable.
llvm-svn: 27874
2006-04-20 08:56:16 +00:00
Chris Lattner