6a124a84dc
[mips] Do not tail-call optimize vararg functions or functions with byval
...
arguments.
This is rather conservative and should be fixed later to be more aggressive.
llvm-svn: 166851
2012-10-27 00:56:56 +00:00
2c07f1f140
[mips] Make sure FuncArg doesn't advance when OrigArgIndex is the same as in the
...
previous iteration.
llvm-svn: 166850
2012-10-27 00:44:39 +00:00
ac8c669985
Use the methods and classes that were added to simplify LowerCall and
...
LowerFormalArguments in MipsTargetLowering.
No functionality change intended.
llvm-svn: 166846
2012-10-27 00:29:43 +00:00
2a13402a66
Add method MipsTargetLowering::writeVarArgRegs which copies argument registers
...
of vararg functions back to the stack.
llvm-svn: 166844
2012-10-27 00:21:13 +00:00
35f55b1622
Add method MipsTargetLowering::passByValArg.
...
This method emits nodes for passing byval arguments in registers and stack.
This has the same functionality as existing functions PassByValArg64 and
WriteByValArg which will be deleted later.
llvm-svn: 166843
2012-10-27 00:16:36 +00:00
25dad19f0e
Add method MipsTargetLowering::copyByValRegs.
...
This method copies byval arguments passed in registers onto the stack and has
the same functionality as existing functions CopyMips64ByValRegs and
ReadByValArg which will be deleted later.
llvm-svn: 166841
2012-10-27 00:10:18 +00:00
4a3711d077
Add class MipsCC which provides methods used to analyze formal and call
...
arguments and inquire about calling convention information.
llvm-svn: 166840
2012-10-26 23:56:38 +00:00
e485c65642
Delete MipsFunctionInfo::InArgFIRange.
...
llvm-svn: 166837
2012-10-26 23:49:51 +00:00
868b3a333b
[mips] Make sure sret argument is returned in register V0.
...
llvm-svn: 166539
2012-10-24 02:10:54 +00:00
0c7d131a7b
[mips] Use 64-bit registers to return an sret pointer if target ABI is N64.
...
llvm-svn: 166344
2012-10-19 22:11:40 +00:00
90131ac26c
[mips] Add code to do tail call optimization.
...
Currently, it is enabled only if option "enable-mips-tail-calls" is given and
all of the callee's arguments are passed in registers.
llvm-svn: 166342
2012-10-19 21:47:33 +00:00
c046243488
[mips] Delete MipsFunctionInfo::MaxCallFrameSize which is no longer used.
...
llvm-svn: 166339
2012-10-19 21:18:38 +00:00
91318df0cc
Add node and enum for mips tail call.
...
llvm-svn: 166318
2012-10-19 20:59:39 +00:00
9c8dcfc73a
Implement MipsTargetLowering::CanLowerReturn.
...
Patch by Sasa Stankovic.
llvm-svn: 165585
2012-10-10 01:27:09 +00:00
240322140e
Patch for integer multiply, signed/unsigned, long/long long.
...
llvm-svn: 165322
2012-10-05 18:27:54 +00:00
e4bd054f98
MIPS DSP: Branch on Greater Than or Equal To Value 32 in DSPControl Pos Field instruction.
...
llvm-svn: 164751
2012-09-27 02:15:57 +00:00
9061a46443
MIPS DSP: all the remaining instructions which read or write accumulators.
...
llvm-svn: 164750
2012-09-27 02:11:20 +00:00
1babeaa44c
MIPS DSP: add support for extract-word instructions.
...
llvm-svn: 164749
2012-09-27 02:05:42 +00:00
fabb8cf421
Add MIPS DSP register classes. Set actions of DSP vector operations and override
...
TargetLowering's callback functions.
llvm-svn: 164431
2012-09-21 23:58:31 +00:00
233ac53a3f
SelectionDAG node enums for MIPS DSP nodes.
...
llvm-svn: 164430
2012-09-21 23:52:47 +00:00
189d0adde9
Handled unaligned load/stores properly in Mips16
...
Patch by Reed Kotler.
llvm-svn: 163956
2012-09-15 01:02:03 +00:00
92a96e1da4
Misc.
...
1. Remove RA from list of allocatable registers
2. Enable d,y,r constraint inline assembly instructions
Patch by Reed Kotler.
llvm-svn: 163753
2012-09-12 23:27:55 +00:00
abb87d4857
Fix PR11985
...
- BlockAddress has no support of BA + offset form and there is no way to
propagate that offset into machine operand;
- Add BA + offset support and a new interface 'getTargetBlockAddress' to
simplify target block address forming;
- All targets are modified to use new interface and X86 backend is enhanced to
support BA + offset addressing.
llvm-svn: 163743
2012-09-12 21:43:09 +00:00
ad06cee239
Stop casting away const qualifier needlessly.
...
llvm-svn: 163258
2012-09-05 22:26:57 +00:00
ad4950258b
Add register Mips::GP to the list of reserved registers if target is bare-metal
...
to prevent it from being clobbered. mips uses $gp to access small data section.
This bug was originally reported by Carl Norum.
llvm-svn: 162340
2012-08-22 03:18:13 +00:00
33a25af5a8
Expand DYNAMIC_STACKALLOC nodes rather than doing custom-lowering.
...
The frame object which points to the dynamically allocated area will not be
needed after changes are made to cease reserving call frames.
llvm-svn: 161076
2012-07-31 20:54:48 +00:00
beda2241a4
When store nodes or memcpy nodes are created to copy the function call
...
arguments to the stack in MipsISelLowering::LowerCall, use stack pointer and
integer offset operands rather than frame object operands.
llvm-svn: 161068
2012-07-31 18:46:41 +00:00
4ce7c4060d
Fix type of LUXC1 and SUXC1. These instructions were incorrectly defined as
...
single-precision load and store.
Also avoid selecting LUXC1 and SUXC1 instructions during isel. It is incorrect
to map unaligned floating point load/store nodes to these instructions.
llvm-svn: 161063
2012-07-31 18:16:49 +00:00
97ba7696f8
Pass the correct call frame size to callseq_start node. This is needed to
...
replace uses of function getMaxCallFrameSize defined in MipsFunctionInfo with
the one MachineFrameInfo has.
llvm-svn: 160841
2012-07-26 23:27:01 +00:00
64626fc20f
Fix call setup for PIC.
...
Patch by Reed Kotler.
llvm-svn: 160774
2012-07-26 02:24:43 +00:00
26e9ecb7a3
Add basic ability to setup call frame, and make procedure calls.
...
Hello world will compile and execute with this patch.
Patch by Reed Kotler.
llvm-svn: 160651
2012-07-23 23:45:54 +00:00
b49c68a65d
Revert accidental commit.
...
llvm-svn: 160598
2012-07-21 02:20:33 +00:00
f73e362758
Add VK_Mips_HIGHER and VK_Mips_HIGHEST to MCSymbolRefExpr::VariantKind.
...
Test case will be added later when long branch patch is checked in.
llvm-svn: 160597
2012-07-21 02:15:19 +00:00
24cf4e36e5
Implement MipsTargetLowering::LowerSELECT_CC to custom lower SELECT_CC.
...
llvm-svn: 160064
2012-07-11 19:32:27 +00:00
878ad8b28d
Lower RETURNADDR node in Mips backend.
...
Patch by Sasa Stankovic.
llvm-svn: 160031
2012-07-11 00:53:32 +00:00
efff7b763b
Make register Mips::RA allocatable if not in mips16 mode.
...
llvm-svn: 159971
2012-07-10 00:19:06 +00:00
b353094f27
mips32 long long register inline asm constraint support.
...
inlineasm-cnstrnt-bad-r-1.ll is NOT supposed to fail, so it was removed. This resulted in the removal of a negative test (inlineasm-cnstrnt-bad-r-1.ll)
llvm-svn: 159625
2012-07-02 23:35:23 +00:00
dfc3e68c40
Revert " mips32 long long register inline asm constraint support." as
...
it appears to be breaking the bots.
This reverts commit 1b055ce320fa13f6f1ac81670d11b45e01f79876.
llvm-svn: 159619
2012-07-02 23:22:25 +00:00
5c1a01a625
mips32 long long register inline asm constraint support.
...
inlineasm-cnstrnt-bad-r-1.ll is NOT supposed to fail, so it was removed. This resulted in the removal of a negative test (inlineasm-cnstrnt-bad-r-1.ll)
llvm-svn: 159610
2012-07-02 22:39:45 +00:00
5fd22485a3
Fix coding style violations. Remove white spaces and tabs.
...
llvm-svn: 158471
2012-06-14 21:10:56 +00:00
df5205ef3d
Implement a DAGCombine in MipsISelLowering.cpp which transforms the following
...
pattern:
(add v0, (add v1, abs_lo(tjt))) => (add (add v0, v1), abs_lo(tjt))
"tjt" is a TargetJumpTable node.
llvm-svn: 158419
2012-06-13 20:33:18 +00:00
1daf8c2a16
Set a higher value for maxStoresPerMemcpy in MipsISelLowering.cpp.
...
llvm-svn: 158414
2012-06-13 19:33:32 +00:00
9586618c58
Simplify CreateLoadLR and CreateStoreLR in MipsISelLowering.cpp.
...
llvm-svn: 158413
2012-06-13 19:06:08 +00:00
f0273603f5
Implement fastcc calling convention for MIPS.
...
llvm-svn: 158410
2012-06-13 18:06:00 +00:00
6734685f21
Fix a bug in MipsTargetLowering::LowerLOAD. A shift-right-logical node is
...
inserted after the shift-left-logical node.
llvm-svn: 157937
2012-06-04 17:46:29 +00:00
245917b536
MIPS TLS: use the model selected by TargetMachine::getTLSModel().
...
This was mostly done already in r156162, but I missed one place.
llvm-svn: 157929
2012-06-04 14:02:08 +00:00
58268c23ac
remove an unused variable.
...
llvm-svn: 157872
2012-06-02 01:03:42 +00:00
019e592f75
Set operation actions for load/store nodes in the Mips backend.
...
llvm-svn: 157866
2012-06-02 00:04:42 +00:00
8f1db778a4
Define functions MipsTargetLowering::LowerLOAD and LowerSTORE which
...
custom-lower unaligned load and store nodes.
llvm-svn: 157864
2012-06-02 00:03:49 +00:00
b9ebf8d644
Define Mips specific unaligned load/store nodes.
...
llvm-svn: 157863
2012-06-02 00:03:12 +00:00
4e76bf8282
Expand unaligned i16 loads/stores for the Mips backend.
...
This is the first of a series of patches which make changes to the backend to
emit unaligned load/store instructions (lwl,lwr,swl,swr) during instruction
selection.
llvm-svn: 157862
2012-06-02 00:02:45 +00:00
bff8e31d3c
Cleanup and factoring of mips16 tablegen classes. Make register classes
...
CPU16RegsRegClass and CPURARegRegClass available. Add definition of mips16
jalr instruction.
Patch by Reed Kotler.
llvm-svn: 157730
2012-05-31 02:59:44 +00:00
aa58397b3c
Change interface for TargetLowering::LowerCallTo and TargetLowering::LowerCall
...
to pass around a struct instead of a large set of individual values. This
cleans up the interface and allows more information to be added to the struct
for future targets without requiring changes to each and every target.
NV_CONTRIB
llvm-svn: 157479
2012-05-25 16:35:28 +00:00
f542ebd958
Make the following changes in MipsISelLowering.cpp:
...
- Stop creating stack frame objects needed for saving $gp.
- Insert a node that copies the global pointer register to register $gp
before the call node. This will ensure $gp is valid at the entry of the
called function.
llvm-svn: 156692
2012-05-12 03:19:04 +00:00
0a8ab718cb
Expand 64-bit shifts if target ABI is O32.
...
llvm-svn: 156457
2012-05-09 00:55:21 +00:00
0d8c15d20f
Add support for the 'x' constraint.
...
Patch by Jack Carter.
llvm-svn: 156295
2012-05-07 06:25:19 +00:00
9c492e6ebf
Add support for the 'l' constraint.
...
Patch by Jack Carter.
llvm-svn: 156294
2012-05-07 06:25:15 +00:00
e3c494de82
Add support for the 'c' constraint.
...
Patch by Jack Carter.
llvm-svn: 156293
2012-05-07 06:25:10 +00:00
c18ae4a3b1
Add support for the 'P' constraint.
...
Patch by Jack Carter.
llvm-svn: 156292
2012-05-07 06:25:02 +00:00
470578a91b
Add support for the 'O' constraint.
...
Patch by Jack Carter.
llvm-svn: 156285
2012-05-07 05:46:48 +00:00
e07aa430b8
Add support for the 'N' inline asm constraint.
...
Patch by Jack Carter.
llvm-svn: 156284
2012-05-07 05:46:43 +00:00
1109b3406d
Add support for the 'L' inline asm constraint.
...
Patch by Jack Carter.
llvm-svn: 156283
2012-05-07 05:46:37 +00:00
3ff88a05b7
Add support for the inline asm constraint 'K'.
...
llvm-svn: 156282
2012-05-07 05:46:29 +00:00
7201e1b4b9
Support the 'J' constraint.
...
Patch by Jack Carter.
llvm-svn: 156280
2012-05-07 03:13:42 +00:00
1d6c89eea1
Add support for the 'I' inline asm constraint. Also add tests
...
from the previous 2 patches.
Patch by Jack Carter.
llvm-svn: 156279
2012-05-07 03:13:32 +00:00
58daf04681
Allow 64 bit integer values in gpu registers if arch and abi are 64 bit.
...
Patch by Jack Carter.
llvm-svn: 156278
2012-05-07 03:13:22 +00:00
cfcd77b0bc
When using inline asm constraints representing
...
non-floating point general registers allow 8 and 16-bit
elements.
Patch by Jack Carter.
llvm-svn: 156277
2012-05-07 03:13:16 +00:00
aea412008e
Make ARM and Mips use TargetMachine::getTLSModel()
...
This moves the logic for selecting a TLS model to a single place,
instead of the previous three (ARM, Mips, and X86 which already
uses this function).
llvm-svn: 156162
2012-05-04 09:40:39 +00:00
e30303fa86
llvm/lib/Target: [PR12611] Add "llvm/Support/raw_ostream.h" for Debug build on MSVC.
...
Thanks to Andy Gibbs, to report the issue.
llvm-svn: 155287
2012-04-21 15:31:45 +00:00
c7242e054d
Convert more uses of XXXRegisterClass to &XXXRegClass. No functional change since they are equivalent.
...
llvm-svn: 155188
2012-04-20 07:30:17 +00:00
47ad674f67
Emit neg.s or neg.d only if -enable-no-nans-fp-math is supplied by user,
...
otherwise expand FNEG during legalization.
llvm-svn: 154546
2012-04-11 22:59:08 +00:00
7f4c9d1429
Emit abs.s or abs.d only if -enable-no-nans-fp-math is supplied by user.
...
Invalid operation is signaled if the operand of these instructions is NaN.
llvm-svn: 154545
2012-04-11 22:49:04 +00:00
4f5c8421b3
Fix bugs in lowering of FCOPYSIGN nodes.
...
- FCOPYSIGN nodes that have operands of different types were not handled.
- Different code was generated depending on the endianness of the target.
Additionally, code is added that emits INS and EXT instructions, if they are
supported by target (they are R2 instructions).
llvm-svn: 154540
2012-04-11 22:13:04 +00:00
121342fcc2
Reapply 154038 without the failing test.
...
llvm-svn: 154062
2012-04-04 22:16:36 +00:00
4743c6e159
Revert r154038. It was causing make check failures.
...
llvm-svn: 154054
2012-04-04 21:18:58 +00:00
9705c865d9
Fix LowerGlobalAddress to produce instructions with the correct relocation
...
types for N32 ABI. Add new test case and update existing ones.
llvm-svn: 154038
2012-04-04 19:02:38 +00:00
591ecdd7c1
Fix LowerJumpTable to produce instructions with the correct relocation
...
types for N32 ABI. Test case will be updated after the patch that fixes
TargetLowering::getPICJumpTableRelocBase is checked in.
llvm-svn: 154036
2012-04-04 18:31:32 +00:00
b3a2b8c199
Fix LowerConstantPool to produce instructions with the correct relocation
...
types for N32 ABI and update test case.
llvm-svn: 154034
2012-04-04 18:26:12 +00:00
aeff24e424
Fix LowerBlockAddress to produce instructions with the correct relocation
...
types for N32 ABI and update test case.
llvm-svn: 154031
2012-04-04 18:22:53 +00:00
0603ad8c65
Expand FREM.
...
llvm-svn: 153671
2012-03-29 18:43:11 +00:00
8a7633c74e
Pass the llvm IR pointer value and offset to the constructor of
...
MachinePointerInfo when getStore is called to create a node that stores an
argument passed in register to the stack. Without this change, the post RA
scheduler will fail to discover the dependencies between the stores
instructions and the instructions that load from a structure passed by value.
The link to the related discussion is here:
http://lists.cs.uiuc.edu/pipermail/llvmdev/2012-March/048055.html
llvm-svn: 153499
2012-03-27 03:13:56 +00:00
769f69f9b6
Fix bug in LowerConstantPool.
...
llvm-svn: 153498
2012-03-27 02:55:31 +00:00
b25fda95f6
Reorder includes in Target backends to following coding standards. Remove some superfluous forward declarations.
...
llvm-svn: 152997
2012-03-17 18:46:09 +00:00
bef78fc2ee
Convert more static tables of registers used by calling convention to uint16_t to reduce space.
...
llvm-svn: 152538
2012-03-11 07:57:25 +00:00
da00aa80b6
Do not custom lower i64 nodes if i64 is not a legal type. Move lines that set
...
operation action of nodes.
llvm-svn: 152452
2012-03-10 00:03:50 +00:00
b7f78592e2
Lower SETCC nodes during legalization. Previously, it was lowered in DAG combine pass.
...
llvm-svn: 152450
2012-03-09 23:46:03 +00:00
5e152182a4
Invoke setTargetDAGCombine for SELECT.
...
llvm-svn: 152290
2012-03-08 03:26:37 +00:00
7dd7c08419
Swap the operands of a select node if the false (the second) operand is 0.
...
For example, this pattern
(select (setcc lhs, rhs, cc), true, 0)
is transformed to this one:
(select (setcc lhs, rhs, inverse(cc)), 0, true)
This enables MipsDAGToDAGISel::ReplaceUsesWithZeroReg (added in r152280) to
replace 0 with $zero.
llvm-svn: 152285
2012-03-08 02:14:24 +00:00
956dd2261e
Set minimum function alignment to 3 if target is Mips64.
...
llvm-svn: 152282
2012-03-08 01:59:33 +00:00
5350c24509
Changes for migrating to using register mask operands.
...
llvm-svn: 151847
2012-03-01 22:27:29 +00:00
6bbe1f0d10
Fix bugs which were introduced when support for base+index floating point loads
...
and stores was added.
- SelectAddr should return false if Parent is an unaligned f32 load or store.
- Only aligned load and store nodes should be matched to select reg+imm
floating point instructions.
- MIPS does not have support for f64 unaligned load or store instructions.
llvm-svn: 151843
2012-03-01 22:12:30 +00:00
65f9d19c4f
Re-commit r151623 with fix. Only issue special no-return calls if it's a direct call.
...
llvm-svn: 151645
2012-02-28 18:51:51 +00:00
ee7b899343
Revert r151623 "Some ARM implementaions, e.g. A-series, does return stack prediction. ...", it is breaking the Clang build during the Compiler-RT part.
...
llvm-svn: 151630
2012-02-28 15:36:07 +00:00
f54f60f3ce
remove blanks, and some code format
...
llvm-svn: 151625
2012-02-28 07:46:26 +00:00
87c7b09d8d
Some ARM implementaions, e.g. A-series, does return stack prediction. That is,
...
the processor keeps a return addresses stack (RAS) which stores the address
and the instruction execution state of the instruction after a function-call
type branch instruction.
Calling a "noreturn" function with normal call instructions (e.g. bl) can
corrupt RAS and causes 100% return misprediction so LLVM should use a
unconditional branch instead. i.e.
mov lr, pc
b _foo
The "mov lr, pc" is issued in order to get proper backtrace.
rdar://8979299
llvm-svn: 151623
2012-02-28 06:42:03 +00:00
330d901ce3
Add support for floating point base register + offset register addressing mode
...
load and store instructions.
llvm-svn: 151611
2012-02-28 02:55:02 +00:00
b049aef2d1
Add an option to use a virtual register as the global base register instead of
...
reserving a physical register ($gp or $28) for that purpose.
This will completely eliminate loads that restore the value of $gp after every
function call, if the register allocator assigns a callee-saved register, or
eliminate unnecessary loads if it assigns a temporary register.
example:
.cpload $25 // set $gp.
...
.cprestore 16 // store $gp to stack slot 16($sp).
...
jalr $25 // function call. clobbers $gp.
lw $gp, 16($sp) // not emitted if callee-saved reg is chosen.
...
lw $2, 4($gp)
...
jalr $25 // function call.
lw $gp, 16($sp) // not emitted if $gp is not live after this instruction.
...
llvm-svn: 151402
2012-02-24 22:34:47 +00:00
760b134ffa
Make all pointers to TargetRegisterClass const since they are all pointers to static data that should not be modified.
...
llvm-svn: 151134
2012-02-22 05:59:10 +00:00
9f6101191b
remove Emacs-tag form .cpp files in Mips Backend, and fix some typo.
...
llvm-svn: 150805
2012-02-17 08:55:11 +00:00
d608bac682
Do not promote i32 arguments to i64. This was causing unnecessary sign extension
...
instructions to be emitted.
llvm-svn: 150782
2012-02-17 02:20:26 +00:00
Akira Hatanaka