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llvm-project/llvm/lib/Target/RISCV
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Craig Topper ba63cdb8f2 [RISCV] Store SEW in RISCV vector pseudo instructions in log2 form. 
This shrinks the immediate that isel table needs to emit for these
instructions. Hoping this allows me to change OPC_EmitInteger to
use a better variable length encoding for representing negative
numbers. Similar to what was done a few months ago for OPC_CheckInteger.

The alternative encoding uses less bytes for negative numbers, but
increases the number of bytes need to encode 64 which was a very
common number in the RISCV table due to SEW=64. By using Log2 this
becomes 6 and is no longer a problem.
 		2021-05-02 12:09:20 -07:00
..
AsmParser [RISCV] Have assembler check that the temp register is different than dest register for vmsgeu.vx pseudo. 2021-04-23 09:33:29 -07:00
Disassembler [RISCV] Fix shared libs build 2021-02-09 06:14:25 -06:00
MCTargetDesc [RISCV] Add explanatory comment to RISCVOp::OPERAND_AVL. 2021-04-28 09:55:36 -07:00
TargetInfo llvmbuildectomy - replace llvm-build by plain cmake 2020-11-13 10:35:24 +01:00
CMakeLists.txt [RISCV] Merge Utils library into MCTargetDesc 2021-01-14 11:47:30 -08:00
RISCV.h [RISCV] Support clang -fpatchable-function-entry && GNU function attribute 'patchable_function_entry' 2021-03-16 10:02:35 -07:00
RISCV.td [RISCV][NFC] Fix formatting 2021-04-09 14:41:09 +08:00
RISCVAsmPrinter.cpp [RISCV] Support clang -fpatchable-function-entry && GNU function attribute 'patchable_function_entry' 2021-03-16 10:02:35 -07:00
RISCVCallLowering.cpp [GlobalISel] Base implementation for sret demotion. 2021-01-06 10:30:50 +05:30
RISCVCallLowering.h [GlobalISel] Base implementation for sret demotion. 2021-01-06 10:30:50 +05:30
RISCVCallingConv.td
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RISCVCleanupVSETVLI.cpp [RISCV] Optimize more redundant VSETVLIs 2021-04-02 10:04:07 +01:00
RISCVExpandAtomicPseudoInsts.cpp
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RISCVExpandPseudoInsts.cpp [RISCV] Spilling for Zvlsseg registers. 2021-03-19 07:46:16 +08:00
RISCVFrameLowering.cpp [RISCV] Fix StackOffset calculation when using sp to access the fixed stack object in the case of rvv vector objects existed 2021-04-30 11:02:38 +08:00
RISCVFrameLowering.h [RISCV] Fix offset computation for RVV 2021-03-29 17:03:49 +00:00
RISCVISelDAGToDAG.cpp [RISCV] Store SEW in RISCV vector pseudo instructions in log2 form. 2021-05-02 12:09:20 -07:00
RISCVISelDAGToDAG.h [RISCV] Refactor an optimization of addition with immediate 2021-04-20 18:04:25 +08:00
RISCVISelLowering.cpp [RISCV] Store SEW in RISCV vector pseudo instructions in log2 form. 2021-05-02 12:09:20 -07:00
RISCVISelLowering.h [RISCV] [1/2] Add IR intrinsic for Zbe extension 2021-04-25 19:14:34 -07:00
RISCVInstrFormats.td [RISCV] Share RVInstIShift and RVInstIShiftW instruction format classes with the B extension. 2021-04-15 11:08:28 -07:00
RISCVInstrFormatsC.td
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RISCVInstrFormatsV.td [RISCV] Add new vector instructions in v0.10. 2021-02-03 13:28:58 +08:00
RISCVInstrInfo.cpp [RISCV] Fix missing emergency slots for scalable stack offsets 2021-04-20 09:59:41 +01:00
RISCVInstrInfo.h [RISCV] Spilling for Zvlsseg registers. 2021-03-19 07:46:16 +08:00
RISCVInstrInfo.td [RISCV] Optimize addition with immediate 2021-04-26 13:26:17 +08:00
RISCVInstrInfoA.td [RISCV][NFC] Add explicit type i64 to RV64 only patterns. 2021-04-09 09:37:04 +08:00
RISCVInstrInfoB.td [RISCV] [1/2] Add IR intrinsic for Zbe extension 2021-04-25 19:14:34 -07:00
RISCVInstrInfoC.td [RISCV] Rename WriteShift/ReadShift scheduler classes to WriteShiftImm/ReadShiftImm. Move variable shifts from WriteIALU/ReadIALU to new WriteShiftReg/ReadShiftReg. 2021-03-19 20:39:49 -07:00
RISCVInstrInfoD.td [RISCV] Cleanup up the spec version references around fmaxnum/fminnum. 2021-04-21 14:50:29 -07:00
RISCVInstrInfoF.td [RISCV] Cleanup up the spec version references around fmaxnum/fminnum. 2021-04-21 14:50:29 -07:00
RISCVInstrInfoM.td [RISCV] Add custom type legalization to form MULHSU when possible. 2021-04-01 10:15:55 -07:00
RISCVInstrInfoV.td [RISCV] Temporary in vmsge(u).vx pseudo instructions can't be V0. 2021-04-21 14:50:29 -07:00
RISCVInstrInfoVPseudos.td [RISCV] Store SEW in RISCV vector pseudo instructions in log2 form. 2021-05-02 12:09:20 -07:00
RISCVInstrInfoVSDPatterns.td [RISCV] Store SEW in RISCV vector pseudo instructions in log2 form. 2021-05-02 12:09:20 -07:00
RISCVInstrInfoVVLPatterns.td [RISCV] Store SEW in RISCV vector pseudo instructions in log2 form. 2021-05-02 12:09:20 -07:00
RISCVInstrInfoZfh.td [RISCV] Cleanup up the spec version references around fmaxnum/fminnum. 2021-04-21 14:50:29 -07:00
RISCVInstructionSelector.cpp
…
RISCVLegalizerInfo.cpp
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RISCVLegalizerInfo.h
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RISCVMCInstLower.cpp [RISCV] Support clang -fpatchable-function-entry && GNU function attribute 'patchable_function_entry' 2021-03-16 10:02:35 -07:00
RISCVMachineFunctionInfo.h [RISCV] Don't emit save-restore call if function is a interrupt handler 2021-04-16 12:54:47 +08:00
RISCVMergeBaseOffset.cpp [RISCV] Support Zfh half-precision floating-point extension. 2020-12-03 09:16:33 +08:00
RISCVRegisterBankInfo.cpp
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RISCVRegisterBankInfo.h
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RISCVRegisterBanks.td
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RISCVRegisterInfo.cpp [RISCV] Further fixes for RVV stack offset computation 2021-04-21 10:51:07 +01:00
RISCVRegisterInfo.h [RISCV] Improve register allocation around vector masks 2021-02-20 14:47:51 +00:00
RISCVRegisterInfo.td [RISCV] Introduce floating point control and state registers 2021-04-21 12:55:30 +07:00
RISCVSchedRocket.td [RISCV] Add UnsupportedSchedZfh multiclass to reduce duplicate lines from RISCVSchedRocket.td and RISCVSchedSiFive7.td. NFC 2021-03-31 15:06:14 -07:00
RISCVSchedSiFive7.td [RISCV] Add UnsupportedSchedZfh multiclass to reduce duplicate lines from RISCVSchedRocket.td and RISCVSchedSiFive7.td. NFC 2021-03-31 15:06:14 -07:00
RISCVSchedule.td [RISCV] Add UnsupportedSchedZfh multiclass to reduce duplicate lines from RISCVSchedRocket.td and RISCVSchedSiFive7.td. NFC 2021-03-31 15:06:14 -07:00
RISCVScheduleB.td [RISCV] Move scheduling resources for B into a separate file (NFC) 2021-03-29 20:37:22 -05:00
RISCVSubtarget.cpp [RISCV] Move getLMULForFixedLengthVector out of RISCVSubtarget. 2021-04-23 15:06:20 -07:00
RISCVSubtarget.h [RISCV] Move getLMULForFixedLengthVector out of RISCVSubtarget. 2021-04-23 15:06:20 -07:00
RISCVSystemOperands.td [RISCV] Introduce floating point control and state registers 2021-04-21 12:55:30 +07:00
RISCVTargetMachine.cpp [AArch64][GlobalISel] Enable use of the optsize predicate in the selector. 2021-03-02 12:55:51 -08:00
RISCVTargetMachine.h [RISCV] Address clang-tidy warnings in RISCVTargetMachine. NFC. 2020-12-18 21:50:55 +00:00
RISCVTargetObjectFile.cpp ELF: Create unique SHF_GNU_RETAIN sections for llvm.used global objects 2021-02-26 16:38:44 -08:00
RISCVTargetObjectFile.h
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RISCVTargetTransformInfo.cpp [TTI] NFC: Change getIntImmCost[Inst|Intrin] to return InstructionCost 2021-04-23 16:06:36 +01:00
RISCVTargetTransformInfo.h [TTI] NFC: Change getIntImmCost[Inst|Intrin] to return InstructionCost 2021-04-23 16:06:36 +01:00