forked from OSchip/llvm-project
405 lines
17 KiB
LLVM
405 lines
17 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=amdgcn-amd- -mcpu=gfx600 -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX6 %s
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX7 %s
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX10-WGP %s
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -mattr=+cumode -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX10-CU %s
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; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx700 -amdgcn-skip-cache-invalidations -verify-machineinstrs < %s | FileCheck --check-prefixes=SKIP-CACHE-INV %s
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define amdgpu_kernel void @private_volatile_load_0(
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; GFX6-LABEL: private_volatile_load_0:
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; GFX6: ; %bb.0: ; %entry
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; GFX6-NEXT: s_mov_b32 s8, SCRATCH_RSRC_DWORD0
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; GFX6-NEXT: s_mov_b32 s9, SCRATCH_RSRC_DWORD1
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; GFX6-NEXT: s_load_dword s4, s[0:1], 0x9
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; GFX6-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xb
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; GFX6-NEXT: s_mov_b32 s10, -1
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; GFX6-NEXT: s_mov_b32 s11, 0xe8f000
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; GFX6-NEXT: s_add_u32 s8, s8, s3
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; GFX6-NEXT: s_addc_u32 s9, s9, 0
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; GFX6-NEXT: s_waitcnt lgkmcnt(0)
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; GFX6-NEXT: v_mov_b32_e32 v0, s4
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; GFX6-NEXT: buffer_load_dword v0, v0, s[8:11], 0 offen glc
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; GFX6-NEXT: s_waitcnt vmcnt(0)
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; GFX6-NEXT: s_mov_b32 s3, 0xf000
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; GFX6-NEXT: s_mov_b32 s2, -1
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; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
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; GFX6-NEXT: s_endpgm
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;
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; GFX7-LABEL: private_volatile_load_0:
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; GFX7: ; %bb.0: ; %entry
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; GFX7-NEXT: s_mov_b64 s[10:11], s[2:3]
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; GFX7-NEXT: s_mov_b64 s[8:9], s[0:1]
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; GFX7-NEXT: s_load_dword s2, s[4:5], 0x0
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; GFX7-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x2
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; GFX7-NEXT: s_add_u32 s8, s8, s7
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; GFX7-NEXT: s_addc_u32 s9, s9, 0
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; GFX7-NEXT: s_waitcnt lgkmcnt(0)
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; GFX7-NEXT: v_mov_b32_e32 v0, s2
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; GFX7-NEXT: buffer_load_dword v2, v0, s[8:11], 0 offen glc
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; GFX7-NEXT: s_waitcnt vmcnt(0)
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; GFX7-NEXT: v_mov_b32_e32 v0, s0
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; GFX7-NEXT: v_mov_b32_e32 v1, s1
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; GFX7-NEXT: flat_store_dword v[0:1], v2
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; GFX7-NEXT: s_endpgm
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;
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; GFX10-WGP-LABEL: private_volatile_load_0:
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; GFX10-WGP: ; %bb.0: ; %entry
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; GFX10-WGP-NEXT: s_mov_b64 s[10:11], s[2:3]
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; GFX10-WGP-NEXT: s_mov_b64 s[8:9], s[0:1]
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; GFX10-WGP-NEXT: s_clause 0x1
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; GFX10-WGP-NEXT: s_load_dword s2, s[4:5], 0x0
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; GFX10-WGP-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x8
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; GFX10-WGP-NEXT: s_add_u32 s8, s8, s7
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; GFX10-WGP-NEXT: s_addc_u32 s9, s9, 0
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; GFX10-WGP-NEXT: v_mov_b32_e32 v1, 0
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; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
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; GFX10-WGP-NEXT: v_mov_b32_e32 v0, s2
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; GFX10-WGP-NEXT: buffer_load_dword v0, v0, s[8:11], 0 offen glc dlc
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; GFX10-WGP-NEXT: s_waitcnt vmcnt(0)
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; GFX10-WGP-NEXT: global_store_dword v1, v0, s[0:1]
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; GFX10-WGP-NEXT: s_endpgm
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;
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; GFX10-CU-LABEL: private_volatile_load_0:
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; GFX10-CU: ; %bb.0: ; %entry
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; GFX10-CU-NEXT: s_mov_b64 s[10:11], s[2:3]
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; GFX10-CU-NEXT: s_mov_b64 s[8:9], s[0:1]
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; GFX10-CU-NEXT: s_clause 0x1
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; GFX10-CU-NEXT: s_load_dword s2, s[4:5], 0x0
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; GFX10-CU-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x8
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; GFX10-CU-NEXT: s_add_u32 s8, s8, s7
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; GFX10-CU-NEXT: s_addc_u32 s9, s9, 0
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; GFX10-CU-NEXT: v_mov_b32_e32 v1, 0
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; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
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; GFX10-CU-NEXT: v_mov_b32_e32 v0, s2
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; GFX10-CU-NEXT: buffer_load_dword v0, v0, s[8:11], 0 offen glc dlc
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; GFX10-CU-NEXT: s_waitcnt vmcnt(0)
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; GFX10-CU-NEXT: global_store_dword v1, v0, s[0:1]
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; GFX10-CU-NEXT: s_endpgm
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;
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; SKIP-CACHE-INV-LABEL: private_volatile_load_0:
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; SKIP-CACHE-INV: ; %bb.0: ; %entry
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; SKIP-CACHE-INV-NEXT: s_getpc_b64 s[8:9]
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; SKIP-CACHE-INV-NEXT: s_mov_b32 s8, s0
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; SKIP-CACHE-INV-NEXT: s_load_dwordx4 s[8:11], s[8:9], 0x0
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; SKIP-CACHE-INV-NEXT: s_load_dword s4, s[0:1], 0x9
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; SKIP-CACHE-INV-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xb
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; SKIP-CACHE-INV-NEXT: s_mov_b32 s2, -1
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; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
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; SKIP-CACHE-INV-NEXT: s_add_u32 s8, s8, s3
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; SKIP-CACHE-INV-NEXT: s_addc_u32 s9, s9, 0
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; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v0, s4
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; SKIP-CACHE-INV-NEXT: buffer_load_dword v0, v0, s[8:11], 0 offen glc
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; SKIP-CACHE-INV-NEXT: s_waitcnt vmcnt(0)
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; SKIP-CACHE-INV-NEXT: s_mov_b32 s3, 0xf000
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; SKIP-CACHE-INV-NEXT: buffer_store_dword v0, off, s[0:3], 0
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; SKIP-CACHE-INV-NEXT: s_endpgm
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i32 addrspace(5)* %in, i32 addrspace(1)* %out) {
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entry:
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%val = load volatile i32, i32 addrspace(5)* %in, align 4
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store i32 %val, i32 addrspace(1)* %out
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ret void
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}
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define amdgpu_kernel void @private_volatile_load_1(
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; GFX6-LABEL: private_volatile_load_1:
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; GFX6: ; %bb.0: ; %entry
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; GFX6-NEXT: s_mov_b32 s8, SCRATCH_RSRC_DWORD0
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; GFX6-NEXT: s_mov_b32 s9, SCRATCH_RSRC_DWORD1
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; GFX6-NEXT: s_load_dword s4, s[0:1], 0x9
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; GFX6-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xb
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; GFX6-NEXT: s_mov_b32 s10, -1
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; GFX6-NEXT: s_mov_b32 s11, 0xe8f000
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; GFX6-NEXT: s_add_u32 s8, s8, s3
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; GFX6-NEXT: v_lshlrev_b32_e32 v0, 2, v0
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; GFX6-NEXT: s_addc_u32 s9, s9, 0
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; GFX6-NEXT: s_waitcnt lgkmcnt(0)
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; GFX6-NEXT: v_add_i32_e32 v0, vcc, s4, v0
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; GFX6-NEXT: buffer_load_dword v0, v0, s[8:11], 0 offen glc
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; GFX6-NEXT: s_waitcnt vmcnt(0)
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; GFX6-NEXT: s_mov_b32 s3, 0xf000
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; GFX6-NEXT: s_mov_b32 s2, -1
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; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
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; GFX6-NEXT: s_endpgm
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;
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; GFX7-LABEL: private_volatile_load_1:
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; GFX7: ; %bb.0: ; %entry
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; GFX7-NEXT: s_mov_b64 s[10:11], s[2:3]
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; GFX7-NEXT: s_mov_b64 s[8:9], s[0:1]
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; GFX7-NEXT: s_load_dword s2, s[4:5], 0x0
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; GFX7-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x2
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; GFX7-NEXT: s_add_u32 s8, s8, s7
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; GFX7-NEXT: v_lshlrev_b32_e32 v0, 2, v0
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; GFX7-NEXT: s_addc_u32 s9, s9, 0
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; GFX7-NEXT: s_waitcnt lgkmcnt(0)
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; GFX7-NEXT: v_add_i32_e32 v0, vcc, s2, v0
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; GFX7-NEXT: buffer_load_dword v2, v0, s[8:11], 0 offen glc
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; GFX7-NEXT: s_waitcnt vmcnt(0)
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; GFX7-NEXT: v_mov_b32_e32 v0, s0
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; GFX7-NEXT: v_mov_b32_e32 v1, s1
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; GFX7-NEXT: flat_store_dword v[0:1], v2
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; GFX7-NEXT: s_endpgm
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;
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; GFX10-WGP-LABEL: private_volatile_load_1:
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; GFX10-WGP: ; %bb.0: ; %entry
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; GFX10-WGP-NEXT: s_mov_b64 s[10:11], s[2:3]
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; GFX10-WGP-NEXT: s_mov_b64 s[8:9], s[0:1]
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; GFX10-WGP-NEXT: s_clause 0x1
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; GFX10-WGP-NEXT: s_load_dword s2, s[4:5], 0x0
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; GFX10-WGP-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x8
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; GFX10-WGP-NEXT: s_add_u32 s8, s8, s7
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; GFX10-WGP-NEXT: s_addc_u32 s9, s9, 0
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; GFX10-WGP-NEXT: v_mov_b32_e32 v1, 0
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; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
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; GFX10-WGP-NEXT: v_lshl_add_u32 v0, v0, 2, s2
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; GFX10-WGP-NEXT: buffer_load_dword v0, v0, s[8:11], 0 offen glc dlc
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; GFX10-WGP-NEXT: s_waitcnt vmcnt(0)
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; GFX10-WGP-NEXT: global_store_dword v1, v0, s[0:1]
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; GFX10-WGP-NEXT: s_endpgm
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;
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; GFX10-CU-LABEL: private_volatile_load_1:
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; GFX10-CU: ; %bb.0: ; %entry
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; GFX10-CU-NEXT: s_mov_b64 s[10:11], s[2:3]
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; GFX10-CU-NEXT: s_mov_b64 s[8:9], s[0:1]
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; GFX10-CU-NEXT: s_clause 0x1
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; GFX10-CU-NEXT: s_load_dword s2, s[4:5], 0x0
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; GFX10-CU-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x8
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; GFX10-CU-NEXT: s_add_u32 s8, s8, s7
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; GFX10-CU-NEXT: s_addc_u32 s9, s9, 0
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; GFX10-CU-NEXT: v_mov_b32_e32 v1, 0
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; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
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; GFX10-CU-NEXT: v_lshl_add_u32 v0, v0, 2, s2
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; GFX10-CU-NEXT: buffer_load_dword v0, v0, s[8:11], 0 offen glc dlc
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; GFX10-CU-NEXT: s_waitcnt vmcnt(0)
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; GFX10-CU-NEXT: global_store_dword v1, v0, s[0:1]
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; GFX10-CU-NEXT: s_endpgm
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;
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; SKIP-CACHE-INV-LABEL: private_volatile_load_1:
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; SKIP-CACHE-INV: ; %bb.0: ; %entry
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; SKIP-CACHE-INV-NEXT: s_getpc_b64 s[8:9]
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; SKIP-CACHE-INV-NEXT: s_mov_b32 s8, s0
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; SKIP-CACHE-INV-NEXT: s_load_dwordx4 s[8:11], s[8:9], 0x0
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; SKIP-CACHE-INV-NEXT: s_load_dword s4, s[0:1], 0x9
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; SKIP-CACHE-INV-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xb
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; SKIP-CACHE-INV-NEXT: v_lshlrev_b32_e32 v0, 2, v0
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; SKIP-CACHE-INV-NEXT: s_mov_b32 s2, -1
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; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
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; SKIP-CACHE-INV-NEXT: s_add_u32 s8, s8, s3
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; SKIP-CACHE-INV-NEXT: s_addc_u32 s9, s9, 0
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; SKIP-CACHE-INV-NEXT: v_add_i32_e32 v0, vcc, s4, v0
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; SKIP-CACHE-INV-NEXT: buffer_load_dword v0, v0, s[8:11], 0 offen glc
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; SKIP-CACHE-INV-NEXT: s_waitcnt vmcnt(0)
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; SKIP-CACHE-INV-NEXT: s_mov_b32 s3, 0xf000
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; SKIP-CACHE-INV-NEXT: buffer_store_dword v0, off, s[0:3], 0
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; SKIP-CACHE-INV-NEXT: s_endpgm
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i32 addrspace(5)* %in, i32 addrspace(1)* %out) {
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entry:
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%val.gep = getelementptr inbounds i32, i32 addrspace(5)* %in, i32 %tid
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%val = load volatile i32, i32 addrspace(5)* %val.gep, align 4
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store i32 %val, i32 addrspace(1)* %out
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ret void
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}
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define amdgpu_kernel void @private_volatile_store_0(
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; GFX6-LABEL: private_volatile_store_0:
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; GFX6: ; %bb.0: ; %entry
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; GFX6-NEXT: s_mov_b32 s4, SCRATCH_RSRC_DWORD0
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; GFX6-NEXT: s_mov_b32 s5, SCRATCH_RSRC_DWORD1
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; GFX6-NEXT: s_mov_b32 s6, -1
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; GFX6-NEXT: s_mov_b32 s7, 0xe8f000
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; GFX6-NEXT: s_add_u32 s4, s4, s3
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; GFX6-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x9
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; GFX6-NEXT: s_load_dword s0, s[0:1], 0xb
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; GFX6-NEXT: s_addc_u32 s5, s5, 0
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; GFX6-NEXT: s_waitcnt lgkmcnt(0)
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; GFX6-NEXT: s_load_dword s1, s[2:3], 0x0
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; GFX6-NEXT: v_mov_b32_e32 v1, s0
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; GFX6-NEXT: s_waitcnt lgkmcnt(0)
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; GFX6-NEXT: v_mov_b32_e32 v0, s1
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; GFX6-NEXT: buffer_store_dword v0, v1, s[4:7], 0 offen
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; GFX6-NEXT: s_waitcnt vmcnt(0)
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; GFX6-NEXT: s_endpgm
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;
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; GFX7-LABEL: private_volatile_store_0:
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; GFX7: ; %bb.0: ; %entry
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; GFX7-NEXT: s_mov_b64 s[10:11], s[2:3]
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; GFX7-NEXT: s_mov_b64 s[8:9], s[0:1]
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; GFX7-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
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; GFX7-NEXT: s_load_dword s2, s[4:5], 0x2
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; GFX7-NEXT: s_add_u32 s8, s8, s7
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; GFX7-NEXT: s_addc_u32 s9, s9, 0
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; GFX7-NEXT: s_waitcnt lgkmcnt(0)
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; GFX7-NEXT: s_load_dword s0, s[0:1], 0x0
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; GFX7-NEXT: v_mov_b32_e32 v1, s2
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; GFX7-NEXT: s_waitcnt lgkmcnt(0)
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; GFX7-NEXT: v_mov_b32_e32 v0, s0
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; GFX7-NEXT: buffer_store_dword v0, v1, s[8:11], 0 offen
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; GFX7-NEXT: s_waitcnt vmcnt(0)
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; GFX7-NEXT: s_endpgm
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;
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; GFX10-WGP-LABEL: private_volatile_store_0:
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; GFX10-WGP: ; %bb.0: ; %entry
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; GFX10-WGP-NEXT: s_mov_b64 s[10:11], s[2:3]
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; GFX10-WGP-NEXT: s_mov_b64 s[8:9], s[0:1]
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; GFX10-WGP-NEXT: s_clause 0x1
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; GFX10-WGP-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
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; GFX10-WGP-NEXT: s_load_dword s2, s[4:5], 0x8
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; GFX10-WGP-NEXT: s_add_u32 s8, s8, s7
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; GFX10-WGP-NEXT: s_addc_u32 s9, s9, 0
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; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
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; GFX10-WGP-NEXT: s_load_dword s0, s[0:1], 0x0
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; GFX10-WGP-NEXT: v_mov_b32_e32 v1, s2
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; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
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; GFX10-WGP-NEXT: v_mov_b32_e32 v0, s0
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; GFX10-WGP-NEXT: buffer_store_dword v0, v1, s[8:11], 0 offen
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; GFX10-WGP-NEXT: s_waitcnt_vscnt null, 0x0
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; GFX10-WGP-NEXT: s_endpgm
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;
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; GFX10-CU-LABEL: private_volatile_store_0:
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; GFX10-CU: ; %bb.0: ; %entry
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; GFX10-CU-NEXT: s_mov_b64 s[10:11], s[2:3]
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; GFX10-CU-NEXT: s_mov_b64 s[8:9], s[0:1]
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; GFX10-CU-NEXT: s_clause 0x1
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; GFX10-CU-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
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; GFX10-CU-NEXT: s_load_dword s2, s[4:5], 0x8
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; GFX10-CU-NEXT: s_add_u32 s8, s8, s7
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; GFX10-CU-NEXT: s_addc_u32 s9, s9, 0
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; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
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; GFX10-CU-NEXT: s_load_dword s0, s[0:1], 0x0
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; GFX10-CU-NEXT: v_mov_b32_e32 v1, s2
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; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
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; GFX10-CU-NEXT: v_mov_b32_e32 v0, s0
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; GFX10-CU-NEXT: buffer_store_dword v0, v1, s[8:11], 0 offen
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; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0
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; GFX10-CU-NEXT: s_endpgm
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;
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; SKIP-CACHE-INV-LABEL: private_volatile_store_0:
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; SKIP-CACHE-INV: ; %bb.0: ; %entry
|
|
; SKIP-CACHE-INV-NEXT: s_getpc_b64 s[4:5]
|
|
; SKIP-CACHE-INV-NEXT: s_mov_b32 s4, s0
|
|
; SKIP-CACHE-INV-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x0
|
|
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
|
|
; SKIP-CACHE-INV-NEXT: s_add_u32 s4, s4, s3
|
|
; SKIP-CACHE-INV-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x9
|
|
; SKIP-CACHE-INV-NEXT: s_load_dword s0, s[0:1], 0xb
|
|
; SKIP-CACHE-INV-NEXT: s_addc_u32 s5, s5, 0
|
|
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
|
|
; SKIP-CACHE-INV-NEXT: s_load_dword s1, s[2:3], 0x0
|
|
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v1, s0
|
|
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
|
|
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v0, s1
|
|
; SKIP-CACHE-INV-NEXT: buffer_store_dword v0, v1, s[4:7], 0 offen
|
|
; SKIP-CACHE-INV-NEXT: s_waitcnt vmcnt(0)
|
|
; SKIP-CACHE-INV-NEXT: s_endpgm
|
|
i32 addrspace(1)* %in, i32 addrspace(5)* %out) {
|
|
entry:
|
|
%val = load i32, i32 addrspace(1)* %in, align 4
|
|
store volatile i32 %val, i32 addrspace(5)* %out
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_kernel void @private_volatile_store_1(
|
|
; GFX6-LABEL: private_volatile_store_1:
|
|
; GFX6: ; %bb.0: ; %entry
|
|
; GFX6-NEXT: s_mov_b32 s4, SCRATCH_RSRC_DWORD0
|
|
; GFX6-NEXT: s_mov_b32 s5, SCRATCH_RSRC_DWORD1
|
|
; GFX6-NEXT: s_mov_b32 s6, -1
|
|
; GFX6-NEXT: s_mov_b32 s7, 0xe8f000
|
|
; GFX6-NEXT: s_add_u32 s4, s4, s3
|
|
; GFX6-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x9
|
|
; GFX6-NEXT: s_load_dword s0, s[0:1], 0xb
|
|
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX6-NEXT: s_addc_u32 s5, s5, 0
|
|
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX6-NEXT: s_load_dword s1, s[2:3], 0x0
|
|
; GFX6-NEXT: v_add_i32_e32 v0, vcc, s0, v0
|
|
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX6-NEXT: v_mov_b32_e32 v1, s1
|
|
; GFX6-NEXT: buffer_store_dword v1, v0, s[4:7], 0 offen
|
|
; GFX6-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX6-NEXT: s_endpgm
|
|
;
|
|
; GFX7-LABEL: private_volatile_store_1:
|
|
; GFX7: ; %bb.0: ; %entry
|
|
; GFX7-NEXT: s_mov_b64 s[10:11], s[2:3]
|
|
; GFX7-NEXT: s_mov_b64 s[8:9], s[0:1]
|
|
; GFX7-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
|
|
; GFX7-NEXT: s_load_dword s2, s[4:5], 0x2
|
|
; GFX7-NEXT: s_add_u32 s8, s8, s7
|
|
; GFX7-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX7-NEXT: s_addc_u32 s9, s9, 0
|
|
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX7-NEXT: s_load_dword s0, s[0:1], 0x0
|
|
; GFX7-NEXT: v_add_i32_e32 v0, vcc, s2, v0
|
|
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX7-NEXT: v_mov_b32_e32 v1, s0
|
|
; GFX7-NEXT: buffer_store_dword v1, v0, s[8:11], 0 offen
|
|
; GFX7-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX7-NEXT: s_endpgm
|
|
;
|
|
; GFX10-WGP-LABEL: private_volatile_store_1:
|
|
; GFX10-WGP: ; %bb.0: ; %entry
|
|
; GFX10-WGP-NEXT: s_mov_b64 s[10:11], s[2:3]
|
|
; GFX10-WGP-NEXT: s_mov_b64 s[8:9], s[0:1]
|
|
; GFX10-WGP-NEXT: s_clause 0x1
|
|
; GFX10-WGP-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
|
|
; GFX10-WGP-NEXT: s_load_dword s2, s[4:5], 0x8
|
|
; GFX10-WGP-NEXT: s_add_u32 s8, s8, s7
|
|
; GFX10-WGP-NEXT: s_addc_u32 s9, s9, 0
|
|
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX10-WGP-NEXT: s_load_dword s0, s[0:1], 0x0
|
|
; GFX10-WGP-NEXT: v_lshl_add_u32 v0, v0, 2, s2
|
|
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX10-WGP-NEXT: v_mov_b32_e32 v1, s0
|
|
; GFX10-WGP-NEXT: buffer_store_dword v1, v0, s[8:11], 0 offen
|
|
; GFX10-WGP-NEXT: s_waitcnt_vscnt null, 0x0
|
|
; GFX10-WGP-NEXT: s_endpgm
|
|
;
|
|
; GFX10-CU-LABEL: private_volatile_store_1:
|
|
; GFX10-CU: ; %bb.0: ; %entry
|
|
; GFX10-CU-NEXT: s_mov_b64 s[10:11], s[2:3]
|
|
; GFX10-CU-NEXT: s_mov_b64 s[8:9], s[0:1]
|
|
; GFX10-CU-NEXT: s_clause 0x1
|
|
; GFX10-CU-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
|
|
; GFX10-CU-NEXT: s_load_dword s2, s[4:5], 0x8
|
|
; GFX10-CU-NEXT: s_add_u32 s8, s8, s7
|
|
; GFX10-CU-NEXT: s_addc_u32 s9, s9, 0
|
|
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX10-CU-NEXT: s_load_dword s0, s[0:1], 0x0
|
|
; GFX10-CU-NEXT: v_lshl_add_u32 v0, v0, 2, s2
|
|
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX10-CU-NEXT: v_mov_b32_e32 v1, s0
|
|
; GFX10-CU-NEXT: buffer_store_dword v1, v0, s[8:11], 0 offen
|
|
; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0
|
|
; GFX10-CU-NEXT: s_endpgm
|
|
;
|
|
; SKIP-CACHE-INV-LABEL: private_volatile_store_1:
|
|
; SKIP-CACHE-INV: ; %bb.0: ; %entry
|
|
; SKIP-CACHE-INV-NEXT: s_getpc_b64 s[4:5]
|
|
; SKIP-CACHE-INV-NEXT: s_mov_b32 s4, s0
|
|
; SKIP-CACHE-INV-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x0
|
|
; SKIP-CACHE-INV-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
|
|
; SKIP-CACHE-INV-NEXT: s_add_u32 s4, s4, s3
|
|
; SKIP-CACHE-INV-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x9
|
|
; SKIP-CACHE-INV-NEXT: s_load_dword s0, s[0:1], 0xb
|
|
; SKIP-CACHE-INV-NEXT: s_addc_u32 s5, s5, 0
|
|
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
|
|
; SKIP-CACHE-INV-NEXT: s_load_dword s1, s[2:3], 0x0
|
|
; SKIP-CACHE-INV-NEXT: v_add_i32_e32 v0, vcc, s0, v0
|
|
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
|
|
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v1, s1
|
|
; SKIP-CACHE-INV-NEXT: buffer_store_dword v1, v0, s[4:7], 0 offen
|
|
; SKIP-CACHE-INV-NEXT: s_waitcnt vmcnt(0)
|
|
; SKIP-CACHE-INV-NEXT: s_endpgm
|
|
i32 addrspace(1)* %in, i32 addrspace(5)* %out) {
|
|
entry:
|
|
%tid = call i32 @llvm.amdgcn.workitem.id.x()
|
|
%val = load i32, i32 addrspace(1)* %in, align 4
|
|
%out.gep = getelementptr inbounds i32, i32 addrspace(5)* %out, i32 %tid
|
|
store volatile i32 %val, i32 addrspace(5)* %out.gep
|
|
ret void
|
|
}
|
|
|
|
declare i32 @llvm.amdgcn.workitem.id.x()
|