forked from OSchip/llvm-project
83 lines
2.7 KiB
LLVM
83 lines
2.7 KiB
LLVM
; Test the MSA fixed-point to floating point conversion intrinsics that are
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; encoded with the 2RF instruction format.
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; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
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; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
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@llvm_mips_ffql_w_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
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@llvm_mips_ffql_w_RES = global <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, align 16
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define void @llvm_mips_ffql_w_test() nounwind {
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entry:
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%0 = load <8 x i16>, <8 x i16>* @llvm_mips_ffql_w_ARG1
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%1 = tail call <4 x float> @llvm.mips.ffql.w(<8 x i16> %0)
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store <4 x float> %1, <4 x float>* @llvm_mips_ffql_w_RES
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ret void
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}
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declare <4 x float> @llvm.mips.ffql.w(<8 x i16>) nounwind
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; CHECK: llvm_mips_ffql_w_test:
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; CHECK: ld.h
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; CHECK: ffql.w
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; CHECK: st.w
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; CHECK: .size llvm_mips_ffql_w_test
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;
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@llvm_mips_ffql_d_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
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@llvm_mips_ffql_d_RES = global <2 x double> <double 0.000000e+00, double 0.000000e+00>, align 16
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define void @llvm_mips_ffql_d_test() nounwind {
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entry:
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%0 = load <4 x i32>, <4 x i32>* @llvm_mips_ffql_d_ARG1
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%1 = tail call <2 x double> @llvm.mips.ffql.d(<4 x i32> %0)
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store <2 x double> %1, <2 x double>* @llvm_mips_ffql_d_RES
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ret void
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}
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declare <2 x double> @llvm.mips.ffql.d(<4 x i32>) nounwind
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; CHECK: llvm_mips_ffql_d_test:
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; CHECK: ld.w
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; CHECK: ffql.d
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; CHECK: st.d
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; CHECK: .size llvm_mips_ffql_d_test
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;
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@llvm_mips_ffqr_w_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
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@llvm_mips_ffqr_w_RES = global <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, align 16
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define void @llvm_mips_ffqr_w_test() nounwind {
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entry:
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%0 = load <8 x i16>, <8 x i16>* @llvm_mips_ffqr_w_ARG1
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%1 = tail call <4 x float> @llvm.mips.ffqr.w(<8 x i16> %0)
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store <4 x float> %1, <4 x float>* @llvm_mips_ffqr_w_RES
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ret void
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}
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declare <4 x float> @llvm.mips.ffqr.w(<8 x i16>) nounwind
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; CHECK: llvm_mips_ffqr_w_test:
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; CHECK: ld.h
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; CHECK: ffqr.w
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; CHECK: st.w
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; CHECK: .size llvm_mips_ffqr_w_test
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;
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@llvm_mips_ffqr_d_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
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@llvm_mips_ffqr_d_RES = global <2 x double> <double 0.000000e+00, double 0.000000e+00>, align 16
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define void @llvm_mips_ffqr_d_test() nounwind {
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entry:
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%0 = load <4 x i32>, <4 x i32>* @llvm_mips_ffqr_d_ARG1
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%1 = tail call <2 x double> @llvm.mips.ffqr.d(<4 x i32> %0)
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store <2 x double> %1, <2 x double>* @llvm_mips_ffqr_d_RES
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ret void
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}
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declare <2 x double> @llvm.mips.ffqr.d(<4 x i32>) nounwind
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; CHECK: llvm_mips_ffqr_d_test:
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; CHECK: ld.w
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; CHECK: ffqr.d
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; CHECK: st.d
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; CHECK: .size llvm_mips_ffqr_d_test
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;
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