Elena Demikhovsky 0ccdd1315b I optimized the following patterns: ... sext <4 x i1> to <4 x i64> sext <4 x i8> to <4 x i64> sext <4 x i16> to <4 x i64> I'm running Combine on SIGN_EXTEND_IN_REG and revert SEXT patterns: (sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) -> (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT))) The sext_in_reg (v4i32 x) may be lowered to shl+sar operations. The "sar" does not exist on 64-bit operation, so lowering sext_in_reg (v4i64 x) has no vector solution. I also added a cost of this operations to the AVX costs table. llvm-svn: 175619		2013-02-20 12:42:54 +00:00
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ARM	ARM cost model: Add vector reverse shuffle costs	2013-02-12 02:40:39 +00:00
PowerPC	Refine fix to bug 15041.	2013-02-08 18:19:17 +00:00
X86	I optimized the following patterns:	2013-02-20 12:42:54 +00:00
lit.local.cfg	…
no_info.ll	Make opt grab the triple from the module and use it to initialize the target machine.	2013-01-01 08:00:32 +00:00