add ahb2apb.v
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yunlongLi
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//==========================================================
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//--Author : colonel
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//--Date : 11-13
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//--Module : ahb_to_apb
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//--Function: convert ahb to apb
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//--Ref: https://ee.ac.cn/index.php/archives/600.html
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//==========================================================
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`timescale 1ns / 1ps
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module ahb_to_apb #(
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// Parameter to define address width
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// 16 = 2^16 = 64KB APB address space
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parameter ADDRWIDTH = 16,
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parameter REGISTER_RDATA = 1,
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parameter REGISTER_WDATA = 0
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)
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(
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//----------------------------------
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// IO Declarations
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//----------------------------------
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input wire HCLK, // Clock
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input wire HRESETn, // Reset
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input wire PCLKEN, // APB clock enable signal
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input wire HSEL, // Device select
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input wire [ADDRWIDTH-1:0] HADDR, // Address
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input wire [1:0] HTRANS, // Transfer control
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input wire [2:0] HSIZE, // Transfer size
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input wire [3:0] HPROT, // Protection control
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input wire HWRITE, // Write control
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input wire HREADY, // Transfer phase done
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input wire [31:0] HWDATA, // Write data
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output reg HREADYOUT, // Device ready
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output wire [31:0] HRDATA, // Read data output
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output wire HRESP, // Device response
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// APB Output
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output wire [ADDRWIDTH-1:0] PADDR, // APB Address
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output wire PENABLE, // APB Enable
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output wire PWRITE, // APB Write
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output wire [3:0] PSTRB, // APB Byte Strobe
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output wire [2:0] PPROT, // APB Prot
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output wire [31:0] PWDATA, // APB write data
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output wire PSEL, // APB Select
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output wire APBACTIVE, // APB bus is active, for clock gating of APB bus
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// APB Input
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input wire [31:0] PRDATA, // Read data for each APB slave
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input wire PREADY, // Ready for each APB slave
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input wire PSLVERR // Error state for each APB slave
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);
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//----------------------------------
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// Variable Declarations
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//----------------------------------
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reg [ADDRWIDTH-3:0] addr_reg; // Address sample register
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reg wr_reg; // Write control sample register
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reg [2:0] state_reg; // State for finite state machine
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reg [3:0] pstrb_reg; // Byte lane strobe register
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wire [3:0] pstrb_nxt; // Byte lane strobe next state
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reg [1:0] pprot_reg; // PPROT register
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wire [1:0] pprot_nxt; // PPROT register next state
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wire apb_select; // APB bridge is selected
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wire apb_tran_end; // Transfer is completed on APB
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reg [2:0] next_state; // Next state for finite state machine
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reg [31:0] rwdata_reg; // Read/Write data sample register
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wire reg_rdata_cfg; // REGISTER_RDATA paramater
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wire reg_wdata_cfg; // REGISTER_WDATA paramater
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reg sample_wdata_reg; // Control signal to sample HWDATA
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//----------------------------------
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// Local Parameter Declarations
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//----------------------------------
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// State machine
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localparam ST_BITS = 3;
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localparam [ST_BITS-1:0] ST_IDLE = 3'b000; // Idle waiting for transaction
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localparam [ST_BITS-1:0] ST_APB_WAIT = 3'b001; // Wait APB transfer
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localparam [ST_BITS-1:0] ST_APB_TRNF = 3'b010; // Start APB transfer
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localparam [ST_BITS-1:0] ST_APB_TRNF2 = 3'b011; // Second APB transfer cycle
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localparam [ST_BITS-1:0] ST_APB_ENDOK = 3'b100; // Ending cycle for OKAY
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localparam [ST_BITS-1:0] ST_APB_ERR1 = 3'b101; // First cycle for Error response
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localparam [ST_BITS-1:0] ST_APB_ERR2 = 3'b110; // Second cycle for Error response
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localparam [ST_BITS-1:0] ST_ILLEGAL = 3'b111; // Illegal state
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//----------------------------------
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// Start of Main Code
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//----------------------------------
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// Configuration signal
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assign reg_rdata_cfg = (REGISTER_RDATA == 0) ? 1'b0 : 1'b1;
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assign reg_wdata_cfg = (REGISTER_WDATA == 0) ? 1'b0 : 1'b1;
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// Generate APB bridge select
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assign apb_select = HSEL & HTRANS[1] & HREADY;
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// Generate APB transfer ended
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assign apb_tran_end = (state_reg == 3'b011) & PREADY;
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assign pprot_nxt[0] = HPROT[1]; // (0) Normal, (1) Privileged
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assign pprot_nxt[1] = ~HPROT[0]; // (0) Data, (1) Instruction
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// Byte strobe generation
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// - Only enable for write operations
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// - For word write transfers (HSIZE[1]=1), all byte strobes are 1
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// - For hword write transfers (HSIZE[0]=1), check HADDR[1]
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// - For byte write transfers, check HADDR[1:0]
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assign pstrb_nxt[0] = HWRITE & ((HSIZE[1])|((HSIZE[0])&(~HADDR[1]))|(HADDR[1:0]==2'b00));
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assign pstrb_nxt[1] = HWRITE & ((HSIZE[1])|((HSIZE[0])&(~HADDR[1]))|(HADDR[1:0]==2'b01));
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assign pstrb_nxt[2] = HWRITE & ((HSIZE[1])|((HSIZE[0])&( HADDR[1]))|(HADDR[1:0]==2'b10));
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assign pstrb_nxt[3] = HWRITE & ((HSIZE[1])|((HSIZE[0])&( HADDR[1]))|(HADDR[1:0]==2'b11));
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// Sample control signals
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always @(posedge HCLK or negedge HRESETn)
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begin
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if (~HRESETn) begin
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addr_reg <= {(ADDRWIDTH-2){1'b0}};
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wr_reg <= 1'b0;
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pprot_reg <= {2{1'b0}};
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pstrb_reg <= {4{1'b0}};
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end
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else if (apb_select) begin // Capture transfer information at the end of AHB address phase
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addr_reg <= HADDR[ADDRWIDTH-1:2];
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wr_reg <= HWRITE;
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pprot_reg <= pprot_nxt;
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pstrb_reg <= pstrb_nxt;
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end
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end
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// Sample write data control signal
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// Assert after write address phase, deassert after PCLKEN=1
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wire sample_wdata_set = apb_select & HWRITE & reg_wdata_cfg;
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wire sample_wdata_clr = sample_wdata_reg & PCLKEN;
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always @(posedge HCLK or negedge HRESETn)
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begin
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if (~HRESETn)
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sample_wdata_reg <= 1'b0;
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else if (sample_wdata_set | sample_wdata_clr)
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sample_wdata_reg <= sample_wdata_set;
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end
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// Generate next state for FSM
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// Note : case 3'b111 is not used. The design has been checked that
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// this illegal state cannot be entered using formal verification.
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always @(state_reg or PREADY or PSLVERR or apb_select or reg_rdata_cfg or
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PCLKEN or reg_wdata_cfg or HWRITE)
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begin
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case (state_reg)
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// Idle
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ST_IDLE : begin
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if (PCLKEN & apb_select & ~(reg_wdata_cfg & HWRITE))
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next_state = ST_APB_TRNF; // Start APB transfer in next cycle
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else if (apb_select)
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next_state = ST_APB_WAIT; // Wait for start of APB transfer at PCLKEN high
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else
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next_state = ST_IDLE; // Remain idle
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end
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// Transfer announced on AHB, but PCLKEN was low, so waiting
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ST_APB_WAIT : begin
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if (PCLKEN)
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next_state = ST_APB_TRNF; // Start APB transfer in next cycle
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else
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next_state = ST_APB_WAIT; // Wait for start of APB transfer at PCLKEN high
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end
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// First APB transfer cycle
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ST_APB_TRNF : begin
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if (PCLKEN)
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next_state = ST_APB_TRNF2; // Change to second cycle of APB transfer
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else
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next_state = ST_APB_TRNF; // Change to state-2
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end
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// Second APB transfer cycle
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ST_APB_TRNF2 : begin
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if (PREADY & PSLVERR & PCLKEN) // Error received - Generate two cycle
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// Error response on AHB by
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next_state = ST_APB_ERR1; // Changing to state-5 and 6
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else if (PREADY & (~PSLVERR) & PCLKEN) begin // Okay received
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if (reg_rdata_cfg)
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// Registered version
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next_state = ST_APB_ENDOK; // Generate okay response in state 4
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else
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// Non-registered version
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next_state = {2'b00, apb_select}; // Terminate transfer
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end
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else // Slave not ready
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next_state = ST_APB_TRNF2; // Unchange
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end
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// Ending cycle for OKAY (registered response)
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ST_APB_ENDOK : begin
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if (PCLKEN & apb_select & ~(reg_wdata_cfg & HWRITE))
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next_state = ST_APB_TRNF; // Start APB transfer in next cycle
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else if (apb_select)
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next_state = ST_APB_WAIT; // Wait for start of APB transfer at PCLKEN high
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else
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next_state = ST_IDLE; // Remain idle
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end
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// First cycle for Error response
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ST_APB_ERR1 :
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next_state = ST_APB_ERR2; // Goto 2nd cycle of error response
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// Second cycle for Error response
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ST_APB_ERR2 : begin
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if (PCLKEN & apb_select & ~(reg_wdata_cfg & HWRITE))
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next_state = ST_APB_TRNF; // Start APB transfer in next cycle
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else if (apb_select)
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next_state = ST_APB_WAIT; // Wait for start of APB transfer at PCLKEN high
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else
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next_state = ST_IDLE; // Remain idle
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end
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default : // Not used
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next_state = 3'bxxx; // X-Propagation
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endcase
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end
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// Registering state machine
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always @(posedge HCLK or negedge HRESETn)
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begin
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if (~HRESETn)
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state_reg <= 3'b000;
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else
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state_reg <= next_state;
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end
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// Sample PRDATA or HWDATA
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always @(posedge HCLK or negedge HRESETn)
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begin
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if (~HRESETn)
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rwdata_reg <= {32{1'b0}};
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else
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if (sample_wdata_reg & reg_wdata_cfg & PCLKEN)
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rwdata_reg <= HWDATA;
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else if (apb_tran_end & reg_rdata_cfg & PCLKEN)
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rwdata_reg <= PRDATA;
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end
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// Connect outputs to top level
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assign PADDR = {addr_reg, 2'b00}; // from sample register
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assign PWRITE = wr_reg; // from sample register
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// From sample register or from HWDATA directly
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assign PWDATA = (reg_wdata_cfg) ? rwdata_reg : HWDATA;
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assign PSEL = (state_reg == ST_APB_TRNF) | (state_reg == ST_APB_TRNF2);
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assign PENABLE = (state_reg == ST_APB_TRNF2);
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assign PPROT = {pprot_reg[1], 1'b0, pprot_reg[0]};
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assign PSTRB = pstrb_reg[3:0];
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// Generate HREADYOUT
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always @(state_reg or reg_rdata_cfg or PREADY or PSLVERR or PCLKEN)
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begin
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case (state_reg)
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ST_IDLE : HREADYOUT = 1'b1; // Idle
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ST_APB_WAIT : HREADYOUT = 1'b0; // Transfer announced on AHB, but PCLKEN was low, so waiting
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ST_APB_TRNF : HREADYOUT = 1'b0; // First APB transfer cycle
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// Second APB transfer cycle:
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// if Non-registered feedback version, and APB transfer completed without error
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// Then response with ready immediately. If registered feedback version,
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// wait until state_reg == ST_APB_ENDOK
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ST_APB_TRNF2 : HREADYOUT = (~reg_rdata_cfg) & PREADY & (~PSLVERR) & PCLKEN;
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ST_APB_ENDOK : HREADYOUT = reg_rdata_cfg; // Ending cycle for OKAY (registered response only)
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ST_APB_ERR1 : HREADYOUT = 1'b0; // First cycle for Error response
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ST_APB_ERR2 : HREADYOUT = 1'b1; // Second cycle for Error response
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default : HREADYOUT = 1'bx; // x propagation (note :3'b111 is illegal state)
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endcase
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end
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// From sample register or from PRDATA directly
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assign HRDATA = (reg_rdata_cfg) ? rwdata_reg : PRDATA;
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assign HRESP = (state_reg == ST_APB_ERR1) | (state_reg == ST_APB_ERR2);
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assign APBACTIVE = (HSEL & HTRANS[1]) | (|state_reg);
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endmodule
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