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yunlongLi 2024-10-31 00:00:52 +08:00
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README.md
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# IC_FPGA_projects
This repository is used to introduce to some projects or modules bases on the mainly lanuage--verilog.
# 1

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common/sync_fifo.v Normal file
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//====================================
//--Author : colonel
//--Date : 10-30
//--Module : sync_fifo
//--Function: the sync clk fifo logic
//====================================