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@[TOC](cfg_noc_bridge详细设计文档)
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# 1 需求分解支持
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需求实现noc req测到AXI测协议bridge；
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需求实现AXI测到APB测转换bridge；；
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需求实现AXI master 1to2 转换；；
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需求实现APB decoder功能；；
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# 2 功能概述
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该设计文档是实现noc总线协议到AMBA总线协议的转换，，用以配置不同Slave的CSR；大致模块框图结构如下图所示：：
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# 2 输入输出接口
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## 2.1 noc2AXI接口
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### 2.1.1 noc测接口：
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Name | I/O | Width | Description
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----------------|-------------|---------------|-----------------
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noc_req_rdy O 1 ready
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noc_req_vld I 1 valid
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noc_req_flit I 64 flit
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----------------------------------------------------------------
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noc_rsp_rdy I 1 ready
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noc_rsp_vld O 1 valid
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noc_rsp_flit O 64 flit
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### 2.1.2 AXI接口
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Name | I/O | Width | Description
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----------------|-------------|---------------|-----------------
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awready
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awvalid
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awaddr
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awlen
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awsize
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awburst
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------------------------------------------------------------------
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wready O 1 ready
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wavlid
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wdata
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wstrb
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wlast
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------------------------------------------------------------------
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bready
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bvalid
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bid
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bresp
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------------------------------------------------------------------
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arready
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arvalid
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araddr
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araid
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arlen
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arsize
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arburst
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------------------------------------------------------------------
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rready
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rvalid
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rid
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rdata
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rresp
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rlast
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------------------------------------------------------------------
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### 2.1.3 接口时序
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相关接口时序图如下图所示:
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## 2.2 AXI2APB接口
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### 2.2.1 AXI接口
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如上节所示
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### 2.2.1 APB接口
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Name | I/O | Width | Description
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----------------|-------------|---------------|-----------------
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psel
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penable
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pwrite
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paddr
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pready
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prdata
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### 2.2.3 AXI2APB接口时序
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相关接口时序图如下图所示：
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1.write接口时序如下：：
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必要描述：：
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2.read接口时序如下：：
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必要描述：：
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# 3 设计详述
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## 3.1 noc2axi_bridge
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### 3.1.1 状态机
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该bridge设计模块的状态机如下图所示：：
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## 3.2 axi2apb_bridge
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该bridge设计模块的状态机如下图所示：：
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## 3.3 axi_1to2
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通过高位地址进行MUX；；
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## 3.4 apb_decoder
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通过高位地址进行MUX；；
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{
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// "signal": [
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// { "name": "ACLK", "wave": "p.|..................", "period": 1 },
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//
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// // AXI写通道
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// ['AW_CH',
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// { "name": "AWVALID", "wave": "0.|.1.0.............." },
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// { "name": "AWREADY", "wave": "0.|..10.............." },
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// { "name": "AWADDR", "wave": "x.|.3.x..............", "data": "awaddr" },
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// {},
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// ],
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// ['W_CH',
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// { "name": "WVALID", "wave": "0..|...1..0.........." },
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// { "name": "WREADY", "wave": "0..|.....10.........." },
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// { "name": "WDATA", "wave": "x..|...3..x..........", "data": "wdata" },
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// {},
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// ],
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// ['B_CH',
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// { "name": "BVALID", "wave": "0.|...........1.0...." },
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// { "name": "BREADY", "wave": "0.|............1.0..." },
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// {},
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// ],
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//
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// // FSM Idication
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// { "name": "STATE", "wave": "=.|...3...33..3.3.xxx", "data": ["IDLE","WAIT_WDATA","SET","ACS","RESP_W","IDLE"] },
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// ['APB',
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// { "name": "PSEL", "wave": "0.|.......1...0......" },
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// { "name": "PENABLE", "wave": "0.|........1..0......" },
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// { "name": "PWRITE", "wave": "0.|.......1...0......" },
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// { "name": "PADDR", "wave": "x.|.......3...x......", "data": ["addr",] },
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// { "name": "PWDATA", "wave": "x.|.......3...x......", "data": ["wdata",] },
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// { "name": "PREADY", "wave": "1.|........0.1......." },
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// { "name": "PRDATA", "wave": "x.|..................", "data": [""] },
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// ],
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//
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// ],
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"signal": [
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{ "name": "ACLK", "wave": "p.|..............", "period": 1 },
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// AXI读通道
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['AW_CH',
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{ "name": "ARVALID", "wave": "0.|..1..0......." },
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{ "name": "ARREADY", "wave": "0.|....10......." },
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{ "name": "ARADDR", "wave": "x.|..3..x.......", "data": "araddr" },
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{},
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],
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['R_CH',
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{ "name": "RVALID", "wave": "0.|.........1.0." },
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{ "name": "RREADY", "wave": "0.|..........10." },
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{ "name": "RDATA", "wave": "x.|.........3.x.", "data": "rdata" },
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{},
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],
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// FSM Idication
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{ "name": "STATE", "wave": "=..|....33..3.=.", "data": ["IDLE","SET","ACS","RESP_R","IDLE"] },
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{},
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['APB',
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{ "name": "PSEL", "wave": "0.|.....1...0..." },
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{ "name": "PENABLE", "wave": "0.|......1..0..." },
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{ "name": "PWRITE", "wave": "0.|.....1...0..." },
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{ "name": "PADDR", "wave": "x.|.....3...x...", "data": ["addr",] },
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{ "name": "PREADY", "wave": "1.|......0.1...." },
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{ "name": "PRDATA", "wave": "x.|........3x...", "data": ["prdata"] },
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{ "name": "PWDATA", "wave": "x.|.........x...", "data": ["wdata",] },
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],
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],
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"head": {
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"text": "AXI4 to APB3 Bridge Timing",
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"tick": 0,
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"every": 1
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},
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// "foot": {
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// "text": "Cycle: 0 1 2 3 4 5 6 7 8 9",
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// "tick": 0
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// }
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}
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